2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_hdr.h"
10 #include "qlcnic_83xx_hw.h"
11 #include "qlcnic_hw.h"
15 #define QLC_83XX_MINIDUMP_FLASH 0x520000
16 #define QLC_83XX_OCM_INDEX 3
17 #define QLC_83XX_PCI_INDEX 0
18 #define QLC_83XX_DMA_ENGINE_INDEX 8
20 static const u32 qlcnic_ms_read_data[] = {
21 0x410000A8, 0x410000AC, 0x410000B8, 0x410000BC
24 #define QLCNIC_DUMP_WCRB BIT_0
25 #define QLCNIC_DUMP_RWCRB BIT_1
26 #define QLCNIC_DUMP_ANDCRB BIT_2
27 #define QLCNIC_DUMP_ORCRB BIT_3
28 #define QLCNIC_DUMP_POLLCRB BIT_4
29 #define QLCNIC_DUMP_RD_SAVE BIT_5
30 #define QLCNIC_DUMP_WRT_SAVED BIT_6
31 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
32 #define QLCNIC_DUMP_SKIP BIT_7
34 #define QLCNIC_DUMP_MASK_MAX 0xff
36 struct qlcnic_pex_dma_descriptor {
42 u32 dma_bus_addr_high;
46 struct qlcnic_common_entry_hdr {
100 u32 read_addr_stride;
172 struct qlcnic_dump_entry {
173 struct qlcnic_common_entry_hdr hdr;
176 struct __cache cache;
182 struct __pollrdmwr pollrdmwr;
184 struct __pollrd pollrd;
188 enum qlcnic_minidump_opcode {
190 QLCNIC_DUMP_READ_CRB = 1,
191 QLCNIC_DUMP_READ_MUX = 2,
192 QLCNIC_DUMP_QUEUE = 3,
193 QLCNIC_DUMP_BRD_CONFIG = 4,
194 QLCNIC_DUMP_READ_OCM = 6,
195 QLCNIC_DUMP_PEG_REG = 7,
196 QLCNIC_DUMP_L1_DTAG = 8,
197 QLCNIC_DUMP_L1_ITAG = 9,
198 QLCNIC_DUMP_L1_DATA = 11,
199 QLCNIC_DUMP_L1_INST = 12,
200 QLCNIC_DUMP_L2_DTAG = 21,
201 QLCNIC_DUMP_L2_ITAG = 22,
202 QLCNIC_DUMP_L2_DATA = 23,
203 QLCNIC_DUMP_L2_INST = 24,
204 QLCNIC_DUMP_POLL_RD = 35,
205 QLCNIC_READ_MUX2 = 36,
206 QLCNIC_READ_POLLRDMWR = 37,
207 QLCNIC_DUMP_READ_ROM = 71,
208 QLCNIC_DUMP_READ_MEM = 72,
209 QLCNIC_DUMP_READ_CTRL = 98,
210 QLCNIC_DUMP_TLHDR = 99,
211 QLCNIC_DUMP_RDEND = 255
214 inline u32 qlcnic_82xx_get_saved_state(void *t_hdr, u32 index)
216 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
218 return hdr->saved_state[index];
221 inline void qlcnic_82xx_set_saved_state(void *t_hdr, u32 index,
224 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
226 hdr->saved_state[index] = value;
229 void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *fw_dump)
231 struct qlcnic_82xx_dump_template_hdr *hdr;
233 hdr = fw_dump->tmpl_hdr;
234 fw_dump->tmpl_hdr_size = hdr->size;
235 fw_dump->version = hdr->version;
236 fw_dump->num_entries = hdr->num_entries;
237 fw_dump->offset = hdr->offset;
239 hdr->drv_cap_mask = hdr->cap_mask;
240 fw_dump->cap_mask = hdr->cap_mask;
242 fw_dump->use_pex_dma = (hdr->capabilities & BIT_0) ? true : false;
245 inline u32 qlcnic_82xx_get_cap_size(void *t_hdr, int index)
247 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
249 return hdr->cap_sizes[index];
252 void qlcnic_82xx_set_sys_info(void *t_hdr, int idx, u32 value)
254 struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
256 hdr->sys_info[idx] = value;
259 void qlcnic_82xx_store_cap_mask(void *tmpl_hdr, u32 mask)
261 struct qlcnic_82xx_dump_template_hdr *hdr = tmpl_hdr;
263 hdr->drv_cap_mask = mask;
266 inline u32 qlcnic_83xx_get_saved_state(void *t_hdr, u32 index)
268 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
270 return hdr->saved_state[index];
273 inline void qlcnic_83xx_set_saved_state(void *t_hdr, u32 index,
276 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
278 hdr->saved_state[index] = value;
281 #define QLCNIC_TEMPLATE_VERSION (0x20001)
283 void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *fw_dump)
285 struct qlcnic_83xx_dump_template_hdr *hdr;
287 hdr = fw_dump->tmpl_hdr;
288 fw_dump->tmpl_hdr_size = hdr->size;
289 fw_dump->version = hdr->version;
290 fw_dump->num_entries = hdr->num_entries;
291 fw_dump->offset = hdr->offset;
293 hdr->drv_cap_mask = hdr->cap_mask;
294 fw_dump->cap_mask = hdr->cap_mask;
296 fw_dump->use_pex_dma = (fw_dump->version & 0xfffff) >=
297 QLCNIC_TEMPLATE_VERSION;
300 inline u32 qlcnic_83xx_get_cap_size(void *t_hdr, int index)
302 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
304 return hdr->cap_sizes[index];
307 void qlcnic_83xx_set_sys_info(void *t_hdr, int idx, u32 value)
309 struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
311 hdr->sys_info[idx] = value;
314 void qlcnic_83xx_store_cap_mask(void *tmpl_hdr, u32 mask)
316 struct qlcnic_83xx_dump_template_hdr *hdr;
319 hdr->drv_cap_mask = mask;
322 struct qlcnic_dump_operations {
323 enum qlcnic_minidump_opcode opcode;
324 u32 (*handler)(struct qlcnic_adapter *, struct qlcnic_dump_entry *,
328 static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter,
329 struct qlcnic_dump_entry *entry, __le32 *buffer)
333 struct __crb *crb = &entry->region.crb;
337 for (i = 0; i < crb->no_ops; i++) {
338 data = qlcnic_ind_rd(adapter, addr);
339 *buffer++ = cpu_to_le32(addr);
340 *buffer++ = cpu_to_le32(data);
343 return crb->no_ops * 2 * sizeof(u32);
346 static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
347 struct qlcnic_dump_entry *entry, __le32 *buffer)
349 void *hdr = adapter->ahw->fw_dump.tmpl_hdr;
350 struct __ctrl *ctr = &entry->region.ctrl;
351 int i, k, timeout = 0;
352 u32 addr, data, temp;
356 no_ops = ctr->no_ops;
358 for (i = 0; i < no_ops; i++) {
360 for (k = 0; k < 8; k++) {
361 if (!(ctr->opcode & (1 << k)))
364 case QLCNIC_DUMP_WCRB:
365 qlcnic_ind_wr(adapter, addr, ctr->val1);
367 case QLCNIC_DUMP_RWCRB:
368 data = qlcnic_ind_rd(adapter, addr);
369 qlcnic_ind_wr(adapter, addr, data);
371 case QLCNIC_DUMP_ANDCRB:
372 data = qlcnic_ind_rd(adapter, addr);
373 qlcnic_ind_wr(adapter, addr,
376 case QLCNIC_DUMP_ORCRB:
377 data = qlcnic_ind_rd(adapter, addr);
378 qlcnic_ind_wr(adapter, addr,
381 case QLCNIC_DUMP_POLLCRB:
382 while (timeout <= ctr->timeout) {
383 data = qlcnic_ind_rd(adapter, addr);
384 if ((data & ctr->val2) == ctr->val1)
386 usleep_range(1000, 2000);
389 if (timeout > ctr->timeout) {
390 dev_info(&adapter->pdev->dev,
391 "Timed out, aborting poll CRB\n");
395 case QLCNIC_DUMP_RD_SAVE:
398 addr = qlcnic_get_saved_state(adapter,
401 data = qlcnic_ind_rd(adapter, addr);
402 qlcnic_set_saved_state(adapter, hdr,
405 case QLCNIC_DUMP_WRT_SAVED:
408 data = qlcnic_get_saved_state(adapter,
416 addr = qlcnic_get_saved_state(adapter,
419 qlcnic_ind_wr(adapter, addr, data);
421 case QLCNIC_DUMP_MOD_SAVE_ST:
422 data = qlcnic_get_saved_state(adapter, hdr,
424 data <<= ctr->shl_val;
425 data >>= ctr->shr_val;
430 qlcnic_set_saved_state(adapter, hdr,
434 dev_info(&adapter->pdev->dev,
444 static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter,
445 struct qlcnic_dump_entry *entry, __le32 *buffer)
449 struct __mux *mux = &entry->region.mux;
452 for (loop = 0; loop < mux->no_ops; loop++) {
453 qlcnic_ind_wr(adapter, mux->addr, val);
454 data = qlcnic_ind_rd(adapter, mux->read_addr);
455 *buffer++ = cpu_to_le32(val);
456 *buffer++ = cpu_to_le32(data);
457 val += mux->val_stride;
459 return 2 * mux->no_ops * sizeof(u32);
462 static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter,
463 struct qlcnic_dump_entry *entry, __le32 *buffer)
466 u32 cnt, addr, data, que_id = 0;
467 struct __queue *que = &entry->region.que;
469 addr = que->read_addr;
470 cnt = que->read_addr_cnt;
472 for (loop = 0; loop < que->no_ops; loop++) {
473 qlcnic_ind_wr(adapter, que->sel_addr, que_id);
474 addr = que->read_addr;
475 for (i = 0; i < cnt; i++) {
476 data = qlcnic_ind_rd(adapter, addr);
477 *buffer++ = cpu_to_le32(data);
478 addr += que->read_addr_stride;
480 que_id += que->stride;
482 return que->no_ops * cnt * sizeof(u32);
485 static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter,
486 struct qlcnic_dump_entry *entry, __le32 *buffer)
491 struct __ocm *ocm = &entry->region.ocm;
493 addr = adapter->ahw->pci_base0 + ocm->read_addr;
494 for (i = 0; i < ocm->no_ops; i++) {
496 *buffer++ = cpu_to_le32(data);
497 addr += ocm->read_addr_stride;
499 return ocm->no_ops * sizeof(u32);
502 static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter,
503 struct qlcnic_dump_entry *entry, __le32 *buffer)
506 u32 fl_addr, size, val, lck_val, addr;
507 struct __mem *rom = &entry->region.mem;
510 size = rom->size / 4;
512 lck_val = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
513 if (!lck_val && count < MAX_CTL_CHECK) {
514 usleep_range(10000, 11000);
518 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
519 adapter->ahw->pci_func);
520 for (i = 0; i < size; i++) {
521 addr = fl_addr & 0xFFFF0000;
522 qlcnic_ind_wr(adapter, FLASH_ROM_WINDOW, addr);
523 addr = LSW(fl_addr) + FLASH_ROM_DATA;
524 val = qlcnic_ind_rd(adapter, addr);
526 *buffer++ = cpu_to_le32(val);
528 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
532 static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
533 struct qlcnic_dump_entry *entry, __le32 *buffer)
536 u32 cnt, val, data, addr;
537 struct __cache *l1 = &entry->region.cache;
539 val = l1->init_tag_val;
541 for (i = 0; i < l1->no_ops; i++) {
542 qlcnic_ind_wr(adapter, l1->addr, val);
543 qlcnic_ind_wr(adapter, l1->ctrl_addr, LSW(l1->ctrl_val));
544 addr = l1->read_addr;
545 cnt = l1->read_addr_num;
547 data = qlcnic_ind_rd(adapter, addr);
548 *buffer++ = cpu_to_le32(data);
549 addr += l1->read_addr_stride;
554 return l1->no_ops * l1->read_addr_num * sizeof(u32);
557 static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
558 struct qlcnic_dump_entry *entry, __le32 *buffer)
561 u32 cnt, val, data, addr;
562 u8 poll_mask, poll_to, time_out = 0;
563 struct __cache *l2 = &entry->region.cache;
565 val = l2->init_tag_val;
566 poll_mask = LSB(MSW(l2->ctrl_val));
567 poll_to = MSB(MSW(l2->ctrl_val));
569 for (i = 0; i < l2->no_ops; i++) {
570 qlcnic_ind_wr(adapter, l2->addr, val);
571 if (LSW(l2->ctrl_val))
572 qlcnic_ind_wr(adapter, l2->ctrl_addr,
577 data = qlcnic_ind_rd(adapter, l2->ctrl_addr);
578 if (!(data & poll_mask))
580 usleep_range(1000, 2000);
582 } while (time_out <= poll_to);
584 if (time_out > poll_to) {
585 dev_err(&adapter->pdev->dev,
586 "Timeout exceeded in %s, aborting dump\n",
591 addr = l2->read_addr;
592 cnt = l2->read_addr_num;
594 data = qlcnic_ind_rd(adapter, addr);
595 *buffer++ = cpu_to_le32(data);
596 addr += l2->read_addr_stride;
601 return l2->no_ops * l2->read_addr_num * sizeof(u32);
604 static u32 qlcnic_read_memory_test_agent(struct qlcnic_adapter *adapter,
605 struct __mem *mem, __le32 *buffer,
608 u32 addr, data, test;
611 reg_read = mem->size;
613 /* check for data size of multiple of 16 and 16 byte alignment */
614 if ((addr & 0xf) || (reg_read%16)) {
615 dev_info(&adapter->pdev->dev,
616 "Unaligned memory addr:0x%x size:0x%x\n",
622 mutex_lock(&adapter->ahw->mem_lock);
624 while (reg_read != 0) {
625 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
626 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
627 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_START_ENABLE);
629 for (i = 0; i < MAX_CTL_CHECK; i++) {
630 test = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
631 if (!(test & TA_CTL_BUSY))
634 if (i == MAX_CTL_CHECK) {
635 if (printk_ratelimit()) {
636 dev_err(&adapter->pdev->dev,
637 "failed to read through agent\n");
642 for (i = 0; i < 4; i++) {
643 data = qlcnic_ind_rd(adapter, qlcnic_ms_read_data[i]);
644 *buffer++ = cpu_to_le32(data);
651 mutex_unlock(&adapter->ahw->mem_lock);
655 /* DMA register base address */
656 #define QLC_DMA_REG_BASE_ADDR(dma_no) (0x77320000 + (dma_no * 0x10000))
658 /* DMA register offsets w.r.t base address */
659 #define QLC_DMA_CMD_BUFF_ADDR_LOW 0
660 #define QLC_DMA_CMD_BUFF_ADDR_HI 4
661 #define QLC_DMA_CMD_STATUS_CTRL 8
663 static int qlcnic_start_pex_dma(struct qlcnic_adapter *adapter,
666 struct device *dev = &adapter->pdev->dev;
667 u32 dma_no, dma_base_addr, temp_addr;
671 tmpl_hdr = adapter->ahw->fw_dump.tmpl_hdr;
672 dma_no = qlcnic_get_saved_state(adapter, tmpl_hdr,
673 QLC_83XX_DMA_ENGINE_INDEX);
674 dma_base_addr = QLC_DMA_REG_BASE_ADDR(dma_no);
676 temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_LOW;
677 ret = qlcnic_ind_wr(adapter, temp_addr, mem->desc_card_addr);
681 temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_HI;
682 ret = qlcnic_ind_wr(adapter, temp_addr, 0);
686 temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL;
687 ret = qlcnic_ind_wr(adapter, temp_addr, mem->start_dma_cmd);
691 /* Wait for DMA to complete */
692 temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL;
693 for (i = 0; i < 400; i++) {
694 dma_sts = qlcnic_ind_rd(adapter, temp_addr);
697 usleep_range(250, 500);
703 dev_info(dev, "PEX DMA operation timed out");
710 static u32 qlcnic_read_memory_pexdma(struct qlcnic_adapter *adapter,
712 __le32 *buffer, int *ret)
714 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
715 u32 temp, dma_base_addr, size = 0, read_size = 0;
716 struct qlcnic_pex_dma_descriptor *dma_descr;
717 struct device *dev = &adapter->pdev->dev;
718 dma_addr_t dma_phys_addr;
722 tmpl_hdr = fw_dump->tmpl_hdr;
724 /* Check if DMA engine is available */
725 temp = qlcnic_get_saved_state(adapter, tmpl_hdr,
726 QLC_83XX_DMA_ENGINE_INDEX);
727 dma_base_addr = QLC_DMA_REG_BASE_ADDR(temp);
728 temp = qlcnic_ind_rd(adapter,
729 dma_base_addr + QLC_DMA_CMD_STATUS_CTRL);
731 if (!(temp & BIT_31)) {
732 dev_info(dev, "%s: DMA engine is not available\n", __func__);
737 /* Create DMA descriptor */
738 dma_descr = kzalloc(sizeof(struct qlcnic_pex_dma_descriptor),
745 /* dma_desc_cmd 0:15 = 0
746 * dma_desc_cmd 16:19 = mem->dma_desc_cmd 0:3
747 * dma_desc_cmd 20:23 = pci function number
748 * dma_desc_cmd 24:31 = mem->dma_desc_cmd 8:15
750 dma_phys_addr = fw_dump->phys_addr;
751 dma_buffer = fw_dump->dma_buffer;
753 temp = mem->dma_desc_cmd & 0xff0f;
754 temp |= (adapter->ahw->pci_func & 0xf) << 4;
755 dma_descr->dma_desc_cmd = (temp << 16) & 0xffff0000;
756 dma_descr->dma_bus_addr_low = LSD(dma_phys_addr);
757 dma_descr->dma_bus_addr_high = MSD(dma_phys_addr);
758 dma_descr->src_addr_high = 0;
760 /* Collect memory dump using multiple DMA operations if required */
761 while (read_size < mem->size) {
762 if (mem->size - read_size >= QLC_PEX_DMA_READ_SIZE)
763 size = QLC_PEX_DMA_READ_SIZE;
765 size = mem->size - read_size;
767 dma_descr->src_addr_low = mem->addr + read_size;
768 dma_descr->read_data_size = size;
770 /* Write DMA descriptor to MS memory*/
771 temp = sizeof(struct qlcnic_pex_dma_descriptor) / 16;
772 *ret = qlcnic_ms_mem_write128(adapter, mem->desc_card_addr,
773 (u32 *)dma_descr, temp);
775 dev_info(dev, "Failed to write DMA descriptor to MS memory at address 0x%x\n",
776 mem->desc_card_addr);
780 *ret = qlcnic_start_pex_dma(adapter, mem);
782 dev_info(dev, "Failed to start PEX DMA operation\n");
786 memcpy(buffer, dma_buffer, size);
797 static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter,
798 struct qlcnic_dump_entry *entry, __le32 *buffer)
800 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
801 struct device *dev = &adapter->pdev->dev;
802 struct __mem *mem = &entry->region.mem;
806 if (fw_dump->use_pex_dma) {
807 data_size = qlcnic_read_memory_pexdma(adapter, mem, buffer,
811 "Failed to read memory dump using PEX DMA: mask[0x%x]\n",
817 data_size = qlcnic_read_memory_test_agent(adapter, mem, buffer, &ret);
820 "Failed to read memory dump using test agent method: mask[0x%x]\n",
828 static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter,
829 struct qlcnic_dump_entry *entry, __le32 *buffer)
831 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
835 static int qlcnic_valid_dump_entry(struct device *dev,
836 struct qlcnic_dump_entry *entry, u32 size)
839 if (size != entry->hdr.cap_size) {
841 "Invalid entry, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
842 entry->hdr.type, entry->hdr.mask, size,
843 entry->hdr.cap_size);
849 static u32 qlcnic_read_pollrdmwr(struct qlcnic_adapter *adapter,
850 struct qlcnic_dump_entry *entry,
853 struct __pollrdmwr *poll = &entry->region.pollrdmwr;
854 u32 data, wait_count, poll_wait, temp;
856 poll_wait = poll->poll_wait;
858 qlcnic_ind_wr(adapter, poll->addr1, poll->val1);
861 while (wait_count < poll_wait) {
862 data = qlcnic_ind_rd(adapter, poll->addr1);
863 if ((data & poll->poll_mask) != 0)
868 if (wait_count == poll_wait) {
869 dev_err(&adapter->pdev->dev,
870 "Timeout exceeded in %s, aborting dump\n",
875 data = qlcnic_ind_rd(adapter, poll->addr2) & poll->mod_mask;
876 qlcnic_ind_wr(adapter, poll->addr2, data);
877 qlcnic_ind_wr(adapter, poll->addr1, poll->val2);
880 while (wait_count < poll_wait) {
881 temp = qlcnic_ind_rd(adapter, poll->addr1);
882 if ((temp & poll->poll_mask) != 0)
887 *buffer++ = cpu_to_le32(poll->addr2);
888 *buffer++ = cpu_to_le32(data);
890 return 2 * sizeof(u32);
894 static u32 qlcnic_read_pollrd(struct qlcnic_adapter *adapter,
895 struct qlcnic_dump_entry *entry, __le32 *buffer)
897 struct __pollrd *pollrd = &entry->region.pollrd;
898 u32 data, wait_count, poll_wait, sel_val;
901 poll_wait = pollrd->poll_wait;
902 sel_val = pollrd->sel_val;
904 for (i = 0; i < pollrd->no_ops; i++) {
905 qlcnic_ind_wr(adapter, pollrd->sel_addr, sel_val);
907 while (wait_count < poll_wait) {
908 data = qlcnic_ind_rd(adapter, pollrd->sel_addr);
909 if ((data & pollrd->poll_mask) != 0)
914 if (wait_count == poll_wait) {
915 dev_err(&adapter->pdev->dev,
916 "Timeout exceeded in %s, aborting dump\n",
921 data = qlcnic_ind_rd(adapter, pollrd->read_addr);
922 *buffer++ = cpu_to_le32(sel_val);
923 *buffer++ = cpu_to_le32(data);
924 sel_val += pollrd->sel_val_stride;
926 return pollrd->no_ops * (2 * sizeof(u32));
929 static u32 qlcnic_read_mux2(struct qlcnic_adapter *adapter,
930 struct qlcnic_dump_entry *entry, __le32 *buffer)
932 struct __mux2 *mux2 = &entry->region.mux2;
934 u32 t_sel_val, sel_val1, sel_val2;
937 sel_val1 = mux2->sel_val1;
938 sel_val2 = mux2->sel_val2;
940 for (i = 0; i < mux2->no_ops; i++) {
941 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val1);
942 t_sel_val = sel_val1 & mux2->sel_val_mask;
943 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val);
944 data = qlcnic_ind_rd(adapter, mux2->read_addr);
945 *buffer++ = cpu_to_le32(t_sel_val);
946 *buffer++ = cpu_to_le32(data);
947 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val2);
948 t_sel_val = sel_val2 & mux2->sel_val_mask;
949 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val);
950 data = qlcnic_ind_rd(adapter, mux2->read_addr);
951 *buffer++ = cpu_to_le32(t_sel_val);
952 *buffer++ = cpu_to_le32(data);
953 sel_val1 += mux2->sel_val_stride;
954 sel_val2 += mux2->sel_val_stride;
957 return mux2->no_ops * (4 * sizeof(u32));
960 static u32 qlcnic_83xx_dump_rom(struct qlcnic_adapter *adapter,
961 struct qlcnic_dump_entry *entry, __le32 *buffer)
964 struct __mem *rom = &entry->region.mem;
967 size = rom->size / 4;
969 if (!qlcnic_83xx_lockless_flash_read32(adapter, fl_addr,
976 static const struct qlcnic_dump_operations qlcnic_fw_dump_ops[] = {
977 {QLCNIC_DUMP_NOP, qlcnic_dump_nop},
978 {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb},
979 {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux},
980 {QLCNIC_DUMP_QUEUE, qlcnic_dump_que},
981 {QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom},
982 {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm},
983 {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl},
984 {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache},
985 {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache},
986 {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache},
987 {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache},
988 {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache},
989 {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache},
990 {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache},
991 {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache},
992 {QLCNIC_DUMP_READ_ROM, qlcnic_read_rom},
993 {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory},
994 {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl},
995 {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop},
996 {QLCNIC_DUMP_RDEND, qlcnic_dump_nop},
999 static const struct qlcnic_dump_operations qlcnic_83xx_fw_dump_ops[] = {
1000 {QLCNIC_DUMP_NOP, qlcnic_dump_nop},
1001 {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb},
1002 {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux},
1003 {QLCNIC_DUMP_QUEUE, qlcnic_dump_que},
1004 {QLCNIC_DUMP_BRD_CONFIG, qlcnic_83xx_dump_rom},
1005 {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm},
1006 {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl},
1007 {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache},
1008 {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache},
1009 {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache},
1010 {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache},
1011 {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache},
1012 {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache},
1013 {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache},
1014 {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache},
1015 {QLCNIC_DUMP_POLL_RD, qlcnic_read_pollrd},
1016 {QLCNIC_READ_MUX2, qlcnic_read_mux2},
1017 {QLCNIC_READ_POLLRDMWR, qlcnic_read_pollrdmwr},
1018 {QLCNIC_DUMP_READ_ROM, qlcnic_83xx_dump_rom},
1019 {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory},
1020 {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl},
1021 {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop},
1022 {QLCNIC_DUMP_RDEND, qlcnic_dump_nop},
1025 static uint32_t qlcnic_temp_checksum(uint32_t *temp_buffer, u32 temp_size)
1028 int count = temp_size / sizeof(uint32_t);
1030 sum += *temp_buffer++;
1032 sum = (sum & 0xFFFFFFFF) + (sum >> 32);
1036 static int qlcnic_fw_flash_get_minidump_temp(struct qlcnic_adapter *adapter,
1037 u8 *buffer, u32 size)
1041 if (qlcnic_82xx_check(adapter))
1044 if (qlcnic_83xx_lock_flash(adapter))
1047 ret = qlcnic_83xx_lockless_flash_read32(adapter,
1048 QLC_83XX_MINIDUMP_FLASH,
1049 buffer, size / sizeof(u32));
1051 qlcnic_83xx_unlock_flash(adapter);
1057 qlcnic_fw_flash_get_minidump_temp_size(struct qlcnic_adapter *adapter,
1058 struct qlcnic_cmd_args *cmd)
1060 struct qlcnic_83xx_dump_template_hdr tmp_hdr;
1061 u32 size = sizeof(tmp_hdr) / sizeof(u32);
1064 if (qlcnic_82xx_check(adapter))
1067 if (qlcnic_83xx_lock_flash(adapter))
1070 ret = qlcnic_83xx_lockless_flash_read32(adapter,
1071 QLC_83XX_MINIDUMP_FLASH,
1072 (u8 *)&tmp_hdr, size);
1074 qlcnic_83xx_unlock_flash(adapter);
1076 cmd->rsp.arg[2] = tmp_hdr.size;
1077 cmd->rsp.arg[3] = tmp_hdr.version;
1082 static int qlcnic_fw_get_minidump_temp_size(struct qlcnic_adapter *adapter,
1083 u32 *version, u32 *temp_size,
1087 struct qlcnic_cmd_args cmd;
1089 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TEMP_SIZE))
1092 err = qlcnic_issue_cmd(adapter, &cmd);
1093 if (err != QLCNIC_RCODE_SUCCESS) {
1094 if (qlcnic_fw_flash_get_minidump_temp_size(adapter, &cmd)) {
1095 qlcnic_free_mbx_args(&cmd);
1098 *use_flash_temp = 1;
1101 *temp_size = cmd.rsp.arg[2];
1102 *version = cmd.rsp.arg[3];
1103 qlcnic_free_mbx_args(&cmd);
1111 static int __qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter,
1112 u32 *buffer, u32 temp_size)
1117 struct qlcnic_cmd_args cmd;
1118 dma_addr_t tmp_addr_t = 0;
1120 tmp_addr = dma_alloc_coherent(&adapter->pdev->dev, temp_size,
1121 &tmp_addr_t, GFP_KERNEL);
1125 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_TEMP_HDR)) {
1130 cmd.req.arg[1] = LSD(tmp_addr_t);
1131 cmd.req.arg[2] = MSD(tmp_addr_t);
1132 cmd.req.arg[3] = temp_size;
1133 err = qlcnic_issue_cmd(adapter, &cmd);
1136 if (err == QLCNIC_RCODE_SUCCESS) {
1137 for (i = 0; i < temp_size / sizeof(u32); i++)
1138 *buffer++ = __le32_to_cpu(*tmp_buf++);
1141 qlcnic_free_mbx_args(&cmd);
1144 dma_free_coherent(&adapter->pdev->dev, temp_size, tmp_addr, tmp_addr_t);
1149 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter)
1151 struct qlcnic_hardware_context *ahw;
1152 struct qlcnic_fw_dump *fw_dump;
1153 u32 version, csum, *tmp_buf;
1154 u8 use_flash_temp = 0;
1160 fw_dump = &ahw->fw_dump;
1161 err = qlcnic_fw_get_minidump_temp_size(adapter, &version, &temp_size,
1164 dev_err(&adapter->pdev->dev,
1165 "Can't get template size %d\n", err);
1169 fw_dump->tmpl_hdr = vzalloc(temp_size);
1170 if (!fw_dump->tmpl_hdr)
1173 tmp_buf = (u32 *)fw_dump->tmpl_hdr;
1177 err = __qlcnic_fw_cmd_get_minidump_temp(adapter, tmp_buf, temp_size);
1181 err = qlcnic_fw_flash_get_minidump_temp(adapter, (u8 *)tmp_buf,
1185 dev_err(&adapter->pdev->dev,
1186 "Failed to get minidump template header %d\n",
1188 vfree(fw_dump->tmpl_hdr);
1189 fw_dump->tmpl_hdr = NULL;
1194 csum = qlcnic_temp_checksum((uint32_t *)tmp_buf, temp_size);
1197 dev_err(&adapter->pdev->dev,
1198 "Template header checksum validation failed\n");
1199 vfree(fw_dump->tmpl_hdr);
1200 fw_dump->tmpl_hdr = NULL;
1204 qlcnic_cache_tmpl_hdr_values(adapter, fw_dump);
1206 if (fw_dump->use_pex_dma) {
1207 fw_dump->dma_buffer = NULL;
1208 temp_buffer = dma_alloc_coherent(&adapter->pdev->dev,
1209 QLC_PEX_DMA_READ_SIZE,
1210 &fw_dump->phys_addr,
1213 fw_dump->use_pex_dma = false;
1215 fw_dump->dma_buffer = temp_buffer;
1219 dev_info(&adapter->pdev->dev,
1220 "Default minidump capture mask 0x%x\n",
1223 qlcnic_enable_fw_dump_state(adapter);
1228 int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
1230 struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
1231 static const struct qlcnic_dump_operations *fw_dump_ops;
1232 struct qlcnic_83xx_dump_template_hdr *hdr_83xx;
1233 u32 entry_offset, dump, no_entries, buf_offset = 0;
1234 int i, k, ops_cnt, ops_index, dump_size = 0;
1235 struct device *dev = &adapter->pdev->dev;
1236 struct qlcnic_hardware_context *ahw;
1237 struct qlcnic_dump_entry *entry;
1242 char *msg[] = {mesg, NULL};
1245 tmpl_hdr = fw_dump->tmpl_hdr;
1247 /* Return if we don't have firmware dump template header */
1251 if (!qlcnic_check_fw_dump_state(adapter)) {
1252 dev_info(&adapter->pdev->dev, "Dump not enabled\n");
1257 dev_info(&adapter->pdev->dev,
1258 "Previous dump not cleared, not capturing dump\n");
1262 netif_info(adapter->ahw, drv, adapter->netdev, "Take FW dump\n");
1263 /* Calculate the size for dump data area only */
1264 for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
1265 if (i & fw_dump->cap_mask)
1266 dump_size += qlcnic_get_cap_size(adapter, tmpl_hdr, k);
1271 fw_dump->data = vzalloc(dump_size);
1275 buffer = fw_dump->data;
1276 fw_dump->size = dump_size;
1277 no_entries = fw_dump->num_entries;
1278 entry_offset = fw_dump->offset;
1279 qlcnic_set_sys_info(adapter, tmpl_hdr, 0, QLCNIC_DRIVER_VERSION);
1280 qlcnic_set_sys_info(adapter, tmpl_hdr, 1, adapter->fw_version);
1282 if (qlcnic_82xx_check(adapter)) {
1283 ops_cnt = ARRAY_SIZE(qlcnic_fw_dump_ops);
1284 fw_dump_ops = qlcnic_fw_dump_ops;
1286 hdr_83xx = tmpl_hdr;
1287 ops_cnt = ARRAY_SIZE(qlcnic_83xx_fw_dump_ops);
1288 fw_dump_ops = qlcnic_83xx_fw_dump_ops;
1289 ocm_window = hdr_83xx->ocm_wnd_reg[ahw->pci_func];
1290 hdr_83xx->saved_state[QLC_83XX_OCM_INDEX] = ocm_window;
1291 hdr_83xx->saved_state[QLC_83XX_PCI_INDEX] = ahw->pci_func;
1294 for (i = 0; i < no_entries; i++) {
1295 entry = tmpl_hdr + entry_offset;
1296 if (!(entry->hdr.mask & fw_dump->cap_mask)) {
1297 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1298 entry_offset += entry->hdr.offset;
1302 /* Find the handler for this entry */
1304 while (ops_index < ops_cnt) {
1305 if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
1310 if (ops_index == ops_cnt) {
1311 dev_info(dev, "Skipping unknown entry opcode %d\n",
1313 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1314 entry_offset += entry->hdr.offset;
1318 /* Collect dump for this entry */
1319 dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
1320 if (!qlcnic_valid_dump_entry(dev, entry, dump)) {
1321 entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1322 entry_offset += entry->hdr.offset;
1326 buf_offset += entry->hdr.cap_size;
1327 entry_offset += entry->hdr.offset;
1328 buffer = fw_dump->data + buf_offset;
1332 snprintf(mesg, sizeof(mesg), "FW_DUMP=%s", adapter->netdev->name);
1333 netdev_info(adapter->netdev,
1334 "Dump data %d bytes captured, template header size %d bytes\n",
1335 fw_dump->size, fw_dump->tmpl_hdr_size);
1336 /* Send a udev event to notify availability of FW dump */
1337 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, msg);
1342 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *adapter)
1344 u32 prev_version, current_version;
1345 struct qlcnic_hardware_context *ahw = adapter->ahw;
1346 struct qlcnic_fw_dump *fw_dump = &ahw->fw_dump;
1347 struct pci_dev *pdev = adapter->pdev;
1349 prev_version = adapter->fw_version;
1350 current_version = qlcnic_83xx_get_fw_version(adapter);
1352 if (fw_dump->tmpl_hdr == NULL || current_version > prev_version) {
1353 if (fw_dump->tmpl_hdr)
1354 vfree(fw_dump->tmpl_hdr);
1355 if (!qlcnic_fw_cmd_get_minidump_temp(adapter))
1356 dev_info(&pdev->dev, "Supports FW dump capability\n");