2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2013 QLogic Corporation
5 * See LICENSE.qlcnic for copyright and licensing details.
9 #include "qlcnic_sriov.h"
10 #include <linux/if_vlan.h>
11 #include <linux/ipv6.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/aer.h>
16 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *);
17 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
18 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
19 struct qlcnic_cmd_args *);
20 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
21 static irqreturn_t qlcnic_83xx_handle_aen(int, void *);
22 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *,
24 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
25 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *);
26 static void qlcnic_83xx_io_resume(struct pci_dev *);
27 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
28 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *);
29 static int qlcnic_83xx_resume(struct qlcnic_adapter *);
30 static int qlcnic_83xx_shutdown(struct pci_dev *);
31 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
33 #define RSS_HASHTYPE_IP_TCP 0x3
34 #define QLC_83XX_FW_MBX_CMD 0
35 #define QLC_SKIP_INACTIVE_PCI_REGS 7
36 #define QLC_MAX_LEGACY_FUNC_SUPP 8
38 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
39 {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
40 {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
41 {QLCNIC_CMD_CREATE_RX_CTX, 136, 27},
42 {QLCNIC_CMD_DESTROY_RX_CTX, 2, 1},
43 {QLCNIC_CMD_CREATE_TX_CTX, 54, 18},
44 {QLCNIC_CMD_DESTROY_TX_CTX, 2, 1},
45 {QLCNIC_CMD_CONFIGURE_MAC_LEARNING, 2, 1},
46 {QLCNIC_CMD_INTRPT_TEST, 22, 12},
47 {QLCNIC_CMD_SET_MTU, 3, 1},
48 {QLCNIC_CMD_READ_PHY, 4, 2},
49 {QLCNIC_CMD_WRITE_PHY, 5, 1},
50 {QLCNIC_CMD_READ_HW_REG, 4, 1},
51 {QLCNIC_CMD_GET_FLOW_CTL, 4, 2},
52 {QLCNIC_CMD_SET_FLOW_CTL, 4, 1},
53 {QLCNIC_CMD_READ_MAX_MTU, 4, 2},
54 {QLCNIC_CMD_READ_MAX_LRO, 4, 2},
55 {QLCNIC_CMD_MAC_ADDRESS, 4, 3},
56 {QLCNIC_CMD_GET_PCI_INFO, 1, 129},
57 {QLCNIC_CMD_GET_NIC_INFO, 2, 19},
58 {QLCNIC_CMD_SET_NIC_INFO, 32, 1},
59 {QLCNIC_CMD_GET_ESWITCH_CAPABILITY, 4, 3},
60 {QLCNIC_CMD_TOGGLE_ESWITCH, 4, 1},
61 {QLCNIC_CMD_GET_ESWITCH_STATUS, 4, 3},
62 {QLCNIC_CMD_SET_PORTMIRRORING, 4, 1},
63 {QLCNIC_CMD_CONFIGURE_ESWITCH, 4, 1},
64 {QLCNIC_CMD_GET_ESWITCH_PORT_CONFIG, 4, 3},
65 {QLCNIC_CMD_GET_ESWITCH_STATS, 5, 1},
66 {QLCNIC_CMD_CONFIG_PORT, 4, 1},
67 {QLCNIC_CMD_TEMP_SIZE, 1, 4},
68 {QLCNIC_CMD_GET_TEMP_HDR, 5, 5},
69 {QLCNIC_CMD_GET_LINK_EVENT, 2, 1},
70 {QLCNIC_CMD_CONFIG_MAC_VLAN, 4, 3},
71 {QLCNIC_CMD_CONFIG_INTR_COAL, 6, 1},
72 {QLCNIC_CMD_CONFIGURE_RSS, 14, 1},
73 {QLCNIC_CMD_CONFIGURE_LED, 2, 1},
74 {QLCNIC_CMD_CONFIGURE_MAC_RX_MODE, 2, 1},
75 {QLCNIC_CMD_CONFIGURE_HW_LRO, 2, 1},
76 {QLCNIC_CMD_GET_STATISTICS, 2, 80},
77 {QLCNIC_CMD_SET_PORT_CONFIG, 2, 1},
78 {QLCNIC_CMD_GET_PORT_CONFIG, 2, 2},
79 {QLCNIC_CMD_GET_LINK_STATUS, 2, 4},
80 {QLCNIC_CMD_IDC_ACK, 5, 1},
81 {QLCNIC_CMD_INIT_NIC_FUNC, 3, 1},
82 {QLCNIC_CMD_STOP_NIC_FUNC, 2, 1},
83 {QLCNIC_CMD_SET_LED_CONFIG, 5, 1},
84 {QLCNIC_CMD_GET_LED_CONFIG, 1, 5},
85 {QLCNIC_CMD_83XX_SET_DRV_VER, 4, 1},
86 {QLCNIC_CMD_ADD_RCV_RINGS, 130, 26},
87 {QLCNIC_CMD_CONFIG_VPORT, 4, 4},
88 {QLCNIC_CMD_BC_EVENT_SETUP, 2, 1},
89 {QLCNIC_CMD_DCB_QUERY_CAP, 1, 2},
90 {QLCNIC_CMD_DCB_QUERY_PARAM, 1, 50},
91 {QLCNIC_CMD_SET_INGRESS_ENCAP, 2, 1},
94 const u32 qlcnic_83xx_ext_reg_tbl[] = {
95 0x38CC, /* Global Reset */
96 0x38F0, /* Wildcard */
97 0x38FC, /* Informant */
98 0x3038, /* Host MBX ctrl */
99 0x303C, /* FW MBX ctrl */
100 0x355C, /* BOOT LOADER ADDRESS REG */
101 0x3560, /* BOOT LOADER SIZE REG */
102 0x3564, /* FW IMAGE ADDR REG */
103 0x1000, /* MBX intr enable */
104 0x1200, /* Default Intr mask */
105 0x1204, /* Default Interrupt ID */
106 0x3780, /* QLC_83XX_IDC_MAJ_VERSION */
107 0x3784, /* QLC_83XX_IDC_DEV_STATE */
108 0x3788, /* QLC_83XX_IDC_DRV_PRESENCE */
109 0x378C, /* QLC_83XX_IDC_DRV_ACK */
110 0x3790, /* QLC_83XX_IDC_CTRL */
111 0x3794, /* QLC_83XX_IDC_DRV_AUDIT */
112 0x3798, /* QLC_83XX_IDC_MIN_VERSION */
113 0x379C, /* QLC_83XX_RECOVER_DRV_LOCK */
114 0x37A0, /* QLC_83XX_IDC_PF_0 */
115 0x37A4, /* QLC_83XX_IDC_PF_1 */
116 0x37A8, /* QLC_83XX_IDC_PF_2 */
117 0x37AC, /* QLC_83XX_IDC_PF_3 */
118 0x37B0, /* QLC_83XX_IDC_PF_4 */
119 0x37B4, /* QLC_83XX_IDC_PF_5 */
120 0x37B8, /* QLC_83XX_IDC_PF_6 */
121 0x37BC, /* QLC_83XX_IDC_PF_7 */
122 0x37C0, /* QLC_83XX_IDC_PF_8 */
123 0x37C4, /* QLC_83XX_IDC_PF_9 */
124 0x37C8, /* QLC_83XX_IDC_PF_10 */
125 0x37CC, /* QLC_83XX_IDC_PF_11 */
126 0x37D0, /* QLC_83XX_IDC_PF_12 */
127 0x37D4, /* QLC_83XX_IDC_PF_13 */
128 0x37D8, /* QLC_83XX_IDC_PF_14 */
129 0x37DC, /* QLC_83XX_IDC_PF_15 */
130 0x37E0, /* QLC_83XX_IDC_DEV_PARTITION_INFO_1 */
131 0x37E4, /* QLC_83XX_IDC_DEV_PARTITION_INFO_2 */
132 0x37F0, /* QLC_83XX_DRV_OP_MODE */
133 0x37F4, /* QLC_83XX_VNIC_STATE */
134 0x3868, /* QLC_83XX_DRV_LOCK */
135 0x386C, /* QLC_83XX_DRV_UNLOCK */
136 0x3504, /* QLC_83XX_DRV_LOCK_ID */
137 0x34A4, /* QLC_83XX_ASIC_TEMP */
140 const u32 qlcnic_83xx_reg_tbl[] = {
141 0x34A8, /* PEG_HALT_STAT1 */
142 0x34AC, /* PEG_HALT_STAT2 */
143 0x34B0, /* FW_HEARTBEAT */
144 0x3500, /* FLASH LOCK_ID */
145 0x3528, /* FW_CAPABILITIES */
146 0x3538, /* Driver active, DRV_REG0 */
147 0x3540, /* Device state, DRV_REG1 */
148 0x3544, /* Driver state, DRV_REG2 */
149 0x3548, /* Driver scratch, DRV_REG3 */
150 0x354C, /* Device partiton info, DRV_REG4 */
151 0x3524, /* Driver IDC ver, DRV_REG5 */
152 0x3550, /* FW_VER_MAJOR */
153 0x3554, /* FW_VER_MINOR */
154 0x3558, /* FW_VER_SUB */
155 0x359C, /* NPAR STATE */
156 0x35FC, /* FW_IMG_VALID */
157 0x3650, /* CMD_PEG_STATE */
158 0x373C, /* RCV_PEG_STATE */
159 0x37B4, /* ASIC TEMP */
161 0x3570, /* DRV OP MODE */
162 0x3850, /* FLASH LOCK */
163 0x3854, /* FLASH UNLOCK */
166 static struct qlcnic_hardware_ops qlcnic_83xx_hw_ops = {
167 .read_crb = qlcnic_83xx_read_crb,
168 .write_crb = qlcnic_83xx_write_crb,
169 .read_reg = qlcnic_83xx_rd_reg_indirect,
170 .write_reg = qlcnic_83xx_wrt_reg_indirect,
171 .get_mac_address = qlcnic_83xx_get_mac_address,
172 .setup_intr = qlcnic_83xx_setup_intr,
173 .alloc_mbx_args = qlcnic_83xx_alloc_mbx_args,
174 .mbx_cmd = qlcnic_83xx_issue_cmd,
175 .get_func_no = qlcnic_83xx_get_func_no,
176 .api_lock = qlcnic_83xx_cam_lock,
177 .api_unlock = qlcnic_83xx_cam_unlock,
178 .add_sysfs = qlcnic_83xx_add_sysfs,
179 .remove_sysfs = qlcnic_83xx_remove_sysfs,
180 .process_lb_rcv_ring_diag = qlcnic_83xx_process_rcv_ring_diag,
181 .create_rx_ctx = qlcnic_83xx_create_rx_ctx,
182 .create_tx_ctx = qlcnic_83xx_create_tx_ctx,
183 .del_rx_ctx = qlcnic_83xx_del_rx_ctx,
184 .del_tx_ctx = qlcnic_83xx_del_tx_ctx,
185 .setup_link_event = qlcnic_83xx_setup_link_event,
186 .get_nic_info = qlcnic_83xx_get_nic_info,
187 .get_pci_info = qlcnic_83xx_get_pci_info,
188 .set_nic_info = qlcnic_83xx_set_nic_info,
189 .change_macvlan = qlcnic_83xx_sre_macaddr_change,
190 .napi_enable = qlcnic_83xx_napi_enable,
191 .napi_disable = qlcnic_83xx_napi_disable,
192 .config_intr_coal = qlcnic_83xx_config_intr_coal,
193 .config_rss = qlcnic_83xx_config_rss,
194 .config_hw_lro = qlcnic_83xx_config_hw_lro,
195 .config_promisc_mode = qlcnic_83xx_nic_set_promisc,
196 .change_l2_filter = qlcnic_83xx_change_l2_filter,
197 .get_board_info = qlcnic_83xx_get_port_info,
198 .set_mac_filter_count = qlcnic_83xx_set_mac_filter_count,
199 .free_mac_list = qlcnic_82xx_free_mac_list,
200 .io_error_detected = qlcnic_83xx_io_error_detected,
201 .io_slot_reset = qlcnic_83xx_io_slot_reset,
202 .io_resume = qlcnic_83xx_io_resume,
203 .get_beacon_state = qlcnic_83xx_get_beacon_state,
204 .enable_sds_intr = qlcnic_83xx_enable_sds_intr,
205 .disable_sds_intr = qlcnic_83xx_disable_sds_intr,
206 .enable_tx_intr = qlcnic_83xx_enable_tx_intr,
207 .disable_tx_intr = qlcnic_83xx_disable_tx_intr,
208 .get_saved_state = qlcnic_83xx_get_saved_state,
209 .set_saved_state = qlcnic_83xx_set_saved_state,
210 .cache_tmpl_hdr_values = qlcnic_83xx_cache_tmpl_hdr_values,
211 .get_cap_size = qlcnic_83xx_get_cap_size,
212 .set_sys_info = qlcnic_83xx_set_sys_info,
213 .store_cap_mask = qlcnic_83xx_store_cap_mask,
216 static struct qlcnic_nic_template qlcnic_83xx_ops = {
217 .config_bridged_mode = qlcnic_config_bridged_mode,
218 .config_led = qlcnic_config_led,
219 .request_reset = qlcnic_83xx_idc_request_reset,
220 .cancel_idc_work = qlcnic_83xx_idc_exit,
221 .napi_add = qlcnic_83xx_napi_add,
222 .napi_del = qlcnic_83xx_napi_del,
223 .config_ipaddr = qlcnic_83xx_config_ipaddr,
224 .clear_legacy_intr = qlcnic_83xx_clear_legacy_intr,
225 .shutdown = qlcnic_83xx_shutdown,
226 .resume = qlcnic_83xx_resume,
229 void qlcnic_83xx_register_map(struct qlcnic_hardware_context *ahw)
231 ahw->hw_ops = &qlcnic_83xx_hw_ops;
232 ahw->reg_tbl = (u32 *)qlcnic_83xx_reg_tbl;
233 ahw->ext_reg_tbl = (u32 *)qlcnic_83xx_ext_reg_tbl;
236 int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *adapter)
238 u32 fw_major, fw_minor, fw_build;
239 struct pci_dev *pdev = adapter->pdev;
241 fw_major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
242 fw_minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
243 fw_build = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
244 adapter->fw_version = QLCNIC_VERSION_CODE(fw_major, fw_minor, fw_build);
246 dev_info(&pdev->dev, "Driver v%s, firmware version %d.%d.%d\n",
247 QLCNIC_LINUX_VERSIONID, fw_major, fw_minor, fw_build);
249 return adapter->fw_version;
252 static int __qlcnic_set_win_base(struct qlcnic_adapter *adapter, u32 addr)
257 base = adapter->ahw->pci_base0 +
258 QLC_83XX_CRB_WIN_FUNC(adapter->ahw->pci_func);
267 int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
270 struct qlcnic_hardware_context *ahw = adapter->ahw;
272 *err = __qlcnic_set_win_base(adapter, (u32) addr);
274 return QLCRDX(ahw, QLCNIC_WILDCARD);
276 dev_err(&adapter->pdev->dev,
277 "%s failed, addr = 0x%lx\n", __func__, addr);
282 int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *adapter, ulong addr,
286 struct qlcnic_hardware_context *ahw = adapter->ahw;
288 err = __qlcnic_set_win_base(adapter, (u32) addr);
290 QLCWRX(ahw, QLCNIC_WILDCARD, data);
293 dev_err(&adapter->pdev->dev,
294 "%s failed, addr = 0x%x data = 0x%x\n",
295 __func__, (int)addr, data);
300 static void qlcnic_83xx_enable_legacy(struct qlcnic_adapter *adapter)
302 struct qlcnic_hardware_context *ahw = adapter->ahw;
304 /* MSI-X enablement failed, use legacy interrupt */
305 adapter->tgt_status_reg = ahw->pci_base0 + QLC_83XX_INTX_PTR;
306 adapter->tgt_mask_reg = ahw->pci_base0 + QLC_83XX_INTX_MASK;
307 adapter->isr_int_vec = ahw->pci_base0 + QLC_83XX_INTX_TRGR;
308 adapter->msix_entries[0].vector = adapter->pdev->irq;
309 dev_info(&adapter->pdev->dev, "using legacy interrupt\n");
312 static int qlcnic_83xx_calculate_msix_vector(struct qlcnic_adapter *adapter)
316 num_msix = adapter->drv_sds_rings;
318 /* account for AEN interrupt MSI-X based interrupts */
321 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
322 num_msix += adapter->drv_tx_rings;
327 int qlcnic_83xx_setup_intr(struct qlcnic_adapter *adapter)
329 struct qlcnic_hardware_context *ahw = adapter->ahw;
330 int err, i, num_msix;
332 if (adapter->flags & QLCNIC_TSS_RSS) {
333 err = qlcnic_setup_tss_rss_intr(adapter);
336 num_msix = ahw->num_msix;
338 num_msix = qlcnic_83xx_calculate_msix_vector(adapter);
340 err = qlcnic_enable_msix(adapter, num_msix);
344 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
345 num_msix = ahw->num_msix;
347 if (qlcnic_sriov_vf_check(adapter))
350 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
351 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
355 /* setup interrupt mapping table for fw */
356 ahw->intr_tbl = vzalloc(num_msix *
357 sizeof(struct qlcnic_intrpt_config));
361 if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
362 if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
363 dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
368 qlcnic_83xx_enable_legacy(adapter);
371 for (i = 0; i < num_msix; i++) {
372 if (adapter->flags & QLCNIC_MSIX_ENABLED)
373 ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
375 ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
376 ahw->intr_tbl[i].id = i;
377 ahw->intr_tbl[i].src = 0;
383 static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
385 writel(0, adapter->tgt_mask_reg);
388 static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
390 if (adapter->tgt_mask_reg)
391 writel(1, adapter->tgt_mask_reg);
394 static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
399 /* Mailbox in MSI-x mode and Legacy Interrupt share the same
400 * source register. We could be here before contexts are created
401 * and sds_ring->crb_intr_mask has not been initialized, calculate
402 * BAR offset for Interrupt Source Register
404 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
405 writel(0, adapter->ahw->pci_base0 + mask);
408 void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
412 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
413 writel(1, adapter->ahw->pci_base0 + mask);
414 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
417 static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
418 struct qlcnic_cmd_args *cmd)
422 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
425 for (i = 0; i < cmd->rsp.num; i++)
426 cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
429 irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
432 struct qlcnic_hardware_context *ahw = adapter->ahw;
435 intr_val = readl(adapter->tgt_status_reg);
437 if (!QLC_83XX_VALID_INTX_BIT31(intr_val))
440 if (QLC_83XX_INTX_FUNC(intr_val) != adapter->ahw->pci_func) {
441 adapter->stats.spurious_intr++;
444 /* The barrier is required to ensure writes to the registers */
447 /* clear the interrupt trigger control register */
448 writel(0, adapter->isr_int_vec);
449 intr_val = readl(adapter->isr_int_vec);
451 intr_val = readl(adapter->tgt_status_reg);
452 if (QLC_83XX_INTX_FUNC(intr_val) != ahw->pci_func)
455 } while (QLC_83XX_VALID_INTX_BIT30(intr_val) &&
456 (retries < QLC_83XX_LEGACY_INTX_MAX_RETRY));
461 static inline void qlcnic_83xx_notify_mbx_response(struct qlcnic_mailbox *mbx)
463 atomic_set(&mbx->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
464 complete(&mbx->completion);
467 static void qlcnic_83xx_poll_process_aen(struct qlcnic_adapter *adapter)
469 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
470 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
473 spin_lock_irqsave(&mbx->aen_lock, flags);
474 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
475 if (!(resp & QLCNIC_SET_OWNER))
478 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
479 if (event & QLCNIC_MBX_ASYNC_EVENT) {
480 __qlcnic_83xx_process_aen(adapter);
482 if (atomic_read(&mbx->rsp_status) != rsp_status)
483 qlcnic_83xx_notify_mbx_response(mbx);
486 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
487 spin_unlock_irqrestore(&mbx->aen_lock, flags);
490 irqreturn_t qlcnic_83xx_intr(int irq, void *data)
492 struct qlcnic_adapter *adapter = data;
493 struct qlcnic_host_sds_ring *sds_ring;
494 struct qlcnic_hardware_context *ahw = adapter->ahw;
496 if (qlcnic_83xx_clear_legacy_intr(adapter) == IRQ_NONE)
499 qlcnic_83xx_poll_process_aen(adapter);
501 if (ahw->diag_test) {
502 if (ahw->diag_test == QLCNIC_INTERRUPT_TEST)
504 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
508 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
509 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
511 sds_ring = &adapter->recv_ctx->sds_rings[0];
512 napi_schedule(&sds_ring->napi);
518 irqreturn_t qlcnic_83xx_tmp_intr(int irq, void *data)
520 struct qlcnic_host_sds_ring *sds_ring = data;
521 struct qlcnic_adapter *adapter = sds_ring->adapter;
523 if (adapter->flags & QLCNIC_MSIX_ENABLED)
526 if (adapter->nic_ops->clear_legacy_intr(adapter) == IRQ_NONE)
530 adapter->ahw->diag_cnt++;
531 qlcnic_enable_sds_intr(adapter, sds_ring);
536 void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *adapter)
540 if (!(adapter->flags & QLCNIC_MSIX_ENABLED))
541 qlcnic_83xx_set_legacy_intr_mask(adapter);
543 qlcnic_83xx_disable_mbx_intr(adapter);
545 if (adapter->flags & QLCNIC_MSIX_ENABLED)
546 num_msix = adapter->ahw->num_msix - 1;
552 if (adapter->msix_entries) {
553 synchronize_irq(adapter->msix_entries[num_msix].vector);
554 free_irq(adapter->msix_entries[num_msix].vector, adapter);
558 int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *adapter)
560 irq_handler_t handler;
563 unsigned long flags = 0;
565 if (!(adapter->flags & QLCNIC_MSI_ENABLED) &&
566 !(adapter->flags & QLCNIC_MSIX_ENABLED))
567 flags |= IRQF_SHARED;
569 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
570 handler = qlcnic_83xx_handle_aen;
571 val = adapter->msix_entries[adapter->ahw->num_msix - 1].vector;
572 err = request_irq(val, handler, flags, "qlcnic-MB", adapter);
574 dev_err(&adapter->pdev->dev,
575 "failed to register MBX interrupt\n");
579 handler = qlcnic_83xx_intr;
580 val = adapter->msix_entries[0].vector;
581 err = request_irq(val, handler, flags, "qlcnic", adapter);
583 dev_err(&adapter->pdev->dev,
584 "failed to register INTx interrupt\n");
587 qlcnic_83xx_clear_legacy_intr_mask(adapter);
590 /* Enable mailbox interrupt */
591 qlcnic_83xx_enable_mbx_interrupt(adapter);
596 void qlcnic_83xx_get_func_no(struct qlcnic_adapter *adapter)
598 u32 val = QLCRDX(adapter->ahw, QLCNIC_INFORMANT);
599 adapter->ahw->pci_func = (val >> 24) & 0xff;
602 int qlcnic_83xx_cam_lock(struct qlcnic_adapter *adapter)
607 struct qlcnic_hardware_context *ahw = adapter->ahw;
609 addr = ahw->pci_base0 + QLC_83XX_SEM_LOCK_FUNC(ahw->pci_func);
613 /* write the function number to register */
614 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
618 usleep_range(1000, 2000);
619 } while (++limit <= QLCNIC_PCIE_SEM_TIMEOUT);
624 void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *adapter)
628 struct qlcnic_hardware_context *ahw = adapter->ahw;
630 addr = ahw->pci_base0 + QLC_83XX_SEM_UNLOCK_FUNC(ahw->pci_func);
634 void qlcnic_83xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
635 loff_t offset, size_t size)
640 if (qlcnic_api_lock(adapter)) {
641 dev_err(&adapter->pdev->dev,
642 "%s: failed to acquire lock. addr offset 0x%x\n",
643 __func__, (u32)offset);
647 data = QLCRD32(adapter, (u32) offset, &ret);
648 qlcnic_api_unlock(adapter);
651 dev_err(&adapter->pdev->dev,
652 "%s: failed. addr offset 0x%x\n",
653 __func__, (u32)offset);
656 memcpy(buf, &data, size);
659 void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
660 loff_t offset, size_t size)
664 memcpy(&data, buf, size);
665 qlcnic_83xx_wrt_reg_indirect(adapter, (u32) offset, data);
668 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
672 status = qlcnic_83xx_get_port_config(adapter);
674 dev_err(&adapter->pdev->dev,
675 "Get Port Info failed\n");
677 if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
678 adapter->ahw->port_type = QLCNIC_XGBE;
680 adapter->ahw->port_type = QLCNIC_GBE;
682 if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
683 adapter->ahw->link_autoneg = AUTONEG_ENABLE;
688 static void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *adapter)
690 struct qlcnic_hardware_context *ahw = adapter->ahw;
691 u16 act_pci_fn = ahw->total_nic_func;
694 ahw->max_mc_count = QLC_83XX_MAX_MC_COUNT;
696 count = (QLC_83XX_MAX_UC_COUNT - QLC_83XX_MAX_MC_COUNT) /
699 count = (QLC_83XX_LB_MAX_FILTERS - QLC_83XX_MAX_MC_COUNT) /
701 ahw->max_uc_count = count;
704 void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *adapter)
708 if (adapter->flags & QLCNIC_MSIX_ENABLED)
709 val = BIT_2 | ((adapter->ahw->num_msix - 1) << 8);
713 QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, val);
714 qlcnic_83xx_enable_legacy_msix_mbx_intr(adapter);
717 void qlcnic_83xx_check_vf(struct qlcnic_adapter *adapter,
718 const struct pci_device_id *ent)
720 u32 op_mode, priv_level;
721 struct qlcnic_hardware_context *ahw = adapter->ahw;
723 ahw->fw_hal_version = 2;
724 qlcnic_get_func_no(adapter);
726 if (qlcnic_sriov_vf_check(adapter)) {
727 qlcnic_sriov_vf_set_ops(adapter);
731 /* Determine function privilege level */
732 op_mode = QLCRDX(adapter->ahw, QLC_83XX_DRV_OP_MODE);
733 if (op_mode == QLC_83XX_DEFAULT_OPMODE)
734 priv_level = QLCNIC_MGMT_FUNC;
736 priv_level = QLC_83XX_GET_FUNC_PRIVILEGE(op_mode,
739 if (priv_level == QLCNIC_NON_PRIV_FUNC) {
740 ahw->op_mode = QLCNIC_NON_PRIV_FUNC;
741 dev_info(&adapter->pdev->dev,
742 "HAL Version: %d Non Privileged function\n",
743 ahw->fw_hal_version);
744 adapter->nic_ops = &qlcnic_vf_ops;
746 if (pci_find_ext_capability(adapter->pdev,
747 PCI_EXT_CAP_ID_SRIOV))
748 set_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state);
749 adapter->nic_ops = &qlcnic_83xx_ops;
753 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
755 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
758 void qlcnic_dump_mbx(struct qlcnic_adapter *adapter,
759 struct qlcnic_cmd_args *cmd)
763 if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
766 dev_info(&adapter->pdev->dev,
767 "Host MBX regs(%d)\n", cmd->req.num);
768 for (i = 0; i < cmd->req.num; i++) {
771 pr_info("%08x ", cmd->req.arg[i]);
774 dev_info(&adapter->pdev->dev,
775 "FW MBX regs(%d)\n", cmd->rsp.num);
776 for (i = 0; i < cmd->rsp.num; i++) {
779 pr_info("%08x ", cmd->rsp.arg[i]);
784 static void qlcnic_83xx_poll_for_mbx_completion(struct qlcnic_adapter *adapter,
785 struct qlcnic_cmd_args *cmd)
787 struct qlcnic_hardware_context *ahw = adapter->ahw;
788 int opcode = LSW(cmd->req.arg[0]);
789 unsigned long max_loops;
791 max_loops = cmd->total_cmds * QLC_83XX_MBX_CMD_LOOP;
793 for (; max_loops; max_loops--) {
794 if (atomic_read(&cmd->rsp_status) ==
795 QLC_83XX_MBX_RESPONSE_ARRIVED)
801 dev_err(&adapter->pdev->dev,
802 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
803 __func__, opcode, cmd->type, ahw->pci_func, ahw->op_mode);
804 flush_workqueue(ahw->mailbox->work_q);
808 int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *adapter,
809 struct qlcnic_cmd_args *cmd)
811 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
812 struct qlcnic_hardware_context *ahw = adapter->ahw;
813 int cmd_type, err, opcode;
814 unsigned long timeout;
819 opcode = LSW(cmd->req.arg[0]);
820 cmd_type = cmd->type;
821 err = mbx->ops->enqueue_cmd(adapter, cmd, &timeout);
823 dev_err(&adapter->pdev->dev,
824 "%s: Mailbox not available, cmd_op=0x%x, cmd_context=0x%x, pci_func=0x%x, op_mode=0x%x\n",
825 __func__, opcode, cmd->type, ahw->pci_func,
831 case QLC_83XX_MBX_CMD_WAIT:
832 if (!wait_for_completion_timeout(&cmd->completion, timeout)) {
833 dev_err(&adapter->pdev->dev,
834 "%s: Mailbox command timed out, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
835 __func__, opcode, cmd_type, ahw->pci_func,
837 flush_workqueue(mbx->work_q);
840 case QLC_83XX_MBX_CMD_NO_WAIT:
842 case QLC_83XX_MBX_CMD_BUSY_WAIT:
843 qlcnic_83xx_poll_for_mbx_completion(adapter, cmd);
846 dev_err(&adapter->pdev->dev,
847 "%s: Invalid mailbox command, cmd_op=0x%x, cmd_type=0x%x, pci_func=0x%x, op_mode=0x%x\n",
848 __func__, opcode, cmd_type, ahw->pci_func,
850 qlcnic_83xx_detach_mailbox_work(adapter);
853 return cmd->rsp_opcode;
856 int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
857 struct qlcnic_adapter *adapter, u32 type)
861 const struct qlcnic_mailbox_metadata *mbx_tbl;
863 memset(mbx, 0, sizeof(struct qlcnic_cmd_args));
864 mbx_tbl = qlcnic_83xx_mbx_tbl;
865 size = ARRAY_SIZE(qlcnic_83xx_mbx_tbl);
866 for (i = 0; i < size; i++) {
867 if (type == mbx_tbl[i].cmd) {
868 mbx->op_type = QLC_83XX_FW_MBX_CMD;
869 mbx->req.num = mbx_tbl[i].in_args;
870 mbx->rsp.num = mbx_tbl[i].out_args;
871 mbx->req.arg = kcalloc(mbx->req.num, sizeof(u32),
875 mbx->rsp.arg = kcalloc(mbx->rsp.num, sizeof(u32),
882 memset(mbx->req.arg, 0, sizeof(u32) * mbx->req.num);
883 memset(mbx->rsp.arg, 0, sizeof(u32) * mbx->rsp.num);
884 temp = adapter->ahw->fw_hal_version << 29;
885 mbx->req.arg[0] = (type | (mbx->req.num << 16) | temp);
891 dev_err(&adapter->pdev->dev, "%s: Invalid mailbox command opcode 0x%x\n",
896 void qlcnic_83xx_idc_aen_work(struct work_struct *work)
898 struct qlcnic_adapter *adapter;
899 struct qlcnic_cmd_args cmd;
902 adapter = container_of(work, struct qlcnic_adapter, idc_aen_work.work);
903 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_IDC_ACK);
907 for (i = 1; i < QLC_83XX_MBX_AEN_CNT; i++)
908 cmd.req.arg[i] = adapter->ahw->mbox_aen[i];
910 err = qlcnic_issue_cmd(adapter, &cmd);
912 dev_info(&adapter->pdev->dev,
913 "%s: Mailbox IDC ACK failed.\n", __func__);
914 qlcnic_free_mbx_args(&cmd);
917 static void qlcnic_83xx_handle_idc_comp_aen(struct qlcnic_adapter *adapter,
920 dev_dbg(&adapter->pdev->dev, "Completion AEN:0x%x.\n",
921 QLCNIC_MBX_RSP(data[0]));
922 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status);
926 static void __qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
928 struct qlcnic_hardware_context *ahw = adapter->ahw;
929 u32 event[QLC_83XX_MBX_AEN_CNT];
932 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
933 event[i] = readl(QLCNIC_MBX_FW(ahw, i));
935 switch (QLCNIC_MBX_RSP(event[0])) {
937 case QLCNIC_MBX_LINK_EVENT:
938 qlcnic_83xx_handle_link_aen(adapter, event);
940 case QLCNIC_MBX_COMP_EVENT:
941 qlcnic_83xx_handle_idc_comp_aen(adapter, event);
943 case QLCNIC_MBX_REQUEST_EVENT:
944 for (i = 0; i < QLC_83XX_MBX_AEN_CNT; i++)
945 adapter->ahw->mbox_aen[i] = QLCNIC_MBX_RSP(event[i]);
946 queue_delayed_work(adapter->qlcnic_wq,
947 &adapter->idc_aen_work, 0);
949 case QLCNIC_MBX_TIME_EXTEND_EVENT:
950 ahw->extend_lb_time = event[1] >> 8 & 0xf;
952 case QLCNIC_MBX_BC_EVENT:
953 qlcnic_sriov_handle_bc_event(adapter, event[1]);
955 case QLCNIC_MBX_SFP_INSERT_EVENT:
956 dev_info(&adapter->pdev->dev, "SFP+ Insert AEN:0x%x.\n",
957 QLCNIC_MBX_RSP(event[0]));
959 case QLCNIC_MBX_SFP_REMOVE_EVENT:
960 dev_info(&adapter->pdev->dev, "SFP Removed AEN:0x%x.\n",
961 QLCNIC_MBX_RSP(event[0]));
963 case QLCNIC_MBX_DCBX_CONFIG_CHANGE_EVENT:
964 qlcnic_dcb_aen_handler(adapter->dcb, (void *)&event[1]);
967 dev_dbg(&adapter->pdev->dev, "Unsupported AEN:0x%x.\n",
968 QLCNIC_MBX_RSP(event[0]));
972 QLCWRX(ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
975 static void qlcnic_83xx_process_aen(struct qlcnic_adapter *adapter)
977 u32 resp, event, rsp_status = QLC_83XX_MBX_RESPONSE_ARRIVED;
978 struct qlcnic_hardware_context *ahw = adapter->ahw;
979 struct qlcnic_mailbox *mbx = ahw->mailbox;
982 spin_lock_irqsave(&mbx->aen_lock, flags);
983 resp = QLCRDX(ahw, QLCNIC_FW_MBX_CTRL);
984 if (resp & QLCNIC_SET_OWNER) {
985 event = readl(QLCNIC_MBX_FW(ahw, 0));
986 if (event & QLCNIC_MBX_ASYNC_EVENT) {
987 __qlcnic_83xx_process_aen(adapter);
989 if (atomic_read(&mbx->rsp_status) != rsp_status)
990 qlcnic_83xx_notify_mbx_response(mbx);
993 spin_unlock_irqrestore(&mbx->aen_lock, flags);
996 static void qlcnic_83xx_mbx_poll_work(struct work_struct *work)
998 struct qlcnic_adapter *adapter;
1000 adapter = container_of(work, struct qlcnic_adapter, mbx_poll_work.work);
1002 if (!test_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1005 qlcnic_83xx_process_aen(adapter);
1006 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work,
1010 void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *adapter)
1012 if (test_and_set_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1015 INIT_DELAYED_WORK(&adapter->mbx_poll_work, qlcnic_83xx_mbx_poll_work);
1016 queue_delayed_work(adapter->qlcnic_wq, &adapter->mbx_poll_work, 0);
1019 void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *adapter)
1021 if (!test_and_clear_bit(__QLCNIC_MBX_POLL_ENABLE, &adapter->state))
1023 cancel_delayed_work_sync(&adapter->mbx_poll_work);
1026 static int qlcnic_83xx_add_rings(struct qlcnic_adapter *adapter)
1028 int index, i, err, sds_mbx_size;
1029 u32 *buf, intrpt_id, intr_mask;
1032 struct qlcnic_cmd_args cmd;
1033 struct qlcnic_host_sds_ring *sds;
1034 struct qlcnic_sds_mbx sds_mbx;
1035 struct qlcnic_add_rings_mbx_out *mbx_out;
1036 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1037 struct qlcnic_hardware_context *ahw = adapter->ahw;
1039 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1040 context_id = recv_ctx->context_id;
1041 num_sds = adapter->drv_sds_rings - QLCNIC_MAX_SDS_RINGS;
1042 ahw->hw_ops->alloc_mbx_args(&cmd, adapter,
1043 QLCNIC_CMD_ADD_RCV_RINGS);
1044 cmd.req.arg[1] = 0 | (num_sds << 8) | (context_id << 16);
1046 /* set up status rings, mbx 2-81 */
1048 for (i = 8; i < adapter->drv_sds_rings; i++) {
1049 memset(&sds_mbx, 0, sds_mbx_size);
1050 sds = &recv_ctx->sds_rings[i];
1052 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1053 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1054 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1055 sds_mbx.sds_ring_size = sds->num_desc;
1057 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1058 intrpt_id = ahw->intr_tbl[i].id;
1060 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1062 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1063 sds_mbx.intrpt_id = intrpt_id;
1065 sds_mbx.intrpt_id = 0xffff;
1066 sds_mbx.intrpt_val = 0;
1067 buf = &cmd.req.arg[index];
1068 memcpy(buf, &sds_mbx, sds_mbx_size);
1069 index += sds_mbx_size / sizeof(u32);
1072 /* send the mailbox command */
1073 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1075 dev_err(&adapter->pdev->dev,
1076 "Failed to add rings %d\n", err);
1080 mbx_out = (struct qlcnic_add_rings_mbx_out *)&cmd.rsp.arg[1];
1082 /* status descriptor ring */
1083 for (i = 8; i < adapter->drv_sds_rings; i++) {
1084 sds = &recv_ctx->sds_rings[i];
1085 sds->crb_sts_consumer = ahw->pci_base0 +
1086 mbx_out->host_csmr[index];
1087 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1088 intr_mask = ahw->intr_tbl[i].src;
1090 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1092 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1096 qlcnic_free_mbx_args(&cmd);
1100 void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *adapter)
1104 struct qlcnic_cmd_args cmd;
1105 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1107 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_RX_CTX))
1110 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1111 cmd.req.arg[0] |= (0x3 << 29);
1113 if (qlcnic_sriov_pf_check(adapter))
1114 qlcnic_pf_set_interface_id_del_rx_ctx(adapter, &temp);
1116 cmd.req.arg[1] = recv_ctx->context_id | temp;
1117 err = qlcnic_issue_cmd(adapter, &cmd);
1119 dev_err(&adapter->pdev->dev,
1120 "Failed to destroy rx ctx in firmware\n");
1122 recv_ctx->state = QLCNIC_HOST_CTX_STATE_FREED;
1123 qlcnic_free_mbx_args(&cmd);
1126 int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *adapter)
1128 int i, err, index, sds_mbx_size, rds_mbx_size;
1129 u8 num_sds, num_rds;
1130 u32 *buf, intrpt_id, intr_mask, cap = 0;
1131 struct qlcnic_host_sds_ring *sds;
1132 struct qlcnic_host_rds_ring *rds;
1133 struct qlcnic_sds_mbx sds_mbx;
1134 struct qlcnic_rds_mbx rds_mbx;
1135 struct qlcnic_cmd_args cmd;
1136 struct qlcnic_rcv_mbx_out *mbx_out;
1137 struct qlcnic_recv_context *recv_ctx = adapter->recv_ctx;
1138 struct qlcnic_hardware_context *ahw = adapter->ahw;
1139 num_rds = adapter->max_rds_rings;
1141 if (adapter->drv_sds_rings <= QLCNIC_MAX_SDS_RINGS)
1142 num_sds = adapter->drv_sds_rings;
1144 num_sds = QLCNIC_MAX_SDS_RINGS;
1146 sds_mbx_size = sizeof(struct qlcnic_sds_mbx);
1147 rds_mbx_size = sizeof(struct qlcnic_rds_mbx);
1148 cap = QLCNIC_CAP0_LEGACY_CONTEXT;
1150 if (adapter->flags & QLCNIC_FW_LRO_MSS_CAP)
1151 cap |= QLC_83XX_FW_CAP_LRO_MSS;
1153 /* set mailbox hdr and capabilities */
1154 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1155 QLCNIC_CMD_CREATE_RX_CTX);
1159 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1160 cmd.req.arg[0] |= (0x3 << 29);
1162 cmd.req.arg[1] = cap;
1163 cmd.req.arg[5] = 1 | (num_rds << 5) | (num_sds << 8) |
1164 (QLC_83XX_HOST_RDS_MODE_UNIQUE << 16);
1166 if (qlcnic_sriov_pf_check(adapter))
1167 qlcnic_pf_set_interface_id_create_rx_ctx(adapter,
1169 /* set up status rings, mbx 8-57/87 */
1170 index = QLC_83XX_HOST_SDS_MBX_IDX;
1171 for (i = 0; i < num_sds; i++) {
1172 memset(&sds_mbx, 0, sds_mbx_size);
1173 sds = &recv_ctx->sds_rings[i];
1175 memset(sds->desc_head, 0, STATUS_DESC_RINGSIZE(sds));
1176 sds_mbx.phy_addr_low = LSD(sds->phys_addr);
1177 sds_mbx.phy_addr_high = MSD(sds->phys_addr);
1178 sds_mbx.sds_ring_size = sds->num_desc;
1179 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1180 intrpt_id = ahw->intr_tbl[i].id;
1182 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1183 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1184 sds_mbx.intrpt_id = intrpt_id;
1186 sds_mbx.intrpt_id = 0xffff;
1187 sds_mbx.intrpt_val = 0;
1188 buf = &cmd.req.arg[index];
1189 memcpy(buf, &sds_mbx, sds_mbx_size);
1190 index += sds_mbx_size / sizeof(u32);
1192 /* set up receive rings, mbx 88-111/135 */
1193 index = QLCNIC_HOST_RDS_MBX_IDX;
1194 rds = &recv_ctx->rds_rings[0];
1196 memset(&rds_mbx, 0, rds_mbx_size);
1197 rds_mbx.phy_addr_reg_low = LSD(rds->phys_addr);
1198 rds_mbx.phy_addr_reg_high = MSD(rds->phys_addr);
1199 rds_mbx.reg_ring_sz = rds->dma_size;
1200 rds_mbx.reg_ring_len = rds->num_desc;
1202 rds = &recv_ctx->rds_rings[1];
1204 rds_mbx.phy_addr_jmb_low = LSD(rds->phys_addr);
1205 rds_mbx.phy_addr_jmb_high = MSD(rds->phys_addr);
1206 rds_mbx.jmb_ring_sz = rds->dma_size;
1207 rds_mbx.jmb_ring_len = rds->num_desc;
1208 buf = &cmd.req.arg[index];
1209 memcpy(buf, &rds_mbx, rds_mbx_size);
1211 /* send the mailbox command */
1212 err = ahw->hw_ops->mbx_cmd(adapter, &cmd);
1214 dev_err(&adapter->pdev->dev,
1215 "Failed to create Rx ctx in firmware%d\n", err);
1218 mbx_out = (struct qlcnic_rcv_mbx_out *)&cmd.rsp.arg[1];
1219 recv_ctx->context_id = mbx_out->ctx_id;
1220 recv_ctx->state = mbx_out->state;
1221 recv_ctx->virt_port = mbx_out->vport_id;
1222 dev_info(&adapter->pdev->dev, "Rx Context[%d] Created, state:0x%x\n",
1223 recv_ctx->context_id, recv_ctx->state);
1224 /* Receive descriptor ring */
1226 rds = &recv_ctx->rds_rings[0];
1227 rds->crb_rcv_producer = ahw->pci_base0 +
1228 mbx_out->host_prod[0].reg_buf;
1230 rds = &recv_ctx->rds_rings[1];
1231 rds->crb_rcv_producer = ahw->pci_base0 +
1232 mbx_out->host_prod[0].jmb_buf;
1233 /* status descriptor ring */
1234 for (i = 0; i < num_sds; i++) {
1235 sds = &recv_ctx->sds_rings[i];
1236 sds->crb_sts_consumer = ahw->pci_base0 +
1237 mbx_out->host_csmr[i];
1238 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1239 intr_mask = ahw->intr_tbl[i].src;
1241 intr_mask = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
1242 sds->crb_intr_mask = ahw->pci_base0 + intr_mask;
1245 if (adapter->drv_sds_rings > QLCNIC_MAX_SDS_RINGS)
1246 err = qlcnic_83xx_add_rings(adapter);
1248 qlcnic_free_mbx_args(&cmd);
1252 void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *adapter,
1253 struct qlcnic_host_tx_ring *tx_ring)
1255 struct qlcnic_cmd_args cmd;
1258 if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_DESTROY_TX_CTX))
1261 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1262 cmd.req.arg[0] |= (0x3 << 29);
1264 if (qlcnic_sriov_pf_check(adapter))
1265 qlcnic_pf_set_interface_id_del_tx_ctx(adapter, &temp);
1267 cmd.req.arg[1] = tx_ring->ctx_id | temp;
1268 if (qlcnic_issue_cmd(adapter, &cmd))
1269 dev_err(&adapter->pdev->dev,
1270 "Failed to destroy tx ctx in firmware\n");
1271 qlcnic_free_mbx_args(&cmd);
1274 int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *adapter,
1275 struct qlcnic_host_tx_ring *tx, int ring)
1279 u32 *buf, intr_mask, temp = 0;
1280 struct qlcnic_cmd_args cmd;
1281 struct qlcnic_tx_mbx mbx;
1282 struct qlcnic_tx_mbx_out *mbx_out;
1283 struct qlcnic_hardware_context *ahw = adapter->ahw;
1286 /* Reset host resources */
1288 tx->sw_consumer = 0;
1289 *(tx->hw_consumer) = 0;
1291 memset(&mbx, 0, sizeof(struct qlcnic_tx_mbx));
1293 /* setup mailbox inbox registerss */
1294 mbx.phys_addr_low = LSD(tx->phys_addr);
1295 mbx.phys_addr_high = MSD(tx->phys_addr);
1296 mbx.cnsmr_index_low = LSD(tx->hw_cons_phys_addr);
1297 mbx.cnsmr_index_high = MSD(tx->hw_cons_phys_addr);
1298 mbx.size = tx->num_desc;
1299 if (adapter->flags & QLCNIC_MSIX_ENABLED) {
1300 if (!(adapter->flags & QLCNIC_TX_INTR_SHARED))
1301 msix_vector = adapter->drv_sds_rings + ring;
1303 msix_vector = adapter->drv_sds_rings - 1;
1304 msix_id = ahw->intr_tbl[msix_vector].id;
1306 msix_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
1309 if (adapter->ahw->diag_test != QLCNIC_LOOPBACK_TEST)
1310 mbx.intr_id = msix_id;
1312 mbx.intr_id = 0xffff;
1315 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CREATE_TX_CTX);
1319 if (qlcnic_sriov_pf_check(adapter) || qlcnic_sriov_vf_check(adapter))
1320 cmd.req.arg[0] |= (0x3 << 29);
1322 if (qlcnic_sriov_pf_check(adapter))
1323 qlcnic_pf_set_interface_id_create_tx_ctx(adapter, &temp);
1325 cmd.req.arg[1] = QLCNIC_CAP0_LEGACY_CONTEXT;
1326 cmd.req.arg[5] = QLCNIC_SINGLE_RING | temp;
1328 buf = &cmd.req.arg[6];
1329 memcpy(buf, &mbx, sizeof(struct qlcnic_tx_mbx));
1330 /* send the mailbox command*/
1331 err = qlcnic_issue_cmd(adapter, &cmd);
1333 netdev_err(adapter->netdev,
1334 "Failed to create Tx ctx in firmware 0x%x\n", err);
1337 mbx_out = (struct qlcnic_tx_mbx_out *)&cmd.rsp.arg[2];
1338 tx->crb_cmd_producer = ahw->pci_base0 + mbx_out->host_prod;
1339 tx->ctx_id = mbx_out->ctx_id;
1340 if ((adapter->flags & QLCNIC_MSIX_ENABLED) &&
1341 !(adapter->flags & QLCNIC_TX_INTR_SHARED)) {
1342 intr_mask = ahw->intr_tbl[adapter->drv_sds_rings + ring].src;
1343 tx->crb_intr_mask = ahw->pci_base0 + intr_mask;
1345 netdev_info(adapter->netdev,
1346 "Tx Context[0x%x] Created, state:0x%x\n",
1347 tx->ctx_id, mbx_out->state);
1349 qlcnic_free_mbx_args(&cmd);
1353 static int qlcnic_83xx_diag_alloc_res(struct net_device *netdev, int test,
1356 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1357 struct qlcnic_host_sds_ring *sds_ring;
1358 struct qlcnic_host_rds_ring *rds_ring;
1359 u16 adapter_state = adapter->is_up;
1363 netif_device_detach(netdev);
1365 if (netif_running(netdev))
1366 __qlcnic_down(adapter, netdev);
1368 qlcnic_detach(adapter);
1370 adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
1371 adapter->ahw->diag_test = test;
1372 adapter->ahw->linkup = 0;
1374 ret = qlcnic_attach(adapter);
1376 netif_device_attach(netdev);
1380 ret = qlcnic_fw_create_ctx(adapter);
1382 qlcnic_detach(adapter);
1383 if (adapter_state == QLCNIC_ADAPTER_UP_MAGIC) {
1384 adapter->drv_sds_rings = num_sds_ring;
1385 qlcnic_attach(adapter);
1387 netif_device_attach(netdev);
1391 for (ring = 0; ring < adapter->max_rds_rings; ring++) {
1392 rds_ring = &adapter->recv_ctx->rds_rings[ring];
1393 qlcnic_post_rx_buffers(adapter, rds_ring, ring);
1396 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1397 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1398 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1399 qlcnic_enable_sds_intr(adapter, sds_ring);
1403 if (adapter->ahw->diag_test == QLCNIC_LOOPBACK_TEST) {
1404 adapter->ahw->loopback_state = 0;
1405 adapter->ahw->hw_ops->setup_link_event(adapter, 1);
1408 set_bit(__QLCNIC_DEV_UP, &adapter->state);
1412 static void qlcnic_83xx_diag_free_res(struct net_device *netdev,
1415 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1416 struct qlcnic_host_sds_ring *sds_ring;
1419 clear_bit(__QLCNIC_DEV_UP, &adapter->state);
1420 if (adapter->ahw->diag_test == QLCNIC_INTERRUPT_TEST) {
1421 for (ring = 0; ring < adapter->drv_sds_rings; ring++) {
1422 sds_ring = &adapter->recv_ctx->sds_rings[ring];
1423 if (adapter->flags & QLCNIC_MSIX_ENABLED)
1424 qlcnic_disable_sds_intr(adapter, sds_ring);
1428 qlcnic_fw_destroy_ctx(adapter);
1429 qlcnic_detach(adapter);
1431 adapter->ahw->diag_test = 0;
1432 adapter->drv_sds_rings = drv_sds_rings;
1434 if (qlcnic_attach(adapter))
1437 if (netif_running(netdev))
1438 __qlcnic_up(adapter, netdev);
1441 netif_device_attach(netdev);
1444 static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *adapter)
1446 struct qlcnic_hardware_context *ahw = adapter->ahw;
1447 struct qlcnic_cmd_args cmd;
1451 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LED_CONFIG);
1453 err = qlcnic_issue_cmd(adapter, &cmd);
1455 beacon_state = cmd.rsp.arg[4];
1456 if (beacon_state == QLCNIC_BEACON_DISABLE)
1457 ahw->beacon_state = QLC_83XX_BEACON_OFF;
1458 else if (beacon_state == QLC_83XX_ENABLE_BEACON)
1459 ahw->beacon_state = QLC_83XX_BEACON_ON;
1462 netdev_err(adapter->netdev, "Get beacon state failed, err=%d\n",
1466 qlcnic_free_mbx_args(&cmd);
1471 int qlcnic_83xx_config_led(struct qlcnic_adapter *adapter, u32 state,
1474 struct qlcnic_cmd_args cmd;
1479 /* Get LED configuration */
1480 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1481 QLCNIC_CMD_GET_LED_CONFIG);
1485 status = qlcnic_issue_cmd(adapter, &cmd);
1487 dev_err(&adapter->pdev->dev,
1488 "Get led config failed.\n");
1491 for (i = 0; i < 4; i++)
1492 adapter->ahw->mbox_reg[i] = cmd.rsp.arg[i+1];
1494 qlcnic_free_mbx_args(&cmd);
1495 /* Set LED Configuration */
1496 mbx_in = (LSW(QLC_83XX_LED_CONFIG) << 16) |
1497 LSW(QLC_83XX_LED_CONFIG);
1498 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1499 QLCNIC_CMD_SET_LED_CONFIG);
1503 cmd.req.arg[1] = mbx_in;
1504 cmd.req.arg[2] = mbx_in;
1505 cmd.req.arg[3] = mbx_in;
1507 cmd.req.arg[4] = QLC_83XX_ENABLE_BEACON;
1508 status = qlcnic_issue_cmd(adapter, &cmd);
1510 dev_err(&adapter->pdev->dev,
1511 "Set led config failed.\n");
1514 qlcnic_free_mbx_args(&cmd);
1518 /* Restoring default LED configuration */
1519 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1520 QLCNIC_CMD_SET_LED_CONFIG);
1524 cmd.req.arg[1] = adapter->ahw->mbox_reg[0];
1525 cmd.req.arg[2] = adapter->ahw->mbox_reg[1];
1526 cmd.req.arg[3] = adapter->ahw->mbox_reg[2];
1528 cmd.req.arg[4] = adapter->ahw->mbox_reg[3];
1529 status = qlcnic_issue_cmd(adapter, &cmd);
1531 dev_err(&adapter->pdev->dev,
1532 "Restoring led config failed.\n");
1533 qlcnic_free_mbx_args(&cmd);
1538 int qlcnic_83xx_set_led(struct net_device *netdev,
1539 enum ethtool_phys_id_state state)
1541 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1542 int err = -EIO, active = 1;
1544 if (adapter->ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1546 "LED test is not supported in non-privileged mode\n");
1551 case ETHTOOL_ID_ACTIVE:
1552 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
1555 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1558 err = qlcnic_83xx_config_led(adapter, active, 0);
1560 netdev_err(netdev, "Failed to set LED blink state\n");
1562 case ETHTOOL_ID_INACTIVE:
1565 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
1568 err = qlcnic_83xx_config_led(adapter, active, 0);
1570 netdev_err(netdev, "Failed to reset LED blink state\n");
1578 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
1583 void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *adapter, int enable)
1585 struct qlcnic_cmd_args cmd;
1588 if (qlcnic_sriov_vf_check(adapter))
1592 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1593 QLCNIC_CMD_INIT_NIC_FUNC);
1595 status = qlcnic_alloc_mbx_args(&cmd, adapter,
1596 QLCNIC_CMD_STOP_NIC_FUNC);
1601 cmd.req.arg[1] = QLC_REGISTER_LB_IDC | QLC_INIT_FW_RESOURCES;
1604 cmd.req.arg[1] |= QLC_REGISTER_DCB_AEN;
1606 status = qlcnic_issue_cmd(adapter, &cmd);
1608 dev_err(&adapter->pdev->dev,
1609 "Failed to %s in NIC IDC function event.\n",
1610 (enable ? "register" : "unregister"));
1612 qlcnic_free_mbx_args(&cmd);
1615 static int qlcnic_83xx_set_port_config(struct qlcnic_adapter *adapter)
1617 struct qlcnic_cmd_args cmd;
1620 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_PORT_CONFIG);
1624 cmd.req.arg[1] = adapter->ahw->port_config;
1625 err = qlcnic_issue_cmd(adapter, &cmd);
1627 dev_info(&adapter->pdev->dev, "Set Port Config failed.\n");
1628 qlcnic_free_mbx_args(&cmd);
1632 static int qlcnic_83xx_get_port_config(struct qlcnic_adapter *adapter)
1634 struct qlcnic_cmd_args cmd;
1637 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PORT_CONFIG);
1641 err = qlcnic_issue_cmd(adapter, &cmd);
1643 dev_info(&adapter->pdev->dev, "Get Port config failed\n");
1645 adapter->ahw->port_config = cmd.rsp.arg[1];
1646 qlcnic_free_mbx_args(&cmd);
1650 int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *adapter, int enable)
1654 struct qlcnic_cmd_args cmd;
1656 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_EVENT);
1660 temp = adapter->recv_ctx->context_id << 16;
1661 cmd.req.arg[1] = (enable ? 1 : 0) | BIT_8 | temp;
1662 err = qlcnic_issue_cmd(adapter, &cmd);
1664 dev_info(&adapter->pdev->dev,
1665 "Setup linkevent mailbox failed\n");
1666 qlcnic_free_mbx_args(&cmd);
1670 static void qlcnic_83xx_set_interface_id_promisc(struct qlcnic_adapter *adapter,
1673 if (qlcnic_sriov_pf_check(adapter)) {
1674 qlcnic_alloc_lb_filters_mem(adapter);
1675 qlcnic_pf_set_interface_id_promisc(adapter, interface_id);
1676 adapter->rx_mac_learn = true;
1678 if (!qlcnic_sriov_vf_check(adapter))
1679 *interface_id = adapter->recv_ctx->context_id << 16;
1683 int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
1685 struct qlcnic_cmd_args *cmd = NULL;
1689 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1692 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
1696 err = qlcnic_alloc_mbx_args(cmd, adapter,
1697 QLCNIC_CMD_CONFIGURE_MAC_RX_MODE);
1701 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
1702 qlcnic_83xx_set_interface_id_promisc(adapter, &temp);
1704 if (qlcnic_84xx_check(adapter) && qlcnic_sriov_pf_check(adapter))
1705 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1707 cmd->req.arg[1] = mode | temp;
1708 err = qlcnic_issue_cmd(adapter, cmd);
1712 qlcnic_free_mbx_args(cmd);
1719 int qlcnic_83xx_loopback_test(struct net_device *netdev, u8 mode)
1721 struct qlcnic_adapter *adapter = netdev_priv(netdev);
1722 struct qlcnic_hardware_context *ahw = adapter->ahw;
1723 u8 drv_sds_rings = adapter->drv_sds_rings;
1724 u8 drv_tx_rings = adapter->drv_tx_rings;
1725 int ret = 0, loop = 0;
1727 if (ahw->op_mode == QLCNIC_NON_PRIV_FUNC) {
1729 "Loopback test not supported in non privileged mode\n");
1733 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1734 netdev_info(netdev, "Device is resetting\n");
1738 if (qlcnic_get_diag_lock(adapter)) {
1739 netdev_info(netdev, "Device is in diagnostics mode\n");
1743 netdev_info(netdev, "%s loopback test in progress\n",
1744 mode == QLCNIC_ILB_MODE ? "internal" : "external");
1746 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_LOOPBACK_TEST,
1749 goto fail_diag_alloc;
1751 ret = qlcnic_83xx_set_lb_mode(adapter, mode);
1755 /* Poll for link up event before running traffic */
1757 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1759 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1761 "Device is resetting, free LB test resources\n");
1765 if (loop++ > QLC_83XX_LB_WAIT_COUNT) {
1767 "Firmware didn't sent link up event to loopback request\n");
1769 qlcnic_83xx_clear_lb_mode(adapter, mode);
1772 } while ((adapter->ahw->linkup && ahw->has_link_events) != 1);
1774 ret = qlcnic_do_lb_test(adapter, mode);
1776 qlcnic_83xx_clear_lb_mode(adapter, mode);
1779 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
1782 adapter->drv_sds_rings = drv_sds_rings;
1783 adapter->drv_tx_rings = drv_tx_rings;
1784 qlcnic_release_diag_lock(adapter);
1788 static void qlcnic_extend_lb_idc_cmpltn_wait(struct qlcnic_adapter *adapter,
1789 u32 *max_wait_count)
1791 struct qlcnic_hardware_context *ahw = adapter->ahw;
1794 netdev_info(adapter->netdev, "Received loopback IDC time extend event for 0x%x seconds\n",
1795 ahw->extend_lb_time);
1796 temp = ahw->extend_lb_time * 1000;
1797 *max_wait_count += temp / QLC_83XX_LB_MSLEEP_COUNT;
1798 ahw->extend_lb_time = 0;
1801 static int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1803 struct qlcnic_hardware_context *ahw = adapter->ahw;
1804 struct net_device *netdev = adapter->netdev;
1805 u32 config, max_wait_count;
1806 int status = 0, loop = 0;
1808 ahw->extend_lb_time = 0;
1809 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1810 status = qlcnic_83xx_get_port_config(adapter);
1814 config = ahw->port_config;
1816 /* Check if port is already in loopback mode */
1817 if ((config & QLC_83XX_CFG_LOOPBACK_HSS) ||
1818 (config & QLC_83XX_CFG_LOOPBACK_EXT)) {
1820 "Port already in Loopback mode.\n");
1821 return -EINPROGRESS;
1824 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1826 if (mode == QLCNIC_ILB_MODE)
1827 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_HSS;
1828 if (mode == QLCNIC_ELB_MODE)
1829 ahw->port_config |= QLC_83XX_CFG_LOOPBACK_EXT;
1831 status = qlcnic_83xx_set_port_config(adapter);
1834 "Failed to Set Loopback Mode = 0x%x.\n",
1836 ahw->port_config = config;
1837 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1841 /* Wait for Link and IDC Completion AEN */
1843 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1845 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1847 "Device is resetting, free LB test resources\n");
1848 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1852 if (ahw->extend_lb_time)
1853 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1856 if (loop++ > max_wait_count) {
1857 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1859 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1860 qlcnic_83xx_clear_lb_mode(adapter, mode);
1863 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1865 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1870 static int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
1872 struct qlcnic_hardware_context *ahw = adapter->ahw;
1873 u32 config = ahw->port_config, max_wait_count;
1874 struct net_device *netdev = adapter->netdev;
1875 int status = 0, loop = 0;
1877 ahw->extend_lb_time = 0;
1878 max_wait_count = QLC_83XX_LB_WAIT_COUNT;
1879 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1880 if (mode == QLCNIC_ILB_MODE)
1881 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_HSS;
1882 if (mode == QLCNIC_ELB_MODE)
1883 ahw->port_config &= ~QLC_83XX_CFG_LOOPBACK_EXT;
1885 status = qlcnic_83xx_set_port_config(adapter);
1888 "Failed to Clear Loopback Mode = 0x%x.\n",
1890 ahw->port_config = config;
1891 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1895 /* Wait for Link and IDC Completion AEN */
1897 msleep(QLC_83XX_LB_MSLEEP_COUNT);
1899 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
1901 "Device is resetting, free LB test resources\n");
1902 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1906 if (ahw->extend_lb_time)
1907 qlcnic_extend_lb_idc_cmpltn_wait(adapter,
1910 if (loop++ > max_wait_count) {
1911 netdev_err(netdev, "%s: Did not receive loopback IDC completion AEN\n",
1913 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status);
1916 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status));
1918 qlcnic_sre_macaddr_change(adapter, adapter->mac_addr, 0,
1923 static void qlcnic_83xx_set_interface_id_ipaddr(struct qlcnic_adapter *adapter,
1926 if (qlcnic_sriov_pf_check(adapter)) {
1927 qlcnic_pf_set_interface_id_ipaddr(adapter, interface_id);
1929 if (!qlcnic_sriov_vf_check(adapter))
1930 *interface_id = adapter->recv_ctx->context_id << 16;
1934 void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip,
1938 u32 temp = 0, temp_ip;
1939 struct qlcnic_cmd_args cmd;
1941 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1942 QLCNIC_CMD_CONFIGURE_IP_ADDR);
1946 qlcnic_83xx_set_interface_id_ipaddr(adapter, &temp);
1948 if (mode == QLCNIC_IP_UP)
1949 cmd.req.arg[1] = 1 | temp;
1951 cmd.req.arg[1] = 2 | temp;
1954 * Adapter needs IP address in network byte order.
1955 * But hardware mailbox registers go through writel(), hence IP address
1956 * gets swapped on big endian architecture.
1957 * To negate swapping of writel() on big endian architecture
1958 * use swab32(value).
1961 temp_ip = swab32(ntohl(ip));
1962 memcpy(&cmd.req.arg[2], &temp_ip, sizeof(u32));
1963 err = qlcnic_issue_cmd(adapter, &cmd);
1964 if (err != QLCNIC_RCODE_SUCCESS)
1965 dev_err(&adapter->netdev->dev,
1966 "could not notify %s IP 0x%x request\n",
1967 (mode == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
1969 qlcnic_free_mbx_args(&cmd);
1972 int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *adapter, int mode)
1976 struct qlcnic_cmd_args cmd;
1979 lro_bit_mask = (mode ? (BIT_0 | BIT_1 | BIT_2 | BIT_3) : 0);
1981 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
1984 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_HW_LRO);
1988 temp = adapter->recv_ctx->context_id << 16;
1989 arg1 = lro_bit_mask | temp;
1990 cmd.req.arg[1] = arg1;
1992 err = qlcnic_issue_cmd(adapter, &cmd);
1994 dev_info(&adapter->pdev->dev, "LRO config failed\n");
1995 qlcnic_free_mbx_args(&cmd);
2000 int qlcnic_83xx_config_rss(struct qlcnic_adapter *adapter, int enable)
2004 struct qlcnic_cmd_args cmd;
2005 const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
2006 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
2007 0x255b0ec26d5a56daULL };
2009 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIGURE_RSS);
2015 * 5-4: hash_type_ipv4
2016 * 7-6: hash_type_ipv6
2018 * 9: use indirection table
2019 * 16-31: indirection table mask
2021 word = ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
2022 ((u32)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
2023 ((u32)(enable & 0x1) << 8) |
2025 cmd.req.arg[1] = (adapter->recv_ctx->context_id);
2026 cmd.req.arg[2] = word;
2027 memcpy(&cmd.req.arg[4], key, sizeof(key));
2029 err = qlcnic_issue_cmd(adapter, &cmd);
2032 dev_info(&adapter->pdev->dev, "RSS config failed\n");
2033 qlcnic_free_mbx_args(&cmd);
2039 static void qlcnic_83xx_set_interface_id_macaddr(struct qlcnic_adapter *adapter,
2042 if (qlcnic_sriov_pf_check(adapter)) {
2043 qlcnic_pf_set_interface_id_macaddr(adapter, interface_id);
2045 if (!qlcnic_sriov_vf_check(adapter))
2046 *interface_id = adapter->recv_ctx->context_id << 16;
2050 int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
2053 struct qlcnic_cmd_args *cmd = NULL;
2054 struct qlcnic_macvlan_mbx mv;
2058 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2061 cmd = kzalloc(sizeof(*cmd), GFP_ATOMIC);
2065 err = qlcnic_alloc_mbx_args(cmd, adapter, QLCNIC_CMD_CONFIG_MAC_VLAN);
2069 cmd->type = QLC_83XX_MBX_CMD_NO_WAIT;
2072 op = (op == QLCNIC_MAC_ADD || op == QLCNIC_MAC_VLAN_ADD) ?
2073 QLCNIC_MAC_VLAN_ADD : QLCNIC_MAC_VLAN_DEL;
2075 cmd->req.arg[1] = op | (1 << 8);
2076 qlcnic_83xx_set_interface_id_macaddr(adapter, &temp);
2077 cmd->req.arg[1] |= temp;
2079 mv.mac_addr0 = addr[0];
2080 mv.mac_addr1 = addr[1];
2081 mv.mac_addr2 = addr[2];
2082 mv.mac_addr3 = addr[3];
2083 mv.mac_addr4 = addr[4];
2084 mv.mac_addr5 = addr[5];
2085 buf = &cmd->req.arg[2];
2086 memcpy(buf, &mv, sizeof(struct qlcnic_macvlan_mbx));
2087 err = qlcnic_issue_cmd(adapter, cmd);
2091 qlcnic_free_mbx_args(cmd);
2097 void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *adapter, u64 *addr,
2101 memcpy(&mac, addr, ETH_ALEN);
2102 qlcnic_83xx_sre_macaddr_change(adapter, mac, vlan_id, QLCNIC_MAC_ADD);
2105 static void qlcnic_83xx_configure_mac(struct qlcnic_adapter *adapter, u8 *mac,
2106 u8 type, struct qlcnic_cmd_args *cmd)
2109 case QLCNIC_SET_STATION_MAC:
2110 case QLCNIC_SET_FAC_DEF_MAC:
2111 memcpy(&cmd->req.arg[2], mac, sizeof(u32));
2112 memcpy(&cmd->req.arg[3], &mac[4], sizeof(u16));
2115 cmd->req.arg[1] = type;
2118 int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *adapter, u8 *mac,
2122 struct qlcnic_cmd_args cmd;
2123 u32 mac_low, mac_high;
2126 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_MAC_ADDRESS);
2130 qlcnic_83xx_configure_mac(adapter, mac, QLCNIC_GET_CURRENT_MAC, &cmd);
2131 err = qlcnic_issue_cmd(adapter, &cmd);
2133 if (err == QLCNIC_RCODE_SUCCESS) {
2134 mac_low = cmd.rsp.arg[1];
2135 mac_high = cmd.rsp.arg[2];
2137 for (i = 0; i < 2; i++)
2138 mac[i] = (u8) (mac_high >> ((1 - i) * 8));
2139 for (i = 2; i < 6; i++)
2140 mac[i] = (u8) (mac_low >> ((5 - i) * 8));
2142 dev_err(&adapter->pdev->dev, "Failed to get mac address%d\n",
2146 qlcnic_free_mbx_args(&cmd);
2150 static int qlcnic_83xx_set_rx_intr_coal(struct qlcnic_adapter *adapter)
2152 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2153 struct qlcnic_cmd_args cmd;
2157 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2161 temp = adapter->recv_ctx->context_id;
2162 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_RX | temp << 16;
2163 temp = coal->rx_time_us;
2164 cmd.req.arg[2] = coal->rx_packets | temp << 16;
2165 cmd.req.arg[3] = coal->flag;
2167 err = qlcnic_issue_cmd(adapter, &cmd);
2168 if (err != QLCNIC_RCODE_SUCCESS)
2169 netdev_err(adapter->netdev,
2170 "failed to set interrupt coalescing parameters\n");
2172 qlcnic_free_mbx_args(&cmd);
2177 static int qlcnic_83xx_set_tx_intr_coal(struct qlcnic_adapter *adapter)
2179 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2180 struct qlcnic_cmd_args cmd;
2184 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTR_COAL);
2188 temp = adapter->tx_ring->ctx_id;
2189 cmd.req.arg[1] = QLCNIC_INTR_COAL_TYPE_TX | temp << 16;
2190 temp = coal->tx_time_us;
2191 cmd.req.arg[2] = coal->tx_packets | temp << 16;
2192 cmd.req.arg[3] = coal->flag;
2194 err = qlcnic_issue_cmd(adapter, &cmd);
2195 if (err != QLCNIC_RCODE_SUCCESS)
2196 netdev_err(adapter->netdev,
2197 "failed to set interrupt coalescing parameters\n");
2199 qlcnic_free_mbx_args(&cmd);
2204 int qlcnic_83xx_set_rx_tx_intr_coal(struct qlcnic_adapter *adapter)
2208 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2210 netdev_err(adapter->netdev,
2211 "failed to set Rx coalescing parameters\n");
2213 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2215 netdev_err(adapter->netdev,
2216 "failed to set Tx coalescing parameters\n");
2221 int qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *adapter,
2222 struct ethtool_coalesce *ethcoal)
2224 struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
2225 u32 rx_coalesce_usecs, rx_max_frames;
2226 u32 tx_coalesce_usecs, tx_max_frames;
2229 if (adapter->recv_ctx->state == QLCNIC_HOST_CTX_STATE_FREED)
2232 tx_coalesce_usecs = ethcoal->tx_coalesce_usecs;
2233 tx_max_frames = ethcoal->tx_max_coalesced_frames;
2234 rx_coalesce_usecs = ethcoal->rx_coalesce_usecs;
2235 rx_max_frames = ethcoal->rx_max_coalesced_frames;
2236 coal->flag = QLCNIC_INTR_DEFAULT;
2238 if ((coal->rx_time_us == rx_coalesce_usecs) &&
2239 (coal->rx_packets == rx_max_frames)) {
2240 coal->type = QLCNIC_INTR_COAL_TYPE_TX;
2241 coal->tx_time_us = tx_coalesce_usecs;
2242 coal->tx_packets = tx_max_frames;
2243 } else if ((coal->tx_time_us == tx_coalesce_usecs) &&
2244 (coal->tx_packets == tx_max_frames)) {
2245 coal->type = QLCNIC_INTR_COAL_TYPE_RX;
2246 coal->rx_time_us = rx_coalesce_usecs;
2247 coal->rx_packets = rx_max_frames;
2249 coal->type = QLCNIC_INTR_COAL_TYPE_RX_TX;
2250 coal->rx_time_us = rx_coalesce_usecs;
2251 coal->rx_packets = rx_max_frames;
2252 coal->tx_time_us = tx_coalesce_usecs;
2253 coal->tx_packets = tx_max_frames;
2256 switch (coal->type) {
2257 case QLCNIC_INTR_COAL_TYPE_RX:
2258 err = qlcnic_83xx_set_rx_intr_coal(adapter);
2260 case QLCNIC_INTR_COAL_TYPE_TX:
2261 err = qlcnic_83xx_set_tx_intr_coal(adapter);
2263 case QLCNIC_INTR_COAL_TYPE_RX_TX:
2264 err = qlcnic_83xx_set_rx_tx_intr_coal(adapter);
2268 netdev_err(adapter->netdev,
2269 "Invalid Interrupt coalescing type\n");
2276 static void qlcnic_83xx_handle_link_aen(struct qlcnic_adapter *adapter,
2279 struct qlcnic_hardware_context *ahw = adapter->ahw;
2280 u8 link_status, duplex;
2282 link_status = LSB(data[3]) & 1;
2284 ahw->link_speed = MSW(data[2]);
2285 duplex = LSB(MSW(data[3]));
2287 ahw->link_duplex = DUPLEX_FULL;
2289 ahw->link_duplex = DUPLEX_HALF;
2291 ahw->link_speed = SPEED_UNKNOWN;
2292 ahw->link_duplex = DUPLEX_UNKNOWN;
2295 ahw->link_autoneg = MSB(MSW(data[3]));
2296 ahw->module_type = MSB(LSW(data[3]));
2297 ahw->has_link_events = 1;
2298 ahw->lb_mode = data[4] & QLCNIC_LB_MODE_MASK;
2299 qlcnic_advert_link_change(adapter, link_status);
2302 static irqreturn_t qlcnic_83xx_handle_aen(int irq, void *data)
2304 struct qlcnic_adapter *adapter = data;
2305 struct qlcnic_mailbox *mbx;
2306 u32 mask, resp, event;
2307 unsigned long flags;
2309 mbx = adapter->ahw->mailbox;
2310 spin_lock_irqsave(&mbx->aen_lock, flags);
2311 resp = QLCRDX(adapter->ahw, QLCNIC_FW_MBX_CTRL);
2312 if (!(resp & QLCNIC_SET_OWNER))
2315 event = readl(QLCNIC_MBX_FW(adapter->ahw, 0));
2316 if (event & QLCNIC_MBX_ASYNC_EVENT)
2317 __qlcnic_83xx_process_aen(adapter);
2319 qlcnic_83xx_notify_mbx_response(mbx);
2322 mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
2323 writel(0, adapter->ahw->pci_base0 + mask);
2324 spin_unlock_irqrestore(&mbx->aen_lock, flags);
2328 int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *adapter,
2329 struct qlcnic_info *nic)
2332 struct qlcnic_cmd_args cmd;
2334 if (adapter->ahw->op_mode != QLCNIC_MGMT_FUNC) {
2335 dev_err(&adapter->pdev->dev,
2336 "%s: Error, invoked by non management func\n",
2341 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_SET_NIC_INFO);
2345 cmd.req.arg[1] = (nic->pci_func << 16);
2346 cmd.req.arg[2] = 0x1 << 16;
2347 cmd.req.arg[3] = nic->phys_port | (nic->switch_mode << 16);
2348 cmd.req.arg[4] = nic->capabilities;
2349 cmd.req.arg[5] = (nic->max_mac_filters & 0xFF) | ((nic->max_mtu) << 16);
2350 cmd.req.arg[6] = (nic->max_tx_ques) | ((nic->max_rx_ques) << 16);
2351 cmd.req.arg[7] = (nic->min_tx_bw) | ((nic->max_tx_bw) << 16);
2352 for (i = 8; i < 32; i++)
2355 err = qlcnic_issue_cmd(adapter, &cmd);
2357 if (err != QLCNIC_RCODE_SUCCESS) {
2358 dev_err(&adapter->pdev->dev, "Failed to set nic info%d\n",
2363 qlcnic_free_mbx_args(&cmd);
2368 int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *adapter,
2369 struct qlcnic_info *npar_info, u8 func_id)
2374 struct qlcnic_cmd_args cmd;
2375 struct qlcnic_hardware_context *ahw = adapter->ahw;
2377 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_NIC_INFO);
2381 if (func_id != ahw->pci_func) {
2382 temp = func_id << 16;
2383 cmd.req.arg[1] = op | BIT_31 | temp;
2385 cmd.req.arg[1] = ahw->pci_func << 16;
2387 err = qlcnic_issue_cmd(adapter, &cmd);
2389 dev_info(&adapter->pdev->dev,
2390 "Failed to get nic info %d\n", err);
2394 npar_info->op_type = cmd.rsp.arg[1];
2395 npar_info->pci_func = cmd.rsp.arg[2] & 0xFFFF;
2396 npar_info->op_mode = (cmd.rsp.arg[2] & 0xFFFF0000) >> 16;
2397 npar_info->phys_port = cmd.rsp.arg[3] & 0xFFFF;
2398 npar_info->switch_mode = (cmd.rsp.arg[3] & 0xFFFF0000) >> 16;
2399 npar_info->capabilities = cmd.rsp.arg[4];
2400 npar_info->max_mac_filters = cmd.rsp.arg[5] & 0xFF;
2401 npar_info->max_mtu = (cmd.rsp.arg[5] & 0xFFFF0000) >> 16;
2402 npar_info->max_tx_ques = cmd.rsp.arg[6] & 0xFFFF;
2403 npar_info->max_rx_ques = (cmd.rsp.arg[6] & 0xFFFF0000) >> 16;
2404 npar_info->min_tx_bw = cmd.rsp.arg[7] & 0xFFFF;
2405 npar_info->max_tx_bw = (cmd.rsp.arg[7] & 0xFFFF0000) >> 16;
2406 if (cmd.rsp.arg[8] & 0x1)
2407 npar_info->max_bw_reg_offset = (cmd.rsp.arg[8] & 0x7FFE) >> 1;
2408 if (cmd.rsp.arg[8] & 0x10000) {
2409 temp = (cmd.rsp.arg[8] & 0x7FFE0000) >> 17;
2410 npar_info->max_linkspeed_reg_offset = temp;
2413 memcpy(ahw->extra_capability, &cmd.rsp.arg[16],
2414 sizeof(ahw->extra_capability));
2417 qlcnic_free_mbx_args(&cmd);
2421 int qlcnic_get_pci_func_type(struct qlcnic_adapter *adapter, u16 type,
2422 u16 *nic, u16 *fcoe, u16 *iscsi)
2424 struct device *dev = &adapter->pdev->dev;
2428 case QLCNIC_TYPE_NIC:
2431 case QLCNIC_TYPE_FCOE:
2434 case QLCNIC_TYPE_ISCSI:
2438 dev_err(dev, "%s: Unknown PCI type[%x]\n",
2446 int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *adapter,
2447 struct qlcnic_pci_info *pci_info)
2449 struct qlcnic_hardware_context *ahw = adapter->ahw;
2450 struct device *dev = &adapter->pdev->dev;
2451 u16 nic = 0, fcoe = 0, iscsi = 0;
2452 struct qlcnic_cmd_args cmd;
2453 int i, err = 0, j = 0;
2456 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_PCI_INFO);
2460 err = qlcnic_issue_cmd(adapter, &cmd);
2462 ahw->total_nic_func = 0;
2463 if (err == QLCNIC_RCODE_SUCCESS) {
2464 ahw->max_pci_func = cmd.rsp.arg[1] & 0xFF;
2465 for (i = 2, j = 0; j < ahw->max_vnic_func; j++, pci_info++) {
2466 pci_info->id = cmd.rsp.arg[i] & 0xFFFF;
2467 pci_info->active = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2469 if (!pci_info->active) {
2470 i += QLC_SKIP_INACTIVE_PCI_REGS;
2473 pci_info->type = cmd.rsp.arg[i] & 0xFFFF;
2474 err = qlcnic_get_pci_func_type(adapter, pci_info->type,
2475 &nic, &fcoe, &iscsi);
2476 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2477 pci_info->default_port = temp;
2479 pci_info->tx_min_bw = cmd.rsp.arg[i] & 0xFFFF;
2480 temp = (cmd.rsp.arg[i] & 0xFFFF0000) >> 16;
2481 pci_info->tx_max_bw = temp;
2483 memcpy(pci_info->mac, &cmd.rsp.arg[i], ETH_ALEN - 2);
2485 memcpy(pci_info->mac + sizeof(u32), &cmd.rsp.arg[i], 2);
2489 dev_err(dev, "Failed to get PCI Info, error = %d\n", err);
2493 ahw->total_nic_func = nic;
2494 ahw->total_pci_func = nic + fcoe + iscsi;
2495 if (ahw->total_nic_func == 0 || ahw->total_pci_func == 0) {
2496 dev_err(dev, "%s: Invalid function count: total nic func[%x], total pci func[%x]\n",
2497 __func__, ahw->total_nic_func, ahw->total_pci_func);
2500 qlcnic_free_mbx_args(&cmd);
2505 int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *adapter, bool op_type)
2509 u32 val, temp, type;
2510 struct qlcnic_cmd_args cmd;
2512 max_ints = adapter->ahw->num_msix - 1;
2513 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_CONFIG_INTRPT);
2517 cmd.req.arg[1] = max_ints;
2519 if (qlcnic_sriov_vf_check(adapter))
2520 cmd.req.arg[1] |= (adapter->ahw->pci_func << 8) | BIT_16;
2522 for (i = 0, index = 2; i < max_ints; i++) {
2523 type = op_type ? QLCNIC_INTRPT_ADD : QLCNIC_INTRPT_DEL;
2524 val = type | (adapter->ahw->intr_tbl[i].type << 4);
2525 if (adapter->ahw->intr_tbl[i].type == QLCNIC_INTRPT_MSIX)
2526 val |= (adapter->ahw->intr_tbl[i].id << 16);
2527 cmd.req.arg[index++] = val;
2529 err = qlcnic_issue_cmd(adapter, &cmd);
2531 dev_err(&adapter->pdev->dev,
2532 "Failed to configure interrupts 0x%x\n", err);
2536 max_ints = cmd.rsp.arg[1];
2537 for (i = 0, index = 2; i < max_ints; i++, index += 2) {
2538 val = cmd.rsp.arg[index];
2540 dev_info(&adapter->pdev->dev,
2541 "Can't configure interrupt %d\n",
2542 adapter->ahw->intr_tbl[i].id);
2546 adapter->ahw->intr_tbl[i].id = MSW(val);
2547 adapter->ahw->intr_tbl[i].enabled = 1;
2548 temp = cmd.rsp.arg[index + 1];
2549 adapter->ahw->intr_tbl[i].src = temp;
2551 adapter->ahw->intr_tbl[i].id = i;
2552 adapter->ahw->intr_tbl[i].enabled = 0;
2553 adapter->ahw->intr_tbl[i].src = 0;
2557 qlcnic_free_mbx_args(&cmd);
2561 int qlcnic_83xx_lock_flash(struct qlcnic_adapter *adapter)
2563 int id, timeout = 0;
2566 while (status == 0) {
2567 status = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
2571 if (++timeout >= QLC_83XX_FLASH_LOCK_TIMEOUT) {
2572 id = QLC_SHARED_REG_RD32(adapter,
2573 QLCNIC_FLASH_LOCK_OWNER);
2574 dev_err(&adapter->pdev->dev,
2575 "%s: failed, lock held by %d\n", __func__, id);
2578 usleep_range(1000, 2000);
2581 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, adapter->portnum);
2585 void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *adapter)
2587 QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
2588 QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER, 0xFF);
2591 int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *adapter,
2592 u32 flash_addr, u8 *p_data,
2595 u32 word, range, flash_offset, addr = flash_addr, ret;
2596 ulong indirect_add, direct_window;
2599 flash_offset = addr & (QLCNIC_FLASH_SECTOR_SIZE - 1);
2601 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
2605 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_DIRECT_WINDOW,
2608 range = flash_offset + (count * sizeof(u32));
2609 /* Check if data is spread across multiple sectors */
2610 if (range > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2612 /* Multi sector read */
2613 for (i = 0; i < count; i++) {
2614 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2615 ret = QLCRD32(adapter, indirect_add, &err);
2620 *(u32 *)p_data = word;
2621 p_data = p_data + 4;
2623 flash_offset = flash_offset + 4;
2625 if (flash_offset > (QLCNIC_FLASH_SECTOR_SIZE - 1)) {
2626 direct_window = QLC_83XX_FLASH_DIRECT_WINDOW;
2627 /* This write is needed once for each sector */
2628 qlcnic_83xx_wrt_reg_indirect(adapter,
2635 /* Single sector read */
2636 for (i = 0; i < count; i++) {
2637 indirect_add = QLC_83XX_FLASH_DIRECT_DATA(addr);
2638 ret = QLCRD32(adapter, indirect_add, &err);
2643 *(u32 *)p_data = word;
2644 p_data = p_data + 4;
2652 static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
2655 int retries = QLC_83XX_FLASH_READ_RETRY_COUNT;
2659 status = QLCRD32(adapter, QLC_83XX_FLASH_STATUS, &err);
2663 if ((status & QLC_83XX_FLASH_STATUS_READY) ==
2664 QLC_83XX_FLASH_STATUS_READY)
2667 msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
2668 } while (--retries);
2676 int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *adapter)
2680 cmd = adapter->ahw->fdt.write_statusreg_cmd;
2681 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2682 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG | cmd));
2683 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2684 adapter->ahw->fdt.write_enable_bits);
2685 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2686 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2687 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2694 int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *adapter)
2698 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2699 (QLC_83XX_FLASH_FDT_WRITE_DEF_SIG |
2700 adapter->ahw->fdt.write_statusreg_cmd));
2701 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2702 adapter->ahw->fdt.write_disable_bits);
2703 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2704 QLC_83XX_FLASH_SECOND_ERASE_MS_VAL);
2705 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2712 int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *adapter)
2717 if (qlcnic_83xx_lock_flash(adapter))
2720 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2721 QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL);
2722 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2723 QLC_83XX_FLASH_READ_CTRL);
2724 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2726 qlcnic_83xx_unlock_flash(adapter);
2730 mfg_id = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
2732 qlcnic_83xx_unlock_flash(adapter);
2736 adapter->flash_mfg_id = (mfg_id & 0xFF);
2737 qlcnic_83xx_unlock_flash(adapter);
2742 int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *adapter)
2744 int count, fdt_size, ret = 0;
2746 fdt_size = sizeof(struct qlcnic_fdt);
2747 count = fdt_size / sizeof(u32);
2749 if (qlcnic_83xx_lock_flash(adapter))
2752 memset(&adapter->ahw->fdt, 0, fdt_size);
2753 ret = qlcnic_83xx_lockless_flash_read32(adapter, QLCNIC_FDT_LOCATION,
2754 (u8 *)&adapter->ahw->fdt,
2757 qlcnic_83xx_unlock_flash(adapter);
2761 int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *adapter,
2762 u32 sector_start_addr)
2764 u32 reversed_addr, addr1, addr2, cmd;
2767 if (qlcnic_83xx_lock_flash(adapter) != 0)
2770 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2771 ret = qlcnic_83xx_enable_flash_write(adapter);
2773 qlcnic_83xx_unlock_flash(adapter);
2774 dev_err(&adapter->pdev->dev,
2775 "%s failed at %d\n",
2776 __func__, __LINE__);
2781 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2783 qlcnic_83xx_unlock_flash(adapter);
2784 dev_err(&adapter->pdev->dev,
2785 "%s: failed at %d\n", __func__, __LINE__);
2789 addr1 = (sector_start_addr & 0xFF) << 16;
2790 addr2 = (sector_start_addr & 0xFF0000) >> 16;
2791 reversed_addr = addr1 | addr2;
2793 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2795 cmd = QLC_83XX_FLASH_FDT_ERASE_DEF_SIG | adapter->ahw->fdt.erase_cmd;
2796 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id)
2797 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, cmd);
2799 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2800 QLC_83XX_FLASH_OEM_ERASE_SIG);
2801 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2802 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2804 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2806 qlcnic_83xx_unlock_flash(adapter);
2807 dev_err(&adapter->pdev->dev,
2808 "%s: failed at %d\n", __func__, __LINE__);
2812 if (adapter->ahw->fdt.mfg_id == adapter->flash_mfg_id) {
2813 ret = qlcnic_83xx_disable_flash_write(adapter);
2815 qlcnic_83xx_unlock_flash(adapter);
2816 dev_err(&adapter->pdev->dev,
2817 "%s: failed at %d\n", __func__, __LINE__);
2822 qlcnic_83xx_unlock_flash(adapter);
2827 int qlcnic_83xx_flash_write32(struct qlcnic_adapter *adapter, u32 addr,
2831 u32 addr1 = 0x00800000 | (addr >> 2);
2833 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR, addr1);
2834 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data);
2835 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2836 QLC_83XX_FLASH_LAST_ERASE_MS_VAL);
2837 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2839 dev_err(&adapter->pdev->dev,
2840 "%s: failed at %d\n", __func__, __LINE__);
2847 int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *adapter, u32 addr,
2848 u32 *p_data, int count)
2851 int ret = -EIO, err = 0;
2853 if ((count < QLC_83XX_FLASH_WRITE_MIN) ||
2854 (count > QLC_83XX_FLASH_WRITE_MAX)) {
2855 dev_err(&adapter->pdev->dev,
2856 "%s: Invalid word count\n", __func__);
2860 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2864 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_SPI_CONTROL,
2865 (temp | QLC_83XX_FLASH_SPI_CTRL));
2866 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2867 QLC_83XX_FLASH_ADDR_TEMP_VAL);
2869 /* First DWORD write */
2870 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2871 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2872 QLC_83XX_FLASH_FIRST_MS_PATTERN);
2873 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2875 dev_err(&adapter->pdev->dev,
2876 "%s: failed at %d\n", __func__, __LINE__);
2881 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2882 QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL);
2883 /* Second to N-1 DWORD writes */
2884 while (count != 1) {
2885 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA,
2887 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2888 QLC_83XX_FLASH_SECOND_MS_PATTERN);
2889 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2891 dev_err(&adapter->pdev->dev,
2892 "%s: failed at %d\n", __func__, __LINE__);
2898 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
2899 QLC_83XX_FLASH_ADDR_TEMP_VAL |
2901 /* Last DWORD write */
2902 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_WRDATA, *p_data++);
2903 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
2904 QLC_83XX_FLASH_LAST_MS_PATTERN);
2905 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
2907 dev_err(&adapter->pdev->dev,
2908 "%s: failed at %d\n", __func__, __LINE__);
2912 ret = QLCRD32(adapter, QLC_83XX_FLASH_SPI_STATUS, &err);
2916 if ((ret & QLC_83XX_FLASH_SPI_CTRL) == QLC_83XX_FLASH_SPI_CTRL) {
2917 dev_err(&adapter->pdev->dev, "%s: failed at %d\n",
2918 __func__, __LINE__);
2919 /* Operation failed, clear error bit */
2920 temp = QLCRD32(adapter, QLC_83XX_FLASH_SPI_CONTROL, &err);
2924 qlcnic_83xx_wrt_reg_indirect(adapter,
2925 QLC_83XX_FLASH_SPI_CONTROL,
2926 (temp | QLC_83XX_FLASH_SPI_CTRL));
2932 static void qlcnic_83xx_recover_driver_lock(struct qlcnic_adapter *adapter)
2936 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2938 /* Check if recovery need to be performed by the calling function */
2939 if ((val & QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK) == 0) {
2941 val = val | ((adapter->portnum << 2) |
2942 QLC_83XX_NEED_DRV_LOCK_RECOVERY);
2943 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2944 dev_info(&adapter->pdev->dev,
2945 "%s: lock recovery initiated\n", __func__);
2946 msleep(QLC_83XX_DRV_LOCK_RECOVERY_DELAY);
2947 val = QLCRDX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK);
2948 id = ((val >> 2) & 0xF);
2949 if (id == adapter->portnum) {
2950 val = val & ~QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK;
2951 val = val | QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS;
2952 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2953 /* Force release the lock */
2954 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
2955 /* Clear recovery bits */
2957 QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, val);
2958 dev_info(&adapter->pdev->dev,
2959 "%s: lock recovery completed\n", __func__);
2961 dev_info(&adapter->pdev->dev,
2962 "%s: func %d to resume lock recovery process\n",
2966 dev_info(&adapter->pdev->dev,
2967 "%s: lock recovery initiated by other functions\n",
2972 int qlcnic_83xx_lock_driver(struct qlcnic_adapter *adapter)
2974 u32 lock_alive_counter, val, id, i = 0, status = 0, temp = 0;
2975 int max_attempt = 0;
2977 while (status == 0) {
2978 status = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK);
2982 msleep(QLC_83XX_DRV_LOCK_WAIT_DELAY);
2986 temp = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2988 if (i == QLC_83XX_DRV_LOCK_WAIT_COUNTER) {
2989 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
2992 dev_info(&adapter->pdev->dev,
2993 "%s: lock to be recovered from %d\n",
2995 qlcnic_83xx_recover_driver_lock(adapter);
2999 dev_err(&adapter->pdev->dev,
3000 "%s: failed to get lock\n", __func__);
3005 /* Force exit from while loop after few attempts */
3006 if (max_attempt == QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT) {
3007 dev_err(&adapter->pdev->dev,
3008 "%s: failed to get lock\n", __func__);
3013 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3014 lock_alive_counter = val >> 8;
3015 lock_alive_counter++;
3016 val = lock_alive_counter << 8 | adapter->portnum;
3017 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3022 void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *adapter)
3024 u32 val, lock_alive_counter, id;
3026 val = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
3028 lock_alive_counter = val >> 8;
3030 if (id != adapter->portnum)
3031 dev_err(&adapter->pdev->dev,
3032 "%s:Warning func %d is unlocking lock owned by %d\n",
3033 __func__, adapter->portnum, id);
3035 val = (lock_alive_counter << 8) | 0xFF;
3036 QLCWRX(adapter->ahw, QLC_83XX_DRV_LOCK_ID, val);
3037 QLCRDX(adapter->ahw, QLC_83XX_DRV_UNLOCK);
3040 int qlcnic_ms_mem_write128(struct qlcnic_adapter *adapter, u64 addr,
3041 u32 *data, u32 count)
3046 /* Check alignment */
3050 mutex_lock(&adapter->ahw->mem_lock);
3051 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
3053 for (i = 0; i < count; i++, addr += 16) {
3054 if (!((ADDR_IN_RANGE(addr, QLCNIC_ADDR_QDR_NET,
3055 QLCNIC_ADDR_QDR_NET_MAX)) ||
3056 (ADDR_IN_RANGE(addr, QLCNIC_ADDR_DDR_NET,
3057 QLCNIC_ADDR_DDR_NET_MAX)))) {
3058 mutex_unlock(&adapter->ahw->mem_lock);
3062 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
3063 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_LO, *data++);
3064 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_HI, *data++);
3065 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_ULO, *data++);
3066 qlcnic_ind_wr(adapter, QLCNIC_MS_WRTDATA_UHI, *data++);
3067 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_ENABLE);
3068 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_WRITE_START);
3070 for (j = 0; j < MAX_CTL_CHECK; j++) {
3071 temp = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
3073 if ((temp & TA_CTL_BUSY) == 0)
3077 /* Status check failure */
3078 if (j >= MAX_CTL_CHECK) {
3079 printk_ratelimited(KERN_WARNING
3080 "MS memory write failed\n");
3081 mutex_unlock(&adapter->ahw->mem_lock);
3086 mutex_unlock(&adapter->ahw->mem_lock);
3091 int qlcnic_83xx_flash_read32(struct qlcnic_adapter *adapter, u32 flash_addr,
3092 u8 *p_data, int count)
3094 u32 word, addr = flash_addr, ret;
3095 ulong indirect_addr;
3098 if (qlcnic_83xx_lock_flash(adapter) != 0)
3102 dev_err(&adapter->pdev->dev, "Illegal addr = 0x%x\n", addr);
3103 qlcnic_83xx_unlock_flash(adapter);
3107 for (i = 0; i < count; i++) {
3108 if (qlcnic_83xx_wrt_reg_indirect(adapter,
3109 QLC_83XX_FLASH_DIRECT_WINDOW,
3111 qlcnic_83xx_unlock_flash(adapter);
3115 indirect_addr = QLC_83XX_FLASH_DIRECT_DATA(addr);
3116 ret = QLCRD32(adapter, indirect_addr, &err);
3121 *(u32 *)p_data = word;
3122 p_data = p_data + 4;
3126 qlcnic_83xx_unlock_flash(adapter);
3131 int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
3135 u32 config = 0, state;
3136 struct qlcnic_cmd_args cmd;
3137 struct qlcnic_hardware_context *ahw = adapter->ahw;
3139 if (qlcnic_sriov_vf_check(adapter))
3140 pci_func = adapter->portnum;
3142 pci_func = ahw->pci_func;
3144 state = readl(ahw->pci_base0 + QLC_83XX_LINK_STATE(pci_func));
3145 if (!QLC_83xx_FUNC_VAL(state, pci_func)) {
3146 dev_info(&adapter->pdev->dev, "link state down\n");
3150 err = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_LINK_STATUS);
3154 err = qlcnic_issue_cmd(adapter, &cmd);
3156 dev_info(&adapter->pdev->dev,
3157 "Get Link Status Command failed: 0x%x\n", err);
3160 config = cmd.rsp.arg[1];
3161 switch (QLC_83XX_CURRENT_LINK_SPEED(config)) {
3162 case QLC_83XX_10M_LINK:
3163 ahw->link_speed = SPEED_10;
3165 case QLC_83XX_100M_LINK:
3166 ahw->link_speed = SPEED_100;
3168 case QLC_83XX_1G_LINK:
3169 ahw->link_speed = SPEED_1000;
3171 case QLC_83XX_10G_LINK:
3172 ahw->link_speed = SPEED_10000;
3175 ahw->link_speed = 0;
3178 config = cmd.rsp.arg[3];
3179 if (QLC_83XX_SFP_PRESENT(config)) {
3180 switch (ahw->module_type) {
3181 case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
3182 case LINKEVENT_MODULE_OPTICAL_SRLR:
3183 case LINKEVENT_MODULE_OPTICAL_LRM:
3184 case LINKEVENT_MODULE_OPTICAL_SFP_1G:
3185 ahw->supported_type = PORT_FIBRE;
3187 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
3188 case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
3189 case LINKEVENT_MODULE_TWINAX:
3190 ahw->supported_type = PORT_TP;
3193 ahw->supported_type = PORT_OTHER;
3200 qlcnic_free_mbx_args(&cmd);
3204 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
3205 struct ethtool_cmd *ecmd)
3209 struct qlcnic_hardware_context *ahw = adapter->ahw;
3211 if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
3212 /* Get port configuration info */
3213 status = qlcnic_83xx_get_port_info(adapter);
3214 /* Get Link Status related info */
3215 config = qlcnic_83xx_test_link(adapter);
3216 ahw->module_type = QLC_83XX_SFP_MODULE_TYPE(config);
3219 /* hard code until there is a way to get it from flash */
3220 ahw->board_type = QLCNIC_BRDTYPE_83XX_10G;
3222 if (netif_running(adapter->netdev) && ahw->has_link_events) {
3223 ethtool_cmd_speed_set(ecmd, ahw->link_speed);
3224 ecmd->duplex = ahw->link_duplex;
3225 ecmd->autoneg = ahw->link_autoneg;
3227 ethtool_cmd_speed_set(ecmd, SPEED_UNKNOWN);
3228 ecmd->duplex = DUPLEX_UNKNOWN;
3229 ecmd->autoneg = AUTONEG_DISABLE;
3232 if (ahw->port_type == QLCNIC_XGBE) {
3233 ecmd->supported = SUPPORTED_10000baseT_Full;
3234 ecmd->advertising = ADVERTISED_10000baseT_Full;
3236 ecmd->supported = (SUPPORTED_10baseT_Half |
3237 SUPPORTED_10baseT_Full |
3238 SUPPORTED_100baseT_Half |
3239 SUPPORTED_100baseT_Full |
3240 SUPPORTED_1000baseT_Half |
3241 SUPPORTED_1000baseT_Full);
3242 ecmd->advertising = (ADVERTISED_100baseT_Half |
3243 ADVERTISED_100baseT_Full |
3244 ADVERTISED_1000baseT_Half |
3245 ADVERTISED_1000baseT_Full);
3248 switch (ahw->supported_type) {
3250 ecmd->supported |= SUPPORTED_FIBRE;
3251 ecmd->advertising |= ADVERTISED_FIBRE;
3252 ecmd->port = PORT_FIBRE;
3253 ecmd->transceiver = XCVR_EXTERNAL;
3256 ecmd->supported |= SUPPORTED_TP;
3257 ecmd->advertising |= ADVERTISED_TP;
3258 ecmd->port = PORT_TP;
3259 ecmd->transceiver = XCVR_INTERNAL;
3262 ecmd->supported |= SUPPORTED_FIBRE;
3263 ecmd->advertising |= ADVERTISED_FIBRE;
3264 ecmd->port = PORT_OTHER;
3265 ecmd->transceiver = XCVR_EXTERNAL;
3268 ecmd->phy_address = ahw->physical_port;
3272 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
3273 struct ethtool_cmd *ecmd)
3276 u32 config = adapter->ahw->port_config;
3279 adapter->ahw->port_config |= BIT_15;
3281 switch (ethtool_cmd_speed(ecmd)) {
3283 adapter->ahw->port_config |= BIT_8;
3286 adapter->ahw->port_config |= BIT_9;
3289 adapter->ahw->port_config |= BIT_10;
3292 adapter->ahw->port_config |= BIT_11;
3298 status = qlcnic_83xx_set_port_config(adapter);
3300 dev_info(&adapter->pdev->dev,
3301 "Failed to Set Link Speed and autoneg.\n");
3302 adapter->ahw->port_config = config;
3307 static inline u64 *qlcnic_83xx_copy_stats(struct qlcnic_cmd_args *cmd,
3308 u64 *data, int index)
3313 low = cmd->rsp.arg[index];
3314 hi = cmd->rsp.arg[index + 1];
3315 val = (((u64) low) | (((u64) hi) << 32));
3320 static u64 *qlcnic_83xx_fill_stats(struct qlcnic_adapter *adapter,
3321 struct qlcnic_cmd_args *cmd, u64 *data,
3324 int err, k, total_regs;
3327 err = qlcnic_issue_cmd(adapter, cmd);
3328 if (err != QLCNIC_RCODE_SUCCESS) {
3329 dev_info(&adapter->pdev->dev,
3330 "Error in get statistics mailbox command\n");
3334 total_regs = cmd->rsp.num;
3336 case QLC_83XX_STAT_MAC:
3337 /* fill in MAC tx counters */
3338 for (k = 2; k < 28; k += 2)
3339 data = qlcnic_83xx_copy_stats(cmd, data, k);
3340 /* skip 24 bytes of reserved area */
3341 /* fill in MAC rx counters */
3342 for (k += 6; k < 60; k += 2)
3343 data = qlcnic_83xx_copy_stats(cmd, data, k);
3344 /* skip 24 bytes of reserved area */
3345 /* fill in MAC rx frame stats */
3346 for (k += 6; k < 80; k += 2)
3347 data = qlcnic_83xx_copy_stats(cmd, data, k);
3348 /* fill in eSwitch stats */
3349 for (; k < total_regs; k += 2)
3350 data = qlcnic_83xx_copy_stats(cmd, data, k);
3352 case QLC_83XX_STAT_RX:
3353 for (k = 2; k < 8; k += 2)
3354 data = qlcnic_83xx_copy_stats(cmd, data, k);
3355 /* skip 8 bytes of reserved data */
3356 for (k += 2; k < 24; k += 2)
3357 data = qlcnic_83xx_copy_stats(cmd, data, k);
3358 /* skip 8 bytes containing RE1FBQ error data */
3359 for (k += 2; k < total_regs; k += 2)
3360 data = qlcnic_83xx_copy_stats(cmd, data, k);
3362 case QLC_83XX_STAT_TX:
3363 for (k = 2; k < 10; k += 2)
3364 data = qlcnic_83xx_copy_stats(cmd, data, k);
3365 /* skip 8 bytes of reserved data */
3366 for (k += 2; k < total_regs; k += 2)
3367 data = qlcnic_83xx_copy_stats(cmd, data, k);
3370 dev_warn(&adapter->pdev->dev, "Unknown get statistics mode\n");
3376 void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data)
3378 struct qlcnic_cmd_args cmd;
3379 struct net_device *netdev = adapter->netdev;
3382 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_STATISTICS);
3386 cmd.req.arg[1] = BIT_1 | (adapter->tx_ring->ctx_id << 16);
3387 cmd.rsp.num = QLC_83XX_TX_STAT_REGS;
3388 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3389 QLC_83XX_STAT_TX, &ret);
3391 netdev_err(netdev, "Error getting Tx stats\n");
3395 cmd.req.arg[1] = BIT_2 | (adapter->portnum << 16);
3396 cmd.rsp.num = QLC_83XX_MAC_STAT_REGS;
3397 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3398 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3399 QLC_83XX_STAT_MAC, &ret);
3401 netdev_err(netdev, "Error getting MAC stats\n");
3405 cmd.req.arg[1] = adapter->recv_ctx->context_id << 16;
3406 cmd.rsp.num = QLC_83XX_RX_STAT_REGS;
3407 memset(cmd.rsp.arg, 0, sizeof(u32) * cmd.rsp.num);
3408 data = qlcnic_83xx_fill_stats(adapter, &cmd, data,
3409 QLC_83XX_STAT_RX, &ret);
3411 netdev_err(netdev, "Error getting Rx stats\n");
3413 qlcnic_free_mbx_args(&cmd);
3416 int qlcnic_83xx_reg_test(struct qlcnic_adapter *adapter)
3418 u32 major, minor, sub;
3420 major = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MAJOR);
3421 minor = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_MINOR);
3422 sub = QLC_SHARED_REG_RD32(adapter, QLCNIC_FW_VERSION_SUB);
3424 if (adapter->fw_version != QLCNIC_VERSION_CODE(major, minor, sub)) {
3425 dev_info(&adapter->pdev->dev, "%s: Reg test failed\n",
3432 inline int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *adapter)
3434 return (ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl) *
3435 sizeof(*adapter->ahw->ext_reg_tbl)) +
3436 (ARRAY_SIZE(qlcnic_83xx_reg_tbl) *
3437 sizeof(*adapter->ahw->reg_tbl));
3440 int qlcnic_83xx_get_registers(struct qlcnic_adapter *adapter, u32 *regs_buff)
3444 for (i = QLCNIC_DEV_INFO_SIZE + 1;
3445 j < ARRAY_SIZE(qlcnic_83xx_reg_tbl); i++, j++)
3446 regs_buff[i] = QLC_SHARED_REG_RD32(adapter, j);
3448 for (j = 0; j < ARRAY_SIZE(qlcnic_83xx_ext_reg_tbl); j++)
3449 regs_buff[i++] = QLCRDX(adapter->ahw, j);
3453 int qlcnic_83xx_interrupt_test(struct net_device *netdev)
3455 struct qlcnic_adapter *adapter = netdev_priv(netdev);
3456 struct qlcnic_hardware_context *ahw = adapter->ahw;
3457 struct qlcnic_cmd_args cmd;
3458 u8 val, drv_sds_rings = adapter->drv_sds_rings;
3459 u8 drv_tx_rings = adapter->drv_tx_rings;
3464 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3465 netdev_info(netdev, "Device is resetting\n");
3469 if (qlcnic_get_diag_lock(adapter)) {
3470 netdev_info(netdev, "Device in diagnostics mode\n");
3474 ret = qlcnic_83xx_diag_alloc_res(netdev, QLCNIC_INTERRUPT_TEST,
3480 ret = qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_INTRPT_TEST);
3484 if (adapter->flags & QLCNIC_MSIX_ENABLED)
3485 intrpt_id = ahw->intr_tbl[0].id;
3487 intrpt_id = QLCRDX(ahw, QLCNIC_DEF_INT_ID);
3490 cmd.req.arg[2] = intrpt_id;
3491 cmd.req.arg[3] = BIT_0;
3493 ret = qlcnic_issue_cmd(adapter, &cmd);
3494 data = cmd.rsp.arg[2];
3496 val = LSB(MSW(data));
3497 if (id != intrpt_id)
3498 dev_info(&adapter->pdev->dev,
3499 "Interrupt generated: 0x%x, requested:0x%x\n",
3502 dev_err(&adapter->pdev->dev,
3503 "Interrupt test error: 0x%x\n", val);
3508 ret = !ahw->diag_cnt;
3511 qlcnic_free_mbx_args(&cmd);
3512 qlcnic_83xx_diag_free_res(netdev, drv_sds_rings);
3515 adapter->drv_sds_rings = drv_sds_rings;
3516 adapter->drv_tx_rings = drv_tx_rings;
3517 qlcnic_release_diag_lock(adapter);
3521 void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *adapter,
3522 struct ethtool_pauseparam *pause)
3524 struct qlcnic_hardware_context *ahw = adapter->ahw;
3528 status = qlcnic_83xx_get_port_config(adapter);
3530 dev_err(&adapter->pdev->dev,
3531 "%s: Get Pause Config failed\n", __func__);
3534 config = ahw->port_config;
3535 if (config & QLC_83XX_CFG_STD_PAUSE) {
3536 switch (MSW(config)) {
3537 case QLC_83XX_TX_PAUSE:
3538 pause->tx_pause = 1;
3540 case QLC_83XX_RX_PAUSE:
3541 pause->rx_pause = 1;
3543 case QLC_83XX_TX_RX_PAUSE:
3545 /* Backward compatibility for existing
3548 pause->tx_pause = 1;
3549 pause->rx_pause = 1;
3553 if (QLC_83XX_AUTONEG(config))
3557 int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *adapter,
3558 struct ethtool_pauseparam *pause)
3560 struct qlcnic_hardware_context *ahw = adapter->ahw;
3564 status = qlcnic_83xx_get_port_config(adapter);
3566 dev_err(&adapter->pdev->dev,
3567 "%s: Get Pause Config failed.\n", __func__);
3570 config = ahw->port_config;
3572 if (ahw->port_type == QLCNIC_GBE) {
3574 ahw->port_config |= QLC_83XX_ENABLE_AUTONEG;
3575 if (!pause->autoneg)
3576 ahw->port_config &= ~QLC_83XX_ENABLE_AUTONEG;
3577 } else if ((ahw->port_type == QLCNIC_XGBE) && (pause->autoneg)) {
3581 if (!(config & QLC_83XX_CFG_STD_PAUSE))
3582 ahw->port_config |= QLC_83XX_CFG_STD_PAUSE;
3584 if (pause->rx_pause && pause->tx_pause) {
3585 ahw->port_config |= QLC_83XX_CFG_STD_TX_RX_PAUSE;
3586 } else if (pause->rx_pause && !pause->tx_pause) {
3587 ahw->port_config &= ~QLC_83XX_CFG_STD_TX_PAUSE;
3588 ahw->port_config |= QLC_83XX_CFG_STD_RX_PAUSE;
3589 } else if (pause->tx_pause && !pause->rx_pause) {
3590 ahw->port_config &= ~QLC_83XX_CFG_STD_RX_PAUSE;
3591 ahw->port_config |= QLC_83XX_CFG_STD_TX_PAUSE;
3592 } else if (!pause->rx_pause && !pause->tx_pause) {
3593 ahw->port_config &= ~(QLC_83XX_CFG_STD_TX_RX_PAUSE |
3594 QLC_83XX_CFG_STD_PAUSE);
3596 status = qlcnic_83xx_set_port_config(adapter);
3598 dev_err(&adapter->pdev->dev,
3599 "%s: Set Pause Config failed.\n", __func__);
3600 ahw->port_config = config;
3605 static int qlcnic_83xx_read_flash_status_reg(struct qlcnic_adapter *adapter)
3610 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_ADDR,
3611 QLC_83XX_FLASH_OEM_READ_SIG);
3612 qlcnic_83xx_wrt_reg_indirect(adapter, QLC_83XX_FLASH_CONTROL,
3613 QLC_83XX_FLASH_READ_CTRL);
3614 ret = qlcnic_83xx_poll_flash_status_reg(adapter);
3618 temp = QLCRD32(adapter, QLC_83XX_FLASH_RDDATA, &err);
3625 int qlcnic_83xx_flash_test(struct qlcnic_adapter *adapter)
3629 status = qlcnic_83xx_read_flash_status_reg(adapter);
3630 if (status == -EIO) {
3631 dev_info(&adapter->pdev->dev, "%s: EEPROM test failed.\n",
3638 static int qlcnic_83xx_shutdown(struct pci_dev *pdev)
3640 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
3641 struct net_device *netdev = adapter->netdev;
3644 netif_device_detach(netdev);
3645 qlcnic_cancel_idc_work(adapter);
3647 if (netif_running(netdev))
3648 qlcnic_down(adapter, netdev);
3650 qlcnic_83xx_disable_mbx_intr(adapter);
3651 cancel_delayed_work_sync(&adapter->idc_aen_work);
3653 retval = pci_save_state(pdev);
3660 static int qlcnic_83xx_resume(struct qlcnic_adapter *adapter)
3662 struct qlcnic_hardware_context *ahw = adapter->ahw;
3663 struct qlc_83xx_idc *idc = &ahw->idc;
3666 err = qlcnic_83xx_idc_init(adapter);
3670 if (ahw->nic_mode == QLCNIC_VNIC_MODE) {
3671 if (ahw->op_mode == QLCNIC_MGMT_FUNC) {
3672 qlcnic_83xx_set_vnic_opmode(adapter);
3674 err = qlcnic_83xx_check_vnic_state(adapter);
3680 err = qlcnic_83xx_idc_reattach_driver(adapter);
3684 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
3689 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx)
3691 reinit_completion(&mbx->completion);
3692 set_bit(QLC_83XX_MBX_READY, &mbx->status);
3695 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx)
3700 destroy_workqueue(mbx->work_q);
3705 qlcnic_83xx_notify_cmd_completion(struct qlcnic_adapter *adapter,
3706 struct qlcnic_cmd_args *cmd)
3708 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_ARRIVED);
3710 if (cmd->type == QLC_83XX_MBX_CMD_NO_WAIT) {
3711 qlcnic_free_mbx_args(cmd);
3715 complete(&cmd->completion);
3718 static void qlcnic_83xx_flush_mbx_queue(struct qlcnic_adapter *adapter)
3720 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3721 struct list_head *head = &mbx->cmd_q;
3722 struct qlcnic_cmd_args *cmd = NULL;
3724 spin_lock(&mbx->queue_lock);
3726 while (!list_empty(head)) {
3727 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3728 dev_info(&adapter->pdev->dev, "%s: Mailbox command 0x%x\n",
3729 __func__, cmd->cmd_op);
3730 list_del(&cmd->list);
3732 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3735 spin_unlock(&mbx->queue_lock);
3738 static int qlcnic_83xx_check_mbx_status(struct qlcnic_adapter *adapter)
3740 struct qlcnic_hardware_context *ahw = adapter->ahw;
3741 struct qlcnic_mailbox *mbx = ahw->mailbox;
3744 if (!test_bit(QLC_83XX_MBX_READY, &mbx->status))
3747 host_mbx_ctrl = QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL);
3748 if (host_mbx_ctrl) {
3749 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3750 ahw->idc.collect_dump = 1;
3757 static inline void qlcnic_83xx_signal_mbx_cmd(struct qlcnic_adapter *adapter,
3761 QLCWRX(adapter->ahw, QLCNIC_HOST_MBX_CTRL, QLCNIC_SET_OWNER);
3763 QLCWRX(adapter->ahw, QLCNIC_FW_MBX_CTRL, QLCNIC_CLR_OWNER);
3766 static void qlcnic_83xx_dequeue_mbx_cmd(struct qlcnic_adapter *adapter,
3767 struct qlcnic_cmd_args *cmd)
3769 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3771 spin_lock(&mbx->queue_lock);
3773 list_del(&cmd->list);
3776 spin_unlock(&mbx->queue_lock);
3778 qlcnic_83xx_notify_cmd_completion(adapter, cmd);
3781 static void qlcnic_83xx_encode_mbx_cmd(struct qlcnic_adapter *adapter,
3782 struct qlcnic_cmd_args *cmd)
3784 u32 mbx_cmd, fw_hal_version, hdr_size, total_size, tmp;
3785 struct qlcnic_hardware_context *ahw = adapter->ahw;
3788 if (cmd->op_type != QLC_83XX_MBX_POST_BC_OP) {
3789 mbx_cmd = cmd->req.arg[0];
3790 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3791 for (i = 1; i < cmd->req.num; i++)
3792 writel(cmd->req.arg[i], QLCNIC_MBX_HOST(ahw, i));
3794 fw_hal_version = ahw->fw_hal_version;
3795 hdr_size = sizeof(struct qlcnic_bc_hdr) / sizeof(u32);
3796 total_size = cmd->pay_size + hdr_size;
3797 tmp = QLCNIC_CMD_BC_EVENT_SETUP | total_size << 16;
3798 mbx_cmd = tmp | fw_hal_version << 29;
3799 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 0));
3801 /* Back channel specific operations bits */
3802 mbx_cmd = 0x1 | 1 << 4;
3804 if (qlcnic_sriov_pf_check(adapter))
3805 mbx_cmd |= cmd->func_num << 5;
3807 writel(mbx_cmd, QLCNIC_MBX_HOST(ahw, 1));
3809 for (i = 2, j = 0; j < hdr_size; i++, j++)
3810 writel(*(cmd->hdr++), QLCNIC_MBX_HOST(ahw, i));
3811 for (j = 0; j < cmd->pay_size; j++, i++)
3812 writel(*(cmd->pay++), QLCNIC_MBX_HOST(ahw, i));
3816 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *adapter)
3818 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3823 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3824 complete(&mbx->completion);
3825 cancel_work_sync(&mbx->work);
3826 flush_workqueue(mbx->work_q);
3827 qlcnic_83xx_flush_mbx_queue(adapter);
3830 static int qlcnic_83xx_enqueue_mbx_cmd(struct qlcnic_adapter *adapter,
3831 struct qlcnic_cmd_args *cmd,
3832 unsigned long *timeout)
3834 struct qlcnic_mailbox *mbx = adapter->ahw->mailbox;
3836 if (test_bit(QLC_83XX_MBX_READY, &mbx->status)) {
3837 atomic_set(&cmd->rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3838 init_completion(&cmd->completion);
3839 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_UNKNOWN;
3841 spin_lock(&mbx->queue_lock);
3843 list_add_tail(&cmd->list, &mbx->cmd_q);
3845 cmd->total_cmds = mbx->num_cmds;
3846 *timeout = cmd->total_cmds * QLC_83XX_MBX_TIMEOUT;
3847 queue_work(mbx->work_q, &mbx->work);
3849 spin_unlock(&mbx->queue_lock);
3857 static int qlcnic_83xx_check_mac_rcode(struct qlcnic_adapter *adapter,
3858 struct qlcnic_cmd_args *cmd)
3863 if (cmd->cmd_op == QLCNIC_CMD_CONFIG_MAC_VLAN) {
3864 fw_data = readl(QLCNIC_MBX_FW(adapter->ahw, 2));
3865 mac_cmd_rcode = (u8)fw_data;
3866 if (mac_cmd_rcode == QLC_83XX_NO_NIC_RESOURCE ||
3867 mac_cmd_rcode == QLC_83XX_MAC_PRESENT ||
3868 mac_cmd_rcode == QLC_83XX_MAC_ABSENT) {
3869 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3870 return QLCNIC_RCODE_SUCCESS;
3877 static void qlcnic_83xx_decode_mbx_rsp(struct qlcnic_adapter *adapter,
3878 struct qlcnic_cmd_args *cmd)
3880 struct qlcnic_hardware_context *ahw = adapter->ahw;
3881 struct device *dev = &adapter->pdev->dev;
3885 fw_data = readl(QLCNIC_MBX_FW(ahw, 0));
3886 mbx_err_code = QLCNIC_MBX_STATUS(fw_data);
3887 qlcnic_83xx_get_mbx_data(adapter, cmd);
3889 switch (mbx_err_code) {
3890 case QLCNIC_MBX_RSP_OK:
3891 case QLCNIC_MBX_PORT_RSP_OK:
3892 cmd->rsp_opcode = QLCNIC_RCODE_SUCCESS;
3895 if (!qlcnic_83xx_check_mac_rcode(adapter, cmd))
3898 dev_err(dev, "%s: Mailbox command failed, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x, error=0x%x\n",
3899 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3900 ahw->op_mode, mbx_err_code);
3901 cmd->rsp_opcode = QLC_83XX_MBX_RESPONSE_FAILED;
3902 qlcnic_dump_mbx(adapter, cmd);
3908 static inline void qlcnic_dump_mailbox_registers(struct qlcnic_adapter *adapter)
3910 struct qlcnic_hardware_context *ahw = adapter->ahw;
3913 offset = QLCRDX(ahw, QLCNIC_DEF_INT_MASK);
3914 dev_info(&adapter->pdev->dev, "Mbx interrupt mask=0x%x, Mbx interrupt enable=0x%x, Host mbx control=0x%x, Fw mbx control=0x%x",
3915 readl(ahw->pci_base0 + offset),
3916 QLCRDX(ahw, QLCNIC_MBX_INTR_ENBL),
3917 QLCRDX(ahw, QLCNIC_HOST_MBX_CTRL),
3918 QLCRDX(ahw, QLCNIC_FW_MBX_CTRL));
3921 static void qlcnic_83xx_mailbox_worker(struct work_struct *work)
3923 struct qlcnic_mailbox *mbx = container_of(work, struct qlcnic_mailbox,
3925 struct qlcnic_adapter *adapter = mbx->adapter;
3926 struct qlcnic_mbx_ops *mbx_ops = mbx->ops;
3927 struct device *dev = &adapter->pdev->dev;
3928 atomic_t *rsp_status = &mbx->rsp_status;
3929 struct list_head *head = &mbx->cmd_q;
3930 struct qlcnic_hardware_context *ahw;
3931 struct qlcnic_cmd_args *cmd = NULL;
3936 if (qlcnic_83xx_check_mbx_status(adapter)) {
3937 qlcnic_83xx_flush_mbx_queue(adapter);
3941 atomic_set(rsp_status, QLC_83XX_MBX_RESPONSE_WAIT);
3943 spin_lock(&mbx->queue_lock);
3945 if (list_empty(head)) {
3946 spin_unlock(&mbx->queue_lock);
3949 cmd = list_entry(head->next, struct qlcnic_cmd_args, list);
3951 spin_unlock(&mbx->queue_lock);
3953 mbx_ops->encode_cmd(adapter, cmd);
3954 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_REQUEST);
3956 if (wait_for_completion_timeout(&mbx->completion,
3957 QLC_83XX_MBX_TIMEOUT)) {
3958 mbx_ops->decode_resp(adapter, cmd);
3959 mbx_ops->nofity_fw(adapter, QLC_83XX_MBX_COMPLETION);
3961 dev_err(dev, "%s: Mailbox command timeout, opcode=0x%x, cmd_type=0x%x, func=0x%x, op_mode=0x%x\n",
3962 __func__, cmd->cmd_op, cmd->type, ahw->pci_func,
3964 clear_bit(QLC_83XX_MBX_READY, &mbx->status);
3965 qlcnic_dump_mailbox_registers(adapter);
3966 qlcnic_83xx_get_mbx_data(adapter, cmd);
3967 qlcnic_dump_mbx(adapter, cmd);
3968 qlcnic_83xx_idc_request_reset(adapter,
3969 QLCNIC_FORCE_FW_DUMP_KEY);
3970 cmd->rsp_opcode = QLCNIC_RCODE_TIMEOUT;
3972 mbx_ops->dequeue_cmd(adapter, cmd);
3976 static struct qlcnic_mbx_ops qlcnic_83xx_mbx_ops = {
3977 .enqueue_cmd = qlcnic_83xx_enqueue_mbx_cmd,
3978 .dequeue_cmd = qlcnic_83xx_dequeue_mbx_cmd,
3979 .decode_resp = qlcnic_83xx_decode_mbx_rsp,
3980 .encode_cmd = qlcnic_83xx_encode_mbx_cmd,
3981 .nofity_fw = qlcnic_83xx_signal_mbx_cmd,
3984 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *adapter)
3986 struct qlcnic_hardware_context *ahw = adapter->ahw;
3987 struct qlcnic_mailbox *mbx;
3989 ahw->mailbox = kzalloc(sizeof(*mbx), GFP_KERNEL);
3994 mbx->ops = &qlcnic_83xx_mbx_ops;
3995 mbx->adapter = adapter;
3997 spin_lock_init(&mbx->queue_lock);
3998 spin_lock_init(&mbx->aen_lock);
3999 INIT_LIST_HEAD(&mbx->cmd_q);
4000 init_completion(&mbx->completion);
4002 mbx->work_q = create_singlethread_workqueue("qlcnic_mailbox");
4003 if (mbx->work_q == NULL) {
4008 INIT_WORK(&mbx->work, qlcnic_83xx_mailbox_worker);
4009 set_bit(QLC_83XX_MBX_READY, &mbx->status);
4013 static pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *pdev,
4014 pci_channel_state_t state)
4016 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4018 if (state == pci_channel_io_perm_failure)
4019 return PCI_ERS_RESULT_DISCONNECT;
4021 if (state == pci_channel_io_normal)
4022 return PCI_ERS_RESULT_RECOVERED;
4024 set_bit(__QLCNIC_AER, &adapter->state);
4025 set_bit(__QLCNIC_RESETTING, &adapter->state);
4027 qlcnic_83xx_aer_stop_poll_work(adapter);
4029 pci_save_state(pdev);
4030 pci_disable_device(pdev);
4032 return PCI_ERS_RESULT_NEED_RESET;
4035 static pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *pdev)
4037 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4040 pdev->error_state = pci_channel_io_normal;
4041 err = pci_enable_device(pdev);
4045 pci_set_power_state(pdev, PCI_D0);
4046 pci_set_master(pdev);
4047 pci_restore_state(pdev);
4049 err = qlcnic_83xx_aer_reset(adapter);
4051 return PCI_ERS_RESULT_RECOVERED;
4053 clear_bit(__QLCNIC_AER, &adapter->state);
4054 clear_bit(__QLCNIC_RESETTING, &adapter->state);
4055 return PCI_ERS_RESULT_DISCONNECT;
4058 static void qlcnic_83xx_io_resume(struct pci_dev *pdev)
4060 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
4062 pci_cleanup_aer_uncorrect_error_status(pdev);
4063 if (test_and_clear_bit(__QLCNIC_AER, &adapter->state))
4064 qlcnic_83xx_aer_start_poll_work(adapter);