2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #include <linux/io-mapping.h>
41 #include <linux/interrupt.h>
42 #include <linux/delay.h>
43 #include <linux/mlx5/driver.h>
44 #include <linux/mlx5/cq.h>
45 #include <linux/mlx5/qp.h>
46 #include <linux/mlx5/srq.h>
47 #include <linux/debugfs.h>
48 #include <linux/kmod.h>
49 #include <linux/delay.h>
50 #include <linux/mlx5/mlx5_ifc.h>
51 #include "mlx5_core.h"
53 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
54 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
55 MODULE_LICENSE("Dual BSD/GPL");
56 MODULE_VERSION(DRIVER_VERSION);
58 int mlx5_core_debug_mask;
59 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
60 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
62 #define MLX5_DEFAULT_PROF 2
63 static int prof_sel = MLX5_DEFAULT_PROF;
64 module_param_named(prof_sel, prof_sel, int, 0444);
65 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
67 static LIST_HEAD(intf_list);
68 static LIST_HEAD(dev_list);
69 static DEFINE_MUTEX(intf_mutex);
71 struct mlx5_device_context {
72 struct list_head list;
73 struct mlx5_interface *intf;
77 static struct mlx5_profile profile[] = {
82 .mask = MLX5_PROF_MASK_QP_SIZE,
86 .mask = MLX5_PROF_MASK_QP_SIZE |
87 MLX5_PROF_MASK_MR_CACHE,
156 #define FW_INIT_TIMEOUT_MILI 2000
157 #define FW_INIT_WAIT_MS 2
159 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
161 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
164 while (fw_initializing(dev)) {
165 if (time_after(jiffies, end)) {
169 msleep(FW_INIT_WAIT_MS);
175 static int set_dma_caps(struct pci_dev *pdev)
179 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
181 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
182 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
184 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
189 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
192 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
193 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
196 "Can't set consistent PCI DMA mask, aborting\n");
201 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
205 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
207 struct pci_dev *pdev = dev->pdev;
210 mutex_lock(&dev->pci_status_mutex);
211 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
212 err = pci_enable_device(pdev);
214 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
216 mutex_unlock(&dev->pci_status_mutex);
221 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
223 struct pci_dev *pdev = dev->pdev;
225 mutex_lock(&dev->pci_status_mutex);
226 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
227 pci_disable_device(pdev);
228 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
230 mutex_unlock(&dev->pci_status_mutex);
233 static int request_bar(struct pci_dev *pdev)
237 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
238 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
242 err = pci_request_regions(pdev, DRIVER_NAME);
244 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
249 static void release_bar(struct pci_dev *pdev)
251 pci_release_regions(pdev);
254 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
256 struct mlx5_priv *priv = &dev->priv;
257 struct mlx5_eq_table *table = &priv->eq_table;
258 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
262 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
263 MLX5_EQ_VEC_COMP_BASE;
264 nvec = min_t(int, nvec, num_eqs);
265 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
268 priv->msix_arr = kcalloc(nvec, sizeof(*priv->msix_arr), GFP_KERNEL);
270 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
271 if (!priv->msix_arr || !priv->irq_info)
274 for (i = 0; i < nvec; i++)
275 priv->msix_arr[i].entry = i;
277 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
278 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
282 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
287 kfree(priv->irq_info);
288 kfree(priv->msix_arr);
292 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
294 struct mlx5_priv *priv = &dev->priv;
296 pci_disable_msix(dev->pdev);
297 kfree(priv->irq_info);
298 kfree(priv->msix_arr);
301 struct mlx5_reg_host_endianess {
307 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
310 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
311 MLX5_DEV_CAP_FLAG_DCT,
314 static u16 to_fw_pkey_sz(u32 size)
330 pr_warn("invalid pkey table size %d\n", size);
335 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
336 enum mlx5_cap_mode cap_mode)
338 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
339 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
340 void *out, *hca_caps;
341 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
344 memset(in, 0, sizeof(in));
345 out = kzalloc(out_sz, GFP_KERNEL);
349 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
350 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
351 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
355 err = mlx5_cmd_status_to_err_v2(out);
358 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
359 cap_type, cap_mode, err);
363 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
366 case HCA_CAP_OPMOD_GET_MAX:
367 memcpy(dev->hca_caps_max[cap_type], hca_caps,
368 MLX5_UN_SZ_BYTES(hca_cap_union));
370 case HCA_CAP_OPMOD_GET_CUR:
371 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
372 MLX5_UN_SZ_BYTES(hca_cap_union));
376 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
386 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
388 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
391 memset(out, 0, sizeof(out));
393 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
394 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
398 err = mlx5_cmd_status_to_err_v2(out);
403 static int handle_hca_cap(struct mlx5_core_dev *dev)
405 void *set_ctx = NULL;
406 struct mlx5_profile *prof = dev->profile;
408 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
411 set_ctx = kzalloc(set_sz, GFP_KERNEL);
415 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
419 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
423 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
425 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
426 MLX5_ST_SZ_BYTES(cmd_hca_cap));
428 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
429 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
431 /* we limit the size of the pkey table to 128 entries for now */
432 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
435 /* Check log_max_qp from HCA caps to set in current profile */
436 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
437 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
438 profile[prof_sel].log_max_qp,
439 MLX5_CAP_GEN_MAX(dev, log_max_qp));
440 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
442 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
443 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
446 /* disable cmdif checksum */
447 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
449 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
451 err = set_caps(dev, set_ctx, set_sz);
458 static int set_hca_ctrl(struct mlx5_core_dev *dev)
460 struct mlx5_reg_host_endianess he_in;
461 struct mlx5_reg_host_endianess he_out;
464 memset(&he_in, 0, sizeof(he_in));
465 he_in.he = MLX5_SET_HOST_ENDIANNESS;
466 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
467 &he_out, sizeof(he_out),
468 MLX5_REG_HOST_ENDIANNESS, 0, 1);
472 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
475 struct mlx5_enable_hca_mbox_in in;
476 struct mlx5_enable_hca_mbox_out out;
478 memset(&in, 0, sizeof(in));
479 memset(&out, 0, sizeof(out));
480 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ENABLE_HCA);
481 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
486 return mlx5_cmd_status_to_err(&out.hdr);
491 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
494 struct mlx5_disable_hca_mbox_in in;
495 struct mlx5_disable_hca_mbox_out out;
497 memset(&in, 0, sizeof(in));
498 memset(&out, 0, sizeof(out));
499 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_DISABLE_HCA);
500 err = mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
505 return mlx5_cmd_status_to_err(&out.hdr);
510 static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
512 struct mlx5_priv *priv = &mdev->priv;
513 struct msix_entry *msix = priv->msix_arr;
514 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
515 int numa_node = priv->numa_node;
518 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
519 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
523 cpumask_set_cpu(cpumask_local_spread(i, numa_node),
524 priv->irq_info[i].mask);
526 err = irq_set_affinity_hint(irq, priv->irq_info[i].mask);
528 mlx5_core_warn(mdev, "irq_set_affinity_hint failed,irq 0x%.4x",
536 free_cpumask_var(priv->irq_info[i].mask);
540 static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
542 struct mlx5_priv *priv = &mdev->priv;
543 struct msix_entry *msix = priv->msix_arr;
544 int irq = msix[i + MLX5_EQ_VEC_COMP_BASE].vector;
546 irq_set_affinity_hint(irq, NULL);
547 free_cpumask_var(priv->irq_info[i].mask);
550 static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
555 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
556 err = mlx5_irq_set_affinity_hint(mdev, i);
564 for (i--; i >= 0; i--)
565 mlx5_irq_clear_affinity_hint(mdev, i);
570 static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
574 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
575 mlx5_irq_clear_affinity_hint(mdev, i);
578 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
581 struct mlx5_eq_table *table = &dev->priv.eq_table;
582 struct mlx5_eq *eq, *n;
585 spin_lock(&table->lock);
586 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
587 if (eq->index == vector) {
594 spin_unlock(&table->lock);
598 EXPORT_SYMBOL(mlx5_vector2eqn);
600 static void free_comp_eqs(struct mlx5_core_dev *dev)
602 struct mlx5_eq_table *table = &dev->priv.eq_table;
603 struct mlx5_eq *eq, *n;
605 spin_lock(&table->lock);
606 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
608 spin_unlock(&table->lock);
609 if (mlx5_destroy_unmap_eq(dev, eq))
610 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
613 spin_lock(&table->lock);
615 spin_unlock(&table->lock);
618 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
620 struct mlx5_eq_table *table = &dev->priv.eq_table;
621 char name[MLX5_MAX_IRQ_NAME];
628 INIT_LIST_HEAD(&table->comp_eqs_list);
629 ncomp_vec = table->num_comp_vectors;
630 nent = MLX5_COMP_EQ_SIZE;
631 for (i = 0; i < ncomp_vec; i++) {
632 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
638 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
639 err = mlx5_create_map_eq(dev, eq,
640 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
641 name, &dev->priv.uuari.uars[0]);
646 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
648 spin_lock(&table->lock);
649 list_add_tail(&eq->list, &table->comp_eqs_list);
650 spin_unlock(&table->lock);
660 #ifdef CONFIG_MLX5_CORE_EN
661 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
663 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
664 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
665 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
666 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
670 memset(query_in, 0, sizeof(query_in));
671 memset(query_out, 0, sizeof(query_out));
673 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
675 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
676 query_out, sizeof(query_out));
678 if (((struct mlx5_outbox_hdr *)query_out)->status ==
679 MLX5_CMD_STAT_BAD_OP_ERR) {
680 pr_debug("Only ISSI 0 is supported\n");
684 pr_err("failed to query ISSI\n");
688 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
690 if (sup_issi & (1 << 1)) {
691 memset(set_in, 0, sizeof(set_in));
692 memset(set_out, 0, sizeof(set_out));
694 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
695 MLX5_SET(set_issi_in, set_in, current_issi, 1);
697 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
698 set_out, sizeof(set_out));
700 pr_err("failed to set ISSI=1\n");
707 } else if (sup_issi & (1 << 0) || !sup_issi) {
715 static int map_bf_area(struct mlx5_core_dev *dev)
717 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
718 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
720 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
722 return dev->priv.bf_mapping ? 0 : -ENOMEM;
725 static void unmap_bf_area(struct mlx5_core_dev *dev)
727 if (dev->priv.bf_mapping)
728 io_mapping_free(dev->priv.bf_mapping);
731 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
733 struct mlx5_device_context *dev_ctx;
734 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
736 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
740 dev_ctx->intf = intf;
741 dev_ctx->context = intf->add(dev);
743 if (dev_ctx->context) {
744 spin_lock_irq(&priv->ctx_lock);
745 list_add_tail(&dev_ctx->list, &priv->ctx_list);
746 spin_unlock_irq(&priv->ctx_lock);
752 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
754 struct mlx5_device_context *dev_ctx;
755 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
757 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
758 if (dev_ctx->intf == intf) {
759 spin_lock_irq(&priv->ctx_lock);
760 list_del(&dev_ctx->list);
761 spin_unlock_irq(&priv->ctx_lock);
763 intf->remove(dev, dev_ctx->context);
769 static int mlx5_register_device(struct mlx5_core_dev *dev)
771 struct mlx5_priv *priv = &dev->priv;
772 struct mlx5_interface *intf;
774 mutex_lock(&intf_mutex);
775 list_add_tail(&priv->dev_list, &dev_list);
776 list_for_each_entry(intf, &intf_list, list)
777 mlx5_add_device(intf, priv);
778 mutex_unlock(&intf_mutex);
783 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
785 struct mlx5_priv *priv = &dev->priv;
786 struct mlx5_interface *intf;
788 mutex_lock(&intf_mutex);
789 list_for_each_entry(intf, &intf_list, list)
790 mlx5_remove_device(intf, priv);
791 list_del(&priv->dev_list);
792 mutex_unlock(&intf_mutex);
795 int mlx5_register_interface(struct mlx5_interface *intf)
797 struct mlx5_priv *priv;
799 if (!intf->add || !intf->remove)
802 mutex_lock(&intf_mutex);
803 list_add_tail(&intf->list, &intf_list);
804 list_for_each_entry(priv, &dev_list, dev_list)
805 mlx5_add_device(intf, priv);
806 mutex_unlock(&intf_mutex);
810 EXPORT_SYMBOL(mlx5_register_interface);
812 void mlx5_unregister_interface(struct mlx5_interface *intf)
814 struct mlx5_priv *priv;
816 mutex_lock(&intf_mutex);
817 list_for_each_entry(priv, &dev_list, dev_list)
818 mlx5_remove_device(intf, priv);
819 list_del(&intf->list);
820 mutex_unlock(&intf_mutex);
822 EXPORT_SYMBOL(mlx5_unregister_interface);
824 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
826 struct mlx5_priv *priv = &mdev->priv;
827 struct mlx5_device_context *dev_ctx;
831 spin_lock_irqsave(&priv->ctx_lock, flags);
833 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
834 if ((dev_ctx->intf->protocol == protocol) &&
835 dev_ctx->intf->get_dev) {
836 result = dev_ctx->intf->get_dev(dev_ctx->context);
840 spin_unlock_irqrestore(&priv->ctx_lock, flags);
844 EXPORT_SYMBOL(mlx5_get_protocol_dev);
846 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
848 struct pci_dev *pdev = dev->pdev;
851 pci_set_drvdata(dev->pdev, dev);
852 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
853 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
855 mutex_init(&priv->pgdir_mutex);
856 INIT_LIST_HEAD(&priv->pgdir_list);
857 spin_lock_init(&priv->mkey_lock);
859 mutex_init(&priv->alloc_mutex);
861 priv->numa_node = dev_to_node(&dev->pdev->dev);
863 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
867 err = mlx5_pci_enable_device(dev);
869 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
873 err = request_bar(pdev);
875 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
879 pci_set_master(pdev);
881 err = set_dma_caps(pdev);
883 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
887 dev->iseg_base = pci_resource_start(dev->pdev, 0);
888 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
891 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
898 pci_clear_master(dev->pdev);
899 release_bar(dev->pdev);
901 mlx5_pci_disable_device(dev);
904 debugfs_remove(priv->dbg_root);
908 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
911 pci_clear_master(dev->pdev);
912 release_bar(dev->pdev);
913 mlx5_pci_disable_device(dev);
914 debugfs_remove(priv->dbg_root);
917 #define MLX5_IB_MOD "mlx5_ib"
918 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
920 struct pci_dev *pdev = dev->pdev;
923 mutex_lock(&dev->intf_state_mutex);
924 if (dev->interface_state == MLX5_INTERFACE_STATE_UP) {
925 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
930 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
931 fw_rev_min(dev), fw_rev_sub(dev));
933 /* on load removing any previous indication of internal error, device is
936 dev->state = MLX5_DEVICE_STATE_UP;
938 err = mlx5_cmd_init(dev);
940 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
944 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
946 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
947 FW_INIT_TIMEOUT_MILI);
951 mlx5_pagealloc_init(dev);
953 err = mlx5_core_enable_hca(dev);
955 dev_err(&pdev->dev, "enable hca failed\n");
956 goto err_pagealloc_cleanup;
959 #ifdef CONFIG_MLX5_CORE_EN
960 err = mlx5_core_set_issi(dev);
962 dev_err(&pdev->dev, "failed to set issi\n");
963 goto err_disable_hca;
967 err = mlx5_satisfy_startup_pages(dev, 1);
969 dev_err(&pdev->dev, "failed to allocate boot pages\n");
970 goto err_disable_hca;
973 err = set_hca_ctrl(dev);
975 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
976 goto reclaim_boot_pages;
979 err = handle_hca_cap(dev);
981 dev_err(&pdev->dev, "handle_hca_cap failed\n");
982 goto reclaim_boot_pages;
985 err = mlx5_satisfy_startup_pages(dev, 0);
987 dev_err(&pdev->dev, "failed to allocate init pages\n");
988 goto reclaim_boot_pages;
991 err = mlx5_pagealloc_start(dev);
993 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
994 goto reclaim_boot_pages;
997 err = mlx5_cmd_init_hca(dev);
999 dev_err(&pdev->dev, "init hca failed\n");
1000 goto err_pagealloc_stop;
1003 mlx5_start_health_poll(dev);
1005 err = mlx5_query_hca_caps(dev);
1007 dev_err(&pdev->dev, "query hca failed\n");
1011 err = mlx5_query_board_id(dev);
1013 dev_err(&pdev->dev, "query board id failed\n");
1017 err = mlx5_enable_msix(dev);
1019 dev_err(&pdev->dev, "enable msix failed\n");
1023 err = mlx5_eq_init(dev);
1025 dev_err(&pdev->dev, "failed to initialize eq\n");
1029 err = mlx5_alloc_uuars(dev, &priv->uuari);
1031 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1032 goto err_eq_cleanup;
1035 err = mlx5_start_eqs(dev);
1037 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1041 err = alloc_comp_eqs(dev);
1043 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1047 if (map_bf_area(dev))
1048 dev_err(&pdev->dev, "Failed to map blue flame area\n");
1050 err = mlx5_irq_set_affinity_hints(dev);
1052 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1053 goto err_unmap_bf_area;
1056 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1058 mlx5_init_cq_table(dev);
1059 mlx5_init_qp_table(dev);
1060 mlx5_init_srq_table(dev);
1061 mlx5_init_mr_table(dev);
1063 err = mlx5_register_device(dev);
1065 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1069 err = request_module_nowait(MLX5_IB_MOD);
1071 pr_info("failed request module on %s\n", MLX5_IB_MOD);
1073 dev->interface_state = MLX5_INTERFACE_STATE_UP;
1075 mutex_unlock(&dev->intf_state_mutex);
1080 mlx5_cleanup_mr_table(dev);
1081 mlx5_cleanup_srq_table(dev);
1082 mlx5_cleanup_qp_table(dev);
1083 mlx5_cleanup_cq_table(dev);
1084 mlx5_irq_clear_affinity_hints(dev);
1095 mlx5_free_uuars(dev, &priv->uuari);
1098 mlx5_eq_cleanup(dev);
1101 mlx5_disable_msix(dev);
1104 mlx5_stop_health_poll(dev);
1105 if (mlx5_cmd_teardown_hca(dev)) {
1106 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1111 mlx5_pagealloc_stop(dev);
1114 mlx5_reclaim_startup_pages(dev);
1117 mlx5_core_disable_hca(dev);
1119 err_pagealloc_cleanup:
1120 mlx5_pagealloc_cleanup(dev);
1121 mlx5_cmd_cleanup(dev);
1124 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1125 mutex_unlock(&dev->intf_state_mutex);
1130 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1134 mutex_lock(&dev->intf_state_mutex);
1135 if (dev->interface_state == MLX5_INTERFACE_STATE_DOWN) {
1136 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1140 mlx5_unregister_device(dev);
1141 mlx5_cleanup_mr_table(dev);
1142 mlx5_cleanup_srq_table(dev);
1143 mlx5_cleanup_qp_table(dev);
1144 mlx5_cleanup_cq_table(dev);
1145 mlx5_irq_clear_affinity_hints(dev);
1149 mlx5_free_uuars(dev, &priv->uuari);
1150 mlx5_eq_cleanup(dev);
1151 mlx5_disable_msix(dev);
1152 mlx5_stop_health_poll(dev);
1153 err = mlx5_cmd_teardown_hca(dev);
1155 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1158 mlx5_pagealloc_stop(dev);
1159 mlx5_reclaim_startup_pages(dev);
1160 mlx5_core_disable_hca(dev);
1161 mlx5_pagealloc_cleanup(dev);
1162 mlx5_cmd_cleanup(dev);
1165 dev->interface_state = MLX5_INTERFACE_STATE_DOWN;
1166 mutex_unlock(&dev->intf_state_mutex);
1170 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1171 unsigned long param)
1173 struct mlx5_priv *priv = &dev->priv;
1174 struct mlx5_device_context *dev_ctx;
1175 unsigned long flags;
1177 spin_lock_irqsave(&priv->ctx_lock, flags);
1179 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1180 if (dev_ctx->intf->event)
1181 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1183 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1186 struct mlx5_core_event_handler {
1187 void (*event)(struct mlx5_core_dev *dev,
1188 enum mlx5_dev_event event,
1193 static int init_one(struct pci_dev *pdev,
1194 const struct pci_device_id *id)
1196 struct mlx5_core_dev *dev;
1197 struct mlx5_priv *priv;
1200 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1202 dev_err(&pdev->dev, "kzalloc failed\n");
1207 pci_set_drvdata(pdev, dev);
1209 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profile)) {
1210 pr_warn("selected profile out of range, selecting default (%d)\n",
1212 prof_sel = MLX5_DEFAULT_PROF;
1214 dev->profile = &profile[prof_sel];
1216 dev->event = mlx5_core_event;
1218 INIT_LIST_HEAD(&priv->ctx_list);
1219 spin_lock_init(&priv->ctx_lock);
1220 mutex_init(&dev->pci_status_mutex);
1221 mutex_init(&dev->intf_state_mutex);
1222 err = mlx5_pci_init(dev, priv);
1224 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1228 err = mlx5_health_init(dev);
1230 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1234 err = mlx5_load_one(dev, priv);
1236 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1243 mlx5_health_cleanup(dev);
1245 mlx5_pci_close(dev, priv);
1247 pci_set_drvdata(pdev, NULL);
1253 static void remove_one(struct pci_dev *pdev)
1255 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1256 struct mlx5_priv *priv = &dev->priv;
1258 if (mlx5_unload_one(dev, priv)) {
1259 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1260 mlx5_health_cleanup(dev);
1263 mlx5_health_cleanup(dev);
1264 mlx5_pci_close(dev, priv);
1265 pci_set_drvdata(pdev, NULL);
1269 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1270 pci_channel_state_t state)
1272 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1273 struct mlx5_priv *priv = &dev->priv;
1275 dev_info(&pdev->dev, "%s was called\n", __func__);
1276 mlx5_enter_error_state(dev);
1277 mlx5_unload_one(dev, priv);
1278 mlx5_pci_disable_device(dev);
1279 return state == pci_channel_io_perm_failure ?
1280 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1283 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1285 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1288 dev_info(&pdev->dev, "%s was called\n", __func__);
1290 err = mlx5_pci_enable_device(dev);
1292 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1294 return PCI_ERS_RESULT_DISCONNECT;
1296 pci_set_master(pdev);
1297 pci_set_power_state(pdev, PCI_D0);
1298 pci_restore_state(pdev);
1300 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1303 void mlx5_disable_device(struct mlx5_core_dev *dev)
1305 mlx5_pci_err_detected(dev->pdev, 0);
1308 /* wait for the device to show vital signs. For now we check
1309 * that we can read the device ID and that the health buffer
1310 * shows a non zero value which is different than 0xffffffff
1312 static void wait_vital(struct pci_dev *pdev)
1314 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1315 struct mlx5_core_health *health = &dev->priv.health;
1316 const int niter = 100;
1321 /* Wait for firmware to be ready after reset */
1323 for (i = 0; i < niter; i++) {
1324 if (pci_read_config_word(pdev, 2, &did)) {
1325 dev_warn(&pdev->dev, "failed reading config word\n");
1328 if (did == pdev->device) {
1329 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1335 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1337 for (i = 0; i < niter; i++) {
1338 count = ioread32be(health->health_counter);
1339 if (count && count != 0xffffffff) {
1340 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1347 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1350 static void mlx5_pci_resume(struct pci_dev *pdev)
1352 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1353 struct mlx5_priv *priv = &dev->priv;
1356 dev_info(&pdev->dev, "%s was called\n", __func__);
1358 pci_save_state(pdev);
1361 err = mlx5_load_one(dev, priv);
1363 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1366 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1369 static const struct pci_error_handlers mlx5_err_handler = {
1370 .error_detected = mlx5_pci_err_detected,
1371 .slot_reset = mlx5_pci_slot_reset,
1372 .resume = mlx5_pci_resume
1375 static const struct pci_device_id mlx5_core_pci_table[] = {
1376 { PCI_VDEVICE(MELLANOX, 0x1011) }, /* Connect-IB */
1377 { PCI_VDEVICE(MELLANOX, 0x1012) }, /* Connect-IB VF */
1378 { PCI_VDEVICE(MELLANOX, 0x1013) }, /* ConnectX-4 */
1379 { PCI_VDEVICE(MELLANOX, 0x1014) }, /* ConnectX-4 VF */
1380 { PCI_VDEVICE(MELLANOX, 0x1015) }, /* ConnectX-4LX */
1381 { PCI_VDEVICE(MELLANOX, 0x1016) }, /* ConnectX-4LX VF */
1385 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1387 static struct pci_driver mlx5_core_driver = {
1388 .name = DRIVER_NAME,
1389 .id_table = mlx5_core_pci_table,
1391 .remove = remove_one,
1392 .err_handler = &mlx5_err_handler
1395 static int __init init(void)
1399 mlx5_register_debugfs();
1401 err = pci_register_driver(&mlx5_core_driver);
1405 #ifdef CONFIG_MLX5_CORE_EN
1412 mlx5_unregister_debugfs();
1416 static void __exit cleanup(void)
1418 #ifdef CONFIG_MLX5_CORE_EN
1421 pci_unregister_driver(&mlx5_core_driver);
1422 mlx5_unregister_debugfs();
1426 module_exit(cleanup);