2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/errno.h>
34 #include <linux/if_ether.h>
35 #include <linux/export.h>
37 #include <linux/mlx4/cmd.h>
41 #define MLX4_MAC_VALID (1ull << 63)
43 #define MLX4_VLAN_VALID (1u << 31)
44 #define MLX4_VLAN_MASK 0xfff
46 #define MLX4_STATS_TRAFFIC_COUNTERS_MASK 0xfULL
47 #define MLX4_STATS_TRAFFIC_DROPS_MASK 0xc0ULL
48 #define MLX4_STATS_ERROR_COUNTERS_MASK 0x1ffc30ULL
49 #define MLX4_STATS_PORT_COUNTERS_MASK 0x1fe00000ULL
51 void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table)
55 mutex_init(&table->mutex);
56 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
57 table->entries[i] = 0;
60 table->max = 1 << dev->caps.log_num_macs;
64 void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table)
68 mutex_init(&table->mutex);
69 for (i = 0; i < MLX4_MAX_VLAN_NUM; i++) {
70 table->entries[i] = 0;
73 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR;
77 static int mlx4_uc_steer_add(struct mlx4_dev *dev, u8 port,
78 u64 mac, int *qpn, u64 *reg_id)
84 be_mac = cpu_to_be64(mac << 16);
86 switch (dev->caps.steering_mode) {
87 case MLX4_STEERING_MODE_B0: {
92 memcpy(&gid[10], &be_mac, ETH_ALEN);
95 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
98 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
99 struct mlx4_spec_list spec_eth = { {NULL} };
100 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
102 struct mlx4_net_trans_rule rule = {
103 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
106 .promisc_mode = MLX4_FS_PROMISC_NONE,
107 .priority = MLX4_DOMAIN_NIC,
112 INIT_LIST_HEAD(&rule.list);
114 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
115 memcpy(spec_eth.eth.dst_mac, &be_mac, ETH_ALEN);
116 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
117 list_add_tail(&spec_eth.list, &rule.list);
119 err = mlx4_flow_attach(dev, &rule, reg_id);
126 mlx4_warn(dev, "Failed Attaching Unicast\n");
131 static void mlx4_uc_steer_release(struct mlx4_dev *dev, u8 port,
132 u64 mac, int qpn, u64 reg_id)
134 switch (dev->caps.steering_mode) {
135 case MLX4_STEERING_MODE_B0: {
141 mac &= MLX4_MAC_MASK;
142 be_mac = cpu_to_be64(mac << 16);
143 memcpy(&gid[10], &be_mac, ETH_ALEN);
146 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
149 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
150 mlx4_flow_detach(dev, reg_id);
154 mlx4_err(dev, "Invalid steering mode.\n");
158 static int validate_index(struct mlx4_dev *dev,
159 struct mlx4_mac_table *table, int index)
163 if (index < 0 || index >= table->max || !table->entries[index]) {
164 mlx4_warn(dev, "No valid Mac entry for the given index\n");
170 static int find_index(struct mlx4_dev *dev,
171 struct mlx4_mac_table *table, u64 mac)
175 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
176 if ((mac & MLX4_MAC_MASK) ==
177 (MLX4_MAC_MASK & be64_to_cpu(table->entries[i])))
184 int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn)
186 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
187 struct mlx4_mac_entry *entry;
192 mlx4_dbg(dev, "Registering MAC: 0x%llx for adding\n",
193 (unsigned long long) mac);
194 index = mlx4_register_mac(dev, port, mac);
197 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
198 (unsigned long long) mac);
202 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
203 *qpn = info->base_qpn + index;
207 err = mlx4_qp_reserve_range(dev, 1, 1, qpn);
208 mlx4_dbg(dev, "Reserved qp %d\n", *qpn);
210 mlx4_err(dev, "Failed to reserve qp for mac registration\n");
214 err = mlx4_uc_steer_add(dev, port, mac, qpn, ®_id);
218 entry = kmalloc(sizeof *entry, GFP_KERNEL);
224 entry->reg_id = reg_id;
225 err = radix_tree_insert(&info->mac_tree, *qpn, entry);
234 mlx4_uc_steer_release(dev, port, mac, *qpn, reg_id);
237 mlx4_qp_release_range(dev, *qpn, 1);
240 mlx4_unregister_mac(dev, port, mac);
243 EXPORT_SYMBOL_GPL(mlx4_get_eth_qp);
245 void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn)
247 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
248 struct mlx4_mac_entry *entry;
250 mlx4_dbg(dev, "Registering MAC: 0x%llx for deleting\n",
251 (unsigned long long) mac);
252 mlx4_unregister_mac(dev, port, mac);
254 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
255 entry = radix_tree_lookup(&info->mac_tree, qpn);
257 mlx4_dbg(dev, "Releasing qp: port %d, mac 0x%llx,"
259 (unsigned long long) mac, qpn);
260 mlx4_uc_steer_release(dev, port, entry->mac,
262 mlx4_qp_release_range(dev, qpn, 1);
263 radix_tree_delete(&info->mac_tree, qpn);
268 EXPORT_SYMBOL_GPL(mlx4_put_eth_qp);
270 static int mlx4_set_port_mac_table(struct mlx4_dev *dev, u8 port,
273 struct mlx4_cmd_mailbox *mailbox;
277 mailbox = mlx4_alloc_cmd_mailbox(dev);
279 return PTR_ERR(mailbox);
281 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE);
283 in_mod = MLX4_SET_PORT_MAC_TABLE << 8 | port;
285 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
286 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
288 mlx4_free_cmd_mailbox(dev, mailbox);
292 int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
294 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
295 struct mlx4_mac_table *table = &info->mac_table;
299 mlx4_dbg(dev, "Registering MAC: 0x%llx for port %d\n",
300 (unsigned long long) mac, port);
302 mutex_lock(&table->mutex);
303 for (i = 0; i < MLX4_MAX_MAC_NUM; i++) {
304 if (free < 0 && !table->entries[i]) {
309 if (mac == (MLX4_MAC_MASK & be64_to_cpu(table->entries[i]))) {
310 /* MAC already registered, Must not have duplicates */
316 mlx4_dbg(dev, "Free MAC index is %d\n", free);
318 if (table->total == table->max) {
319 /* No free mac entries */
324 /* Register new MAC */
325 table->entries[free] = cpu_to_be64(mac | MLX4_MAC_VALID);
327 err = mlx4_set_port_mac_table(dev, port, table->entries);
329 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
330 (unsigned long long) mac);
331 table->entries[free] = 0;
338 mutex_unlock(&table->mutex);
341 EXPORT_SYMBOL_GPL(__mlx4_register_mac);
343 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac)
348 if (mlx4_is_mfunc(dev)) {
349 set_param_l(&out_param, port);
350 err = mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
351 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
352 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
356 return get_param_l(&out_param);
358 return __mlx4_register_mac(dev, port, mac);
360 EXPORT_SYMBOL_GPL(mlx4_register_mac);
363 void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
365 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
366 struct mlx4_mac_table *table = &info->mac_table;
369 index = find_index(dev, table, mac);
371 mutex_lock(&table->mutex);
373 if (validate_index(dev, table, index))
376 table->entries[index] = 0;
377 mlx4_set_port_mac_table(dev, port, table->entries);
380 mutex_unlock(&table->mutex);
382 EXPORT_SYMBOL_GPL(__mlx4_unregister_mac);
384 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac)
388 if (mlx4_is_mfunc(dev)) {
389 set_param_l(&out_param, port);
390 (void) mlx4_cmd_imm(dev, mac, &out_param, RES_MAC,
391 RES_OP_RESERVE_AND_MAP, MLX4_CMD_FREE_RES,
392 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
395 __mlx4_unregister_mac(dev, port, mac);
398 EXPORT_SYMBOL_GPL(mlx4_unregister_mac);
400 int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac)
402 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
403 struct mlx4_mac_table *table = &info->mac_table;
404 struct mlx4_mac_entry *entry;
405 int index = qpn - info->base_qpn;
408 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
409 entry = radix_tree_lookup(&info->mac_tree, qpn);
412 mlx4_uc_steer_release(dev, port, entry->mac,
414 mlx4_unregister_mac(dev, port, entry->mac);
415 entry->mac = new_mac;
417 mlx4_register_mac(dev, port, new_mac);
418 err = mlx4_uc_steer_add(dev, port, entry->mac,
419 &qpn, &entry->reg_id);
423 /* CX1 doesn't support multi-functions */
424 mutex_lock(&table->mutex);
426 err = validate_index(dev, table, index);
430 table->entries[index] = cpu_to_be64(new_mac | MLX4_MAC_VALID);
432 err = mlx4_set_port_mac_table(dev, port, table->entries);
434 mlx4_err(dev, "Failed adding MAC: 0x%llx\n",
435 (unsigned long long) new_mac);
436 table->entries[index] = 0;
439 mutex_unlock(&table->mutex);
442 EXPORT_SYMBOL_GPL(mlx4_replace_mac);
444 static int mlx4_set_port_vlan_table(struct mlx4_dev *dev, u8 port,
447 struct mlx4_cmd_mailbox *mailbox;
451 mailbox = mlx4_alloc_cmd_mailbox(dev);
453 return PTR_ERR(mailbox);
455 memcpy(mailbox->buf, entries, MLX4_VLAN_TABLE_SIZE);
456 in_mod = MLX4_SET_PORT_VLAN_TABLE << 8 | port;
457 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
458 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
460 mlx4_free_cmd_mailbox(dev, mailbox);
465 int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx)
467 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
470 for (i = 0; i < MLX4_MAX_VLAN_NUM; ++i) {
471 if (table->refs[i] &&
472 (vid == (MLX4_VLAN_MASK &
473 be32_to_cpu(table->entries[i])))) {
474 /* VLAN already registered, increase reference count */
482 EXPORT_SYMBOL_GPL(mlx4_find_cached_vlan);
484 static int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan,
487 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
491 mutex_lock(&table->mutex);
493 if (table->total == table->max) {
494 /* No free vlan entries */
499 for (i = MLX4_VLAN_REGULAR; i < MLX4_MAX_VLAN_NUM; i++) {
500 if (free < 0 && (table->refs[i] == 0)) {
505 if (table->refs[i] &&
506 (vlan == (MLX4_VLAN_MASK &
507 be32_to_cpu(table->entries[i])))) {
508 /* Vlan already registered, increase references count */
520 /* Register new VLAN */
521 table->refs[free] = 1;
522 table->entries[free] = cpu_to_be32(vlan | MLX4_VLAN_VALID);
524 err = mlx4_set_port_vlan_table(dev, port, table->entries);
526 mlx4_warn(dev, "Failed adding vlan: %u\n", vlan);
527 table->refs[free] = 0;
528 table->entries[free] = 0;
535 mutex_unlock(&table->mutex);
539 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index)
544 if (mlx4_is_mfunc(dev)) {
545 set_param_l(&out_param, port);
546 err = mlx4_cmd_imm(dev, vlan, &out_param, RES_VLAN,
547 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
548 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
550 *index = get_param_l(&out_param);
554 return __mlx4_register_vlan(dev, port, vlan, index);
556 EXPORT_SYMBOL_GPL(mlx4_register_vlan);
558 static void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
560 struct mlx4_vlan_table *table = &mlx4_priv(dev)->port[port].vlan_table;
562 if (index < MLX4_VLAN_REGULAR) {
563 mlx4_warn(dev, "Trying to free special vlan index %d\n", index);
567 mutex_lock(&table->mutex);
568 if (!table->refs[index]) {
569 mlx4_warn(dev, "No vlan entry for index %d\n", index);
572 if (--table->refs[index]) {
573 mlx4_dbg(dev, "Have more references for index %d,"
574 "no need to modify vlan table\n", index);
577 table->entries[index] = 0;
578 mlx4_set_port_vlan_table(dev, port, table->entries);
581 mutex_unlock(&table->mutex);
584 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index)
589 if (mlx4_is_mfunc(dev)) {
590 set_param_l(&in_param, port);
591 err = mlx4_cmd(dev, in_param, RES_VLAN, RES_OP_RESERVE_AND_MAP,
592 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
595 mlx4_warn(dev, "Failed freeing vlan at index:%d\n",
600 __mlx4_unregister_vlan(dev, port, index);
602 EXPORT_SYMBOL_GPL(mlx4_unregister_vlan);
604 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps)
606 struct mlx4_cmd_mailbox *inmailbox, *outmailbox;
610 inmailbox = mlx4_alloc_cmd_mailbox(dev);
611 if (IS_ERR(inmailbox))
612 return PTR_ERR(inmailbox);
614 outmailbox = mlx4_alloc_cmd_mailbox(dev);
615 if (IS_ERR(outmailbox)) {
616 mlx4_free_cmd_mailbox(dev, inmailbox);
617 return PTR_ERR(outmailbox);
620 inbuf = inmailbox->buf;
621 outbuf = outmailbox->buf;
622 memset(inbuf, 0, 256);
623 memset(outbuf, 0, 256);
628 *(__be16 *) (&inbuf[16]) = cpu_to_be16(0x0015);
629 *(__be32 *) (&inbuf[20]) = cpu_to_be32(port);
631 err = mlx4_cmd_box(dev, inmailbox->dma, outmailbox->dma, port, 3,
632 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
635 *caps = *(__be32 *) (outbuf + 84);
636 mlx4_free_cmd_mailbox(dev, inmailbox);
637 mlx4_free_cmd_mailbox(dev, outmailbox);
641 static int mlx4_common_set_port(struct mlx4_dev *dev, int slave, u32 in_mod,
642 u8 op_mod, struct mlx4_cmd_mailbox *inbox)
644 struct mlx4_priv *priv = mlx4_priv(dev);
645 struct mlx4_port_info *port_info;
646 struct mlx4_mfunc_master_ctx *master = &priv->mfunc.master;
647 struct mlx4_slave_state *slave_st = &master->slave_state[slave];
648 struct mlx4_set_port_rqp_calc_context *qpn_context;
649 struct mlx4_set_port_general_context *gen_context;
650 int reset_qkey_viols;
659 __be32 slave_cap_mask;
662 port = in_mod & 0xff;
663 in_modifier = in_mod >> 8;
665 port_info = &priv->port[port];
667 /* Slaves cannot perform SET_PORT operations except changing MTU */
669 if (slave != dev->caps.function &&
670 in_modifier != MLX4_SET_PORT_GENERAL) {
671 mlx4_warn(dev, "denying SET_PORT for slave:%d\n",
675 switch (in_modifier) {
676 case MLX4_SET_PORT_RQP_CALC:
677 qpn_context = inbox->buf;
678 qpn_context->base_qpn =
679 cpu_to_be32(port_info->base_qpn);
680 qpn_context->n_mac = 0x7;
681 promisc = be32_to_cpu(qpn_context->promisc) >>
682 SET_PORT_PROMISC_SHIFT;
683 qpn_context->promisc = cpu_to_be32(
684 promisc << SET_PORT_PROMISC_SHIFT |
685 port_info->base_qpn);
686 promisc = be32_to_cpu(qpn_context->mcast) >>
687 SET_PORT_MC_PROMISC_SHIFT;
688 qpn_context->mcast = cpu_to_be32(
689 promisc << SET_PORT_MC_PROMISC_SHIFT |
690 port_info->base_qpn);
692 case MLX4_SET_PORT_GENERAL:
693 gen_context = inbox->buf;
694 /* Mtu is configured as the max MTU among all the
695 * the functions on the port. */
696 mtu = be16_to_cpu(gen_context->mtu);
697 mtu = min_t(int, mtu, dev->caps.eth_mtu_cap[port]);
698 prev_mtu = slave_st->mtu[port];
699 slave_st->mtu[port] = mtu;
700 if (mtu > master->max_mtu[port])
701 master->max_mtu[port] = mtu;
702 if (mtu < prev_mtu && prev_mtu ==
703 master->max_mtu[port]) {
704 slave_st->mtu[port] = mtu;
705 master->max_mtu[port] = mtu;
706 for (i = 0; i < dev->num_slaves; i++) {
707 master->max_mtu[port] =
708 max(master->max_mtu[port],
709 master->slave_state[i].mtu[port]);
713 gen_context->mtu = cpu_to_be16(master->max_mtu[port]);
716 return mlx4_cmd(dev, inbox->dma, in_mod, op_mod,
717 MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
721 /* For IB, we only consider:
722 * - The capability mask, which is set to the aggregate of all
723 * slave function capabilities
724 * - The QKey violatin counter - reset according to each request.
727 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
728 reset_qkey_viols = (*(u8 *) inbox->buf) & 0x40;
729 new_cap_mask = ((__be32 *) inbox->buf)[2];
731 reset_qkey_viols = ((u8 *) inbox->buf)[3] & 0x1;
732 new_cap_mask = ((__be32 *) inbox->buf)[1];
737 priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
738 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] = new_cap_mask;
739 for (i = 0; i < dev->num_slaves; i++)
741 priv->mfunc.master.slave_state[i].ib_cap_mask[port];
743 /* only clear mailbox for guests. Master may be setting
744 * MTU or PKEY table size
746 if (slave != dev->caps.function)
747 memset(inbox->buf, 0, 256);
748 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
749 *(u8 *) inbox->buf |= !!reset_qkey_viols << 6;
750 ((__be32 *) inbox->buf)[2] = agg_cap_mask;
752 ((u8 *) inbox->buf)[3] |= !!reset_qkey_viols;
753 ((__be32 *) inbox->buf)[1] = agg_cap_mask;
756 err = mlx4_cmd(dev, inbox->dma, port, is_eth, MLX4_CMD_SET_PORT,
757 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
759 priv->mfunc.master.slave_state[slave].ib_cap_mask[port] =
764 int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
765 struct mlx4_vhcr *vhcr,
766 struct mlx4_cmd_mailbox *inbox,
767 struct mlx4_cmd_mailbox *outbox,
768 struct mlx4_cmd_info *cmd)
770 return mlx4_common_set_port(dev, slave, vhcr->in_modifier,
771 vhcr->op_modifier, inbox);
774 /* bit locations for set port command with zero op modifier */
776 MLX4_SET_PORT_VL_CAP = 4, /* bits 7:4 */
777 MLX4_SET_PORT_MTU_CAP = 12, /* bits 15:12 */
778 MLX4_CHANGE_PORT_PKEY_TBL_SZ = 20,
779 MLX4_CHANGE_PORT_VL_CAP = 21,
780 MLX4_CHANGE_PORT_MTU_CAP = 22,
783 int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz)
785 struct mlx4_cmd_mailbox *mailbox;
786 int err, vl_cap, pkey_tbl_flag = 0;
788 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
791 mailbox = mlx4_alloc_cmd_mailbox(dev);
793 return PTR_ERR(mailbox);
795 memset(mailbox->buf, 0, 256);
797 ((__be32 *) mailbox->buf)[1] = dev->caps.ib_port_def_cap[port];
799 if (pkey_tbl_sz >= 0 && mlx4_is_master(dev)) {
801 ((__be16 *) mailbox->buf)[20] = cpu_to_be16(pkey_tbl_sz);
804 /* IB VL CAP enum isn't used by the firmware, just numerical values */
805 for (vl_cap = 8; vl_cap >= 1; vl_cap >>= 1) {
806 ((__be32 *) mailbox->buf)[0] = cpu_to_be32(
807 (1 << MLX4_CHANGE_PORT_MTU_CAP) |
808 (1 << MLX4_CHANGE_PORT_VL_CAP) |
809 (pkey_tbl_flag << MLX4_CHANGE_PORT_PKEY_TBL_SZ) |
810 (dev->caps.port_ib_mtu[port] << MLX4_SET_PORT_MTU_CAP) |
811 (vl_cap << MLX4_SET_PORT_VL_CAP));
812 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_SET_PORT,
813 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
818 mlx4_free_cmd_mailbox(dev, mailbox);
822 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
823 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx)
825 struct mlx4_cmd_mailbox *mailbox;
826 struct mlx4_set_port_general_context *context;
830 mailbox = mlx4_alloc_cmd_mailbox(dev);
832 return PTR_ERR(mailbox);
833 context = mailbox->buf;
834 memset(context, 0, sizeof *context);
836 context->flags = SET_PORT_GEN_ALL_VALID;
837 context->mtu = cpu_to_be16(mtu);
838 context->pptx = (pptx * (!pfctx)) << 7;
839 context->pfctx = pfctx;
840 context->pprx = (pprx * (!pfcrx)) << 7;
841 context->pfcrx = pfcrx;
843 in_mod = MLX4_SET_PORT_GENERAL << 8 | port;
844 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
845 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
847 mlx4_free_cmd_mailbox(dev, mailbox);
850 EXPORT_SYMBOL(mlx4_SET_PORT_general);
852 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
855 struct mlx4_cmd_mailbox *mailbox;
856 struct mlx4_set_port_rqp_calc_context *context;
859 u32 m_promisc = (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) ?
860 MCAST_DIRECT : MCAST_DEFAULT;
862 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
865 mailbox = mlx4_alloc_cmd_mailbox(dev);
867 return PTR_ERR(mailbox);
868 context = mailbox->buf;
869 memset(context, 0, sizeof *context);
871 context->base_qpn = cpu_to_be32(base_qpn);
872 context->n_mac = dev->caps.log_num_macs;
873 context->promisc = cpu_to_be32(promisc << SET_PORT_PROMISC_SHIFT |
875 context->mcast = cpu_to_be32(m_promisc << SET_PORT_MC_PROMISC_SHIFT |
877 context->intra_no_vlan = 0;
878 context->no_vlan = MLX4_NO_VLAN_IDX;
879 context->intra_vlan_miss = 0;
880 context->vlan_miss = MLX4_VLAN_MISS_IDX;
882 in_mod = MLX4_SET_PORT_RQP_CALC << 8 | port;
883 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
884 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_WRAPPED);
886 mlx4_free_cmd_mailbox(dev, mailbox);
889 EXPORT_SYMBOL(mlx4_SET_PORT_qpn_calc);
891 int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc)
893 struct mlx4_cmd_mailbox *mailbox;
894 struct mlx4_set_port_prio2tc_context *context;
899 mailbox = mlx4_alloc_cmd_mailbox(dev);
901 return PTR_ERR(mailbox);
902 context = mailbox->buf;
903 memset(context, 0, sizeof *context);
905 for (i = 0; i < MLX4_NUM_UP; i += 2)
906 context->prio2tc[i >> 1] = prio2tc[i] << 4 | prio2tc[i + 1];
908 in_mod = MLX4_SET_PORT_PRIO2TC << 8 | port;
909 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
910 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
912 mlx4_free_cmd_mailbox(dev, mailbox);
915 EXPORT_SYMBOL(mlx4_SET_PORT_PRIO2TC);
917 int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
918 u8 *pg, u16 *ratelimit)
920 struct mlx4_cmd_mailbox *mailbox;
921 struct mlx4_set_port_scheduler_context *context;
926 mailbox = mlx4_alloc_cmd_mailbox(dev);
928 return PTR_ERR(mailbox);
929 context = mailbox->buf;
930 memset(context, 0, sizeof *context);
932 for (i = 0; i < MLX4_NUM_TC; i++) {
933 struct mlx4_port_scheduler_tc_cfg_be *tc = &context->tc[i];
934 u16 r = ratelimit && ratelimit[i] ? ratelimit[i] :
935 MLX4_RATELIMIT_DEFAULT;
937 tc->pg = htons(pg[i]);
938 tc->bw_precentage = htons(tc_tx_bw[i]);
940 tc->max_bw_units = htons(MLX4_RATELIMIT_UNITS);
941 tc->max_bw_value = htons(r);
944 in_mod = MLX4_SET_PORT_SCHEDULER << 8 | port;
945 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT,
946 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
948 mlx4_free_cmd_mailbox(dev, mailbox);
951 EXPORT_SYMBOL(mlx4_SET_PORT_SCHEDULER);
953 int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
954 struct mlx4_vhcr *vhcr,
955 struct mlx4_cmd_mailbox *inbox,
956 struct mlx4_cmd_mailbox *outbox,
957 struct mlx4_cmd_info *cmd)
964 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port,
965 u64 mac, u64 clear, u8 mode)
967 return mlx4_cmd(dev, (mac | (clear << 63)), port, mode,
968 MLX4_CMD_SET_MCAST_FLTR, MLX4_CMD_TIME_CLASS_B,
971 EXPORT_SYMBOL(mlx4_SET_MCAST_FLTR);
973 int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
974 struct mlx4_vhcr *vhcr,
975 struct mlx4_cmd_mailbox *inbox,
976 struct mlx4_cmd_mailbox *outbox,
977 struct mlx4_cmd_info *cmd)
984 int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave,
985 u32 in_mod, struct mlx4_cmd_mailbox *outbox)
987 return mlx4_cmd_box(dev, 0, outbox->dma, in_mod, 0,
988 MLX4_CMD_DUMP_ETH_STATS, MLX4_CMD_TIME_CLASS_B,
992 int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
993 struct mlx4_vhcr *vhcr,
994 struct mlx4_cmd_mailbox *inbox,
995 struct mlx4_cmd_mailbox *outbox,
996 struct mlx4_cmd_info *cmd)
998 if (slave != dev->caps.function)
1000 return mlx4_common_dump_eth_stats(dev, slave,
1001 vhcr->in_modifier, outbox);
1004 void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap)
1006 if (!mlx4_is_mfunc(dev)) {
1011 *stats_bitmap = (MLX4_STATS_TRAFFIC_COUNTERS_MASK |
1012 MLX4_STATS_TRAFFIC_DROPS_MASK |
1013 MLX4_STATS_PORT_COUNTERS_MASK);
1015 if (mlx4_is_master(dev))
1016 *stats_bitmap |= MLX4_STATS_ERROR_COUNTERS_MASK;
1018 EXPORT_SYMBOL(mlx4_set_stats_bitmap);