drivers/net/ethernet/mellanox/mlx4/main.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  */
  35
  36 #include <linux/module.h>
  37 #include <linux/init.h>
  38 #include <linux/errno.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-mapping.h>
  41 #include <linux/slab.h>
  42 #include <linux/io-mapping.h>
  43
  44 #include <linux/mlx4/device.h>
  45 #include <linux/mlx4/doorbell.h>
  46
  47 #include "mlx4.h"
  48 #include "fw.h"
  49 #include "icm.h"
  50
  51 MODULE_AUTHOR("Roland Dreier");
  52 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
  53 MODULE_LICENSE("Dual BSD/GPL");
  54 MODULE_VERSION(DRV_VERSION);
  55
  56 struct workqueue_struct *mlx4_wq;
  57
  58 #ifdef CONFIG_MLX4_DEBUG
  59
  60 int mlx4_debug_level = 0;
  61 module_param_named(debug_level, mlx4_debug_level, int, 0644);
  62 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
  63
  64 #endif /* CONFIG_MLX4_DEBUG */
  65
  66 #ifdef CONFIG_PCI_MSI
  67
  68 static int msi_x = 1;
  69 module_param(msi_x, int, 0444);
  70 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
  71
  72 #else /* CONFIG_PCI_MSI */
  73
  74 #define msi_x (0)
  75
  76 #endif /* CONFIG_PCI_MSI */
  77
  78 int mlx4_log_num_mgm_entry_size = 10;
  79 module_param_named(log_num_mgm_entry_size,
  80                         mlx4_log_num_mgm_entry_size, int, 0444);
  81 MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
  82                                          " of qp per mcg, for example:"
  83                                          " 10 gives 248.range: 9<="
  84                                          " log_num_mgm_entry_size <= 12");
  85
  86 static char mlx4_version[] __devinitdata =
  87         DRV_NAME ": Mellanox ConnectX core driver v"
  88         DRV_VERSION " (" DRV_RELDATE ")\n";
  89
  90 static struct mlx4_profile default_profile = {
  91         .num_qp         = 1 << 17,
  92         .num_srq        = 1 << 16,
  93         .rdmarc_per_qp  = 1 << 4,
  94         .num_cq         = 1 << 16,
  95         .num_mcg        = 1 << 13,
  96         .num_mpt        = 1 << 17,
  97         .num_mtt        = 1 << 20,
  98 };
  99
 100 static int log_num_mac = 2;
 101 module_param_named(log_num_mac, log_num_mac, int, 0444);
 102 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
 103
 104 static int log_num_vlan;
 105 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
 106 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
 107 /* Log2 max number of VLANs per ETH port (0-7) */
 108 #define MLX4_LOG_NUM_VLANS 7
 109
 110 static int use_prio;
 111 module_param_named(use_prio, use_prio, bool, 0444);
 112 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
 113                   "(0/1, default 0)");
 114
 115 int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
 116 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
 117 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
 118
 119 int mlx4_check_port_params(struct mlx4_dev *dev,
 120                            enum mlx4_port_type *port_type)
 121 {
 122         int i;
 123
 124         for (i = 0; i < dev->caps.num_ports - 1; i++) {
 125                 if (port_type[i] != port_type[i + 1]) {
 126                         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 127                                 mlx4_err(dev, "Only same port types supported "
 128                                          "on this HCA, aborting.\n");
 129                                 return -EINVAL;
 130                         }
 131                         if (port_type[i] == MLX4_PORT_TYPE_ETH &&
 132                             port_type[i + 1] == MLX4_PORT_TYPE_IB)
 133                                 return -EINVAL;
 134                 }
 135         }
 136
 137         for (i = 0; i < dev->caps.num_ports; i++) {
 138                 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
 139                         mlx4_err(dev, "Requested port type for port %d is not "
 140                                       "supported on this HCA\n", i + 1);
 141                         return -EINVAL;
 142                 }
 143         }
 144         return 0;
 145 }
 146
 147 static void mlx4_set_port_mask(struct mlx4_dev *dev)
 148 {
 149         int i;
 150
 151         for (i = 1; i <= dev->caps.num_ports; ++i)
 152                 dev->caps.port_mask[i] = dev->caps.port_type[i];
 153 }
 154
 155 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
 156 {
 157         int err;
 158         int i;
 159
 160         err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
 161         if (err) {
 162                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 163                 return err;
 164         }
 165
 166         if (dev_cap->min_page_sz > PAGE_SIZE) {
 167                 mlx4_err(dev, "HCA minimum page size of %d bigger than "
 168                          "kernel PAGE_SIZE of %ld, aborting.\n",
 169                          dev_cap->min_page_sz, PAGE_SIZE);
 170                 return -ENODEV;
 171         }
 172         if (dev_cap->num_ports > MLX4_MAX_PORTS) {
 173                 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
 174                          "aborting.\n",
 175                          dev_cap->num_ports, MLX4_MAX_PORTS);
 176                 return -ENODEV;
 177         }
 178
 179         if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
 180                 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
 181                          "PCI resource 2 size of 0x%llx, aborting.\n",
 182                          dev_cap->uar_size,
 183                          (unsigned long long) pci_resource_len(dev->pdev, 2));
 184                 return -ENODEV;
 185         }
 186
 187         dev->caps.num_ports          = dev_cap->num_ports;
 188         for (i = 1; i <= dev->caps.num_ports; ++i) {
 189                 dev->caps.vl_cap[i]         = dev_cap->max_vl[i];
 190                 dev->caps.ib_mtu_cap[i]     = dev_cap->ib_mtu[i];
 191                 dev->caps.gid_table_len[i]  = dev_cap->max_gids[i];
 192                 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
 193                 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
 194                 dev->caps.eth_mtu_cap[i]    = dev_cap->eth_mtu[i];
 195                 dev->caps.def_mac[i]        = dev_cap->def_mac[i];
 196                 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
 197                 dev->caps.trans_type[i]     = dev_cap->trans_type[i];
 198                 dev->caps.vendor_oui[i]     = dev_cap->vendor_oui[i];
 199                 dev->caps.wavelength[i]     = dev_cap->wavelength[i];
 200                 dev->caps.trans_code[i]     = dev_cap->trans_code[i];
 201         }
 202
 203         dev->caps.num_uars           = dev_cap->uar_size / PAGE_SIZE;
 204         dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
 205         dev->caps.bf_reg_size        = dev_cap->bf_reg_size;
 206         dev->caps.bf_regs_per_page   = dev_cap->bf_regs_per_page;
 207         dev->caps.max_sq_sg          = dev_cap->max_sq_sg;
 208         dev->caps.max_rq_sg          = dev_cap->max_rq_sg;
 209         dev->caps.max_wqes           = dev_cap->max_qp_sz;
 210         dev->caps.max_qp_init_rdma   = dev_cap->max_requester_per_qp;
 211         dev->caps.max_srq_wqes       = dev_cap->max_srq_sz;
 212         dev->caps.max_srq_sge        = dev_cap->max_rq_sg - 1;
 213         dev->caps.reserved_srqs      = dev_cap->reserved_srqs;
 214         dev->caps.max_sq_desc_sz     = dev_cap->max_sq_desc_sz;
 215         dev->caps.max_rq_desc_sz     = dev_cap->max_rq_desc_sz;
 216         dev->caps.num_qp_per_mgm     = mlx4_get_qp_per_mgm(dev);
 217         /*
 218          * Subtract 1 from the limit because we need to allocate a
 219          * spare CQE so the HCA HW can tell the difference between an
 220          * empty CQ and a full CQ.
 221          */
 222         dev->caps.max_cqes           = dev_cap->max_cq_sz - 1;
 223         dev->caps.reserved_cqs       = dev_cap->reserved_cqs;
 224         dev->caps.reserved_eqs       = dev_cap->reserved_eqs;
 225         dev->caps.reserved_mtts      = dev_cap->reserved_mtts;
 226         dev->caps.reserved_mrws      = dev_cap->reserved_mrws;
 227         dev->caps.reserved_uars      = dev_cap->reserved_uars;
 228         dev->caps.reserved_pds       = dev_cap->reserved_pds;
 229         dev->caps.reserved_xrcds     = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 230                                         dev_cap->reserved_xrcds : 0;
 231         dev->caps.max_xrcds          = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
 232                                         dev_cap->max_xrcds : 0;
 233         dev->caps.mtt_entry_sz       = dev_cap->mtt_entry_sz;
 234
 235         dev->caps.max_msg_sz         = dev_cap->max_msg_sz;
 236         dev->caps.page_size_cap      = ~(u32) (dev_cap->min_page_sz - 1);
 237         dev->caps.flags              = dev_cap->flags;
 238         dev->caps.bmme_flags         = dev_cap->bmme_flags;
 239         dev->caps.reserved_lkey      = dev_cap->reserved_lkey;
 240         dev->caps.stat_rate_support  = dev_cap->stat_rate_support;
 241         dev->caps.max_gso_sz         = dev_cap->max_gso_sz;
 242
 243         dev->caps.log_num_macs  = log_num_mac;
 244         dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
 245         dev->caps.log_num_prios = use_prio ? 3 : 0;
 246
 247         for (i = 1; i <= dev->caps.num_ports; ++i) {
 248                 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
 249                         dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
 250                 else
 251                         dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
 252                 dev->caps.possible_type[i] = dev->caps.port_type[i];
 253                 mlx4_priv(dev)->sense.sense_allowed[i] =
 254                         dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
 255
 256                 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
 257                         dev->caps.log_num_macs = dev_cap->log_max_macs[i];
 258                         mlx4_warn(dev, "Requested number of MACs is too much "
 259                                   "for port %d, reducing to %d.\n",
 260                                   i, 1 << dev->caps.log_num_macs);
 261                 }
 262                 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
 263                         dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
 264                         mlx4_warn(dev, "Requested number of VLANs is too much "
 265                                   "for port %d, reducing to %d.\n",
 266                                   i, 1 << dev->caps.log_num_vlans);
 267                 }
 268         }
 269
 270         mlx4_set_port_mask(dev);
 271
 272         dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters);
 273
 274         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
 275         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
 276                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
 277                 (1 << dev->caps.log_num_macs) *
 278                 (1 << dev->caps.log_num_vlans) *
 279                 (1 << dev->caps.log_num_prios) *
 280                 dev->caps.num_ports;
 281         dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
 282
 283         dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
 284                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
 285                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
 286                 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
 287
 288         return 0;
 289 }
 290
 291 /*
 292  * Change the port configuration of the device.
 293  * Every user of this function must hold the port mutex.
 294  */
 295 int mlx4_change_port_types(struct mlx4_dev *dev,
 296                            enum mlx4_port_type *port_types)
 297 {
 298         int err = 0;
 299         int change = 0;
 300         int port;
 301
 302         for (port = 0; port <  dev->caps.num_ports; port++) {
 303                 /* Change the port type only if the new type is different
 304                  * from the current, and not set to Auto */
 305                 if (port_types[port] != dev->caps.port_type[port + 1]) {
 306                         change = 1;
 307                         dev->caps.port_type[port + 1] = port_types[port];
 308                 }
 309         }
 310         if (change) {
 311                 mlx4_unregister_device(dev);
 312                 for (port = 1; port <= dev->caps.num_ports; port++) {
 313                         mlx4_CLOSE_PORT(dev, port);
 314                         err = mlx4_SET_PORT(dev, port);
 315                         if (err) {
 316                                 mlx4_err(dev, "Failed to set port %d, "
 317                                               "aborting\n", port);
 318                                 goto out;
 319                         }
 320                 }
 321                 mlx4_set_port_mask(dev);
 322                 err = mlx4_register_device(dev);
 323         }
 324
 325 out:
 326         return err;
 327 }
 328
 329 static ssize_t show_port_type(struct device *dev,
 330                               struct device_attribute *attr,
 331                               char *buf)
 332 {
 333         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 334                                                    port_attr);
 335         struct mlx4_dev *mdev = info->dev;
 336         char type[8];
 337
 338         sprintf(type, "%s",
 339                 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
 340                 "ib" : "eth");
 341         if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
 342                 sprintf(buf, "auto (%s)\n", type);
 343         else
 344                 sprintf(buf, "%s\n", type);
 345
 346         return strlen(buf);
 347 }
 348
 349 static ssize_t set_port_type(struct device *dev,
 350                              struct device_attribute *attr,
 351                              const char *buf, size_t count)
 352 {
 353         struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
 354                                                    port_attr);
 355         struct mlx4_dev *mdev = info->dev;
 356         struct mlx4_priv *priv = mlx4_priv(mdev);
 357         enum mlx4_port_type types[MLX4_MAX_PORTS];
 358         enum mlx4_port_type new_types[MLX4_MAX_PORTS];
 359         int i;
 360         int err = 0;
 361
 362         if (!strcmp(buf, "ib\n"))
 363                 info->tmp_type = MLX4_PORT_TYPE_IB;
 364         else if (!strcmp(buf, "eth\n"))
 365                 info->tmp_type = MLX4_PORT_TYPE_ETH;
 366         else if (!strcmp(buf, "auto\n"))
 367                 info->tmp_type = MLX4_PORT_TYPE_AUTO;
 368         else {
 369                 mlx4_err(mdev, "%s is not supported port type\n", buf);
 370                 return -EINVAL;
 371         }
 372
 373         mlx4_stop_sense(mdev);
 374         mutex_lock(&priv->port_mutex);
 375         /* Possible type is always the one that was delivered */
 376         mdev->caps.possible_type[info->port] = info->tmp_type;
 377
 378         for (i = 0; i < mdev->caps.num_ports; i++) {
 379                 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
 380                                         mdev->caps.possible_type[i+1];
 381                 if (types[i] == MLX4_PORT_TYPE_AUTO)
 382                         types[i] = mdev->caps.port_type[i+1];
 383         }
 384
 385         if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
 386                 for (i = 1; i <= mdev->caps.num_ports; i++) {
 387                         if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
 388                                 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
 389                                 err = -EINVAL;
 390                         }
 391                 }
 392         }
 393         if (err) {
 394                 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
 395                                "Set only 'eth' or 'ib' for both ports "
 396                                "(should be the same)\n");
 397                 goto out;
 398         }
 399
 400         mlx4_do_sense_ports(mdev, new_types, types);
 401
 402         err = mlx4_check_port_params(mdev, new_types);
 403         if (err)
 404                 goto out;
 405
 406         /* We are about to apply the changes after the configuration
 407          * was verified, no need to remember the temporary types
 408          * any more */
 409         for (i = 0; i < mdev->caps.num_ports; i++)
 410                 priv->port[i + 1].tmp_type = 0;
 411
 412         err = mlx4_change_port_types(mdev, new_types);
 413
 414 out:
 415         mlx4_start_sense(mdev);
 416         mutex_unlock(&priv->port_mutex);
 417         return err ? err : count;
 418 }
 419
 420 static int mlx4_load_fw(struct mlx4_dev *dev)
 421 {
 422         struct mlx4_priv *priv = mlx4_priv(dev);
 423         int err;
 424
 425         priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
 426                                          GFP_HIGHUSER | __GFP_NOWARN, 0);
 427         if (!priv->fw.fw_icm) {
 428                 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
 429                 return -ENOMEM;
 430         }
 431
 432         err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
 433         if (err) {
 434                 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
 435                 goto err_free;
 436         }
 437
 438         err = mlx4_RUN_FW(dev);
 439         if (err) {
 440                 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
 441                 goto err_unmap_fa;
 442         }
 443
 444         return 0;
 445
 446 err_unmap_fa:
 447         mlx4_UNMAP_FA(dev);
 448
 449 err_free:
 450         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 451         return err;
 452 }
 453
 454 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
 455                                 int cmpt_entry_sz)
 456 {
 457         struct mlx4_priv *priv = mlx4_priv(dev);
 458         int err;
 459
 460         err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
 461                                   cmpt_base +
 462                                   ((u64) (MLX4_CMPT_TYPE_QP *
 463                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 464                                   cmpt_entry_sz, dev->caps.num_qps,
 465                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 466                                   0, 0);
 467         if (err)
 468                 goto err;
 469
 470         err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
 471                                   cmpt_base +
 472                                   ((u64) (MLX4_CMPT_TYPE_SRQ *
 473                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 474                                   cmpt_entry_sz, dev->caps.num_srqs,
 475                                   dev->caps.reserved_srqs, 0, 0);
 476         if (err)
 477                 goto err_qp;
 478
 479         err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
 480                                   cmpt_base +
 481                                   ((u64) (MLX4_CMPT_TYPE_CQ *
 482                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 483                                   cmpt_entry_sz, dev->caps.num_cqs,
 484                                   dev->caps.reserved_cqs, 0, 0);
 485         if (err)
 486                 goto err_srq;
 487
 488         err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
 489                                   cmpt_base +
 490                                   ((u64) (MLX4_CMPT_TYPE_EQ *
 491                                           cmpt_entry_sz) << MLX4_CMPT_SHIFT),
 492                                   cmpt_entry_sz,
 493                                   dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
 494         if (err)
 495                 goto err_cq;
 496
 497         return 0;
 498
 499 err_cq:
 500         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 501
 502 err_srq:
 503         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 504
 505 err_qp:
 506         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 507
 508 err:
 509         return err;
 510 }
 511
 512 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
 513                          struct mlx4_init_hca_param *init_hca, u64 icm_size)
 514 {
 515         struct mlx4_priv *priv = mlx4_priv(dev);
 516         u64 aux_pages;
 517         int err;
 518
 519         err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
 520         if (err) {
 521                 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
 522                 return err;
 523         }
 524
 525         mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
 526                  (unsigned long long) icm_size >> 10,
 527                  (unsigned long long) aux_pages << 2);
 528
 529         priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
 530                                           GFP_HIGHUSER | __GFP_NOWARN, 0);
 531         if (!priv->fw.aux_icm) {
 532                 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
 533                 return -ENOMEM;
 534         }
 535
 536         err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
 537         if (err) {
 538                 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
 539                 goto err_free_aux;
 540         }
 541
 542         err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
 543         if (err) {
 544                 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
 545                 goto err_unmap_aux;
 546         }
 547
 548         err = mlx4_init_icm_table(dev, &priv->eq_table.table,
 549                                   init_hca->eqc_base, dev_cap->eqc_entry_sz,
 550                                   dev->caps.num_eqs, dev->caps.num_eqs,
 551                                   0, 0);
 552         if (err) {
 553                 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
 554                 goto err_unmap_cmpt;
 555         }
 556
 557         /*
 558          * Reserved MTT entries must be aligned up to a cacheline
 559          * boundary, since the FW will write to them, while the driver
 560          * writes to all other MTT entries. (The variable
 561          * dev->caps.mtt_entry_sz below is really the MTT segment
 562          * size, not the raw entry size)
 563          */
 564         dev->caps.reserved_mtts =
 565                 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
 566                       dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
 567
 568         err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
 569                                   init_hca->mtt_base,
 570                                   dev->caps.mtt_entry_sz,
 571                                   dev->caps.num_mtts,
 572                                   dev->caps.reserved_mtts, 1, 0);
 573         if (err) {
 574                 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
 575                 goto err_unmap_eq;
 576         }
 577
 578         err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
 579                                   init_hca->dmpt_base,
 580                                   dev_cap->dmpt_entry_sz,
 581                                   dev->caps.num_mpts,
 582                                   dev->caps.reserved_mrws, 1, 1);
 583         if (err) {
 584                 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
 585                 goto err_unmap_mtt;
 586         }
 587
 588         err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
 589                                   init_hca->qpc_base,
 590                                   dev_cap->qpc_entry_sz,
 591                                   dev->caps.num_qps,
 592                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 593                                   0, 0);
 594         if (err) {
 595                 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
 596                 goto err_unmap_dmpt;
 597         }
 598
 599         err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
 600                                   init_hca->auxc_base,
 601                                   dev_cap->aux_entry_sz,
 602                                   dev->caps.num_qps,
 603                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 604                                   0, 0);
 605         if (err) {
 606                 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
 607                 goto err_unmap_qp;
 608         }
 609
 610         err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
 611                                   init_hca->altc_base,
 612                                   dev_cap->altc_entry_sz,
 613                                   dev->caps.num_qps,
 614                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 615                                   0, 0);
 616         if (err) {
 617                 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
 618                 goto err_unmap_auxc;
 619         }
 620
 621         err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
 622                                   init_hca->rdmarc_base,
 623                                   dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
 624                                   dev->caps.num_qps,
 625                                   dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
 626                                   0, 0);
 627         if (err) {
 628                 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
 629                 goto err_unmap_altc;
 630         }
 631
 632         err = mlx4_init_icm_table(dev, &priv->cq_table.table,
 633                                   init_hca->cqc_base,
 634                                   dev_cap->cqc_entry_sz,
 635                                   dev->caps.num_cqs,
 636                                   dev->caps.reserved_cqs, 0, 0);
 637         if (err) {
 638                 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
 639                 goto err_unmap_rdmarc;
 640         }
 641
 642         err = mlx4_init_icm_table(dev, &priv->srq_table.table,
 643                                   init_hca->srqc_base,
 644                                   dev_cap->srq_entry_sz,
 645                                   dev->caps.num_srqs,
 646                                   dev->caps.reserved_srqs, 0, 0);
 647         if (err) {
 648                 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
 649                 goto err_unmap_cq;
 650         }
 651
 652         /*
 653          * It's not strictly required, but for simplicity just map the
 654          * whole multicast group table now.  The table isn't very big
 655          * and it's a lot easier than trying to track ref counts.
 656          */
 657         err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
 658                                   init_hca->mc_base,
 659                                   mlx4_get_mgm_entry_size(dev),
 660                                   dev->caps.num_mgms + dev->caps.num_amgms,
 661                                   dev->caps.num_mgms + dev->caps.num_amgms,
 662                                   0, 0);
 663         if (err) {
 664                 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
 665                 goto err_unmap_srq;
 666         }
 667
 668         return 0;
 669
 670 err_unmap_srq:
 671         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
 672
 673 err_unmap_cq:
 674         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
 675
 676 err_unmap_rdmarc:
 677         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
 678
 679 err_unmap_altc:
 680         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
 681
 682 err_unmap_auxc:
 683         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
 684
 685 err_unmap_qp:
 686         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
 687
 688 err_unmap_dmpt:
 689         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
 690
 691 err_unmap_mtt:
 692         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
 693
 694 err_unmap_eq:
 695         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 696
 697 err_unmap_cmpt:
 698         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
 699         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 700         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 701         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 702
 703 err_unmap_aux:
 704         mlx4_UNMAP_ICM_AUX(dev);
 705
 706 err_free_aux:
 707         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
 708
 709         return err;
 710 }
 711
 712 static void mlx4_free_icms(struct mlx4_dev *dev)
 713 {
 714         struct mlx4_priv *priv = mlx4_priv(dev);
 715
 716         mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
 717         mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
 718         mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
 719         mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
 720         mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
 721         mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
 722         mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
 723         mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
 724         mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
 725         mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
 726         mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
 727         mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
 728         mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
 729         mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
 730
 731         mlx4_UNMAP_ICM_AUX(dev);
 732         mlx4_free_icm(dev, priv->fw.aux_icm, 0);
 733 }
 734
 735 static int map_bf_area(struct mlx4_dev *dev)
 736 {
 737         struct mlx4_priv *priv = mlx4_priv(dev);
 738         resource_size_t bf_start;
 739         resource_size_t bf_len;
 740         int err = 0;
 741
 742         bf_start = pci_resource_start(dev->pdev, 2) + (dev->caps.num_uars << PAGE_SHIFT);
 743         bf_len = pci_resource_len(dev->pdev, 2) - (dev->caps.num_uars << PAGE_SHIFT);
 744         priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
 745         if (!priv->bf_mapping)
 746                 err = -ENOMEM;
 747
 748         return err;
 749 }
 750
 751 static void unmap_bf_area(struct mlx4_dev *dev)
 752 {
 753         if (mlx4_priv(dev)->bf_mapping)
 754                 io_mapping_free(mlx4_priv(dev)->bf_mapping);
 755 }
 756
 757 static void mlx4_close_hca(struct mlx4_dev *dev)
 758 {
 759         unmap_bf_area(dev);
 760         mlx4_CLOSE_HCA(dev, 0);
 761         mlx4_free_icms(dev);
 762         mlx4_UNMAP_FA(dev);
 763         mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
 764 }
 765
 766 static int mlx4_init_hca(struct mlx4_dev *dev)
 767 {
 768         struct mlx4_priv          *priv = mlx4_priv(dev);
 769         struct mlx4_adapter        adapter;
 770         struct mlx4_dev_cap        dev_cap;
 771         struct mlx4_mod_stat_cfg   mlx4_cfg;
 772         struct mlx4_profile        profile;
 773         struct mlx4_init_hca_param init_hca;
 774         u64 icm_size;
 775         int err;
 776
 777         err = mlx4_QUERY_FW(dev);
 778         if (err) {
 779                 if (err == -EACCES)
 780                         mlx4_info(dev, "non-primary physical function, skipping.\n");
 781                 else
 782                         mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
 783                 return err;
 784         }
 785
 786         err = mlx4_load_fw(dev);
 787         if (err) {
 788                 mlx4_err(dev, "Failed to start FW, aborting.\n");
 789                 return err;
 790         }
 791
 792         mlx4_cfg.log_pg_sz_m = 1;
 793         mlx4_cfg.log_pg_sz = 0;
 794         err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
 795         if (err)
 796                 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
 797
 798         err = mlx4_dev_cap(dev, &dev_cap);
 799         if (err) {
 800                 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
 801                 goto err_stop_fw;
 802         }
 803
 804         profile = default_profile;
 805
 806         icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
 807         if ((long long) icm_size < 0) {
 808                 err = icm_size;
 809                 goto err_stop_fw;
 810         }
 811
 812         if (map_bf_area(dev))
 813                 mlx4_dbg(dev, "Failed to map blue flame area\n");
 814
 815         init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
 816
 817         err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
 818         if (err)
 819                 goto err_stop_fw;
 820
 821         err = mlx4_INIT_HCA(dev, &init_hca);
 822         if (err) {
 823                 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
 824                 goto err_free_icm;
 825         }
 826
 827         err = mlx4_QUERY_ADAPTER(dev, &adapter);
 828         if (err) {
 829                 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
 830                 goto err_close;
 831         }
 832
 833         priv->eq_table.inta_pin = adapter.inta_pin;
 834         memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
 835
 836         return 0;
 837
 838 err_close:
 839         mlx4_CLOSE_HCA(dev, 0);
 840
 841 err_free_icm:
 842         mlx4_free_icms(dev);
 843
 844 err_stop_fw:
 845         unmap_bf_area(dev);
 846         mlx4_UNMAP_FA(dev);
 847         mlx4_free_icm(dev, priv->fw.fw_icm, 0);
 848
 849         return err;
 850 }
 851
 852 static int mlx4_init_counters_table(struct mlx4_dev *dev)
 853 {
 854         struct mlx4_priv *priv = mlx4_priv(dev);
 855         int nent;
 856
 857         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
 858                 return -ENOENT;
 859
 860         nent = dev->caps.max_counters;
 861         return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0);
 862 }
 863
 864 static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
 865 {
 866         mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
 867 }
 868
 869 int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
 870 {
 871         struct mlx4_priv *priv = mlx4_priv(dev);
 872
 873         if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
 874                 return -ENOENT;
 875
 876         *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
 877         if (*idx == -1)
 878                 return -ENOMEM;
 879
 880         return 0;
 881 }
 882 EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
 883
 884 void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
 885 {
 886         mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx);
 887         return;
 888 }
 889 EXPORT_SYMBOL_GPL(mlx4_counter_free);
 890
 891 static int mlx4_setup_hca(struct mlx4_dev *dev)
 892 {
 893         struct mlx4_priv *priv = mlx4_priv(dev);
 894         int err;
 895         int port;
 896         __be32 ib_port_default_caps;
 897
 898         err = mlx4_init_uar_table(dev);
 899         if (err) {
 900                 mlx4_err(dev, "Failed to initialize "
 901                          "user access region table, aborting.\n");
 902                 return err;
 903         }
 904
 905         err = mlx4_uar_alloc(dev, &priv->driver_uar);
 906         if (err) {
 907                 mlx4_err(dev, "Failed to allocate driver access region, "
 908                          "aborting.\n");
 909                 goto err_uar_table_free;
 910         }
 911
 912         priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
 913         if (!priv->kar) {
 914                 mlx4_err(dev, "Couldn't map kernel access region, "
 915                          "aborting.\n");
 916                 err = -ENOMEM;
 917                 goto err_uar_free;
 918         }
 919
 920         err = mlx4_init_pd_table(dev);
 921         if (err) {
 922                 mlx4_err(dev, "Failed to initialize "
 923                          "protection domain table, aborting.\n");
 924                 goto err_kar_unmap;
 925         }
 926
 927         err = mlx4_init_xrcd_table(dev);
 928         if (err) {
 929                 mlx4_err(dev, "Failed to initialize "
 930                          "reliable connection domain table, aborting.\n");
 931                 goto err_pd_table_free;
 932         }
 933
 934         err = mlx4_init_mr_table(dev);
 935         if (err) {
 936                 mlx4_err(dev, "Failed to initialize "
 937                          "memory region table, aborting.\n");
 938                 goto err_xrcd_table_free;
 939         }
 940
 941         err = mlx4_init_eq_table(dev);
 942         if (err) {
 943                 mlx4_err(dev, "Failed to initialize "
 944                          "event queue table, aborting.\n");
 945                 goto err_mr_table_free;
 946         }
 947
 948         err = mlx4_cmd_use_events(dev);
 949         if (err) {
 950                 mlx4_err(dev, "Failed to switch to event-driven "
 951                          "firmware commands, aborting.\n");
 952                 goto err_eq_table_free;
 953         }
 954
 955         err = mlx4_NOP(dev);
 956         if (err) {
 957                 if (dev->flags & MLX4_FLAG_MSI_X) {
 958                         mlx4_warn(dev, "NOP command failed to generate MSI-X "
 959                                   "interrupt IRQ %d).\n",
 960                                   priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
 961                         mlx4_warn(dev, "Trying again without MSI-X.\n");
 962                 } else {
 963                         mlx4_err(dev, "NOP command failed to generate interrupt "
 964                                  "(IRQ %d), aborting.\n",
 965                                  priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
 966                         mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
 967                 }
 968
 969                 goto err_cmd_poll;
 970         }
 971
 972         mlx4_dbg(dev, "NOP command IRQ test passed\n");
 973
 974         err = mlx4_init_cq_table(dev);
 975         if (err) {
 976                 mlx4_err(dev, "Failed to initialize "
 977                          "completion queue table, aborting.\n");
 978                 goto err_cmd_poll;
 979         }
 980
 981         err = mlx4_init_srq_table(dev);
 982         if (err) {
 983                 mlx4_err(dev, "Failed to initialize "
 984                          "shared receive queue table, aborting.\n");
 985                 goto err_cq_table_free;
 986         }
 987
 988         err = mlx4_init_qp_table(dev);
 989         if (err) {
 990                 mlx4_err(dev, "Failed to initialize "
 991                          "queue pair table, aborting.\n");
 992                 goto err_srq_table_free;
 993         }
 994
 995         err = mlx4_init_mcg_table(dev);
 996         if (err) {
 997                 mlx4_err(dev, "Failed to initialize "
 998                          "multicast group table, aborting.\n");
 999                 goto err_qp_table_free;
1000         }
1001
1002         err = mlx4_init_counters_table(dev);
1003         if (err && err != -ENOENT) {
1004                 mlx4_err(dev, "Failed to initialize counters table, aborting.\n");
1005                 goto err_counters_table_free;
1006         }
1007
1008         for (port = 1; port <= dev->caps.num_ports; port++) {
1009                 enum mlx4_port_type port_type = 0;
1010                 mlx4_SENSE_PORT(dev, port, &port_type);
1011                 if (port_type)
1012                         dev->caps.port_type[port] = port_type;
1013                 ib_port_default_caps = 0;
1014                 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
1015                 if (err)
1016                         mlx4_warn(dev, "failed to get port %d default "
1017                                   "ib capabilities (%d). Continuing with "
1018                                   "caps = 0\n", port, err);
1019                 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
1020
1021                 err = mlx4_check_ext_port_caps(dev, port);
1022                 if (err)
1023                         mlx4_warn(dev, "failed to get port %d extended "
1024                                   "port capabilities support info (%d)."
1025                                   " Assuming not supported\n", port, err);
1026
1027                 err = mlx4_SET_PORT(dev, port);
1028                 if (err) {
1029                         mlx4_err(dev, "Failed to set port %d, aborting\n",
1030                                 port);
1031                         goto err_mcg_table_free;
1032                 }
1033         }
1034         mlx4_set_port_mask(dev);
1035
1036         return 0;
1037
1038 err_mcg_table_free:
1039         mlx4_cleanup_mcg_table(dev);
1040
1041 err_counters_table_free:
1042         mlx4_cleanup_counters_table(dev);
1043
1044 err_qp_table_free:
1045         mlx4_cleanup_qp_table(dev);
1046
1047 err_srq_table_free:
1048         mlx4_cleanup_srq_table(dev);
1049
1050 err_cq_table_free:
1051         mlx4_cleanup_cq_table(dev);
1052
1053 err_cmd_poll:
1054         mlx4_cmd_use_polling(dev);
1055
1056 err_eq_table_free:
1057         mlx4_cleanup_eq_table(dev);
1058
1059 err_mr_table_free:
1060         mlx4_cleanup_mr_table(dev);
1061
1062 err_xrcd_table_free:
1063         mlx4_cleanup_xrcd_table(dev);
1064
1065 err_pd_table_free:
1066         mlx4_cleanup_pd_table(dev);
1067
1068 err_kar_unmap:
1069         iounmap(priv->kar);
1070
1071 err_uar_free:
1072         mlx4_uar_free(dev, &priv->driver_uar);
1073
1074 err_uar_table_free:
1075         mlx4_cleanup_uar_table(dev);
1076         return err;
1077 }
1078
1079 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
1080 {
1081         struct mlx4_priv *priv = mlx4_priv(dev);
1082         struct msix_entry *entries;
1083         int nreq = min_t(int, dev->caps.num_ports *
1084                          min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT)
1085                                 + MSIX_LEGACY_SZ, MAX_MSIX);
1086         int err;
1087         int i;
1088
1089         if (msi_x) {
1090                 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
1091                              nreq);
1092                 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
1093                 if (!entries)
1094                         goto no_msi;
1095
1096                 for (i = 0; i < nreq; ++i)
1097                         entries[i].entry = i;
1098
1099         retry:
1100                 err = pci_enable_msix(dev->pdev, entries, nreq);
1101                 if (err) {
1102                         /* Try again if at least 2 vectors are available */
1103                         if (err > 1) {
1104                                 mlx4_info(dev, "Requested %d vectors, "
1105                                           "but only %d MSI-X vectors available, "
1106                                           "trying again\n", nreq, err);
1107                                 nreq = err;
1108                                 goto retry;
1109                         }
1110                         kfree(entries);
1111                         goto no_msi;
1112                 }
1113
1114                 if (nreq <
1115                     MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) {
1116                         /*Working in legacy mode , all EQ's shared*/
1117                         dev->caps.comp_pool           = 0;
1118                         dev->caps.num_comp_vectors = nreq - 1;
1119                 } else {
1120                         dev->caps.comp_pool           = nreq - MSIX_LEGACY_SZ;
1121                         dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1;
1122                 }
1123                 for (i = 0; i < nreq; ++i)
1124                         priv->eq_table.eq[i].irq = entries[i].vector;
1125
1126                 dev->flags |= MLX4_FLAG_MSI_X;
1127
1128                 kfree(entries);
1129                 return;
1130         }
1131
1132 no_msi:
1133         dev->caps.num_comp_vectors = 1;
1134         dev->caps.comp_pool        = 0;
1135
1136         for (i = 0; i < 2; ++i)
1137                 priv->eq_table.eq[i].irq = dev->pdev->irq;
1138 }
1139
1140 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1141 {
1142         struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1143         int err = 0;
1144
1145         info->dev = dev;
1146         info->port = port;
1147         mlx4_init_mac_table(dev, &info->mac_table);
1148         mlx4_init_vlan_table(dev, &info->vlan_table);
1149         info->base_qpn = dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] +
1150                         (port - 1) * (1 << log_num_mac);
1151
1152         sprintf(info->dev_name, "mlx4_port%d", port);
1153         info->port_attr.attr.name = info->dev_name;
1154         info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1155         info->port_attr.show      = show_port_type;
1156         info->port_attr.store     = set_port_type;
1157         sysfs_attr_init(&info->port_attr.attr);
1158
1159         err = device_create_file(&dev->pdev->dev, &info->port_attr);
1160         if (err) {
1161                 mlx4_err(dev, "Failed to create file for port %d\n", port);
1162                 info->port = -1;
1163         }
1164
1165         return err;
1166 }
1167
1168 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1169 {
1170         if (info->port < 0)
1171                 return;
1172
1173         device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1174 }
1175
1176 static int mlx4_init_steering(struct mlx4_dev *dev)
1177 {
1178         struct mlx4_priv *priv = mlx4_priv(dev);
1179         int num_entries = dev->caps.num_ports;
1180         int i, j;
1181
1182         priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
1183         if (!priv->steer)
1184                 return -ENOMEM;
1185
1186         for (i = 0; i < num_entries; i++) {
1187                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1188                         INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
1189                         INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
1190                 }
1191                 INIT_LIST_HEAD(&priv->steer[i].high_prios);
1192         }
1193         return 0;
1194 }
1195
1196 static void mlx4_clear_steering(struct mlx4_dev *dev)
1197 {
1198         struct mlx4_priv *priv = mlx4_priv(dev);
1199         struct mlx4_steer_index *entry, *tmp_entry;
1200         struct mlx4_promisc_qp *pqp, *tmp_pqp;
1201         int num_entries = dev->caps.num_ports;
1202         int i, j;
1203
1204         for (i = 0; i < num_entries; i++) {
1205                 for (j = 0; j < MLX4_NUM_STEERS; j++) {
1206                         list_for_each_entry_safe(pqp, tmp_pqp,
1207                                                  &priv->steer[i].promisc_qps[j],
1208                                                  list) {
1209                                 list_del(&pqp->list);
1210                                 kfree(pqp);
1211                         }
1212                         list_for_each_entry_safe(entry, tmp_entry,
1213                                                  &priv->steer[i].steer_entries[j],
1214                                                  list) {
1215                                 list_del(&entry->list);
1216                                 list_for_each_entry_safe(pqp, tmp_pqp,
1217                                                          &entry->duplicates,
1218                                                          list) {
1219                                         list_del(&pqp->list);
1220                                         kfree(pqp);
1221                                 }
1222                                 kfree(entry);
1223                         }
1224                 }
1225         }
1226         kfree(priv->steer);
1227 }
1228
1229 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1230 {
1231         struct mlx4_priv *priv;
1232         struct mlx4_dev *dev;
1233         int err;
1234         int port;
1235
1236         pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1237
1238         err = pci_enable_device(pdev);
1239         if (err) {
1240                 dev_err(&pdev->dev, "Cannot enable PCI device, "
1241                         "aborting.\n");
1242                 return err;
1243         }
1244
1245         /*
1246          * Check for BARs.  We expect 0: 1MB
1247          */
1248         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1249             pci_resource_len(pdev, 0) != 1 << 20) {
1250                 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1251                 err = -ENODEV;
1252                 goto err_disable_pdev;
1253         }
1254         if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1255                 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1256                 err = -ENODEV;
1257                 goto err_disable_pdev;
1258         }
1259
1260         err = pci_request_regions(pdev, DRV_NAME);
1261         if (err) {
1262                 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1263                 goto err_disable_pdev;
1264         }
1265
1266         pci_set_master(pdev);
1267
1268         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1269         if (err) {
1270                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1271                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1272                 if (err) {
1273                         dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1274                         goto err_release_regions;
1275                 }
1276         }
1277         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1278         if (err) {
1279                 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1280                          "consistent PCI DMA mask.\n");
1281                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1282                 if (err) {
1283                         dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1284                                 "aborting.\n");
1285                         goto err_release_regions;
1286                 }
1287         }
1288
1289         /* Allow large DMA segments, up to the firmware limit of 1 GB */
1290         dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
1291
1292         priv = kzalloc(sizeof *priv, GFP_KERNEL);
1293         if (!priv) {
1294                 dev_err(&pdev->dev, "Device struct alloc failed, "
1295                         "aborting.\n");
1296                 err = -ENOMEM;
1297                 goto err_release_regions;
1298         }
1299
1300         dev       = &priv->dev;
1301         dev->pdev = pdev;
1302         INIT_LIST_HEAD(&priv->ctx_list);
1303         spin_lock_init(&priv->ctx_lock);
1304
1305         mutex_init(&priv->port_mutex);
1306
1307         INIT_LIST_HEAD(&priv->pgdir_list);
1308         mutex_init(&priv->pgdir_mutex);
1309
1310         INIT_LIST_HEAD(&priv->bf_list);
1311         mutex_init(&priv->bf_mutex);
1312
1313         dev->rev_id = pdev->revision;
1314
1315         /*
1316          * Now reset the HCA before we touch the PCI capabilities or
1317          * attempt a firmware command, since a boot ROM may have left
1318          * the HCA in an undefined state.
1319          */
1320         err = mlx4_reset(dev);
1321         if (err) {
1322                 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1323                 goto err_free_dev;
1324         }
1325
1326         if (mlx4_cmd_init(dev)) {
1327                 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1328                 goto err_free_dev;
1329         }
1330
1331         err = mlx4_init_hca(dev);
1332         if (err)
1333                 goto err_cmd;
1334
1335         err = mlx4_alloc_eq_table(dev);
1336         if (err)
1337                 goto err_close;
1338
1339         priv->msix_ctl.pool_bm = 0;
1340         spin_lock_init(&priv->msix_ctl.pool_lock);
1341
1342         mlx4_enable_msi_x(dev);
1343
1344         err = mlx4_init_steering(dev);
1345         if (err)
1346                 goto err_free_eq;
1347
1348         err = mlx4_setup_hca(dev);
1349         if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1350                 dev->flags &= ~MLX4_FLAG_MSI_X;
1351                 pci_disable_msix(pdev);
1352                 err = mlx4_setup_hca(dev);
1353         }
1354
1355         if (err)
1356                 goto err_steer;
1357
1358         for (port = 1; port <= dev->caps.num_ports; port++) {
1359                 err = mlx4_init_port_info(dev, port);
1360                 if (err)
1361                         goto err_port;
1362         }
1363
1364         err = mlx4_register_device(dev);
1365         if (err)
1366                 goto err_port;
1367
1368         mlx4_sense_init(dev);
1369         mlx4_start_sense(dev);
1370
1371         pci_set_drvdata(pdev, dev);
1372
1373         return 0;
1374
1375 err_port:
1376         for (--port; port >= 1; --port)
1377                 mlx4_cleanup_port_info(&priv->port[port]);
1378
1379         mlx4_cleanup_counters_table(dev);
1380         mlx4_cleanup_mcg_table(dev);
1381         mlx4_cleanup_qp_table(dev);
1382         mlx4_cleanup_srq_table(dev);
1383         mlx4_cleanup_cq_table(dev);
1384         mlx4_cmd_use_polling(dev);
1385         mlx4_cleanup_eq_table(dev);
1386         mlx4_cleanup_mr_table(dev);
1387         mlx4_cleanup_xrcd_table(dev);
1388         mlx4_cleanup_pd_table(dev);
1389         mlx4_cleanup_uar_table(dev);
1390
1391 err_steer:
1392         mlx4_clear_steering(dev);
1393
1394 err_free_eq:
1395         mlx4_free_eq_table(dev);
1396
1397 err_close:
1398         if (dev->flags & MLX4_FLAG_MSI_X)
1399                 pci_disable_msix(pdev);
1400
1401         mlx4_close_hca(dev);
1402
1403 err_cmd:
1404         mlx4_cmd_cleanup(dev);
1405
1406 err_free_dev:
1407         kfree(priv);
1408
1409 err_release_regions:
1410         pci_release_regions(pdev);
1411
1412 err_disable_pdev:
1413         pci_disable_device(pdev);
1414         pci_set_drvdata(pdev, NULL);
1415         return err;
1416 }
1417
1418 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1419                                    const struct pci_device_id *id)
1420 {
1421         printk_once(KERN_INFO "%s", mlx4_version);
1422
1423         return __mlx4_init_one(pdev, id);
1424 }
1425
1426 static void mlx4_remove_one(struct pci_dev *pdev)
1427 {
1428         struct mlx4_dev  *dev  = pci_get_drvdata(pdev);
1429         struct mlx4_priv *priv = mlx4_priv(dev);
1430         int p;
1431
1432         if (dev) {
1433                 mlx4_stop_sense(dev);
1434                 mlx4_unregister_device(dev);
1435
1436                 for (p = 1; p <= dev->caps.num_ports; p++) {
1437                         mlx4_cleanup_port_info(&priv->port[p]);
1438                         mlx4_CLOSE_PORT(dev, p);
1439                 }
1440
1441                 mlx4_cleanup_counters_table(dev);
1442                 mlx4_cleanup_mcg_table(dev);
1443                 mlx4_cleanup_qp_table(dev);
1444                 mlx4_cleanup_srq_table(dev);
1445                 mlx4_cleanup_cq_table(dev);
1446                 mlx4_cmd_use_polling(dev);
1447                 mlx4_cleanup_eq_table(dev);
1448                 mlx4_cleanup_mr_table(dev);
1449                 mlx4_cleanup_xrcd_table(dev);
1450                 mlx4_cleanup_pd_table(dev);
1451
1452                 iounmap(priv->kar);
1453                 mlx4_uar_free(dev, &priv->driver_uar);
1454                 mlx4_cleanup_uar_table(dev);
1455                 mlx4_clear_steering(dev);
1456                 mlx4_free_eq_table(dev);
1457                 mlx4_close_hca(dev);
1458                 mlx4_cmd_cleanup(dev);
1459
1460                 if (dev->flags & MLX4_FLAG_MSI_X)
1461                         pci_disable_msix(pdev);
1462
1463                 kfree(priv);
1464                 pci_release_regions(pdev);
1465                 pci_disable_device(pdev);
1466                 pci_set_drvdata(pdev, NULL);
1467         }
1468 }
1469
1470 int mlx4_restart_one(struct pci_dev *pdev)
1471 {
1472         mlx4_remove_one(pdev);
1473         return __mlx4_init_one(pdev, NULL);
1474 }
1475
1476 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
1477         { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1478         { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1479         { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1480         { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1481         { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1482         { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1483         { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1484         { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1485         { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1486         { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
1487         { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
1488         { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
1489         { PCI_VDEVICE(MELLANOX, 0x1002) }, /* MT25400 Family [ConnectX-2 Virtual Function] */
1490         { PCI_VDEVICE(MELLANOX, 0x1003) }, /* MT27500 Family [ConnectX-3] */
1491         { PCI_VDEVICE(MELLANOX, 0x1004) }, /* MT27500 Family [ConnectX-3 Virtual Function] */
1492         { PCI_VDEVICE(MELLANOX, 0x1005) }, /* MT27510 Family */
1493         { PCI_VDEVICE(MELLANOX, 0x1006) }, /* MT27511 Family */
1494         { PCI_VDEVICE(MELLANOX, 0x1007) }, /* MT27520 Family */
1495         { PCI_VDEVICE(MELLANOX, 0x1008) }, /* MT27521 Family */
1496         { PCI_VDEVICE(MELLANOX, 0x1009) }, /* MT27530 Family */
1497         { PCI_VDEVICE(MELLANOX, 0x100a) }, /* MT27531 Family */
1498         { PCI_VDEVICE(MELLANOX, 0x100b) }, /* MT27540 Family */
1499         { PCI_VDEVICE(MELLANOX, 0x100c) }, /* MT27541 Family */
1500         { PCI_VDEVICE(MELLANOX, 0x100d) }, /* MT27550 Family */
1501         { PCI_VDEVICE(MELLANOX, 0x100e) }, /* MT27551 Family */
1502         { PCI_VDEVICE(MELLANOX, 0x100f) }, /* MT27560 Family */
1503         { PCI_VDEVICE(MELLANOX, 0x1010) }, /* MT27561 Family */
1504         { 0, }
1505 };
1506
1507 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1508
1509 static struct pci_driver mlx4_driver = {
1510         .name           = DRV_NAME,
1511         .id_table       = mlx4_pci_table,
1512         .probe          = mlx4_init_one,
1513         .remove         = __devexit_p(mlx4_remove_one)
1514 };
1515
1516 static int __init mlx4_verify_params(void)
1517 {
1518         if ((log_num_mac < 0) || (log_num_mac > 7)) {
1519                 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
1520                 return -1;
1521         }
1522
1523         if (log_num_vlan != 0)
1524                 pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
1525                            MLX4_LOG_NUM_VLANS);
1526
1527         if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
1528                 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1529                 return -1;
1530         }
1531
1532         return 0;
1533 }
1534
1535 static int __init mlx4_init(void)
1536 {
1537         int ret;
1538
1539         if (mlx4_verify_params())
1540                 return -EINVAL;
1541
1542         mlx4_catas_init();
1543
1544         mlx4_wq = create_singlethread_workqueue("mlx4");
1545         if (!mlx4_wq)
1546                 return -ENOMEM;
1547
1548         ret = pci_register_driver(&mlx4_driver);
1549         return ret < 0 ? ret : 0;
1550 }
1551
1552 static void __exit mlx4_cleanup(void)
1553 {
1554         pci_unregister_driver(&mlx4_driver);
1555         destroy_workqueue(mlx4_wq);
1556 }
1557
1558 module_init(mlx4_init);
1559 module_exit(mlx4_cleanup);