2 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/init.h>
35 #include <linux/interrupt.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/cpu_rmap.h>
48 MLX4_IRQNAME_SIZE = 32
52 MLX4_NUM_ASYNC_EQE = 0x100,
53 MLX4_NUM_SPARE_EQE = 0x80,
54 MLX4_EQ_ENTRY_SIZE = 0x20
57 #define MLX4_EQ_STATUS_OK ( 0 << 28)
58 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28)
59 #define MLX4_EQ_OWNER_SW ( 0 << 24)
60 #define MLX4_EQ_OWNER_HW ( 1 << 24)
61 #define MLX4_EQ_FLAG_EC ( 1 << 18)
62 #define MLX4_EQ_FLAG_OI ( 1 << 17)
63 #define MLX4_EQ_STATE_ARMED ( 9 << 8)
64 #define MLX4_EQ_STATE_FIRED (10 << 8)
65 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8)
67 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \
68 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \
69 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \
70 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \
71 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \
72 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \
73 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \
74 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
75 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \
76 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \
77 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \
78 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \
79 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \
80 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \
81 (1ull << MLX4_EVENT_TYPE_CMD) | \
82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \
83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \
84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING))
86 static u64 get_async_ev_mask(struct mlx4_dev *dev)
88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK;
89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV)
90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT);
95 static void eq_set_ci(struct mlx4_eq *eq, int req_not)
97 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) |
100 /* We still want ordering, just not swabbing, so add a barrier */
104 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor)
106 /* (entry & (eq->nent - 1)) gives us a cyclic array */
107 unsigned long offset = (entry & (eq->nent - 1)) * (MLX4_EQ_ENTRY_SIZE << eqe_factor);
108 /* CX3 is capable of extending the EQE from 32 to 64 bytes.
109 * When this feature is enabled, the first (in the lower addresses)
110 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes
111 * contain the legacy EQE information.
113 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE;
116 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor)
118 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor);
119 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe;
122 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq)
124 struct mlx4_eqe *eqe =
125 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)];
126 return (!!(eqe->owner & 0x80) ^
127 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ?
131 void mlx4_gen_slave_eqe(struct work_struct *work)
133 struct mlx4_mfunc_master_ctx *master =
134 container_of(work, struct mlx4_mfunc_master_ctx,
136 struct mlx4_mfunc *mfunc =
137 container_of(master, struct mlx4_mfunc, master);
138 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc);
139 struct mlx4_dev *dev = &priv->dev;
140 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq;
141 struct mlx4_eqe *eqe;
145 for (eqe = next_slave_event_eqe(slave_eq); eqe;
146 eqe = next_slave_event_eqe(slave_eq)) {
147 slave = eqe->slave_id;
149 /* All active slaves need to receive the event */
150 if (slave == ALL_SLAVES) {
151 for (i = 0; i < dev->num_slaves; i++) {
152 if (i != dev->caps.function &&
153 master->slave_state[i].active)
154 if (mlx4_GEN_EQE(dev, i, eqe))
155 mlx4_warn(dev, "Failed to "
157 "for slave %d\n", i);
160 if (mlx4_GEN_EQE(dev, slave, eqe))
161 mlx4_warn(dev, "Failed to generate event "
162 "for slave %d\n", slave);
169 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe)
171 struct mlx4_priv *priv = mlx4_priv(dev);
172 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq;
173 struct mlx4_eqe *s_eqe;
176 spin_lock_irqsave(&slave_eq->event_lock, flags);
177 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)];
178 if ((!!(s_eqe->owner & 0x80)) ^
179 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) {
180 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. "
181 "No free EQE on slave events queue\n", slave);
182 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
186 memcpy(s_eqe, eqe, dev->caps.eqe_size - 1);
187 s_eqe->slave_id = slave;
188 /* ensure all information is written before setting the ownersip bit */
190 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80;
193 queue_work(priv->mfunc.master.comm_wq,
194 &priv->mfunc.master.slave_event_work);
195 spin_unlock_irqrestore(&slave_eq->event_lock, flags);
198 static void mlx4_slave_event(struct mlx4_dev *dev, int slave,
199 struct mlx4_eqe *eqe)
201 struct mlx4_priv *priv = mlx4_priv(dev);
202 struct mlx4_slave_state *s_slave =
203 &priv->mfunc.master.slave_state[slave];
205 if (!s_slave->active) {
206 /*mlx4_warn(dev, "Trying to pass event to inactive slave\n");*/
210 slave_event(dev, slave, eqe);
213 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port)
217 struct mlx4_priv *priv = mlx4_priv(dev);
218 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave];
220 if (!s_slave->active)
223 memset(&eqe, 0, sizeof eqe);
225 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
226 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE;
227 eqe.event.port_mgmt_change.port = port;
229 return mlx4_GEN_EQE(dev, slave, &eqe);
231 EXPORT_SYMBOL(mlx4_gen_pkey_eqe);
233 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port)
237 /*don't send if we don't have the that slave */
238 if (dev->num_vfs < slave)
240 memset(&eqe, 0, sizeof eqe);
242 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
243 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO;
244 eqe.event.port_mgmt_change.port = port;
246 return mlx4_GEN_EQE(dev, slave, &eqe);
248 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe);
250 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port,
251 u8 port_subtype_change)
255 /*don't send if we don't have the that slave */
256 if (dev->num_vfs < slave)
258 memset(&eqe, 0, sizeof eqe);
260 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE;
261 eqe.subtype = port_subtype_change;
262 eqe.event.port_change.port = cpu_to_be32(port << 28);
264 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__,
265 port_subtype_change, slave, port);
266 return mlx4_GEN_EQE(dev, slave, &eqe);
268 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe);
270 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port)
272 struct mlx4_priv *priv = mlx4_priv(dev);
273 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
274 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS) {
275 pr_err("%s: Error: asking for slave:%d, port:%d\n",
276 __func__, slave, port);
277 return SLAVE_PORT_DOWN;
279 return s_state[slave].port_state[port];
281 EXPORT_SYMBOL(mlx4_get_slave_port_state);
283 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port,
284 enum slave_port_state state)
286 struct mlx4_priv *priv = mlx4_priv(dev);
287 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state;
289 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
290 pr_err("%s: Error: asking for slave:%d, port:%d\n",
291 __func__, slave, port);
294 s_state[slave].port_state[port] = state;
299 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event)
302 enum slave_port_gen_event gen_event;
304 for (i = 0; i < dev->num_slaves; i++)
305 set_and_calc_slave_port_state(dev, i, port, event, &gen_event);
307 /**************************************************************************
308 The function get as input the new event to that port,
309 and according to the prev state change the slave's port state.
311 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
312 MLX4_PORT_STATE_DEV_EVENT_PORT_UP
313 MLX4_PORT_STATE_IB_EVENT_GID_VALID
314 MLX4_PORT_STATE_IB_EVENT_GID_INVALID
315 ***************************************************************************/
316 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave,
318 enum slave_port_gen_event *gen_event)
320 struct mlx4_priv *priv = mlx4_priv(dev);
321 struct mlx4_slave_state *ctx = NULL;
324 enum slave_port_state cur_state =
325 mlx4_get_slave_port_state(dev, slave, port);
327 *gen_event = SLAVE_PORT_GEN_EVENT_NONE;
329 if (slave >= dev->num_slaves || port > MLX4_MAX_PORTS || port == 0) {
330 pr_err("%s: Error: asking for slave:%d, port:%d\n",
331 __func__, slave, port);
335 ctx = &priv->mfunc.master.slave_state[slave];
336 spin_lock_irqsave(&ctx->lock, flags);
339 case SLAVE_PORT_DOWN:
340 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event)
341 mlx4_set_slave_port_state(dev, slave, port,
344 case SLAVE_PENDING_UP:
345 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event)
346 mlx4_set_slave_port_state(dev, slave, port,
348 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) {
349 mlx4_set_slave_port_state(dev, slave, port,
351 *gen_event = SLAVE_PORT_GEN_EVENT_UP;
355 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) {
356 mlx4_set_slave_port_state(dev, slave, port,
358 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
359 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID ==
361 mlx4_set_slave_port_state(dev, slave, port,
363 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN;
367 pr_err("%s: BUG!!! UNKNOWN state: "
368 "slave:%d, port:%d\n", __func__, slave, port);
371 ret = mlx4_get_slave_port_state(dev, slave, port);
374 spin_unlock_irqrestore(&ctx->lock, flags);
378 EXPORT_SYMBOL(set_and_calc_slave_port_state);
380 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr)
384 memset(&eqe, 0, sizeof eqe);
386 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT;
387 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO;
388 eqe.event.port_mgmt_change.port = port;
389 eqe.event.port_mgmt_change.params.port_info.changed_attr =
390 cpu_to_be32((u32) attr);
392 slave_event(dev, ALL_SLAVES, &eqe);
395 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev);
397 void mlx4_master_handle_slave_flr(struct work_struct *work)
399 struct mlx4_mfunc_master_ctx *master =
400 container_of(work, struct mlx4_mfunc_master_ctx,
401 slave_flr_event_work);
402 struct mlx4_mfunc *mfunc =
403 container_of(master, struct mlx4_mfunc, master);
404 struct mlx4_priv *priv =
405 container_of(mfunc, struct mlx4_priv, mfunc);
406 struct mlx4_dev *dev = &priv->dev;
407 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
412 mlx4_dbg(dev, "mlx4_handle_slave_flr\n");
414 for (i = 0 ; i < dev->num_slaves; i++) {
416 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) {
417 mlx4_dbg(dev, "mlx4_handle_slave_flr: "
418 "clean slave: %d\n", i);
420 mlx4_delete_all_resources_for_slave(dev, i);
421 /*return the slave to running mode*/
422 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
423 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET;
424 slave_state[i].is_slave_going_down = 0;
425 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
427 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE,
428 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
430 mlx4_warn(dev, "Failed to notify FW on "
431 "FLR done (slave:%d)\n", i);
436 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq)
438 struct mlx4_priv *priv = mlx4_priv(dev);
439 struct mlx4_eqe *eqe;
447 u8 update_slave_state;
449 enum slave_port_gen_event gen_event;
452 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor))) {
454 * Make sure we read EQ entry contents after we've
455 * checked the ownership bit.
460 case MLX4_EVENT_TYPE_COMP:
461 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;
462 mlx4_cq_completion(dev, cqn);
465 case MLX4_EVENT_TYPE_PATH_MIG:
466 case MLX4_EVENT_TYPE_COMM_EST:
467 case MLX4_EVENT_TYPE_SQ_DRAINED:
468 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
469 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
470 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
471 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
472 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
473 mlx4_dbg(dev, "event %d arrived\n", eqe->type);
474 if (mlx4_is_master(dev)) {
475 /* forward only to slave owning the QP */
476 ret = mlx4_get_slave_from_resource_id(dev,
478 be32_to_cpu(eqe->event.qp.qpn)
480 if (ret && ret != -ENOENT) {
481 mlx4_dbg(dev, "QP event %02x(%02x) on "
482 "EQ %d at index %u: could "
483 "not get slave id (%d)\n",
484 eqe->type, eqe->subtype,
485 eq->eqn, eq->cons_index, ret);
489 if (!ret && slave != dev->caps.function) {
490 mlx4_slave_event(dev, slave, eqe);
495 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) &
496 0xffffff, eqe->type);
499 case MLX4_EVENT_TYPE_SRQ_LIMIT:
500 mlx4_warn(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n",
502 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR:
503 if (mlx4_is_master(dev)) {
504 /* forward only to slave owning the SRQ */
505 ret = mlx4_get_slave_from_resource_id(dev,
507 be32_to_cpu(eqe->event.srq.srqn)
510 if (ret && ret != -ENOENT) {
511 mlx4_warn(dev, "SRQ event %02x(%02x) "
512 "on EQ %d at index %u: could"
513 " not get slave id (%d)\n",
514 eqe->type, eqe->subtype,
515 eq->eqn, eq->cons_index, ret);
518 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x,"
519 " event: %02x(%02x)\n", __func__,
521 be32_to_cpu(eqe->event.srq.srqn),
522 eqe->type, eqe->subtype);
524 if (!ret && slave != dev->caps.function) {
525 mlx4_warn(dev, "%s: sending event "
526 "%02x(%02x) to slave:%d\n",
528 eqe->subtype, slave);
529 mlx4_slave_event(dev, slave, eqe);
533 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) &
534 0xffffff, eqe->type);
537 case MLX4_EVENT_TYPE_CMD:
539 be16_to_cpu(eqe->event.cmd.token),
540 eqe->event.cmd.status,
541 be64_to_cpu(eqe->event.cmd.out_param));
544 case MLX4_EVENT_TYPE_PORT_CHANGE:
545 port = be32_to_cpu(eqe->event.port_change.port) >> 28;
546 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) {
547 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN,
549 mlx4_priv(dev)->sense.do_sense_port[port] = 1;
550 if (!mlx4_is_master(dev))
552 for (i = 0; i < dev->num_slaves; i++) {
553 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) {
554 if (i == mlx4_master_func_num(dev))
556 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN"
557 " to slave: %d, port:%d\n",
559 mlx4_slave_event(dev, i, eqe);
560 } else { /* IB port */
561 set_and_calc_slave_port_state(dev, i, port,
562 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
564 /*we can be in pending state, then do not send port_down event*/
565 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) {
566 if (i == mlx4_master_func_num(dev))
568 mlx4_slave_event(dev, i, eqe);
573 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port);
575 mlx4_priv(dev)->sense.do_sense_port[port] = 0;
577 if (!mlx4_is_master(dev))
579 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
580 for (i = 0; i < dev->num_slaves; i++) {
581 if (i == mlx4_master_func_num(dev))
583 mlx4_slave_event(dev, i, eqe);
586 /* port-up event will be sent to a slave when the
587 * slave's alias-guid is set. This is done in alias_GUID.c
589 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP);
593 case MLX4_EVENT_TYPE_CQ_ERROR:
594 mlx4_warn(dev, "CQ %s on CQN %06x\n",
595 eqe->event.cq_err.syndrome == 1 ?
596 "overrun" : "access violation",
597 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);
598 if (mlx4_is_master(dev)) {
599 ret = mlx4_get_slave_from_resource_id(dev,
601 be32_to_cpu(eqe->event.cq_err.cqn)
603 if (ret && ret != -ENOENT) {
604 mlx4_dbg(dev, "CQ event %02x(%02x) on "
605 "EQ %d at index %u: could "
606 "not get slave id (%d)\n",
607 eqe->type, eqe->subtype,
608 eq->eqn, eq->cons_index, ret);
612 if (!ret && slave != dev->caps.function) {
613 mlx4_slave_event(dev, slave, eqe);
618 be32_to_cpu(eqe->event.cq_err.cqn)
623 case MLX4_EVENT_TYPE_EQ_OVERFLOW:
624 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn);
627 case MLX4_EVENT_TYPE_COMM_CHANNEL:
628 if (!mlx4_is_master(dev)) {
629 mlx4_warn(dev, "Received comm channel event "
630 "for non master device\n");
633 memcpy(&priv->mfunc.master.comm_arm_bit_vector,
634 eqe->event.comm_channel_arm.bit_vec,
635 sizeof eqe->event.comm_channel_arm.bit_vec);
636 queue_work(priv->mfunc.master.comm_wq,
637 &priv->mfunc.master.comm_work);
640 case MLX4_EVENT_TYPE_FLR_EVENT:
641 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id);
642 if (!mlx4_is_master(dev)) {
643 mlx4_warn(dev, "Non-master function received"
648 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave);
650 if (flr_slave >= dev->num_slaves) {
652 "Got FLR for unknown function: %d\n",
654 update_slave_state = 0;
656 update_slave_state = 1;
658 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
659 if (update_slave_state) {
660 priv->mfunc.master.slave_state[flr_slave].active = false;
661 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR;
662 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1;
664 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
665 queue_work(priv->mfunc.master.comm_wq,
666 &priv->mfunc.master.slave_flr_event_work);
669 case MLX4_EVENT_TYPE_FATAL_WARNING:
670 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) {
671 if (mlx4_is_master(dev))
672 for (i = 0; i < dev->num_slaves; i++) {
673 mlx4_dbg(dev, "%s: Sending "
674 "MLX4_FATAL_WARNING_SUBTYPE_WARMING"
675 " to slave: %d\n", __func__, i);
676 if (i == dev->caps.function)
678 mlx4_slave_event(dev, i, eqe);
680 mlx4_err(dev, "Temperature Threshold was reached! "
681 "Threshold: %d celsius degrees; "
682 "Current Temperature: %d\n",
683 be16_to_cpu(eqe->event.warming.warning_threshold),
684 be16_to_cpu(eqe->event.warming.current_temperature));
686 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), "
687 "subtype %02x on EQ %d at index %u. owner=%x, "
688 "nent=0x%x, slave=%x, ownership=%s\n",
689 eqe->type, eqe->subtype, eq->eqn,
690 eq->cons_index, eqe->owner, eq->nent,
692 !!(eqe->owner & 0x80) ^
693 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
697 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT:
698 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE,
699 (unsigned long) eqe);
702 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR:
703 case MLX4_EVENT_TYPE_ECC_DETECT:
705 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at "
706 "index %u. owner=%x, nent=0x%x, slave=%x, "
708 eqe->type, eqe->subtype, eq->eqn,
709 eq->cons_index, eqe->owner, eq->nent,
711 !!(eqe->owner & 0x80) ^
712 !!(eq->cons_index & eq->nent) ? "HW" : "SW");
721 * The HCA will think the queue has overflowed if we
722 * don't tell it we've been processing events. We
723 * create our EQs with MLX4_NUM_SPARE_EQE extra
724 * entries, so we must update our consumer index at
727 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) {
738 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr)
740 struct mlx4_dev *dev = dev_ptr;
741 struct mlx4_priv *priv = mlx4_priv(dev);
745 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int);
747 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
748 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]);
750 return IRQ_RETVAL(work);
753 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr)
755 struct mlx4_eq *eq = eq_ptr;
756 struct mlx4_dev *dev = eq->dev;
758 mlx4_eq_int(dev, eq);
760 /* MSI-X vectors always belong to us */
764 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
765 struct mlx4_vhcr *vhcr,
766 struct mlx4_cmd_mailbox *inbox,
767 struct mlx4_cmd_mailbox *outbox,
768 struct mlx4_cmd_info *cmd)
770 struct mlx4_priv *priv = mlx4_priv(dev);
771 struct mlx4_slave_event_eq_info *event_eq =
772 priv->mfunc.master.slave_state[slave].event_eq;
773 u32 in_modifier = vhcr->in_modifier;
774 u32 eqn = in_modifier & 0x3FF;
775 u64 in_param = vhcr->in_param;
779 if (slave == dev->caps.function)
780 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn,
781 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
784 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i)
785 if (in_param & (1LL << i))
786 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn;
791 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap,
794 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num,
795 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B,
799 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
802 return mlx4_cmd(dev, mailbox->dma, eq_num, 0,
803 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A,
807 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
810 return mlx4_cmd_box(dev, 0, mailbox->dma, eq_num,
811 0, MLX4_CMD_HW2SW_EQ, MLX4_CMD_TIME_CLASS_A,
815 static int mlx4_num_eq_uar(struct mlx4_dev *dev)
818 * Each UAR holds 4 EQ doorbells. To figure out how many UARs
819 * we need to map, take the difference of highest index and
820 * the lowest index we'll use and add 1.
822 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs +
823 dev->caps.comp_pool)/4 - dev->caps.reserved_eqs/4 + 1;
826 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
828 struct mlx4_priv *priv = mlx4_priv(dev);
831 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
833 if (!priv->eq_table.uar_map[index]) {
834 priv->eq_table.uar_map[index] =
835 ioremap(pci_resource_start(dev->pdev, 2) +
836 ((eq->eqn / 4) << PAGE_SHIFT),
838 if (!priv->eq_table.uar_map[index]) {
839 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n",
845 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4);
848 static void mlx4_unmap_uar(struct mlx4_dev *dev)
850 struct mlx4_priv *priv = mlx4_priv(dev);
853 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
854 if (priv->eq_table.uar_map[i]) {
855 iounmap(priv->eq_table.uar_map[i]);
856 priv->eq_table.uar_map[i] = NULL;
860 static int mlx4_create_eq(struct mlx4_dev *dev, int nent,
861 u8 intr, struct mlx4_eq *eq)
863 struct mlx4_priv *priv = mlx4_priv(dev);
864 struct mlx4_cmd_mailbox *mailbox;
865 struct mlx4_eq_context *eq_context;
867 u64 *dma_list = NULL;
874 eq->nent = roundup_pow_of_two(max(nent, 2));
875 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
876 npages = PAGE_ALIGN(eq->nent * (MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor)) / PAGE_SIZE;
878 eq->page_list = kmalloc(npages * sizeof *eq->page_list,
883 for (i = 0; i < npages; ++i)
884 eq->page_list[i].buf = NULL;
886 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
890 mailbox = mlx4_alloc_cmd_mailbox(dev);
893 eq_context = mailbox->buf;
895 for (i = 0; i < npages; ++i) {
896 eq->page_list[i].buf = dma_alloc_coherent(&dev->pdev->dev,
897 PAGE_SIZE, &t, GFP_KERNEL);
898 if (!eq->page_list[i].buf)
899 goto err_out_free_pages;
902 eq->page_list[i].map = t;
904 memset(eq->page_list[i].buf, 0, PAGE_SIZE);
907 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap);
909 goto err_out_free_pages;
911 eq->doorbell = mlx4_get_eq_uar(dev, eq);
914 goto err_out_free_eq;
917 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt);
919 goto err_out_free_eq;
921 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list);
923 goto err_out_free_mtt;
925 memset(eq_context, 0, sizeof *eq_context);
926 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK |
927 MLX4_EQ_STATE_ARMED);
928 eq_context->log_eq_size = ilog2(eq->nent);
929 eq_context->intr = intr;
930 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT;
932 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt);
933 eq_context->mtt_base_addr_h = mtt_addr >> 32;
934 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
936 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn);
938 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err);
939 goto err_out_free_mtt;
943 mlx4_free_cmd_mailbox(dev, mailbox);
950 mlx4_mtt_cleanup(dev, &eq->mtt);
953 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
956 for (i = 0; i < npages; ++i)
957 if (eq->page_list[i].buf)
958 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
959 eq->page_list[i].buf,
960 eq->page_list[i].map);
962 mlx4_free_cmd_mailbox(dev, mailbox);
965 kfree(eq->page_list);
972 static void mlx4_free_eq(struct mlx4_dev *dev,
975 struct mlx4_priv *priv = mlx4_priv(dev);
976 struct mlx4_cmd_mailbox *mailbox;
979 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes */
980 int npages = PAGE_ALIGN((MLX4_EQ_ENTRY_SIZE << dev->caps.eqe_factor) * eq->nent) / PAGE_SIZE;
982 mailbox = mlx4_alloc_cmd_mailbox(dev);
986 err = mlx4_HW2SW_EQ(dev, mailbox, eq->eqn);
988 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err);
991 mlx4_dbg(dev, "Dumping EQ context %02x:\n", eq->eqn);
992 for (i = 0; i < sizeof (struct mlx4_eq_context) / 4; ++i) {
994 pr_cont("[%02x] ", i * 4);
995 pr_cont(" %08x", be32_to_cpup(mailbox->buf + i * 4));
996 if ((i + 1) % 4 == 0)
1001 mlx4_mtt_cleanup(dev, &eq->mtt);
1002 for (i = 0; i < npages; ++i)
1003 dma_free_coherent(&dev->pdev->dev, PAGE_SIZE,
1004 eq->page_list[i].buf,
1005 eq->page_list[i].map);
1007 kfree(eq->page_list);
1008 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn);
1009 mlx4_free_cmd_mailbox(dev, mailbox);
1012 static void mlx4_free_irqs(struct mlx4_dev *dev)
1014 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table;
1015 struct mlx4_priv *priv = mlx4_priv(dev);
1018 if (eq_table->have_irq)
1019 free_irq(dev->pdev->irq, dev);
1021 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1022 if (eq_table->eq[i].have_irq) {
1023 free_irq(eq_table->eq[i].irq, eq_table->eq + i);
1024 eq_table->eq[i].have_irq = 0;
1027 for (i = 0; i < dev->caps.comp_pool; i++) {
1029 * Freeing the assigned irq's
1030 * all bits should be 0, but we need to validate
1032 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1033 /* NO need protecting*/
1034 vec = dev->caps.num_comp_vectors + 1 + i;
1035 free_irq(priv->eq_table.eq[vec].irq,
1036 &priv->eq_table.eq[vec]);
1041 kfree(eq_table->irq_names);
1044 static int mlx4_map_clr_int(struct mlx4_dev *dev)
1046 struct mlx4_priv *priv = mlx4_priv(dev);
1048 priv->clr_base = ioremap(pci_resource_start(dev->pdev, priv->fw.clr_int_bar) +
1049 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE);
1050 if (!priv->clr_base) {
1051 mlx4_err(dev, "Couldn't map interrupt clear register, aborting.\n");
1058 static void mlx4_unmap_clr_int(struct mlx4_dev *dev)
1060 struct mlx4_priv *priv = mlx4_priv(dev);
1062 iounmap(priv->clr_base);
1065 int mlx4_alloc_eq_table(struct mlx4_dev *dev)
1067 struct mlx4_priv *priv = mlx4_priv(dev);
1069 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs,
1070 sizeof *priv->eq_table.eq, GFP_KERNEL);
1071 if (!priv->eq_table.eq)
1077 void mlx4_free_eq_table(struct mlx4_dev *dev)
1079 kfree(mlx4_priv(dev)->eq_table.eq);
1082 int mlx4_init_eq_table(struct mlx4_dev *dev)
1084 struct mlx4_priv *priv = mlx4_priv(dev);
1088 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev),
1089 sizeof *priv->eq_table.uar_map,
1091 if (!priv->eq_table.uar_map) {
1096 err = mlx4_bitmap_init(&priv->eq_table.bitmap, dev->caps.num_eqs,
1097 dev->caps.num_eqs - 1, dev->caps.reserved_eqs, 0);
1101 for (i = 0; i < mlx4_num_eq_uar(dev); ++i)
1102 priv->eq_table.uar_map[i] = NULL;
1104 if (!mlx4_is_slave(dev)) {
1105 err = mlx4_map_clr_int(dev);
1107 goto err_out_bitmap;
1109 priv->eq_table.clr_mask =
1110 swab32(1 << (priv->eq_table.inta_pin & 31));
1111 priv->eq_table.clr_int = priv->clr_base +
1112 (priv->eq_table.inta_pin < 32 ? 4 : 0);
1115 priv->eq_table.irq_names =
1116 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1 +
1117 dev->caps.comp_pool),
1119 if (!priv->eq_table.irq_names) {
1121 goto err_out_bitmap;
1124 for (i = 0; i < dev->caps.num_comp_vectors; ++i) {
1125 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1126 dev->caps.reserved_cqs +
1128 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1129 &priv->eq_table.eq[i]);
1136 err = mlx4_create_eq(dev, MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE,
1137 (dev->flags & MLX4_FLAG_MSI_X) ? dev->caps.num_comp_vectors : 0,
1138 &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1142 /*if additional completion vectors poolsize is 0 this loop will not run*/
1143 for (i = dev->caps.num_comp_vectors + 1;
1144 i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i) {
1146 err = mlx4_create_eq(dev, dev->caps.num_cqs -
1147 dev->caps.reserved_cqs +
1149 (dev->flags & MLX4_FLAG_MSI_X) ? i : 0,
1150 &priv->eq_table.eq[i]);
1158 if (dev->flags & MLX4_FLAG_MSI_X) {
1159 const char *eq_name;
1161 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) {
1162 if (i < dev->caps.num_comp_vectors) {
1163 snprintf(priv->eq_table.irq_names +
1164 i * MLX4_IRQNAME_SIZE,
1166 "mlx4-comp-%d@pci:%s", i,
1167 pci_name(dev->pdev));
1169 snprintf(priv->eq_table.irq_names +
1170 i * MLX4_IRQNAME_SIZE,
1172 "mlx4-async@pci:%s",
1173 pci_name(dev->pdev));
1176 eq_name = priv->eq_table.irq_names +
1177 i * MLX4_IRQNAME_SIZE;
1178 err = request_irq(priv->eq_table.eq[i].irq,
1179 mlx4_msi_x_interrupt, 0, eq_name,
1180 priv->eq_table.eq + i);
1184 priv->eq_table.eq[i].have_irq = 1;
1187 snprintf(priv->eq_table.irq_names,
1190 pci_name(dev->pdev));
1191 err = request_irq(dev->pdev->irq, mlx4_interrupt,
1192 IRQF_SHARED, priv->eq_table.irq_names, dev);
1196 priv->eq_table.have_irq = 1;
1199 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1200 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1202 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n",
1203 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn, err);
1205 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i)
1206 eq_set_ci(&priv->eq_table.eq[i], 1);
1211 mlx4_free_eq(dev, &priv->eq_table.eq[dev->caps.num_comp_vectors]);
1214 i = dev->caps.num_comp_vectors - 1;
1218 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1221 if (!mlx4_is_slave(dev))
1222 mlx4_unmap_clr_int(dev);
1223 mlx4_free_irqs(dev);
1226 mlx4_unmap_uar(dev);
1227 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1230 kfree(priv->eq_table.uar_map);
1235 void mlx4_cleanup_eq_table(struct mlx4_dev *dev)
1237 struct mlx4_priv *priv = mlx4_priv(dev);
1240 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1,
1241 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1243 mlx4_free_irqs(dev);
1245 for (i = 0; i < dev->caps.num_comp_vectors + dev->caps.comp_pool + 1; ++i)
1246 mlx4_free_eq(dev, &priv->eq_table.eq[i]);
1248 if (!mlx4_is_slave(dev))
1249 mlx4_unmap_clr_int(dev);
1251 mlx4_unmap_uar(dev);
1252 mlx4_bitmap_cleanup(&priv->eq_table.bitmap);
1254 kfree(priv->eq_table.uar_map);
1257 /* A test that verifies that we can accept interrupts on all
1258 * the irq vectors of the device.
1259 * Interrupts are checked using the NOP command.
1261 int mlx4_test_interrupts(struct mlx4_dev *dev)
1263 struct mlx4_priv *priv = mlx4_priv(dev);
1267 err = mlx4_NOP(dev);
1268 /* When not in MSI_X, there is only one irq to check */
1269 if (!(dev->flags & MLX4_FLAG_MSI_X) || mlx4_is_slave(dev))
1272 /* A loop over all completion vectors, for each vector we will check
1273 * whether it works by mapping command completions to that vector
1274 * and performing a NOP command
1276 for(i = 0; !err && (i < dev->caps.num_comp_vectors); ++i) {
1277 /* Temporary use polling for command completions */
1278 mlx4_cmd_use_polling(dev);
1280 /* Map the new eq to handle all asynchronous events */
1281 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1282 priv->eq_table.eq[i].eqn);
1284 mlx4_warn(dev, "Failed mapping eq for interrupt test\n");
1285 mlx4_cmd_use_events(dev);
1289 /* Go back to using events */
1290 mlx4_cmd_use_events(dev);
1291 err = mlx4_NOP(dev);
1294 /* Return to default */
1295 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0,
1296 priv->eq_table.eq[dev->caps.num_comp_vectors].eqn);
1299 EXPORT_SYMBOL(mlx4_test_interrupts);
1301 int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
1305 struct mlx4_priv *priv = mlx4_priv(dev);
1306 int vec = 0, err = 0, i;
1308 mutex_lock(&priv->msix_ctl.pool_lock);
1309 for (i = 0; !vec && i < dev->caps.comp_pool; i++) {
1310 if (~priv->msix_ctl.pool_bm & 1ULL << i) {
1311 priv->msix_ctl.pool_bm |= 1ULL << i;
1312 vec = dev->caps.num_comp_vectors + 1 + i;
1313 snprintf(priv->eq_table.irq_names +
1314 vec * MLX4_IRQNAME_SIZE,
1315 MLX4_IRQNAME_SIZE, "%s", name);
1316 #ifdef CONFIG_RFS_ACCEL
1318 err = irq_cpu_rmap_add(rmap,
1319 priv->eq_table.eq[vec].irq);
1321 mlx4_warn(dev, "Failed adding irq rmap\n");
1324 err = request_irq(priv->eq_table.eq[vec].irq,
1325 mlx4_msi_x_interrupt, 0,
1326 &priv->eq_table.irq_names[vec<<5],
1327 priv->eq_table.eq + vec);
1329 /*zero out bit by fliping it*/
1330 priv->msix_ctl.pool_bm ^= 1 << i;
1333 /*we dont want to break here*/
1335 eq_set_ci(&priv->eq_table.eq[vec], 1);
1338 mutex_unlock(&priv->msix_ctl.pool_lock);
1344 err = (i == dev->caps.comp_pool) ? -ENOSPC : err;
1348 EXPORT_SYMBOL(mlx4_assign_eq);
1350 void mlx4_release_eq(struct mlx4_dev *dev, int vec)
1352 struct mlx4_priv *priv = mlx4_priv(dev);
1354 int i = vec - dev->caps.num_comp_vectors - 1;
1356 if (likely(i >= 0)) {
1357 /*sanity check , making sure were not trying to free irq's
1358 Belonging to a legacy EQ*/
1359 mutex_lock(&priv->msix_ctl.pool_lock);
1360 if (priv->msix_ctl.pool_bm & 1ULL << i) {
1361 free_irq(priv->eq_table.eq[vec].irq,
1362 &priv->eq_table.eq[vec]);
1363 priv->msix_ctl.pool_bm &= ~(1ULL << i);
1365 mutex_unlock(&priv->msix_ctl.pool_lock);
1369 EXPORT_SYMBOL(mlx4_release_eq);