2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kernel.h>
35 #include <linux/ethtool.h>
36 #include <linux/netdevice.h>
37 #include <linux/mlx4/driver.h>
38 #include <linux/mlx4/device.h>
41 #include <linux/bitmap.h>
46 #define EN_ETHTOOL_QP_ATTACH (1ull << 63)
47 #define EN_ETHTOOL_SHORT_MASK cpu_to_be16(0xffff)
48 #define EN_ETHTOOL_WORD_MASK cpu_to_be32(0xffffffff)
50 static int mlx4_en_moderation_update(struct mlx4_en_priv *priv)
55 for (i = 0; i < priv->tx_ring_num; i++) {
56 priv->tx_cq[i]->moder_cnt = priv->tx_frames;
57 priv->tx_cq[i]->moder_time = priv->tx_usecs;
59 err = mlx4_en_set_cq_moder(priv, priv->tx_cq[i]);
65 if (priv->adaptive_rx_coal)
68 for (i = 0; i < priv->rx_ring_num; i++) {
69 priv->rx_cq[i]->moder_cnt = priv->rx_frames;
70 priv->rx_cq[i]->moder_time = priv->rx_usecs;
71 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
73 err = mlx4_en_set_cq_moder(priv, priv->rx_cq[i]);
83 mlx4_en_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *drvinfo)
85 struct mlx4_en_priv *priv = netdev_priv(dev);
86 struct mlx4_en_dev *mdev = priv->mdev;
88 strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
89 strlcpy(drvinfo->version, DRV_VERSION " (" DRV_RELDATE ")",
90 sizeof(drvinfo->version));
91 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
93 (u16) (mdev->dev->caps.fw_ver >> 32),
94 (u16) ((mdev->dev->caps.fw_ver >> 16) & 0xffff),
95 (u16) (mdev->dev->caps.fw_ver & 0xffff));
96 strlcpy(drvinfo->bus_info, pci_name(mdev->dev->persist->pdev),
97 sizeof(drvinfo->bus_info));
99 drvinfo->regdump_len = 0;
100 drvinfo->eedump_len = 0;
103 static const char mlx4_en_priv_flags[][ETH_GSTRING_LEN] = {
107 static const char main_strings[][ETH_GSTRING_LEN] = {
108 /* main statistics */
109 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
110 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
111 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
112 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
113 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
114 "tx_heartbeat_errors", "tx_window_errors",
116 /* port statistics */
119 "queue_stopped", "wake_queue", "tx_timeout", "rx_alloc_failed",
120 "rx_csum_good", "rx_csum_none", "rx_csum_complete", "tx_chksum_offload",
122 /* priority flow control statistics rx */
123 "rx_pause_prio_0", "rx_pause_duration_prio_0",
124 "rx_pause_transition_prio_0",
125 "rx_pause_prio_1", "rx_pause_duration_prio_1",
126 "rx_pause_transition_prio_1",
127 "rx_pause_prio_2", "rx_pause_duration_prio_2",
128 "rx_pause_transition_prio_2",
129 "rx_pause_prio_3", "rx_pause_duration_prio_3",
130 "rx_pause_transition_prio_3",
131 "rx_pause_prio_4", "rx_pause_duration_prio_4",
132 "rx_pause_transition_prio_4",
133 "rx_pause_prio_5", "rx_pause_duration_prio_5",
134 "rx_pause_transition_prio_5",
135 "rx_pause_prio_6", "rx_pause_duration_prio_6",
136 "rx_pause_transition_prio_6",
137 "rx_pause_prio_7", "rx_pause_duration_prio_7",
138 "rx_pause_transition_prio_7",
140 /* flow control statistics rx */
141 "rx_pause", "rx_pause_duration", "rx_pause_transition",
143 /* priority flow control statistics tx */
144 "tx_pause_prio_0", "tx_pause_duration_prio_0",
145 "tx_pause_transition_prio_0",
146 "tx_pause_prio_1", "tx_pause_duration_prio_1",
147 "tx_pause_transition_prio_1",
148 "tx_pause_prio_2", "tx_pause_duration_prio_2",
149 "tx_pause_transition_prio_2",
150 "tx_pause_prio_3", "tx_pause_duration_prio_3",
151 "tx_pause_transition_prio_3",
152 "tx_pause_prio_4", "tx_pause_duration_prio_4",
153 "tx_pause_transition_prio_4",
154 "tx_pause_prio_5", "tx_pause_duration_prio_5",
155 "tx_pause_transition_prio_5",
156 "tx_pause_prio_6", "tx_pause_duration_prio_6",
157 "tx_pause_transition_prio_6",
158 "tx_pause_prio_7", "tx_pause_duration_prio_7",
159 "tx_pause_transition_prio_7",
161 /* flow control statistics tx */
162 "tx_pause", "tx_pause_duration", "tx_pause_transition",
164 /* packet statistics */
165 "rx_multicast_packets",
166 "rx_broadcast_packets",
168 "rx_in_range_length_error",
169 "rx_out_range_length_error",
170 "tx_multicast_packets",
171 "tx_broadcast_packets",
172 "rx_prio_0_packets", "rx_prio_0_bytes",
173 "rx_prio_1_packets", "rx_prio_1_bytes",
174 "rx_prio_2_packets", "rx_prio_2_bytes",
175 "rx_prio_3_packets", "rx_prio_3_bytes",
176 "rx_prio_4_packets", "rx_prio_4_bytes",
177 "rx_prio_5_packets", "rx_prio_5_bytes",
178 "rx_prio_6_packets", "rx_prio_6_bytes",
179 "rx_prio_7_packets", "rx_prio_7_bytes",
180 "rx_novlan_packets", "rx_novlan_bytes",
181 "tx_prio_0_packets", "tx_prio_0_bytes",
182 "tx_prio_1_packets", "tx_prio_1_bytes",
183 "tx_prio_2_packets", "tx_prio_2_bytes",
184 "tx_prio_3_packets", "tx_prio_3_bytes",
185 "tx_prio_4_packets", "tx_prio_4_bytes",
186 "tx_prio_5_packets", "tx_prio_5_bytes",
187 "tx_prio_6_packets", "tx_prio_6_bytes",
188 "tx_prio_7_packets", "tx_prio_7_bytes",
189 "tx_novlan_packets", "tx_novlan_bytes",
193 static const char mlx4_en_test_names[][ETH_GSTRING_LEN]= {
201 static u32 mlx4_en_get_msglevel(struct net_device *dev)
203 return ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable;
206 static void mlx4_en_set_msglevel(struct net_device *dev, u32 val)
208 ((struct mlx4_en_priv *) netdev_priv(dev))->msg_enable = val;
211 static void mlx4_en_get_wol(struct net_device *netdev,
212 struct ethtool_wolinfo *wol)
214 struct mlx4_en_priv *priv = netdev_priv(netdev);
219 if ((priv->port < 1) || (priv->port > 2)) {
220 en_err(priv, "Failed to get WoL information\n");
224 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
225 MLX4_DEV_CAP_FLAG_WOL_PORT2;
227 if (!(priv->mdev->dev->caps.flags & mask)) {
233 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
235 en_err(priv, "Failed to get WoL information\n");
239 if (config & MLX4_EN_WOL_MAGIC)
240 wol->supported = WAKE_MAGIC;
244 if (config & MLX4_EN_WOL_ENABLED)
245 wol->wolopts = WAKE_MAGIC;
250 static int mlx4_en_set_wol(struct net_device *netdev,
251 struct ethtool_wolinfo *wol)
253 struct mlx4_en_priv *priv = netdev_priv(netdev);
258 if ((priv->port < 1) || (priv->port > 2))
261 mask = (priv->port == 1) ? MLX4_DEV_CAP_FLAG_WOL_PORT1 :
262 MLX4_DEV_CAP_FLAG_WOL_PORT2;
264 if (!(priv->mdev->dev->caps.flags & mask))
267 if (wol->supported & ~WAKE_MAGIC)
270 err = mlx4_wol_read(priv->mdev->dev, &config, priv->port);
272 en_err(priv, "Failed to get WoL info, unable to modify\n");
276 if (wol->wolopts & WAKE_MAGIC) {
277 config |= MLX4_EN_WOL_DO_MODIFY | MLX4_EN_WOL_ENABLED |
280 config &= ~(MLX4_EN_WOL_ENABLED | MLX4_EN_WOL_MAGIC);
281 config |= MLX4_EN_WOL_DO_MODIFY;
284 err = mlx4_wol_write(priv->mdev->dev, config, priv->port);
286 en_err(priv, "Failed to set WoL information\n");
291 struct bitmap_iterator {
292 unsigned long *stats_bitmap;
294 unsigned int iterator;
295 bool advance_array; /* if set, force no increments */
298 static inline void bitmap_iterator_init(struct bitmap_iterator *h,
299 unsigned long *stats_bitmap,
303 h->advance_array = !bitmap_empty(stats_bitmap, count);
304 h->count = h->advance_array ? bitmap_weight(stats_bitmap, count)
306 h->stats_bitmap = stats_bitmap;
309 static inline int bitmap_iterator_test(struct bitmap_iterator *h)
311 return !h->advance_array ? 1 : test_bit(h->iterator, h->stats_bitmap);
314 static inline int bitmap_iterator_inc(struct bitmap_iterator *h)
316 return h->iterator++;
319 static inline unsigned int
320 bitmap_iterator_count(struct bitmap_iterator *h)
325 static int mlx4_en_get_sset_count(struct net_device *dev, int sset)
327 struct mlx4_en_priv *priv = netdev_priv(dev);
328 struct bitmap_iterator it;
330 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
334 return bitmap_iterator_count(&it) +
335 (priv->tx_ring_num * 2) +
336 #ifdef CONFIG_NET_RX_BUSY_POLL
337 (priv->rx_ring_num * 5);
339 (priv->rx_ring_num * 2);
342 return MLX4_EN_NUM_SELF_TEST - !(priv->mdev->dev->caps.flags
343 & MLX4_DEV_CAP_FLAG_UC_LOOPBACK) * 2;
344 case ETH_SS_PRIV_FLAGS:
345 return ARRAY_SIZE(mlx4_en_priv_flags);
351 static void mlx4_en_get_ethtool_stats(struct net_device *dev,
352 struct ethtool_stats *stats, uint64_t *data)
354 struct mlx4_en_priv *priv = netdev_priv(dev);
357 struct bitmap_iterator it;
359 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
361 spin_lock_bh(&priv->stats_lock);
363 for (i = 0; i < NUM_MAIN_STATS; i++, bitmap_iterator_inc(&it))
364 if (bitmap_iterator_test(&it))
365 data[index++] = ((unsigned long *)&priv->stats)[i];
367 for (i = 0; i < NUM_PORT_STATS; i++, bitmap_iterator_inc(&it))
368 if (bitmap_iterator_test(&it))
369 data[index++] = ((unsigned long *)&priv->port_stats)[i];
371 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_RX;
372 i++, bitmap_iterator_inc(&it))
373 if (bitmap_iterator_test(&it))
375 ((u64 *)&priv->rx_priority_flowstats)[i];
377 for (i = 0; i < NUM_FLOW_STATS_RX; i++, bitmap_iterator_inc(&it))
378 if (bitmap_iterator_test(&it))
379 data[index++] = ((u64 *)&priv->rx_flowstats)[i];
381 for (i = 0; i < NUM_FLOW_PRIORITY_STATS_TX;
382 i++, bitmap_iterator_inc(&it))
383 if (bitmap_iterator_test(&it))
385 ((u64 *)&priv->tx_priority_flowstats)[i];
387 for (i = 0; i < NUM_FLOW_STATS_TX; i++, bitmap_iterator_inc(&it))
388 if (bitmap_iterator_test(&it))
389 data[index++] = ((u64 *)&priv->tx_flowstats)[i];
391 for (i = 0; i < NUM_PKT_STATS; i++, bitmap_iterator_inc(&it))
392 if (bitmap_iterator_test(&it))
393 data[index++] = ((unsigned long *)&priv->pkstats)[i];
395 for (i = 0; i < priv->tx_ring_num; i++) {
396 data[index++] = priv->tx_ring[i]->packets;
397 data[index++] = priv->tx_ring[i]->bytes;
399 for (i = 0; i < priv->rx_ring_num; i++) {
400 data[index++] = priv->rx_ring[i]->packets;
401 data[index++] = priv->rx_ring[i]->bytes;
402 #ifdef CONFIG_NET_RX_BUSY_POLL
403 data[index++] = priv->rx_ring[i]->yields;
404 data[index++] = priv->rx_ring[i]->misses;
405 data[index++] = priv->rx_ring[i]->cleaned;
408 spin_unlock_bh(&priv->stats_lock);
412 static void mlx4_en_self_test(struct net_device *dev,
413 struct ethtool_test *etest, u64 *buf)
415 mlx4_en_ex_selftest(dev, &etest->flags, buf);
418 static void mlx4_en_get_strings(struct net_device *dev,
419 uint32_t stringset, uint8_t *data)
421 struct mlx4_en_priv *priv = netdev_priv(dev);
424 struct bitmap_iterator it;
426 bitmap_iterator_init(&it, priv->stats_bitmap.bitmap, NUM_ALL_STATS);
430 for (i = 0; i < MLX4_EN_NUM_SELF_TEST - 2; i++)
431 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
432 if (priv->mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UC_LOOPBACK)
433 for (; i < MLX4_EN_NUM_SELF_TEST; i++)
434 strcpy(data + i * ETH_GSTRING_LEN, mlx4_en_test_names[i]);
438 /* Add main counters */
439 for (i = 0; i < NUM_MAIN_STATS; i++, strings++,
440 bitmap_iterator_inc(&it))
441 if (bitmap_iterator_test(&it))
442 strcpy(data + (index++) * ETH_GSTRING_LEN,
443 main_strings[strings]);
445 for (i = 0; i < NUM_PORT_STATS; i++, strings++,
446 bitmap_iterator_inc(&it))
447 if (bitmap_iterator_test(&it))
448 strcpy(data + (index++) * ETH_GSTRING_LEN,
449 main_strings[strings]);
451 for (i = 0; i < NUM_FLOW_STATS; i++, strings++,
452 bitmap_iterator_inc(&it))
453 if (bitmap_iterator_test(&it))
454 strcpy(data + (index++) * ETH_GSTRING_LEN,
455 main_strings[strings]);
457 for (i = 0; i < NUM_PKT_STATS; i++, strings++,
458 bitmap_iterator_inc(&it))
459 if (bitmap_iterator_test(&it))
460 strcpy(data + (index++) * ETH_GSTRING_LEN,
461 main_strings[strings]);
463 for (i = 0; i < priv->tx_ring_num; i++) {
464 sprintf(data + (index++) * ETH_GSTRING_LEN,
466 sprintf(data + (index++) * ETH_GSTRING_LEN,
469 for (i = 0; i < priv->rx_ring_num; i++) {
470 sprintf(data + (index++) * ETH_GSTRING_LEN,
472 sprintf(data + (index++) * ETH_GSTRING_LEN,
474 #ifdef CONFIG_NET_RX_BUSY_POLL
475 sprintf(data + (index++) * ETH_GSTRING_LEN,
476 "rx%d_napi_yield", i);
477 sprintf(data + (index++) * ETH_GSTRING_LEN,
479 sprintf(data + (index++) * ETH_GSTRING_LEN,
484 case ETH_SS_PRIV_FLAGS:
485 for (i = 0; i < ARRAY_SIZE(mlx4_en_priv_flags); i++)
486 strcpy(data + i * ETH_GSTRING_LEN,
487 mlx4_en_priv_flags[i]);
493 static u32 mlx4_en_autoneg_get(struct net_device *dev)
495 struct mlx4_en_priv *priv = netdev_priv(dev);
496 struct mlx4_en_dev *mdev = priv->mdev;
497 u32 autoneg = AUTONEG_DISABLE;
499 if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
500 (priv->port_state.flags & MLX4_EN_PORT_ANE))
501 autoneg = AUTONEG_ENABLE;
506 static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg)
508 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
510 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
511 | MLX4_PROT_MASK(MLX4_1000BASE_T)
512 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
516 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
517 | MLX4_PROT_MASK(MLX4_10GBASE_SR)
518 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
519 | MLX4_PROT_MASK(MLX4_40GBASE_CR4)
520 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
521 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
522 return SUPPORTED_FIBRE;
525 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
526 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
527 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
528 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
529 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
530 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
531 return SUPPORTED_Backplane;
536 static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
538 u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
540 if (!eth_proto) /* link down */
541 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
543 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
544 | MLX4_PROT_MASK(MLX4_1000BASE_T)
545 | MLX4_PROT_MASK(MLX4_100BASE_TX))) {
549 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
550 | MLX4_PROT_MASK(MLX4_56GBASE_SR4)
551 | MLX4_PROT_MASK(MLX4_40GBASE_SR4)
552 | MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
556 if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
557 | MLX4_PROT_MASK(MLX4_56GBASE_CR4)
558 | MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
562 if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
563 | MLX4_PROT_MASK(MLX4_40GBASE_KR4)
564 | MLX4_PROT_MASK(MLX4_20GBASE_KR2)
565 | MLX4_PROT_MASK(MLX4_10GBASE_KR)
566 | MLX4_PROT_MASK(MLX4_10GBASE_KX4)
567 | MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
573 #define MLX4_LINK_MODES_SZ \
574 (FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
576 enum ethtool_report {
582 /* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
583 static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = {
584 [MLX4_100BASE_TX] = {
585 SUPPORTED_100baseT_Full,
586 ADVERTISED_100baseT_Full,
590 [MLX4_1000BASE_T] = {
591 SUPPORTED_1000baseT_Full,
592 ADVERTISED_1000baseT_Full,
595 [MLX4_1000BASE_CX_SGMII] = {
596 SUPPORTED_1000baseKX_Full,
597 ADVERTISED_1000baseKX_Full,
600 [MLX4_1000BASE_KX] = {
601 SUPPORTED_1000baseKX_Full,
602 ADVERTISED_1000baseKX_Full,
607 SUPPORTED_10000baseT_Full,
608 ADVERTISED_10000baseT_Full,
611 [MLX4_10GBASE_CX4] = {
612 SUPPORTED_10000baseKX4_Full,
613 ADVERTISED_10000baseKX4_Full,
616 [MLX4_10GBASE_KX4] = {
617 SUPPORTED_10000baseKX4_Full,
618 ADVERTISED_10000baseKX4_Full,
621 [MLX4_10GBASE_KR] = {
622 SUPPORTED_10000baseKR_Full,
623 ADVERTISED_10000baseKR_Full,
626 [MLX4_10GBASE_CR] = {
627 SUPPORTED_10000baseKR_Full,
628 ADVERTISED_10000baseKR_Full,
631 [MLX4_10GBASE_SR] = {
632 SUPPORTED_10000baseKR_Full,
633 ADVERTISED_10000baseKR_Full,
637 [MLX4_20GBASE_KR2] = {
638 SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full,
639 ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full,
643 [MLX4_40GBASE_CR4] = {
644 SUPPORTED_40000baseCR4_Full,
645 ADVERTISED_40000baseCR4_Full,
648 [MLX4_40GBASE_KR4] = {
649 SUPPORTED_40000baseKR4_Full,
650 ADVERTISED_40000baseKR4_Full,
653 [MLX4_40GBASE_SR4] = {
654 SUPPORTED_40000baseSR4_Full,
655 ADVERTISED_40000baseSR4_Full,
659 [MLX4_56GBASE_KR4] = {
660 SUPPORTED_56000baseKR4_Full,
661 ADVERTISED_56000baseKR4_Full,
664 [MLX4_56GBASE_CR4] = {
665 SUPPORTED_56000baseCR4_Full,
666 ADVERTISED_56000baseCR4_Full,
669 [MLX4_56GBASE_SR4] = {
670 SUPPORTED_56000baseSR4_Full,
671 ADVERTISED_56000baseSR4_Full,
676 static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report)
681 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
682 if (eth_proto & MLX4_PROT_MASK(i))
683 link_modes |= ptys2ethtool_map[i][report];
688 static u32 ethtool2ptys_link_modes(u32 link_modes, enum ethtool_report report)
693 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
694 if (ptys2ethtool_map[i][report] & link_modes)
695 ptys_modes |= 1 << i;
700 /* Convert actual speed (SPEED_XXX) to ptys link modes */
701 static u32 speed2ptys_link_modes(u32 speed)
706 for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
707 if (ptys2ethtool_map[i][SPEED] == speed)
708 ptys_modes |= 1 << i;
713 static int ethtool_get_ptys_settings(struct net_device *dev,
714 struct ethtool_cmd *cmd)
716 struct mlx4_en_priv *priv = netdev_priv(dev);
717 struct mlx4_ptys_reg ptys_reg;
721 memset(&ptys_reg, 0, sizeof(ptys_reg));
722 ptys_reg.local_port = priv->port;
723 ptys_reg.proto_mask = MLX4_PTYS_EN;
724 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
725 MLX4_ACCESS_REG_QUERY, &ptys_reg);
727 en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
731 en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
732 ptys_reg.proto_mask);
733 en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
734 be32_to_cpu(ptys_reg.eth_proto_cap));
735 en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
736 be32_to_cpu(ptys_reg.eth_proto_admin));
737 en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
738 be32_to_cpu(ptys_reg.eth_proto_oper));
739 en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
740 be32_to_cpu(ptys_reg.eth_proto_lp_adv));
743 cmd->advertising = 0;
745 cmd->supported |= ptys_get_supported_port(&ptys_reg);
747 eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
748 cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED);
750 eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
751 cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED);
753 cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
754 cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0;
756 cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ?
757 ADVERTISED_Asym_Pause : 0;
759 cmd->port = ptys_get_active_port(&ptys_reg);
760 cmd->transceiver = (SUPPORTED_TP & cmd->supported) ?
761 XCVR_EXTERNAL : XCVR_INTERNAL;
763 if (mlx4_en_autoneg_get(dev)) {
764 cmd->supported |= SUPPORTED_Autoneg;
765 cmd->advertising |= ADVERTISED_Autoneg;
768 cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
769 AUTONEG_ENABLE : AUTONEG_DISABLE;
771 eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
772 cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED);
774 cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
775 ADVERTISED_Autoneg : 0;
777 cmd->phy_address = 0;
778 cmd->mdio_support = 0;
781 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
782 cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
787 static void ethtool_get_default_settings(struct net_device *dev,
788 struct ethtool_cmd *cmd)
790 struct mlx4_en_priv *priv = netdev_priv(dev);
793 cmd->autoneg = AUTONEG_DISABLE;
794 cmd->supported = SUPPORTED_10000baseT_Full;
795 cmd->advertising = ADVERTISED_10000baseT_Full;
796 trans_type = priv->port_state.transceiver;
798 if (trans_type > 0 && trans_type <= 0xC) {
799 cmd->port = PORT_FIBRE;
800 cmd->transceiver = XCVR_EXTERNAL;
801 cmd->supported |= SUPPORTED_FIBRE;
802 cmd->advertising |= ADVERTISED_FIBRE;
803 } else if (trans_type == 0x80 || trans_type == 0) {
805 cmd->transceiver = XCVR_INTERNAL;
806 cmd->supported |= SUPPORTED_TP;
807 cmd->advertising |= ADVERTISED_TP;
810 cmd->transceiver = -1;
814 static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
816 struct mlx4_en_priv *priv = netdev_priv(dev);
819 if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
822 en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
823 priv->port_state.flags & MLX4_EN_PORT_ANC,
824 priv->port_state.flags & MLX4_EN_PORT_ANE);
826 if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
827 ret = ethtool_get_ptys_settings(dev, cmd);
828 if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
829 ethtool_get_default_settings(dev, cmd);
831 if (netif_carrier_ok(dev)) {
832 ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
833 cmd->duplex = DUPLEX_FULL;
835 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
836 cmd->duplex = DUPLEX_UNKNOWN;
841 /* Calculate PTYS admin according ethtool speed (SPEED_XXX) */
842 static __be32 speed_set_ptys_admin(struct mlx4_en_priv *priv, u32 speed,
845 __be32 proto_admin = 0;
847 if (!speed) { /* Speed = 0 ==> Reset Link modes */
848 proto_admin = proto_cap;
849 en_info(priv, "Speed was set to 0, Reset advertised Link Modes to default (%x)\n",
850 be32_to_cpu(proto_cap));
852 u32 ptys_link_modes = speed2ptys_link_modes(speed);
854 proto_admin = cpu_to_be32(ptys_link_modes) & proto_cap;
855 en_info(priv, "Setting Speed to %d\n", speed);
860 static int mlx4_en_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
862 struct mlx4_en_priv *priv = netdev_priv(dev);
863 struct mlx4_ptys_reg ptys_reg;
867 u32 ptys_adv = ethtool2ptys_link_modes(cmd->advertising, ADVERTISED);
868 int speed = ethtool_cmd_speed(cmd);
870 en_dbg(DRV, priv, "Set Speed=%d adv=0x%x autoneg=%d duplex=%d\n",
871 speed, cmd->advertising, cmd->autoneg, cmd->duplex);
873 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL) ||
874 (cmd->duplex == DUPLEX_HALF))
877 memset(&ptys_reg, 0, sizeof(ptys_reg));
878 ptys_reg.local_port = priv->port;
879 ptys_reg.proto_mask = MLX4_PTYS_EN;
880 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
881 MLX4_ACCESS_REG_QUERY, &ptys_reg);
883 en_warn(priv, "Failed to QUERY mlx4_ACCESS_PTYS_REG status(%x)\n",
888 proto_admin = cmd->autoneg == AUTONEG_ENABLE ?
889 cpu_to_be32(ptys_adv) :
890 speed_set_ptys_admin(priv, speed,
891 ptys_reg.eth_proto_cap);
893 proto_admin &= ptys_reg.eth_proto_cap;
895 en_warn(priv, "Not supported link mode(s) requested, check supported link modes.\n");
896 return -EINVAL; /* nothing to change due to bad input */
899 if (proto_admin == ptys_reg.eth_proto_admin)
900 return 0; /* Nothing to change */
902 en_dbg(DRV, priv, "mlx4_ACCESS_PTYS_REG SET: ptys_reg.eth_proto_admin = 0x%x\n",
903 be32_to_cpu(proto_admin));
905 ptys_reg.eth_proto_admin = proto_admin;
906 ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev, MLX4_ACCESS_REG_WRITE,
909 en_warn(priv, "Failed to write mlx4_ACCESS_PTYS_REG eth_proto_admin(0x%x) status(0x%x)",
910 be32_to_cpu(ptys_reg.eth_proto_admin), ret);
914 mutex_lock(&priv->mdev->state_lock);
916 en_warn(priv, "Port link mode changed, restarting port...\n");
917 mlx4_en_stop_port(dev, 1);
918 if (mlx4_en_start_port(dev))
919 en_err(priv, "Failed restarting port %d\n", priv->port);
921 mutex_unlock(&priv->mdev->state_lock);
925 static int mlx4_en_get_coalesce(struct net_device *dev,
926 struct ethtool_coalesce *coal)
928 struct mlx4_en_priv *priv = netdev_priv(dev);
930 coal->tx_coalesce_usecs = priv->tx_usecs;
931 coal->tx_max_coalesced_frames = priv->tx_frames;
932 coal->tx_max_coalesced_frames_irq = priv->tx_work_limit;
934 coal->rx_coalesce_usecs = priv->rx_usecs;
935 coal->rx_max_coalesced_frames = priv->rx_frames;
937 coal->pkt_rate_low = priv->pkt_rate_low;
938 coal->rx_coalesce_usecs_low = priv->rx_usecs_low;
939 coal->pkt_rate_high = priv->pkt_rate_high;
940 coal->rx_coalesce_usecs_high = priv->rx_usecs_high;
941 coal->rate_sample_interval = priv->sample_interval;
942 coal->use_adaptive_rx_coalesce = priv->adaptive_rx_coal;
947 static int mlx4_en_set_coalesce(struct net_device *dev,
948 struct ethtool_coalesce *coal)
950 struct mlx4_en_priv *priv = netdev_priv(dev);
952 if (!coal->tx_max_coalesced_frames_irq)
955 priv->rx_frames = (coal->rx_max_coalesced_frames ==
957 MLX4_EN_RX_COAL_TARGET :
958 coal->rx_max_coalesced_frames;
959 priv->rx_usecs = (coal->rx_coalesce_usecs ==
961 MLX4_EN_RX_COAL_TIME :
962 coal->rx_coalesce_usecs;
964 /* Setting TX coalescing parameters */
965 if (coal->tx_coalesce_usecs != priv->tx_usecs ||
966 coal->tx_max_coalesced_frames != priv->tx_frames) {
967 priv->tx_usecs = coal->tx_coalesce_usecs;
968 priv->tx_frames = coal->tx_max_coalesced_frames;
971 /* Set adaptive coalescing params */
972 priv->pkt_rate_low = coal->pkt_rate_low;
973 priv->rx_usecs_low = coal->rx_coalesce_usecs_low;
974 priv->pkt_rate_high = coal->pkt_rate_high;
975 priv->rx_usecs_high = coal->rx_coalesce_usecs_high;
976 priv->sample_interval = coal->rate_sample_interval;
977 priv->adaptive_rx_coal = coal->use_adaptive_rx_coalesce;
978 priv->tx_work_limit = coal->tx_max_coalesced_frames_irq;
980 return mlx4_en_moderation_update(priv);
983 static int mlx4_en_set_pauseparam(struct net_device *dev,
984 struct ethtool_pauseparam *pause)
986 struct mlx4_en_priv *priv = netdev_priv(dev);
987 struct mlx4_en_dev *mdev = priv->mdev;
993 priv->prof->tx_pause = pause->tx_pause != 0;
994 priv->prof->rx_pause = pause->rx_pause != 0;
995 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
996 priv->rx_skb_size + ETH_FCS_LEN,
997 priv->prof->tx_pause,
999 priv->prof->rx_pause,
1000 priv->prof->rx_ppp);
1002 en_err(priv, "Failed setting pause params\n");
1004 mlx4_en_update_pfc_stats_bitmap(mdev->dev, &priv->stats_bitmap,
1006 priv->prof->rx_pause,
1008 priv->prof->tx_pause);
1013 static void mlx4_en_get_pauseparam(struct net_device *dev,
1014 struct ethtool_pauseparam *pause)
1016 struct mlx4_en_priv *priv = netdev_priv(dev);
1018 pause->tx_pause = priv->prof->tx_pause;
1019 pause->rx_pause = priv->prof->rx_pause;
1022 static int mlx4_en_set_ringparam(struct net_device *dev,
1023 struct ethtool_ringparam *param)
1025 struct mlx4_en_priv *priv = netdev_priv(dev);
1026 struct mlx4_en_dev *mdev = priv->mdev;
1027 u32 rx_size, tx_size;
1031 if (param->rx_jumbo_pending || param->rx_mini_pending)
1034 rx_size = roundup_pow_of_two(param->rx_pending);
1035 rx_size = max_t(u32, rx_size, MLX4_EN_MIN_RX_SIZE);
1036 rx_size = min_t(u32, rx_size, MLX4_EN_MAX_RX_SIZE);
1037 tx_size = roundup_pow_of_two(param->tx_pending);
1038 tx_size = max_t(u32, tx_size, MLX4_EN_MIN_TX_SIZE);
1039 tx_size = min_t(u32, tx_size, MLX4_EN_MAX_TX_SIZE);
1041 if (rx_size == (priv->port_up ? priv->rx_ring[0]->actual_size :
1042 priv->rx_ring[0]->size) &&
1043 tx_size == priv->tx_ring[0]->size)
1046 mutex_lock(&mdev->state_lock);
1047 if (priv->port_up) {
1049 mlx4_en_stop_port(dev, 1);
1052 mlx4_en_free_resources(priv);
1054 priv->prof->tx_ring_size = tx_size;
1055 priv->prof->rx_ring_size = rx_size;
1057 err = mlx4_en_alloc_resources(priv);
1059 en_err(priv, "Failed reallocating port resources\n");
1063 err = mlx4_en_start_port(dev);
1065 en_err(priv, "Failed starting port\n");
1068 err = mlx4_en_moderation_update(priv);
1071 mutex_unlock(&mdev->state_lock);
1075 static void mlx4_en_get_ringparam(struct net_device *dev,
1076 struct ethtool_ringparam *param)
1078 struct mlx4_en_priv *priv = netdev_priv(dev);
1080 memset(param, 0, sizeof(*param));
1081 param->rx_max_pending = MLX4_EN_MAX_RX_SIZE;
1082 param->tx_max_pending = MLX4_EN_MAX_TX_SIZE;
1083 param->rx_pending = priv->port_up ?
1084 priv->rx_ring[0]->actual_size : priv->rx_ring[0]->size;
1085 param->tx_pending = priv->tx_ring[0]->size;
1088 static u32 mlx4_en_get_rxfh_indir_size(struct net_device *dev)
1090 struct mlx4_en_priv *priv = netdev_priv(dev);
1092 return priv->rx_ring_num;
1095 static u32 mlx4_en_get_rxfh_key_size(struct net_device *netdev)
1097 return MLX4_EN_RSS_KEY_SIZE;
1100 static int mlx4_en_check_rxfh_func(struct net_device *dev, u8 hfunc)
1102 struct mlx4_en_priv *priv = netdev_priv(dev);
1104 /* check if requested function is supported by the device */
1105 if ((hfunc == ETH_RSS_HASH_TOP &&
1106 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) ||
1107 (hfunc == ETH_RSS_HASH_XOR &&
1108 !(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR)))
1111 priv->rss_hash_fn = hfunc;
1112 if (hfunc == ETH_RSS_HASH_TOP && !(dev->features & NETIF_F_RXHASH))
1114 "Toeplitz hash function should be used in conjunction with RX hashing for optimal performance\n");
1115 if (hfunc == ETH_RSS_HASH_XOR && (dev->features & NETIF_F_RXHASH))
1117 "Enabling both XOR Hash function and RX Hashing can limit RPS functionality\n");
1121 static int mlx4_en_get_rxfh(struct net_device *dev, u32 *ring_index, u8 *key,
1124 struct mlx4_en_priv *priv = netdev_priv(dev);
1125 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
1127 size_t n = priv->rx_ring_num;
1130 rss_rings = priv->prof->rss_rings ?: priv->rx_ring_num;
1131 rss_rings = 1 << ilog2(rss_rings);
1136 ring_index[n] = rss_map->qps[n % rss_rings].qpn -
1140 memcpy(key, priv->rss_key, MLX4_EN_RSS_KEY_SIZE);
1142 *hfunc = priv->rss_hash_fn;
1146 static int mlx4_en_set_rxfh(struct net_device *dev, const u32 *ring_index,
1147 const u8 *key, const u8 hfunc)
1149 struct mlx4_en_priv *priv = netdev_priv(dev);
1150 struct mlx4_en_dev *mdev = priv->mdev;
1156 /* Calculate RSS table size and make sure flows are spread evenly
1159 for (i = 0; i < priv->rx_ring_num; i++) {
1162 if (i > 0 && !ring_index[i] && !rss_rings)
1165 if (ring_index[i] != (i % (rss_rings ?: priv->rx_ring_num)))
1170 rss_rings = priv->rx_ring_num;
1172 /* RSS table size must be an order of 2 */
1173 if (!is_power_of_2(rss_rings))
1176 if (hfunc != ETH_RSS_HASH_NO_CHANGE) {
1177 err = mlx4_en_check_rxfh_func(dev, hfunc);
1182 mutex_lock(&mdev->state_lock);
1183 if (priv->port_up) {
1185 mlx4_en_stop_port(dev, 1);
1189 priv->prof->rss_rings = rss_rings;
1191 memcpy(priv->rss_key, key, MLX4_EN_RSS_KEY_SIZE);
1194 err = mlx4_en_start_port(dev);
1196 en_err(priv, "Failed starting port\n");
1199 mutex_unlock(&mdev->state_lock);
1203 #define all_zeros_or_all_ones(field) \
1204 ((field) == 0 || (field) == (__force typeof(field))-1)
1206 static int mlx4_en_validate_flow(struct net_device *dev,
1207 struct ethtool_rxnfc *cmd)
1209 struct ethtool_usrip4_spec *l3_mask;
1210 struct ethtool_tcpip4_spec *l4_mask;
1211 struct ethhdr *eth_mask;
1213 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1216 if (cmd->fs.flow_type & FLOW_MAC_EXT) {
1217 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1218 if (!is_broadcast_ether_addr(cmd->fs.m_ext.h_dest))
1222 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1225 if (cmd->fs.m_u.tcp_ip4_spec.tos)
1227 l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1228 /* don't allow mask which isn't all 0 or 1 */
1229 if (!all_zeros_or_all_ones(l4_mask->ip4src) ||
1230 !all_zeros_or_all_ones(l4_mask->ip4dst) ||
1231 !all_zeros_or_all_ones(l4_mask->psrc) ||
1232 !all_zeros_or_all_ones(l4_mask->pdst))
1236 l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1237 if (l3_mask->l4_4_bytes || l3_mask->tos || l3_mask->proto ||
1238 cmd->fs.h_u.usr_ip4_spec.ip_ver != ETH_RX_NFC_IP4 ||
1239 (!l3_mask->ip4src && !l3_mask->ip4dst) ||
1240 !all_zeros_or_all_ones(l3_mask->ip4src) ||
1241 !all_zeros_or_all_ones(l3_mask->ip4dst))
1245 eth_mask = &cmd->fs.m_u.ether_spec;
1246 /* source mac mask must not be set */
1247 if (!is_zero_ether_addr(eth_mask->h_source))
1250 /* dest mac mask must be ff:ff:ff:ff:ff:ff */
1251 if (!is_broadcast_ether_addr(eth_mask->h_dest))
1254 if (!all_zeros_or_all_ones(eth_mask->h_proto))
1261 if ((cmd->fs.flow_type & FLOW_EXT)) {
1262 if (cmd->fs.m_ext.vlan_etype ||
1263 !((cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1265 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK)) ==
1266 cpu_to_be16(VLAN_VID_MASK)))
1269 if (cmd->fs.m_ext.vlan_tci) {
1270 if (be16_to_cpu(cmd->fs.h_ext.vlan_tci) >= VLAN_N_VID)
1279 static int mlx4_en_ethtool_add_mac_rule(struct ethtool_rxnfc *cmd,
1280 struct list_head *rule_list_h,
1281 struct mlx4_spec_list *spec_l2,
1285 __be64 mac_msk = cpu_to_be64(MLX4_MAC_MASK << 16);
1287 spec_l2->id = MLX4_NET_TRANS_RULE_ID_ETH;
1288 memcpy(spec_l2->eth.dst_mac_msk, &mac_msk, ETH_ALEN);
1289 memcpy(spec_l2->eth.dst_mac, mac, ETH_ALEN);
1291 if ((cmd->fs.flow_type & FLOW_EXT) &&
1292 (cmd->fs.m_ext.vlan_tci & cpu_to_be16(VLAN_VID_MASK))) {
1293 spec_l2->eth.vlan_id = cmd->fs.h_ext.vlan_tci;
1294 spec_l2->eth.vlan_id_msk = cpu_to_be16(VLAN_VID_MASK);
1297 list_add_tail(&spec_l2->list, rule_list_h);
1302 static int mlx4_en_ethtool_add_mac_rule_by_ipv4(struct mlx4_en_priv *priv,
1303 struct ethtool_rxnfc *cmd,
1304 struct list_head *rule_list_h,
1305 struct mlx4_spec_list *spec_l2,
1309 unsigned char mac[ETH_ALEN];
1311 if (!ipv4_is_multicast(ipv4_dst)) {
1312 if (cmd->fs.flow_type & FLOW_MAC_EXT)
1313 memcpy(&mac, cmd->fs.h_ext.h_dest, ETH_ALEN);
1315 memcpy(&mac, priv->dev->dev_addr, ETH_ALEN);
1317 ip_eth_mc_map(ipv4_dst, mac);
1320 return mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2, &mac[0]);
1326 static int add_ip_rule(struct mlx4_en_priv *priv,
1327 struct ethtool_rxnfc *cmd,
1328 struct list_head *list_h)
1331 struct mlx4_spec_list *spec_l2 = NULL;
1332 struct mlx4_spec_list *spec_l3 = NULL;
1333 struct ethtool_usrip4_spec *l3_mask = &cmd->fs.m_u.usr_ip4_spec;
1335 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1336 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1337 if (!spec_l2 || !spec_l3) {
1342 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h, spec_l2,
1344 usr_ip4_spec.ip4dst);
1347 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1348 spec_l3->ipv4.src_ip = cmd->fs.h_u.usr_ip4_spec.ip4src;
1349 if (l3_mask->ip4src)
1350 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1351 spec_l3->ipv4.dst_ip = cmd->fs.h_u.usr_ip4_spec.ip4dst;
1352 if (l3_mask->ip4dst)
1353 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1354 list_add_tail(&spec_l3->list, list_h);
1364 static int add_tcp_udp_rule(struct mlx4_en_priv *priv,
1365 struct ethtool_rxnfc *cmd,
1366 struct list_head *list_h, int proto)
1369 struct mlx4_spec_list *spec_l2 = NULL;
1370 struct mlx4_spec_list *spec_l3 = NULL;
1371 struct mlx4_spec_list *spec_l4 = NULL;
1372 struct ethtool_tcpip4_spec *l4_mask = &cmd->fs.m_u.tcp_ip4_spec;
1374 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1375 spec_l3 = kzalloc(sizeof(*spec_l3), GFP_KERNEL);
1376 spec_l4 = kzalloc(sizeof(*spec_l4), GFP_KERNEL);
1377 if (!spec_l2 || !spec_l3 || !spec_l4) {
1382 spec_l3->id = MLX4_NET_TRANS_RULE_ID_IPV4;
1384 if (proto == TCP_V4_FLOW) {
1385 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1388 tcp_ip4_spec.ip4dst);
1391 spec_l4->id = MLX4_NET_TRANS_RULE_ID_TCP;
1392 spec_l3->ipv4.src_ip = cmd->fs.h_u.tcp_ip4_spec.ip4src;
1393 spec_l3->ipv4.dst_ip = cmd->fs.h_u.tcp_ip4_spec.ip4dst;
1394 spec_l4->tcp_udp.src_port = cmd->fs.h_u.tcp_ip4_spec.psrc;
1395 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.tcp_ip4_spec.pdst;
1397 err = mlx4_en_ethtool_add_mac_rule_by_ipv4(priv, cmd, list_h,
1400 udp_ip4_spec.ip4dst);
1403 spec_l4->id = MLX4_NET_TRANS_RULE_ID_UDP;
1404 spec_l3->ipv4.src_ip = cmd->fs.h_u.udp_ip4_spec.ip4src;
1405 spec_l3->ipv4.dst_ip = cmd->fs.h_u.udp_ip4_spec.ip4dst;
1406 spec_l4->tcp_udp.src_port = cmd->fs.h_u.udp_ip4_spec.psrc;
1407 spec_l4->tcp_udp.dst_port = cmd->fs.h_u.udp_ip4_spec.pdst;
1410 if (l4_mask->ip4src)
1411 spec_l3->ipv4.src_ip_msk = EN_ETHTOOL_WORD_MASK;
1412 if (l4_mask->ip4dst)
1413 spec_l3->ipv4.dst_ip_msk = EN_ETHTOOL_WORD_MASK;
1416 spec_l4->tcp_udp.src_port_msk = EN_ETHTOOL_SHORT_MASK;
1418 spec_l4->tcp_udp.dst_port_msk = EN_ETHTOOL_SHORT_MASK;
1420 list_add_tail(&spec_l3->list, list_h);
1421 list_add_tail(&spec_l4->list, list_h);
1432 static int mlx4_en_ethtool_to_net_trans_rule(struct net_device *dev,
1433 struct ethtool_rxnfc *cmd,
1434 struct list_head *rule_list_h)
1437 struct ethhdr *eth_spec;
1438 struct mlx4_spec_list *spec_l2;
1439 struct mlx4_en_priv *priv = netdev_priv(dev);
1441 err = mlx4_en_validate_flow(dev, cmd);
1445 switch (cmd->fs.flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
1447 spec_l2 = kzalloc(sizeof(*spec_l2), GFP_KERNEL);
1451 eth_spec = &cmd->fs.h_u.ether_spec;
1452 mlx4_en_ethtool_add_mac_rule(cmd, rule_list_h, spec_l2,
1453 ð_spec->h_dest[0]);
1454 spec_l2->eth.ether_type = eth_spec->h_proto;
1455 if (eth_spec->h_proto)
1456 spec_l2->eth.ether_type_enable = 1;
1459 err = add_ip_rule(priv, cmd, rule_list_h);
1462 err = add_tcp_udp_rule(priv, cmd, rule_list_h, TCP_V4_FLOW);
1465 err = add_tcp_udp_rule(priv, cmd, rule_list_h, UDP_V4_FLOW);
1472 static int mlx4_en_flow_replace(struct net_device *dev,
1473 struct ethtool_rxnfc *cmd)
1476 struct mlx4_en_priv *priv = netdev_priv(dev);
1477 struct ethtool_flow_id *loc_rule;
1478 struct mlx4_spec_list *spec, *tmp_spec;
1482 struct mlx4_net_trans_rule rule = {
1483 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
1485 .allow_loopback = 1,
1486 .promisc_mode = MLX4_FS_REGULAR,
1489 rule.port = priv->port;
1490 rule.priority = MLX4_DOMAIN_ETHTOOL | cmd->fs.location;
1491 INIT_LIST_HEAD(&rule.list);
1493 /* Allow direct QP attaches if the EN_ETHTOOL_QP_ATTACH flag is set */
1494 if (cmd->fs.ring_cookie == RX_CLS_FLOW_DISC)
1495 qpn = priv->drop_qp.qpn;
1496 else if (cmd->fs.ring_cookie & EN_ETHTOOL_QP_ATTACH) {
1497 qpn = cmd->fs.ring_cookie & (EN_ETHTOOL_QP_ATTACH - 1);
1499 if (cmd->fs.ring_cookie >= priv->rx_ring_num) {
1500 en_warn(priv, "rxnfc: RX ring (%llu) doesn't exist\n",
1501 cmd->fs.ring_cookie);
1504 qpn = priv->rss_map.qps[cmd->fs.ring_cookie].qpn;
1506 en_warn(priv, "rxnfc: RX ring (%llu) is inactive\n",
1507 cmd->fs.ring_cookie);
1512 err = mlx4_en_ethtool_to_net_trans_rule(dev, cmd, &rule.list);
1516 loc_rule = &priv->ethtool_rules[cmd->fs.location];
1518 err = mlx4_flow_detach(priv->mdev->dev, loc_rule->id);
1520 en_err(priv, "Fail to detach network rule at location %d. registration id = %llx\n",
1521 cmd->fs.location, loc_rule->id);
1525 memset(&loc_rule->flow_spec, 0,
1526 sizeof(struct ethtool_rx_flow_spec));
1527 list_del(&loc_rule->list);
1529 err = mlx4_flow_attach(priv->mdev->dev, &rule, ®_id);
1531 en_err(priv, "Fail to attach network rule at location %d\n",
1535 loc_rule->id = reg_id;
1536 memcpy(&loc_rule->flow_spec, &cmd->fs,
1537 sizeof(struct ethtool_rx_flow_spec));
1538 list_add_tail(&loc_rule->list, &priv->ethtool_list);
1541 list_for_each_entry_safe(spec, tmp_spec, &rule.list, list) {
1542 list_del(&spec->list);
1548 static int mlx4_en_flow_detach(struct net_device *dev,
1549 struct ethtool_rxnfc *cmd)
1552 struct ethtool_flow_id *rule;
1553 struct mlx4_en_priv *priv = netdev_priv(dev);
1555 if (cmd->fs.location >= MAX_NUM_OF_FS_RULES)
1558 rule = &priv->ethtool_rules[cmd->fs.location];
1564 err = mlx4_flow_detach(priv->mdev->dev, rule->id);
1566 en_err(priv, "Fail to detach network rule at location %d. registration id = 0x%llx\n",
1567 cmd->fs.location, rule->id);
1571 memset(&rule->flow_spec, 0, sizeof(struct ethtool_rx_flow_spec));
1572 list_del(&rule->list);
1578 static int mlx4_en_get_flow(struct net_device *dev, struct ethtool_rxnfc *cmd,
1582 struct ethtool_flow_id *rule;
1583 struct mlx4_en_priv *priv = netdev_priv(dev);
1585 if (loc < 0 || loc >= MAX_NUM_OF_FS_RULES)
1588 rule = &priv->ethtool_rules[loc];
1590 memcpy(&cmd->fs, &rule->flow_spec,
1591 sizeof(struct ethtool_rx_flow_spec));
1598 static int mlx4_en_get_num_flows(struct mlx4_en_priv *priv)
1602 for (i = 0; i < MAX_NUM_OF_FS_RULES; i++) {
1603 if (priv->ethtool_rules[i].id)
1610 static int mlx4_en_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
1613 struct mlx4_en_priv *priv = netdev_priv(dev);
1614 struct mlx4_en_dev *mdev = priv->mdev;
1616 int i = 0, priority = 0;
1618 if ((cmd->cmd == ETHTOOL_GRXCLSRLCNT ||
1619 cmd->cmd == ETHTOOL_GRXCLSRULE ||
1620 cmd->cmd == ETHTOOL_GRXCLSRLALL) &&
1621 (mdev->dev->caps.steering_mode !=
1622 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up))
1626 case ETHTOOL_GRXRINGS:
1627 cmd->data = priv->rx_ring_num;
1629 case ETHTOOL_GRXCLSRLCNT:
1630 cmd->rule_cnt = mlx4_en_get_num_flows(priv);
1632 case ETHTOOL_GRXCLSRULE:
1633 err = mlx4_en_get_flow(dev, cmd, cmd->fs.location);
1635 case ETHTOOL_GRXCLSRLALL:
1636 while ((!err || err == -ENOENT) && priority < cmd->rule_cnt) {
1637 err = mlx4_en_get_flow(dev, cmd, i);
1639 rule_locs[priority++] = i;
1652 static int mlx4_en_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
1655 struct mlx4_en_priv *priv = netdev_priv(dev);
1656 struct mlx4_en_dev *mdev = priv->mdev;
1658 if (mdev->dev->caps.steering_mode !=
1659 MLX4_STEERING_MODE_DEVICE_MANAGED || !priv->port_up)
1663 case ETHTOOL_SRXCLSRLINS:
1664 err = mlx4_en_flow_replace(dev, cmd);
1666 case ETHTOOL_SRXCLSRLDEL:
1667 err = mlx4_en_flow_detach(dev, cmd);
1670 en_warn(priv, "Unsupported ethtool command. (%d)\n", cmd->cmd);
1677 static void mlx4_en_get_channels(struct net_device *dev,
1678 struct ethtool_channels *channel)
1680 struct mlx4_en_priv *priv = netdev_priv(dev);
1682 memset(channel, 0, sizeof(*channel));
1684 channel->max_rx = MAX_RX_RINGS;
1685 channel->max_tx = MLX4_EN_MAX_TX_RING_P_UP;
1687 channel->rx_count = priv->rx_ring_num;
1688 channel->tx_count = priv->tx_ring_num / MLX4_EN_NUM_UP;
1691 static int mlx4_en_set_channels(struct net_device *dev,
1692 struct ethtool_channels *channel)
1694 struct mlx4_en_priv *priv = netdev_priv(dev);
1695 struct mlx4_en_dev *mdev = priv->mdev;
1699 if (channel->other_count || channel->combined_count ||
1700 channel->tx_count > MLX4_EN_MAX_TX_RING_P_UP ||
1701 channel->rx_count > MAX_RX_RINGS ||
1702 !channel->tx_count || !channel->rx_count)
1705 mutex_lock(&mdev->state_lock);
1706 if (priv->port_up) {
1708 mlx4_en_stop_port(dev, 1);
1711 mlx4_en_free_resources(priv);
1713 priv->num_tx_rings_p_up = channel->tx_count;
1714 priv->tx_ring_num = channel->tx_count * MLX4_EN_NUM_UP;
1715 priv->rx_ring_num = channel->rx_count;
1717 err = mlx4_en_alloc_resources(priv);
1719 en_err(priv, "Failed reallocating port resources\n");
1723 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
1724 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
1727 mlx4_en_setup_tc(dev, MLX4_EN_NUM_UP);
1729 en_warn(priv, "Using %d TX rings\n", priv->tx_ring_num);
1730 en_warn(priv, "Using %d RX rings\n", priv->rx_ring_num);
1733 err = mlx4_en_start_port(dev);
1735 en_err(priv, "Failed starting port\n");
1738 err = mlx4_en_moderation_update(priv);
1741 mutex_unlock(&mdev->state_lock);
1745 static int mlx4_en_get_ts_info(struct net_device *dev,
1746 struct ethtool_ts_info *info)
1748 struct mlx4_en_priv *priv = netdev_priv(dev);
1749 struct mlx4_en_dev *mdev = priv->mdev;
1752 ret = ethtool_op_get_ts_info(dev, info);
1756 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
1757 info->so_timestamping |=
1758 SOF_TIMESTAMPING_TX_HARDWARE |
1759 SOF_TIMESTAMPING_RX_HARDWARE |
1760 SOF_TIMESTAMPING_RAW_HARDWARE;
1763 (1 << HWTSTAMP_TX_OFF) |
1764 (1 << HWTSTAMP_TX_ON);
1767 (1 << HWTSTAMP_FILTER_NONE) |
1768 (1 << HWTSTAMP_FILTER_ALL);
1770 if (mdev->ptp_clock)
1771 info->phc_index = ptp_clock_index(mdev->ptp_clock);
1777 static int mlx4_en_set_priv_flags(struct net_device *dev, u32 flags)
1779 struct mlx4_en_priv *priv = netdev_priv(dev);
1780 bool bf_enabled_new = !!(flags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1781 bool bf_enabled_old = !!(priv->pflags & MLX4_EN_PRIV_FLAGS_BLUEFLAME);
1784 if (bf_enabled_new == bf_enabled_old)
1785 return 0; /* Nothing to do */
1787 if (bf_enabled_new) {
1788 bool bf_supported = true;
1790 for (i = 0; i < priv->tx_ring_num; i++)
1791 bf_supported &= priv->tx_ring[i]->bf_alloced;
1793 if (!bf_supported) {
1794 en_err(priv, "BlueFlame is not supported\n");
1798 priv->pflags |= MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1800 priv->pflags &= ~MLX4_EN_PRIV_FLAGS_BLUEFLAME;
1803 for (i = 0; i < priv->tx_ring_num; i++)
1804 priv->tx_ring[i]->bf_enabled = bf_enabled_new;
1806 en_info(priv, "BlueFlame %s\n",
1807 bf_enabled_new ? "Enabled" : "Disabled");
1812 static u32 mlx4_en_get_priv_flags(struct net_device *dev)
1814 struct mlx4_en_priv *priv = netdev_priv(dev);
1816 return priv->pflags;
1819 static int mlx4_en_get_tunable(struct net_device *dev,
1820 const struct ethtool_tunable *tuna,
1823 const struct mlx4_en_priv *priv = netdev_priv(dev);
1827 case ETHTOOL_TX_COPYBREAK:
1828 *(u32 *)data = priv->prof->inline_thold;
1838 static int mlx4_en_set_tunable(struct net_device *dev,
1839 const struct ethtool_tunable *tuna,
1842 struct mlx4_en_priv *priv = netdev_priv(dev);
1846 case ETHTOOL_TX_COPYBREAK:
1848 if (val < MIN_PKT_LEN || val > MAX_INLINE)
1851 priv->prof->inline_thold = val;
1861 static int mlx4_en_get_module_info(struct net_device *dev,
1862 struct ethtool_modinfo *modinfo)
1864 struct mlx4_en_priv *priv = netdev_priv(dev);
1865 struct mlx4_en_dev *mdev = priv->mdev;
1869 /* Read first 2 bytes to get Module & REV ID */
1870 ret = mlx4_get_module_info(mdev->dev, priv->port,
1871 0/*offset*/, 2/*size*/, data);
1875 switch (data[0] /* identifier */) {
1876 case MLX4_MODULE_ID_QSFP:
1877 modinfo->type = ETH_MODULE_SFF_8436;
1878 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1880 case MLX4_MODULE_ID_QSFP_PLUS:
1881 if (data[1] >= 0x3) { /* revision id */
1882 modinfo->type = ETH_MODULE_SFF_8636;
1883 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1885 modinfo->type = ETH_MODULE_SFF_8436;
1886 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
1889 case MLX4_MODULE_ID_QSFP28:
1890 modinfo->type = ETH_MODULE_SFF_8636;
1891 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
1893 case MLX4_MODULE_ID_SFP:
1894 modinfo->type = ETH_MODULE_SFF_8472;
1895 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1904 static int mlx4_en_get_module_eeprom(struct net_device *dev,
1905 struct ethtool_eeprom *ee,
1908 struct mlx4_en_priv *priv = netdev_priv(dev);
1909 struct mlx4_en_dev *mdev = priv->mdev;
1910 int offset = ee->offset;
1916 memset(data, 0, ee->len);
1918 while (i < ee->len) {
1920 "mlx4_get_module_info i(%d) offset(%d) len(%d)\n",
1921 i, offset, ee->len - i);
1923 ret = mlx4_get_module_info(mdev->dev, priv->port,
1924 offset, ee->len - i, data + i);
1926 if (!ret) /* Done reading */
1931 "mlx4_get_module_info i(%d) offset(%d) bytes_to_read(%d) - FAILED (0x%x)\n",
1932 i, offset, ee->len - i, ret);
1942 static int mlx4_en_set_phys_id(struct net_device *dev,
1943 enum ethtool_phys_id_state state)
1946 u16 beacon_duration;
1947 struct mlx4_en_priv *priv = netdev_priv(dev);
1948 struct mlx4_en_dev *mdev = priv->mdev;
1950 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_BEACON))
1954 case ETHTOOL_ID_ACTIVE:
1955 beacon_duration = PORT_BEACON_MAX_LIMIT;
1957 case ETHTOOL_ID_INACTIVE:
1958 beacon_duration = 0;
1964 err = mlx4_SET_PORT_BEACON(mdev->dev, priv->port, beacon_duration);
1968 const struct ethtool_ops mlx4_en_ethtool_ops = {
1969 .get_drvinfo = mlx4_en_get_drvinfo,
1970 .get_settings = mlx4_en_get_settings,
1971 .set_settings = mlx4_en_set_settings,
1972 .get_link = ethtool_op_get_link,
1973 .get_strings = mlx4_en_get_strings,
1974 .get_sset_count = mlx4_en_get_sset_count,
1975 .get_ethtool_stats = mlx4_en_get_ethtool_stats,
1976 .self_test = mlx4_en_self_test,
1977 .set_phys_id = mlx4_en_set_phys_id,
1978 .get_wol = mlx4_en_get_wol,
1979 .set_wol = mlx4_en_set_wol,
1980 .get_msglevel = mlx4_en_get_msglevel,
1981 .set_msglevel = mlx4_en_set_msglevel,
1982 .get_coalesce = mlx4_en_get_coalesce,
1983 .set_coalesce = mlx4_en_set_coalesce,
1984 .get_pauseparam = mlx4_en_get_pauseparam,
1985 .set_pauseparam = mlx4_en_set_pauseparam,
1986 .get_ringparam = mlx4_en_get_ringparam,
1987 .set_ringparam = mlx4_en_set_ringparam,
1988 .get_rxnfc = mlx4_en_get_rxnfc,
1989 .set_rxnfc = mlx4_en_set_rxnfc,
1990 .get_rxfh_indir_size = mlx4_en_get_rxfh_indir_size,
1991 .get_rxfh_key_size = mlx4_en_get_rxfh_key_size,
1992 .get_rxfh = mlx4_en_get_rxfh,
1993 .set_rxfh = mlx4_en_set_rxfh,
1994 .get_channels = mlx4_en_get_channels,
1995 .set_channels = mlx4_en_set_channels,
1996 .get_ts_info = mlx4_en_get_ts_info,
1997 .set_priv_flags = mlx4_en_set_priv_flags,
1998 .get_priv_flags = mlx4_en_get_priv_flags,
1999 .get_tunable = mlx4_en_get_tunable,
2000 .set_tunable = mlx4_en_set_tunable,
2001 .get_module_info = mlx4_en_get_module_info,
2002 .get_module_eeprom = mlx4_en_get_module_eeprom