2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/semaphore.h>
44 #include <rdma/ib_smi.h>
51 #define CMD_POLL_TOKEN 0xffff
52 #define INBOX_MASK 0xffffffffffffff00ULL
54 #define CMD_CHAN_VER 1
55 #define CMD_CHAN_IF_REV 1
58 /* command completed successfully: */
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
105 HCR_OPMOD_SHIFT = 12,
112 GO_BIT_TIMEOUT_MSECS = 10000
115 enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
123 struct mlx4_cmd_context {
124 struct completion done;
132 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
135 static int mlx4_status_to_errno(u8 status)
137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
148 [CMD_STAT_ICM_ERROR] = -ENFILE,
149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
162 return trans_table[status];
165 static u8 mlx4_errno_to_status(int errno)
169 return CMD_STAT_BAD_OP;
171 return CMD_STAT_BAD_PARAM;
173 return CMD_STAT_BAD_SYS_STATE;
175 return CMD_STAT_RESOURCE_BUSY;
177 return CMD_STAT_EXCEED_LIM;
179 return CMD_STAT_ICM_ERROR;
181 return CMD_STAT_INTERNAL_ERR;
185 static int comm_pending(struct mlx4_dev *dev)
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
193 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
195 struct mlx4_priv *priv = mlx4_priv(dev);
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
205 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
208 struct mlx4_priv *priv = mlx4_priv(dev);
211 int ret_from_pending = 0;
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
215 mlx4_warn(dev, "Communication channel is not idle."
216 "my toggle is %d (cmd:0x%x)\n",
217 priv->cmd.comm_toggle, cmd);
222 down(&priv->cmd.poll_sem);
223 mlx4_comm_cmd_post(dev, cmd, param);
225 end = msecs_to_jiffies(timeout) + jiffies;
226 while (comm_pending(dev) && time_before(jiffies, end))
228 ret_from_pending = comm_pending(dev);
229 if (ret_from_pending) {
230 /* check if the slave is trying to boot in the middle of
231 * FLR process. The only non-zero result in the RESET command
232 * is MLX4_DELAY_RESET_SLAVE*/
233 if ((MLX4_COMM_CMD_RESET == cmd)) {
234 err = MLX4_DELAY_RESET_SLAVE;
236 mlx4_warn(dev, "Communication channel timed out\n");
241 up(&priv->cmd.poll_sem);
245 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
246 u16 param, unsigned long timeout)
248 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
249 struct mlx4_cmd_context *context;
253 down(&cmd->event_sem);
255 spin_lock(&cmd->context_lock);
256 BUG_ON(cmd->free_head < 0);
257 context = &cmd->context[cmd->free_head];
258 context->token += cmd->token_mask + 1;
259 cmd->free_head = context->next;
260 spin_unlock(&cmd->context_lock);
262 init_completion(&context->done);
264 mlx4_comm_cmd_post(dev, op, param);
266 if (!wait_for_completion_timeout(&context->done,
267 msecs_to_jiffies(timeout))) {
268 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
274 err = context->result;
275 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
276 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
277 op, context->fw_status);
282 /* wait for comm channel ready
283 * this is necessary for prevention the race
284 * when switching between event to polling mode
286 end = msecs_to_jiffies(timeout) + jiffies;
287 while (comm_pending(dev) && time_before(jiffies, end))
290 spin_lock(&cmd->context_lock);
291 context->next = cmd->free_head;
292 cmd->free_head = context - cmd->context;
293 spin_unlock(&cmd->context_lock);
299 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
300 unsigned long timeout)
302 if (mlx4_priv(dev)->cmd.use_events)
303 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
304 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
307 static int cmd_pending(struct mlx4_dev *dev)
311 if (pci_channel_offline(dev->pdev))
314 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
316 return (status & swab32(1 << HCR_GO_BIT)) ||
317 (mlx4_priv(dev)->cmd.toggle ==
318 !!(status & swab32(1 << HCR_T_BIT)));
321 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
322 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
325 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
326 u32 __iomem *hcr = cmd->hcr;
330 mutex_lock(&cmd->hcr_mutex);
332 if (pci_channel_offline(dev->pdev)) {
334 * Device is going through error recovery
335 * and cannot accept commands.
343 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
345 while (cmd_pending(dev)) {
346 if (pci_channel_offline(dev->pdev)) {
348 * Device is going through error recovery
349 * and cannot accept commands.
355 if (time_after_eq(jiffies, end)) {
356 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
363 * We use writel (instead of something like memcpy_toio)
364 * because writes of less than 32 bits to the HCR don't work
365 * (and some architectures such as ia64 implement memcpy_toio
366 * in terms of writeb).
368 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
369 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
370 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
371 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
372 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
373 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
375 /* __raw_writel may not order writes. */
378 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
379 (cmd->toggle << HCR_T_BIT) |
380 (event ? (1 << HCR_E_BIT) : 0) |
381 (op_modifier << HCR_OPMOD_SHIFT) |
385 * Make sure that our HCR writes don't get mixed in with
386 * writes from another CPU starting a FW command.
390 cmd->toggle = cmd->toggle ^ 1;
395 mutex_unlock(&cmd->hcr_mutex);
399 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
400 int out_is_imm, u32 in_modifier, u8 op_modifier,
401 u16 op, unsigned long timeout)
403 struct mlx4_priv *priv = mlx4_priv(dev);
404 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
407 mutex_lock(&priv->cmd.slave_cmd_mutex);
409 vhcr->in_param = cpu_to_be64(in_param);
410 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
411 vhcr->in_modifier = cpu_to_be32(in_modifier);
412 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
413 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
415 vhcr->flags = !!(priv->cmd.use_events) << 6;
417 if (mlx4_is_master(dev)) {
418 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
423 be64_to_cpu(vhcr->out_param);
425 mlx4_err(dev, "response expected while"
426 "output mailbox is NULL for "
427 "command 0x%x\n", op);
428 vhcr->status = CMD_STAT_BAD_PARAM;
431 ret = mlx4_status_to_errno(vhcr->status);
434 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
435 MLX4_COMM_TIME + timeout);
440 be64_to_cpu(vhcr->out_param);
442 mlx4_err(dev, "response expected while"
443 "output mailbox is NULL for "
444 "command 0x%x\n", op);
445 vhcr->status = CMD_STAT_BAD_PARAM;
448 ret = mlx4_status_to_errno(vhcr->status);
450 mlx4_err(dev, "failed execution of VHCR_POST command"
451 "opcode 0x%x\n", op);
454 mutex_unlock(&priv->cmd.slave_cmd_mutex);
458 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
459 int out_is_imm, u32 in_modifier, u8 op_modifier,
460 u16 op, unsigned long timeout)
462 struct mlx4_priv *priv = mlx4_priv(dev);
463 void __iomem *hcr = priv->cmd.hcr;
468 down(&priv->cmd.poll_sem);
470 if (pci_channel_offline(dev->pdev)) {
472 * Device is going through error recovery
473 * and cannot accept commands.
479 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
480 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
484 end = msecs_to_jiffies(timeout) + jiffies;
485 while (cmd_pending(dev) && time_before(jiffies, end)) {
486 if (pci_channel_offline(dev->pdev)) {
488 * Device is going through error recovery
489 * and cannot accept commands.
498 if (cmd_pending(dev)) {
499 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
507 (u64) be32_to_cpu((__force __be32)
508 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
509 (u64) be32_to_cpu((__force __be32)
510 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
511 stat = be32_to_cpu((__force __be32)
512 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
513 err = mlx4_status_to_errno(stat);
515 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
519 up(&priv->cmd.poll_sem);
523 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
525 struct mlx4_priv *priv = mlx4_priv(dev);
526 struct mlx4_cmd_context *context =
527 &priv->cmd.context[token & priv->cmd.token_mask];
529 /* previously timed out command completing at long last */
530 if (token != context->token)
533 context->fw_status = status;
534 context->result = mlx4_status_to_errno(status);
535 context->out_param = out_param;
537 complete(&context->done);
540 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
541 int out_is_imm, u32 in_modifier, u8 op_modifier,
542 u16 op, unsigned long timeout)
544 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
545 struct mlx4_cmd_context *context;
548 down(&cmd->event_sem);
550 spin_lock(&cmd->context_lock);
551 BUG_ON(cmd->free_head < 0);
552 context = &cmd->context[cmd->free_head];
553 context->token += cmd->token_mask + 1;
554 cmd->free_head = context->next;
555 spin_unlock(&cmd->context_lock);
557 init_completion(&context->done);
559 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
560 in_modifier, op_modifier, op, context->token, 1);
562 if (!wait_for_completion_timeout(&context->done,
563 msecs_to_jiffies(timeout))) {
564 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
570 err = context->result;
572 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
573 op, context->fw_status);
578 *out_param = context->out_param;
581 spin_lock(&cmd->context_lock);
582 context->next = cmd->free_head;
583 cmd->free_head = context - cmd->context;
584 spin_unlock(&cmd->context_lock);
590 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
591 int out_is_imm, u32 in_modifier, u8 op_modifier,
592 u16 op, unsigned long timeout, int native)
594 if (pci_channel_offline(dev->pdev))
597 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
598 if (mlx4_priv(dev)->cmd.use_events)
599 return mlx4_cmd_wait(dev, in_param, out_param,
600 out_is_imm, in_modifier,
601 op_modifier, op, timeout);
603 return mlx4_cmd_poll(dev, in_param, out_param,
604 out_is_imm, in_modifier,
605 op_modifier, op, timeout);
607 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
608 in_modifier, op_modifier, op, timeout);
610 EXPORT_SYMBOL_GPL(__mlx4_cmd);
613 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
615 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
616 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
619 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
620 int slave, u64 slave_addr,
621 int size, int is_read)
626 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
627 (slave & ~0x7f) | (size & 0xff)) {
628 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
629 "master_addr:0x%llx slave_id:%d size:%d\n",
630 slave_addr, master_addr, slave, size);
635 in_param = (u64) slave | slave_addr;
636 out_param = (u64) dev->caps.function | master_addr;
638 in_param = (u64) dev->caps.function | master_addr;
639 out_param = (u64) slave | slave_addr;
642 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
644 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
647 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
648 struct mlx4_cmd_mailbox *inbox,
649 struct mlx4_cmd_mailbox *outbox)
651 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
652 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
659 in_mad->attr_mod = cpu_to_be32(index / 32);
661 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
662 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
667 for (i = 0; i < 32; ++i)
668 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
673 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
674 struct mlx4_cmd_mailbox *inbox,
675 struct mlx4_cmd_mailbox *outbox)
680 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
681 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
688 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
689 #define PORT_STATE_OFFSET 32
691 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
693 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
694 return IB_PORT_ACTIVE;
699 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
700 struct mlx4_vhcr *vhcr,
701 struct mlx4_cmd_mailbox *inbox,
702 struct mlx4_cmd_mailbox *outbox,
703 struct mlx4_cmd_info *cmd)
705 struct ib_smp *smp = inbox->buf;
713 struct mlx4_priv *priv = mlx4_priv(dev);
714 struct ib_smp *outsmp = outbox->buf;
715 __be16 *outtab = (__be16 *)(outsmp->data);
716 __be32 slave_cap_mask;
717 __be64 slave_node_guid;
719 port = vhcr->in_modifier;
721 /* network-view bit is for driver use only, and should not be passed to FW */
722 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
723 network_view = !!(vhcr->op_modifier & 0x8);
725 if (smp->base_version == 1 &&
726 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
727 smp->class_version == 1) {
728 /* host view is paravirtualized */
729 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
730 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
731 index = be32_to_cpu(smp->attr_mod);
732 if (port < 1 || port > dev->caps.num_ports)
734 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
737 /* need to get the full pkey table because the paravirtualized
738 * pkeys may be scattered among several pkey blocks.
740 err = get_full_pkey_table(dev, port, table, inbox, outbox);
742 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
743 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
744 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
750 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
751 /*get the slave specific caps:*/
753 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
754 vhcr->in_modifier, opcode_modifier,
755 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
756 /* modify the response for slaves */
757 if (!err && slave != mlx4_master_func_num(dev)) {
758 u8 *state = outsmp->data + PORT_STATE_OFFSET;
760 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
761 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
762 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
766 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
767 /* compute slave's gid block */
768 smp->attr_mod = cpu_to_be32(slave / 8);
770 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
771 vhcr->in_modifier, opcode_modifier,
772 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
774 /* if needed, move slave gid to index 0 */
777 outsmp->data + (slave % 8) * 8, 8);
778 /* delete all other gids */
779 memset(outsmp->data + 8, 0, 56);
783 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
784 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
785 vhcr->in_modifier, opcode_modifier,
786 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
788 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
789 memcpy(outsmp->data + 12, &slave_node_guid, 8);
796 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
797 * These are the MADs used by ib verbs (such as ib_query_gids).
799 if (slave != mlx4_master_func_num(dev) &&
800 !mlx4_vf_smi_enabled(dev, slave, port)) {
801 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
802 smp->method == IB_MGMT_METHOD_GET) || network_view) {
803 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
804 slave, smp->method, smp->mgmt_class,
805 network_view ? "Network" : "Host",
806 be16_to_cpu(smp->attr_id));
811 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
812 vhcr->in_modifier, opcode_modifier,
813 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
816 static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
817 struct mlx4_vhcr *vhcr,
818 struct mlx4_cmd_mailbox *inbox,
819 struct mlx4_cmd_mailbox *outbox,
820 struct mlx4_cmd_info *cmd)
825 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
826 struct mlx4_vhcr *vhcr,
827 struct mlx4_cmd_mailbox *inbox,
828 struct mlx4_cmd_mailbox *outbox,
829 struct mlx4_cmd_info *cmd)
835 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
836 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
837 if (cmd->encode_slave_id) {
838 in_param &= 0xffffffffffffff00ll;
842 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
843 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
844 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
847 vhcr->out_param = out_param;
852 static struct mlx4_cmd_info cmd_info[] = {
854 .opcode = MLX4_CMD_QUERY_FW,
858 .encode_slave_id = false,
860 .wrapper = mlx4_QUERY_FW_wrapper
863 .opcode = MLX4_CMD_QUERY_HCA,
867 .encode_slave_id = false,
872 .opcode = MLX4_CMD_QUERY_DEV_CAP,
876 .encode_slave_id = false,
878 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
881 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
885 .encode_slave_id = false,
887 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
890 .opcode = MLX4_CMD_QUERY_ADAPTER,
894 .encode_slave_id = false,
899 .opcode = MLX4_CMD_INIT_PORT,
903 .encode_slave_id = false,
905 .wrapper = mlx4_INIT_PORT_wrapper
908 .opcode = MLX4_CMD_CLOSE_PORT,
912 .encode_slave_id = false,
914 .wrapper = mlx4_CLOSE_PORT_wrapper
917 .opcode = MLX4_CMD_QUERY_PORT,
921 .encode_slave_id = false,
923 .wrapper = mlx4_QUERY_PORT_wrapper
926 .opcode = MLX4_CMD_SET_PORT,
930 .encode_slave_id = false,
932 .wrapper = mlx4_SET_PORT_wrapper
935 .opcode = MLX4_CMD_MAP_EQ,
939 .encode_slave_id = false,
941 .wrapper = mlx4_MAP_EQ_wrapper
944 .opcode = MLX4_CMD_SW2HW_EQ,
948 .encode_slave_id = true,
950 .wrapper = mlx4_SW2HW_EQ_wrapper
953 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
957 .encode_slave_id = false,
962 .opcode = MLX4_CMD_NOP,
966 .encode_slave_id = false,
971 .opcode = MLX4_CMD_CONFIG_DEV,
975 .encode_slave_id = false,
977 .wrapper = mlx4_CMD_EPERM_wrapper
980 .opcode = MLX4_CMD_ALLOC_RES,
984 .encode_slave_id = false,
986 .wrapper = mlx4_ALLOC_RES_wrapper
989 .opcode = MLX4_CMD_FREE_RES,
993 .encode_slave_id = false,
995 .wrapper = mlx4_FREE_RES_wrapper
998 .opcode = MLX4_CMD_SW2HW_MPT,
1000 .has_outbox = false,
1001 .out_is_imm = false,
1002 .encode_slave_id = true,
1004 .wrapper = mlx4_SW2HW_MPT_wrapper
1007 .opcode = MLX4_CMD_QUERY_MPT,
1010 .out_is_imm = false,
1011 .encode_slave_id = false,
1013 .wrapper = mlx4_QUERY_MPT_wrapper
1016 .opcode = MLX4_CMD_HW2SW_MPT,
1018 .has_outbox = false,
1019 .out_is_imm = false,
1020 .encode_slave_id = false,
1022 .wrapper = mlx4_HW2SW_MPT_wrapper
1025 .opcode = MLX4_CMD_READ_MTT,
1028 .out_is_imm = false,
1029 .encode_slave_id = false,
1034 .opcode = MLX4_CMD_WRITE_MTT,
1036 .has_outbox = false,
1037 .out_is_imm = false,
1038 .encode_slave_id = false,
1040 .wrapper = mlx4_WRITE_MTT_wrapper
1043 .opcode = MLX4_CMD_SYNC_TPT,
1045 .has_outbox = false,
1046 .out_is_imm = false,
1047 .encode_slave_id = false,
1052 .opcode = MLX4_CMD_HW2SW_EQ,
1055 .out_is_imm = false,
1056 .encode_slave_id = true,
1058 .wrapper = mlx4_HW2SW_EQ_wrapper
1061 .opcode = MLX4_CMD_QUERY_EQ,
1064 .out_is_imm = false,
1065 .encode_slave_id = true,
1067 .wrapper = mlx4_QUERY_EQ_wrapper
1070 .opcode = MLX4_CMD_SW2HW_CQ,
1072 .has_outbox = false,
1073 .out_is_imm = false,
1074 .encode_slave_id = true,
1076 .wrapper = mlx4_SW2HW_CQ_wrapper
1079 .opcode = MLX4_CMD_HW2SW_CQ,
1081 .has_outbox = false,
1082 .out_is_imm = false,
1083 .encode_slave_id = false,
1085 .wrapper = mlx4_HW2SW_CQ_wrapper
1088 .opcode = MLX4_CMD_QUERY_CQ,
1091 .out_is_imm = false,
1092 .encode_slave_id = false,
1094 .wrapper = mlx4_QUERY_CQ_wrapper
1097 .opcode = MLX4_CMD_MODIFY_CQ,
1099 .has_outbox = false,
1101 .encode_slave_id = false,
1103 .wrapper = mlx4_MODIFY_CQ_wrapper
1106 .opcode = MLX4_CMD_SW2HW_SRQ,
1108 .has_outbox = false,
1109 .out_is_imm = false,
1110 .encode_slave_id = true,
1112 .wrapper = mlx4_SW2HW_SRQ_wrapper
1115 .opcode = MLX4_CMD_HW2SW_SRQ,
1117 .has_outbox = false,
1118 .out_is_imm = false,
1119 .encode_slave_id = false,
1121 .wrapper = mlx4_HW2SW_SRQ_wrapper
1124 .opcode = MLX4_CMD_QUERY_SRQ,
1127 .out_is_imm = false,
1128 .encode_slave_id = false,
1130 .wrapper = mlx4_QUERY_SRQ_wrapper
1133 .opcode = MLX4_CMD_ARM_SRQ,
1135 .has_outbox = false,
1136 .out_is_imm = false,
1137 .encode_slave_id = false,
1139 .wrapper = mlx4_ARM_SRQ_wrapper
1142 .opcode = MLX4_CMD_RST2INIT_QP,
1144 .has_outbox = false,
1145 .out_is_imm = false,
1146 .encode_slave_id = true,
1148 .wrapper = mlx4_RST2INIT_QP_wrapper
1151 .opcode = MLX4_CMD_INIT2INIT_QP,
1153 .has_outbox = false,
1154 .out_is_imm = false,
1155 .encode_slave_id = false,
1157 .wrapper = mlx4_INIT2INIT_QP_wrapper
1160 .opcode = MLX4_CMD_INIT2RTR_QP,
1162 .has_outbox = false,
1163 .out_is_imm = false,
1164 .encode_slave_id = false,
1166 .wrapper = mlx4_INIT2RTR_QP_wrapper
1169 .opcode = MLX4_CMD_RTR2RTS_QP,
1171 .has_outbox = false,
1172 .out_is_imm = false,
1173 .encode_slave_id = false,
1175 .wrapper = mlx4_RTR2RTS_QP_wrapper
1178 .opcode = MLX4_CMD_RTS2RTS_QP,
1180 .has_outbox = false,
1181 .out_is_imm = false,
1182 .encode_slave_id = false,
1184 .wrapper = mlx4_RTS2RTS_QP_wrapper
1187 .opcode = MLX4_CMD_SQERR2RTS_QP,
1189 .has_outbox = false,
1190 .out_is_imm = false,
1191 .encode_slave_id = false,
1193 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1196 .opcode = MLX4_CMD_2ERR_QP,
1198 .has_outbox = false,
1199 .out_is_imm = false,
1200 .encode_slave_id = false,
1202 .wrapper = mlx4_GEN_QP_wrapper
1205 .opcode = MLX4_CMD_RTS2SQD_QP,
1207 .has_outbox = false,
1208 .out_is_imm = false,
1209 .encode_slave_id = false,
1211 .wrapper = mlx4_GEN_QP_wrapper
1214 .opcode = MLX4_CMD_SQD2SQD_QP,
1216 .has_outbox = false,
1217 .out_is_imm = false,
1218 .encode_slave_id = false,
1220 .wrapper = mlx4_SQD2SQD_QP_wrapper
1223 .opcode = MLX4_CMD_SQD2RTS_QP,
1225 .has_outbox = false,
1226 .out_is_imm = false,
1227 .encode_slave_id = false,
1229 .wrapper = mlx4_SQD2RTS_QP_wrapper
1232 .opcode = MLX4_CMD_2RST_QP,
1234 .has_outbox = false,
1235 .out_is_imm = false,
1236 .encode_slave_id = false,
1238 .wrapper = mlx4_2RST_QP_wrapper
1241 .opcode = MLX4_CMD_QUERY_QP,
1244 .out_is_imm = false,
1245 .encode_slave_id = false,
1247 .wrapper = mlx4_GEN_QP_wrapper
1250 .opcode = MLX4_CMD_SUSPEND_QP,
1252 .has_outbox = false,
1253 .out_is_imm = false,
1254 .encode_slave_id = false,
1256 .wrapper = mlx4_GEN_QP_wrapper
1259 .opcode = MLX4_CMD_UNSUSPEND_QP,
1261 .has_outbox = false,
1262 .out_is_imm = false,
1263 .encode_slave_id = false,
1265 .wrapper = mlx4_GEN_QP_wrapper
1268 .opcode = MLX4_CMD_UPDATE_QP,
1270 .has_outbox = false,
1271 .out_is_imm = false,
1272 .encode_slave_id = false,
1274 .wrapper = mlx4_UPDATE_QP_wrapper
1277 .opcode = MLX4_CMD_GET_OP_REQ,
1279 .has_outbox = false,
1280 .out_is_imm = false,
1281 .encode_slave_id = false,
1283 .wrapper = mlx4_CMD_EPERM_wrapper,
1286 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1288 .has_outbox = false,
1289 .out_is_imm = false,
1290 .encode_slave_id = false,
1291 .verify = NULL, /* XXX verify: only demux can do this */
1295 .opcode = MLX4_CMD_MAD_IFC,
1298 .out_is_imm = false,
1299 .encode_slave_id = false,
1301 .wrapper = mlx4_MAD_IFC_wrapper
1304 .opcode = MLX4_CMD_QUERY_IF_STAT,
1307 .out_is_imm = false,
1308 .encode_slave_id = false,
1310 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1312 /* Native multicast commands are not available for guests */
1314 .opcode = MLX4_CMD_QP_ATTACH,
1316 .has_outbox = false,
1317 .out_is_imm = false,
1318 .encode_slave_id = false,
1320 .wrapper = mlx4_QP_ATTACH_wrapper
1323 .opcode = MLX4_CMD_PROMISC,
1325 .has_outbox = false,
1326 .out_is_imm = false,
1327 .encode_slave_id = false,
1329 .wrapper = mlx4_PROMISC_wrapper
1331 /* Ethernet specific commands */
1333 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1335 .has_outbox = false,
1336 .out_is_imm = false,
1337 .encode_slave_id = false,
1339 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1342 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1344 .has_outbox = false,
1345 .out_is_imm = false,
1346 .encode_slave_id = false,
1348 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1351 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1354 .out_is_imm = false,
1355 .encode_slave_id = false,
1357 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1360 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1362 .has_outbox = false,
1363 .out_is_imm = false,
1364 .encode_slave_id = false,
1368 /* flow steering commands */
1370 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1372 .has_outbox = false,
1374 .encode_slave_id = false,
1376 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1379 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1381 .has_outbox = false,
1382 .out_is_imm = false,
1383 .encode_slave_id = false,
1385 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1388 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1390 .has_outbox = false,
1391 .out_is_imm = false,
1392 .encode_slave_id = false,
1394 .wrapper = mlx4_CMD_EPERM_wrapper
1398 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1399 struct mlx4_vhcr_cmd *in_vhcr)
1401 struct mlx4_priv *priv = mlx4_priv(dev);
1402 struct mlx4_cmd_info *cmd = NULL;
1403 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1404 struct mlx4_vhcr *vhcr;
1405 struct mlx4_cmd_mailbox *inbox = NULL;
1406 struct mlx4_cmd_mailbox *outbox = NULL;
1413 /* Create sw representation of Virtual HCR */
1414 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1418 /* DMA in the vHCR */
1420 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1421 priv->mfunc.master.slave_state[slave].vhcr_dma,
1422 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1423 MLX4_ACCESS_MEM_ALIGN), 1);
1425 mlx4_err(dev, "%s:Failed reading vhcr"
1426 "ret: 0x%x\n", __func__, ret);
1432 /* Fill SW VHCR fields */
1433 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1434 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1435 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1436 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1437 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1438 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1439 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1441 /* Lookup command */
1442 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1443 if (vhcr->op == cmd_info[i].opcode) {
1449 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1451 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1456 if (cmd->has_inbox) {
1457 vhcr->in_param &= INBOX_MASK;
1458 inbox = mlx4_alloc_cmd_mailbox(dev);
1459 if (IS_ERR(inbox)) {
1460 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1465 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1467 MLX4_MAILBOX_SIZE, 1)) {
1468 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1469 __func__, cmd->opcode);
1470 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1475 /* Apply permission and bound checks if applicable */
1476 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1477 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1478 "checks for resource_id:%d\n", vhcr->op, slave,
1480 vhcr_cmd->status = CMD_STAT_BAD_OP;
1484 /* Allocate outbox */
1485 if (cmd->has_outbox) {
1486 outbox = mlx4_alloc_cmd_mailbox(dev);
1487 if (IS_ERR(outbox)) {
1488 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1494 /* Execute the command! */
1496 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1498 if (cmd->out_is_imm)
1499 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1501 in_param = cmd->has_inbox ? (u64) inbox->dma :
1503 out_param = cmd->has_outbox ? (u64) outbox->dma :
1505 err = __mlx4_cmd(dev, in_param, &out_param,
1506 cmd->out_is_imm, vhcr->in_modifier,
1507 vhcr->op_modifier, vhcr->op,
1508 MLX4_CMD_TIME_CLASS_A,
1511 if (cmd->out_is_imm) {
1512 vhcr->out_param = out_param;
1513 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1518 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1519 " error:%d, status %d\n",
1520 vhcr->op, slave, vhcr->errno, err);
1521 vhcr_cmd->status = mlx4_errno_to_status(err);
1526 /* Write outbox if command completed successfully */
1527 if (cmd->has_outbox && !vhcr_cmd->status) {
1528 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1530 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1532 /* If we failed to write back the outbox after the
1533 *command was successfully executed, we must fail this
1534 * slave, as it is now in undefined state */
1535 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1541 /* DMA back vhcr result */
1543 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1544 priv->mfunc.master.slave_state[slave].vhcr_dma,
1545 ALIGN(sizeof(struct mlx4_vhcr),
1546 MLX4_ACCESS_MEM_ALIGN),
1549 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1551 else if (vhcr->e_bit &&
1552 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1553 mlx4_warn(dev, "Failed to generate command completion "
1554 "eqe for slave %d\n", slave);
1559 mlx4_free_cmd_mailbox(dev, inbox);
1560 mlx4_free_cmd_mailbox(dev, outbox);
1564 static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
1565 int slave, int port)
1567 struct mlx4_vport_oper_state *vp_oper;
1568 struct mlx4_vport_state *vp_admin;
1569 struct mlx4_vf_immed_vlan_work *work;
1570 struct mlx4_dev *dev = &(priv->dev);
1572 int admin_vlan_ix = NO_INDX;
1574 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1575 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1577 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
1578 vp_oper->state.default_qos == vp_admin->default_qos &&
1579 vp_oper->state.link_state == vp_admin->link_state)
1582 if (!(priv->mfunc.master.slave_state[slave].active &&
1583 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
1584 /* even if the UPDATE_QP command isn't supported, we still want
1585 * to set this VF link according to the admin directive
1587 vp_oper->state.link_state = vp_admin->link_state;
1591 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1593 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n", vp_admin->default_vlan,
1594 vp_admin->default_qos, vp_admin->link_state);
1596 work = kzalloc(sizeof(*work), GFP_KERNEL);
1600 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
1601 if (MLX4_VGT != vp_admin->default_vlan) {
1602 err = __mlx4_register_vlan(&priv->dev, port,
1603 vp_admin->default_vlan,
1607 mlx4_warn((&priv->dev),
1608 "No vlan resources slave %d, port %d\n",
1613 admin_vlan_ix = NO_INDX;
1615 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1616 mlx4_dbg((&(priv->dev)),
1617 "alloc vlan %d idx %d slave %d port %d\n",
1618 (int)(vp_admin->default_vlan),
1619 admin_vlan_ix, slave, port);
1622 /* save original vlan ix and vlan id */
1623 work->orig_vlan_id = vp_oper->state.default_vlan;
1624 work->orig_vlan_ix = vp_oper->vlan_idx;
1626 /* handle new qos */
1627 if (vp_oper->state.default_qos != vp_admin->default_qos)
1628 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1630 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1631 vp_oper->vlan_idx = admin_vlan_ix;
1633 vp_oper->state.default_vlan = vp_admin->default_vlan;
1634 vp_oper->state.default_qos = vp_admin->default_qos;
1635 vp_oper->state.link_state = vp_admin->link_state;
1637 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1638 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
1640 /* iterate over QPs owned by this slave, using UPDATE_QP */
1642 work->slave = slave;
1643 work->qos = vp_oper->state.default_qos;
1644 work->vlan_id = vp_oper->state.default_vlan;
1645 work->vlan_ix = vp_oper->vlan_idx;
1647 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1648 queue_work(priv->mfunc.master.comm_wq, &work->work);
1654 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1657 struct mlx4_vport_state *vp_admin;
1658 struct mlx4_vport_oper_state *vp_oper;
1659 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1661 int min_port = find_first_bit(actv_ports.ports,
1662 priv->dev.caps.num_ports) + 1;
1663 int max_port = min_port - 1 +
1664 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1666 for (port = min_port; port <= max_port; port++) {
1667 if (!test_bit(port - 1, actv_ports.ports))
1669 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1670 priv->mfunc.master.vf_admin[slave].enable_smi[port];
1671 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1672 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1673 vp_oper->state = *vp_admin;
1674 if (MLX4_VGT != vp_admin->default_vlan) {
1675 err = __mlx4_register_vlan(&priv->dev, port,
1676 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1678 vp_oper->vlan_idx = NO_INDX;
1679 mlx4_warn((&priv->dev),
1680 "No vlan resorces slave %d, port %d\n",
1684 mlx4_dbg((&(priv->dev)), "alloc vlan %d idx %d slave %d port %d\n",
1685 (int)(vp_oper->state.default_vlan),
1686 vp_oper->vlan_idx, slave, port);
1688 if (vp_admin->spoofchk) {
1689 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1692 if (0 > vp_oper->mac_idx) {
1693 err = vp_oper->mac_idx;
1694 vp_oper->mac_idx = NO_INDX;
1695 mlx4_warn((&priv->dev),
1696 "No mac resorces slave %d, port %d\n",
1700 mlx4_dbg((&(priv->dev)), "alloc mac %llx idx %d slave %d port %d\n",
1701 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1707 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1710 struct mlx4_vport_oper_state *vp_oper;
1711 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1713 int min_port = find_first_bit(actv_ports.ports,
1714 priv->dev.caps.num_ports) + 1;
1715 int max_port = min_port - 1 +
1716 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1719 for (port = min_port; port <= max_port; port++) {
1720 if (!test_bit(port - 1, actv_ports.ports))
1722 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1723 MLX4_VF_SMI_DISABLED;
1724 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1725 if (NO_INDX != vp_oper->vlan_idx) {
1726 __mlx4_unregister_vlan(&priv->dev,
1727 port, vp_oper->state.default_vlan);
1728 vp_oper->vlan_idx = NO_INDX;
1730 if (NO_INDX != vp_oper->mac_idx) {
1731 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
1732 vp_oper->mac_idx = NO_INDX;
1738 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1739 u16 param, u8 toggle)
1741 struct mlx4_priv *priv = mlx4_priv(dev);
1742 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1744 u8 is_going_down = 0;
1746 unsigned long flags;
1748 slave_state[slave].comm_toggle ^= 1;
1749 reply = (u32) slave_state[slave].comm_toggle << 31;
1750 if (toggle != slave_state[slave].comm_toggle) {
1751 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1752 "STATE COMPROMISIED ***\n", toggle, slave);
1755 if (cmd == MLX4_COMM_CMD_RESET) {
1756 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1757 slave_state[slave].active = false;
1758 slave_state[slave].old_vlan_api = false;
1759 mlx4_master_deactivate_admin_state(priv, slave);
1760 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1761 slave_state[slave].event_eq[i].eqn = -1;
1762 slave_state[slave].event_eq[i].token = 0;
1764 /*check if we are in the middle of FLR process,
1765 if so return "retry" status to the slave*/
1766 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1767 goto inform_slave_state;
1769 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1771 /* write the version in the event field */
1772 reply |= mlx4_comm_get_version();
1776 /*command from slave in the middle of FLR*/
1777 if (cmd != MLX4_COMM_CMD_RESET &&
1778 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1779 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1780 "in the middle of FLR\n", slave, cmd);
1785 case MLX4_COMM_CMD_VHCR0:
1786 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1788 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1789 priv->mfunc.master.slave_state[slave].cookie = 0;
1790 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1792 case MLX4_COMM_CMD_VHCR1:
1793 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1795 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1797 case MLX4_COMM_CMD_VHCR2:
1798 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1800 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1802 case MLX4_COMM_CMD_VHCR_EN:
1803 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1805 slave_state[slave].vhcr_dma |= param;
1806 if (mlx4_master_activate_admin_state(priv, slave))
1808 slave_state[slave].active = true;
1809 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1811 case MLX4_COMM_CMD_VHCR_POST:
1812 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1813 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1816 mutex_lock(&priv->cmd.slave_cmd_mutex);
1817 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1818 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1819 " resetting slave.\n", slave);
1820 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1823 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1826 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1829 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1830 if (!slave_state[slave].is_slave_going_down)
1831 slave_state[slave].last_cmd = cmd;
1834 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1835 if (is_going_down) {
1836 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1837 " executing from slave:%d\n",
1841 __raw_writel((__force u32) cpu_to_be32(reply),
1842 &priv->mfunc.comm[slave].slave_read);
1848 /* cleanup any slave resources */
1849 mlx4_delete_all_resources_for_slave(dev, slave);
1850 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1851 if (!slave_state[slave].is_slave_going_down)
1852 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1853 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1854 /*with slave in the middle of flr, no need to clean resources again.*/
1856 memset(&slave_state[slave].event_eq, 0,
1857 sizeof(struct mlx4_slave_event_eq_info));
1858 __raw_writel((__force u32) cpu_to_be32(reply),
1859 &priv->mfunc.comm[slave].slave_read);
1863 /* master command processing */
1864 void mlx4_master_comm_channel(struct work_struct *work)
1866 struct mlx4_mfunc_master_ctx *master =
1868 struct mlx4_mfunc_master_ctx,
1870 struct mlx4_mfunc *mfunc =
1871 container_of(master, struct mlx4_mfunc, master);
1872 struct mlx4_priv *priv =
1873 container_of(mfunc, struct mlx4_priv, mfunc);
1874 struct mlx4_dev *dev = &priv->dev;
1884 bit_vec = master->comm_arm_bit_vector;
1885 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1886 vec = be32_to_cpu(bit_vec[i]);
1887 for (j = 0; j < 32; j++) {
1888 if (!(vec & (1 << j)))
1891 slave = (i * 32) + j;
1892 comm_cmd = swab32(readl(
1893 &mfunc->comm[slave].slave_write));
1894 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1896 toggle = comm_cmd >> 31;
1897 if (toggle != slt) {
1898 if (master->slave_state[slave].comm_toggle
1900 printk(KERN_INFO "slave %d out of sync."
1901 " read toggle %d, state toggle %d. "
1902 "Resynching.\n", slave, slt,
1903 master->slave_state[slave].comm_toggle);
1904 master->slave_state[slave].comm_toggle =
1907 mlx4_master_do_cmd(dev, slave,
1908 comm_cmd >> 16 & 0xff,
1909 comm_cmd & 0xffff, toggle);
1915 if (reported && reported != served)
1916 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1917 " but %d were served\n",
1920 if (mlx4_ARM_COMM_CHANNEL(dev))
1921 mlx4_warn(dev, "Failed to arm comm channel events\n");
1924 static int sync_toggles(struct mlx4_dev *dev)
1926 struct mlx4_priv *priv = mlx4_priv(dev);
1931 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1932 end = jiffies + msecs_to_jiffies(5000);
1934 while (time_before(jiffies, end)) {
1935 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1936 if (rd_toggle == wr_toggle) {
1937 priv->cmd.comm_toggle = rd_toggle;
1945 * we could reach here if for example the previous VM using this
1946 * function misbehaved and left the channel with unsynced state. We
1947 * should fix this here and give this VM a chance to use a properly
1950 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1951 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1952 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1953 priv->cmd.comm_toggle = 0;
1958 int mlx4_multi_func_init(struct mlx4_dev *dev)
1960 struct mlx4_priv *priv = mlx4_priv(dev);
1961 struct mlx4_slave_state *s_state;
1962 int i, j, err, port;
1964 if (mlx4_is_master(dev))
1966 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1967 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1970 ioremap(pci_resource_start(dev->pdev, 2) +
1971 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1972 if (!priv->mfunc.comm) {
1973 mlx4_err(dev, "Couldn't map communication vector.\n");
1977 if (mlx4_is_master(dev)) {
1978 priv->mfunc.master.slave_state =
1979 kzalloc(dev->num_slaves *
1980 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1981 if (!priv->mfunc.master.slave_state)
1984 priv->mfunc.master.vf_admin =
1985 kzalloc(dev->num_slaves *
1986 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1987 if (!priv->mfunc.master.vf_admin)
1988 goto err_comm_admin;
1990 priv->mfunc.master.vf_oper =
1991 kzalloc(dev->num_slaves *
1992 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1993 if (!priv->mfunc.master.vf_oper)
1996 for (i = 0; i < dev->num_slaves; ++i) {
1997 s_state = &priv->mfunc.master.slave_state[i];
1998 s_state->last_cmd = MLX4_COMM_CMD_RESET;
1999 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2000 s_state->event_eq[j].eqn = -1;
2001 __raw_writel((__force u32) 0,
2002 &priv->mfunc.comm[i].slave_write);
2003 __raw_writel((__force u32) 0,
2004 &priv->mfunc.comm[i].slave_read);
2006 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2007 s_state->vlan_filter[port] =
2008 kzalloc(sizeof(struct mlx4_vlan_fltr),
2010 if (!s_state->vlan_filter[port]) {
2012 kfree(s_state->vlan_filter[port]);
2015 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
2016 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
2017 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
2018 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2019 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
2021 spin_lock_init(&s_state->lock);
2024 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
2025 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2026 INIT_WORK(&priv->mfunc.master.comm_work,
2027 mlx4_master_comm_channel);
2028 INIT_WORK(&priv->mfunc.master.slave_event_work,
2029 mlx4_gen_slave_eqe);
2030 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2031 mlx4_master_handle_slave_flr);
2032 spin_lock_init(&priv->mfunc.master.slave_state_lock);
2033 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
2034 priv->mfunc.master.comm_wq =
2035 create_singlethread_workqueue("mlx4_comm");
2036 if (!priv->mfunc.master.comm_wq)
2039 if (mlx4_init_resource_tracker(dev))
2042 err = mlx4_ARM_COMM_CHANNEL(dev);
2044 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2050 err = sync_toggles(dev);
2052 mlx4_err(dev, "Couldn't sync toggles\n");
2059 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
2061 flush_workqueue(priv->mfunc.master.comm_wq);
2062 destroy_workqueue(priv->mfunc.master.comm_wq);
2065 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2066 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2068 kfree(priv->mfunc.master.vf_oper);
2070 kfree(priv->mfunc.master.vf_admin);
2072 kfree(priv->mfunc.master.slave_state);
2074 iounmap(priv->mfunc.comm);
2076 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2078 priv->mfunc.vhcr_dma);
2079 priv->mfunc.vhcr = NULL;
2083 int mlx4_cmd_init(struct mlx4_dev *dev)
2085 struct mlx4_priv *priv = mlx4_priv(dev);
2087 mutex_init(&priv->cmd.hcr_mutex);
2088 mutex_init(&priv->cmd.slave_cmd_mutex);
2089 sema_init(&priv->cmd.poll_sem, 1);
2090 priv->cmd.use_events = 0;
2091 priv->cmd.toggle = 1;
2093 priv->cmd.hcr = NULL;
2094 priv->mfunc.vhcr = NULL;
2096 if (!mlx4_is_slave(dev)) {
2097 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2098 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2099 if (!priv->cmd.hcr) {
2100 mlx4_err(dev, "Couldn't map command register.\n");
2105 if (mlx4_is_mfunc(dev)) {
2106 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2107 &priv->mfunc.vhcr_dma,
2109 if (!priv->mfunc.vhcr)
2113 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2115 MLX4_MAILBOX_SIZE, 0);
2116 if (!priv->cmd.pool)
2122 if (mlx4_is_mfunc(dev))
2123 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2124 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2125 priv->mfunc.vhcr = NULL;
2128 if (!mlx4_is_slave(dev))
2129 iounmap(priv->cmd.hcr);
2133 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2135 struct mlx4_priv *priv = mlx4_priv(dev);
2138 if (mlx4_is_master(dev)) {
2139 flush_workqueue(priv->mfunc.master.comm_wq);
2140 destroy_workqueue(priv->mfunc.master.comm_wq);
2141 for (i = 0; i < dev->num_slaves; i++) {
2142 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2143 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2145 kfree(priv->mfunc.master.slave_state);
2146 kfree(priv->mfunc.master.vf_admin);
2147 kfree(priv->mfunc.master.vf_oper);
2150 iounmap(priv->mfunc.comm);
2153 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2155 struct mlx4_priv *priv = mlx4_priv(dev);
2157 pci_pool_destroy(priv->cmd.pool);
2159 if (!mlx4_is_slave(dev))
2160 iounmap(priv->cmd.hcr);
2161 if (mlx4_is_mfunc(dev))
2162 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2163 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2164 priv->mfunc.vhcr = NULL;
2168 * Switch to using events to issue FW commands (can only be called
2169 * after event queue for command events has been initialized).
2171 int mlx4_cmd_use_events(struct mlx4_dev *dev)
2173 struct mlx4_priv *priv = mlx4_priv(dev);
2177 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2178 sizeof (struct mlx4_cmd_context),
2180 if (!priv->cmd.context)
2183 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2184 priv->cmd.context[i].token = i;
2185 priv->cmd.context[i].next = i + 1;
2188 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2189 priv->cmd.free_head = 0;
2191 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2192 spin_lock_init(&priv->cmd.context_lock);
2194 for (priv->cmd.token_mask = 1;
2195 priv->cmd.token_mask < priv->cmd.max_cmds;
2196 priv->cmd.token_mask <<= 1)
2198 --priv->cmd.token_mask;
2200 down(&priv->cmd.poll_sem);
2201 priv->cmd.use_events = 1;
2207 * Switch back to polling (used when shutting down the device)
2209 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2211 struct mlx4_priv *priv = mlx4_priv(dev);
2214 priv->cmd.use_events = 0;
2216 for (i = 0; i < priv->cmd.max_cmds; ++i)
2217 down(&priv->cmd.event_sem);
2219 kfree(priv->cmd.context);
2221 up(&priv->cmd.poll_sem);
2224 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2226 struct mlx4_cmd_mailbox *mailbox;
2228 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2230 return ERR_PTR(-ENOMEM);
2232 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2234 if (!mailbox->buf) {
2236 return ERR_PTR(-ENOMEM);
2239 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2243 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2245 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2246 struct mlx4_cmd_mailbox *mailbox)
2251 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2254 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2256 u32 mlx4_comm_get_version(void)
2258 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2261 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2263 if ((vf < 0) || (vf >= dev->num_vfs)) {
2264 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2271 int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2273 if (slave < 1 || slave > dev->num_vfs) {
2275 "Bad slave number:%d (number of activated slaves: %lu)\n",
2276 slave, dev->num_slaves);
2282 struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2284 struct mlx4_active_ports actv_ports;
2287 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2290 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2294 vf = mlx4_get_vf_indx(dev, slave);
2298 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2299 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2300 dev->caps.num_ports));
2304 EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2306 int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2309 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2310 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2312 if (port <= 0 || port > m)
2315 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2321 EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2323 int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2325 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2326 if (test_bit(port - 1, actv_ports.ports))
2328 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2332 EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2334 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2338 struct mlx4_slaves_pport slaves_pport;
2340 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2342 if (port <= 0 || port > dev->caps.num_ports)
2343 return slaves_pport;
2345 for (i = 0; i < dev->num_vfs + 1; i++) {
2346 struct mlx4_active_ports actv_ports =
2347 mlx4_get_active_ports(dev, i);
2348 if (test_bit(port - 1, actv_ports.ports))
2349 set_bit(i, slaves_pport.slaves);
2352 return slaves_pport;
2354 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2356 struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2357 struct mlx4_dev *dev,
2358 const struct mlx4_active_ports *crit_ports)
2361 struct mlx4_slaves_pport slaves_pport;
2363 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2365 for (i = 0; i < dev->num_vfs + 1; i++) {
2366 struct mlx4_active_ports actv_ports =
2367 mlx4_get_active_ports(dev, i);
2368 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2369 dev->caps.num_ports))
2370 set_bit(i, slaves_pport.slaves);
2373 return slaves_pport;
2375 EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2377 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2379 struct mlx4_priv *priv = mlx4_priv(dev);
2380 struct mlx4_vport_state *s_info;
2383 if (!mlx4_is_master(dev))
2384 return -EPROTONOSUPPORT;
2386 slave = mlx4_get_slave_indx(dev, vf);
2390 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2392 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2393 vf, port, s_info->mac);
2396 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2399 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2401 struct mlx4_priv *priv = mlx4_priv(dev);
2402 struct mlx4_vport_state *vf_admin;
2405 if ((!mlx4_is_master(dev)) ||
2406 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2407 return -EPROTONOSUPPORT;
2409 if ((vlan > 4095) || (qos > 7))
2412 slave = mlx4_get_slave_indx(dev, vf);
2416 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
2418 if ((0 == vlan) && (0 == qos))
2419 vf_admin->default_vlan = MLX4_VGT;
2421 vf_admin->default_vlan = vlan;
2422 vf_admin->default_qos = qos;
2424 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2426 "updating vf %d port %d config will take effect on next VF restart\n",
2430 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2432 /* mlx4_get_slave_default_vlan -
2433 * return true if VST ( default vlan)
2434 * if VST, will return vlan & qos (if not NULL)
2436 bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2439 struct mlx4_vport_oper_state *vp_oper;
2440 struct mlx4_priv *priv;
2442 priv = mlx4_priv(dev);
2443 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2445 if (MLX4_VGT != vp_oper->state.default_vlan) {
2447 *vlan = vp_oper->state.default_vlan;
2449 *qos = vp_oper->state.default_qos;
2454 EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2456 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2458 struct mlx4_priv *priv = mlx4_priv(dev);
2459 struct mlx4_vport_state *s_info;
2462 if ((!mlx4_is_master(dev)) ||
2463 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2464 return -EPROTONOSUPPORT;
2466 slave = mlx4_get_slave_indx(dev, vf);
2470 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2471 s_info->spoofchk = setting;
2475 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2477 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2479 struct mlx4_priv *priv = mlx4_priv(dev);
2480 struct mlx4_vport_state *s_info;
2483 if (!mlx4_is_master(dev))
2484 return -EPROTONOSUPPORT;
2486 slave = mlx4_get_slave_indx(dev, vf);
2490 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2493 /* need to convert it to a func */
2494 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2495 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2496 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2497 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2498 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2499 ivf->mac[5] = ((s_info->mac) & 0xff);
2501 ivf->vlan = s_info->default_vlan;
2502 ivf->qos = s_info->default_qos;
2503 ivf->tx_rate = s_info->tx_rate;
2504 ivf->spoofchk = s_info->spoofchk;
2505 ivf->linkstate = s_info->link_state;
2509 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2511 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2513 struct mlx4_priv *priv = mlx4_priv(dev);
2514 struct mlx4_vport_state *s_info;
2518 slave = mlx4_get_slave_indx(dev, vf);
2522 switch (link_state) {
2523 case IFLA_VF_LINK_STATE_AUTO:
2524 /* get current link state */
2525 if (!priv->sense.do_sense_port[port])
2526 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2528 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2531 case IFLA_VF_LINK_STATE_ENABLE:
2532 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2535 case IFLA_VF_LINK_STATE_DISABLE:
2536 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2540 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2541 link_state, slave, port);
2544 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2545 s_info->link_state = link_state;
2548 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2550 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2552 "updating vf %d port %d no link state HW enforcment\n",
2556 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
2558 int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
2560 struct mlx4_priv *priv = mlx4_priv(dev);
2562 if (slave < 1 || slave >= dev->num_slaves ||
2563 port < 1 || port > MLX4_MAX_PORTS)
2566 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
2567 MLX4_VF_SMI_ENABLED;
2569 EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
2571 int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
2573 struct mlx4_priv *priv = mlx4_priv(dev);
2575 if (slave == mlx4_master_func_num(dev))
2578 if (slave < 1 || slave >= dev->num_slaves ||
2579 port < 1 || port > MLX4_MAX_PORTS)
2582 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
2583 MLX4_VF_SMI_ENABLED;
2585 EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
2587 int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
2590 struct mlx4_priv *priv = mlx4_priv(dev);
2592 if (slave == mlx4_master_func_num(dev))
2595 if (slave < 1 || slave >= dev->num_slaves ||
2596 port < 1 || port > MLX4_MAX_PORTS ||
2597 enabled < 0 || enabled > 1)
2600 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
2603 EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);