2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/sched.h>
36 #include <linux/slab.h>
37 #include <linux/export.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
41 #include <linux/mlx4/cmd.h>
42 #include <linux/semaphore.h>
43 #include <rdma/ib_smi.h>
50 #define CMD_POLL_TOKEN 0xffff
51 #define INBOX_MASK 0xffffffffffffff00ULL
53 #define CMD_CHAN_VER 1
54 #define CMD_CHAN_IF_REV 1
57 /* command completed successfully: */
59 /* Internal error (such as a bus error) occurred while processing command: */
60 CMD_STAT_INTERNAL_ERR = 0x01,
61 /* Operation/command not supported or opcode modifier not supported: */
62 CMD_STAT_BAD_OP = 0x02,
63 /* Parameter not supported or parameter out of range: */
64 CMD_STAT_BAD_PARAM = 0x03,
65 /* System not enabled or bad system state: */
66 CMD_STAT_BAD_SYS_STATE = 0x04,
67 /* Attempt to access reserved or unallocaterd resource: */
68 CMD_STAT_BAD_RESOURCE = 0x05,
69 /* Requested resource is currently executing a command, or is otherwise busy: */
70 CMD_STAT_RESOURCE_BUSY = 0x06,
71 /* Required capability exceeds device limits: */
72 CMD_STAT_EXCEED_LIM = 0x08,
73 /* Resource is not in the appropriate state or ownership: */
74 CMD_STAT_BAD_RES_STATE = 0x09,
75 /* Index out of range: */
76 CMD_STAT_BAD_INDEX = 0x0a,
77 /* FW image corrupted: */
78 CMD_STAT_BAD_NVMEM = 0x0b,
79 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
80 CMD_STAT_ICM_ERROR = 0x0c,
81 /* Attempt to modify a QP/EE which is not in the presumed state: */
82 CMD_STAT_BAD_QP_STATE = 0x10,
83 /* Bad segment parameters (Address/Size): */
84 CMD_STAT_BAD_SEG_PARAM = 0x20,
85 /* Memory Region has Memory Windows bound to: */
86 CMD_STAT_REG_BOUND = 0x21,
87 /* HCA local attached memory not present: */
88 CMD_STAT_LAM_NOT_PRE = 0x22,
89 /* Bad management packet (silently discarded): */
90 CMD_STAT_BAD_PKT = 0x30,
91 /* More outstanding CQEs in CQ than new CQ size: */
92 CMD_STAT_BAD_SIZE = 0x40,
93 /* Multi Function device support required: */
94 CMD_STAT_MULTI_FUNC_REQ = 0x50,
98 HCR_IN_PARAM_OFFSET = 0x00,
99 HCR_IN_MODIFIER_OFFSET = 0x08,
100 HCR_OUT_PARAM_OFFSET = 0x0c,
101 HCR_TOKEN_OFFSET = 0x14,
102 HCR_STATUS_OFFSET = 0x18,
104 HCR_OPMOD_SHIFT = 12,
111 GO_BIT_TIMEOUT_MSECS = 10000
114 struct mlx4_cmd_context {
115 struct completion done;
123 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
124 struct mlx4_vhcr_cmd *in_vhcr);
126 static int mlx4_status_to_errno(u8 status)
128 static const int trans_table[] = {
129 [CMD_STAT_INTERNAL_ERR] = -EIO,
130 [CMD_STAT_BAD_OP] = -EPERM,
131 [CMD_STAT_BAD_PARAM] = -EINVAL,
132 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
133 [CMD_STAT_BAD_RESOURCE] = -EBADF,
134 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
135 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
136 [CMD_STAT_BAD_RES_STATE] = -EBADF,
137 [CMD_STAT_BAD_INDEX] = -EBADF,
138 [CMD_STAT_BAD_NVMEM] = -EFAULT,
139 [CMD_STAT_ICM_ERROR] = -ENFILE,
140 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
141 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
142 [CMD_STAT_REG_BOUND] = -EBUSY,
143 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
144 [CMD_STAT_BAD_PKT] = -EINVAL,
145 [CMD_STAT_BAD_SIZE] = -ENOMEM,
146 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
149 if (status >= ARRAY_SIZE(trans_table) ||
150 (status != CMD_STAT_OK && trans_table[status] == 0))
153 return trans_table[status];
156 static u8 mlx4_errno_to_status(int errno)
160 return CMD_STAT_BAD_OP;
162 return CMD_STAT_BAD_PARAM;
164 return CMD_STAT_BAD_SYS_STATE;
166 return CMD_STAT_RESOURCE_BUSY;
168 return CMD_STAT_EXCEED_LIM;
170 return CMD_STAT_ICM_ERROR;
172 return CMD_STAT_INTERNAL_ERR;
176 static int comm_pending(struct mlx4_dev *dev)
178 struct mlx4_priv *priv = mlx4_priv(dev);
179 u32 status = readl(&priv->mfunc.comm->slave_read);
181 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
184 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
186 struct mlx4_priv *priv = mlx4_priv(dev);
189 priv->cmd.comm_toggle ^= 1;
190 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
191 __raw_writel((__force u32) cpu_to_be32(val),
192 &priv->mfunc.comm->slave_write);
196 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
197 unsigned long timeout)
199 struct mlx4_priv *priv = mlx4_priv(dev);
202 int ret_from_pending = 0;
204 /* First, verify that the master reports correct status */
205 if (comm_pending(dev)) {
206 mlx4_warn(dev, "Communication channel is not idle."
207 "my toggle is %d (cmd:0x%x)\n",
208 priv->cmd.comm_toggle, cmd);
213 down(&priv->cmd.poll_sem);
214 mlx4_comm_cmd_post(dev, cmd, param);
216 end = msecs_to_jiffies(timeout) + jiffies;
217 while (comm_pending(dev) && time_before(jiffies, end))
219 ret_from_pending = comm_pending(dev);
220 if (ret_from_pending) {
221 /* check if the slave is trying to boot in the middle of
222 * FLR process. The only non-zero result in the RESET command
223 * is MLX4_DELAY_RESET_SLAVE*/
224 if ((MLX4_COMM_CMD_RESET == cmd)) {
225 err = MLX4_DELAY_RESET_SLAVE;
227 mlx4_warn(dev, "Communication channel timed out\n");
232 up(&priv->cmd.poll_sem);
236 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
237 u16 param, unsigned long timeout)
239 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
240 struct mlx4_cmd_context *context;
244 down(&cmd->event_sem);
246 spin_lock(&cmd->context_lock);
247 BUG_ON(cmd->free_head < 0);
248 context = &cmd->context[cmd->free_head];
249 context->token += cmd->token_mask + 1;
250 cmd->free_head = context->next;
251 spin_unlock(&cmd->context_lock);
253 init_completion(&context->done);
255 mlx4_comm_cmd_post(dev, op, param);
257 if (!wait_for_completion_timeout(&context->done,
258 msecs_to_jiffies(timeout))) {
263 err = context->result;
264 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
265 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
266 op, context->fw_status);
271 /* wait for comm channel ready
272 * this is necessary for prevention the race
273 * when switching between event to polling mode
275 end = msecs_to_jiffies(timeout) + jiffies;
276 while (comm_pending(dev) && time_before(jiffies, end))
279 spin_lock(&cmd->context_lock);
280 context->next = cmd->free_head;
281 cmd->free_head = context - cmd->context;
282 spin_unlock(&cmd->context_lock);
288 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
289 unsigned long timeout)
291 if (mlx4_priv(dev)->cmd.use_events)
292 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
293 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
296 static int cmd_pending(struct mlx4_dev *dev)
300 if (pci_channel_offline(dev->pdev))
303 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
305 return (status & swab32(1 << HCR_GO_BIT)) ||
306 (mlx4_priv(dev)->cmd.toggle ==
307 !!(status & swab32(1 << HCR_T_BIT)));
310 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
311 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
314 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
315 u32 __iomem *hcr = cmd->hcr;
319 mutex_lock(&cmd->hcr_mutex);
321 if (pci_channel_offline(dev->pdev)) {
323 * Device is going through error recovery
324 * and cannot accept commands.
332 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
334 while (cmd_pending(dev)) {
335 if (pci_channel_offline(dev->pdev)) {
337 * Device is going through error recovery
338 * and cannot accept commands.
344 if (time_after_eq(jiffies, end)) {
345 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
352 * We use writel (instead of something like memcpy_toio)
353 * because writes of less than 32 bits to the HCR don't work
354 * (and some architectures such as ia64 implement memcpy_toio
355 * in terms of writeb).
357 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
358 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
359 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
360 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
361 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
362 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
364 /* __raw_writel may not order writes. */
367 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
368 (cmd->toggle << HCR_T_BIT) |
369 (event ? (1 << HCR_E_BIT) : 0) |
370 (op_modifier << HCR_OPMOD_SHIFT) |
374 * Make sure that our HCR writes don't get mixed in with
375 * writes from another CPU starting a FW command.
379 cmd->toggle = cmd->toggle ^ 1;
384 mutex_unlock(&cmd->hcr_mutex);
388 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
389 int out_is_imm, u32 in_modifier, u8 op_modifier,
390 u16 op, unsigned long timeout)
392 struct mlx4_priv *priv = mlx4_priv(dev);
393 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
396 mutex_lock(&priv->cmd.slave_cmd_mutex);
398 vhcr->in_param = cpu_to_be64(in_param);
399 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
400 vhcr->in_modifier = cpu_to_be32(in_modifier);
401 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
402 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
404 vhcr->flags = !!(priv->cmd.use_events) << 6;
406 if (mlx4_is_master(dev)) {
407 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
412 be64_to_cpu(vhcr->out_param);
414 mlx4_err(dev, "response expected while"
415 "output mailbox is NULL for "
416 "command 0x%x\n", op);
417 vhcr->status = CMD_STAT_BAD_PARAM;
420 ret = mlx4_status_to_errno(vhcr->status);
423 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
424 MLX4_COMM_TIME + timeout);
429 be64_to_cpu(vhcr->out_param);
431 mlx4_err(dev, "response expected while"
432 "output mailbox is NULL for "
433 "command 0x%x\n", op);
434 vhcr->status = CMD_STAT_BAD_PARAM;
437 ret = mlx4_status_to_errno(vhcr->status);
439 mlx4_err(dev, "failed execution of VHCR_POST command"
440 "opcode 0x%x\n", op);
443 mutex_unlock(&priv->cmd.slave_cmd_mutex);
447 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
448 int out_is_imm, u32 in_modifier, u8 op_modifier,
449 u16 op, unsigned long timeout)
451 struct mlx4_priv *priv = mlx4_priv(dev);
452 void __iomem *hcr = priv->cmd.hcr;
457 down(&priv->cmd.poll_sem);
459 if (pci_channel_offline(dev->pdev)) {
461 * Device is going through error recovery
462 * and cannot accept commands.
468 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
469 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
473 end = msecs_to_jiffies(timeout) + jiffies;
474 while (cmd_pending(dev) && time_before(jiffies, end)) {
475 if (pci_channel_offline(dev->pdev)) {
477 * Device is going through error recovery
478 * and cannot accept commands.
487 if (cmd_pending(dev)) {
494 (u64) be32_to_cpu((__force __be32)
495 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
496 (u64) be32_to_cpu((__force __be32)
497 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
498 stat = be32_to_cpu((__force __be32)
499 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
500 err = mlx4_status_to_errno(stat);
502 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
506 up(&priv->cmd.poll_sem);
510 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
512 struct mlx4_priv *priv = mlx4_priv(dev);
513 struct mlx4_cmd_context *context =
514 &priv->cmd.context[token & priv->cmd.token_mask];
516 /* previously timed out command completing at long last */
517 if (token != context->token)
520 context->fw_status = status;
521 context->result = mlx4_status_to_errno(status);
522 context->out_param = out_param;
524 complete(&context->done);
527 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
528 int out_is_imm, u32 in_modifier, u8 op_modifier,
529 u16 op, unsigned long timeout)
531 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
532 struct mlx4_cmd_context *context;
535 down(&cmd->event_sem);
537 spin_lock(&cmd->context_lock);
538 BUG_ON(cmd->free_head < 0);
539 context = &cmd->context[cmd->free_head];
540 context->token += cmd->token_mask + 1;
541 cmd->free_head = context->next;
542 spin_unlock(&cmd->context_lock);
544 init_completion(&context->done);
546 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
547 in_modifier, op_modifier, op, context->token, 1);
549 if (!wait_for_completion_timeout(&context->done,
550 msecs_to_jiffies(timeout))) {
555 err = context->result;
557 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
558 op, context->fw_status);
563 *out_param = context->out_param;
566 spin_lock(&cmd->context_lock);
567 context->next = cmd->free_head;
568 cmd->free_head = context - cmd->context;
569 spin_unlock(&cmd->context_lock);
575 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
576 int out_is_imm, u32 in_modifier, u8 op_modifier,
577 u16 op, unsigned long timeout, int native)
579 if (pci_channel_offline(dev->pdev))
582 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
583 if (mlx4_priv(dev)->cmd.use_events)
584 return mlx4_cmd_wait(dev, in_param, out_param,
585 out_is_imm, in_modifier,
586 op_modifier, op, timeout);
588 return mlx4_cmd_poll(dev, in_param, out_param,
589 out_is_imm, in_modifier,
590 op_modifier, op, timeout);
592 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
593 in_modifier, op_modifier, op, timeout);
595 EXPORT_SYMBOL_GPL(__mlx4_cmd);
598 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
600 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
601 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
604 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
605 int slave, u64 slave_addr,
606 int size, int is_read)
611 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
612 (slave & ~0x7f) | (size & 0xff)) {
613 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
614 "master_addr:0x%llx slave_id:%d size:%d\n",
615 slave_addr, master_addr, slave, size);
620 in_param = (u64) slave | slave_addr;
621 out_param = (u64) dev->caps.function | master_addr;
623 in_param = (u64) dev->caps.function | master_addr;
624 out_param = (u64) slave | slave_addr;
627 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
629 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
632 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
633 struct mlx4_cmd_mailbox *inbox,
634 struct mlx4_cmd_mailbox *outbox)
636 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
637 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
644 in_mad->attr_mod = cpu_to_be32(index / 32);
646 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
647 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
652 for (i = 0; i < 32; ++i)
653 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
658 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
659 struct mlx4_cmd_mailbox *inbox,
660 struct mlx4_cmd_mailbox *outbox)
665 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
666 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
673 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
674 #define PORT_STATE_OFFSET 32
676 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
678 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
679 return IB_PORT_ACTIVE;
684 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
685 struct mlx4_vhcr *vhcr,
686 struct mlx4_cmd_mailbox *inbox,
687 struct mlx4_cmd_mailbox *outbox,
688 struct mlx4_cmd_info *cmd)
690 struct ib_smp *smp = inbox->buf;
696 struct mlx4_priv *priv = mlx4_priv(dev);
697 struct ib_smp *outsmp = outbox->buf;
698 __be16 *outtab = (__be16 *)(outsmp->data);
699 __be32 slave_cap_mask;
700 __be64 slave_node_guid;
701 port = vhcr->in_modifier;
703 if (smp->base_version == 1 &&
704 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
705 smp->class_version == 1) {
706 if (smp->method == IB_MGMT_METHOD_GET) {
707 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
708 index = be32_to_cpu(smp->attr_mod);
709 if (port < 1 || port > dev->caps.num_ports)
711 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
714 /* need to get the full pkey table because the paravirtualized
715 * pkeys may be scattered among several pkey blocks.
717 err = get_full_pkey_table(dev, port, table, inbox, outbox);
719 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
720 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
721 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
727 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
728 /*get the slave specific caps:*/
730 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
731 vhcr->in_modifier, vhcr->op_modifier,
732 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
733 /* modify the response for slaves */
734 if (!err && slave != mlx4_master_func_num(dev)) {
735 u8 *state = outsmp->data + PORT_STATE_OFFSET;
737 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
738 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
739 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
743 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
744 /* compute slave's gid block */
745 smp->attr_mod = cpu_to_be32(slave / 8);
747 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
748 vhcr->in_modifier, vhcr->op_modifier,
749 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
751 /* if needed, move slave gid to index 0 */
754 outsmp->data + (slave % 8) * 8, 8);
755 /* delete all other gids */
756 memset(outsmp->data + 8, 0, 56);
760 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
761 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
762 vhcr->in_modifier, vhcr->op_modifier,
763 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
765 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
766 memcpy(outsmp->data + 12, &slave_node_guid, 8);
772 if (slave != mlx4_master_func_num(dev) &&
773 ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
774 (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
775 smp->method == IB_MGMT_METHOD_SET))) {
776 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
777 "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
778 slave, smp->method, smp->mgmt_class,
779 be16_to_cpu(smp->attr_id));
783 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
784 vhcr->in_modifier, vhcr->op_modifier,
785 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
788 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
789 struct mlx4_vhcr *vhcr,
790 struct mlx4_cmd_mailbox *inbox,
791 struct mlx4_cmd_mailbox *outbox,
792 struct mlx4_cmd_info *cmd)
798 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
799 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
800 if (cmd->encode_slave_id) {
801 in_param &= 0xffffffffffffff00ll;
805 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
806 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
807 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
810 vhcr->out_param = out_param;
815 static struct mlx4_cmd_info cmd_info[] = {
817 .opcode = MLX4_CMD_QUERY_FW,
821 .encode_slave_id = false,
823 .wrapper = mlx4_QUERY_FW_wrapper
826 .opcode = MLX4_CMD_QUERY_HCA,
830 .encode_slave_id = false,
835 .opcode = MLX4_CMD_QUERY_DEV_CAP,
839 .encode_slave_id = false,
841 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
844 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
848 .encode_slave_id = false,
850 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
853 .opcode = MLX4_CMD_QUERY_ADAPTER,
857 .encode_slave_id = false,
862 .opcode = MLX4_CMD_INIT_PORT,
866 .encode_slave_id = false,
868 .wrapper = mlx4_INIT_PORT_wrapper
871 .opcode = MLX4_CMD_CLOSE_PORT,
875 .encode_slave_id = false,
877 .wrapper = mlx4_CLOSE_PORT_wrapper
880 .opcode = MLX4_CMD_QUERY_PORT,
884 .encode_slave_id = false,
886 .wrapper = mlx4_QUERY_PORT_wrapper
889 .opcode = MLX4_CMD_SET_PORT,
893 .encode_slave_id = false,
895 .wrapper = mlx4_SET_PORT_wrapper
898 .opcode = MLX4_CMD_MAP_EQ,
902 .encode_slave_id = false,
904 .wrapper = mlx4_MAP_EQ_wrapper
907 .opcode = MLX4_CMD_SW2HW_EQ,
911 .encode_slave_id = true,
913 .wrapper = mlx4_SW2HW_EQ_wrapper
916 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
920 .encode_slave_id = false,
925 .opcode = MLX4_CMD_NOP,
929 .encode_slave_id = false,
934 .opcode = MLX4_CMD_ALLOC_RES,
938 .encode_slave_id = false,
940 .wrapper = mlx4_ALLOC_RES_wrapper
943 .opcode = MLX4_CMD_FREE_RES,
947 .encode_slave_id = false,
949 .wrapper = mlx4_FREE_RES_wrapper
952 .opcode = MLX4_CMD_SW2HW_MPT,
956 .encode_slave_id = true,
958 .wrapper = mlx4_SW2HW_MPT_wrapper
961 .opcode = MLX4_CMD_QUERY_MPT,
965 .encode_slave_id = false,
967 .wrapper = mlx4_QUERY_MPT_wrapper
970 .opcode = MLX4_CMD_HW2SW_MPT,
974 .encode_slave_id = false,
976 .wrapper = mlx4_HW2SW_MPT_wrapper
979 .opcode = MLX4_CMD_READ_MTT,
983 .encode_slave_id = false,
988 .opcode = MLX4_CMD_WRITE_MTT,
992 .encode_slave_id = false,
994 .wrapper = mlx4_WRITE_MTT_wrapper
997 .opcode = MLX4_CMD_SYNC_TPT,
1000 .out_is_imm = false,
1001 .encode_slave_id = false,
1006 .opcode = MLX4_CMD_HW2SW_EQ,
1009 .out_is_imm = false,
1010 .encode_slave_id = true,
1012 .wrapper = mlx4_HW2SW_EQ_wrapper
1015 .opcode = MLX4_CMD_QUERY_EQ,
1018 .out_is_imm = false,
1019 .encode_slave_id = true,
1021 .wrapper = mlx4_QUERY_EQ_wrapper
1024 .opcode = MLX4_CMD_SW2HW_CQ,
1026 .has_outbox = false,
1027 .out_is_imm = false,
1028 .encode_slave_id = true,
1030 .wrapper = mlx4_SW2HW_CQ_wrapper
1033 .opcode = MLX4_CMD_HW2SW_CQ,
1035 .has_outbox = false,
1036 .out_is_imm = false,
1037 .encode_slave_id = false,
1039 .wrapper = mlx4_HW2SW_CQ_wrapper
1042 .opcode = MLX4_CMD_QUERY_CQ,
1045 .out_is_imm = false,
1046 .encode_slave_id = false,
1048 .wrapper = mlx4_QUERY_CQ_wrapper
1051 .opcode = MLX4_CMD_MODIFY_CQ,
1053 .has_outbox = false,
1055 .encode_slave_id = false,
1057 .wrapper = mlx4_MODIFY_CQ_wrapper
1060 .opcode = MLX4_CMD_SW2HW_SRQ,
1062 .has_outbox = false,
1063 .out_is_imm = false,
1064 .encode_slave_id = true,
1066 .wrapper = mlx4_SW2HW_SRQ_wrapper
1069 .opcode = MLX4_CMD_HW2SW_SRQ,
1071 .has_outbox = false,
1072 .out_is_imm = false,
1073 .encode_slave_id = false,
1075 .wrapper = mlx4_HW2SW_SRQ_wrapper
1078 .opcode = MLX4_CMD_QUERY_SRQ,
1081 .out_is_imm = false,
1082 .encode_slave_id = false,
1084 .wrapper = mlx4_QUERY_SRQ_wrapper
1087 .opcode = MLX4_CMD_ARM_SRQ,
1089 .has_outbox = false,
1090 .out_is_imm = false,
1091 .encode_slave_id = false,
1093 .wrapper = mlx4_ARM_SRQ_wrapper
1096 .opcode = MLX4_CMD_RST2INIT_QP,
1098 .has_outbox = false,
1099 .out_is_imm = false,
1100 .encode_slave_id = true,
1102 .wrapper = mlx4_RST2INIT_QP_wrapper
1105 .opcode = MLX4_CMD_INIT2INIT_QP,
1107 .has_outbox = false,
1108 .out_is_imm = false,
1109 .encode_slave_id = false,
1111 .wrapper = mlx4_INIT2INIT_QP_wrapper
1114 .opcode = MLX4_CMD_INIT2RTR_QP,
1116 .has_outbox = false,
1117 .out_is_imm = false,
1118 .encode_slave_id = false,
1120 .wrapper = mlx4_INIT2RTR_QP_wrapper
1123 .opcode = MLX4_CMD_RTR2RTS_QP,
1125 .has_outbox = false,
1126 .out_is_imm = false,
1127 .encode_slave_id = false,
1129 .wrapper = mlx4_RTR2RTS_QP_wrapper
1132 .opcode = MLX4_CMD_RTS2RTS_QP,
1134 .has_outbox = false,
1135 .out_is_imm = false,
1136 .encode_slave_id = false,
1138 .wrapper = mlx4_RTS2RTS_QP_wrapper
1141 .opcode = MLX4_CMD_SQERR2RTS_QP,
1143 .has_outbox = false,
1144 .out_is_imm = false,
1145 .encode_slave_id = false,
1147 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1150 .opcode = MLX4_CMD_2ERR_QP,
1152 .has_outbox = false,
1153 .out_is_imm = false,
1154 .encode_slave_id = false,
1156 .wrapper = mlx4_GEN_QP_wrapper
1159 .opcode = MLX4_CMD_RTS2SQD_QP,
1161 .has_outbox = false,
1162 .out_is_imm = false,
1163 .encode_slave_id = false,
1165 .wrapper = mlx4_GEN_QP_wrapper
1168 .opcode = MLX4_CMD_SQD2SQD_QP,
1170 .has_outbox = false,
1171 .out_is_imm = false,
1172 .encode_slave_id = false,
1174 .wrapper = mlx4_SQD2SQD_QP_wrapper
1177 .opcode = MLX4_CMD_SQD2RTS_QP,
1179 .has_outbox = false,
1180 .out_is_imm = false,
1181 .encode_slave_id = false,
1183 .wrapper = mlx4_SQD2RTS_QP_wrapper
1186 .opcode = MLX4_CMD_2RST_QP,
1188 .has_outbox = false,
1189 .out_is_imm = false,
1190 .encode_slave_id = false,
1192 .wrapper = mlx4_2RST_QP_wrapper
1195 .opcode = MLX4_CMD_QUERY_QP,
1198 .out_is_imm = false,
1199 .encode_slave_id = false,
1201 .wrapper = mlx4_GEN_QP_wrapper
1204 .opcode = MLX4_CMD_SUSPEND_QP,
1206 .has_outbox = false,
1207 .out_is_imm = false,
1208 .encode_slave_id = false,
1210 .wrapper = mlx4_GEN_QP_wrapper
1213 .opcode = MLX4_CMD_UNSUSPEND_QP,
1215 .has_outbox = false,
1216 .out_is_imm = false,
1217 .encode_slave_id = false,
1219 .wrapper = mlx4_GEN_QP_wrapper
1222 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1224 .has_outbox = false,
1225 .out_is_imm = false,
1226 .encode_slave_id = false,
1227 .verify = NULL, /* XXX verify: only demux can do this */
1231 .opcode = MLX4_CMD_MAD_IFC,
1234 .out_is_imm = false,
1235 .encode_slave_id = false,
1237 .wrapper = mlx4_MAD_IFC_wrapper
1240 .opcode = MLX4_CMD_QUERY_IF_STAT,
1243 .out_is_imm = false,
1244 .encode_slave_id = false,
1246 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1248 /* Native multicast commands are not available for guests */
1250 .opcode = MLX4_CMD_QP_ATTACH,
1252 .has_outbox = false,
1253 .out_is_imm = false,
1254 .encode_slave_id = false,
1256 .wrapper = mlx4_QP_ATTACH_wrapper
1259 .opcode = MLX4_CMD_PROMISC,
1261 .has_outbox = false,
1262 .out_is_imm = false,
1263 .encode_slave_id = false,
1265 .wrapper = mlx4_PROMISC_wrapper
1267 /* Ethernet specific commands */
1269 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1271 .has_outbox = false,
1272 .out_is_imm = false,
1273 .encode_slave_id = false,
1275 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1278 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1280 .has_outbox = false,
1281 .out_is_imm = false,
1282 .encode_slave_id = false,
1284 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1287 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1290 .out_is_imm = false,
1291 .encode_slave_id = false,
1293 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1296 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1298 .has_outbox = false,
1299 .out_is_imm = false,
1300 .encode_slave_id = false,
1304 /* flow steering commands */
1306 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1308 .has_outbox = false,
1310 .encode_slave_id = false,
1312 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1315 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1317 .has_outbox = false,
1318 .out_is_imm = false,
1319 .encode_slave_id = false,
1321 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1325 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1326 struct mlx4_vhcr_cmd *in_vhcr)
1328 struct mlx4_priv *priv = mlx4_priv(dev);
1329 struct mlx4_cmd_info *cmd = NULL;
1330 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1331 struct mlx4_vhcr *vhcr;
1332 struct mlx4_cmd_mailbox *inbox = NULL;
1333 struct mlx4_cmd_mailbox *outbox = NULL;
1340 /* Create sw representation of Virtual HCR */
1341 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1345 /* DMA in the vHCR */
1347 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1348 priv->mfunc.master.slave_state[slave].vhcr_dma,
1349 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1350 MLX4_ACCESS_MEM_ALIGN), 1);
1352 mlx4_err(dev, "%s:Failed reading vhcr"
1353 "ret: 0x%x\n", __func__, ret);
1359 /* Fill SW VHCR fields */
1360 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1361 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1362 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1363 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1364 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1365 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1366 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1368 /* Lookup command */
1369 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1370 if (vhcr->op == cmd_info[i].opcode) {
1376 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1378 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1383 if (cmd->has_inbox) {
1384 vhcr->in_param &= INBOX_MASK;
1385 inbox = mlx4_alloc_cmd_mailbox(dev);
1386 if (IS_ERR(inbox)) {
1387 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1392 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1394 MLX4_MAILBOX_SIZE, 1)) {
1395 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1396 __func__, cmd->opcode);
1397 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1402 /* Apply permission and bound checks if applicable */
1403 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1404 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1405 "checks for resource_id:%d\n", vhcr->op, slave,
1407 vhcr_cmd->status = CMD_STAT_BAD_OP;
1411 /* Allocate outbox */
1412 if (cmd->has_outbox) {
1413 outbox = mlx4_alloc_cmd_mailbox(dev);
1414 if (IS_ERR(outbox)) {
1415 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1421 /* Execute the command! */
1423 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1425 if (cmd->out_is_imm)
1426 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1428 in_param = cmd->has_inbox ? (u64) inbox->dma :
1430 out_param = cmd->has_outbox ? (u64) outbox->dma :
1432 err = __mlx4_cmd(dev, in_param, &out_param,
1433 cmd->out_is_imm, vhcr->in_modifier,
1434 vhcr->op_modifier, vhcr->op,
1435 MLX4_CMD_TIME_CLASS_A,
1438 if (cmd->out_is_imm) {
1439 vhcr->out_param = out_param;
1440 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1445 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1446 " error:%d, status %d\n",
1447 vhcr->op, slave, vhcr->errno, err);
1448 vhcr_cmd->status = mlx4_errno_to_status(err);
1453 /* Write outbox if command completed successfully */
1454 if (cmd->has_outbox && !vhcr_cmd->status) {
1455 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1457 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1459 /* If we failed to write back the outbox after the
1460 *command was successfully executed, we must fail this
1461 * slave, as it is now in undefined state */
1462 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1468 /* DMA back vhcr result */
1470 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1471 priv->mfunc.master.slave_state[slave].vhcr_dma,
1472 ALIGN(sizeof(struct mlx4_vhcr),
1473 MLX4_ACCESS_MEM_ALIGN),
1476 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1478 else if (vhcr->e_bit &&
1479 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1480 mlx4_warn(dev, "Failed to generate command completion "
1481 "eqe for slave %d\n", slave);
1486 mlx4_free_cmd_mailbox(dev, inbox);
1487 mlx4_free_cmd_mailbox(dev, outbox);
1491 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1494 struct mlx4_vport_state *vp_admin;
1495 struct mlx4_vport_oper_state *vp_oper;
1497 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1498 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1499 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1500 vp_oper->state = *vp_admin;
1501 if (MLX4_VGT != vp_admin->default_vlan) {
1502 err = __mlx4_register_vlan(&priv->dev, port,
1503 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1505 vp_oper->vlan_idx = NO_INDX;
1506 mlx4_warn((&priv->dev),
1507 "No vlan resorces slave %d, port %d\n",
1511 mlx4_dbg((&(priv->dev)), "alloc vlan %d idx %d slave %d port %d\n",
1512 (int)(vp_oper->state.default_vlan),
1513 vp_oper->vlan_idx, slave, port);
1515 if (vp_admin->spoofchk) {
1516 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1519 if (0 > vp_oper->mac_idx) {
1520 err = vp_oper->mac_idx;
1521 vp_oper->mac_idx = NO_INDX;
1522 mlx4_warn((&priv->dev),
1523 "No mac resorces slave %d, port %d\n",
1527 mlx4_dbg((&(priv->dev)), "alloc mac %llx idx %d slave %d port %d\n",
1528 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1534 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1537 struct mlx4_vport_oper_state *vp_oper;
1539 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1540 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1541 if (NO_INDX != vp_oper->vlan_idx) {
1542 __mlx4_unregister_vlan(&priv->dev,
1543 port, vp_oper->vlan_idx);
1544 vp_oper->vlan_idx = NO_INDX;
1546 if (NO_INDX != vp_oper->mac_idx) {
1547 __mlx4_unregister_mac(&priv->dev, port, vp_oper->mac_idx);
1548 vp_oper->mac_idx = NO_INDX;
1554 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1555 u16 param, u8 toggle)
1557 struct mlx4_priv *priv = mlx4_priv(dev);
1558 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1560 u8 is_going_down = 0;
1562 unsigned long flags;
1564 slave_state[slave].comm_toggle ^= 1;
1565 reply = (u32) slave_state[slave].comm_toggle << 31;
1566 if (toggle != slave_state[slave].comm_toggle) {
1567 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1568 "STATE COMPROMISIED ***\n", toggle, slave);
1571 if (cmd == MLX4_COMM_CMD_RESET) {
1572 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1573 slave_state[slave].active = false;
1574 mlx4_master_deactivate_admin_state(priv, slave);
1575 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1576 slave_state[slave].event_eq[i].eqn = -1;
1577 slave_state[slave].event_eq[i].token = 0;
1579 /*check if we are in the middle of FLR process,
1580 if so return "retry" status to the slave*/
1581 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1582 goto inform_slave_state;
1584 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1586 /* write the version in the event field */
1587 reply |= mlx4_comm_get_version();
1591 /*command from slave in the middle of FLR*/
1592 if (cmd != MLX4_COMM_CMD_RESET &&
1593 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1594 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1595 "in the middle of FLR\n", slave, cmd);
1600 case MLX4_COMM_CMD_VHCR0:
1601 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1603 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1604 priv->mfunc.master.slave_state[slave].cookie = 0;
1605 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1607 case MLX4_COMM_CMD_VHCR1:
1608 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1610 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1612 case MLX4_COMM_CMD_VHCR2:
1613 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1615 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1617 case MLX4_COMM_CMD_VHCR_EN:
1618 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1620 slave_state[slave].vhcr_dma |= param;
1621 if (mlx4_master_activate_admin_state(priv, slave))
1623 slave_state[slave].active = true;
1624 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1626 case MLX4_COMM_CMD_VHCR_POST:
1627 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1628 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1631 mutex_lock(&priv->cmd.slave_cmd_mutex);
1632 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1633 mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1634 " resetting slave.\n", slave);
1635 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1638 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1641 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1644 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1645 if (!slave_state[slave].is_slave_going_down)
1646 slave_state[slave].last_cmd = cmd;
1649 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1650 if (is_going_down) {
1651 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1652 " executing from slave:%d\n",
1656 __raw_writel((__force u32) cpu_to_be32(reply),
1657 &priv->mfunc.comm[slave].slave_read);
1663 /* cleanup any slave resources */
1664 mlx4_delete_all_resources_for_slave(dev, slave);
1665 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1666 if (!slave_state[slave].is_slave_going_down)
1667 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1668 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1669 /*with slave in the middle of flr, no need to clean resources again.*/
1671 memset(&slave_state[slave].event_eq, 0,
1672 sizeof(struct mlx4_slave_event_eq_info));
1673 __raw_writel((__force u32) cpu_to_be32(reply),
1674 &priv->mfunc.comm[slave].slave_read);
1678 /* master command processing */
1679 void mlx4_master_comm_channel(struct work_struct *work)
1681 struct mlx4_mfunc_master_ctx *master =
1683 struct mlx4_mfunc_master_ctx,
1685 struct mlx4_mfunc *mfunc =
1686 container_of(master, struct mlx4_mfunc, master);
1687 struct mlx4_priv *priv =
1688 container_of(mfunc, struct mlx4_priv, mfunc);
1689 struct mlx4_dev *dev = &priv->dev;
1699 bit_vec = master->comm_arm_bit_vector;
1700 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1701 vec = be32_to_cpu(bit_vec[i]);
1702 for (j = 0; j < 32; j++) {
1703 if (!(vec & (1 << j)))
1706 slave = (i * 32) + j;
1707 comm_cmd = swab32(readl(
1708 &mfunc->comm[slave].slave_write));
1709 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1711 toggle = comm_cmd >> 31;
1712 if (toggle != slt) {
1713 if (master->slave_state[slave].comm_toggle
1715 printk(KERN_INFO "slave %d out of sync."
1716 " read toggle %d, state toggle %d. "
1717 "Resynching.\n", slave, slt,
1718 master->slave_state[slave].comm_toggle);
1719 master->slave_state[slave].comm_toggle =
1722 mlx4_master_do_cmd(dev, slave,
1723 comm_cmd >> 16 & 0xff,
1724 comm_cmd & 0xffff, toggle);
1730 if (reported && reported != served)
1731 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1732 " but %d were served\n",
1735 if (mlx4_ARM_COMM_CHANNEL(dev))
1736 mlx4_warn(dev, "Failed to arm comm channel events\n");
1739 static int sync_toggles(struct mlx4_dev *dev)
1741 struct mlx4_priv *priv = mlx4_priv(dev);
1746 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1747 end = jiffies + msecs_to_jiffies(5000);
1749 while (time_before(jiffies, end)) {
1750 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1751 if (rd_toggle == wr_toggle) {
1752 priv->cmd.comm_toggle = rd_toggle;
1760 * we could reach here if for example the previous VM using this
1761 * function misbehaved and left the channel with unsynced state. We
1762 * should fix this here and give this VM a chance to use a properly
1765 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1766 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1767 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1768 priv->cmd.comm_toggle = 0;
1773 int mlx4_multi_func_init(struct mlx4_dev *dev)
1775 struct mlx4_priv *priv = mlx4_priv(dev);
1776 struct mlx4_slave_state *s_state;
1777 int i, j, err, port;
1779 if (mlx4_is_master(dev))
1781 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1782 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1785 ioremap(pci_resource_start(dev->pdev, 2) +
1786 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1787 if (!priv->mfunc.comm) {
1788 mlx4_err(dev, "Couldn't map communication vector.\n");
1792 if (mlx4_is_master(dev)) {
1793 priv->mfunc.master.slave_state =
1794 kzalloc(dev->num_slaves *
1795 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1796 if (!priv->mfunc.master.slave_state)
1799 priv->mfunc.master.vf_admin =
1800 kzalloc(dev->num_slaves *
1801 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1802 if (!priv->mfunc.master.vf_admin)
1803 goto err_comm_admin;
1805 priv->mfunc.master.vf_oper =
1806 kzalloc(dev->num_slaves *
1807 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1808 if (!priv->mfunc.master.vf_oper)
1811 for (i = 0; i < dev->num_slaves; ++i) {
1812 s_state = &priv->mfunc.master.slave_state[i];
1813 s_state->last_cmd = MLX4_COMM_CMD_RESET;
1814 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1815 s_state->event_eq[j].eqn = -1;
1816 __raw_writel((__force u32) 0,
1817 &priv->mfunc.comm[i].slave_write);
1818 __raw_writel((__force u32) 0,
1819 &priv->mfunc.comm[i].slave_read);
1821 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1822 s_state->vlan_filter[port] =
1823 kzalloc(sizeof(struct mlx4_vlan_fltr),
1825 if (!s_state->vlan_filter[port]) {
1827 kfree(s_state->vlan_filter[port]);
1830 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1831 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
1832 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
1833 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1834 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
1836 spin_lock_init(&s_state->lock);
1839 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
1840 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1841 INIT_WORK(&priv->mfunc.master.comm_work,
1842 mlx4_master_comm_channel);
1843 INIT_WORK(&priv->mfunc.master.slave_event_work,
1844 mlx4_gen_slave_eqe);
1845 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1846 mlx4_master_handle_slave_flr);
1847 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1848 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1849 priv->mfunc.master.comm_wq =
1850 create_singlethread_workqueue("mlx4_comm");
1851 if (!priv->mfunc.master.comm_wq)
1854 if (mlx4_init_resource_tracker(dev))
1857 err = mlx4_ARM_COMM_CHANNEL(dev);
1859 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1865 err = sync_toggles(dev);
1867 mlx4_err(dev, "Couldn't sync toggles\n");
1874 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1876 flush_workqueue(priv->mfunc.master.comm_wq);
1877 destroy_workqueue(priv->mfunc.master.comm_wq);
1880 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1881 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1883 kfree(priv->mfunc.master.vf_oper);
1885 kfree(priv->mfunc.master.vf_admin);
1887 kfree(priv->mfunc.master.slave_state);
1889 iounmap(priv->mfunc.comm);
1891 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1893 priv->mfunc.vhcr_dma);
1894 priv->mfunc.vhcr = NULL;
1898 int mlx4_cmd_init(struct mlx4_dev *dev)
1900 struct mlx4_priv *priv = mlx4_priv(dev);
1902 mutex_init(&priv->cmd.hcr_mutex);
1903 mutex_init(&priv->cmd.slave_cmd_mutex);
1904 sema_init(&priv->cmd.poll_sem, 1);
1905 priv->cmd.use_events = 0;
1906 priv->cmd.toggle = 1;
1908 priv->cmd.hcr = NULL;
1909 priv->mfunc.vhcr = NULL;
1911 if (!mlx4_is_slave(dev)) {
1912 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1913 MLX4_HCR_BASE, MLX4_HCR_SIZE);
1914 if (!priv->cmd.hcr) {
1915 mlx4_err(dev, "Couldn't map command register.\n");
1920 if (mlx4_is_mfunc(dev)) {
1921 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1922 &priv->mfunc.vhcr_dma,
1924 if (!priv->mfunc.vhcr)
1928 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1930 MLX4_MAILBOX_SIZE, 0);
1931 if (!priv->cmd.pool)
1937 if (mlx4_is_mfunc(dev))
1938 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1939 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1940 priv->mfunc.vhcr = NULL;
1943 if (!mlx4_is_slave(dev))
1944 iounmap(priv->cmd.hcr);
1948 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1950 struct mlx4_priv *priv = mlx4_priv(dev);
1953 if (mlx4_is_master(dev)) {
1954 flush_workqueue(priv->mfunc.master.comm_wq);
1955 destroy_workqueue(priv->mfunc.master.comm_wq);
1956 for (i = 0; i < dev->num_slaves; i++) {
1957 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1958 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1960 kfree(priv->mfunc.master.slave_state);
1961 kfree(priv->mfunc.master.vf_admin);
1962 kfree(priv->mfunc.master.vf_oper);
1965 iounmap(priv->mfunc.comm);
1968 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1970 struct mlx4_priv *priv = mlx4_priv(dev);
1972 pci_pool_destroy(priv->cmd.pool);
1974 if (!mlx4_is_slave(dev))
1975 iounmap(priv->cmd.hcr);
1976 if (mlx4_is_mfunc(dev))
1977 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1978 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1979 priv->mfunc.vhcr = NULL;
1983 * Switch to using events to issue FW commands (can only be called
1984 * after event queue for command events has been initialized).
1986 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1988 struct mlx4_priv *priv = mlx4_priv(dev);
1992 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
1993 sizeof (struct mlx4_cmd_context),
1995 if (!priv->cmd.context)
1998 for (i = 0; i < priv->cmd.max_cmds; ++i) {
1999 priv->cmd.context[i].token = i;
2000 priv->cmd.context[i].next = i + 1;
2003 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2004 priv->cmd.free_head = 0;
2006 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2007 spin_lock_init(&priv->cmd.context_lock);
2009 for (priv->cmd.token_mask = 1;
2010 priv->cmd.token_mask < priv->cmd.max_cmds;
2011 priv->cmd.token_mask <<= 1)
2013 --priv->cmd.token_mask;
2015 down(&priv->cmd.poll_sem);
2016 priv->cmd.use_events = 1;
2022 * Switch back to polling (used when shutting down the device)
2024 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2026 struct mlx4_priv *priv = mlx4_priv(dev);
2029 priv->cmd.use_events = 0;
2031 for (i = 0; i < priv->cmd.max_cmds; ++i)
2032 down(&priv->cmd.event_sem);
2034 kfree(priv->cmd.context);
2036 up(&priv->cmd.poll_sem);
2039 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2041 struct mlx4_cmd_mailbox *mailbox;
2043 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2045 return ERR_PTR(-ENOMEM);
2047 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2049 if (!mailbox->buf) {
2051 return ERR_PTR(-ENOMEM);
2056 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2058 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2059 struct mlx4_cmd_mailbox *mailbox)
2064 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2067 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2069 u32 mlx4_comm_get_version(void)
2071 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2074 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2076 if ((vf < 0) || (vf >= dev->num_vfs)) {
2077 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2084 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2086 struct mlx4_priv *priv = mlx4_priv(dev);
2087 struct mlx4_vport_state *s_info;
2090 if (!mlx4_is_master(dev))
2091 return -EPROTONOSUPPORT;
2093 slave = mlx4_get_slave_indx(dev, vf);
2097 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2099 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2100 vf, port, s_info->mac);
2103 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2105 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2107 struct mlx4_priv *priv = mlx4_priv(dev);
2108 struct mlx4_vport_state *s_info;
2111 if ((!mlx4_is_master(dev)) ||
2112 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2113 return -EPROTONOSUPPORT;
2115 if ((vlan > 4095) || (qos > 7))
2118 slave = mlx4_get_slave_indx(dev, vf);
2122 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2123 if ((0 == vlan) && (0 == qos))
2124 s_info->default_vlan = MLX4_VGT;
2126 s_info->default_vlan = vlan;
2127 s_info->default_qos = qos;
2130 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2132 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2134 struct mlx4_priv *priv = mlx4_priv(dev);
2135 struct mlx4_vport_state *s_info;
2138 if ((!mlx4_is_master(dev)) ||
2139 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2140 return -EPROTONOSUPPORT;
2142 slave = mlx4_get_slave_indx(dev, vf);
2146 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2147 s_info->spoofchk = setting;
2151 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2153 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2155 struct mlx4_priv *priv = mlx4_priv(dev);
2156 struct mlx4_vport_state *s_info;
2159 if (!mlx4_is_master(dev))
2160 return -EPROTONOSUPPORT;
2162 slave = mlx4_get_slave_indx(dev, vf);
2166 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2169 /* need to convert it to a func */
2170 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2171 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2172 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2173 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2174 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2175 ivf->mac[5] = ((s_info->mac) & 0xff);
2177 ivf->vlan = s_info->default_vlan;
2178 ivf->qos = s_info->default_qos;
2179 ivf->tx_rate = s_info->tx_rate;
2180 ivf->spoofchk = s_info->spoofchk;
2184 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);