2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/sched.h>
43 #include <linux/seq_file.h>
44 #include <linux/mii.h>
45 #include <linux/slab.h>
46 #include <linux/dmi.h>
47 #include <linux/prefetch.h>
52 #define DRV_NAME "skge"
53 #define DRV_VERSION "1.14"
55 #define DEFAULT_TX_RING_SIZE 128
56 #define DEFAULT_RX_RING_SIZE 512
57 #define MAX_TX_RING_SIZE 1024
58 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
59 #define MAX_RX_RING_SIZE 4096
60 #define RX_COPY_THRESHOLD 128
61 #define RX_BUF_SIZE 1536
62 #define PHY_RETRIES 1000
63 #define ETH_JUMBO_MTU 9000
64 #define TX_WATCHDOG (5 * HZ)
65 #define NAPI_WEIGHT 64
69 #define SKGE_EEPROM_MAGIC 0x9933aabb
72 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
73 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
74 MODULE_LICENSE("GPL");
75 MODULE_VERSION(DRV_VERSION);
77 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
78 NETIF_MSG_LINK | NETIF_MSG_IFUP |
81 static int debug = -1; /* defaults above */
82 module_param(debug, int, 0);
83 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
85 static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
88 #ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
91 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
94 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
95 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
96 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
97 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
98 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
99 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
102 MODULE_DEVICE_TABLE(pci, skge_id_table);
104 static int skge_up(struct net_device *dev);
105 static int skge_down(struct net_device *dev);
106 static void skge_phy_reset(struct skge_port *skge);
107 static void skge_tx_clean(struct net_device *dev);
108 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
110 static void genesis_get_stats(struct skge_port *skge, u64 *data);
111 static void yukon_get_stats(struct skge_port *skge, u64 *data);
112 static void yukon_init(struct skge_hw *hw, int port);
113 static void genesis_mac_init(struct skge_hw *hw, int port);
114 static void genesis_link_up(struct skge_port *skge);
115 static void skge_set_multicast(struct net_device *dev);
116 static irqreturn_t skge_intr(int irq, void *dev_id);
118 /* Avoid conditionals by using array */
119 static const int txqaddr[] = { Q_XA1, Q_XA2 };
120 static const int rxqaddr[] = { Q_R1, Q_R2 };
121 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
122 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
123 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
124 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
126 static inline bool is_genesis(const struct skge_hw *hw)
128 #ifdef CONFIG_SKGE_GENESIS
129 return hw->chip_id == CHIP_ID_GENESIS;
135 static int skge_get_regs_len(struct net_device *dev)
141 * Returns copy of whole control register region
142 * Note: skip RAM address register because accessing it will
145 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
148 const struct skge_port *skge = netdev_priv(dev);
149 const void __iomem *io = skge->hw->regs;
152 memset(p, 0, regs->len);
153 memcpy_fromio(p, io, B3_RAM_ADDR);
155 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
156 regs->len - B3_RI_WTO_R1);
159 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
160 static u32 wol_supported(const struct skge_hw *hw)
165 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
168 return WAKE_MAGIC | WAKE_PHY;
171 static void skge_wol_init(struct skge_port *skge)
173 struct skge_hw *hw = skge->hw;
174 int port = skge->port;
177 skge_write16(hw, B0_CTST, CS_RST_CLR);
178 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
181 skge_write8(hw, B0_POWER_CTRL,
182 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
184 /* WA code for COMA mode -- clear PHY reset */
185 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
186 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
187 u32 reg = skge_read32(hw, B2_GP_IO);
190 skge_write32(hw, B2_GP_IO, reg);
193 skge_write32(hw, SK_REG(port, GPHY_CTRL),
195 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
196 GPC_ANEG_1 | GPC_RST_SET);
198 skge_write32(hw, SK_REG(port, GPHY_CTRL),
200 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
201 GPC_ANEG_1 | GPC_RST_CLR);
203 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
205 /* Force to 10/100 skge_reset will re-enable on resume */
206 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
207 (PHY_AN_100FULL | PHY_AN_100HALF |
208 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
210 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
211 gm_phy_write(hw, port, PHY_MARV_CTRL,
212 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
213 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
216 /* Set GMAC to no flow control and auto update for speed/duplex */
217 gma_write16(hw, port, GM_GP_CTRL,
218 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
219 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
221 /* Set WOL address */
222 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
223 skge->netdev->dev_addr, ETH_ALEN);
225 /* Turn on appropriate WOL control bits */
226 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
228 if (skge->wol & WAKE_PHY)
229 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
231 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
233 if (skge->wol & WAKE_MAGIC)
234 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
236 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
238 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
239 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
242 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
245 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
247 struct skge_port *skge = netdev_priv(dev);
249 wol->supported = wol_supported(skge->hw);
250 wol->wolopts = skge->wol;
253 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
255 struct skge_port *skge = netdev_priv(dev);
256 struct skge_hw *hw = skge->hw;
258 if ((wol->wolopts & ~wol_supported(hw)) ||
259 !device_can_wakeup(&hw->pdev->dev))
262 skge->wol = wol->wolopts;
264 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
269 /* Determine supported/advertised modes based on hardware.
270 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
272 static u32 skge_supported_modes(const struct skge_hw *hw)
277 supported = (SUPPORTED_10baseT_Half |
278 SUPPORTED_10baseT_Full |
279 SUPPORTED_100baseT_Half |
280 SUPPORTED_100baseT_Full |
281 SUPPORTED_1000baseT_Half |
282 SUPPORTED_1000baseT_Full |
287 supported &= ~(SUPPORTED_10baseT_Half |
288 SUPPORTED_10baseT_Full |
289 SUPPORTED_100baseT_Half |
290 SUPPORTED_100baseT_Full);
292 else if (hw->chip_id == CHIP_ID_YUKON)
293 supported &= ~SUPPORTED_1000baseT_Half;
295 supported = (SUPPORTED_1000baseT_Full |
296 SUPPORTED_1000baseT_Half |
303 static int skge_get_settings(struct net_device *dev,
304 struct ethtool_cmd *ecmd)
306 struct skge_port *skge = netdev_priv(dev);
307 struct skge_hw *hw = skge->hw;
309 ecmd->transceiver = XCVR_INTERNAL;
310 ecmd->supported = skge_supported_modes(hw);
313 ecmd->port = PORT_TP;
314 ecmd->phy_address = hw->phy_addr;
316 ecmd->port = PORT_FIBRE;
318 ecmd->advertising = skge->advertising;
319 ecmd->autoneg = skge->autoneg;
320 ethtool_cmd_speed_set(ecmd, skge->speed);
321 ecmd->duplex = skge->duplex;
325 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
327 struct skge_port *skge = netdev_priv(dev);
328 const struct skge_hw *hw = skge->hw;
329 u32 supported = skge_supported_modes(hw);
332 if (ecmd->autoneg == AUTONEG_ENABLE) {
333 ecmd->advertising = supported;
338 u32 speed = ethtool_cmd_speed(ecmd);
342 if (ecmd->duplex == DUPLEX_FULL)
343 setting = SUPPORTED_1000baseT_Full;
344 else if (ecmd->duplex == DUPLEX_HALF)
345 setting = SUPPORTED_1000baseT_Half;
350 if (ecmd->duplex == DUPLEX_FULL)
351 setting = SUPPORTED_100baseT_Full;
352 else if (ecmd->duplex == DUPLEX_HALF)
353 setting = SUPPORTED_100baseT_Half;
359 if (ecmd->duplex == DUPLEX_FULL)
360 setting = SUPPORTED_10baseT_Full;
361 else if (ecmd->duplex == DUPLEX_HALF)
362 setting = SUPPORTED_10baseT_Half;
370 if ((setting & supported) == 0)
374 skge->duplex = ecmd->duplex;
377 skge->autoneg = ecmd->autoneg;
378 skge->advertising = ecmd->advertising;
380 if (netif_running(dev)) {
392 static void skge_get_drvinfo(struct net_device *dev,
393 struct ethtool_drvinfo *info)
395 struct skge_port *skge = netdev_priv(dev);
397 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
398 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
399 strlcpy(info->bus_info, pci_name(skge->hw->pdev),
400 sizeof(info->bus_info));
403 static const struct skge_stat {
404 char name[ETH_GSTRING_LEN];
408 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
409 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
411 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
412 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
413 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
414 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
415 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
416 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
417 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
418 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
420 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
421 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
422 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
423 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
424 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
425 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
427 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
428 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
429 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
430 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
431 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
434 static int skge_get_sset_count(struct net_device *dev, int sset)
438 return ARRAY_SIZE(skge_stats);
444 static void skge_get_ethtool_stats(struct net_device *dev,
445 struct ethtool_stats *stats, u64 *data)
447 struct skge_port *skge = netdev_priv(dev);
449 if (is_genesis(skge->hw))
450 genesis_get_stats(skge, data);
452 yukon_get_stats(skge, data);
455 /* Use hardware MIB variables for critical path statistics and
456 * transmit feedback not reported at interrupt.
457 * Other errors are accounted for in interrupt handler.
459 static struct net_device_stats *skge_get_stats(struct net_device *dev)
461 struct skge_port *skge = netdev_priv(dev);
462 u64 data[ARRAY_SIZE(skge_stats)];
464 if (is_genesis(skge->hw))
465 genesis_get_stats(skge, data);
467 yukon_get_stats(skge, data);
469 dev->stats.tx_bytes = data[0];
470 dev->stats.rx_bytes = data[1];
471 dev->stats.tx_packets = data[2] + data[4] + data[6];
472 dev->stats.rx_packets = data[3] + data[5] + data[7];
473 dev->stats.multicast = data[3] + data[5];
474 dev->stats.collisions = data[10];
475 dev->stats.tx_aborted_errors = data[12];
480 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
486 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
487 memcpy(data + i * ETH_GSTRING_LEN,
488 skge_stats[i].name, ETH_GSTRING_LEN);
493 static void skge_get_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
496 struct skge_port *skge = netdev_priv(dev);
498 p->rx_max_pending = MAX_RX_RING_SIZE;
499 p->tx_max_pending = MAX_TX_RING_SIZE;
501 p->rx_pending = skge->rx_ring.count;
502 p->tx_pending = skge->tx_ring.count;
505 static int skge_set_ring_param(struct net_device *dev,
506 struct ethtool_ringparam *p)
508 struct skge_port *skge = netdev_priv(dev);
511 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
512 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
515 skge->rx_ring.count = p->rx_pending;
516 skge->tx_ring.count = p->tx_pending;
518 if (netif_running(dev)) {
528 static u32 skge_get_msglevel(struct net_device *netdev)
530 struct skge_port *skge = netdev_priv(netdev);
531 return skge->msg_enable;
534 static void skge_set_msglevel(struct net_device *netdev, u32 value)
536 struct skge_port *skge = netdev_priv(netdev);
537 skge->msg_enable = value;
540 static int skge_nway_reset(struct net_device *dev)
542 struct skge_port *skge = netdev_priv(dev);
544 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
547 skge_phy_reset(skge);
551 static void skge_get_pauseparam(struct net_device *dev,
552 struct ethtool_pauseparam *ecmd)
554 struct skge_port *skge = netdev_priv(dev);
556 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
557 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
558 ecmd->tx_pause = (ecmd->rx_pause ||
559 (skge->flow_control == FLOW_MODE_LOC_SEND));
561 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
564 static int skge_set_pauseparam(struct net_device *dev,
565 struct ethtool_pauseparam *ecmd)
567 struct skge_port *skge = netdev_priv(dev);
568 struct ethtool_pauseparam old;
571 skge_get_pauseparam(dev, &old);
573 if (ecmd->autoneg != old.autoneg)
574 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
576 if (ecmd->rx_pause && ecmd->tx_pause)
577 skge->flow_control = FLOW_MODE_SYMMETRIC;
578 else if (ecmd->rx_pause && !ecmd->tx_pause)
579 skge->flow_control = FLOW_MODE_SYM_OR_REM;
580 else if (!ecmd->rx_pause && ecmd->tx_pause)
581 skge->flow_control = FLOW_MODE_LOC_SEND;
583 skge->flow_control = FLOW_MODE_NONE;
586 if (netif_running(dev)) {
598 /* Chip internal frequency for clock calculations */
599 static inline u32 hwkhz(const struct skge_hw *hw)
601 return is_genesis(hw) ? 53125 : 78125;
604 /* Chip HZ to microseconds */
605 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
607 return (ticks * 1000) / hwkhz(hw);
610 /* Microseconds to chip HZ */
611 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
613 return hwkhz(hw) * usec / 1000;
616 static int skge_get_coalesce(struct net_device *dev,
617 struct ethtool_coalesce *ecmd)
619 struct skge_port *skge = netdev_priv(dev);
620 struct skge_hw *hw = skge->hw;
621 int port = skge->port;
623 ecmd->rx_coalesce_usecs = 0;
624 ecmd->tx_coalesce_usecs = 0;
626 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
627 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
628 u32 msk = skge_read32(hw, B2_IRQM_MSK);
630 if (msk & rxirqmask[port])
631 ecmd->rx_coalesce_usecs = delay;
632 if (msk & txirqmask[port])
633 ecmd->tx_coalesce_usecs = delay;
639 /* Note: interrupt timer is per board, but can turn on/off per port */
640 static int skge_set_coalesce(struct net_device *dev,
641 struct ethtool_coalesce *ecmd)
643 struct skge_port *skge = netdev_priv(dev);
644 struct skge_hw *hw = skge->hw;
645 int port = skge->port;
646 u32 msk = skge_read32(hw, B2_IRQM_MSK);
649 if (ecmd->rx_coalesce_usecs == 0)
650 msk &= ~rxirqmask[port];
651 else if (ecmd->rx_coalesce_usecs < 25 ||
652 ecmd->rx_coalesce_usecs > 33333)
655 msk |= rxirqmask[port];
656 delay = ecmd->rx_coalesce_usecs;
659 if (ecmd->tx_coalesce_usecs == 0)
660 msk &= ~txirqmask[port];
661 else if (ecmd->tx_coalesce_usecs < 25 ||
662 ecmd->tx_coalesce_usecs > 33333)
665 msk |= txirqmask[port];
666 delay = min(delay, ecmd->rx_coalesce_usecs);
669 skge_write32(hw, B2_IRQM_MSK, msk);
671 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
674 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
679 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
680 static void skge_led(struct skge_port *skge, enum led_mode mode)
682 struct skge_hw *hw = skge->hw;
683 int port = skge->port;
685 spin_lock_bh(&hw->phy_lock);
686 if (is_genesis(hw)) {
689 if (hw->phy_type == SK_PHY_BCOM)
690 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
692 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
693 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
695 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
696 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
697 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
701 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
705 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
710 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
711 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
714 if (hw->phy_type == SK_PHY_BCOM)
715 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
717 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
718 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
719 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
726 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
727 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
728 PHY_M_LED_MO_DUP(MO_LED_OFF) |
729 PHY_M_LED_MO_10(MO_LED_OFF) |
730 PHY_M_LED_MO_100(MO_LED_OFF) |
731 PHY_M_LED_MO_1000(MO_LED_OFF) |
732 PHY_M_LED_MO_RX(MO_LED_OFF));
735 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
736 PHY_M_LED_PULS_DUR(PULS_170MS) |
737 PHY_M_LED_BLINK_RT(BLINK_84MS) |
741 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
742 PHY_M_LED_MO_RX(MO_LED_OFF) |
743 (skge->speed == SPEED_100 ?
744 PHY_M_LED_MO_100(MO_LED_ON) : 0));
747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
749 PHY_M_LED_MO_DUP(MO_LED_ON) |
750 PHY_M_LED_MO_10(MO_LED_ON) |
751 PHY_M_LED_MO_100(MO_LED_ON) |
752 PHY_M_LED_MO_1000(MO_LED_ON) |
753 PHY_M_LED_MO_RX(MO_LED_ON));
756 spin_unlock_bh(&hw->phy_lock);
759 /* blink LED's for finding board */
760 static int skge_set_phys_id(struct net_device *dev,
761 enum ethtool_phys_id_state state)
763 struct skge_port *skge = netdev_priv(dev);
766 case ETHTOOL_ID_ACTIVE:
767 return 2; /* cycle on/off twice per second */
770 skge_led(skge, LED_MODE_TST);
774 skge_led(skge, LED_MODE_OFF);
777 case ETHTOOL_ID_INACTIVE:
778 /* back to regular LED state */
779 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
785 static int skge_get_eeprom_len(struct net_device *dev)
787 struct skge_port *skge = netdev_priv(dev);
790 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
791 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
794 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
798 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
801 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
802 } while (!(offset & PCI_VPD_ADDR_F));
804 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
808 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
810 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
811 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
812 offset | PCI_VPD_ADDR_F);
815 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
816 } while (offset & PCI_VPD_ADDR_F);
819 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
822 struct skge_port *skge = netdev_priv(dev);
823 struct pci_dev *pdev = skge->hw->pdev;
824 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
825 int length = eeprom->len;
826 u16 offset = eeprom->offset;
831 eeprom->magic = SKGE_EEPROM_MAGIC;
834 u32 val = skge_vpd_read(pdev, cap, offset);
835 int n = min_t(int, length, sizeof(val));
837 memcpy(data, &val, n);
845 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
848 struct skge_port *skge = netdev_priv(dev);
849 struct pci_dev *pdev = skge->hw->pdev;
850 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
851 int length = eeprom->len;
852 u16 offset = eeprom->offset;
857 if (eeprom->magic != SKGE_EEPROM_MAGIC)
862 int n = min_t(int, length, sizeof(val));
865 val = skge_vpd_read(pdev, cap, offset);
866 memcpy(&val, data, n);
868 skge_vpd_write(pdev, cap, offset, val);
877 static const struct ethtool_ops skge_ethtool_ops = {
878 .get_settings = skge_get_settings,
879 .set_settings = skge_set_settings,
880 .get_drvinfo = skge_get_drvinfo,
881 .get_regs_len = skge_get_regs_len,
882 .get_regs = skge_get_regs,
883 .get_wol = skge_get_wol,
884 .set_wol = skge_set_wol,
885 .get_msglevel = skge_get_msglevel,
886 .set_msglevel = skge_set_msglevel,
887 .nway_reset = skge_nway_reset,
888 .get_link = ethtool_op_get_link,
889 .get_eeprom_len = skge_get_eeprom_len,
890 .get_eeprom = skge_get_eeprom,
891 .set_eeprom = skge_set_eeprom,
892 .get_ringparam = skge_get_ring_param,
893 .set_ringparam = skge_set_ring_param,
894 .get_pauseparam = skge_get_pauseparam,
895 .set_pauseparam = skge_set_pauseparam,
896 .get_coalesce = skge_get_coalesce,
897 .set_coalesce = skge_set_coalesce,
898 .get_strings = skge_get_strings,
899 .set_phys_id = skge_set_phys_id,
900 .get_sset_count = skge_get_sset_count,
901 .get_ethtool_stats = skge_get_ethtool_stats,
905 * Allocate ring elements and chain them together
906 * One-to-one association of board descriptors with ring elements
908 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
910 struct skge_tx_desc *d;
911 struct skge_element *e;
914 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
918 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
920 if (i == ring->count - 1) {
921 e->next = ring->start;
922 d->next_offset = base;
925 d->next_offset = base + (i+1) * sizeof(*d);
928 ring->to_use = ring->to_clean = ring->start;
933 /* Allocate and setup a new buffer for receiving */
934 static int skge_rx_setup(struct pci_dev *pdev,
935 struct skge_element *e,
936 struct sk_buff *skb, unsigned int bufsize)
938 struct skge_rx_desc *rd = e->desc;
941 map = pci_map_single(pdev, skb->data, bufsize,
943 if (pci_dma_mapping_error(pdev, map))
946 rd->dma_lo = lower_32_bits(map);
947 rd->dma_hi = upper_32_bits(map);
949 rd->csum1_start = ETH_HLEN;
950 rd->csum2_start = ETH_HLEN;
956 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
957 dma_unmap_addr_set(e, mapaddr, map);
958 dma_unmap_len_set(e, maplen, bufsize);
963 dev_warn(&pdev->dev, "%s: rx mapping error\n",
968 /* Resume receiving using existing skb,
969 * Note: DMA address is not changed by chip.
970 * MTU not changed while receiver active.
972 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
974 struct skge_rx_desc *rd = e->desc;
977 rd->csum2_start = ETH_HLEN;
981 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
985 /* Free all buffers in receive ring, assumes receiver stopped */
986 static void skge_rx_clean(struct skge_port *skge)
988 struct skge_hw *hw = skge->hw;
989 struct skge_ring *ring = &skge->rx_ring;
990 struct skge_element *e;
994 struct skge_rx_desc *rd = e->desc;
997 pci_unmap_single(hw->pdev,
998 dma_unmap_addr(e, mapaddr),
999 dma_unmap_len(e, maplen),
1000 PCI_DMA_FROMDEVICE);
1001 dev_kfree_skb(e->skb);
1004 } while ((e = e->next) != ring->start);
1008 /* Allocate buffers for receive ring
1009 * For receive: to_clean is next received frame.
1011 static int skge_rx_fill(struct net_device *dev)
1013 struct skge_port *skge = netdev_priv(dev);
1014 struct skge_ring *ring = &skge->rx_ring;
1015 struct skge_element *e;
1019 struct sk_buff *skb;
1021 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1026 skb_reserve(skb, NET_IP_ALIGN);
1027 if (skge_rx_setup(skge->hw->pdev, e, skb, skge->rx_buf_size)) {
1032 } while ((e = e->next) != ring->start);
1034 ring->to_clean = ring->start;
1038 static const char *skge_pause(enum pause_status status)
1041 case FLOW_STAT_NONE:
1043 case FLOW_STAT_REM_SEND:
1045 case FLOW_STAT_LOC_SEND:
1047 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1050 return "indeterminated";
1055 static void skge_link_up(struct skge_port *skge)
1057 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1058 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1060 netif_carrier_on(skge->netdev);
1061 netif_wake_queue(skge->netdev);
1063 netif_info(skge, link, skge->netdev,
1064 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1066 skge->duplex == DUPLEX_FULL ? "full" : "half",
1067 skge_pause(skge->flow_status));
1070 static void skge_link_down(struct skge_port *skge)
1072 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1073 netif_carrier_off(skge->netdev);
1074 netif_stop_queue(skge->netdev);
1076 netif_info(skge, link, skge->netdev, "Link is down\n");
1079 static void xm_link_down(struct skge_hw *hw, int port)
1081 struct net_device *dev = hw->dev[port];
1082 struct skge_port *skge = netdev_priv(dev);
1084 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1086 if (netif_carrier_ok(dev))
1087 skge_link_down(skge);
1090 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1094 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1095 *val = xm_read16(hw, port, XM_PHY_DATA);
1097 if (hw->phy_type == SK_PHY_XMAC)
1100 for (i = 0; i < PHY_RETRIES; i++) {
1101 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1108 *val = xm_read16(hw, port, XM_PHY_DATA);
1113 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1116 if (__xm_phy_read(hw, port, reg, &v))
1117 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
1121 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1125 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1126 for (i = 0; i < PHY_RETRIES; i++) {
1127 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1134 xm_write16(hw, port, XM_PHY_DATA, val);
1135 for (i = 0; i < PHY_RETRIES; i++) {
1136 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1143 static void genesis_init(struct skge_hw *hw)
1145 /* set blink source counter */
1146 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1147 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1149 /* configure mac arbiter */
1150 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1152 /* configure mac arbiter timeout values */
1153 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1154 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1155 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1156 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1158 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1159 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1160 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1161 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1163 /* configure packet arbiter timeout */
1164 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1165 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1166 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1167 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1168 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1171 static void genesis_reset(struct skge_hw *hw, int port)
1173 static const u8 zero[8] = { 0 };
1176 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1178 /* reset the statistics module */
1179 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1180 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1181 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1182 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1183 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1185 /* disable Broadcom PHY IRQ */
1186 if (hw->phy_type == SK_PHY_BCOM)
1187 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1189 xm_outhash(hw, port, XM_HSM, zero);
1191 /* Flush TX and RX fifo */
1192 reg = xm_read32(hw, port, XM_MODE);
1193 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1194 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1197 /* Convert mode to MII values */
1198 static const u16 phy_pause_map[] = {
1199 [FLOW_MODE_NONE] = 0,
1200 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1201 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1202 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1205 /* special defines for FIBER (88E1011S only) */
1206 static const u16 fiber_pause_map[] = {
1207 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1208 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1209 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1210 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1214 /* Check status of Broadcom phy link */
1215 static void bcom_check_link(struct skge_hw *hw, int port)
1217 struct net_device *dev = hw->dev[port];
1218 struct skge_port *skge = netdev_priv(dev);
1221 /* read twice because of latch */
1222 xm_phy_read(hw, port, PHY_BCOM_STAT);
1223 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1225 if ((status & PHY_ST_LSYNC) == 0) {
1226 xm_link_down(hw, port);
1230 if (skge->autoneg == AUTONEG_ENABLE) {
1233 if (!(status & PHY_ST_AN_OVER))
1236 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1237 if (lpa & PHY_B_AN_RF) {
1238 netdev_notice(dev, "remote fault\n");
1242 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1244 /* Check Duplex mismatch */
1245 switch (aux & PHY_B_AS_AN_RES_MSK) {
1246 case PHY_B_RES_1000FD:
1247 skge->duplex = DUPLEX_FULL;
1249 case PHY_B_RES_1000HD:
1250 skge->duplex = DUPLEX_HALF;
1253 netdev_notice(dev, "duplex mismatch\n");
1257 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1258 switch (aux & PHY_B_AS_PAUSE_MSK) {
1259 case PHY_B_AS_PAUSE_MSK:
1260 skge->flow_status = FLOW_STAT_SYMMETRIC;
1263 skge->flow_status = FLOW_STAT_REM_SEND;
1266 skge->flow_status = FLOW_STAT_LOC_SEND;
1269 skge->flow_status = FLOW_STAT_NONE;
1271 skge->speed = SPEED_1000;
1274 if (!netif_carrier_ok(dev))
1275 genesis_link_up(skge);
1278 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1279 * Phy on for 100 or 10Mbit operation
1281 static void bcom_phy_init(struct skge_port *skge)
1283 struct skge_hw *hw = skge->hw;
1284 int port = skge->port;
1286 u16 id1, r, ext, ctl;
1288 /* magic workaround patterns for Broadcom */
1289 static const struct {
1293 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1294 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1295 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1296 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1298 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1299 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1302 /* read Id from external PHY (all have the same address) */
1303 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1305 /* Optimize MDIO transfer by suppressing preamble. */
1306 r = xm_read16(hw, port, XM_MMU_CMD);
1308 xm_write16(hw, port, XM_MMU_CMD, r);
1311 case PHY_BCOM_ID1_C0:
1313 * Workaround BCOM Errata for the C0 type.
1314 * Write magic patterns to reserved registers.
1316 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1317 xm_phy_write(hw, port,
1318 C0hack[i].reg, C0hack[i].val);
1321 case PHY_BCOM_ID1_A1:
1323 * Workaround BCOM Errata for the A1 type.
1324 * Write magic patterns to reserved registers.
1326 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1327 xm_phy_write(hw, port,
1328 A1hack[i].reg, A1hack[i].val);
1333 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1334 * Disable Power Management after reset.
1336 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1337 r |= PHY_B_AC_DIS_PM;
1338 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1341 xm_read16(hw, port, XM_ISRC);
1343 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1344 ctl = PHY_CT_SP1000; /* always 1000mbit */
1346 if (skge->autoneg == AUTONEG_ENABLE) {
1348 * Workaround BCOM Errata #1 for the C5 type.
1349 * 1000Base-T Link Acquisition Failure in Slave Mode
1350 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1352 u16 adv = PHY_B_1000C_RD;
1353 if (skge->advertising & ADVERTISED_1000baseT_Half)
1354 adv |= PHY_B_1000C_AHD;
1355 if (skge->advertising & ADVERTISED_1000baseT_Full)
1356 adv |= PHY_B_1000C_AFD;
1357 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1359 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1361 if (skge->duplex == DUPLEX_FULL)
1362 ctl |= PHY_CT_DUP_MD;
1363 /* Force to slave */
1364 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1367 /* Set autonegotiation pause parameters */
1368 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1369 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1371 /* Handle Jumbo frames */
1372 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1373 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1374 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1376 ext |= PHY_B_PEC_HIGH_LA;
1380 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1381 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1383 /* Use link status change interrupt */
1384 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1387 static void xm_phy_init(struct skge_port *skge)
1389 struct skge_hw *hw = skge->hw;
1390 int port = skge->port;
1393 if (skge->autoneg == AUTONEG_ENABLE) {
1394 if (skge->advertising & ADVERTISED_1000baseT_Half)
1395 ctrl |= PHY_X_AN_HD;
1396 if (skge->advertising & ADVERTISED_1000baseT_Full)
1397 ctrl |= PHY_X_AN_FD;
1399 ctrl |= fiber_pause_map[skge->flow_control];
1401 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1403 /* Restart Auto-negotiation */
1404 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1406 /* Set DuplexMode in Config register */
1407 if (skge->duplex == DUPLEX_FULL)
1408 ctrl |= PHY_CT_DUP_MD;
1410 * Do NOT enable Auto-negotiation here. This would hold
1411 * the link down because no IDLEs are transmitted
1415 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1417 /* Poll PHY for status changes */
1418 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1421 static int xm_check_link(struct net_device *dev)
1423 struct skge_port *skge = netdev_priv(dev);
1424 struct skge_hw *hw = skge->hw;
1425 int port = skge->port;
1428 /* read twice because of latch */
1429 xm_phy_read(hw, port, PHY_XMAC_STAT);
1430 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1432 if ((status & PHY_ST_LSYNC) == 0) {
1433 xm_link_down(hw, port);
1437 if (skge->autoneg == AUTONEG_ENABLE) {
1440 if (!(status & PHY_ST_AN_OVER))
1443 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1444 if (lpa & PHY_B_AN_RF) {
1445 netdev_notice(dev, "remote fault\n");
1449 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1451 /* Check Duplex mismatch */
1452 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1454 skge->duplex = DUPLEX_FULL;
1457 skge->duplex = DUPLEX_HALF;
1460 netdev_notice(dev, "duplex mismatch\n");
1464 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1465 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1466 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1467 (lpa & PHY_X_P_SYM_MD))
1468 skge->flow_status = FLOW_STAT_SYMMETRIC;
1469 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1470 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1471 /* Enable PAUSE receive, disable PAUSE transmit */
1472 skge->flow_status = FLOW_STAT_REM_SEND;
1473 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1474 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1475 /* Disable PAUSE receive, enable PAUSE transmit */
1476 skge->flow_status = FLOW_STAT_LOC_SEND;
1478 skge->flow_status = FLOW_STAT_NONE;
1480 skge->speed = SPEED_1000;
1483 if (!netif_carrier_ok(dev))
1484 genesis_link_up(skge);
1488 /* Poll to check for link coming up.
1490 * Since internal PHY is wired to a level triggered pin, can't
1491 * get an interrupt when carrier is detected, need to poll for
1494 static void xm_link_timer(unsigned long arg)
1496 struct skge_port *skge = (struct skge_port *) arg;
1497 struct net_device *dev = skge->netdev;
1498 struct skge_hw *hw = skge->hw;
1499 int port = skge->port;
1501 unsigned long flags;
1503 if (!netif_running(dev))
1506 spin_lock_irqsave(&hw->phy_lock, flags);
1509 * Verify that the link by checking GPIO register three times.
1510 * This pin has the signal from the link_sync pin connected to it.
1512 for (i = 0; i < 3; i++) {
1513 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1517 /* Re-enable interrupt to detect link down */
1518 if (xm_check_link(dev)) {
1519 u16 msk = xm_read16(hw, port, XM_IMSK);
1520 msk &= ~XM_IS_INP_ASS;
1521 xm_write16(hw, port, XM_IMSK, msk);
1522 xm_read16(hw, port, XM_ISRC);
1525 mod_timer(&skge->link_timer,
1526 round_jiffies(jiffies + LINK_HZ));
1528 spin_unlock_irqrestore(&hw->phy_lock, flags);
1531 static void genesis_mac_init(struct skge_hw *hw, int port)
1533 struct net_device *dev = hw->dev[port];
1534 struct skge_port *skge = netdev_priv(dev);
1535 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1538 static const u8 zero[6] = { 0 };
1540 for (i = 0; i < 10; i++) {
1541 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1543 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1548 netdev_warn(dev, "genesis reset failed\n");
1551 /* Unreset the XMAC. */
1552 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1555 * Perform additional initialization for external PHYs,
1556 * namely for the 1000baseTX cards that use the XMAC's
1559 if (hw->phy_type != SK_PHY_XMAC) {
1560 /* Take external Phy out of reset */
1561 r = skge_read32(hw, B2_GP_IO);
1563 r |= GP_DIR_0|GP_IO_0;
1565 r |= GP_DIR_2|GP_IO_2;
1567 skge_write32(hw, B2_GP_IO, r);
1569 /* Enable GMII interface */
1570 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1574 switch (hw->phy_type) {
1579 bcom_phy_init(skge);
1580 bcom_check_link(hw, port);
1583 /* Set Station Address */
1584 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1586 /* We don't use match addresses so clear */
1587 for (i = 1; i < 16; i++)
1588 xm_outaddr(hw, port, XM_EXM(i), zero);
1590 /* Clear MIB counters */
1591 xm_write16(hw, port, XM_STAT_CMD,
1592 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1593 /* Clear two times according to Errata #3 */
1594 xm_write16(hw, port, XM_STAT_CMD,
1595 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1597 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1598 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1600 /* We don't need the FCS appended to the packet. */
1601 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1603 r |= XM_RX_BIG_PK_OK;
1605 if (skge->duplex == DUPLEX_HALF) {
1607 * If in manual half duplex mode the other side might be in
1608 * full duplex mode, so ignore if a carrier extension is not seen
1609 * on frames received
1611 r |= XM_RX_DIS_CEXT;
1613 xm_write16(hw, port, XM_RX_CMD, r);
1615 /* We want short frames padded to 60 bytes. */
1616 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1618 /* Increase threshold for jumbo frames on dual port */
1619 if (hw->ports > 1 && jumbo)
1620 xm_write16(hw, port, XM_TX_THR, 1020);
1622 xm_write16(hw, port, XM_TX_THR, 512);
1625 * Enable the reception of all error frames. This is is
1626 * a necessary evil due to the design of the XMAC. The
1627 * XMAC's receive FIFO is only 8K in size, however jumbo
1628 * frames can be up to 9000 bytes in length. When bad
1629 * frame filtering is enabled, the XMAC's RX FIFO operates
1630 * in 'store and forward' mode. For this to work, the
1631 * entire frame has to fit into the FIFO, but that means
1632 * that jumbo frames larger than 8192 bytes will be
1633 * truncated. Disabling all bad frame filtering causes
1634 * the RX FIFO to operate in streaming mode, in which
1635 * case the XMAC will start transferring frames out of the
1636 * RX FIFO as soon as the FIFO threshold is reached.
1638 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1642 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1643 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1644 * and 'Octets Rx OK Hi Cnt Ov'.
1646 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1649 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1650 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1651 * and 'Octets Tx OK Hi Cnt Ov'.
1653 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1655 /* Configure MAC arbiter */
1656 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1658 /* configure timeout values */
1659 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1660 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1661 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1662 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1664 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1665 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1666 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1667 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1669 /* Configure Rx MAC FIFO */
1670 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1671 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1672 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1674 /* Configure Tx MAC FIFO */
1675 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1676 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1677 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1680 /* Enable frame flushing if jumbo frames used */
1681 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1683 /* enable timeout timers if normal frames */
1684 skge_write16(hw, B3_PA_CTRL,
1685 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1689 static void genesis_stop(struct skge_port *skge)
1691 struct skge_hw *hw = skge->hw;
1692 int port = skge->port;
1693 unsigned retries = 1000;
1696 /* Disable Tx and Rx */
1697 cmd = xm_read16(hw, port, XM_MMU_CMD);
1698 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1699 xm_write16(hw, port, XM_MMU_CMD, cmd);
1701 genesis_reset(hw, port);
1703 /* Clear Tx packet arbiter timeout IRQ */
1704 skge_write16(hw, B3_PA_CTRL,
1705 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1708 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1710 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1711 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1713 } while (--retries > 0);
1715 /* For external PHYs there must be special handling */
1716 if (hw->phy_type != SK_PHY_XMAC) {
1717 u32 reg = skge_read32(hw, B2_GP_IO);
1725 skge_write32(hw, B2_GP_IO, reg);
1726 skge_read32(hw, B2_GP_IO);
1729 xm_write16(hw, port, XM_MMU_CMD,
1730 xm_read16(hw, port, XM_MMU_CMD)
1731 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1733 xm_read16(hw, port, XM_MMU_CMD);
1737 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1739 struct skge_hw *hw = skge->hw;
1740 int port = skge->port;
1742 unsigned long timeout = jiffies + HZ;
1744 xm_write16(hw, port,
1745 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1747 /* wait for update to complete */
1748 while (xm_read16(hw, port, XM_STAT_CMD)
1749 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1750 if (time_after(jiffies, timeout))
1755 /* special case for 64 bit octet counter */
1756 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1757 | xm_read32(hw, port, XM_TXO_OK_LO);
1758 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1759 | xm_read32(hw, port, XM_RXO_OK_LO);
1761 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1762 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1765 static void genesis_mac_intr(struct skge_hw *hw, int port)
1767 struct net_device *dev = hw->dev[port];
1768 struct skge_port *skge = netdev_priv(dev);
1769 u16 status = xm_read16(hw, port, XM_ISRC);
1771 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1772 "mac interrupt status 0x%x\n", status);
1774 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1775 xm_link_down(hw, port);
1776 mod_timer(&skge->link_timer, jiffies + 1);
1779 if (status & XM_IS_TXF_UR) {
1780 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1781 ++dev->stats.tx_fifo_errors;
1785 static void genesis_link_up(struct skge_port *skge)
1787 struct skge_hw *hw = skge->hw;
1788 int port = skge->port;
1792 cmd = xm_read16(hw, port, XM_MMU_CMD);
1795 * enabling pause frame reception is required for 1000BT
1796 * because the XMAC is not reset if the link is going down
1798 if (skge->flow_status == FLOW_STAT_NONE ||
1799 skge->flow_status == FLOW_STAT_LOC_SEND)
1800 /* Disable Pause Frame Reception */
1801 cmd |= XM_MMU_IGN_PF;
1803 /* Enable Pause Frame Reception */
1804 cmd &= ~XM_MMU_IGN_PF;
1806 xm_write16(hw, port, XM_MMU_CMD, cmd);
1808 mode = xm_read32(hw, port, XM_MODE);
1809 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1810 skge->flow_status == FLOW_STAT_LOC_SEND) {
1812 * Configure Pause Frame Generation
1813 * Use internal and external Pause Frame Generation.
1814 * Sending pause frames is edge triggered.
1815 * Send a Pause frame with the maximum pause time if
1816 * internal oder external FIFO full condition occurs.
1817 * Send a zero pause time frame to re-start transmission.
1819 /* XM_PAUSE_DA = '010000C28001' (default) */
1820 /* XM_MAC_PTIME = 0xffff (maximum) */
1821 /* remember this value is defined in big endian (!) */
1822 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1824 mode |= XM_PAUSE_MODE;
1825 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1828 * disable pause frame generation is required for 1000BT
1829 * because the XMAC is not reset if the link is going down
1831 /* Disable Pause Mode in Mode Register */
1832 mode &= ~XM_PAUSE_MODE;
1834 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1837 xm_write32(hw, port, XM_MODE, mode);
1839 /* Turn on detection of Tx underrun */
1840 msk = xm_read16(hw, port, XM_IMSK);
1841 msk &= ~XM_IS_TXF_UR;
1842 xm_write16(hw, port, XM_IMSK, msk);
1844 xm_read16(hw, port, XM_ISRC);
1846 /* get MMU Command Reg. */
1847 cmd = xm_read16(hw, port, XM_MMU_CMD);
1848 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1849 cmd |= XM_MMU_GMII_FD;
1852 * Workaround BCOM Errata (#10523) for all BCom Phys
1853 * Enable Power Management after link up
1855 if (hw->phy_type == SK_PHY_BCOM) {
1856 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1857 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1858 & ~PHY_B_AC_DIS_PM);
1859 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1863 xm_write16(hw, port, XM_MMU_CMD,
1864 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1869 static inline void bcom_phy_intr(struct skge_port *skge)
1871 struct skge_hw *hw = skge->hw;
1872 int port = skge->port;
1875 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1876 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1877 "phy interrupt status 0x%x\n", isrc);
1879 if (isrc & PHY_B_IS_PSE)
1880 pr_err("%s: uncorrectable pair swap error\n",
1881 hw->dev[port]->name);
1883 /* Workaround BCom Errata:
1884 * enable and disable loopback mode if "NO HCD" occurs.
1886 if (isrc & PHY_B_IS_NO_HDCL) {
1887 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1888 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1889 ctrl | PHY_CT_LOOP);
1890 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1891 ctrl & ~PHY_CT_LOOP);
1894 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1895 bcom_check_link(hw, port);
1899 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1903 gma_write16(hw, port, GM_SMI_DATA, val);
1904 gma_write16(hw, port, GM_SMI_CTRL,
1905 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1906 for (i = 0; i < PHY_RETRIES; i++) {
1909 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1913 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
1917 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1921 gma_write16(hw, port, GM_SMI_CTRL,
1922 GM_SMI_CT_PHY_AD(hw->phy_addr)
1923 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1925 for (i = 0; i < PHY_RETRIES; i++) {
1927 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1933 *val = gma_read16(hw, port, GM_SMI_DATA);
1937 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1940 if (__gm_phy_read(hw, port, reg, &v))
1941 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
1945 /* Marvell Phy Initialization */
1946 static void yukon_init(struct skge_hw *hw, int port)
1948 struct skge_port *skge = netdev_priv(hw->dev[port]);
1949 u16 ctrl, ct1000, adv;
1951 if (skge->autoneg == AUTONEG_ENABLE) {
1952 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1954 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1955 PHY_M_EC_MAC_S_MSK);
1956 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1958 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1960 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1963 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1964 if (skge->autoneg == AUTONEG_DISABLE)
1965 ctrl &= ~PHY_CT_ANE;
1967 ctrl |= PHY_CT_RESET;
1968 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1974 if (skge->autoneg == AUTONEG_ENABLE) {
1976 if (skge->advertising & ADVERTISED_1000baseT_Full)
1977 ct1000 |= PHY_M_1000C_AFD;
1978 if (skge->advertising & ADVERTISED_1000baseT_Half)
1979 ct1000 |= PHY_M_1000C_AHD;
1980 if (skge->advertising & ADVERTISED_100baseT_Full)
1981 adv |= PHY_M_AN_100_FD;
1982 if (skge->advertising & ADVERTISED_100baseT_Half)
1983 adv |= PHY_M_AN_100_HD;
1984 if (skge->advertising & ADVERTISED_10baseT_Full)
1985 adv |= PHY_M_AN_10_FD;
1986 if (skge->advertising & ADVERTISED_10baseT_Half)
1987 adv |= PHY_M_AN_10_HD;
1989 /* Set Flow-control capabilities */
1990 adv |= phy_pause_map[skge->flow_control];
1992 if (skge->advertising & ADVERTISED_1000baseT_Full)
1993 adv |= PHY_M_AN_1000X_AFD;
1994 if (skge->advertising & ADVERTISED_1000baseT_Half)
1995 adv |= PHY_M_AN_1000X_AHD;
1997 adv |= fiber_pause_map[skge->flow_control];
2000 /* Restart Auto-negotiation */
2001 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2003 /* forced speed/duplex settings */
2004 ct1000 = PHY_M_1000C_MSE;
2006 if (skge->duplex == DUPLEX_FULL)
2007 ctrl |= PHY_CT_DUP_MD;
2009 switch (skge->speed) {
2011 ctrl |= PHY_CT_SP1000;
2014 ctrl |= PHY_CT_SP100;
2018 ctrl |= PHY_CT_RESET;
2021 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2023 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2024 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2026 /* Enable phy interrupt on autonegotiation complete (or link up) */
2027 if (skge->autoneg == AUTONEG_ENABLE)
2028 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2030 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2033 static void yukon_reset(struct skge_hw *hw, int port)
2035 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2036 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2037 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2038 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2039 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2041 gma_write16(hw, port, GM_RX_CTRL,
2042 gma_read16(hw, port, GM_RX_CTRL)
2043 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2046 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2047 static int is_yukon_lite_a0(struct skge_hw *hw)
2052 if (hw->chip_id != CHIP_ID_YUKON)
2055 reg = skge_read32(hw, B2_FAR);
2056 skge_write8(hw, B2_FAR + 3, 0xff);
2057 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2058 skge_write32(hw, B2_FAR, reg);
2062 static void yukon_mac_init(struct skge_hw *hw, int port)
2064 struct skge_port *skge = netdev_priv(hw->dev[port]);
2067 const u8 *addr = hw->dev[port]->dev_addr;
2069 /* WA code for COMA mode -- set PHY reset */
2070 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2071 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2072 reg = skge_read32(hw, B2_GP_IO);
2073 reg |= GP_DIR_9 | GP_IO_9;
2074 skge_write32(hw, B2_GP_IO, reg);
2078 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2079 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2081 /* WA code for COMA mode -- clear PHY reset */
2082 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2083 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2084 reg = skge_read32(hw, B2_GP_IO);
2087 skge_write32(hw, B2_GP_IO, reg);
2090 /* Set hardware config mode */
2091 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2092 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2093 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2095 /* Clear GMC reset */
2096 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2097 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2098 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2100 if (skge->autoneg == AUTONEG_DISABLE) {
2101 reg = GM_GPCR_AU_ALL_DIS;
2102 gma_write16(hw, port, GM_GP_CTRL,
2103 gma_read16(hw, port, GM_GP_CTRL) | reg);
2105 switch (skge->speed) {
2107 reg &= ~GM_GPCR_SPEED_100;
2108 reg |= GM_GPCR_SPEED_1000;
2111 reg &= ~GM_GPCR_SPEED_1000;
2112 reg |= GM_GPCR_SPEED_100;
2115 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2119 if (skge->duplex == DUPLEX_FULL)
2120 reg |= GM_GPCR_DUP_FULL;
2122 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2124 switch (skge->flow_control) {
2125 case FLOW_MODE_NONE:
2126 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2127 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2129 case FLOW_MODE_LOC_SEND:
2130 /* disable Rx flow-control */
2131 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2133 case FLOW_MODE_SYMMETRIC:
2134 case FLOW_MODE_SYM_OR_REM:
2135 /* enable Tx & Rx flow-control */
2139 gma_write16(hw, port, GM_GP_CTRL, reg);
2140 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2142 yukon_init(hw, port);
2145 reg = gma_read16(hw, port, GM_PHY_ADDR);
2146 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2148 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2149 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2150 gma_write16(hw, port, GM_PHY_ADDR, reg);
2152 /* transmit control */
2153 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2155 /* receive control reg: unicast + multicast + no FCS */
2156 gma_write16(hw, port, GM_RX_CTRL,
2157 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2159 /* transmit flow control */
2160 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2162 /* transmit parameter */
2163 gma_write16(hw, port, GM_TX_PARAM,
2164 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2165 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2166 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2168 /* configure the Serial Mode Register */
2169 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2171 | IPG_DATA_VAL(IPG_DATA_DEF);
2173 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2174 reg |= GM_SMOD_JUMBO_ENA;
2176 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2178 /* physical address: used for pause frames */
2179 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2180 /* virtual address for data */
2181 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2183 /* enable interrupt mask for counter overflows */
2184 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2185 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2186 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2188 /* Initialize Mac Fifo */
2190 /* Configure Rx MAC FIFO */
2191 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2192 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2194 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2195 if (is_yukon_lite_a0(hw))
2196 reg &= ~GMF_RX_F_FL_ON;
2198 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2199 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2201 * because Pause Packet Truncation in GMAC is not working
2202 * we have to increase the Flush Threshold to 64 bytes
2203 * in order to flush pause packets in Rx FIFO on Yukon-1
2205 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2207 /* Configure Tx MAC FIFO */
2208 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2209 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2212 /* Go into power down mode */
2213 static void yukon_suspend(struct skge_hw *hw, int port)
2217 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2218 ctrl |= PHY_M_PC_POL_R_DIS;
2219 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2221 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2222 ctrl |= PHY_CT_RESET;
2223 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2225 /* switch IEEE compatible power down mode on */
2226 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2227 ctrl |= PHY_CT_PDOWN;
2228 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2231 static void yukon_stop(struct skge_port *skge)
2233 struct skge_hw *hw = skge->hw;
2234 int port = skge->port;
2236 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2237 yukon_reset(hw, port);
2239 gma_write16(hw, port, GM_GP_CTRL,
2240 gma_read16(hw, port, GM_GP_CTRL)
2241 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2242 gma_read16(hw, port, GM_GP_CTRL);
2244 yukon_suspend(hw, port);
2246 /* set GPHY Control reset */
2247 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2248 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2251 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2253 struct skge_hw *hw = skge->hw;
2254 int port = skge->port;
2257 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2258 | gma_read32(hw, port, GM_TXO_OK_LO);
2259 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2260 | gma_read32(hw, port, GM_RXO_OK_LO);
2262 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2263 data[i] = gma_read32(hw, port,
2264 skge_stats[i].gma_offset);
2267 static void yukon_mac_intr(struct skge_hw *hw, int port)
2269 struct net_device *dev = hw->dev[port];
2270 struct skge_port *skge = netdev_priv(dev);
2271 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2273 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2274 "mac interrupt status 0x%x\n", status);
2276 if (status & GM_IS_RX_FF_OR) {
2277 ++dev->stats.rx_fifo_errors;
2278 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2281 if (status & GM_IS_TX_FF_UR) {
2282 ++dev->stats.tx_fifo_errors;
2283 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2288 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2290 switch (aux & PHY_M_PS_SPEED_MSK) {
2291 case PHY_M_PS_SPEED_1000:
2293 case PHY_M_PS_SPEED_100:
2300 static void yukon_link_up(struct skge_port *skge)
2302 struct skge_hw *hw = skge->hw;
2303 int port = skge->port;
2306 /* Enable Transmit FIFO Underrun */
2307 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2309 reg = gma_read16(hw, port, GM_GP_CTRL);
2310 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2311 reg |= GM_GPCR_DUP_FULL;
2314 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2315 gma_write16(hw, port, GM_GP_CTRL, reg);
2317 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2321 static void yukon_link_down(struct skge_port *skge)
2323 struct skge_hw *hw = skge->hw;
2324 int port = skge->port;
2327 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2328 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2329 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2331 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2332 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2333 ctrl |= PHY_M_AN_ASP;
2334 /* restore Asymmetric Pause bit */
2335 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2338 skge_link_down(skge);
2340 yukon_init(hw, port);
2343 static void yukon_phy_intr(struct skge_port *skge)
2345 struct skge_hw *hw = skge->hw;
2346 int port = skge->port;
2347 const char *reason = NULL;
2348 u16 istatus, phystat;
2350 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2351 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2353 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2354 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2356 if (istatus & PHY_M_IS_AN_COMPL) {
2357 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2359 reason = "remote fault";
2363 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2364 reason = "master/slave fault";
2368 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2369 reason = "speed/duplex";
2373 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2374 ? DUPLEX_FULL : DUPLEX_HALF;
2375 skge->speed = yukon_speed(hw, phystat);
2377 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2378 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2379 case PHY_M_PS_PAUSE_MSK:
2380 skge->flow_status = FLOW_STAT_SYMMETRIC;
2382 case PHY_M_PS_RX_P_EN:
2383 skge->flow_status = FLOW_STAT_REM_SEND;
2385 case PHY_M_PS_TX_P_EN:
2386 skge->flow_status = FLOW_STAT_LOC_SEND;
2389 skge->flow_status = FLOW_STAT_NONE;
2392 if (skge->flow_status == FLOW_STAT_NONE ||
2393 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2394 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2396 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2397 yukon_link_up(skge);
2401 if (istatus & PHY_M_IS_LSP_CHANGE)
2402 skge->speed = yukon_speed(hw, phystat);
2404 if (istatus & PHY_M_IS_DUP_CHANGE)
2405 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2406 if (istatus & PHY_M_IS_LST_CHANGE) {
2407 if (phystat & PHY_M_PS_LINK_UP)
2408 yukon_link_up(skge);
2410 yukon_link_down(skge);
2414 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2416 /* XXX restart autonegotiation? */
2419 static void skge_phy_reset(struct skge_port *skge)
2421 struct skge_hw *hw = skge->hw;
2422 int port = skge->port;
2423 struct net_device *dev = hw->dev[port];
2425 netif_stop_queue(skge->netdev);
2426 netif_carrier_off(skge->netdev);
2428 spin_lock_bh(&hw->phy_lock);
2429 if (is_genesis(hw)) {
2430 genesis_reset(hw, port);
2431 genesis_mac_init(hw, port);
2433 yukon_reset(hw, port);
2434 yukon_init(hw, port);
2436 spin_unlock_bh(&hw->phy_lock);
2438 skge_set_multicast(dev);
2441 /* Basic MII support */
2442 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2444 struct mii_ioctl_data *data = if_mii(ifr);
2445 struct skge_port *skge = netdev_priv(dev);
2446 struct skge_hw *hw = skge->hw;
2447 int err = -EOPNOTSUPP;
2449 if (!netif_running(dev))
2450 return -ENODEV; /* Phy still in reset */
2454 data->phy_id = hw->phy_addr;
2459 spin_lock_bh(&hw->phy_lock);
2462 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2464 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2465 spin_unlock_bh(&hw->phy_lock);
2466 data->val_out = val;
2471 spin_lock_bh(&hw->phy_lock);
2473 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2476 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2478 spin_unlock_bh(&hw->phy_lock);
2484 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2490 end = start + len - 1;
2492 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2493 skge_write32(hw, RB_ADDR(q, RB_START), start);
2494 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2495 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2496 skge_write32(hw, RB_ADDR(q, RB_END), end);
2498 if (q == Q_R1 || q == Q_R2) {
2499 /* Set thresholds on receive queue's */
2500 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2502 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2505 /* Enable store & forward on Tx queue's because
2506 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2508 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2511 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2514 /* Setup Bus Memory Interface */
2515 static void skge_qset(struct skge_port *skge, u16 q,
2516 const struct skge_element *e)
2518 struct skge_hw *hw = skge->hw;
2519 u32 watermark = 0x600;
2520 u64 base = skge->dma + (e->desc - skge->mem);
2522 /* optimization to reduce window on 32bit/33mhz */
2523 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2526 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2527 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2528 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2529 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2532 static int skge_up(struct net_device *dev)
2534 struct skge_port *skge = netdev_priv(dev);
2535 struct skge_hw *hw = skge->hw;
2536 int port = skge->port;
2537 u32 chunk, ram_addr;
2538 size_t rx_size, tx_size;
2541 if (!is_valid_ether_addr(dev->dev_addr))
2544 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2546 if (dev->mtu > RX_BUF_SIZE)
2547 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2549 skge->rx_buf_size = RX_BUF_SIZE;
2552 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2553 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2554 skge->mem_size = tx_size + rx_size;
2555 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2559 BUG_ON(skge->dma & 7);
2561 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2562 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2567 memset(skge->mem, 0, skge->mem_size);
2569 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2573 err = skge_rx_fill(dev);
2577 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2578 skge->dma + rx_size);
2582 if (hw->ports == 1) {
2583 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2586 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2587 hw->pdev->irq, err);
2592 /* Initialize MAC */
2593 netif_carrier_off(dev);
2594 spin_lock_bh(&hw->phy_lock);
2596 genesis_mac_init(hw, port);
2598 yukon_mac_init(hw, port);
2599 spin_unlock_bh(&hw->phy_lock);
2601 /* Configure RAMbuffers - equally between ports and tx/rx */
2602 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2603 ram_addr = hw->ram_offset + 2 * chunk * port;
2605 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2606 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2608 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2609 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2610 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2612 /* Start receiver BMU */
2614 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2615 skge_led(skge, LED_MODE_ON);
2617 spin_lock_irq(&hw->hw_lock);
2618 hw->intr_mask |= portmask[port];
2619 skge_write32(hw, B0_IMSK, hw->intr_mask);
2620 skge_read32(hw, B0_IMSK);
2621 spin_unlock_irq(&hw->hw_lock);
2623 napi_enable(&skge->napi);
2625 skge_set_multicast(dev);
2630 kfree(skge->tx_ring.start);
2632 skge_rx_clean(skge);
2633 kfree(skge->rx_ring.start);
2635 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2642 static void skge_rx_stop(struct skge_hw *hw, int port)
2644 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2645 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2646 RB_RST_SET|RB_DIS_OP_MD);
2647 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2650 static int skge_down(struct net_device *dev)
2652 struct skge_port *skge = netdev_priv(dev);
2653 struct skge_hw *hw = skge->hw;
2654 int port = skge->port;
2656 if (skge->mem == NULL)
2659 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2661 netif_tx_disable(dev);
2663 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2664 del_timer_sync(&skge->link_timer);
2666 napi_disable(&skge->napi);
2667 netif_carrier_off(dev);
2669 spin_lock_irq(&hw->hw_lock);
2670 hw->intr_mask &= ~portmask[port];
2671 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2672 skge_read32(hw, B0_IMSK);
2673 spin_unlock_irq(&hw->hw_lock);
2676 free_irq(hw->pdev->irq, hw);
2678 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2684 /* Stop transmitter */
2685 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2686 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2687 RB_RST_SET|RB_DIS_OP_MD);
2690 /* Disable Force Sync bit and Enable Alloc bit */
2691 skge_write8(hw, SK_REG(port, TXA_CTRL),
2692 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2694 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2695 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2696 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2698 /* Reset PCI FIFO */
2699 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2700 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2702 /* Reset the RAM Buffer async Tx queue */
2703 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2705 skge_rx_stop(hw, port);
2707 if (is_genesis(hw)) {
2708 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2709 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2711 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2712 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2715 skge_led(skge, LED_MODE_OFF);
2717 netif_tx_lock_bh(dev);
2719 netif_tx_unlock_bh(dev);
2721 skge_rx_clean(skge);
2723 kfree(skge->rx_ring.start);
2724 kfree(skge->tx_ring.start);
2725 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2730 static inline int skge_avail(const struct skge_ring *ring)
2733 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2734 + (ring->to_clean - ring->to_use) - 1;
2737 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2738 struct net_device *dev)
2740 struct skge_port *skge = netdev_priv(dev);
2741 struct skge_hw *hw = skge->hw;
2742 struct skge_element *e;
2743 struct skge_tx_desc *td;
2748 if (skb_padto(skb, ETH_ZLEN))
2749 return NETDEV_TX_OK;
2751 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2752 return NETDEV_TX_BUSY;
2754 e = skge->tx_ring.to_use;
2756 BUG_ON(td->control & BMU_OWN);
2758 len = skb_headlen(skb);
2759 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2760 if (pci_dma_mapping_error(hw->pdev, map))
2763 dma_unmap_addr_set(e, mapaddr, map);
2764 dma_unmap_len_set(e, maplen, len);
2766 td->dma_lo = lower_32_bits(map);
2767 td->dma_hi = upper_32_bits(map);
2769 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2770 const int offset = skb_checksum_start_offset(skb);
2772 /* This seems backwards, but it is what the sk98lin
2773 * does. Looks like hardware is wrong?
2775 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2776 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2777 control = BMU_TCP_CHECK;
2779 control = BMU_UDP_CHECK;
2782 td->csum_start = offset;
2783 td->csum_write = offset + skb->csum_offset;
2785 control = BMU_CHECK;
2787 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2788 control |= BMU_EOF | BMU_IRQ_EOF;
2790 struct skge_tx_desc *tf = td;
2792 control |= BMU_STFWD;
2793 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2794 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2796 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2797 skb_frag_size(frag), DMA_TO_DEVICE);
2798 if (dma_mapping_error(&hw->pdev->dev, map))
2799 goto mapping_unwind;
2804 BUG_ON(tf->control & BMU_OWN);
2806 tf->dma_lo = lower_32_bits(map);
2807 tf->dma_hi = upper_32_bits(map);
2808 dma_unmap_addr_set(e, mapaddr, map);
2809 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2811 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2813 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2815 /* Make sure all the descriptors written */
2817 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2820 netdev_sent_queue(dev, skb->len);
2822 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2824 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2825 "tx queued, slot %td, len %d\n",
2826 e - skge->tx_ring.start, skb->len);
2828 skge->tx_ring.to_use = e->next;
2831 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2832 netdev_dbg(dev, "transmit queue full\n");
2833 netif_stop_queue(dev);
2836 return NETDEV_TX_OK;
2839 /* unroll any pages that were already mapped. */
2840 if (e != skge->tx_ring.to_use) {
2841 struct skge_element *u;
2843 for (u = skge->tx_ring.to_use->next; u != e; u = u->next)
2844 pci_unmap_page(hw->pdev, dma_unmap_addr(u, mapaddr),
2845 dma_unmap_len(u, maplen),
2847 e = skge->tx_ring.to_use;
2849 /* undo the mapping for the skb header */
2850 pci_unmap_single(hw->pdev, dma_unmap_addr(e, mapaddr),
2851 dma_unmap_len(e, maplen),
2854 /* mapping error causes error message and packet to be discarded. */
2855 if (net_ratelimit())
2856 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2858 return NETDEV_TX_OK;
2862 /* Free resources associated with this reing element */
2863 static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2866 /* skb header vs. fragment */
2867 if (control & BMU_STF)
2868 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2869 dma_unmap_len(e, maplen),
2872 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2873 dma_unmap_len(e, maplen),
2877 /* Free all buffers in transmit ring */
2878 static void skge_tx_clean(struct net_device *dev)
2880 struct skge_port *skge = netdev_priv(dev);
2881 struct skge_element *e;
2883 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2884 struct skge_tx_desc *td = e->desc;
2886 skge_tx_unmap(skge->hw->pdev, e, td->control);
2888 if (td->control & BMU_EOF)
2889 dev_kfree_skb(e->skb);
2893 netdev_reset_queue(dev);
2894 skge->tx_ring.to_clean = e;
2897 static void skge_tx_timeout(struct net_device *dev)
2899 struct skge_port *skge = netdev_priv(dev);
2901 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2903 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2905 netif_wake_queue(dev);
2908 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2912 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2915 if (!netif_running(dev)) {
2931 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2933 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2937 crc = ether_crc_le(ETH_ALEN, addr);
2939 filter[bit/8] |= 1 << (bit%8);
2942 static void genesis_set_multicast(struct net_device *dev)
2944 struct skge_port *skge = netdev_priv(dev);
2945 struct skge_hw *hw = skge->hw;
2946 int port = skge->port;
2947 struct netdev_hw_addr *ha;
2951 mode = xm_read32(hw, port, XM_MODE);
2952 mode |= XM_MD_ENA_HASH;
2953 if (dev->flags & IFF_PROMISC)
2954 mode |= XM_MD_ENA_PROM;
2956 mode &= ~XM_MD_ENA_PROM;
2958 if (dev->flags & IFF_ALLMULTI)
2959 memset(filter, 0xff, sizeof(filter));
2961 memset(filter, 0, sizeof(filter));
2963 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2964 skge->flow_status == FLOW_STAT_SYMMETRIC)
2965 genesis_add_filter(filter, pause_mc_addr);
2967 netdev_for_each_mc_addr(ha, dev)
2968 genesis_add_filter(filter, ha->addr);
2971 xm_write32(hw, port, XM_MODE, mode);
2972 xm_outhash(hw, port, XM_HSM, filter);
2975 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2977 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2978 filter[bit/8] |= 1 << (bit%8);
2981 static void yukon_set_multicast(struct net_device *dev)
2983 struct skge_port *skge = netdev_priv(dev);
2984 struct skge_hw *hw = skge->hw;
2985 int port = skge->port;
2986 struct netdev_hw_addr *ha;
2987 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2988 skge->flow_status == FLOW_STAT_SYMMETRIC);
2992 memset(filter, 0, sizeof(filter));
2994 reg = gma_read16(hw, port, GM_RX_CTRL);
2995 reg |= GM_RXCR_UCF_ENA;
2997 if (dev->flags & IFF_PROMISC) /* promiscuous */
2998 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2999 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
3000 memset(filter, 0xff, sizeof(filter));
3001 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
3002 reg &= ~GM_RXCR_MCF_ENA;
3004 reg |= GM_RXCR_MCF_ENA;
3007 yukon_add_filter(filter, pause_mc_addr);
3009 netdev_for_each_mc_addr(ha, dev)
3010 yukon_add_filter(filter, ha->addr);
3014 gma_write16(hw, port, GM_MC_ADDR_H1,
3015 (u16)filter[0] | ((u16)filter[1] << 8));
3016 gma_write16(hw, port, GM_MC_ADDR_H2,
3017 (u16)filter[2] | ((u16)filter[3] << 8));
3018 gma_write16(hw, port, GM_MC_ADDR_H3,
3019 (u16)filter[4] | ((u16)filter[5] << 8));
3020 gma_write16(hw, port, GM_MC_ADDR_H4,
3021 (u16)filter[6] | ((u16)filter[7] << 8));
3023 gma_write16(hw, port, GM_RX_CTRL, reg);
3026 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3029 return status >> XMR_FS_LEN_SHIFT;
3031 return status >> GMR_FS_LEN_SHIFT;
3034 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3037 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3039 return (status & GMR_FS_ANY_ERR) ||
3040 (status & GMR_FS_RX_OK) == 0;
3043 static void skge_set_multicast(struct net_device *dev)
3045 struct skge_port *skge = netdev_priv(dev);
3047 if (is_genesis(skge->hw))
3048 genesis_set_multicast(dev);
3050 yukon_set_multicast(dev);
3055 /* Get receive buffer from descriptor.
3056 * Handles copy of small buffers and reallocation failures
3058 static struct sk_buff *skge_rx_get(struct net_device *dev,
3059 struct skge_element *e,
3060 u32 control, u32 status, u16 csum)
3062 struct skge_port *skge = netdev_priv(dev);
3063 struct sk_buff *skb;
3064 u16 len = control & BMU_BBC;
3066 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3067 "rx slot %td status 0x%x len %d\n",
3068 e - skge->rx_ring.start, status, len);
3070 if (len > skge->rx_buf_size)
3073 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3076 if (bad_phy_status(skge->hw, status))
3079 if (phy_length(skge->hw, status) != len)
3082 if (len < RX_COPY_THRESHOLD) {
3083 skb = netdev_alloc_skb_ip_align(dev, len);
3087 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3088 dma_unmap_addr(e, mapaddr),
3089 len, PCI_DMA_FROMDEVICE);
3090 skb_copy_from_linear_data(e->skb, skb->data, len);
3091 pci_dma_sync_single_for_device(skge->hw->pdev,
3092 dma_unmap_addr(e, mapaddr),
3093 len, PCI_DMA_FROMDEVICE);
3094 skge_rx_reuse(e, skge->rx_buf_size);
3096 struct sk_buff *nskb;
3098 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3102 if (unlikely(skge_rx_setup(skge->hw->pdev, e, nskb, skge->rx_buf_size))) {
3103 dev_kfree_skb(nskb);
3107 pci_unmap_single(skge->hw->pdev,
3108 dma_unmap_addr(e, mapaddr),
3109 dma_unmap_len(e, maplen),
3110 PCI_DMA_FROMDEVICE);
3112 prefetch(skb->data);
3117 if (dev->features & NETIF_F_RXCSUM) {
3119 skb->ip_summed = CHECKSUM_COMPLETE;
3122 skb->protocol = eth_type_trans(skb, dev);
3127 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3128 "rx err, slot %td control 0x%x status 0x%x\n",
3129 e - skge->rx_ring.start, control, status);
3131 if (is_genesis(skge->hw)) {
3132 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3133 dev->stats.rx_length_errors++;
3134 if (status & XMR_FS_FRA_ERR)
3135 dev->stats.rx_frame_errors++;
3136 if (status & XMR_FS_FCS_ERR)
3137 dev->stats.rx_crc_errors++;
3139 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3140 dev->stats.rx_length_errors++;
3141 if (status & GMR_FS_FRAGMENT)
3142 dev->stats.rx_frame_errors++;
3143 if (status & GMR_FS_CRC_ERR)
3144 dev->stats.rx_crc_errors++;
3148 skge_rx_reuse(e, skge->rx_buf_size);
3152 /* Free all buffers in Tx ring which are no longer owned by device */
3153 static void skge_tx_done(struct net_device *dev)
3155 struct skge_port *skge = netdev_priv(dev);
3156 struct skge_ring *ring = &skge->tx_ring;
3157 struct skge_element *e;
3158 unsigned int bytes_compl = 0, pkts_compl = 0;
3160 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3162 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3163 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3165 if (control & BMU_OWN)
3168 skge_tx_unmap(skge->hw->pdev, e, control);
3170 if (control & BMU_EOF) {
3171 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3172 "tx done slot %td\n",
3173 e - skge->tx_ring.start);
3176 bytes_compl += e->skb->len;
3178 dev_kfree_skb(e->skb);
3181 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3182 skge->tx_ring.to_clean = e;
3184 /* Can run lockless until we need to synchronize to restart queue. */
3187 if (unlikely(netif_queue_stopped(dev) &&
3188 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3190 if (unlikely(netif_queue_stopped(dev) &&
3191 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3192 netif_wake_queue(dev);
3195 netif_tx_unlock(dev);
3199 static int skge_poll(struct napi_struct *napi, int to_do)
3201 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3202 struct net_device *dev = skge->netdev;
3203 struct skge_hw *hw = skge->hw;
3204 struct skge_ring *ring = &skge->rx_ring;
3205 struct skge_element *e;
3210 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3212 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3213 struct skge_rx_desc *rd = e->desc;
3214 struct sk_buff *skb;
3218 control = rd->control;
3219 if (control & BMU_OWN)
3222 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3224 napi_gro_receive(napi, skb);
3230 /* restart receiver */
3232 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3234 if (work_done < to_do) {
3235 unsigned long flags;
3237 napi_gro_flush(napi);
3238 spin_lock_irqsave(&hw->hw_lock, flags);
3239 __napi_complete(napi);
3240 hw->intr_mask |= napimask[skge->port];
3241 skge_write32(hw, B0_IMSK, hw->intr_mask);
3242 skge_read32(hw, B0_IMSK);
3243 spin_unlock_irqrestore(&hw->hw_lock, flags);
3249 /* Parity errors seem to happen when Genesis is connected to a switch
3250 * with no other ports present. Heartbeat error??
3252 static void skge_mac_parity(struct skge_hw *hw, int port)
3254 struct net_device *dev = hw->dev[port];
3256 ++dev->stats.tx_heartbeat_errors;
3259 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3262 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3263 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3264 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3265 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3268 static void skge_mac_intr(struct skge_hw *hw, int port)
3271 genesis_mac_intr(hw, port);
3273 yukon_mac_intr(hw, port);
3276 /* Handle device specific framing and timeout interrupts */
3277 static void skge_error_irq(struct skge_hw *hw)
3279 struct pci_dev *pdev = hw->pdev;
3280 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3282 if (is_genesis(hw)) {
3283 /* clear xmac errors */
3284 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3285 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3286 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3287 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3289 /* Timestamp (unused) overflow */
3290 if (hwstatus & IS_IRQ_TIST_OV)
3291 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3294 if (hwstatus & IS_RAM_RD_PAR) {
3295 dev_err(&pdev->dev, "Ram read data parity error\n");
3296 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3299 if (hwstatus & IS_RAM_WR_PAR) {
3300 dev_err(&pdev->dev, "Ram write data parity error\n");
3301 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3304 if (hwstatus & IS_M1_PAR_ERR)
3305 skge_mac_parity(hw, 0);
3307 if (hwstatus & IS_M2_PAR_ERR)
3308 skge_mac_parity(hw, 1);
3310 if (hwstatus & IS_R1_PAR_ERR) {
3311 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3313 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3316 if (hwstatus & IS_R2_PAR_ERR) {
3317 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3319 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3322 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3323 u16 pci_status, pci_cmd;
3325 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3326 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3328 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3329 pci_cmd, pci_status);
3331 /* Write the error bits back to clear them. */
3332 pci_status &= PCI_STATUS_ERROR_BITS;
3333 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3334 pci_write_config_word(pdev, PCI_COMMAND,
3335 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3336 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3337 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3339 /* if error still set then just ignore it */
3340 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3341 if (hwstatus & IS_IRQ_STAT) {
3342 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3343 hw->intr_mask &= ~IS_HW_ERR;
3349 * Interrupt from PHY are handled in tasklet (softirq)
3350 * because accessing phy registers requires spin wait which might
3351 * cause excess interrupt latency.
3353 static void skge_extirq(unsigned long arg)
3355 struct skge_hw *hw = (struct skge_hw *) arg;
3358 for (port = 0; port < hw->ports; port++) {
3359 struct net_device *dev = hw->dev[port];
3361 if (netif_running(dev)) {
3362 struct skge_port *skge = netdev_priv(dev);
3364 spin_lock(&hw->phy_lock);
3365 if (!is_genesis(hw))
3366 yukon_phy_intr(skge);
3367 else if (hw->phy_type == SK_PHY_BCOM)
3368 bcom_phy_intr(skge);
3369 spin_unlock(&hw->phy_lock);
3373 spin_lock_irq(&hw->hw_lock);
3374 hw->intr_mask |= IS_EXT_REG;
3375 skge_write32(hw, B0_IMSK, hw->intr_mask);
3376 skge_read32(hw, B0_IMSK);
3377 spin_unlock_irq(&hw->hw_lock);
3380 static irqreturn_t skge_intr(int irq, void *dev_id)
3382 struct skge_hw *hw = dev_id;
3386 spin_lock(&hw->hw_lock);
3387 /* Reading this register masks IRQ */
3388 status = skge_read32(hw, B0_SP_ISRC);
3389 if (status == 0 || status == ~0)
3393 status &= hw->intr_mask;
3394 if (status & IS_EXT_REG) {
3395 hw->intr_mask &= ~IS_EXT_REG;
3396 tasklet_schedule(&hw->phy_task);
3399 if (status & (IS_XA1_F|IS_R1_F)) {
3400 struct skge_port *skge = netdev_priv(hw->dev[0]);
3401 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3402 napi_schedule(&skge->napi);
3405 if (status & IS_PA_TO_TX1)
3406 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3408 if (status & IS_PA_TO_RX1) {
3409 ++hw->dev[0]->stats.rx_over_errors;
3410 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3414 if (status & IS_MAC1)
3415 skge_mac_intr(hw, 0);
3418 struct skge_port *skge = netdev_priv(hw->dev[1]);
3420 if (status & (IS_XA2_F|IS_R2_F)) {
3421 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3422 napi_schedule(&skge->napi);
3425 if (status & IS_PA_TO_RX2) {
3426 ++hw->dev[1]->stats.rx_over_errors;
3427 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3430 if (status & IS_PA_TO_TX2)
3431 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3433 if (status & IS_MAC2)
3434 skge_mac_intr(hw, 1);
3437 if (status & IS_HW_ERR)
3440 skge_write32(hw, B0_IMSK, hw->intr_mask);
3441 skge_read32(hw, B0_IMSK);
3443 spin_unlock(&hw->hw_lock);
3445 return IRQ_RETVAL(handled);
3448 #ifdef CONFIG_NET_POLL_CONTROLLER
3449 static void skge_netpoll(struct net_device *dev)
3451 struct skge_port *skge = netdev_priv(dev);
3453 disable_irq(dev->irq);
3454 skge_intr(dev->irq, skge->hw);
3455 enable_irq(dev->irq);
3459 static int skge_set_mac_address(struct net_device *dev, void *p)
3461 struct skge_port *skge = netdev_priv(dev);
3462 struct skge_hw *hw = skge->hw;
3463 unsigned port = skge->port;
3464 const struct sockaddr *addr = p;
3467 if (!is_valid_ether_addr(addr->sa_data))
3468 return -EADDRNOTAVAIL;
3470 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3472 if (!netif_running(dev)) {
3473 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3474 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3477 spin_lock_bh(&hw->phy_lock);
3478 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3479 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3481 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3482 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3485 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3487 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3488 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3491 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3492 spin_unlock_bh(&hw->phy_lock);
3498 static const struct {
3502 { CHIP_ID_GENESIS, "Genesis" },
3503 { CHIP_ID_YUKON, "Yukon" },
3504 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3505 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3508 static const char *skge_board_name(const struct skge_hw *hw)
3511 static char buf[16];
3513 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3514 if (skge_chips[i].id == hw->chip_id)
3515 return skge_chips[i].name;
3517 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3523 * Setup the board data structure, but don't bring up
3526 static int skge_reset(struct skge_hw *hw)
3529 u16 ctst, pci_status;
3530 u8 t8, mac_cfg, pmd_type;
3533 ctst = skge_read16(hw, B0_CTST);
3536 skge_write8(hw, B0_CTST, CS_RST_SET);
3537 skge_write8(hw, B0_CTST, CS_RST_CLR);
3539 /* clear PCI errors, if any */
3540 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3541 skge_write8(hw, B2_TST_CTRL2, 0);
3543 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3544 pci_write_config_word(hw->pdev, PCI_STATUS,
3545 pci_status | PCI_STATUS_ERROR_BITS);
3546 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3547 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3549 /* restore CLK_RUN bits (for Yukon-Lite) */
3550 skge_write16(hw, B0_CTST,
3551 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3553 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3554 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3555 pmd_type = skge_read8(hw, B2_PMD_TYP);
3556 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3558 switch (hw->chip_id) {
3559 case CHIP_ID_GENESIS:
3560 #ifdef CONFIG_SKGE_GENESIS
3561 switch (hw->phy_type) {
3563 hw->phy_addr = PHY_ADDR_XMAC;
3566 hw->phy_addr = PHY_ADDR_BCOM;
3569 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3575 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3580 case CHIP_ID_YUKON_LITE:
3581 case CHIP_ID_YUKON_LP:
3582 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3585 hw->phy_addr = PHY_ADDR_MARV;
3589 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3594 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3595 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3596 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3598 /* read the adapters RAM size */
3599 t8 = skge_read8(hw, B2_E_0);
3600 if (is_genesis(hw)) {
3602 /* special case: 4 x 64k x 36, offset = 0x80000 */
3603 hw->ram_size = 0x100000;
3604 hw->ram_offset = 0x80000;
3606 hw->ram_size = t8 * 512;
3608 hw->ram_size = 0x20000;
3610 hw->ram_size = t8 * 4096;
3612 hw->intr_mask = IS_HW_ERR;
3614 /* Use PHY IRQ for all but fiber based Genesis board */
3615 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3616 hw->intr_mask |= IS_EXT_REG;
3621 /* switch power to VCC (WA for VAUX problem) */
3622 skge_write8(hw, B0_POWER_CTRL,
3623 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3625 /* avoid boards with stuck Hardware error bits */
3626 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3627 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3628 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3629 hw->intr_mask &= ~IS_HW_ERR;
3632 /* Clear PHY COMA */
3633 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3634 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3635 reg &= ~PCI_PHY_COMA;
3636 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3637 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3640 for (i = 0; i < hw->ports; i++) {
3641 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3642 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3646 /* turn off hardware timer (unused) */
3647 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3648 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3649 skge_write8(hw, B0_LED, LED_STAT_ON);
3651 /* enable the Tx Arbiters */
3652 for (i = 0; i < hw->ports; i++)
3653 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3655 /* Initialize ram interface */
3656 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3658 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3661 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3662 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3663 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3664 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3665 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3666 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3667 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3668 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3669 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3671 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3673 /* Set interrupt moderation for Transmit only
3674 * Receive interrupts avoided by NAPI
3676 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3677 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3678 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3680 /* Leave irq disabled until first port is brought up. */
3681 skge_write32(hw, B0_IMSK, 0);
3683 for (i = 0; i < hw->ports; i++) {
3685 genesis_reset(hw, i);
3694 #ifdef CONFIG_SKGE_DEBUG
3696 static struct dentry *skge_debug;
3698 static int skge_debug_show(struct seq_file *seq, void *v)
3700 struct net_device *dev = seq->private;
3701 const struct skge_port *skge = netdev_priv(dev);
3702 const struct skge_hw *hw = skge->hw;
3703 const struct skge_element *e;
3705 if (!netif_running(dev))
3708 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3709 skge_read32(hw, B0_IMSK));
3711 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3712 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3713 const struct skge_tx_desc *t = e->desc;
3714 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3715 t->control, t->dma_hi, t->dma_lo, t->status,
3716 t->csum_offs, t->csum_write, t->csum_start);
3719 seq_printf(seq, "\nRx Ring:\n");
3720 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3721 const struct skge_rx_desc *r = e->desc;
3723 if (r->control & BMU_OWN)
3726 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3727 r->control, r->dma_hi, r->dma_lo, r->status,
3728 r->timestamp, r->csum1, r->csum1_start);
3734 static int skge_debug_open(struct inode *inode, struct file *file)
3736 return single_open(file, skge_debug_show, inode->i_private);
3739 static const struct file_operations skge_debug_fops = {
3740 .owner = THIS_MODULE,
3741 .open = skge_debug_open,
3743 .llseek = seq_lseek,
3744 .release = single_release,
3748 * Use network device events to create/remove/rename
3749 * debugfs file entries
3751 static int skge_device_event(struct notifier_block *unused,
3752 unsigned long event, void *ptr)
3754 struct net_device *dev = ptr;
3755 struct skge_port *skge;
3758 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3761 skge = netdev_priv(dev);
3763 case NETDEV_CHANGENAME:
3764 if (skge->debugfs) {
3765 d = debugfs_rename(skge_debug, skge->debugfs,
3766 skge_debug, dev->name);
3770 netdev_info(dev, "rename failed\n");
3771 debugfs_remove(skge->debugfs);
3776 case NETDEV_GOING_DOWN:
3777 if (skge->debugfs) {
3778 debugfs_remove(skge->debugfs);
3779 skge->debugfs = NULL;
3784 d = debugfs_create_file(dev->name, S_IRUGO,
3787 if (!d || IS_ERR(d))
3788 netdev_info(dev, "debugfs create failed\n");
3798 static struct notifier_block skge_notifier = {
3799 .notifier_call = skge_device_event,
3803 static __init void skge_debug_init(void)
3807 ent = debugfs_create_dir("skge", NULL);
3808 if (!ent || IS_ERR(ent)) {
3809 pr_info("debugfs create directory failed\n");
3814 register_netdevice_notifier(&skge_notifier);
3817 static __exit void skge_debug_cleanup(void)
3820 unregister_netdevice_notifier(&skge_notifier);
3821 debugfs_remove(skge_debug);
3827 #define skge_debug_init()
3828 #define skge_debug_cleanup()
3831 static const struct net_device_ops skge_netdev_ops = {
3832 .ndo_open = skge_up,
3833 .ndo_stop = skge_down,
3834 .ndo_start_xmit = skge_xmit_frame,
3835 .ndo_do_ioctl = skge_ioctl,
3836 .ndo_get_stats = skge_get_stats,
3837 .ndo_tx_timeout = skge_tx_timeout,
3838 .ndo_change_mtu = skge_change_mtu,
3839 .ndo_validate_addr = eth_validate_addr,
3840 .ndo_set_rx_mode = skge_set_multicast,
3841 .ndo_set_mac_address = skge_set_mac_address,
3842 #ifdef CONFIG_NET_POLL_CONTROLLER
3843 .ndo_poll_controller = skge_netpoll,
3848 /* Initialize network device */
3849 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3852 struct skge_port *skge;
3853 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3856 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3860 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3861 dev->netdev_ops = &skge_netdev_ops;
3862 dev->ethtool_ops = &skge_ethtool_ops;
3863 dev->watchdog_timeo = TX_WATCHDOG;
3864 dev->irq = hw->pdev->irq;
3867 dev->features |= NETIF_F_HIGHDMA;
3869 skge = netdev_priv(dev);
3870 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3873 skge->msg_enable = netif_msg_init(debug, default_msg);
3875 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3876 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3878 /* Auto speed and flow control */
3879 skge->autoneg = AUTONEG_ENABLE;
3880 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3883 skge->advertising = skge_supported_modes(hw);
3885 if (device_can_wakeup(&hw->pdev->dev)) {
3886 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3887 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3890 hw->dev[port] = dev;
3894 /* Only used for Genesis XMAC */
3896 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3898 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3900 dev->features |= dev->hw_features;
3903 /* read the mac address */
3904 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3905 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3910 static void __devinit skge_show_addr(struct net_device *dev)
3912 const struct skge_port *skge = netdev_priv(dev);
3914 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3917 static int only_32bit_dma;
3919 static int __devinit skge_probe(struct pci_dev *pdev,
3920 const struct pci_device_id *ent)
3922 struct net_device *dev, *dev1;
3924 int err, using_dac = 0;
3926 err = pci_enable_device(pdev);
3928 dev_err(&pdev->dev, "cannot enable PCI device\n");
3932 err = pci_request_regions(pdev, DRV_NAME);
3934 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3935 goto err_out_disable_pdev;
3938 pci_set_master(pdev);
3940 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3942 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3943 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3945 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3949 dev_err(&pdev->dev, "no usable DMA configuration\n");
3950 goto err_out_free_regions;
3954 /* byte swap descriptors in hardware */
3958 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3959 reg |= PCI_REV_DESC;
3960 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3965 /* space for skge@pci:0000:04:00.0 */
3966 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3967 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3969 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3970 goto err_out_free_regions;
3972 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3975 spin_lock_init(&hw->hw_lock);
3976 spin_lock_init(&hw->phy_lock);
3977 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3979 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3981 dev_err(&pdev->dev, "cannot map device registers\n");
3982 goto err_out_free_hw;
3985 err = skge_reset(hw);
3987 goto err_out_iounmap;
3989 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3991 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3992 skge_board_name(hw), hw->chip_rev);
3994 dev = skge_devinit(hw, 0, using_dac);
3996 goto err_out_led_off;
3998 /* Some motherboards are broken and has zero in ROM. */
3999 if (!is_valid_ether_addr(dev->dev_addr))
4000 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
4002 err = register_netdev(dev);
4004 dev_err(&pdev->dev, "cannot register net device\n");
4005 goto err_out_free_netdev;
4008 skge_show_addr(dev);
4010 if (hw->ports > 1) {
4011 dev1 = skge_devinit(hw, 1, using_dac);
4014 goto err_out_unregister;
4017 err = register_netdev(dev1);
4019 dev_err(&pdev->dev, "cannot register second net device\n");
4020 goto err_out_free_dev1;
4023 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
4026 dev_err(&pdev->dev, "cannot assign irq %d\n",
4028 goto err_out_unregister_dev1;
4031 skge_show_addr(dev1);
4033 pci_set_drvdata(pdev, hw);
4037 err_out_unregister_dev1:
4038 unregister_netdev(dev1);
4042 unregister_netdev(dev);
4043 err_out_free_netdev:
4046 skge_write16(hw, B0_LED, LED_STAT_OFF);
4051 err_out_free_regions:
4052 pci_release_regions(pdev);
4053 err_out_disable_pdev:
4054 pci_disable_device(pdev);
4055 pci_set_drvdata(pdev, NULL);
4060 static void __devexit skge_remove(struct pci_dev *pdev)
4062 struct skge_hw *hw = pci_get_drvdata(pdev);
4063 struct net_device *dev0, *dev1;
4070 unregister_netdev(dev1);
4072 unregister_netdev(dev0);
4074 tasklet_disable(&hw->phy_task);
4076 spin_lock_irq(&hw->hw_lock);
4079 if (hw->ports > 1) {
4080 skge_write32(hw, B0_IMSK, 0);
4081 skge_read32(hw, B0_IMSK);
4082 free_irq(pdev->irq, hw);
4084 spin_unlock_irq(&hw->hw_lock);
4086 skge_write16(hw, B0_LED, LED_STAT_OFF);
4087 skge_write8(hw, B0_CTST, CS_RST_SET);
4090 free_irq(pdev->irq, hw);
4091 pci_release_regions(pdev);
4092 pci_disable_device(pdev);
4099 pci_set_drvdata(pdev, NULL);
4102 #ifdef CONFIG_PM_SLEEP
4103 static int skge_suspend(struct device *dev)
4105 struct pci_dev *pdev = to_pci_dev(dev);
4106 struct skge_hw *hw = pci_get_drvdata(pdev);
4112 for (i = 0; i < hw->ports; i++) {
4113 struct net_device *dev = hw->dev[i];
4114 struct skge_port *skge = netdev_priv(dev);
4116 if (netif_running(dev))
4120 skge_wol_init(skge);
4123 skge_write32(hw, B0_IMSK, 0);
4128 static int skge_resume(struct device *dev)
4130 struct pci_dev *pdev = to_pci_dev(dev);
4131 struct skge_hw *hw = pci_get_drvdata(pdev);
4137 err = skge_reset(hw);
4141 for (i = 0; i < hw->ports; i++) {
4142 struct net_device *dev = hw->dev[i];
4144 if (netif_running(dev)) {
4148 netdev_err(dev, "could not up: %d\n", err);
4158 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4159 #define SKGE_PM_OPS (&skge_pm_ops)
4163 #define SKGE_PM_OPS NULL
4164 #endif /* CONFIG_PM_SLEEP */
4166 static void skge_shutdown(struct pci_dev *pdev)
4168 struct skge_hw *hw = pci_get_drvdata(pdev);
4174 for (i = 0; i < hw->ports; i++) {
4175 struct net_device *dev = hw->dev[i];
4176 struct skge_port *skge = netdev_priv(dev);
4179 skge_wol_init(skge);
4182 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4183 pci_set_power_state(pdev, PCI_D3hot);
4186 static struct pci_driver skge_driver = {
4188 .id_table = skge_id_table,
4189 .probe = skge_probe,
4190 .remove = __devexit_p(skge_remove),
4191 .shutdown = skge_shutdown,
4192 .driver.pm = SKGE_PM_OPS,
4195 static struct dmi_system_id skge_32bit_dma_boards[] = {
4197 .ident = "Gigabyte nForce boards",
4199 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4200 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4206 static int __init skge_init_module(void)
4208 if (dmi_check_system(skge_32bit_dma_boards))
4211 return pci_register_driver(&skge_driver);
4214 static void __exit skge_cleanup_module(void)
4216 pci_unregister_driver(&skge_driver);
4217 skge_debug_cleanup();
4220 module_init(skge_init_module);
4221 module_exit(skge_cleanup_module);