drivers/net/ethernet/intel/igb/igb_main.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  29
  30 #include <linux/module.h>
  31 #include <linux/types.h>
  32 #include <linux/init.h>
  33 #include <linux/bitops.h>
  34 #include <linux/vmalloc.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ipv6.h>
  38 #include <linux/slab.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/net_tstamp.h>
  42 #include <linux/mii.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/pci.h>
  47 #include <linux/pci-aspm.h>
  48 #include <linux/delay.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/ip.h>
  51 #include <linux/tcp.h>
  52 #include <linux/sctp.h>
  53 #include <linux/if_ether.h>
  54 #include <linux/aer.h>
  55 #include <linux/prefetch.h>
  56 #include <linux/pm_runtime.h>
  57 #ifdef CONFIG_IGB_DCA
  58 #include <linux/dca.h>
  59 #endif
  60 #include <linux/i2c.h>
  61 #include "igb.h"
  62
  63 #define MAJ 4
  64 #define MIN 1
  65 #define BUILD 2
  66 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  67 __stringify(BUILD) "-k"
  68 char igb_driver_name[] = "igb";
  69 char igb_driver_version[] = DRV_VERSION;
  70 static const char igb_driver_string[] =
  71                                 "Intel(R) Gigabit Ethernet Network Driver";
  72 static const char igb_copyright[] =
  73                                 "Copyright (c) 2007-2013 Intel Corporation.";
  74
  75 static const struct e1000_info *igb_info_tbl[] = {
  76         [board_82575] = &e1000_82575_info,
  77 };
  78
  79 static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
  80         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 },
  81         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 },
  82         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 },
  83         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 },
  84         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 },
  85         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
  86         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
  87         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
  88         { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
  89         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
  90         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
  91         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
  92         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
  93         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
  94         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
  95         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
  96         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
  97         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
  98         { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
  99         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
 100         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
 101         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
 102         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
 103         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
 104         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
 105         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
 106         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
 107         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
 108         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
 109         { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
 110         /* required last entry */
 111         {0, }
 112 };
 113
 114 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
 115
 116 void igb_reset(struct igb_adapter *);
 117 static int igb_setup_all_tx_resources(struct igb_adapter *);
 118 static int igb_setup_all_rx_resources(struct igb_adapter *);
 119 static void igb_free_all_tx_resources(struct igb_adapter *);
 120 static void igb_free_all_rx_resources(struct igb_adapter *);
 121 static void igb_setup_mrqc(struct igb_adapter *);
 122 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
 123 static void igb_remove(struct pci_dev *pdev);
 124 static int igb_sw_init(struct igb_adapter *);
 125 static int igb_open(struct net_device *);
 126 static int igb_close(struct net_device *);
 127 static void igb_configure(struct igb_adapter *);
 128 static void igb_configure_tx(struct igb_adapter *);
 129 static void igb_configure_rx(struct igb_adapter *);
 130 static void igb_clean_all_tx_rings(struct igb_adapter *);
 131 static void igb_clean_all_rx_rings(struct igb_adapter *);
 132 static void igb_clean_tx_ring(struct igb_ring *);
 133 static void igb_clean_rx_ring(struct igb_ring *);
 134 static void igb_set_rx_mode(struct net_device *);
 135 static void igb_update_phy_info(unsigned long);
 136 static void igb_watchdog(unsigned long);
 137 static void igb_watchdog_task(struct work_struct *);
 138 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
 139 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
 140                                                  struct rtnl_link_stats64 *stats);
 141 static int igb_change_mtu(struct net_device *, int);
 142 static int igb_set_mac(struct net_device *, void *);
 143 static void igb_set_uta(struct igb_adapter *adapter);
 144 static irqreturn_t igb_intr(int irq, void *);
 145 static irqreturn_t igb_intr_msi(int irq, void *);
 146 static irqreturn_t igb_msix_other(int irq, void *);
 147 static irqreturn_t igb_msix_ring(int irq, void *);
 148 #ifdef CONFIG_IGB_DCA
 149 static void igb_update_dca(struct igb_q_vector *);
 150 static void igb_setup_dca(struct igb_adapter *);
 151 #endif /* CONFIG_IGB_DCA */
 152 static int igb_poll(struct napi_struct *, int);
 153 static bool igb_clean_tx_irq(struct igb_q_vector *);
 154 static bool igb_clean_rx_irq(struct igb_q_vector *, int);
 155 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
 156 static void igb_tx_timeout(struct net_device *);
 157 static void igb_reset_task(struct work_struct *);
 158 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features);
 159 static int igb_vlan_rx_add_vid(struct net_device *, u16);
 160 static int igb_vlan_rx_kill_vid(struct net_device *, u16);
 161 static void igb_restore_vlan(struct igb_adapter *);
 162 static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
 163 static void igb_ping_all_vfs(struct igb_adapter *);
 164 static void igb_msg_task(struct igb_adapter *);
 165 static void igb_vmm_control(struct igb_adapter *);
 166 static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
 167 static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
 168 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
 169 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
 170                                int vf, u16 vlan, u8 qos);
 171 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
 172 static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
 173                                  struct ifla_vf_info *ivi);
 174 static void igb_check_vf_rate_limit(struct igb_adapter *);
 175
 176 #ifdef CONFIG_PCI_IOV
 177 static int igb_vf_configure(struct igb_adapter *adapter, int vf);
 178 static bool igb_vfs_are_assigned(struct igb_adapter *adapter);
 179 #endif
 180
 181 #ifdef CONFIG_PM
 182 #ifdef CONFIG_PM_SLEEP
 183 static int igb_suspend(struct device *);
 184 #endif
 185 static int igb_resume(struct device *);
 186 #ifdef CONFIG_PM_RUNTIME
 187 static int igb_runtime_suspend(struct device *dev);
 188 static int igb_runtime_resume(struct device *dev);
 189 static int igb_runtime_idle(struct device *dev);
 190 #endif
 191 static const struct dev_pm_ops igb_pm_ops = {
 192         SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume)
 193         SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume,
 194                         igb_runtime_idle)
 195 };
 196 #endif
 197 static void igb_shutdown(struct pci_dev *);
 198 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs);
 199 #ifdef CONFIG_IGB_DCA
 200 static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
 201 static struct notifier_block dca_notifier = {
 202         .notifier_call  = igb_notify_dca,
 203         .next           = NULL,
 204         .priority       = 0
 205 };
 206 #endif
 207 #ifdef CONFIG_NET_POLL_CONTROLLER
 208 /* for netdump / net console */
 209 static void igb_netpoll(struct net_device *);
 210 #endif
 211 #ifdef CONFIG_PCI_IOV
 212 static unsigned int max_vfs = 0;
 213 module_param(max_vfs, uint, 0);
 214 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
 215                  "per physical function");
 216 #endif /* CONFIG_PCI_IOV */
 217
 218 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
 219                      pci_channel_state_t);
 220 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
 221 static void igb_io_resume(struct pci_dev *);
 222
 223 static const struct pci_error_handlers igb_err_handler = {
 224         .error_detected = igb_io_error_detected,
 225         .slot_reset = igb_io_slot_reset,
 226         .resume = igb_io_resume,
 227 };
 228
 229 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba);
 230
 231 static struct pci_driver igb_driver = {
 232         .name     = igb_driver_name,
 233         .id_table = igb_pci_tbl,
 234         .probe    = igb_probe,
 235         .remove   = igb_remove,
 236 #ifdef CONFIG_PM
 237         .driver.pm = &igb_pm_ops,
 238 #endif
 239         .shutdown = igb_shutdown,
 240         .sriov_configure = igb_pci_sriov_configure,
 241         .err_handler = &igb_err_handler
 242 };
 243
 244 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
 245 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
 246 MODULE_LICENSE("GPL");
 247 MODULE_VERSION(DRV_VERSION);
 248
 249 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
 250 static int debug = -1;
 251 module_param(debug, int, 0);
 252 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
 253
 254 struct igb_reg_info {
 255         u32 ofs;
 256         char *name;
 257 };
 258
 259 static const struct igb_reg_info igb_reg_info_tbl[] = {
 260
 261         /* General Registers */
 262         {E1000_CTRL, "CTRL"},
 263         {E1000_STATUS, "STATUS"},
 264         {E1000_CTRL_EXT, "CTRL_EXT"},
 265
 266         /* Interrupt Registers */
 267         {E1000_ICR, "ICR"},
 268
 269         /* RX Registers */
 270         {E1000_RCTL, "RCTL"},
 271         {E1000_RDLEN(0), "RDLEN"},
 272         {E1000_RDH(0), "RDH"},
 273         {E1000_RDT(0), "RDT"},
 274         {E1000_RXDCTL(0), "RXDCTL"},
 275         {E1000_RDBAL(0), "RDBAL"},
 276         {E1000_RDBAH(0), "RDBAH"},
 277
 278         /* TX Registers */
 279         {E1000_TCTL, "TCTL"},
 280         {E1000_TDBAL(0), "TDBAL"},
 281         {E1000_TDBAH(0), "TDBAH"},
 282         {E1000_TDLEN(0), "TDLEN"},
 283         {E1000_TDH(0), "TDH"},
 284         {E1000_TDT(0), "TDT"},
 285         {E1000_TXDCTL(0), "TXDCTL"},
 286         {E1000_TDFH, "TDFH"},
 287         {E1000_TDFT, "TDFT"},
 288         {E1000_TDFHS, "TDFHS"},
 289         {E1000_TDFPC, "TDFPC"},
 290
 291         /* List Terminator */
 292         {}
 293 };
 294
 295 /*
 296  * igb_regdump - register printout routine
 297  */
 298 static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
 299 {
 300         int n = 0;
 301         char rname[16];
 302         u32 regs[8];
 303
 304         switch (reginfo->ofs) {
 305         case E1000_RDLEN(0):
 306                 for (n = 0; n < 4; n++)
 307                         regs[n] = rd32(E1000_RDLEN(n));
 308                 break;
 309         case E1000_RDH(0):
 310                 for (n = 0; n < 4; n++)
 311                         regs[n] = rd32(E1000_RDH(n));
 312                 break;
 313         case E1000_RDT(0):
 314                 for (n = 0; n < 4; n++)
 315                         regs[n] = rd32(E1000_RDT(n));
 316                 break;
 317         case E1000_RXDCTL(0):
 318                 for (n = 0; n < 4; n++)
 319                         regs[n] = rd32(E1000_RXDCTL(n));
 320                 break;
 321         case E1000_RDBAL(0):
 322                 for (n = 0; n < 4; n++)
 323                         regs[n] = rd32(E1000_RDBAL(n));
 324                 break;
 325         case E1000_RDBAH(0):
 326                 for (n = 0; n < 4; n++)
 327                         regs[n] = rd32(E1000_RDBAH(n));
 328                 break;
 329         case E1000_TDBAL(0):
 330                 for (n = 0; n < 4; n++)
 331                         regs[n] = rd32(E1000_RDBAL(n));
 332                 break;
 333         case E1000_TDBAH(0):
 334                 for (n = 0; n < 4; n++)
 335                         regs[n] = rd32(E1000_TDBAH(n));
 336                 break;
 337         case E1000_TDLEN(0):
 338                 for (n = 0; n < 4; n++)
 339                         regs[n] = rd32(E1000_TDLEN(n));
 340                 break;
 341         case E1000_TDH(0):
 342                 for (n = 0; n < 4; n++)
 343                         regs[n] = rd32(E1000_TDH(n));
 344                 break;
 345         case E1000_TDT(0):
 346                 for (n = 0; n < 4; n++)
 347                         regs[n] = rd32(E1000_TDT(n));
 348                 break;
 349         case E1000_TXDCTL(0):
 350                 for (n = 0; n < 4; n++)
 351                         regs[n] = rd32(E1000_TXDCTL(n));
 352                 break;
 353         default:
 354                 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs));
 355                 return;
 356         }
 357
 358         snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
 359         pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
 360                 regs[2], regs[3]);
 361 }
 362
 363 /*
 364  * igb_dump - Print registers, tx-rings and rx-rings
 365  */
 366 static void igb_dump(struct igb_adapter *adapter)
 367 {
 368         struct net_device *netdev = adapter->netdev;
 369         struct e1000_hw *hw = &adapter->hw;
 370         struct igb_reg_info *reginfo;
 371         struct igb_ring *tx_ring;
 372         union e1000_adv_tx_desc *tx_desc;
 373         struct my_u0 { u64 a; u64 b; } *u0;
 374         struct igb_ring *rx_ring;
 375         union e1000_adv_rx_desc *rx_desc;
 376         u32 staterr;
 377         u16 i, n;
 378
 379         if (!netif_msg_hw(adapter))
 380                 return;
 381
 382         /* Print netdevice Info */
 383         if (netdev) {
 384                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 385                 pr_info("Device Name     state            trans_start      "
 386                         "last_rx\n");
 387                 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
 388                         netdev->state, netdev->trans_start, netdev->last_rx);
 389         }
 390
 391         /* Print Registers */
 392         dev_info(&adapter->pdev->dev, "Register Dump\n");
 393         pr_info(" Register Name   Value\n");
 394         for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
 395              reginfo->name; reginfo++) {
 396                 igb_regdump(hw, reginfo);
 397         }
 398
 399         /* Print TX Ring Summary */
 400         if (!netdev || !netif_running(netdev))
 401                 goto exit;
 402
 403         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 404         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 405         for (n = 0; n < adapter->num_tx_queues; n++) {
 406                 struct igb_tx_buffer *buffer_info;
 407                 tx_ring = adapter->tx_ring[n];
 408                 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 409                 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
 410                         n, tx_ring->next_to_use, tx_ring->next_to_clean,
 411                         (u64)dma_unmap_addr(buffer_info, dma),
 412                         dma_unmap_len(buffer_info, len),
 413                         buffer_info->next_to_watch,
 414                         (u64)buffer_info->time_stamp);
 415         }
 416
 417         /* Print TX Rings */
 418         if (!netif_msg_tx_done(adapter))
 419                 goto rx_ring_summary;
 420
 421         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 422
 423         /* Transmit Descriptor Formats
 424          *
 425          * Advanced Transmit Descriptor
 426          *   +--------------------------------------------------------------+
 427          * 0 |         Buffer Address [63:0]                                |
 428          *   +--------------------------------------------------------------+
 429          * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
 430          *   +--------------------------------------------------------------+
 431          *   63      46 45    40 39 38 36 35 32 31   24             15       0
 432          */
 433
 434         for (n = 0; n < adapter->num_tx_queues; n++) {
 435                 tx_ring = adapter->tx_ring[n];
 436                 pr_info("------------------------------------\n");
 437                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 438                 pr_info("------------------------------------\n");
 439                 pr_info("T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] "
 440                         "[bi->dma       ] leng  ntw timestamp        "
 441                         "bi->skb\n");
 442
 443                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 444                         const char *next_desc;
 445                         struct igb_tx_buffer *buffer_info;
 446                         tx_desc = IGB_TX_DESC(tx_ring, i);
 447                         buffer_info = &tx_ring->tx_buffer_info[i];
 448                         u0 = (struct my_u0 *)tx_desc;
 449                         if (i == tx_ring->next_to_use &&
 450                             i == tx_ring->next_to_clean)
 451                                 next_desc = " NTC/U";
 452                         else if (i == tx_ring->next_to_use)
 453                                 next_desc = " NTU";
 454                         else if (i == tx_ring->next_to_clean)
 455                                 next_desc = " NTC";
 456                         else
 457                                 next_desc = "";
 458
 459                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 460                                 " %04X  %p %016llX %p%s\n", i,
 461                                 le64_to_cpu(u0->a),
 462                                 le64_to_cpu(u0->b),
 463                                 (u64)dma_unmap_addr(buffer_info, dma),
 464                                 dma_unmap_len(buffer_info, len),
 465                                 buffer_info->next_to_watch,
 466                                 (u64)buffer_info->time_stamp,
 467                                 buffer_info->skb, next_desc);
 468
 469                         if (netif_msg_pktdata(adapter) && buffer_info->skb)
 470                                 print_hex_dump(KERN_INFO, "",
 471                                         DUMP_PREFIX_ADDRESS,
 472                                         16, 1, buffer_info->skb->data,
 473                                         dma_unmap_len(buffer_info, len),
 474                                         true);
 475                 }
 476         }
 477
 478         /* Print RX Rings Summary */
 479 rx_ring_summary:
 480         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 481         pr_info("Queue [NTU] [NTC]\n");
 482         for (n = 0; n < adapter->num_rx_queues; n++) {
 483                 rx_ring = adapter->rx_ring[n];
 484                 pr_info(" %5d %5X %5X\n",
 485                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 486         }
 487
 488         /* Print RX Rings */
 489         if (!netif_msg_rx_status(adapter))
 490                 goto exit;
 491
 492         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 493
 494         /* Advanced Receive Descriptor (Read) Format
 495          *    63                                           1        0
 496          *    +-----------------------------------------------------+
 497          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 498          *    +----------------------------------------------+------+
 499          *  8 |       Header Buffer Address [63:1]           |  DD  |
 500          *    +-----------------------------------------------------+
 501          *
 502          *
 503          * Advanced Receive Descriptor (Write-Back) Format
 504          *
 505          *   63       48 47    32 31  30      21 20 17 16   4 3     0
 506          *   +------------------------------------------------------+
 507          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 508          *   | Checksum   Ident  |   |           |    | Type | Type |
 509          *   +------------------------------------------------------+
 510          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 511          *   +------------------------------------------------------+
 512          *   63       48 47    32 31            20 19               0
 513          */
 514
 515         for (n = 0; n < adapter->num_rx_queues; n++) {
 516                 rx_ring = adapter->rx_ring[n];
 517                 pr_info("------------------------------------\n");
 518                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 519                 pr_info("------------------------------------\n");
 520                 pr_info("R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] "
 521                         "[bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
 522                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] -----"
 523                         "----------- [bi->skb] <-- Adv Rx Write-Back format\n");
 524
 525                 for (i = 0; i < rx_ring->count; i++) {
 526                         const char *next_desc;
 527                         struct igb_rx_buffer *buffer_info;
 528                         buffer_info = &rx_ring->rx_buffer_info[i];
 529                         rx_desc = IGB_RX_DESC(rx_ring, i);
 530                         u0 = (struct my_u0 *)rx_desc;
 531                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 532
 533                         if (i == rx_ring->next_to_use)
 534                                 next_desc = " NTU";
 535                         else if (i == rx_ring->next_to_clean)
 536                                 next_desc = " NTC";
 537                         else
 538                                 next_desc = "";
 539
 540                         if (staterr & E1000_RXD_STAT_DD) {
 541                                 /* Descriptor Done */
 542                                 pr_info("%s[0x%03X]     %016llX %016llX ---------------- %s\n",
 543                                         "RWB", i,
 544                                         le64_to_cpu(u0->a),
 545                                         le64_to_cpu(u0->b),
 546                                         next_desc);
 547                         } else {
 548                                 pr_info("%s[0x%03X]     %016llX %016llX %016llX %s\n",
 549                                         "R  ", i,
 550                                         le64_to_cpu(u0->a),
 551                                         le64_to_cpu(u0->b),
 552                                         (u64)buffer_info->dma,
 553                                         next_desc);
 554
 555                                 if (netif_msg_pktdata(adapter) &&
 556                                     buffer_info->dma && buffer_info->page) {
 557                                         print_hex_dump(KERN_INFO, "",
 558                                           DUMP_PREFIX_ADDRESS,
 559                                           16, 1,
 560                                           page_address(buffer_info->page) +
 561                                                       buffer_info->page_offset,
 562                                           IGB_RX_BUFSZ, true);
 563                                 }
 564                         }
 565                 }
 566         }
 567
 568 exit:
 569         return;
 570 }
 571
 572 /*  igb_get_i2c_data - Reads the I2C SDA data bit
 573  *  @hw: pointer to hardware structure
 574  *  @i2cctl: Current value of I2CCTL register
 575  *
 576  *  Returns the I2C data bit value
 577  */
 578 static int igb_get_i2c_data(void *data)
 579 {
 580         struct igb_adapter *adapter = (struct igb_adapter *)data;
 581         struct e1000_hw *hw = &adapter->hw;
 582         s32 i2cctl = rd32(E1000_I2CPARAMS);
 583
 584         return ((i2cctl & E1000_I2C_DATA_IN) != 0);
 585 }
 586
 587 /* igb_set_i2c_data - Sets the I2C data bit
 588  *  @data: pointer to hardware structure
 589  *  @state: I2C data value (0 or 1) to set
 590  *
 591  *  Sets the I2C data bit
 592  */
 593 static void igb_set_i2c_data(void *data, int state)
 594 {
 595         struct igb_adapter *adapter = (struct igb_adapter *)data;
 596         struct e1000_hw *hw = &adapter->hw;
 597         s32 i2cctl = rd32(E1000_I2CPARAMS);
 598
 599         if (state)
 600                 i2cctl |= E1000_I2C_DATA_OUT;
 601         else
 602                 i2cctl &= ~E1000_I2C_DATA_OUT;
 603
 604         i2cctl &= ~E1000_I2C_DATA_OE_N;
 605         i2cctl |= E1000_I2C_CLK_OE_N;
 606         wr32(E1000_I2CPARAMS, i2cctl);
 607         wrfl();
 608
 609 }
 610
 611 /* igb_set_i2c_clk - Sets the I2C SCL clock
 612  *  @data: pointer to hardware structure
 613  *  @state: state to set clock
 614  *
 615  *  Sets the I2C clock line to state
 616  */
 617 static void igb_set_i2c_clk(void *data, int state)
 618 {
 619         struct igb_adapter *adapter = (struct igb_adapter *)data;
 620         struct e1000_hw *hw = &adapter->hw;
 621         s32 i2cctl = rd32(E1000_I2CPARAMS);
 622
 623         if (state) {
 624                 i2cctl |= E1000_I2C_CLK_OUT;
 625                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 626         } else {
 627                 i2cctl &= ~E1000_I2C_CLK_OUT;
 628                 i2cctl &= ~E1000_I2C_CLK_OE_N;
 629         }
 630         wr32(E1000_I2CPARAMS, i2cctl);
 631         wrfl();
 632 }
 633
 634 /* igb_get_i2c_clk - Gets the I2C SCL clock state
 635  *  @data: pointer to hardware structure
 636  *
 637  *  Gets the I2C clock state
 638  */
 639 static int igb_get_i2c_clk(void *data)
 640 {
 641         struct igb_adapter *adapter = (struct igb_adapter *)data;
 642         struct e1000_hw *hw = &adapter->hw;
 643         s32 i2cctl = rd32(E1000_I2CPARAMS);
 644
 645         return ((i2cctl & E1000_I2C_CLK_IN) != 0);
 646 }
 647
 648 static const struct i2c_algo_bit_data igb_i2c_algo = {
 649         .setsda         = igb_set_i2c_data,
 650         .setscl         = igb_set_i2c_clk,
 651         .getsda         = igb_get_i2c_data,
 652         .getscl         = igb_get_i2c_clk,
 653         .udelay         = 5,
 654         .timeout        = 20,
 655 };
 656
 657 /**
 658  * igb_get_hw_dev - return device
 659  * used by hardware layer to print debugging information
 660  **/
 661 struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
 662 {
 663         struct igb_adapter *adapter = hw->back;
 664         return adapter->netdev;
 665 }
 666
 667 /**
 668  * igb_init_module - Driver Registration Routine
 669  *
 670  * igb_init_module is the first routine called when the driver is
 671  * loaded. All it does is register with the PCI subsystem.
 672  **/
 673 static int __init igb_init_module(void)
 674 {
 675         int ret;
 676         pr_info("%s - version %s\n",
 677                igb_driver_string, igb_driver_version);
 678
 679         pr_info("%s\n", igb_copyright);
 680
 681 #ifdef CONFIG_IGB_DCA
 682         dca_register_notify(&dca_notifier);
 683 #endif
 684         ret = pci_register_driver(&igb_driver);
 685         return ret;
 686 }
 687
 688 module_init(igb_init_module);
 689
 690 /**
 691  * igb_exit_module - Driver Exit Cleanup Routine
 692  *
 693  * igb_exit_module is called just before the driver is removed
 694  * from memory.
 695  **/
 696 static void __exit igb_exit_module(void)
 697 {
 698 #ifdef CONFIG_IGB_DCA
 699         dca_unregister_notify(&dca_notifier);
 700 #endif
 701         pci_unregister_driver(&igb_driver);
 702 }
 703
 704 module_exit(igb_exit_module);
 705
 706 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
 707 /**
 708  * igb_cache_ring_register - Descriptor ring to register mapping
 709  * @adapter: board private structure to initialize
 710  *
 711  * Once we know the feature-set enabled for the device, we'll cache
 712  * the register offset the descriptor ring is assigned to.
 713  **/
 714 static void igb_cache_ring_register(struct igb_adapter *adapter)
 715 {
 716         int i = 0, j = 0;
 717         u32 rbase_offset = adapter->vfs_allocated_count;
 718
 719         switch (adapter->hw.mac.type) {
 720         case e1000_82576:
 721                 /* The queues are allocated for virtualization such that VF 0
 722                  * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
 723                  * In order to avoid collision we start at the first free queue
 724                  * and continue consuming queues in the same sequence
 725                  */
 726                 if (adapter->vfs_allocated_count) {
 727                         for (; i < adapter->rss_queues; i++)
 728                                 adapter->rx_ring[i]->reg_idx = rbase_offset +
 729                                                                Q_IDX_82576(i);
 730                 }
 731         case e1000_82575:
 732         case e1000_82580:
 733         case e1000_i350:
 734         case e1000_i210:
 735         case e1000_i211:
 736         default:
 737                 for (; i < adapter->num_rx_queues; i++)
 738                         adapter->rx_ring[i]->reg_idx = rbase_offset + i;
 739                 for (; j < adapter->num_tx_queues; j++)
 740                         adapter->tx_ring[j]->reg_idx = rbase_offset + j;
 741                 break;
 742         }
 743 }
 744
 745 /**
 746  *  igb_write_ivar - configure ivar for given MSI-X vector
 747  *  @hw: pointer to the HW structure
 748  *  @msix_vector: vector number we are allocating to a given ring
 749  *  @index: row index of IVAR register to write within IVAR table
 750  *  @offset: column offset of in IVAR, should be multiple of 8
 751  *
 752  *  This function is intended to handle the writing of the IVAR register
 753  *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 754  *  each containing an cause allocation for an Rx and Tx ring, and a
 755  *  variable number of rows depending on the number of queues supported.
 756  **/
 757 static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
 758                            int index, int offset)
 759 {
 760         u32 ivar = array_rd32(E1000_IVAR0, index);
 761
 762         /* clear any bits that are currently set */
 763         ivar &= ~((u32)0xFF << offset);
 764
 765         /* write vector and valid bit */
 766         ivar |= (msix_vector | E1000_IVAR_VALID) << offset;
 767
 768         array_wr32(E1000_IVAR0, index, ivar);
 769 }
 770
 771 #define IGB_N0_QUEUE -1
 772 static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
 773 {
 774         struct igb_adapter *adapter = q_vector->adapter;
 775         struct e1000_hw *hw = &adapter->hw;
 776         int rx_queue = IGB_N0_QUEUE;
 777         int tx_queue = IGB_N0_QUEUE;
 778         u32 msixbm = 0;
 779
 780         if (q_vector->rx.ring)
 781                 rx_queue = q_vector->rx.ring->reg_idx;
 782         if (q_vector->tx.ring)
 783                 tx_queue = q_vector->tx.ring->reg_idx;
 784
 785         switch (hw->mac.type) {
 786         case e1000_82575:
 787                 /* The 82575 assigns vectors using a bitmask, which matches the
 788                    bitmask for the EICR/EIMS/EIMC registers.  To assign one
 789                    or more queues to a vector, we write the appropriate bits
 790                    into the MSIXBM register for that vector. */
 791                 if (rx_queue > IGB_N0_QUEUE)
 792                         msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
 793                 if (tx_queue > IGB_N0_QUEUE)
 794                         msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
 795                 if (!adapter->msix_entries && msix_vector == 0)
 796                         msixbm |= E1000_EIMS_OTHER;
 797                 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
 798                 q_vector->eims_value = msixbm;
 799                 break;
 800         case e1000_82576:
 801                 /*
 802                  * 82576 uses a table that essentially consists of 2 columns
 803                  * with 8 rows.  The ordering is column-major so we use the
 804                  * lower 3 bits as the row index, and the 4th bit as the
 805                  * column offset.
 806                  */
 807                 if (rx_queue > IGB_N0_QUEUE)
 808                         igb_write_ivar(hw, msix_vector,
 809                                        rx_queue & 0x7,
 810                                        (rx_queue & 0x8) << 1);
 811                 if (tx_queue > IGB_N0_QUEUE)
 812                         igb_write_ivar(hw, msix_vector,
 813                                        tx_queue & 0x7,
 814                                        ((tx_queue & 0x8) << 1) + 8);
 815                 q_vector->eims_value = 1 << msix_vector;
 816                 break;
 817         case e1000_82580:
 818         case e1000_i350:
 819         case e1000_i210:
 820         case e1000_i211:
 821                 /*
 822                  * On 82580 and newer adapters the scheme is similar to 82576
 823                  * however instead of ordering column-major we have things
 824                  * ordered row-major.  So we traverse the table by using
 825                  * bit 0 as the column offset, and the remaining bits as the
 826                  * row index.
 827                  */
 828                 if (rx_queue > IGB_N0_QUEUE)
 829                         igb_write_ivar(hw, msix_vector,
 830                                        rx_queue >> 1,
 831                                        (rx_queue & 0x1) << 4);
 832                 if (tx_queue > IGB_N0_QUEUE)
 833                         igb_write_ivar(hw, msix_vector,
 834                                        tx_queue >> 1,
 835                                        ((tx_queue & 0x1) << 4) + 8);
 836                 q_vector->eims_value = 1 << msix_vector;
 837                 break;
 838         default:
 839                 BUG();
 840                 break;
 841         }
 842
 843         /* add q_vector eims value to global eims_enable_mask */
 844         adapter->eims_enable_mask |= q_vector->eims_value;
 845
 846         /* configure q_vector to set itr on first interrupt */
 847         q_vector->set_itr = 1;
 848 }
 849
 850 /**
 851  * igb_configure_msix - Configure MSI-X hardware
 852  *
 853  * igb_configure_msix sets up the hardware to properly
 854  * generate MSI-X interrupts.
 855  **/
 856 static void igb_configure_msix(struct igb_adapter *adapter)
 857 {
 858         u32 tmp;
 859         int i, vector = 0;
 860         struct e1000_hw *hw = &adapter->hw;
 861
 862         adapter->eims_enable_mask = 0;
 863
 864         /* set vector for other causes, i.e. link changes */
 865         switch (hw->mac.type) {
 866         case e1000_82575:
 867                 tmp = rd32(E1000_CTRL_EXT);
 868                 /* enable MSI-X PBA support*/
 869                 tmp |= E1000_CTRL_EXT_PBA_CLR;
 870
 871                 /* Auto-Mask interrupts upon ICR read. */
 872                 tmp |= E1000_CTRL_EXT_EIAME;
 873                 tmp |= E1000_CTRL_EXT_IRCA;
 874
 875                 wr32(E1000_CTRL_EXT, tmp);
 876
 877                 /* enable msix_other interrupt */
 878                 array_wr32(E1000_MSIXBM(0), vector++,
 879                                       E1000_EIMS_OTHER);
 880                 adapter->eims_other = E1000_EIMS_OTHER;
 881
 882                 break;
 883
 884         case e1000_82576:
 885         case e1000_82580:
 886         case e1000_i350:
 887         case e1000_i210:
 888         case e1000_i211:
 889                 /* Turn on MSI-X capability first, or our settings
 890                  * won't stick.  And it will take days to debug. */
 891                 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
 892                                 E1000_GPIE_PBA | E1000_GPIE_EIAME |
 893                                 E1000_GPIE_NSICR);
 894
 895                 /* enable msix_other interrupt */
 896                 adapter->eims_other = 1 << vector;
 897                 tmp = (vector++ | E1000_IVAR_VALID) << 8;
 898
 899                 wr32(E1000_IVAR_MISC, tmp);
 900                 break;
 901         default:
 902                 /* do nothing, since nothing else supports MSI-X */
 903                 break;
 904         } /* switch (hw->mac.type) */
 905
 906         adapter->eims_enable_mask |= adapter->eims_other;
 907
 908         for (i = 0; i < adapter->num_q_vectors; i++)
 909                 igb_assign_vector(adapter->q_vector[i], vector++);
 910
 911         wrfl();
 912 }
 913
 914 /**
 915  * igb_request_msix - Initialize MSI-X interrupts
 916  *
 917  * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 918  * kernel.
 919  **/
 920 static int igb_request_msix(struct igb_adapter *adapter)
 921 {
 922         struct net_device *netdev = adapter->netdev;
 923         struct e1000_hw *hw = &adapter->hw;
 924         int i, err = 0, vector = 0, free_vector = 0;
 925
 926         err = request_irq(adapter->msix_entries[vector].vector,
 927                           igb_msix_other, 0, netdev->name, adapter);
 928         if (err)
 929                 goto err_out;
 930
 931         for (i = 0; i < adapter->num_q_vectors; i++) {
 932                 struct igb_q_vector *q_vector = adapter->q_vector[i];
 933
 934                 vector++;
 935
 936                 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);
 937
 938                 if (q_vector->rx.ring && q_vector->tx.ring)
 939                         sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
 940                                 q_vector->rx.ring->queue_index);
 941                 else if (q_vector->tx.ring)
 942                         sprintf(q_vector->name, "%s-tx-%u", netdev->name,
 943                                 q_vector->tx.ring->queue_index);
 944                 else if (q_vector->rx.ring)
 945                         sprintf(q_vector->name, "%s-rx-%u", netdev->name,
 946                                 q_vector->rx.ring->queue_index);
 947                 else
 948                         sprintf(q_vector->name, "%s-unused", netdev->name);
 949
 950                 err = request_irq(adapter->msix_entries[vector].vector,
 951                                   igb_msix_ring, 0, q_vector->name,
 952                                   q_vector);
 953                 if (err)
 954                         goto err_free;
 955         }
 956
 957         igb_configure_msix(adapter);
 958         return 0;
 959
 960 err_free:
 961         /* free already assigned IRQs */
 962         free_irq(adapter->msix_entries[free_vector++].vector, adapter);
 963
 964         vector--;
 965         for (i = 0; i < vector; i++) {
 966                 free_irq(adapter->msix_entries[free_vector++].vector,
 967                          adapter->q_vector[i]);
 968         }
 969 err_out:
 970         return err;
 971 }
 972
 973 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
 974 {
 975         if (adapter->msix_entries) {
 976                 pci_disable_msix(adapter->pdev);
 977                 kfree(adapter->msix_entries);
 978                 adapter->msix_entries = NULL;
 979         } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
 980                 pci_disable_msi(adapter->pdev);
 981         }
 982 }
 983
 984 /**
 985  * igb_free_q_vector - Free memory allocated for specific interrupt vector
 986  * @adapter: board private structure to initialize
 987  * @v_idx: Index of vector to be freed
 988  *
 989  * This function frees the memory allocated to the q_vector.  In addition if
 990  * NAPI is enabled it will delete any references to the NAPI struct prior
 991  * to freeing the q_vector.
 992  **/
 993 static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx)
 994 {
 995         struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
 996
 997         if (q_vector->tx.ring)
 998                 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL;
 999
1000         if (q_vector->rx.ring)
1001                 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL;
1002
1003         adapter->q_vector[v_idx] = NULL;
1004         netif_napi_del(&q_vector->napi);
1005
1006         /*
1007          * ixgbe_get_stats64() might access the rings on this vector,
1008          * we must wait a grace period before freeing it.
1009          */
1010         kfree_rcu(q_vector, rcu);
1011 }
1012
1013 /**
1014  * igb_free_q_vectors - Free memory allocated for interrupt vectors
1015  * @adapter: board private structure to initialize
1016  *
1017  * This function frees the memory allocated to the q_vectors.  In addition if
1018  * NAPI is enabled it will delete any references to the NAPI struct prior
1019  * to freeing the q_vector.
1020  **/
1021 static void igb_free_q_vectors(struct igb_adapter *adapter)
1022 {
1023         int v_idx = adapter->num_q_vectors;
1024
1025         adapter->num_tx_queues = 0;
1026         adapter->num_rx_queues = 0;
1027         adapter->num_q_vectors = 0;
1028
1029         while (v_idx--)
1030                 igb_free_q_vector(adapter, v_idx);
1031 }
1032
1033 /**
1034  * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1035  *
1036  * This function resets the device so that it has 0 rx queues, tx queues, and
1037  * MSI-X interrupts allocated.
1038  */
1039 static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
1040 {
1041         igb_free_q_vectors(adapter);
1042         igb_reset_interrupt_capability(adapter);
1043 }
1044
1045 /**
1046  * igb_set_interrupt_capability - set MSI or MSI-X if supported
1047  *
1048  * Attempt to configure interrupts using the best available
1049  * capabilities of the hardware and kernel.
1050  **/
1051 static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix)
1052 {
1053         int err;
1054         int numvecs, i;
1055
1056         if (!msix)
1057                 goto msi_only;
1058
1059         /* Number of supported queues. */
1060         adapter->num_rx_queues = adapter->rss_queues;
1061         if (adapter->vfs_allocated_count)
1062                 adapter->num_tx_queues = 1;
1063         else
1064                 adapter->num_tx_queues = adapter->rss_queues;
1065
1066         /* start with one vector for every rx queue */
1067         numvecs = adapter->num_rx_queues;
1068
1069         /* if tx handler is separate add 1 for every tx queue */
1070         if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
1071                 numvecs += adapter->num_tx_queues;
1072
1073         /* store the number of vectors reserved for queues */
1074         adapter->num_q_vectors = numvecs;
1075
1076         /* add 1 vector for link status interrupts */
1077         numvecs++;
1078         adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
1079                                         GFP_KERNEL);
1080
1081         if (!adapter->msix_entries)
1082                 goto msi_only;
1083
1084         for (i = 0; i < numvecs; i++)
1085                 adapter->msix_entries[i].entry = i;
1086
1087         err = pci_enable_msix(adapter->pdev,
1088                               adapter->msix_entries,
1089                               numvecs);
1090         if (err == 0)
1091                 return;
1092
1093         igb_reset_interrupt_capability(adapter);
1094
1095         /* If we can't do MSI-X, try MSI */
1096 msi_only:
1097 #ifdef CONFIG_PCI_IOV
1098         /* disable SR-IOV for non MSI-X configurations */
1099         if (adapter->vf_data) {
1100                 struct e1000_hw *hw = &adapter->hw;
1101                 /* disable iov and allow time for transactions to clear */
1102                 pci_disable_sriov(adapter->pdev);
1103                 msleep(500);
1104
1105                 kfree(adapter->vf_data);
1106                 adapter->vf_data = NULL;
1107                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1108                 wrfl();
1109                 msleep(100);
1110                 dev_info(&adapter->pdev->dev, "IOV Disabled\n");
1111         }
1112 #endif
1113         adapter->vfs_allocated_count = 0;
1114         adapter->rss_queues = 1;
1115         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1116         adapter->num_rx_queues = 1;
1117         adapter->num_tx_queues = 1;
1118         adapter->num_q_vectors = 1;
1119         if (!pci_enable_msi(adapter->pdev))
1120                 adapter->flags |= IGB_FLAG_HAS_MSI;
1121 }
1122
1123 static void igb_add_ring(struct igb_ring *ring,
1124                          struct igb_ring_container *head)
1125 {
1126         head->ring = ring;
1127         head->count++;
1128 }
1129
1130 /**
1131  * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1132  * @adapter: board private structure to initialize
1133  * @v_count: q_vectors allocated on adapter, used for ring interleaving
1134  * @v_idx: index of vector in adapter struct
1135  * @txr_count: total number of Tx rings to allocate
1136  * @txr_idx: index of first Tx ring to allocate
1137  * @rxr_count: total number of Rx rings to allocate
1138  * @rxr_idx: index of first Rx ring to allocate
1139  *
1140  * We allocate one q_vector.  If allocation fails we return -ENOMEM.
1141  **/
1142 static int igb_alloc_q_vector(struct igb_adapter *adapter,
1143                               int v_count, int v_idx,
1144                               int txr_count, int txr_idx,
1145                               int rxr_count, int rxr_idx)
1146 {
1147         struct igb_q_vector *q_vector;
1148         struct igb_ring *ring;
1149         int ring_count, size;
1150
1151         /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1152         if (txr_count > 1 || rxr_count > 1)
1153                 return -ENOMEM;
1154
1155         ring_count = txr_count + rxr_count;
1156         size = sizeof(struct igb_q_vector) +
1157                (sizeof(struct igb_ring) * ring_count);
1158
1159         /* allocate q_vector and rings */
1160         q_vector = kzalloc(size, GFP_KERNEL);
1161         if (!q_vector)
1162                 return -ENOMEM;
1163
1164         /* initialize NAPI */
1165         netif_napi_add(adapter->netdev, &q_vector->napi,
1166                        igb_poll, 64);
1167
1168         /* tie q_vector and adapter together */
1169         adapter->q_vector[v_idx] = q_vector;
1170         q_vector->adapter = adapter;
1171
1172         /* initialize work limits */
1173         q_vector->tx.work_limit = adapter->tx_work_limit;
1174
1175         /* initialize ITR configuration */
1176         q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0);
1177         q_vector->itr_val = IGB_START_ITR;
1178
1179         /* initialize pointer to rings */
1180         ring = q_vector->ring;
1181
1182         if (txr_count) {
1183                 /* assign generic ring traits */
1184                 ring->dev = &adapter->pdev->dev;
1185                 ring->netdev = adapter->netdev;
1186
1187                 /* configure backlink on ring */
1188                 ring->q_vector = q_vector;
1189
1190                 /* update q_vector Tx values */
1191                 igb_add_ring(ring, &q_vector->tx);
1192
1193                 /* For 82575, context index must be unique per ring. */
1194                 if (adapter->hw.mac.type == e1000_82575)
1195                         set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
1196
1197                 /* apply Tx specific ring traits */
1198                 ring->count = adapter->tx_ring_count;
1199                 ring->queue_index = txr_idx;
1200
1201                 /* assign ring to adapter */
1202                 adapter->tx_ring[txr_idx] = ring;
1203
1204                 /* push pointer to next ring */
1205                 ring++;
1206         }
1207
1208         if (rxr_count) {
1209                 /* assign generic ring traits */
1210                 ring->dev = &adapter->pdev->dev;
1211                 ring->netdev = adapter->netdev;
1212
1213                 /* configure backlink on ring */
1214                 ring->q_vector = q_vector;
1215
1216                 /* update q_vector Rx values */
1217                 igb_add_ring(ring, &q_vector->rx);
1218
1219                 /* set flag indicating ring supports SCTP checksum offload */
1220                 if (adapter->hw.mac.type >= e1000_82576)
1221                         set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
1222
1223                 /*
1224                  * On i350, i210, and i211, loopback VLAN packets
1225                  * have the tag byte-swapped.
1226                  * */
1227                 if (adapter->hw.mac.type >= e1000_i350)
1228                         set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags);
1229
1230                 /* apply Rx specific ring traits */
1231                 ring->count = adapter->rx_ring_count;
1232                 ring->queue_index = rxr_idx;
1233
1234                 /* assign ring to adapter */
1235                 adapter->rx_ring[rxr_idx] = ring;
1236         }
1237
1238         return 0;
1239 }
1240
1241
1242 /**
1243  * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1244  * @adapter: board private structure to initialize
1245  *
1246  * We allocate one q_vector per queue interrupt.  If allocation fails we
1247  * return -ENOMEM.
1248  **/
1249 static int igb_alloc_q_vectors(struct igb_adapter *adapter)
1250 {
1251         int q_vectors = adapter->num_q_vectors;
1252         int rxr_remaining = adapter->num_rx_queues;
1253         int txr_remaining = adapter->num_tx_queues;
1254         int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1255         int err;
1256
1257         if (q_vectors >= (rxr_remaining + txr_remaining)) {
1258                 for (; rxr_remaining; v_idx++) {
1259                         err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1260                                                  0, 0, 1, rxr_idx);
1261
1262                         if (err)
1263                                 goto err_out;
1264
1265                         /* update counts and index */
1266                         rxr_remaining--;
1267                         rxr_idx++;
1268                 }
1269         }
1270
1271         for (; v_idx < q_vectors; v_idx++) {
1272                 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1273                 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1274                 err = igb_alloc_q_vector(adapter, q_vectors, v_idx,
1275                                          tqpv, txr_idx, rqpv, rxr_idx);
1276
1277                 if (err)
1278                         goto err_out;
1279
1280                 /* update counts and index */
1281                 rxr_remaining -= rqpv;
1282                 txr_remaining -= tqpv;
1283                 rxr_idx++;
1284                 txr_idx++;
1285         }
1286
1287         return 0;
1288
1289 err_out:
1290         adapter->num_tx_queues = 0;
1291         adapter->num_rx_queues = 0;
1292         adapter->num_q_vectors = 0;
1293
1294         while (v_idx--)
1295                 igb_free_q_vector(adapter, v_idx);
1296
1297         return -ENOMEM;
1298 }
1299
1300 /**
1301  * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1302  *
1303  * This function initializes the interrupts and allocates all of the queues.
1304  **/
1305 static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix)
1306 {
1307         struct pci_dev *pdev = adapter->pdev;
1308         int err;
1309
1310         igb_set_interrupt_capability(adapter, msix);
1311
1312         err = igb_alloc_q_vectors(adapter);
1313         if (err) {
1314                 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
1315                 goto err_alloc_q_vectors;
1316         }
1317
1318         igb_cache_ring_register(adapter);
1319
1320         return 0;
1321
1322 err_alloc_q_vectors:
1323         igb_reset_interrupt_capability(adapter);
1324         return err;
1325 }
1326
1327 /**
1328  * igb_request_irq - initialize interrupts
1329  *
1330  * Attempts to configure interrupts using the best available
1331  * capabilities of the hardware and kernel.
1332  **/
1333 static int igb_request_irq(struct igb_adapter *adapter)
1334 {
1335         struct net_device *netdev = adapter->netdev;
1336         struct pci_dev *pdev = adapter->pdev;
1337         int err = 0;
1338
1339         if (adapter->msix_entries) {
1340                 err = igb_request_msix(adapter);
1341                 if (!err)
1342                         goto request_done;
1343                 /* fall back to MSI */
1344                 igb_free_all_tx_resources(adapter);
1345                 igb_free_all_rx_resources(adapter);
1346
1347                 igb_clear_interrupt_scheme(adapter);
1348                 err = igb_init_interrupt_scheme(adapter, false);
1349                 if (err)
1350                         goto request_done;
1351
1352                 igb_setup_all_tx_resources(adapter);
1353                 igb_setup_all_rx_resources(adapter);
1354                 igb_configure(adapter);
1355         }
1356
1357         igb_assign_vector(adapter->q_vector[0], 0);
1358
1359         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1360                 err = request_irq(pdev->irq, igb_intr_msi, 0,
1361                                   netdev->name, adapter);
1362                 if (!err)
1363                         goto request_done;
1364
1365                 /* fall back to legacy interrupts */
1366                 igb_reset_interrupt_capability(adapter);
1367                 adapter->flags &= ~IGB_FLAG_HAS_MSI;
1368         }
1369
1370         err = request_irq(pdev->irq, igb_intr, IRQF_SHARED,
1371                           netdev->name, adapter);
1372
1373         if (err)
1374                 dev_err(&pdev->dev, "Error %d getting interrupt\n",
1375                         err);
1376
1377 request_done:
1378         return err;
1379 }
1380
1381 static void igb_free_irq(struct igb_adapter *adapter)
1382 {
1383         if (adapter->msix_entries) {
1384                 int vector = 0, i;
1385
1386                 free_irq(adapter->msix_entries[vector++].vector, adapter);
1387
1388                 for (i = 0; i < adapter->num_q_vectors; i++)
1389                         free_irq(adapter->msix_entries[vector++].vector,
1390                                  adapter->q_vector[i]);
1391         } else {
1392                 free_irq(adapter->pdev->irq, adapter);
1393         }
1394 }
1395
1396 /**
1397  * igb_irq_disable - Mask off interrupt generation on the NIC
1398  * @adapter: board private structure
1399  **/
1400 static void igb_irq_disable(struct igb_adapter *adapter)
1401 {
1402         struct e1000_hw *hw = &adapter->hw;
1403
1404         /*
1405          * we need to be careful when disabling interrupts.  The VFs are also
1406          * mapped into these registers and so clearing the bits can cause
1407          * issues on the VF drivers so we only need to clear what we set
1408          */
1409         if (adapter->msix_entries) {
1410                 u32 regval = rd32(E1000_EIAM);
1411                 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
1412                 wr32(E1000_EIMC, adapter->eims_enable_mask);
1413                 regval = rd32(E1000_EIAC);
1414                 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1415         }
1416
1417         wr32(E1000_IAM, 0);
1418         wr32(E1000_IMC, ~0);
1419         wrfl();
1420         if (adapter->msix_entries) {
1421                 int i;
1422                 for (i = 0; i < adapter->num_q_vectors; i++)
1423                         synchronize_irq(adapter->msix_entries[i].vector);
1424         } else {
1425                 synchronize_irq(adapter->pdev->irq);
1426         }
1427 }
1428
1429 /**
1430  * igb_irq_enable - Enable default interrupt generation settings
1431  * @adapter: board private structure
1432  **/
1433 static void igb_irq_enable(struct igb_adapter *adapter)
1434 {
1435         struct e1000_hw *hw = &adapter->hw;
1436
1437         if (adapter->msix_entries) {
1438                 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA;
1439                 u32 regval = rd32(E1000_EIAC);
1440                 wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
1441                 regval = rd32(E1000_EIAM);
1442                 wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
1443                 wr32(E1000_EIMS, adapter->eims_enable_mask);
1444                 if (adapter->vfs_allocated_count) {
1445                         wr32(E1000_MBVFIMR, 0xFF);
1446                         ims |= E1000_IMS_VMMB;
1447                 }
1448                 wr32(E1000_IMS, ims);
1449         } else {
1450                 wr32(E1000_IMS, IMS_ENABLE_MASK |
1451                                 E1000_IMS_DRSTA);
1452                 wr32(E1000_IAM, IMS_ENABLE_MASK |
1453                                 E1000_IMS_DRSTA);
1454         }
1455 }
1456
1457 static void igb_update_mng_vlan(struct igb_adapter *adapter)
1458 {
1459         struct e1000_hw *hw = &adapter->hw;
1460         u16 vid = adapter->hw.mng_cookie.vlan_id;
1461         u16 old_vid = adapter->mng_vlan_id;
1462
1463         if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
1464                 /* add VID to filter table */
1465                 igb_vfta_set(hw, vid, true);
1466                 adapter->mng_vlan_id = vid;
1467         } else {
1468                 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1469         }
1470
1471         if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
1472             (vid != old_vid) &&
1473             !test_bit(old_vid, adapter->active_vlans)) {
1474                 /* remove VID from filter table */
1475                 igb_vfta_set(hw, old_vid, false);
1476         }
1477 }
1478
1479 /**
1480  * igb_release_hw_control - release control of the h/w to f/w
1481  * @adapter: address of board private structure
1482  *
1483  * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1484  * For ASF and Pass Through versions of f/w this means that the
1485  * driver is no longer loaded.
1486  *
1487  **/
1488 static void igb_release_hw_control(struct igb_adapter *adapter)
1489 {
1490         struct e1000_hw *hw = &adapter->hw;
1491         u32 ctrl_ext;
1492
1493         /* Let firmware take over control of h/w */
1494         ctrl_ext = rd32(E1000_CTRL_EXT);
1495         wr32(E1000_CTRL_EXT,
1496                         ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
1497 }
1498
1499 /**
1500  * igb_get_hw_control - get control of the h/w from f/w
1501  * @adapter: address of board private structure
1502  *
1503  * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1504  * For ASF and Pass Through versions of f/w this means that
1505  * the driver is loaded.
1506  *
1507  **/
1508 static void igb_get_hw_control(struct igb_adapter *adapter)
1509 {
1510         struct e1000_hw *hw = &adapter->hw;
1511         u32 ctrl_ext;
1512
1513         /* Let firmware know the driver has taken over */
1514         ctrl_ext = rd32(E1000_CTRL_EXT);
1515         wr32(E1000_CTRL_EXT,
1516                         ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
1517 }
1518
1519 /**
1520  * igb_configure - configure the hardware for RX and TX
1521  * @adapter: private board structure
1522  **/
1523 static void igb_configure(struct igb_adapter *adapter)
1524 {
1525         struct net_device *netdev = adapter->netdev;
1526         int i;
1527
1528         igb_get_hw_control(adapter);
1529         igb_set_rx_mode(netdev);
1530
1531         igb_restore_vlan(adapter);
1532
1533         igb_setup_tctl(adapter);
1534         igb_setup_mrqc(adapter);
1535         igb_setup_rctl(adapter);
1536
1537         igb_configure_tx(adapter);
1538         igb_configure_rx(adapter);
1539
1540         igb_rx_fifo_flush_82575(&adapter->hw);
1541
1542         /* call igb_desc_unused which always leaves
1543          * at least 1 descriptor unused to make sure
1544          * next_to_use != next_to_clean */
1545         for (i = 0; i < adapter->num_rx_queues; i++) {
1546                 struct igb_ring *ring = adapter->rx_ring[i];
1547                 igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1548         }
1549 }
1550
1551 /**
1552  * igb_power_up_link - Power up the phy/serdes link
1553  * @adapter: address of board private structure
1554  **/
1555 void igb_power_up_link(struct igb_adapter *adapter)
1556 {
1557         igb_reset_phy(&adapter->hw);
1558
1559         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1560                 igb_power_up_phy_copper(&adapter->hw);
1561         else
1562                 igb_power_up_serdes_link_82575(&adapter->hw);
1563 }
1564
1565 /**
1566  * igb_power_down_link - Power down the phy/serdes link
1567  * @adapter: address of board private structure
1568  */
1569 static void igb_power_down_link(struct igb_adapter *adapter)
1570 {
1571         if (adapter->hw.phy.media_type == e1000_media_type_copper)
1572                 igb_power_down_phy_copper_82575(&adapter->hw);
1573         else
1574                 igb_shutdown_serdes_link_82575(&adapter->hw);
1575 }
1576
1577 /**
1578  * igb_up - Open the interface and prepare it to handle traffic
1579  * @adapter: board private structure
1580  **/
1581 int igb_up(struct igb_adapter *adapter)
1582 {
1583         struct e1000_hw *hw = &adapter->hw;
1584         int i;
1585
1586         /* hardware has been reset, we need to reload some things */
1587         igb_configure(adapter);
1588
1589         clear_bit(__IGB_DOWN, &adapter->state);
1590
1591         for (i = 0; i < adapter->num_q_vectors; i++)
1592                 napi_enable(&(adapter->q_vector[i]->napi));
1593
1594         if (adapter->msix_entries)
1595                 igb_configure_msix(adapter);
1596         else
1597                 igb_assign_vector(adapter->q_vector[0], 0);
1598
1599         /* Clear any pending interrupts. */
1600         rd32(E1000_ICR);
1601         igb_irq_enable(adapter);
1602
1603         /* notify VFs that reset has been completed */
1604         if (adapter->vfs_allocated_count) {
1605                 u32 reg_data = rd32(E1000_CTRL_EXT);
1606                 reg_data |= E1000_CTRL_EXT_PFRSTD;
1607                 wr32(E1000_CTRL_EXT, reg_data);
1608         }
1609
1610         netif_tx_start_all_queues(adapter->netdev);
1611
1612         /* start the watchdog. */
1613         hw->mac.get_link_status = 1;
1614         schedule_work(&adapter->watchdog_task);
1615
1616         return 0;
1617 }
1618
1619 void igb_down(struct igb_adapter *adapter)
1620 {
1621         struct net_device *netdev = adapter->netdev;
1622         struct e1000_hw *hw = &adapter->hw;
1623         u32 tctl, rctl;
1624         int i;
1625
1626         /* signal that we're down so the interrupt handler does not
1627          * reschedule our watchdog timer */
1628         set_bit(__IGB_DOWN, &adapter->state);
1629
1630         /* disable receives in the hardware */
1631         rctl = rd32(E1000_RCTL);
1632         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1633         /* flush and sleep below */
1634
1635         netif_tx_stop_all_queues(netdev);
1636
1637         /* disable transmits in the hardware */
1638         tctl = rd32(E1000_TCTL);
1639         tctl &= ~E1000_TCTL_EN;
1640         wr32(E1000_TCTL, tctl);
1641         /* flush both disables and wait for them to finish */
1642         wrfl();
1643         msleep(10);
1644
1645         for (i = 0; i < adapter->num_q_vectors; i++)
1646                 napi_disable(&(adapter->q_vector[i]->napi));
1647
1648         igb_irq_disable(adapter);
1649
1650         del_timer_sync(&adapter->watchdog_timer);
1651         del_timer_sync(&adapter->phy_info_timer);
1652
1653         netif_carrier_off(netdev);
1654
1655         /* record the stats before reset*/
1656         spin_lock(&adapter->stats64_lock);
1657         igb_update_stats(adapter, &adapter->stats64);
1658         spin_unlock(&adapter->stats64_lock);
1659
1660         adapter->link_speed = 0;
1661         adapter->link_duplex = 0;
1662
1663         if (!pci_channel_offline(adapter->pdev))
1664                 igb_reset(adapter);
1665         igb_clean_all_tx_rings(adapter);
1666         igb_clean_all_rx_rings(adapter);
1667 #ifdef CONFIG_IGB_DCA
1668
1669         /* since we reset the hardware DCA settings were cleared */
1670         igb_setup_dca(adapter);
1671 #endif
1672 }
1673
1674 void igb_reinit_locked(struct igb_adapter *adapter)
1675 {
1676         WARN_ON(in_interrupt());
1677         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
1678                 msleep(1);
1679         igb_down(adapter);
1680         igb_up(adapter);
1681         clear_bit(__IGB_RESETTING, &adapter->state);
1682 }
1683
1684 void igb_reset(struct igb_adapter *adapter)
1685 {
1686         struct pci_dev *pdev = adapter->pdev;
1687         struct e1000_hw *hw = &adapter->hw;
1688         struct e1000_mac_info *mac = &hw->mac;
1689         struct e1000_fc_info *fc = &hw->fc;
1690         u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm;
1691
1692         /* Repartition Pba for greater than 9k mtu
1693          * To take effect CTRL.RST is required.
1694          */
1695         switch (mac->type) {
1696         case e1000_i350:
1697         case e1000_82580:
1698                 pba = rd32(E1000_RXPBS);
1699                 pba = igb_rxpbs_adjust_82580(pba);
1700                 break;
1701         case e1000_82576:
1702                 pba = rd32(E1000_RXPBS);
1703                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1704                 break;
1705         case e1000_82575:
1706         case e1000_i210:
1707         case e1000_i211:
1708         default:
1709                 pba = E1000_PBA_34K;
1710                 break;
1711         }
1712
1713         if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
1714             (mac->type < e1000_82576)) {
1715                 /* adjust PBA for jumbo frames */
1716                 wr32(E1000_PBA, pba);
1717
1718                 /* To maintain wire speed transmits, the Tx FIFO should be
1719                  * large enough to accommodate two full transmit packets,
1720                  * rounded up to the next 1KB and expressed in KB.  Likewise,
1721                  * the Rx FIFO should be large enough to accommodate at least
1722                  * one full receive packet and is similarly rounded up and
1723                  * expressed in KB. */
1724                 pba = rd32(E1000_PBA);
1725                 /* upper 16 bits has Tx packet buffer allocation size in KB */
1726                 tx_space = pba >> 16;
1727                 /* lower 16 bits has Rx packet buffer allocation size in KB */
1728                 pba &= 0xffff;
1729                 /* the tx fifo also stores 16 bytes of information about the tx
1730                  * but don't include ethernet FCS because hardware appends it */
1731                 min_tx_space = (adapter->max_frame_size +
1732                                 sizeof(union e1000_adv_tx_desc) -
1733                                 ETH_FCS_LEN) * 2;
1734                 min_tx_space = ALIGN(min_tx_space, 1024);
1735                 min_tx_space >>= 10;
1736                 /* software strips receive CRC, so leave room for it */
1737                 min_rx_space = adapter->max_frame_size;
1738                 min_rx_space = ALIGN(min_rx_space, 1024);
1739                 min_rx_space >>= 10;
1740
1741                 /* If current Tx allocation is less than the min Tx FIFO size,
1742                  * and the min Tx FIFO size is less than the current Rx FIFO
1743                  * allocation, take space away from current Rx allocation */
1744                 if (tx_space < min_tx_space &&
1745                     ((min_tx_space - tx_space) < pba)) {
1746                         pba = pba - (min_tx_space - tx_space);
1747
1748                         /* if short on rx space, rx wins and must trump tx
1749                          * adjustment */
1750                         if (pba < min_rx_space)
1751                                 pba = min_rx_space;
1752                 }
1753                 wr32(E1000_PBA, pba);
1754         }
1755
1756         /* flow control settings */
1757         /* The high water mark must be low enough to fit one full frame
1758          * (or the size used for early receive) above it in the Rx FIFO.
1759          * Set it to the lower of:
1760          * - 90% of the Rx FIFO size, or
1761          * - the full Rx FIFO size minus one full frame */
1762         hwm = min(((pba << 10) * 9 / 10),
1763                         ((pba << 10) - 2 * adapter->max_frame_size));
1764
1765         fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
1766         fc->low_water = fc->high_water - 16;
1767         fc->pause_time = 0xFFFF;
1768         fc->send_xon = 1;
1769         fc->current_mode = fc->requested_mode;
1770
1771         /* disable receive for all VFs and wait one second */
1772         if (adapter->vfs_allocated_count) {
1773                 int i;
1774                 for (i = 0 ; i < adapter->vfs_allocated_count; i++)
1775                         adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1776
1777                 /* ping all the active vfs to let them know we are going down */
1778                 igb_ping_all_vfs(adapter);
1779
1780                 /* disable transmits and receives */
1781                 wr32(E1000_VFRE, 0);
1782                 wr32(E1000_VFTE, 0);
1783         }
1784
1785         /* Allow time for pending master requests to run */
1786         hw->mac.ops.reset_hw(hw);
1787         wr32(E1000_WUC, 0);
1788
1789         if (hw->mac.ops.init_hw(hw))
1790                 dev_err(&pdev->dev, "Hardware Error\n");
1791
1792         /*
1793          * Flow control settings reset on hardware reset, so guarantee flow
1794          * control is off when forcing speed.
1795          */
1796         if (!hw->mac.autoneg)
1797                 igb_force_mac_fc(hw);
1798
1799         igb_init_dmac(adapter, pba);
1800 #ifdef CONFIG_IGB_HWMON
1801         /* Re-initialize the thermal sensor on i350 devices. */
1802         if (!test_bit(__IGB_DOWN, &adapter->state)) {
1803                 if (mac->type == e1000_i350 && hw->bus.func == 0) {
1804                         /* If present, re-initialize the external thermal sensor
1805                          * interface.
1806                          */
1807                         if (adapter->ets)
1808                                 mac->ops.init_thermal_sensor_thresh(hw);
1809                 }
1810         }
1811 #endif
1812         if (!netif_running(adapter->netdev))
1813                 igb_power_down_link(adapter);
1814
1815         igb_update_mng_vlan(adapter);
1816
1817         /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
1818         wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
1819
1820         /* Re-enable PTP, where applicable. */
1821         igb_ptp_reset(adapter);
1822
1823         igb_get_phy_info(hw);
1824 }
1825
1826 static netdev_features_t igb_fix_features(struct net_device *netdev,
1827         netdev_features_t features)
1828 {
1829         /*
1830          * Since there is no support for separate rx/tx vlan accel
1831          * enable/disable make sure tx flag is always in same state as rx.
1832          */
1833         if (features & NETIF_F_HW_VLAN_RX)
1834                 features |= NETIF_F_HW_VLAN_TX;
1835         else
1836                 features &= ~NETIF_F_HW_VLAN_TX;
1837
1838         return features;
1839 }
1840
1841 static int igb_set_features(struct net_device *netdev,
1842         netdev_features_t features)
1843 {
1844         netdev_features_t changed = netdev->features ^ features;
1845         struct igb_adapter *adapter = netdev_priv(netdev);
1846
1847         if (changed & NETIF_F_HW_VLAN_RX)
1848                 igb_vlan_mode(netdev, features);
1849
1850         if (!(changed & NETIF_F_RXALL))
1851                 return 0;
1852
1853         netdev->features = features;
1854
1855         if (netif_running(netdev))
1856                 igb_reinit_locked(adapter);
1857         else
1858                 igb_reset(adapter);
1859
1860         return 0;
1861 }
1862
1863 static const struct net_device_ops igb_netdev_ops = {
1864         .ndo_open               = igb_open,
1865         .ndo_stop               = igb_close,
1866         .ndo_start_xmit         = igb_xmit_frame,
1867         .ndo_get_stats64        = igb_get_stats64,
1868         .ndo_set_rx_mode        = igb_set_rx_mode,
1869         .ndo_set_mac_address    = igb_set_mac,
1870         .ndo_change_mtu         = igb_change_mtu,
1871         .ndo_do_ioctl           = igb_ioctl,
1872         .ndo_tx_timeout         = igb_tx_timeout,
1873         .ndo_validate_addr      = eth_validate_addr,
1874         .ndo_vlan_rx_add_vid    = igb_vlan_rx_add_vid,
1875         .ndo_vlan_rx_kill_vid   = igb_vlan_rx_kill_vid,
1876         .ndo_set_vf_mac         = igb_ndo_set_vf_mac,
1877         .ndo_set_vf_vlan        = igb_ndo_set_vf_vlan,
1878         .ndo_set_vf_tx_rate     = igb_ndo_set_vf_bw,
1879         .ndo_get_vf_config      = igb_ndo_get_vf_config,
1880 #ifdef CONFIG_NET_POLL_CONTROLLER
1881         .ndo_poll_controller    = igb_netpoll,
1882 #endif
1883         .ndo_fix_features       = igb_fix_features,
1884         .ndo_set_features       = igb_set_features,
1885 };
1886
1887 /**
1888  * igb_set_fw_version - Configure version string for ethtool
1889  * @adapter: adapter struct
1890  *
1891  **/
1892 void igb_set_fw_version(struct igb_adapter *adapter)
1893 {
1894         struct e1000_hw *hw = &adapter->hw;
1895         struct e1000_fw_version fw;
1896
1897         igb_get_fw_version(hw, &fw);
1898
1899         switch (hw->mac.type) {
1900         case e1000_i211:
1901                 snprintf(adapter->fw_version, sizeof(adapter->fw_version),
1902                          "%2d.%2d-%d",
1903                          fw.invm_major, fw.invm_minor, fw.invm_img_type);
1904                 break;
1905
1906         default:
1907                 /* if option is rom valid, display its version too */
1908                 if (fw.or_valid) {
1909                         snprintf(adapter->fw_version,
1910                                  sizeof(adapter->fw_version),
1911                                  "%d.%d, 0x%08x, %d.%d.%d",
1912                                  fw.eep_major, fw.eep_minor, fw.etrack_id,
1913                                  fw.or_major, fw.or_build, fw.or_patch);
1914                 /* no option rom */
1915                 } else {
1916                         snprintf(adapter->fw_version,
1917                                  sizeof(adapter->fw_version),
1918                                  "%d.%d, 0x%08x",
1919                                  fw.eep_major, fw.eep_minor, fw.etrack_id);
1920                 }
1921                 break;
1922         }
1923         return;
1924 }
1925
1926 static const struct i2c_board_info i350_sensor_info = {
1927         I2C_BOARD_INFO("i350bb", 0Xf8),
1928 };
1929
1930 /*  igb_init_i2c - Init I2C interface
1931  *  @adapter: pointer to adapter structure
1932  *
1933  */
1934 static s32 igb_init_i2c(struct igb_adapter *adapter)
1935 {
1936         s32 status = E1000_SUCCESS;
1937
1938         /* I2C interface supported on i350 devices */
1939         if (adapter->hw.mac.type != e1000_i350)
1940                 return E1000_SUCCESS;
1941
1942         /* Initialize the i2c bus which is controlled by the registers.
1943          * This bus will use the i2c_algo_bit structue that implements
1944          * the protocol through toggling of the 4 bits in the register.
1945          */
1946         adapter->i2c_adap.owner = THIS_MODULE;
1947         adapter->i2c_algo = igb_i2c_algo;
1948         adapter->i2c_algo.data = adapter;
1949         adapter->i2c_adap.algo_data = &adapter->i2c_algo;
1950         adapter->i2c_adap.dev.parent = &adapter->pdev->dev;
1951         strlcpy(adapter->i2c_adap.name, "igb BB",
1952                 sizeof(adapter->i2c_adap.name));
1953         status = i2c_bit_add_bus(&adapter->i2c_adap);
1954         return status;
1955 }
1956
1957 /**
1958  * igb_probe - Device Initialization Routine
1959  * @pdev: PCI device information struct
1960  * @ent: entry in igb_pci_tbl
1961  *
1962  * Returns 0 on success, negative on failure
1963  *
1964  * igb_probe initializes an adapter identified by a pci_dev structure.
1965  * The OS initialization, configuring of the adapter private structure,
1966  * and a hardware reset occur.
1967  **/
1968 static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1969 {
1970         struct net_device *netdev;
1971         struct igb_adapter *adapter;
1972         struct e1000_hw *hw;
1973         u16 eeprom_data = 0;
1974         s32 ret_val;
1975         static int global_quad_port_a; /* global quad port a indication */
1976         const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
1977         unsigned long mmio_start, mmio_len;
1978         int err, pci_using_dac;
1979         u8 part_str[E1000_PBANUM_LENGTH];
1980
1981         /* Catch broken hardware that put the wrong VF device ID in
1982          * the PCIe SR-IOV capability.
1983          */
1984         if (pdev->is_virtfn) {
1985                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
1986                         pci_name(pdev), pdev->vendor, pdev->device);
1987                 return -EINVAL;
1988         }
1989
1990         err = pci_enable_device_mem(pdev);
1991         if (err)
1992                 return err;
1993
1994         pci_using_dac = 0;
1995         err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1996         if (!err) {
1997                 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1998                 if (!err)
1999                         pci_using_dac = 1;
2000         } else {
2001                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
2002                 if (err) {
2003                         err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
2004                         if (err) {
2005                                 dev_err(&pdev->dev, "No usable DMA "
2006                                         "configuration, aborting\n");
2007                                 goto err_dma;
2008                         }
2009                 }
2010         }
2011
2012         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
2013                                            IORESOURCE_MEM),
2014                                            igb_driver_name);
2015         if (err)
2016                 goto err_pci_reg;
2017
2018         pci_enable_pcie_error_reporting(pdev);
2019
2020         pci_set_master(pdev);
2021         pci_save_state(pdev);
2022
2023         err = -ENOMEM;
2024         netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
2025                                    IGB_MAX_TX_QUEUES);
2026         if (!netdev)
2027                 goto err_alloc_etherdev;
2028
2029         SET_NETDEV_DEV(netdev, &pdev->dev);
2030
2031         pci_set_drvdata(pdev, netdev);
2032         adapter = netdev_priv(netdev);
2033         adapter->netdev = netdev;
2034         adapter->pdev = pdev;
2035         hw = &adapter->hw;
2036         hw->back = adapter;
2037         adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
2038
2039         mmio_start = pci_resource_start(pdev, 0);
2040         mmio_len = pci_resource_len(pdev, 0);
2041
2042         err = -EIO;
2043         hw->hw_addr = ioremap(mmio_start, mmio_len);
2044         if (!hw->hw_addr)
2045                 goto err_ioremap;
2046
2047         netdev->netdev_ops = &igb_netdev_ops;
2048         igb_set_ethtool_ops(netdev);
2049         netdev->watchdog_timeo = 5 * HZ;
2050
2051         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2052
2053         netdev->mem_start = mmio_start;
2054         netdev->mem_end = mmio_start + mmio_len;
2055
2056         /* PCI config space info */
2057         hw->vendor_id = pdev->vendor;
2058         hw->device_id = pdev->device;
2059         hw->revision_id = pdev->revision;
2060         hw->subsystem_vendor_id = pdev->subsystem_vendor;
2061         hw->subsystem_device_id = pdev->subsystem_device;
2062
2063         /* Copy the default MAC, PHY and NVM function pointers */
2064         memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
2065         memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
2066         memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
2067         /* Initialize skew-specific constants */
2068         err = ei->get_invariants(hw);
2069         if (err)
2070                 goto err_sw_init;
2071
2072         /* setup the private structure */
2073         err = igb_sw_init(adapter);
2074         if (err)
2075                 goto err_sw_init;
2076
2077         igb_get_bus_info_pcie(hw);
2078
2079         hw->phy.autoneg_wait_to_complete = false;
2080
2081         /* Copper options */
2082         if (hw->phy.media_type == e1000_media_type_copper) {
2083                 hw->phy.mdix = AUTO_ALL_MODES;
2084                 hw->phy.disable_polarity_correction = false;
2085                 hw->phy.ms_type = e1000_ms_hw_default;
2086         }
2087
2088         if (igb_check_reset_block(hw))
2089                 dev_info(&pdev->dev,
2090                         "PHY reset is blocked due to SOL/IDER session.\n");
2091
2092         /*
2093          * features is initialized to 0 in allocation, it might have bits
2094          * set by igb_sw_init so we should use an or instead of an
2095          * assignment.
2096          */
2097         netdev->features |= NETIF_F_SG |
2098                             NETIF_F_IP_CSUM |
2099                             NETIF_F_IPV6_CSUM |
2100                             NETIF_F_TSO |
2101                             NETIF_F_TSO6 |
2102                             NETIF_F_RXHASH |
2103                             NETIF_F_RXCSUM |
2104                             NETIF_F_HW_VLAN_RX |
2105                             NETIF_F_HW_VLAN_TX;
2106
2107         /* copy netdev features into list of user selectable features */
2108         netdev->hw_features |= netdev->features;
2109         netdev->hw_features |= NETIF_F_RXALL;
2110
2111         /* set this bit last since it cannot be part of hw_features */
2112         netdev->features |= NETIF_F_HW_VLAN_FILTER;
2113
2114         netdev->vlan_features |= NETIF_F_TSO |
2115                                  NETIF_F_TSO6 |
2116                                  NETIF_F_IP_CSUM |
2117                                  NETIF_F_IPV6_CSUM |
2118                                  NETIF_F_SG;
2119
2120         netdev->priv_flags |= IFF_SUPP_NOFCS;
2121
2122         if (pci_using_dac) {
2123                 netdev->features |= NETIF_F_HIGHDMA;
2124                 netdev->vlan_features |= NETIF_F_HIGHDMA;
2125         }
2126
2127         if (hw->mac.type >= e1000_82576) {
2128                 netdev->hw_features |= NETIF_F_SCTP_CSUM;
2129                 netdev->features |= NETIF_F_SCTP_CSUM;
2130         }
2131
2132         netdev->priv_flags |= IFF_UNICAST_FLT;
2133
2134         adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2135
2136         /* before reading the NVM, reset the controller to put the device in a
2137          * known good starting state */
2138         hw->mac.ops.reset_hw(hw);
2139
2140         /*
2141          * make sure the NVM is good , i211 parts have special NVM that
2142          * doesn't contain a checksum
2143          */
2144         if (hw->mac.type != e1000_i211) {
2145                 if (hw->nvm.ops.validate(hw) < 0) {
2146                         dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
2147                         err = -EIO;
2148                         goto err_eeprom;
2149                 }
2150         }
2151
2152         /* copy the MAC address out of the NVM */
2153         if (hw->mac.ops.read_mac_addr(hw))
2154                 dev_err(&pdev->dev, "NVM Read Error\n");
2155
2156         memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
2157
2158         if (!is_valid_ether_addr(netdev->dev_addr)) {
2159                 dev_err(&pdev->dev, "Invalid MAC Address\n");
2160                 err = -EIO;
2161                 goto err_eeprom;
2162         }
2163
2164         /* get firmware version for ethtool -i */
2165         igb_set_fw_version(adapter);
2166
2167         setup_timer(&adapter->watchdog_timer, igb_watchdog,
2168                     (unsigned long) adapter);
2169         setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2170                     (unsigned long) adapter);
2171
2172         INIT_WORK(&adapter->reset_task, igb_reset_task);
2173         INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
2174
2175         /* Initialize link properties that are user-changeable */
2176         adapter->fc_autoneg = true;
2177         hw->mac.autoneg = true;
2178         hw->phy.autoneg_advertised = 0x2f;
2179
2180         hw->fc.requested_mode = e1000_fc_default;
2181         hw->fc.current_mode = e1000_fc_default;
2182
2183         igb_validate_mdi_setting(hw);
2184
2185         /* By default, support wake on port A */
2186         if (hw->bus.func == 0)
2187                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2188
2189         /* Check the NVM for wake support on non-port A ports */
2190         if (hw->mac.type >= e1000_82580)
2191                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2192                                  NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2193                                  &eeprom_data);
2194         else if (hw->bus.func == 1)
2195                 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2196
2197         if (eeprom_data & IGB_EEPROM_APME)
2198                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2199
2200         /* now that we have the eeprom settings, apply the special cases where
2201          * the eeprom may be wrong or the board simply won't support wake on
2202          * lan on a particular port */
2203         switch (pdev->device) {
2204         case E1000_DEV_ID_82575GB_QUAD_COPPER:
2205                 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2206                 break;
2207         case E1000_DEV_ID_82575EB_FIBER_SERDES:
2208         case E1000_DEV_ID_82576_FIBER:
2209         case E1000_DEV_ID_82576_SERDES:
2210                 /* Wake events only supported on port A for dual fiber
2211                  * regardless of eeprom setting */
2212                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
2213                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2214                 break;
2215         case E1000_DEV_ID_82576_QUAD_COPPER:
2216         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2217                 /* if quad port adapter, disable WoL on all but port A */
2218                 if (global_quad_port_a != 0)
2219                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2220                 else
2221                         adapter->flags |= IGB_FLAG_QUAD_PORT_A;
2222                 /* Reset for multiple quad port adapters */
2223                 if (++global_quad_port_a == 4)
2224                         global_quad_port_a = 0;
2225                 break;
2226         default:
2227                 /* If the device can't wake, don't set software support */
2228                 if (!device_can_wakeup(&adapter->pdev->dev))
2229                         adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED;
2230         }
2231
2232         /* initialize the wol settings based on the eeprom settings */
2233         if (adapter->flags & IGB_FLAG_WOL_SUPPORTED)
2234                 adapter->wol |= E1000_WUFC_MAG;
2235
2236         /* Some vendors want WoL disabled by default, but still supported */
2237         if ((hw->mac.type == e1000_i350) &&
2238             (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
2239                 adapter->flags |= IGB_FLAG_WOL_SUPPORTED;
2240                 adapter->wol = 0;
2241         }
2242
2243         device_set_wakeup_enable(&adapter->pdev->dev,
2244                                  adapter->flags & IGB_FLAG_WOL_SUPPORTED);
2245
2246         /* reset the hardware with the new settings */
2247         igb_reset(adapter);
2248
2249         /* Init the I2C interface */
2250         err = igb_init_i2c(adapter);
2251         if (err) {
2252                 dev_err(&pdev->dev, "failed to init i2c interface\n");
2253                 goto err_eeprom;
2254         }
2255
2256         /* let the f/w know that the h/w is now under the control of the
2257          * driver. */
2258         igb_get_hw_control(adapter);
2259
2260         strcpy(netdev->name, "eth%d");
2261         err = register_netdev(netdev);
2262         if (err)
2263                 goto err_register;
2264
2265         /* carrier off reporting is important to ethtool even BEFORE open */
2266         netif_carrier_off(netdev);
2267
2268 #ifdef CONFIG_IGB_DCA
2269         if (dca_add_requester(&pdev->dev) == 0) {
2270                 adapter->flags |= IGB_FLAG_DCA_ENABLED;
2271                 dev_info(&pdev->dev, "DCA enabled\n");
2272                 igb_setup_dca(adapter);
2273         }
2274
2275 #endif
2276 #ifdef CONFIG_IGB_HWMON
2277         /* Initialize the thermal sensor on i350 devices. */
2278         if (hw->mac.type == e1000_i350 && hw->bus.func == 0) {
2279                 u16 ets_word;
2280
2281                 /*
2282                  * Read the NVM to determine if this i350 device supports an
2283                  * external thermal sensor.
2284                  */
2285                 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word);
2286                 if (ets_word != 0x0000 && ets_word != 0xFFFF)
2287                         adapter->ets = true;
2288                 else
2289                         adapter->ets = false;
2290                 if (igb_sysfs_init(adapter))
2291                         dev_err(&pdev->dev,
2292                                 "failed to allocate sysfs resources\n");
2293         } else {
2294                 adapter->ets = false;
2295         }
2296 #endif
2297         /* do hw tstamp init after resetting */
2298         igb_ptp_init(adapter);
2299
2300         dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
2301         /* print bus type/speed/width info */
2302         dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2303                  netdev->name,
2304                  ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2305                   (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2306                                                             "unknown"),
2307                  ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
2308                   (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
2309                   (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
2310                    "unknown"),
2311                  netdev->dev_addr);
2312
2313         ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
2314         if (ret_val)
2315                 strcpy(part_str, "Unknown");
2316         dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2317         dev_info(&pdev->dev,
2318                 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
2319                 adapter->msix_entries ? "MSI-X" :
2320                 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2321                 adapter->num_rx_queues, adapter->num_tx_queues);
2322         switch (hw->mac.type) {
2323         case e1000_i350:
2324         case e1000_i210:
2325         case e1000_i211:
2326                 igb_set_eee_i350(hw);
2327                 break;
2328         default:
2329                 break;
2330         }
2331
2332         pm_runtime_put_noidle(&pdev->dev);
2333         return 0;
2334
2335 err_register:
2336         igb_release_hw_control(adapter);
2337         memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap));
2338 err_eeprom:
2339         if (!igb_check_reset_block(hw))
2340                 igb_reset_phy(hw);
2341
2342         if (hw->flash_address)
2343                 iounmap(hw->flash_address);
2344 err_sw_init:
2345         igb_clear_interrupt_scheme(adapter);
2346         iounmap(hw->hw_addr);
2347 err_ioremap:
2348         free_netdev(netdev);
2349 err_alloc_etherdev:
2350         pci_release_selected_regions(pdev,
2351                                      pci_select_bars(pdev, IORESOURCE_MEM));
2352 err_pci_reg:
2353 err_dma:
2354         pci_disable_device(pdev);
2355         return err;
2356 }
2357
2358 #ifdef CONFIG_PCI_IOV
2359 static int  igb_disable_sriov(struct pci_dev *pdev)
2360 {
2361         struct net_device *netdev = pci_get_drvdata(pdev);
2362         struct igb_adapter *adapter = netdev_priv(netdev);
2363         struct e1000_hw *hw = &adapter->hw;
2364
2365         /* reclaim resources allocated to VFs */
2366         if (adapter->vf_data) {
2367                 /* disable iov and allow time for transactions to clear */
2368                 if (igb_vfs_are_assigned(adapter)) {
2369                         dev_warn(&pdev->dev,
2370                                  "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2371                         return -EPERM;
2372                 } else {
2373                         pci_disable_sriov(pdev);
2374                         msleep(500);
2375                 }
2376
2377                 kfree(adapter->vf_data);
2378                 adapter->vf_data = NULL;
2379                 adapter->vfs_allocated_count = 0;
2380                 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2381                 wrfl();
2382                 msleep(100);
2383                 dev_info(&pdev->dev, "IOV Disabled\n");
2384
2385                 /* Re-enable DMA Coalescing flag since IOV is turned off */
2386                 adapter->flags |= IGB_FLAG_DMAC;
2387         }
2388
2389         return 0;
2390 }
2391
2392 static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs)
2393 {
2394         struct net_device *netdev = pci_get_drvdata(pdev);
2395         struct igb_adapter *adapter = netdev_priv(netdev);
2396         int old_vfs = pci_num_vf(pdev);
2397         int err = 0;
2398         int i;
2399
2400         if (!num_vfs)
2401                 goto out;
2402         else if (old_vfs && old_vfs == num_vfs)
2403                 goto out;
2404         else if (old_vfs && old_vfs != num_vfs)
2405                 err = igb_disable_sriov(pdev);
2406
2407         if (err)
2408                 goto out;
2409
2410         if (num_vfs > 7) {
2411                 err = -EPERM;
2412                 goto out;
2413         }
2414
2415         adapter->vfs_allocated_count = num_vfs;
2416
2417         adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
2418                                 sizeof(struct vf_data_storage), GFP_KERNEL);
2419
2420         /* if allocation failed then we do not support SR-IOV */
2421         if (!adapter->vf_data) {
2422                 adapter->vfs_allocated_count = 0;
2423                 dev_err(&pdev->dev,
2424                         "Unable to allocate memory for VF Data Storage\n");
2425                 err = -ENOMEM;
2426                 goto out;
2427         }
2428
2429         err = pci_enable_sriov(pdev, adapter->vfs_allocated_count);
2430         if (err)
2431                 goto err_out;
2432
2433         dev_info(&pdev->dev, "%d VFs allocated\n",
2434                  adapter->vfs_allocated_count);
2435         for (i = 0; i < adapter->vfs_allocated_count; i++)
2436                 igb_vf_configure(adapter, i);
2437
2438         /* DMA Coalescing is not supported in IOV mode. */
2439         adapter->flags &= ~IGB_FLAG_DMAC;
2440         goto out;
2441
2442 err_out:
2443         kfree(adapter->vf_data);
2444         adapter->vf_data = NULL;
2445         adapter->vfs_allocated_count = 0;
2446 out:
2447         return err;
2448 }
2449
2450 #endif
2451 /*
2452  *  igb_remove_i2c - Cleanup  I2C interface
2453  *  @adapter: pointer to adapter structure
2454  *
2455  */
2456 static void igb_remove_i2c(struct igb_adapter *adapter)
2457 {
2458
2459         /* free the adapter bus structure */
2460         i2c_del_adapter(&adapter->i2c_adap);
2461 }
2462
2463 /**
2464  * igb_remove - Device Removal Routine
2465  * @pdev: PCI device information struct
2466  *
2467  * igb_remove is called by the PCI subsystem to alert the driver
2468  * that it should release a PCI device.  The could be caused by a
2469  * Hot-Plug event, or because the driver is going to be removed from
2470  * memory.
2471  **/
2472 static void igb_remove(struct pci_dev *pdev)
2473 {
2474         struct net_device *netdev = pci_get_drvdata(pdev);
2475         struct igb_adapter *adapter = netdev_priv(netdev);
2476         struct e1000_hw *hw = &adapter->hw;
2477
2478         pm_runtime_get_noresume(&pdev->dev);
2479 #ifdef CONFIG_IGB_HWMON
2480         igb_sysfs_exit(adapter);
2481 #endif
2482         igb_remove_i2c(adapter);
2483         igb_ptp_stop(adapter);
2484         /*
2485          * The watchdog timer may be rescheduled, so explicitly
2486          * disable watchdog from being rescheduled.
2487          */
2488         set_bit(__IGB_DOWN, &adapter->state);
2489         del_timer_sync(&adapter->watchdog_timer);
2490         del_timer_sync(&adapter->phy_info_timer);
2491
2492         cancel_work_sync(&adapter->reset_task);
2493         cancel_work_sync(&adapter->watchdog_task);
2494
2495 #ifdef CONFIG_IGB_DCA
2496         if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
2497                 dev_info(&pdev->dev, "DCA disabled\n");
2498                 dca_remove_requester(&pdev->dev);
2499                 adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
2500                 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
2501         }
2502 #endif
2503
2504         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
2505          * would have already happened in close and is redundant. */
2506         igb_release_hw_control(adapter);
2507
2508         unregister_netdev(netdev);
2509
2510         igb_clear_interrupt_scheme(adapter);
2511
2512 #ifdef CONFIG_PCI_IOV
2513         igb_disable_sriov(pdev);
2514 #endif
2515
2516         iounmap(hw->hw_addr);
2517         if (hw->flash_address)
2518                 iounmap(hw->flash_address);
2519         pci_release_selected_regions(pdev,
2520                                      pci_select_bars(pdev, IORESOURCE_MEM));
2521
2522         kfree(adapter->shadow_vfta);
2523         free_netdev(netdev);
2524
2525         pci_disable_pcie_error_reporting(pdev);
2526
2527         pci_disable_device(pdev);
2528 }
2529
2530 /**
2531  * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2532  * @adapter: board private structure to initialize
2533  *
2534  * This function initializes the vf specific data storage and then attempts to
2535  * allocate the VFs.  The reason for ordering it this way is because it is much
2536  * mor expensive time wise to disable SR-IOV than it is to allocate and free
2537  * the memory for the VFs.
2538  **/
2539 static void igb_probe_vfs(struct igb_adapter *adapter)
2540 {
2541 #ifdef CONFIG_PCI_IOV
2542         struct pci_dev *pdev = adapter->pdev;
2543         struct e1000_hw *hw = &adapter->hw;
2544
2545         /* Virtualization features not supported on i210 family. */
2546         if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211))
2547                 return;
2548
2549         igb_enable_sriov(pdev, max_vfs);
2550         pci_sriov_set_totalvfs(pdev, 7);
2551
2552 #endif /* CONFIG_PCI_IOV */
2553 }
2554
2555 static void igb_init_queue_configuration(struct igb_adapter *adapter)
2556 {
2557         struct e1000_hw *hw = &adapter->hw;
2558         u32 max_rss_queues;
2559
2560         /* Determine the maximum number of RSS queues supported. */
2561         switch (hw->mac.type) {
2562         case e1000_i211:
2563                 max_rss_queues = IGB_MAX_RX_QUEUES_I211;
2564                 break;
2565         case e1000_82575:
2566         case e1000_i210:
2567                 max_rss_queues = IGB_MAX_RX_QUEUES_82575;
2568                 break;
2569         case e1000_i350:
2570                 /* I350 cannot do RSS and SR-IOV at the same time */
2571                 if (!!adapter->vfs_allocated_count) {
2572                         max_rss_queues = 1;
2573                         break;
2574                 }
2575                 /* fall through */
2576         case e1000_82576:
2577                 if (!!adapter->vfs_allocated_count) {
2578                         max_rss_queues = 2;
2579                         break;
2580                 }
2581                 /* fall through */
2582         case e1000_82580:
2583         default:
2584                 max_rss_queues = IGB_MAX_RX_QUEUES;
2585                 break;
2586         }
2587
2588         adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus());
2589
2590         /* Determine if we need to pair queues. */
2591         switch (hw->mac.type) {
2592         case e1000_82575:
2593         case e1000_i211:
2594                 /* Device supports enough interrupts without queue pairing. */
2595                 break;
2596         case e1000_82576:
2597                 /*
2598                  * If VFs are going to be allocated with RSS queues then we
2599                  * should pair the queues in order to conserve interrupts due
2600                  * to limited supply.
2601                  */
2602                 if ((adapter->rss_queues > 1) &&
2603                     (adapter->vfs_allocated_count > 6))
2604                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2605                 /* fall through */
2606         case e1000_82580:
2607         case e1000_i350:
2608         case e1000_i210:
2609         default:
2610                 /*
2611                  * If rss_queues > half of max_rss_queues, pair the queues in
2612                  * order to conserve interrupts due to limited supply.
2613                  */
2614                 if (adapter->rss_queues > (max_rss_queues / 2))
2615                         adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
2616                 break;
2617         }
2618 }
2619
2620 /**
2621  * igb_sw_init - Initialize general software structures (struct igb_adapter)
2622  * @adapter: board private structure to initialize
2623  *
2624  * igb_sw_init initializes the Adapter private data structure.
2625  * Fields are initialized based on PCI device information and
2626  * OS network device settings (MTU size).
2627  **/
2628 static int igb_sw_init(struct igb_adapter *adapter)
2629 {
2630         struct e1000_hw *hw = &adapter->hw;
2631         struct net_device *netdev = adapter->netdev;
2632         struct pci_dev *pdev = adapter->pdev;
2633
2634         pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
2635
2636         /* set default ring sizes */
2637         adapter->tx_ring_count = IGB_DEFAULT_TXD;
2638         adapter->rx_ring_count = IGB_DEFAULT_RXD;
2639
2640         /* set default ITR values */
2641         adapter->rx_itr_setting = IGB_DEFAULT_ITR;
2642         adapter->tx_itr_setting = IGB_DEFAULT_ITR;
2643
2644         /* set default work limits */
2645         adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;
2646
2647         adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
2648                                   VLAN_HLEN;
2649         adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2650
2651         spin_lock_init(&adapter->stats64_lock);
2652 #ifdef CONFIG_PCI_IOV
2653         switch (hw->mac.type) {
2654         case e1000_82576:
2655         case e1000_i350:
2656                 if (max_vfs > 7) {
2657                         dev_warn(&pdev->dev,
2658                                  "Maximum of 7 VFs per PF, using max\n");
2659                         adapter->vfs_allocated_count = 7;
2660                 } else
2661                         adapter->vfs_allocated_count = max_vfs;
2662                 if (adapter->vfs_allocated_count)
2663                         dev_warn(&pdev->dev,
2664                                  "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2665                 break;
2666         default:
2667                 break;
2668         }
2669 #endif /* CONFIG_PCI_IOV */
2670
2671         igb_init_queue_configuration(adapter);
2672
2673         /* Setup and initialize a copy of the hw vlan table array */
2674         adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32),
2675                                        GFP_ATOMIC);
2676
2677         /* This call may decrease the number of queues */
2678         if (igb_init_interrupt_scheme(adapter, true)) {
2679                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
2680                 return -ENOMEM;
2681         }
2682
2683         igb_probe_vfs(adapter);
2684
2685         /* Explicitly disable IRQ since the NIC can be in any state. */
2686         igb_irq_disable(adapter);
2687
2688         if (hw->mac.type >= e1000_i350)
2689                 adapter->flags &= ~IGB_FLAG_DMAC;
2690
2691         set_bit(__IGB_DOWN, &adapter->state);
2692         return 0;
2693 }
2694
2695 /**
2696  * igb_open - Called when a network interface is made active
2697  * @netdev: network interface device structure
2698  *
2699  * Returns 0 on success, negative value on failure
2700  *
2701  * The open entry point is called when a network interface is made
2702  * active by the system (IFF_UP).  At this point all resources needed
2703  * for transmit and receive operations are allocated, the interrupt
2704  * handler is registered with the OS, the watchdog timer is started,
2705  * and the stack is notified that the interface is ready.
2706  **/
2707 static int __igb_open(struct net_device *netdev, bool resuming)
2708 {
2709         struct igb_adapter *adapter = netdev_priv(netdev);
2710         struct e1000_hw *hw = &adapter->hw;
2711         struct pci_dev *pdev = adapter->pdev;
2712         int err;
2713         int i;
2714
2715         /* disallow open during test */
2716         if (test_bit(__IGB_TESTING, &adapter->state)) {
2717                 WARN_ON(resuming);
2718                 return -EBUSY;
2719         }
2720
2721         if (!resuming)
2722                 pm_runtime_get_sync(&pdev->dev);
2723
2724         netif_carrier_off(netdev);
2725
2726         /* allocate transmit descriptors */
2727         err = igb_setup_all_tx_resources(adapter);
2728         if (err)
2729                 goto err_setup_tx;
2730
2731         /* allocate receive descriptors */
2732         err = igb_setup_all_rx_resources(adapter);
2733         if (err)
2734                 goto err_setup_rx;
2735
2736         igb_power_up_link(adapter);
2737
2738         /* before we allocate an interrupt, we must be ready to handle it.
2739          * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
2740          * as soon as we call pci_request_irq, so we have to setup our
2741          * clean_rx handler before we do so.  */
2742         igb_configure(adapter);
2743
2744         err = igb_request_irq(adapter);
2745         if (err)
2746                 goto err_req_irq;
2747
2748         /* Notify the stack of the actual queue counts. */
2749         err = netif_set_real_num_tx_queues(adapter->netdev,
2750                                            adapter->num_tx_queues);
2751         if (err)
2752                 goto err_set_queues;
2753
2754         err = netif_set_real_num_rx_queues(adapter->netdev,
2755                                            adapter->num_rx_queues);
2756         if (err)
2757                 goto err_set_queues;
2758
2759         /* From here on the code is the same as igb_up() */
2760         clear_bit(__IGB_DOWN, &adapter->state);
2761
2762         for (i = 0; i < adapter->num_q_vectors; i++)
2763                 napi_enable(&(adapter->q_vector[i]->napi));
2764
2765         /* Clear any pending interrupts. */
2766         rd32(E1000_ICR);
2767
2768         igb_irq_enable(adapter);
2769
2770         /* notify VFs that reset has been completed */
2771         if (adapter->vfs_allocated_count) {
2772                 u32 reg_data = rd32(E1000_CTRL_EXT);
2773                 reg_data |= E1000_CTRL_EXT_PFRSTD;
2774                 wr32(E1000_CTRL_EXT, reg_data);
2775         }
2776
2777         netif_tx_start_all_queues(netdev);
2778
2779         if (!resuming)
2780                 pm_runtime_put(&pdev->dev);
2781
2782         /* start the watchdog. */
2783         hw->mac.get_link_status = 1;
2784         schedule_work(&adapter->watchdog_task);
2785
2786         return 0;
2787
2788 err_set_queues:
2789         igb_free_irq(adapter);
2790 err_req_irq:
2791         igb_release_hw_control(adapter);
2792         igb_power_down_link(adapter);
2793         igb_free_all_rx_resources(adapter);
2794 err_setup_rx:
2795         igb_free_all_tx_resources(adapter);
2796 err_setup_tx:
2797         igb_reset(adapter);
2798         if (!resuming)
2799                 pm_runtime_put(&pdev->dev);
2800
2801         return err;
2802 }
2803
2804 static int igb_open(struct net_device *netdev)
2805 {
2806         return __igb_open(netdev, false);
2807 }
2808
2809 /**
2810  * igb_close - Disables a network interface
2811  * @netdev: network interface device structure
2812  *
2813  * Returns 0, this is not allowed to fail
2814  *
2815  * The close entry point is called when an interface is de-activated
2816  * by the OS.  The hardware is still under the driver's control, but
2817  * needs to be disabled.  A global MAC reset is issued to stop the
2818  * hardware, and all transmit and receive resources are freed.
2819  **/
2820 static int __igb_close(struct net_device *netdev, bool suspending)
2821 {
2822         struct igb_adapter *adapter = netdev_priv(netdev);
2823         struct pci_dev *pdev = adapter->pdev;
2824
2825         WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
2826
2827         if (!suspending)
2828                 pm_runtime_get_sync(&pdev->dev);
2829
2830         igb_down(adapter);
2831         igb_free_irq(adapter);
2832
2833         igb_free_all_tx_resources(adapter);
2834         igb_free_all_rx_resources(adapter);
2835
2836         if (!suspending)
2837                 pm_runtime_put_sync(&pdev->dev);
2838         return 0;
2839 }
2840
2841 static int igb_close(struct net_device *netdev)
2842 {
2843         return __igb_close(netdev, false);
2844 }
2845
2846 /**
2847  * igb_setup_tx_resources - allocate Tx resources (Descriptors)
2848  * @tx_ring: tx descriptor ring (for a specific queue) to setup
2849  *
2850  * Return 0 on success, negative on failure
2851  **/
2852 int igb_setup_tx_resources(struct igb_ring *tx_ring)
2853 {
2854         struct device *dev = tx_ring->dev;
2855         int size;
2856
2857         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2858
2859         tx_ring->tx_buffer_info = vzalloc(size);
2860         if (!tx_ring->tx_buffer_info)
2861                 goto err;
2862
2863         /* round up to nearest 4K */
2864         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2865         tx_ring->size = ALIGN(tx_ring->size, 4096);
2866
2867         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2868                                            &tx_ring->dma, GFP_KERNEL);
2869         if (!tx_ring->desc)
2870                 goto err;
2871
2872         tx_ring->next_to_use = 0;
2873         tx_ring->next_to_clean = 0;
2874
2875         return 0;
2876
2877 err:
2878         vfree(tx_ring->tx_buffer_info);
2879         tx_ring->tx_buffer_info = NULL;
2880         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2881         return -ENOMEM;
2882 }
2883
2884 /**
2885  * igb_setup_all_tx_resources - wrapper to allocate Tx resources
2886  *                                (Descriptors) for all queues
2887  * @adapter: board private structure
2888  *
2889  * Return 0 on success, negative on failure
2890  **/
2891 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
2892 {
2893         struct pci_dev *pdev = adapter->pdev;
2894         int i, err = 0;
2895
2896         for (i = 0; i < adapter->num_tx_queues; i++) {
2897                 err = igb_setup_tx_resources(adapter->tx_ring[i]);
2898                 if (err) {
2899                         dev_err(&pdev->dev,
2900                                 "Allocation for Tx Queue %u failed\n", i);
2901                         for (i--; i >= 0; i--)
2902                                 igb_free_tx_resources(adapter->tx_ring[i]);
2903                         break;
2904                 }
2905         }
2906
2907         return err;
2908 }
2909
2910 /**
2911  * igb_setup_tctl - configure the transmit control registers
2912  * @adapter: Board private structure
2913  **/
2914 void igb_setup_tctl(struct igb_adapter *adapter)
2915 {
2916         struct e1000_hw *hw = &adapter->hw;
2917         u32 tctl;
2918
2919         /* disable queue 0 which is enabled by default on 82575 and 82576 */
2920         wr32(E1000_TXDCTL(0), 0);
2921
2922         /* Program the Transmit Control Register */
2923         tctl = rd32(E1000_TCTL);
2924         tctl &= ~E1000_TCTL_CT;
2925         tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2926                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2927
2928         igb_config_collision_dist(hw);
2929
2930         /* Enable transmits */
2931         tctl |= E1000_TCTL_EN;
2932
2933         wr32(E1000_TCTL, tctl);
2934 }
2935
2936 /**
2937  * igb_configure_tx_ring - Configure transmit ring after Reset
2938  * @adapter: board private structure
2939  * @ring: tx ring to configure
2940  *
2941  * Configure a transmit ring after a reset.
2942  **/
2943 void igb_configure_tx_ring(struct igb_adapter *adapter,
2944                            struct igb_ring *ring)
2945 {
2946         struct e1000_hw *hw = &adapter->hw;
2947         u32 txdctl = 0;
2948         u64 tdba = ring->dma;
2949         int reg_idx = ring->reg_idx;
2950
2951         /* disable the queue */
2952         wr32(E1000_TXDCTL(reg_idx), 0);
2953         wrfl();
2954         mdelay(10);
2955
2956         wr32(E1000_TDLEN(reg_idx),
2957                         ring->count * sizeof(union e1000_adv_tx_desc));
2958         wr32(E1000_TDBAL(reg_idx),
2959                         tdba & 0x00000000ffffffffULL);
2960         wr32(E1000_TDBAH(reg_idx), tdba >> 32);
2961
2962         ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2963         wr32(E1000_TDH(reg_idx), 0);
2964         writel(0, ring->tail);
2965
2966         txdctl |= IGB_TX_PTHRESH;
2967         txdctl |= IGB_TX_HTHRESH << 8;
2968         txdctl |= IGB_TX_WTHRESH << 16;
2969
2970         txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
2971         wr32(E1000_TXDCTL(reg_idx), txdctl);
2972 }
2973
2974 /**
2975  * igb_configure_tx - Configure transmit Unit after Reset
2976  * @adapter: board private structure
2977  *
2978  * Configure the Tx unit of the MAC after a reset.
2979  **/
2980 static void igb_configure_tx(struct igb_adapter *adapter)
2981 {
2982         int i;
2983
2984         for (i = 0; i < adapter->num_tx_queues; i++)
2985                 igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2986 }
2987
2988 /**
2989  * igb_setup_rx_resources - allocate Rx resources (Descriptors)
2990  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
2991  *
2992  * Returns 0 on success, negative on failure
2993  **/
2994 int igb_setup_rx_resources(struct igb_ring *rx_ring)
2995 {
2996         struct device *dev = rx_ring->dev;
2997         int size;
2998
2999         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3000
3001         rx_ring->rx_buffer_info = vzalloc(size);
3002         if (!rx_ring->rx_buffer_info)
3003                 goto err;
3004
3005         /* Round up to nearest 4K */
3006         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
3007         rx_ring->size = ALIGN(rx_ring->size, 4096);
3008
3009         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
3010                                            &rx_ring->dma, GFP_KERNEL);
3011         if (!rx_ring->desc)
3012                 goto err;
3013
3014         rx_ring->next_to_alloc = 0;
3015         rx_ring->next_to_clean = 0;
3016         rx_ring->next_to_use = 0;
3017
3018         return 0;
3019
3020 err:
3021         vfree(rx_ring->rx_buffer_info);
3022         rx_ring->rx_buffer_info = NULL;
3023         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
3024         return -ENOMEM;
3025 }
3026
3027 /**
3028  * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3029  *                                (Descriptors) for all queues
3030  * @adapter: board private structure
3031  *
3032  * Return 0 on success, negative on failure
3033  **/
3034 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
3035 {
3036         struct pci_dev *pdev = adapter->pdev;
3037         int i, err = 0;
3038
3039         for (i = 0; i < adapter->num_rx_queues; i++) {
3040                 err = igb_setup_rx_resources(adapter->rx_ring[i]);
3041                 if (err) {
3042                         dev_err(&pdev->dev,
3043                                 "Allocation for Rx Queue %u failed\n", i);
3044                         for (i--; i >= 0; i--)
3045                                 igb_free_rx_resources(adapter->rx_ring[i]);
3046                         break;
3047                 }
3048         }
3049
3050         return err;
3051 }
3052
3053 /**
3054  * igb_setup_mrqc - configure the multiple receive queue control registers
3055  * @adapter: Board private structure
3056  **/
3057 static void igb_setup_mrqc(struct igb_adapter *adapter)
3058 {
3059         struct e1000_hw *hw = &adapter->hw;
3060         u32 mrqc, rxcsum;
3061         u32 j, num_rx_queues, shift = 0;
3062         static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741,
3063                                         0xB08FA343, 0xCB2BCAD0, 0xB4307BAE,
3064                                         0xA32DCB77, 0x0CF23080, 0x3BB7426A,
3065                                         0xFA01ACBE };
3066
3067         /* Fill out hash function seeds */
3068         for (j = 0; j < 10; j++)
3069                 wr32(E1000_RSSRK(j), rsskey[j]);
3070
3071         num_rx_queues = adapter->rss_queues;
3072
3073         switch (hw->mac.type) {
3074         case e1000_82575:
3075                 shift = 6;
3076                 break;
3077         case e1000_82576:
3078                 /* 82576 supports 2 RSS queues for SR-IOV */
3079                 if (adapter->vfs_allocated_count) {
3080                         shift = 3;
3081                         num_rx_queues = 2;
3082                 }
3083                 break;
3084         default:
3085                 break;
3086         }
3087
3088         /*
3089          * Populate the indirection table 4 entries at a time.  To do this
3090          * we are generating the results for n and n+2 and then interleaving
3091          * those with the results with n+1 and n+3.
3092          */
3093         for (j = 0; j < 32; j++) {
3094                 /* first pass generates n and n+2 */
3095                 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues;
3096                 u32 reta = (base & 0x07800780) >> (7 - shift);
3097
3098                 /* second pass generates n+1 and n+3 */
3099                 base += 0x00010001 * num_rx_queues;
3100                 reta |= (base & 0x07800780) << (1 + shift);
3101
3102                 wr32(E1000_RETA(j), reta);
3103         }
3104
3105         /*
3106          * Disable raw packet checksumming so that RSS hash is placed in
3107          * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
3108          * offloads as they are enabled by default
3109          */
3110         rxcsum = rd32(E1000_RXCSUM);
3111         rxcsum |= E1000_RXCSUM_PCSD;
3112
3113         if (adapter->hw.mac.type >= e1000_82576)
3114                 /* Enable Receive Checksum Offload for SCTP */
3115                 rxcsum |= E1000_RXCSUM_CRCOFL;
3116
3117         /* Don't need to set TUOFL or IPOFL, they default to 1 */
3118         wr32(E1000_RXCSUM, rxcsum);
3119
3120         /* Generate RSS hash based on packet types, TCP/UDP
3121          * port numbers and/or IPv4/v6 src and dst addresses
3122          */
3123         mrqc = E1000_MRQC_RSS_FIELD_IPV4 |
3124                E1000_MRQC_RSS_FIELD_IPV4_TCP |
3125                E1000_MRQC_RSS_FIELD_IPV6 |
3126                E1000_MRQC_RSS_FIELD_IPV6_TCP |
3127                E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3128
3129         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
3130                 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
3131         if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
3132                 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
3133
3134         /* If VMDq is enabled then we set the appropriate mode for that, else
3135          * we default to RSS so that an RSS hash is calculated per packet even
3136          * if we are only using one queue */
3137         if (adapter->vfs_allocated_count) {
3138                 if (hw->mac.type > e1000_82575) {
3139                         /* Set the default pool for the PF's first queue */
3140                         u32 vtctl = rd32(E1000_VT_CTL);
3141                         vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
3142                                    E1000_VT_CTL_DISABLE_DEF_POOL);
3143                         vtctl |= adapter->vfs_allocated_count <<
3144                                 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3145                         wr32(E1000_VT_CTL, vtctl);
3146                 }
3147                 if (adapter->rss_queues > 1)
3148                         mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
3149                 else
3150                         mrqc |= E1000_MRQC_ENABLE_VMDQ;
3151         } else {
3152                 if (hw->mac.type != e1000_i211)
3153                         mrqc |= E1000_MRQC_ENABLE_RSS_4Q;
3154         }
3155         igb_vmm_control(adapter);
3156
3157         wr32(E1000_MRQC, mrqc);
3158 }
3159
3160 /**
3161  * igb_setup_rctl - configure the receive control registers
3162  * @adapter: Board private structure
3163  **/
3164 void igb_setup_rctl(struct igb_adapter *adapter)
3165 {
3166         struct e1000_hw *hw = &adapter->hw;
3167         u32 rctl;
3168
3169         rctl = rd32(E1000_RCTL);
3170
3171         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3172         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
3173
3174         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
3175                 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3176
3177         /*
3178          * enable stripping of CRC. It's unlikely this will break BMC
3179          * redirection as it did with e1000. Newer features require
3180          * that the HW strips the CRC.
3181          */
3182         rctl |= E1000_RCTL_SECRC;
3183
3184         /* disable store bad packets and clear size bits. */
3185         rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
3186
3187         /* enable LPE to prevent packets larger than max_frame_size */
3188         rctl |= E1000_RCTL_LPE;
3189
3190         /* disable queue 0 to prevent tail write w/o re-config */
3191         wr32(E1000_RXDCTL(0), 0);
3192
3193         /* Attention!!!  For SR-IOV PF driver operations you must enable
3194          * queue drop for all VF and PF queues to prevent head of line blocking
3195          * if an un-trusted VF does not provide descriptors to hardware.
3196          */
3197         if (adapter->vfs_allocated_count) {
3198                 /* set all queue drop enable bits */
3199                 wr32(E1000_QDE, ALL_QUEUES);
3200         }
3201
3202         /* This is useful for sniffing bad packets. */
3203         if (adapter->netdev->features & NETIF_F_RXALL) {
3204                 /* UPE and MPE will be handled by normal PROMISC logic
3205                  * in e1000e_set_rx_mode */
3206                 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3207                          E1000_RCTL_BAM | /* RX All Bcast Pkts */
3208                          E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3209
3210                 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3211                           E1000_RCTL_DPF | /* Allow filtered pause */
3212                           E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3213                 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3214                  * and that breaks VLANs.
3215                  */
3216         }
3217
3218         wr32(E1000_RCTL, rctl);
3219 }
3220
3221 static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
3222                                    int vfn)
3223 {
3224         struct e1000_hw *hw = &adapter->hw;
3225         u32 vmolr;
3226
3227         /* if it isn't the PF check to see if VFs are enabled and
3228          * increase the size to support vlan tags */
3229         if (vfn < adapter->vfs_allocated_count &&
3230             adapter->vf_data[vfn].vlans_enabled)
3231                 size += VLAN_TAG_SIZE;
3232
3233         vmolr = rd32(E1000_VMOLR(vfn));
3234         vmolr &= ~E1000_VMOLR_RLPML_MASK;
3235         vmolr |= size | E1000_VMOLR_LPE;
3236         wr32(E1000_VMOLR(vfn), vmolr);
3237
3238         return 0;
3239 }
3240
3241 /**
3242  * igb_rlpml_set - set maximum receive packet size
3243  * @adapter: board private structure
3244  *
3245  * Configure maximum receivable packet size.
3246  **/
3247 static void igb_rlpml_set(struct igb_adapter *adapter)
3248 {
3249         u32 max_frame_size = adapter->max_frame_size;
3250         struct e1000_hw *hw = &adapter->hw;
3251         u16 pf_id = adapter->vfs_allocated_count;
3252
3253         if (pf_id) {
3254                 igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3255                 /*
3256                  * If we're in VMDQ or SR-IOV mode, then set global RLPML
3257                  * to our max jumbo frame size, in case we need to enable
3258                  * jumbo frames on one of the rings later.
3259                  * This will not pass over-length frames into the default
3260                  * queue because it's gated by the VMOLR.RLPML.
3261                  */
3262                 max_frame_size = MAX_JUMBO_FRAME_SIZE;
3263         }
3264
3265         wr32(E1000_RLPML, max_frame_size);
3266 }
3267
3268 static inline void igb_set_vmolr(struct igb_adapter *adapter,
3269                                  int vfn, bool aupe)
3270 {
3271         struct e1000_hw *hw = &adapter->hw;
3272         u32 vmolr;
3273
3274         /*
3275          * This register exists only on 82576 and newer so if we are older then
3276          * we should exit and do nothing
3277          */
3278         if (hw->mac.type < e1000_82576)
3279                 return;
3280
3281         vmolr = rd32(E1000_VMOLR(vfn));
3282         vmolr |= E1000_VMOLR_STRVLAN;      /* Strip vlan tags */
3283         if (aupe)
3284                 vmolr |= E1000_VMOLR_AUPE;        /* Accept untagged packets */
3285         else
3286                 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3287
3288         /* clear all bits that might not be set */
3289         vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);
3290
3291         if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3292                 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
3293         /*
3294          * for VMDq only allow the VFs and pool 0 to accept broadcast and
3295          * multicast packets
3296          */
3297         if (vfn <= adapter->vfs_allocated_count)
3298                 vmolr |= E1000_VMOLR_BAM;          /* Accept broadcast */
3299
3300         wr32(E1000_VMOLR(vfn), vmolr);
3301 }
3302
3303 /**
3304  * igb_configure_rx_ring - Configure a receive ring after Reset
3305  * @adapter: board private structure
3306  * @ring: receive ring to be configured
3307  *
3308  * Configure the Rx unit of the MAC after a reset.
3309  **/
3310 void igb_configure_rx_ring(struct igb_adapter *adapter,
3311                            struct igb_ring *ring)
3312 {
3313         struct e1000_hw *hw = &adapter->hw;
3314         u64 rdba = ring->dma;
3315         int reg_idx = ring->reg_idx;
3316         u32 srrctl = 0, rxdctl = 0;
3317
3318         /* disable the queue */
3319         wr32(E1000_RXDCTL(reg_idx), 0);
3320
3321         /* Set DMA base address registers */
3322         wr32(E1000_RDBAL(reg_idx),
3323              rdba & 0x00000000ffffffffULL);
3324         wr32(E1000_RDBAH(reg_idx), rdba >> 32);
3325         wr32(E1000_RDLEN(reg_idx),
3326                        ring->count * sizeof(union e1000_adv_rx_desc));
3327
3328         /* initialize head and tail */
3329         ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3330         wr32(E1000_RDH(reg_idx), 0);
3331         writel(0, ring->tail);
3332
3333         /* set descriptor configuration */
3334         srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3335         srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3336         srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
3337         if (hw->mac.type >= e1000_82580)
3338                 srrctl |= E1000_SRRCTL_TIMESTAMP;
3339         /* Only set Drop Enable if we are supporting multiple queues */
3340         if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
3341                 srrctl |= E1000_SRRCTL_DROP_EN;
3342
3343         wr32(E1000_SRRCTL(reg_idx), srrctl);
3344
3345         /* set filtering for VMDQ pools */
3346         igb_set_vmolr(adapter, reg_idx & 0x7, true);
3347
3348         rxdctl |= IGB_RX_PTHRESH;
3349         rxdctl |= IGB_RX_HTHRESH << 8;
3350         rxdctl |= IGB_RX_WTHRESH << 16;
3351
3352         /* enable receive descriptor fetching */
3353         rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3354         wr32(E1000_RXDCTL(reg_idx), rxdctl);
3355 }
3356
3357 static void igb_set_rx_buffer_len(struct igb_adapter *adapter,
3358                                   struct igb_ring *rx_ring)
3359 {
3360 #define IGB_MAX_BUILD_SKB_SIZE \
3361         (SKB_WITH_OVERHEAD(IGB_RX_BUFSZ) - \
3362          (NET_SKB_PAD + NET_IP_ALIGN + IGB_TS_HDR_LEN))
3363
3364         /* set build_skb flag */
3365         if (adapter->max_frame_size <= IGB_MAX_BUILD_SKB_SIZE)
3366                 set_ring_build_skb_enabled(rx_ring);
3367         else
3368                 clear_ring_build_skb_enabled(rx_ring);
3369 }
3370
3371 /**
3372  * igb_configure_rx - Configure receive Unit after Reset
3373  * @adapter: board private structure
3374  *
3375  * Configure the Rx unit of the MAC after a reset.
3376  **/
3377 static void igb_configure_rx(struct igb_adapter *adapter)
3378 {
3379         int i;
3380
3381         /* set UTA to appropriate mode */
3382         igb_set_uta(adapter);
3383
3384         /* set the correct pool for the PF default MAC address in entry 0 */
3385         igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
3386                          adapter->vfs_allocated_count);
3387
3388         /* Setup the HW Rx Head and Tail Descriptor Pointers and
3389          * the Base and Length of the Rx Descriptor Ring */
3390         for (i = 0; i < adapter->num_rx_queues; i++) {
3391                 struct igb_ring *rx_ring = adapter->rx_ring[i];
3392                 igb_set_rx_buffer_len(adapter, rx_ring);
3393                 igb_configure_rx_ring(adapter, rx_ring);
3394         }
3395 }
3396
3397 /**
3398  * igb_free_tx_resources - Free Tx Resources per Queue
3399  * @tx_ring: Tx descriptor ring for a specific queue
3400  *
3401  * Free all transmit software resources
3402  **/
3403 void igb_free_tx_resources(struct igb_ring *tx_ring)
3404 {
3405         igb_clean_tx_ring(tx_ring);
3406
3407         vfree(tx_ring->tx_buffer_info);
3408         tx_ring->tx_buffer_info = NULL;
3409
3410         /* if not set, then don't free */
3411         if (!tx_ring->desc)
3412                 return;
3413
3414         dma_free_coherent(tx_ring->dev, tx_ring->size,
3415                           tx_ring->desc, tx_ring->dma);
3416
3417         tx_ring->desc = NULL;
3418 }
3419
3420 /**
3421  * igb_free_all_tx_resources - Free Tx Resources for All Queues
3422  * @adapter: board private structure
3423  *
3424  * Free all transmit software resources
3425  **/
3426 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
3427 {
3428         int i;
3429
3430         for (i = 0; i < adapter->num_tx_queues; i++)
3431                 igb_free_tx_resources(adapter->tx_ring[i]);
3432 }
3433
3434 void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
3435                                     struct igb_tx_buffer *tx_buffer)
3436 {
3437         if (tx_buffer->skb) {
3438                 dev_kfree_skb_any(tx_buffer->skb);
3439                 if (dma_unmap_len(tx_buffer, len))
3440                         dma_unmap_single(ring->dev,
3441                                          dma_unmap_addr(tx_buffer, dma),
3442                                          dma_unmap_len(tx_buffer, len),
3443                                          DMA_TO_DEVICE);
3444         } else if (dma_unmap_len(tx_buffer, len)) {
3445                 dma_unmap_page(ring->dev,
3446                                dma_unmap_addr(tx_buffer, dma),
3447                                dma_unmap_len(tx_buffer, len),
3448                                DMA_TO_DEVICE);
3449         }
3450         tx_buffer->next_to_watch = NULL;
3451         tx_buffer->skb = NULL;
3452         dma_unmap_len_set(tx_buffer, len, 0);
3453         /* buffer_info must be completely set up in the transmit path */
3454 }
3455
3456 /**
3457  * igb_clean_tx_ring - Free Tx Buffers
3458  * @tx_ring: ring to be cleaned
3459  **/
3460 static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3461 {
3462         struct igb_tx_buffer *buffer_info;
3463         unsigned long size;
3464         u16 i;
3465
3466         if (!tx_ring->tx_buffer_info)
3467                 return;
3468         /* Free all the Tx ring sk_buffs */
3469
3470         for (i = 0; i < tx_ring->count; i++) {
3471                 buffer_info = &tx_ring->tx_buffer_info[i];
3472                 igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3473         }
3474
3475         netdev_tx_reset_queue(txring_txq(tx_ring));
3476
3477         size = sizeof(struct igb_tx_buffer) * tx_ring->count;
3478         memset(tx_ring->tx_buffer_info, 0, size);
3479
3480         /* Zero out the descriptor ring */
3481         memset(tx_ring->desc, 0, tx_ring->size);
3482
3483         tx_ring->next_to_use = 0;
3484         tx_ring->next_to_clean = 0;
3485 }
3486
3487 /**
3488  * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3489  * @adapter: board private structure
3490  **/
3491 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
3492 {
3493         int i;
3494
3495         for (i = 0; i < adapter->num_tx_queues; i++)
3496                 igb_clean_tx_ring(adapter->tx_ring[i]);
3497 }
3498
3499 /**
3500  * igb_free_rx_resources - Free Rx Resources
3501  * @rx_ring: ring to clean the resources from
3502  *
3503  * Free all receive software resources
3504  **/
3505 void igb_free_rx_resources(struct igb_ring *rx_ring)
3506 {
3507         igb_clean_rx_ring(rx_ring);
3508
3509         vfree(rx_ring->rx_buffer_info);
3510         rx_ring->rx_buffer_info = NULL;
3511
3512         /* if not set, then don't free */
3513         if (!rx_ring->desc)
3514                 return;
3515
3516         dma_free_coherent(rx_ring->dev, rx_ring->size,
3517                           rx_ring->desc, rx_ring->dma);
3518
3519         rx_ring->desc = NULL;
3520 }
3521
3522 /**
3523  * igb_free_all_rx_resources - Free Rx Resources for All Queues
3524  * @adapter: board private structure
3525  *
3526  * Free all receive software resources
3527  **/
3528 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
3529 {
3530         int i;
3531
3532         for (i = 0; i < adapter->num_rx_queues; i++)
3533                 igb_free_rx_resources(adapter->rx_ring[i]);
3534 }
3535
3536 /**
3537  * igb_clean_rx_ring - Free Rx Buffers per Queue
3538  * @rx_ring: ring to free buffers from
3539  **/
3540 static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3541 {
3542         unsigned long size;
3543         u16 i;
3544
3545         if (rx_ring->skb)
3546                 dev_kfree_skb(rx_ring->skb);
3547         rx_ring->skb = NULL;
3548
3549         if (!rx_ring->rx_buffer_info)
3550                 return;
3551
3552         /* Free all the Rx ring sk_buffs */
3553         for (i = 0; i < rx_ring->count; i++) {
3554                 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3555
3556                 if (!buffer_info->page)
3557                         continue;
3558
3559                 dma_unmap_page(rx_ring->dev,
3560                                buffer_info->dma,
3561                                PAGE_SIZE,
3562                                DMA_FROM_DEVICE);
3563                 __free_page(buffer_info->page);
3564
3565                 buffer_info->page = NULL;
3566         }
3567
3568         size = sizeof(struct igb_rx_buffer) * rx_ring->count;
3569         memset(rx_ring->rx_buffer_info, 0, size);
3570
3571         /* Zero out the descriptor ring */
3572         memset(rx_ring->desc, 0, rx_ring->size);
3573
3574         rx_ring->next_to_alloc = 0;
3575         rx_ring->next_to_clean = 0;
3576         rx_ring->next_to_use = 0;
3577 }
3578
3579 /**
3580  * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3581  * @adapter: board private structure
3582  **/
3583 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
3584 {
3585         int i;
3586
3587         for (i = 0; i < adapter->num_rx_queues; i++)
3588                 igb_clean_rx_ring(adapter->rx_ring[i]);
3589 }
3590
3591 /**
3592  * igb_set_mac - Change the Ethernet Address of the NIC
3593  * @netdev: network interface device structure
3594  * @p: pointer to an address structure
3595  *
3596  * Returns 0 on success, negative on failure
3597  **/
3598 static int igb_set_mac(struct net_device *netdev, void *p)
3599 {
3600         struct igb_adapter *adapter = netdev_priv(netdev);
3601         struct e1000_hw *hw = &adapter->hw;
3602         struct sockaddr *addr = p;
3603
3604         if (!is_valid_ether_addr(addr->sa_data))
3605                 return -EADDRNOTAVAIL;
3606
3607         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3608         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3609
3610         /* set the correct pool for the new PF MAC address in entry 0 */
3611         igb_rar_set_qsel(adapter, hw->mac.addr, 0,
3612                          adapter->vfs_allocated_count);
3613
3614         return 0;
3615 }
3616
3617 /**
3618  * igb_write_mc_addr_list - write multicast addresses to MTA
3619  * @netdev: network interface device structure
3620  *
3621  * Writes multicast address list to the MTA hash table.
3622  * Returns: -ENOMEM on failure
3623  *                0 on no addresses written
3624  *                X on writing X addresses to MTA
3625  **/
3626 static int igb_write_mc_addr_list(struct net_device *netdev)
3627 {
3628         struct igb_adapter *adapter = netdev_priv(netdev);
3629         struct e1000_hw *hw = &adapter->hw;
3630         struct netdev_hw_addr *ha;
3631         u8  *mta_list;
3632         int i;
3633
3634         if (netdev_mc_empty(netdev)) {
3635                 /* nothing to program, so clear mc list */
3636                 igb_update_mc_addr_list(hw, NULL, 0);
3637                 igb_restore_vf_multicasts(adapter);
3638                 return 0;
3639         }
3640
3641         mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3642         if (!mta_list)
3643                 return -ENOMEM;
3644
3645         /* The shared function expects a packed array of only addresses. */
3646         i = 0;
3647         netdev_for_each_mc_addr(ha, netdev)
3648                 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3649
3650         igb_update_mc_addr_list(hw, mta_list, i);
3651         kfree(mta_list);
3652
3653         return netdev_mc_count(netdev);
3654 }
3655
3656 /**
3657  * igb_write_uc_addr_list - write unicast addresses to RAR table
3658  * @netdev: network interface device structure
3659  *
3660  * Writes unicast address list to the RAR table.
3661  * Returns: -ENOMEM on failure/insufficient address space
3662  *                0 on no addresses written
3663  *                X on writing X addresses to the RAR table
3664  **/
3665 static int igb_write_uc_addr_list(struct net_device *netdev)
3666 {
3667         struct igb_adapter *adapter = netdev_priv(netdev);
3668         struct e1000_hw *hw = &adapter->hw;
3669         unsigned int vfn = adapter->vfs_allocated_count;
3670         unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
3671         int count = 0;
3672
3673         /* return ENOMEM indicating insufficient memory for addresses */
3674         if (netdev_uc_count(netdev) > rar_entries)
3675                 return -ENOMEM;
3676
3677         if (!netdev_uc_empty(netdev) && rar_entries) {
3678                 struct netdev_hw_addr *ha;
3679
3680                 netdev_for_each_uc_addr(ha, netdev) {
3681                         if (!rar_entries)
3682                                 break;
3683                         igb_rar_set_qsel(adapter, ha->addr,
3684                                          rar_entries--,
3685                                          vfn);
3686                         count++;
3687                 }
3688         }
3689         /* write the addresses in reverse order to avoid write combining */
3690         for (; rar_entries > 0 ; rar_entries--) {
3691                 wr32(E1000_RAH(rar_entries), 0);
3692                 wr32(E1000_RAL(rar_entries), 0);
3693         }
3694         wrfl();
3695
3696         return count;
3697 }
3698
3699 /**
3700  * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3701  * @netdev: network interface device structure
3702  *
3703  * The set_rx_mode entry point is called whenever the unicast or multicast
3704  * address lists or the network interface flags are updated.  This routine is
3705  * responsible for configuring the hardware for proper unicast, multicast,
3706  * promiscuous mode, and all-multi behavior.
3707  **/
3708 static void igb_set_rx_mode(struct net_device *netdev)
3709 {
3710         struct igb_adapter *adapter = netdev_priv(netdev);
3711         struct e1000_hw *hw = &adapter->hw;
3712         unsigned int vfn = adapter->vfs_allocated_count;
3713         u32 rctl, vmolr = 0;
3714         int count;
3715
3716         /* Check for Promiscuous and All Multicast modes */
3717         rctl = rd32(E1000_RCTL);
3718
3719         /* clear the effected bits */
3720         rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);
3721
3722         if (netdev->flags & IFF_PROMISC) {
3723                 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3724                 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
3725         } else {
3726                 if (netdev->flags & IFF_ALLMULTI) {
3727                         rctl |= E1000_RCTL_MPE;
3728                         vmolr |= E1000_VMOLR_MPME;
3729                 } else {
3730                         /*
3731                          * Write addresses to the MTA, if the attempt fails
3732                          * then we should just turn on promiscuous mode so
3733                          * that we can at least receive multicast traffic
3734                          */
3735                         count = igb_write_mc_addr_list(netdev);
3736                         if (count < 0) {
3737                                 rctl |= E1000_RCTL_MPE;
3738                                 vmolr |= E1000_VMOLR_MPME;
3739                         } else if (count) {
3740                                 vmolr |= E1000_VMOLR_ROMPE;
3741                         }
3742                 }
3743                 /*
3744                  * Write addresses to available RAR registers, if there is not
3745                  * sufficient space to store all the addresses then enable
3746                  * unicast promiscuous mode
3747                  */
3748                 count = igb_write_uc_addr_list(netdev);
3749                 if (count < 0) {
3750                         rctl |= E1000_RCTL_UPE;
3751                         vmolr |= E1000_VMOLR_ROPE;
3752                 }
3753                 rctl |= E1000_RCTL_VFE;
3754         }
3755         wr32(E1000_RCTL, rctl);
3756
3757         /*
3758          * In order to support SR-IOV and eventually VMDq it is necessary to set
3759          * the VMOLR to enable the appropriate modes.  Without this workaround
3760          * we will have issues with VLAN tag stripping not being done for frames
3761          * that are only arriving because we are the default pool
3762          */
3763         if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350))
3764                 return;
3765
3766         vmolr |= rd32(E1000_VMOLR(vfn)) &
3767                  ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
3768         wr32(E1000_VMOLR(vfn), vmolr);
3769         igb_restore_vf_multicasts(adapter);
3770 }
3771
3772 static void igb_check_wvbr(struct igb_adapter *adapter)
3773 {
3774         struct e1000_hw *hw = &adapter->hw;
3775         u32 wvbr = 0;
3776
3777         switch (hw->mac.type) {
3778         case e1000_82576:
3779         case e1000_i350:
3780                 if (!(wvbr = rd32(E1000_WVBR)))
3781                         return;
3782                 break;
3783         default:
3784                 break;
3785         }
3786
3787         adapter->wvbr |= wvbr;
3788 }
3789
3790 #define IGB_STAGGERED_QUEUE_OFFSET 8
3791
3792 static void igb_spoof_check(struct igb_adapter *adapter)
3793 {
3794         int j;
3795
3796         if (!adapter->wvbr)
3797                 return;
3798
3799         for(j = 0; j < adapter->vfs_allocated_count; j++) {
3800                 if (adapter->wvbr & (1 << j) ||
3801                     adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
3802                         dev_warn(&adapter->pdev->dev,
3803                                 "Spoof event(s) detected on VF %d\n", j);
3804                         adapter->wvbr &=
3805                                 ~((1 << j) |
3806                                   (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
3807                 }
3808         }
3809 }
3810
3811 /* Need to wait a few seconds after link up to get diagnostic information from
3812  * the phy */
3813 static void igb_update_phy_info(unsigned long data)
3814 {
3815         struct igb_adapter *adapter = (struct igb_adapter *) data;
3816         igb_get_phy_info(&adapter->hw);
3817 }
3818
3819 /**
3820  * igb_has_link - check shared code for link and determine up/down
3821  * @adapter: pointer to driver private info
3822  **/
3823 bool igb_has_link(struct igb_adapter *adapter)
3824 {
3825         struct e1000_hw *hw = &adapter->hw;
3826         bool link_active = false;
3827         s32 ret_val = 0;
3828
3829         /* get_link_status is set on LSC (link status) interrupt or
3830          * rx sequence error interrupt.  get_link_status will stay
3831          * false until the e1000_check_for_link establishes link
3832          * for copper adapters ONLY
3833          */
3834         switch (hw->phy.media_type) {
3835         case e1000_media_type_copper:
3836                 if (hw->mac.get_link_status) {
3837                         ret_val = hw->mac.ops.check_for_link(hw);
3838                         link_active = !hw->mac.get_link_status;
3839                 } else {
3840                         link_active = true;
3841                 }
3842                 break;
3843         case e1000_media_type_internal_serdes:
3844                 ret_val = hw->mac.ops.check_for_link(hw);
3845                 link_active = hw->mac.serdes_has_link;
3846                 break;
3847         default:
3848         case e1000_media_type_unknown:
3849                 break;
3850         }
3851
3852         return link_active;
3853 }
3854
3855 static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
3856 {
3857         bool ret = false;
3858         u32 ctrl_ext, thstat;
3859
3860         /* check for thermal sensor event on i350 copper only */
3861         if (hw->mac.type == e1000_i350) {
3862                 thstat = rd32(E1000_THSTAT);
3863                 ctrl_ext = rd32(E1000_CTRL_EXT);
3864
3865                 if ((hw->phy.media_type == e1000_media_type_copper) &&
3866                     !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
3867                         ret = !!(thstat & event);
3868                 }
3869         }
3870
3871         return ret;
3872 }
3873
3874 /**
3875  * igb_watchdog - Timer Call-back
3876  * @data: pointer to adapter cast into an unsigned long
3877  **/
3878 static void igb_watchdog(unsigned long data)
3879 {
3880         struct igb_adapter *adapter = (struct igb_adapter *)data;
3881         /* Do the rest outside of interrupt context */
3882         schedule_work(&adapter->watchdog_task);
3883 }
3884
3885 static void igb_watchdog_task(struct work_struct *work)
3886 {
3887         struct igb_adapter *adapter = container_of(work,
3888                                                    struct igb_adapter,
3889                                                    watchdog_task);
3890         struct e1000_hw *hw = &adapter->hw;
3891         struct net_device *netdev = adapter->netdev;
3892         u32 link;
3893         int i;
3894
3895         link = igb_has_link(adapter);
3896         if (link) {
3897                 /* Cancel scheduled suspend requests. */
3898                 pm_runtime_resume(netdev->dev.parent);
3899
3900                 if (!netif_carrier_ok(netdev)) {
3901                         u32 ctrl;
3902                         hw->mac.ops.get_speed_and_duplex(hw,
3903                                                          &adapter->link_speed,
3904                                                          &adapter->link_duplex);
3905
3906                         ctrl = rd32(E1000_CTRL);
3907                         /* Links status message must follow this format */
3908                         printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s "
3909                                "Duplex, Flow Control: %s\n",
3910                                netdev->name,
3911                                adapter->link_speed,
3912                                adapter->link_duplex == FULL_DUPLEX ?
3913                                "Full" : "Half",
3914                                (ctrl & E1000_CTRL_TFCE) &&
3915                                (ctrl & E1000_CTRL_RFCE) ? "RX/TX" :
3916                                (ctrl & E1000_CTRL_RFCE) ?  "RX" :
3917                                (ctrl & E1000_CTRL_TFCE) ?  "TX" : "None");
3918
3919                         /* check for thermal sensor event */
3920                         if (igb_thermal_sensor_event(hw,
3921                             E1000_THSTAT_LINK_THROTTLE)) {
3922                                 netdev_info(netdev, "The network adapter link "
3923                                             "speed was downshifted because it "
3924                                             "overheated\n");
3925                         }
3926
3927                         /* adjust timeout factor according to speed/duplex */
3928                         adapter->tx_timeout_factor = 1;
3929                         switch (adapter->link_speed) {
3930                         case SPEED_10:
3931                                 adapter->tx_timeout_factor = 14;
3932                                 break;
3933                         case SPEED_100:
3934                                 /* maybe add some timeout factor ? */
3935                                 break;
3936                         }
3937
3938                         netif_carrier_on(netdev);
3939
3940                         igb_ping_all_vfs(adapter);
3941                         igb_check_vf_rate_limit(adapter);
3942
3943                         /* link state has changed, schedule phy info update */
3944                         if (!test_bit(__IGB_DOWN, &adapter->state))
3945                                 mod_timer(&adapter->phy_info_timer,
3946                                           round_jiffies(jiffies + 2 * HZ));
3947                 }
3948         } else {
3949                 if (netif_carrier_ok(netdev)) {
3950                         adapter->link_speed = 0;
3951                         adapter->link_duplex = 0;
3952
3953                         /* check for thermal sensor event */
3954                         if (igb_thermal_sensor_event(hw,
3955                             E1000_THSTAT_PWR_DOWN)) {
3956                                 netdev_err(netdev, "The network adapter was "
3957                                            "stopped because it overheated\n");
3958                         }
3959
3960                         /* Links status message must follow this format */
3961                         printk(KERN_INFO "igb: %s NIC Link is Down\n",
3962                                netdev->name);
3963                         netif_carrier_off(netdev);
3964
3965                         igb_ping_all_vfs(adapter);
3966
3967                         /* link state has changed, schedule phy info update */
3968                         if (!test_bit(__IGB_DOWN, &adapter->state))
3969                                 mod_timer(&adapter->phy_info_timer,
3970                                           round_jiffies(jiffies + 2 * HZ));
3971
3972                         pm_schedule_suspend(netdev->dev.parent,
3973                                             MSEC_PER_SEC * 5);
3974                 }
3975         }
3976
3977         spin_lock(&adapter->stats64_lock);
3978         igb_update_stats(adapter, &adapter->stats64);
3979         spin_unlock(&adapter->stats64_lock);
3980
3981         for (i = 0; i < adapter->num_tx_queues; i++) {
3982                 struct igb_ring *tx_ring = adapter->tx_ring[i];
3983                 if (!netif_carrier_ok(netdev)) {
3984                         /* We've lost link, so the controller stops DMA,
3985                          * but we've got queued Tx work that's never going
3986                          * to get done, so reset controller to flush Tx.
3987                          * (Do the reset outside of interrupt context). */
3988                         if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
3989                                 adapter->tx_timeout_count++;
3990                                 schedule_work(&adapter->reset_task);
3991                                 /* return immediately since reset is imminent */
3992                                 return;
3993                         }
3994                 }
3995
3996                 /* Force detection of hung controller every watchdog period */
3997                 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3998         }
3999
4000         /* Cause software interrupt to ensure rx ring is cleaned */
4001         if (adapter->msix_entries) {
4002                 u32 eics = 0;
4003                 for (i = 0; i < adapter->num_q_vectors; i++)
4004                         eics |= adapter->q_vector[i]->eims_value;
4005                 wr32(E1000_EICS, eics);
4006         } else {
4007                 wr32(E1000_ICS, E1000_ICS_RXDMT0);
4008         }
4009
4010         igb_spoof_check(adapter);
4011         igb_ptp_rx_hang(adapter);
4012
4013         /* Reset the timer */
4014         if (!test_bit(__IGB_DOWN, &adapter->state))
4015                 mod_timer(&adapter->watchdog_timer,
4016                           round_jiffies(jiffies + 2 * HZ));
4017 }
4018
4019 enum latency_range {
4020         lowest_latency = 0,
4021         low_latency = 1,
4022         bulk_latency = 2,
4023         latency_invalid = 255
4024 };
4025
4026 /**
4027  * igb_update_ring_itr - update the dynamic ITR value based on packet size
4028  *
4029  *      Stores a new ITR value based on strictly on packet size.  This
4030  *      algorithm is less sophisticated than that used in igb_update_itr,
4031  *      due to the difficulty of synchronizing statistics across multiple
4032  *      receive rings.  The divisors and thresholds used by this function
4033  *      were determined based on theoretical maximum wire speed and testing
4034  *      data, in order to minimize response time while increasing bulk
4035  *      throughput.
4036  *      This functionality is controlled by the InterruptThrottleRate module
4037  *      parameter (see igb_param.c)
4038  *      NOTE:  This function is called only when operating in a multiqueue
4039  *             receive environment.
4040  * @q_vector: pointer to q_vector
4041  **/
4042 static void igb_update_ring_itr(struct igb_q_vector *q_vector)
4043 {
4044         int new_val = q_vector->itr_val;
4045         int avg_wire_size = 0;
4046         struct igb_adapter *adapter = q_vector->adapter;
4047         unsigned int packets;
4048
4049         /* For non-gigabit speeds, just fix the interrupt rate at 4000
4050          * ints/sec - ITR timer value of 120 ticks.
4051          */
4052         if (adapter->link_speed != SPEED_1000) {
4053                 new_val = IGB_4K_ITR;
4054                 goto set_itr_val;
4055         }
4056
4057         packets = q_vector->rx.total_packets;
4058         if (packets)
4059                 avg_wire_size = q_vector->rx.total_bytes / packets;
4060
4061         packets = q_vector->tx.total_packets;
4062         if (packets)
4063                 avg_wire_size = max_t(u32, avg_wire_size,
4064                                       q_vector->tx.total_bytes / packets);
4065
4066         /* if avg_wire_size isn't set no work was done */
4067         if (!avg_wire_size)
4068                 goto clear_counts;
4069
4070         /* Add 24 bytes to size to account for CRC, preamble, and gap */
4071         avg_wire_size += 24;
4072
4073         /* Don't starve jumbo frames */
4074         avg_wire_size = min(avg_wire_size, 3000);
4075
4076         /* Give a little boost to mid-size frames */
4077         if ((avg_wire_size > 300) && (avg_wire_size < 1200))
4078                 new_val = avg_wire_size / 3;
4079         else
4080                 new_val = avg_wire_size / 2;
4081
4082         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4083         if (new_val < IGB_20K_ITR &&
4084             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4085              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4086                 new_val = IGB_20K_ITR;
4087
4088 set_itr_val:
4089         if (new_val != q_vector->itr_val) {
4090                 q_vector->itr_val = new_val;
4091                 q_vector->set_itr = 1;
4092         }
4093 clear_counts:
4094         q_vector->rx.total_bytes = 0;
4095         q_vector->rx.total_packets = 0;
4096         q_vector->tx.total_bytes = 0;
4097         q_vector->tx.total_packets = 0;
4098 }
4099
4100 /**
4101  * igb_update_itr - update the dynamic ITR value based on statistics
4102  *      Stores a new ITR value based on packets and byte
4103  *      counts during the last interrupt.  The advantage of per interrupt
4104  *      computation is faster updates and more accurate ITR for the current
4105  *      traffic pattern.  Constants in this function were computed
4106  *      based on theoretical maximum wire speed and thresholds were set based
4107  *      on testing data as well as attempting to minimize response time
4108  *      while increasing bulk throughput.
4109  *      this functionality is controlled by the InterruptThrottleRate module
4110  *      parameter (see igb_param.c)
4111  *      NOTE:  These calculations are only valid when operating in a single-
4112  *             queue environment.
4113  * @q_vector: pointer to q_vector
4114  * @ring_container: ring info to update the itr for
4115  **/
4116 static void igb_update_itr(struct igb_q_vector *q_vector,
4117                            struct igb_ring_container *ring_container)
4118 {
4119         unsigned int packets = ring_container->total_packets;
4120         unsigned int bytes = ring_container->total_bytes;
4121         u8 itrval = ring_container->itr;
4122
4123         /* no packets, exit with status unchanged */
4124         if (packets == 0)
4125                 return;
4126
4127         switch (itrval) {
4128         case lowest_latency:
4129                 /* handle TSO and jumbo frames */
4130                 if (bytes/packets > 8000)
4131                         itrval = bulk_latency;
4132                 else if ((packets < 5) && (bytes > 512))
4133                         itrval = low_latency;
4134                 break;
4135         case low_latency:  /* 50 usec aka 20000 ints/s */
4136                 if (bytes > 10000) {
4137                         /* this if handles the TSO accounting */
4138                         if (bytes/packets > 8000) {
4139                                 itrval = bulk_latency;
4140                         } else if ((packets < 10) || ((bytes/packets) > 1200)) {
4141                                 itrval = bulk_latency;
4142                         } else if ((packets > 35)) {
4143                                 itrval = lowest_latency;
4144                         }
4145                 } else if (bytes/packets > 2000) {
4146                         itrval = bulk_latency;
4147                 } else if (packets <= 2 && bytes < 512) {
4148                         itrval = lowest_latency;
4149                 }
4150                 break;
4151         case bulk_latency: /* 250 usec aka 4000 ints/s */
4152                 if (bytes > 25000) {
4153                         if (packets > 35)
4154                                 itrval = low_latency;
4155                 } else if (bytes < 1500) {
4156                         itrval = low_latency;
4157                 }
4158                 break;
4159         }
4160
4161         /* clear work counters since we have the values we need */
4162         ring_container->total_bytes = 0;
4163         ring_container->total_packets = 0;
4164
4165         /* write updated itr to ring container */
4166         ring_container->itr = itrval;
4167 }
4168
4169 static void igb_set_itr(struct igb_q_vector *q_vector)
4170 {
4171         struct igb_adapter *adapter = q_vector->adapter;
4172         u32 new_itr = q_vector->itr_val;
4173         u8 current_itr = 0;
4174
4175         /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4176         if (adapter->link_speed != SPEED_1000) {
4177                 current_itr = 0;
4178                 new_itr = IGB_4K_ITR;
4179                 goto set_itr_now;
4180         }
4181
4182         igb_update_itr(q_vector, &q_vector->tx);
4183         igb_update_itr(q_vector, &q_vector->rx);
4184
4185         current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
4186
4187         /* conservative mode (itr 3) eliminates the lowest_latency setting */
4188         if (current_itr == lowest_latency &&
4189             ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
4190              (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
4191                 current_itr = low_latency;
4192
4193         switch (current_itr) {
4194         /* counts and packets in update_itr are dependent on these numbers */
4195         case lowest_latency:
4196                 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
4197                 break;
4198         case low_latency:
4199                 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
4200                 break;
4201         case bulk_latency:
4202                 new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
4203                 break;
4204         default:
4205                 break;
4206         }
4207
4208 set_itr_now:
4209         if (new_itr != q_vector->itr_val) {
4210                 /* this attempts to bias the interrupt rate towards Bulk
4211                  * by adding intermediate steps when interrupt rate is
4212                  * increasing */
4213                 new_itr = new_itr > q_vector->itr_val ?
4214                              max((new_itr * q_vector->itr_val) /
4215                                  (new_itr + (q_vector->itr_val >> 2)),
4216                                  new_itr) :
4217                              new_itr;
4218                 /* Don't write the value here; it resets the adapter's
4219                  * internal timer, and causes us to delay far longer than
4220                  * we should between interrupts.  Instead, we write the ITR
4221                  * value at the beginning of the next interrupt so the timing
4222                  * ends up being correct.
4223                  */
4224                 q_vector->itr_val = new_itr;
4225                 q_vector->set_itr = 1;
4226         }
4227 }
4228
4229 static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
4230                             u32 type_tucmd, u32 mss_l4len_idx)
4231 {
4232         struct e1000_adv_tx_context_desc *context_desc;
4233         u16 i = tx_ring->next_to_use;
4234
4235         context_desc = IGB_TX_CTXTDESC(tx_ring, i);
4236
4237         i++;
4238         tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
4239
4240         /* set bits to identify this as an advanced context descriptor */
4241         type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4242
4243         /* For 82575, context index must be unique per ring. */
4244         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4245                 mss_l4len_idx |= tx_ring->reg_idx << 4;
4246
4247         context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
4248         context_desc->seqnum_seed       = 0;
4249         context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
4250         context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);
4251 }
4252
4253 static int igb_tso(struct igb_ring *tx_ring,
4254                    struct igb_tx_buffer *first,
4255                    u8 *hdr_len)
4256 {
4257         struct sk_buff *skb = first->skb;
4258         u32 vlan_macip_lens, type_tucmd;
4259         u32 mss_l4len_idx, l4len;
4260
4261         if (skb->ip_summed != CHECKSUM_PARTIAL)
4262                 return 0;
4263
4264         if (!skb_is_gso(skb))
4265                 return 0;
4266
4267         if (skb_header_cloned(skb)) {
4268                 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4269                 if (err)
4270                         return err;
4271         }
4272
4273         /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4274         type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4275
4276         if (first->protocol == __constant_htons(ETH_P_IP)) {
4277                 struct iphdr *iph = ip_hdr(skb);
4278                 iph->tot_len = 0;
4279                 iph->check = 0;
4280                 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4281                                                          iph->daddr, 0,
4282                                                          IPPROTO_TCP,
4283                                                          0);
4284                 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4285                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4286                                    IGB_TX_FLAGS_CSUM |
4287                                    IGB_TX_FLAGS_IPV4;
4288         } else if (skb_is_gso_v6(skb)) {
4289                 ipv6_hdr(skb)->payload_len = 0;
4290                 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4291                                                        &ipv6_hdr(skb)->daddr,
4292                                                        0, IPPROTO_TCP, 0);
4293                 first->tx_flags |= IGB_TX_FLAGS_TSO |
4294                                    IGB_TX_FLAGS_CSUM;
4295         }
4296
4297         /* compute header lengths */
4298         l4len = tcp_hdrlen(skb);
4299         *hdr_len = skb_transport_offset(skb) + l4len;
4300
4301         /* update gso size and bytecount with header size */
4302         first->gso_segs = skb_shinfo(skb)->gso_segs;
4303         first->bytecount += (first->gso_segs - 1) * *hdr_len;
4304
4305         /* MSS L4LEN IDX */
4306         mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
4307         mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4308
4309         /* VLAN MACLEN IPLEN */
4310         vlan_macip_lens = skb_network_header_len(skb);
4311         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4312         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4313
4314         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4315
4316         return 1;
4317 }
4318
4319 static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4320 {
4321         struct sk_buff *skb = first->skb;
4322         u32 vlan_macip_lens = 0;
4323         u32 mss_l4len_idx = 0;
4324         u32 type_tucmd = 0;
4325
4326         if (skb->ip_summed != CHECKSUM_PARTIAL) {
4327                 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
4328                         return;
4329         } else {
4330                 u8 l4_hdr = 0;
4331                 switch (first->protocol) {
4332                 case __constant_htons(ETH_P_IP):
4333                         vlan_macip_lens |= skb_network_header_len(skb);
4334                         type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4335                         l4_hdr = ip_hdr(skb)->protocol;
4336                         break;
4337                 case __constant_htons(ETH_P_IPV6):
4338                         vlan_macip_lens |= skb_network_header_len(skb);
4339                         l4_hdr = ipv6_hdr(skb)->nexthdr;
4340                         break;
4341                 default:
4342                         if (unlikely(net_ratelimit())) {
4343                                 dev_warn(tx_ring->dev,
4344                                  "partial checksum but proto=%x!\n",
4345                                  first->protocol);
4346                         }
4347                         break;
4348                 }
4349
4350                 switch (l4_hdr) {
4351                 case IPPROTO_TCP:
4352                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
4353                         mss_l4len_idx = tcp_hdrlen(skb) <<
4354                                         E1000_ADVTXD_L4LEN_SHIFT;
4355                         break;
4356                 case IPPROTO_SCTP:
4357                         type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
4358                         mss_l4len_idx = sizeof(struct sctphdr) <<
4359                                         E1000_ADVTXD_L4LEN_SHIFT;
4360                         break;
4361                 case IPPROTO_UDP:
4362                         mss_l4len_idx = sizeof(struct udphdr) <<
4363                                         E1000_ADVTXD_L4LEN_SHIFT;
4364                         break;
4365                 default:
4366                         if (unlikely(net_ratelimit())) {
4367                                 dev_warn(tx_ring->dev,
4368                                  "partial checksum but l4 proto=%x!\n",
4369                                  l4_hdr);
4370                         }
4371                         break;
4372                 }
4373
4374                 /* update TX checksum flag */
4375                 first->tx_flags |= IGB_TX_FLAGS_CSUM;
4376         }
4377
4378         vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4379         vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4380
4381         igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4382 }
4383
4384 #define IGB_SET_FLAG(_input, _flag, _result) \
4385         ((_flag <= _result) ? \
4386          ((u32)(_input & _flag) * (_result / _flag)) : \
4387          ((u32)(_input & _flag) / (_flag / _result)))
4388
4389 static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
4390 {
4391         /* set type for advanced descriptor with frame checksum insertion */
4392         u32 cmd_type = E1000_ADVTXD_DTYP_DATA |
4393                        E1000_ADVTXD_DCMD_DEXT |
4394                        E1000_ADVTXD_DCMD_IFCS;
4395
4396         /* set HW vlan bit if vlan is present */
4397         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN,
4398                                  (E1000_ADVTXD_DCMD_VLE));
4399
4400         /* set segmentation bits for TSO */
4401         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO,
4402                                  (E1000_ADVTXD_DCMD_TSE));
4403
4404         /* set timestamp bit if present */
4405         cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP,
4406                                  (E1000_ADVTXD_MAC_TSTAMP));
4407
4408         /* insert frame checksum */
4409         cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS);
4410
4411         return cmd_type;
4412 }
4413
4414 static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
4415                                  union e1000_adv_tx_desc *tx_desc,
4416                                  u32 tx_flags, unsigned int paylen)
4417 {
4418         u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;
4419
4420         /* 82575 requires a unique index per ring */
4421         if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4422                 olinfo_status |= tx_ring->reg_idx << 4;
4423
4424         /* insert L4 checksum */
4425         olinfo_status |= IGB_SET_FLAG(tx_flags,
4426                                       IGB_TX_FLAGS_CSUM,
4427                                       (E1000_TXD_POPTS_TXSM << 8));
4428
4429         /* insert IPv4 checksum */
4430         olinfo_status |= IGB_SET_FLAG(tx_flags,
4431                                       IGB_TX_FLAGS_IPV4,
4432                                       (E1000_TXD_POPTS_IXSM << 8));
4433
4434         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4435 }
4436
4437 static void igb_tx_map(struct igb_ring *tx_ring,
4438                        struct igb_tx_buffer *first,
4439                        const u8 hdr_len)
4440 {
4441         struct sk_buff *skb = first->skb;
4442         struct igb_tx_buffer *tx_buffer;
4443         union e1000_adv_tx_desc *tx_desc;
4444         struct skb_frag_struct *frag;
4445         dma_addr_t dma;
4446         unsigned int data_len, size;
4447         u32 tx_flags = first->tx_flags;
4448         u32 cmd_type = igb_tx_cmd_type(skb, tx_flags);
4449         u16 i = tx_ring->next_to_use;
4450
4451         tx_desc = IGB_TX_DESC(tx_ring, i);
4452
4453         igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);
4454
4455         size = skb_headlen(skb);
4456         data_len = skb->data_len;
4457
4458         dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
4459
4460         tx_buffer = first;
4461
4462         for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
4463                 if (dma_mapping_error(tx_ring->dev, dma))
4464                         goto dma_error;
4465
4466                 /* record length, and DMA address */
4467                 dma_unmap_len_set(tx_buffer, len, size);
4468                 dma_unmap_addr_set(tx_buffer, dma, dma);
4469
4470                 tx_desc->read.buffer_addr = cpu_to_le64(dma);
4471
4472                 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
4473                         tx_desc->read.cmd_type_len =
4474                                 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD);
4475
4476                         i++;
4477                         tx_desc++;
4478                         if (i == tx_ring->count) {
4479                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
4480                                 i = 0;
4481                         }
4482                         tx_desc->read.olinfo_status = 0;
4483
4484                         dma += IGB_MAX_DATA_PER_TXD;
4485                         size -= IGB_MAX_DATA_PER_TXD;
4486
4487                         tx_desc->read.buffer_addr = cpu_to_le64(dma);
4488                 }
4489
4490                 if (likely(!data_len))
4491                         break;
4492
4493                 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
4494
4495                 i++;
4496                 tx_desc++;
4497                 if (i == tx_ring->count) {
4498                         tx_desc = IGB_TX_DESC(tx_ring, 0);
4499                         i = 0;
4500                 }
4501                 tx_desc->read.olinfo_status = 0;
4502
4503                 size = skb_frag_size(frag);
4504                 data_len -= size;
4505
4506                 dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
4507                                        size, DMA_TO_DEVICE);
4508
4509                 tx_buffer = &tx_ring->tx_buffer_info[i];
4510         }
4511
4512         /* write last descriptor with RS and EOP bits */
4513         cmd_type |= size | IGB_TXD_DCMD;
4514         tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
4515
4516         netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
4517
4518         /* set the timestamp */
4519         first->time_stamp = jiffies;
4520
4521         /*
4522          * Force memory writes to complete before letting h/w know there
4523          * are new descriptors to fetch.  (Only applicable for weak-ordered
4524          * memory model archs, such as IA-64).
4525          *
4526          * We also need this memory barrier to make certain all of the
4527          * status bits have been updated before next_to_watch is written.
4528          */
4529         wmb();
4530
4531         /* set next_to_watch value indicating a packet is present */
4532         first->next_to_watch = tx_desc;
4533
4534         i++;
4535         if (i == tx_ring->count)
4536                 i = 0;
4537
4538         tx_ring->next_to_use = i;
4539
4540         writel(i, tx_ring->tail);
4541
4542         /* we need this if more than one processor can write to our tail
4543          * at a time, it syncronizes IO on IA64/Altix systems */
4544         mmiowb();
4545
4546         return;
4547
4548 dma_error:
4549         dev_err(tx_ring->dev, "TX DMA map failed\n");
4550
4551         /* clear dma mappings for failed tx_buffer_info map */
4552         for (;;) {
4553                 tx_buffer = &tx_ring->tx_buffer_info[i];
4554                 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer);
4555                 if (tx_buffer == first)
4556                         break;
4557                 if (i == 0)
4558                         i = tx_ring->count;
4559                 i--;
4560         }
4561
4562         tx_ring->next_to_use = i;
4563 }
4564
4565 static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4566 {
4567         struct net_device *netdev = tx_ring->netdev;
4568
4569         netif_stop_subqueue(netdev, tx_ring->queue_index);
4570
4571         /* Herbert's original patch had:
4572          *  smp_mb__after_netif_stop_queue();
4573          * but since that doesn't exist yet, just open code it. */
4574         smp_mb();
4575
4576         /* We need to check again in a case another CPU has just
4577          * made room available. */
4578         if (igb_desc_unused(tx_ring) < size)
4579                 return -EBUSY;
4580
4581         /* A reprieve! */
4582         netif_wake_subqueue(netdev, tx_ring->queue_index);
4583
4584         u64_stats_update_begin(&tx_ring->tx_syncp2);
4585         tx_ring->tx_stats.restart_queue2++;
4586         u64_stats_update_end(&tx_ring->tx_syncp2);
4587
4588         return 0;
4589 }
4590
4591 static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4592 {
4593         if (igb_desc_unused(tx_ring) >= size)
4594                 return 0;
4595         return __igb_maybe_stop_tx(tx_ring, size);
4596 }
4597
4598 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
4599                                 struct igb_ring *tx_ring)
4600 {
4601         struct igb_adapter *adapter = netdev_priv(tx_ring->netdev);
4602         struct igb_tx_buffer *first;
4603         int tso;
4604         u32 tx_flags = 0;
4605         u16 count = TXD_USE_COUNT(skb_headlen(skb));
4606         __be16 protocol = vlan_get_protocol(skb);
4607         u8 hdr_len = 0;
4608
4609         /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4610          *       + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4611          *       + 2 desc gap to keep tail from touching head,
4612          *       + 1 desc for context descriptor,
4613          * otherwise try next time
4614          */
4615         if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) {
4616                 unsigned short f;
4617                 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
4618                         count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
4619         } else {
4620                 count += skb_shinfo(skb)->nr_frags;
4621         }
4622
4623         if (igb_maybe_stop_tx(tx_ring, count + 3)) {
4624                 /* this is a hard error */
4625                 return NETDEV_TX_BUSY;
4626         }
4627
4628         /* record the location of the first descriptor for this packet */
4629         first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
4630         first->skb = skb;
4631         first->bytecount = skb->len;
4632         first->gso_segs = 1;
4633
4634         skb_tx_timestamp(skb);
4635
4636         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
4637                      !(adapter->ptp_tx_skb))) {
4638                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4639                 tx_flags |= IGB_TX_FLAGS_TSTAMP;
4640
4641                 adapter->ptp_tx_skb = skb_get(skb);
4642                 adapter->ptp_tx_start = jiffies;
4643                 if (adapter->hw.mac.type == e1000_82576)
4644                         schedule_work(&adapter->ptp_tx_work);
4645         }
4646
4647         if (vlan_tx_tag_present(skb)) {
4648                 tx_flags |= IGB_TX_FLAGS_VLAN;
4649                 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
4650         }
4651
4652         /* record initial flags and protocol */
4653         first->tx_flags = tx_flags;
4654         first->protocol = protocol;
4655
4656         tso = igb_tso(tx_ring, first, &hdr_len);
4657         if (tso < 0)
4658                 goto out_drop;
4659         else if (!tso)
4660                 igb_tx_csum(tx_ring, first);
4661
4662         igb_tx_map(tx_ring, first, hdr_len);
4663
4664         /* Make sure there is space in the ring for the next send. */
4665         igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
4666
4667         return NETDEV_TX_OK;
4668
4669 out_drop:
4670         igb_unmap_and_free_tx_resource(tx_ring, first);
4671
4672         return NETDEV_TX_OK;
4673 }
4674
4675 static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
4676                                                     struct sk_buff *skb)
4677 {
4678         unsigned int r_idx = skb->queue_mapping;
4679
4680         if (r_idx >= adapter->num_tx_queues)
4681                 r_idx = r_idx % adapter->num_tx_queues;
4682
4683         return adapter->tx_ring[r_idx];
4684 }
4685
4686 static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
4687                                   struct net_device *netdev)
4688 {
4689         struct igb_adapter *adapter = netdev_priv(netdev);
4690
4691         if (test_bit(__IGB_DOWN, &adapter->state)) {
4692                 dev_kfree_skb_any(skb);
4693                 return NETDEV_TX_OK;
4694         }
4695
4696         if (skb->len <= 0) {
4697                 dev_kfree_skb_any(skb);
4698                 return NETDEV_TX_OK;
4699         }
4700
4701         /*
4702          * The minimum packet size with TCTL.PSP set is 17 so pad the skb
4703          * in order to meet this minimum size requirement.
4704          */
4705         if (unlikely(skb->len < 17)) {
4706                 if (skb_pad(skb, 17 - skb->len))
4707                         return NETDEV_TX_OK;
4708                 skb->len = 17;
4709                 skb_set_tail_pointer(skb, 17);
4710         }
4711
4712         return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4713 }
4714
4715 /**
4716  * igb_tx_timeout - Respond to a Tx Hang
4717  * @netdev: network interface device structure
4718  **/
4719 static void igb_tx_timeout(struct net_device *netdev)
4720 {
4721         struct igb_adapter *adapter = netdev_priv(netdev);
4722         struct e1000_hw *hw = &adapter->hw;
4723
4724         /* Do the reset outside of interrupt context */
4725         adapter->tx_timeout_count++;
4726
4727         if (hw->mac.type >= e1000_82580)
4728                 hw->dev_spec._82575.global_device_reset = true;
4729
4730         schedule_work(&adapter->reset_task);
4731         wr32(E1000_EICS,
4732              (adapter->eims_enable_mask & ~adapter->eims_other));
4733 }
4734
4735 static void igb_reset_task(struct work_struct *work)
4736 {
4737         struct igb_adapter *adapter;
4738         adapter = container_of(work, struct igb_adapter, reset_task);
4739
4740         igb_dump(adapter);
4741         netdev_err(adapter->netdev, "Reset adapter\n");
4742         igb_reinit_locked(adapter);
4743 }
4744
4745 /**
4746  * igb_get_stats64 - Get System Network Statistics
4747  * @netdev: network interface device structure
4748  * @stats: rtnl_link_stats64 pointer
4749  *
4750  **/
4751 static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
4752                                                  struct rtnl_link_stats64 *stats)
4753 {
4754         struct igb_adapter *adapter = netdev_priv(netdev);
4755
4756         spin_lock(&adapter->stats64_lock);
4757         igb_update_stats(adapter, &adapter->stats64);
4758         memcpy(stats, &adapter->stats64, sizeof(*stats));
4759         spin_unlock(&adapter->stats64_lock);
4760
4761         return stats;
4762 }
4763
4764 /**
4765  * igb_change_mtu - Change the Maximum Transfer Unit
4766  * @netdev: network interface device structure
4767  * @new_mtu: new value for maximum frame size
4768  *
4769  * Returns 0 on success, negative on failure
4770  **/
4771 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
4772 {
4773         struct igb_adapter *adapter = netdev_priv(netdev);
4774         struct pci_dev *pdev = adapter->pdev;
4775         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4776
4777         if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4778                 dev_err(&pdev->dev, "Invalid MTU setting\n");
4779                 return -EINVAL;
4780         }
4781
4782 #define MAX_STD_JUMBO_FRAME_SIZE 9238
4783         if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4784                 dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4785                 return -EINVAL;
4786         }
4787
4788         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
4789                 msleep(1);
4790
4791         /* igb_down has a dependency on max_frame_size */
4792         adapter->max_frame_size = max_frame;
4793
4794         if (netif_running(netdev))
4795                 igb_down(adapter);
4796
4797         dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4798                  netdev->mtu, new_mtu);
4799         netdev->mtu = new_mtu;
4800
4801         if (netif_running(netdev))
4802                 igb_up(adapter);
4803         else
4804                 igb_reset(adapter);
4805
4806         clear_bit(__IGB_RESETTING, &adapter->state);
4807
4808         return 0;
4809 }
4810
4811 /**
4812  * igb_update_stats - Update the board statistics counters
4813  * @adapter: board private structure
4814  **/
4815
4816 void igb_update_stats(struct igb_adapter *adapter,
4817                       struct rtnl_link_stats64 *net_stats)
4818 {
4819         struct e1000_hw *hw = &adapter->hw;
4820         struct pci_dev *pdev = adapter->pdev;
4821         u32 reg, mpc;
4822         u16 phy_tmp;
4823         int i;
4824         u64 bytes, packets;
4825         unsigned int start;
4826         u64 _bytes, _packets;
4827
4828 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
4829
4830         /*
4831          * Prevent stats update while adapter is being reset, or if the pci
4832          * connection is down.
4833          */
4834         if (adapter->link_speed == 0)
4835                 return;
4836         if (pci_channel_offline(pdev))
4837                 return;
4838
4839         bytes = 0;
4840         packets = 0;
4841         for (i = 0; i < adapter->num_rx_queues; i++) {
4842                 u32 rqdpc = rd32(E1000_RQDPC(i));
4843                 struct igb_ring *ring = adapter->rx_ring[i];
4844
4845                 if (rqdpc) {
4846                         ring->rx_stats.drops += rqdpc;
4847                         net_stats->rx_fifo_errors += rqdpc;
4848                 }
4849
4850                 do {
4851                         start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
4852                         _bytes = ring->rx_stats.bytes;
4853                         _packets = ring->rx_stats.packets;
4854                 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
4855                 bytes += _bytes;
4856                 packets += _packets;
4857         }
4858
4859         net_stats->rx_bytes = bytes;
4860         net_stats->rx_packets = packets;
4861
4862         bytes = 0;
4863         packets = 0;
4864         for (i = 0; i < adapter->num_tx_queues; i++) {
4865                 struct igb_ring *ring = adapter->tx_ring[i];
4866                 do {
4867                         start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
4868                         _bytes = ring->tx_stats.bytes;
4869                         _packets = ring->tx_stats.packets;
4870                 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
4871                 bytes += _bytes;
4872                 packets += _packets;
4873         }
4874         net_stats->tx_bytes = bytes;
4875         net_stats->tx_packets = packets;
4876
4877         /* read stats registers */
4878         adapter->stats.crcerrs += rd32(E1000_CRCERRS);
4879         adapter->stats.gprc += rd32(E1000_GPRC);
4880         adapter->stats.gorc += rd32(E1000_GORCL);
4881         rd32(E1000_GORCH); /* clear GORCL */
4882         adapter->stats.bprc += rd32(E1000_BPRC);
4883         adapter->stats.mprc += rd32(E1000_MPRC);
4884         adapter->stats.roc += rd32(E1000_ROC);
4885
4886         adapter->stats.prc64 += rd32(E1000_PRC64);
4887         adapter->stats.prc127 += rd32(E1000_PRC127);
4888         adapter->stats.prc255 += rd32(E1000_PRC255);
4889         adapter->stats.prc511 += rd32(E1000_PRC511);
4890         adapter->stats.prc1023 += rd32(E1000_PRC1023);
4891         adapter->stats.prc1522 += rd32(E1000_PRC1522);
4892         adapter->stats.symerrs += rd32(E1000_SYMERRS);
4893         adapter->stats.sec += rd32(E1000_SEC);
4894
4895         mpc = rd32(E1000_MPC);
4896         adapter->stats.mpc += mpc;
4897         net_stats->rx_fifo_errors += mpc;
4898         adapter->stats.scc += rd32(E1000_SCC);
4899         adapter->stats.ecol += rd32(E1000_ECOL);
4900         adapter->stats.mcc += rd32(E1000_MCC);
4901         adapter->stats.latecol += rd32(E1000_LATECOL);
4902         adapter->stats.dc += rd32(E1000_DC);
4903         adapter->stats.rlec += rd32(E1000_RLEC);
4904         adapter->stats.xonrxc += rd32(E1000_XONRXC);
4905         adapter->stats.xontxc += rd32(E1000_XONTXC);
4906         adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
4907         adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
4908         adapter->stats.fcruc += rd32(E1000_FCRUC);
4909         adapter->stats.gptc += rd32(E1000_GPTC);
4910         adapter->stats.gotc += rd32(E1000_GOTCL);
4911         rd32(E1000_GOTCH); /* clear GOTCL */
4912         adapter->stats.rnbc += rd32(E1000_RNBC);
4913         adapter->stats.ruc += rd32(E1000_RUC);
4914         adapter->stats.rfc += rd32(E1000_RFC);
4915         adapter->stats.rjc += rd32(E1000_RJC);
4916         adapter->stats.tor += rd32(E1000_TORH);
4917         adapter->stats.tot += rd32(E1000_TOTH);
4918         adapter->stats.tpr += rd32(E1000_TPR);
4919
4920         adapter->stats.ptc64 += rd32(E1000_PTC64);
4921         adapter->stats.ptc127 += rd32(E1000_PTC127);
4922         adapter->stats.ptc255 += rd32(E1000_PTC255);
4923         adapter->stats.ptc511 += rd32(E1000_PTC511);
4924         adapter->stats.ptc1023 += rd32(E1000_PTC1023);
4925         adapter->stats.ptc1522 += rd32(E1000_PTC1522);
4926
4927         adapter->stats.mptc += rd32(E1000_MPTC);
4928         adapter->stats.bptc += rd32(E1000_BPTC);
4929
4930         adapter->stats.tpt += rd32(E1000_TPT);
4931         adapter->stats.colc += rd32(E1000_COLC);
4932
4933         adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4934         /* read internal phy specific stats */
4935         reg = rd32(E1000_CTRL_EXT);
4936         if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
4937                 adapter->stats.rxerrc += rd32(E1000_RXERRC);
4938
4939                 /* this stat has invalid values on i210/i211 */
4940                 if ((hw->mac.type != e1000_i210) &&
4941                     (hw->mac.type != e1000_i211))
4942                         adapter->stats.tncrs += rd32(E1000_TNCRS);
4943         }
4944
4945         adapter->stats.tsctc += rd32(E1000_TSCTC);
4946         adapter->stats.tsctfc += rd32(E1000_TSCTFC);
4947
4948         adapter->stats.iac += rd32(E1000_IAC);
4949         adapter->stats.icrxoc += rd32(E1000_ICRXOC);
4950         adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
4951         adapter->stats.icrxatc += rd32(E1000_ICRXATC);
4952         adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
4953         adapter->stats.ictxatc += rd32(E1000_ICTXATC);
4954         adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
4955         adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
4956         adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
4957
4958         /* Fill out the OS statistics structure */
4959         net_stats->multicast = adapter->stats.mprc;
4960         net_stats->collisions = adapter->stats.colc;
4961
4962         /* Rx Errors */
4963
4964         /* RLEC on some newer hardware can be incorrect so build
4965          * our own version based on RUC and ROC */
4966         net_stats->rx_errors = adapter->stats.rxerrc +
4967                 adapter->stats.crcerrs + adapter->stats.algnerrc +
4968                 adapter->stats.ruc + adapter->stats.roc +
4969                 adapter->stats.cexterr;
4970         net_stats->rx_length_errors = adapter->stats.ruc +
4971                                       adapter->stats.roc;
4972         net_stats->rx_crc_errors = adapter->stats.crcerrs;
4973         net_stats->rx_frame_errors = adapter->stats.algnerrc;
4974         net_stats->rx_missed_errors = adapter->stats.mpc;
4975
4976         /* Tx Errors */
4977         net_stats->tx_errors = adapter->stats.ecol +
4978                                adapter->stats.latecol;
4979         net_stats->tx_aborted_errors = adapter->stats.ecol;
4980         net_stats->tx_window_errors = adapter->stats.latecol;
4981         net_stats->tx_carrier_errors = adapter->stats.tncrs;
4982
4983         /* Tx Dropped needs to be maintained elsewhere */
4984
4985         /* Phy Stats */
4986         if (hw->phy.media_type == e1000_media_type_copper) {
4987                 if ((adapter->link_speed == SPEED_1000) &&
4988                    (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4989                         phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
4990                         adapter->phy_stats.idle_errors += phy_tmp;
4991                 }
4992         }
4993
4994         /* Management Stats */
4995         adapter->stats.mgptc += rd32(E1000_MGTPTC);
4996         adapter->stats.mgprc += rd32(E1000_MGTPRC);
4997         adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4998
4999         /* OS2BMC Stats */
5000         reg = rd32(E1000_MANC);
5001         if (reg & E1000_MANC_EN_BMC2OS) {
5002                 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
5003                 adapter->stats.o2bspc += rd32(E1000_O2BSPC);
5004                 adapter->stats.b2ospc += rd32(E1000_B2OSPC);
5005                 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
5006         }
5007 }
5008
5009 static irqreturn_t igb_msix_other(int irq, void *data)
5010 {
5011         struct igb_adapter *adapter = data;
5012         struct e1000_hw *hw = &adapter->hw;
5013         u32 icr = rd32(E1000_ICR);
5014         /* reading ICR causes bit 31 of EICR to be cleared */
5015
5016         if (icr & E1000_ICR_DRSTA)
5017                 schedule_work(&adapter->reset_task);
5018
5019         if (icr & E1000_ICR_DOUTSYNC) {
5020                 /* HW is reporting DMA is out of sync */
5021                 adapter->stats.doosync++;
5022                 /* The DMA Out of Sync is also indication of a spoof event
5023                  * in IOV mode. Check the Wrong VM Behavior register to
5024                  * see if it is really a spoof event. */
5025                 igb_check_wvbr(adapter);
5026         }
5027
5028         /* Check for a mailbox event */
5029         if (icr & E1000_ICR_VMMB)
5030                 igb_msg_task(adapter);
5031
5032         if (icr & E1000_ICR_LSC) {
5033                 hw->mac.get_link_status = 1;
5034                 /* guard against interrupt when we're going down */
5035                 if (!test_bit(__IGB_DOWN, &adapter->state))
5036                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5037         }
5038
5039         if (icr & E1000_ICR_TS) {
5040                 u32 tsicr = rd32(E1000_TSICR);
5041
5042                 if (tsicr & E1000_TSICR_TXTS) {
5043                         /* acknowledge the interrupt */
5044                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5045                         /* retrieve hardware timestamp */
5046                         schedule_work(&adapter->ptp_tx_work);
5047                 }
5048         }
5049
5050         wr32(E1000_EIMS, adapter->eims_other);
5051
5052         return IRQ_HANDLED;
5053 }
5054
5055 static void igb_write_itr(struct igb_q_vector *q_vector)
5056 {
5057         struct igb_adapter *adapter = q_vector->adapter;
5058         u32 itr_val = q_vector->itr_val & 0x7FFC;
5059
5060         if (!q_vector->set_itr)
5061                 return;
5062
5063         if (!itr_val)
5064                 itr_val = 0x4;
5065
5066         if (adapter->hw.mac.type == e1000_82575)
5067                 itr_val |= itr_val << 16;
5068         else
5069                 itr_val |= E1000_EITR_CNT_IGNR;
5070
5071         writel(itr_val, q_vector->itr_register);
5072         q_vector->set_itr = 0;
5073 }
5074
5075 static irqreturn_t igb_msix_ring(int irq, void *data)
5076 {
5077         struct igb_q_vector *q_vector = data;
5078
5079         /* Write the ITR value calculated from the previous interrupt. */
5080         igb_write_itr(q_vector);
5081
5082         napi_schedule(&q_vector->napi);
5083
5084         return IRQ_HANDLED;
5085 }
5086
5087 #ifdef CONFIG_IGB_DCA
5088 static void igb_update_tx_dca(struct igb_adapter *adapter,
5089                               struct igb_ring *tx_ring,
5090                               int cpu)
5091 {
5092         struct e1000_hw *hw = &adapter->hw;
5093         u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
5094
5095         if (hw->mac.type != e1000_82575)
5096                 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT;
5097
5098         /*
5099          * We can enable relaxed ordering for reads, but not writes when
5100          * DCA is enabled.  This is due to a known issue in some chipsets
5101          * which will cause the DCA tag to be cleared.
5102          */
5103         txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN |
5104                   E1000_DCA_TXCTRL_DATA_RRO_EN |
5105                   E1000_DCA_TXCTRL_DESC_DCA_EN;
5106
5107         wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl);
5108 }
5109
5110 static void igb_update_rx_dca(struct igb_adapter *adapter,
5111                               struct igb_ring *rx_ring,
5112                               int cpu)
5113 {
5114         struct e1000_hw *hw = &adapter->hw;
5115         u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu);
5116
5117         if (hw->mac.type != e1000_82575)
5118                 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT;
5119
5120         /*
5121          * We can enable relaxed ordering for reads, but not writes when
5122          * DCA is enabled.  This is due to a known issue in some chipsets
5123          * which will cause the DCA tag to be cleared.
5124          */
5125         rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN |
5126                   E1000_DCA_RXCTRL_DESC_DCA_EN;
5127
5128         wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl);
5129 }
5130
5131 static void igb_update_dca(struct igb_q_vector *q_vector)
5132 {
5133         struct igb_adapter *adapter = q_vector->adapter;
5134         int cpu = get_cpu();
5135
5136         if (q_vector->cpu == cpu)
5137                 goto out_no_update;
5138
5139         if (q_vector->tx.ring)
5140                 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu);
5141
5142         if (q_vector->rx.ring)
5143                 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu);
5144
5145         q_vector->cpu = cpu;
5146 out_no_update:
5147         put_cpu();
5148 }
5149
5150 static void igb_setup_dca(struct igb_adapter *adapter)
5151 {
5152         struct e1000_hw *hw = &adapter->hw;
5153         int i;
5154
5155         if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
5156                 return;
5157
5158         /* Always use CB2 mode, difference is masked in the CB driver. */
5159         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);
5160
5161         for (i = 0; i < adapter->num_q_vectors; i++) {
5162                 adapter->q_vector[i]->cpu = -1;
5163                 igb_update_dca(adapter->q_vector[i]);
5164         }
5165 }
5166
5167 static int __igb_notify_dca(struct device *dev, void *data)
5168 {
5169         struct net_device *netdev = dev_get_drvdata(dev);
5170         struct igb_adapter *adapter = netdev_priv(netdev);
5171         struct pci_dev *pdev = adapter->pdev;
5172         struct e1000_hw *hw = &adapter->hw;
5173         unsigned long event = *(unsigned long *)data;
5174
5175         switch (event) {
5176         case DCA_PROVIDER_ADD:
5177                 /* if already enabled, don't do it again */
5178                 if (adapter->flags & IGB_FLAG_DCA_ENABLED)
5179                         break;
5180                 if (dca_add_requester(dev) == 0) {
5181                         adapter->flags |= IGB_FLAG_DCA_ENABLED;
5182                         dev_info(&pdev->dev, "DCA enabled\n");
5183                         igb_setup_dca(adapter);
5184                         break;
5185                 }
5186                 /* Fall Through since DCA is disabled. */
5187         case DCA_PROVIDER_REMOVE:
5188                 if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
5189                         /* without this a class_device is left
5190                          * hanging around in the sysfs model */
5191                         dca_remove_requester(dev);
5192                         dev_info(&pdev->dev, "DCA disabled\n");
5193                         adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
5194                         wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
5195                 }
5196                 break;
5197         }
5198
5199         return 0;
5200 }
5201
5202 static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
5203                           void *p)
5204 {
5205         int ret_val;
5206
5207         ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
5208                                          __igb_notify_dca);
5209
5210         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
5211 }
5212 #endif /* CONFIG_IGB_DCA */
5213
5214 #ifdef CONFIG_PCI_IOV
5215 static int igb_vf_configure(struct igb_adapter *adapter, int vf)
5216 {
5217         unsigned char mac_addr[ETH_ALEN];
5218
5219         eth_zero_addr(mac_addr);
5220         igb_set_vf_mac(adapter, vf, mac_addr);
5221
5222         return 0;
5223 }
5224
5225 static bool igb_vfs_are_assigned(struct igb_adapter *adapter)
5226 {
5227         struct pci_dev *pdev = adapter->pdev;
5228         struct pci_dev *vfdev;
5229         int dev_id;
5230
5231         switch (adapter->hw.mac.type) {
5232         case e1000_82576:
5233                 dev_id = IGB_82576_VF_DEV_ID;
5234                 break;
5235         case e1000_i350:
5236                 dev_id = IGB_I350_VF_DEV_ID;
5237                 break;
5238         default:
5239                 return false;
5240         }
5241
5242         /* loop through all the VFs to see if we own any that are assigned */
5243         vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL);
5244         while (vfdev) {
5245                 /* if we don't own it we don't care */
5246                 if (vfdev->is_virtfn && vfdev->physfn == pdev) {
5247                         /* if it is assigned we cannot release it */
5248                         if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
5249                                 return true;
5250                 }
5251
5252                 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev);
5253         }
5254
5255         return false;
5256 }
5257
5258 #endif
5259 static void igb_ping_all_vfs(struct igb_adapter *adapter)
5260 {
5261         struct e1000_hw *hw = &adapter->hw;
5262         u32 ping;
5263         int i;
5264
5265         for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
5266                 ping = E1000_PF_CONTROL_MSG;
5267                 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
5268                         ping |= E1000_VT_MSGTYPE_CTS;
5269                 igb_write_mbx(hw, &ping, 1, i);
5270         }
5271 }
5272
5273 static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5274 {
5275         struct e1000_hw *hw = &adapter->hw;
5276         u32 vmolr = rd32(E1000_VMOLR(vf));
5277         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5278
5279         vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
5280                             IGB_VF_FLAG_MULTI_PROMISC);
5281         vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5282
5283         if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
5284                 vmolr |= E1000_VMOLR_MPME;
5285                 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
5286                 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
5287         } else {
5288                 /*
5289                  * if we have hashes and we are clearing a multicast promisc
5290                  * flag we need to write the hashes to the MTA as this step
5291                  * was previously skipped
5292                  */
5293                 if (vf_data->num_vf_mc_hashes > 30) {
5294                         vmolr |= E1000_VMOLR_MPME;
5295                 } else if (vf_data->num_vf_mc_hashes) {
5296                         int j;
5297                         vmolr |= E1000_VMOLR_ROMPE;
5298                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5299                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5300                 }
5301         }
5302
5303         wr32(E1000_VMOLR(vf), vmolr);
5304
5305         /* there are flags left unprocessed, likely not supported */
5306         if (*msgbuf & E1000_VT_MSGINFO_MASK)
5307                 return -EINVAL;
5308
5309         return 0;
5310
5311 }
5312
5313 static int igb_set_vf_multicasts(struct igb_adapter *adapter,
5314                                   u32 *msgbuf, u32 vf)
5315 {
5316         int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5317         u16 *hash_list = (u16 *)&msgbuf[1];
5318         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5319         int i;
5320
5321         /* salt away the number of multicast addresses assigned
5322          * to this VF for later use to restore when the PF multi cast
5323          * list changes
5324          */
5325         vf_data->num_vf_mc_hashes = n;
5326
5327         /* only up to 30 hash values supported */
5328         if (n > 30)
5329                 n = 30;
5330
5331         /* store the hashes for later use */
5332         for (i = 0; i < n; i++)
5333                 vf_data->vf_mc_hashes[i] = hash_list[i];
5334
5335         /* Flush and reset the mta with the new values */
5336         igb_set_rx_mode(adapter->netdev);
5337
5338         return 0;
5339 }
5340
5341 static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
5342 {
5343         struct e1000_hw *hw = &adapter->hw;
5344         struct vf_data_storage *vf_data;
5345         int i, j;
5346
5347         for (i = 0; i < adapter->vfs_allocated_count; i++) {
5348                 u32 vmolr = rd32(E1000_VMOLR(i));
5349                 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);
5350
5351                 vf_data = &adapter->vf_data[i];
5352
5353                 if ((vf_data->num_vf_mc_hashes > 30) ||
5354                     (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
5355                         vmolr |= E1000_VMOLR_MPME;
5356                 } else if (vf_data->num_vf_mc_hashes) {
5357                         vmolr |= E1000_VMOLR_ROMPE;
5358                         for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
5359                                 igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
5360                 }
5361                 wr32(E1000_VMOLR(i), vmolr);
5362         }
5363 }
5364
5365 static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
5366 {
5367         struct e1000_hw *hw = &adapter->hw;
5368         u32 pool_mask, reg, vid;
5369         int i;
5370
5371         pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5372
5373         /* Find the vlan filter for this id */
5374         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5375                 reg = rd32(E1000_VLVF(i));
5376
5377                 /* remove the vf from the pool */
5378                 reg &= ~pool_mask;
5379
5380                 /* if pool is empty then remove entry from vfta */
5381                 if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
5382                     (reg & E1000_VLVF_VLANID_ENABLE)) {
5383                         reg = 0;
5384                         vid = reg & E1000_VLVF_VLANID_MASK;
5385                         igb_vfta_set(hw, vid, false);
5386                 }
5387
5388                 wr32(E1000_VLVF(i), reg);
5389         }
5390
5391         adapter->vf_data[vf].vlans_enabled = 0;
5392 }
5393
5394 static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
5395 {
5396         struct e1000_hw *hw = &adapter->hw;
5397         u32 reg, i;
5398
5399         /* The vlvf table only exists on 82576 hardware and newer */
5400         if (hw->mac.type < e1000_82576)
5401                 return -1;
5402
5403         /* we only need to do this if VMDq is enabled */
5404         if (!adapter->vfs_allocated_count)
5405                 return -1;
5406
5407         /* Find the vlan filter for this id */
5408         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5409                 reg = rd32(E1000_VLVF(i));
5410                 if ((reg & E1000_VLVF_VLANID_ENABLE) &&
5411                     vid == (reg & E1000_VLVF_VLANID_MASK))
5412                         break;
5413         }
5414
5415         if (add) {
5416                 if (i == E1000_VLVF_ARRAY_SIZE) {
5417                         /* Did not find a matching VLAN ID entry that was
5418                          * enabled.  Search for a free filter entry, i.e.
5419                          * one without the enable bit set
5420                          */
5421                         for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
5422                                 reg = rd32(E1000_VLVF(i));
5423                                 if (!(reg & E1000_VLVF_VLANID_ENABLE))
5424                                         break;
5425                         }
5426                 }
5427                 if (i < E1000_VLVF_ARRAY_SIZE) {
5428                         /* Found an enabled/available entry */
5429                         reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);
5430
5431                         /* if !enabled we need to set this up in vfta */
5432                         if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5433                                 /* add VID to filter table */
5434                                 igb_vfta_set(hw, vid, true);
5435                                 reg |= E1000_VLVF_VLANID_ENABLE;
5436                         }
5437                         reg &= ~E1000_VLVF_VLANID_MASK;
5438                         reg |= vid;
5439                         wr32(E1000_VLVF(i), reg);
5440
5441                         /* do not modify RLPML for PF devices */
5442                         if (vf >= adapter->vfs_allocated_count)
5443                                 return 0;
5444
5445                         if (!adapter->vf_data[vf].vlans_enabled) {
5446                                 u32 size;
5447                                 reg = rd32(E1000_VMOLR(vf));
5448                                 size = reg & E1000_VMOLR_RLPML_MASK;
5449                                 size += 4;
5450                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5451                                 reg |= size;
5452                                 wr32(E1000_VMOLR(vf), reg);
5453                         }
5454
5455                         adapter->vf_data[vf].vlans_enabled++;
5456                 }
5457         } else {
5458                 if (i < E1000_VLVF_ARRAY_SIZE) {
5459                         /* remove vf from the pool */
5460                         reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
5461                         /* if pool is empty then remove entry from vfta */
5462                         if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
5463                                 reg = 0;
5464                                 igb_vfta_set(hw, vid, false);
5465                         }
5466                         wr32(E1000_VLVF(i), reg);
5467
5468                         /* do not modify RLPML for PF devices */
5469                         if (vf >= adapter->vfs_allocated_count)
5470                                 return 0;
5471
5472                         adapter->vf_data[vf].vlans_enabled--;
5473                         if (!adapter->vf_data[vf].vlans_enabled) {
5474                                 u32 size;
5475                                 reg = rd32(E1000_VMOLR(vf));
5476                                 size = reg & E1000_VMOLR_RLPML_MASK;
5477                                 size -= 4;
5478                                 reg &= ~E1000_VMOLR_RLPML_MASK;
5479                                 reg |= size;
5480                                 wr32(E1000_VMOLR(vf), reg);
5481                         }
5482                 }
5483         }
5484         return 0;
5485 }
5486
5487 static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
5488 {
5489         struct e1000_hw *hw = &adapter->hw;
5490
5491         if (vid)
5492                 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
5493         else
5494                 wr32(E1000_VMVIR(vf), 0);
5495 }
5496
5497 static int igb_ndo_set_vf_vlan(struct net_device *netdev,
5498                                int vf, u16 vlan, u8 qos)
5499 {
5500         int err = 0;
5501         struct igb_adapter *adapter = netdev_priv(netdev);
5502
5503         if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
5504                 return -EINVAL;
5505         if (vlan || qos) {
5506                 err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
5507                 if (err)
5508                         goto out;
5509                 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
5510                 igb_set_vmolr(adapter, vf, !vlan);
5511                 adapter->vf_data[vf].pf_vlan = vlan;
5512                 adapter->vf_data[vf].pf_qos = qos;
5513                 dev_info(&adapter->pdev->dev,
5514                          "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
5515                 if (test_bit(__IGB_DOWN, &adapter->state)) {
5516                         dev_warn(&adapter->pdev->dev,
5517                                  "The VF VLAN has been set,"
5518                                  " but the PF device is not up.\n");
5519                         dev_warn(&adapter->pdev->dev,
5520                                  "Bring the PF device up before"
5521                                  " attempting to use the VF device.\n");
5522                 }
5523         } else {
5524                 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
5525                                    false, vf);
5526                 igb_set_vmvir(adapter, vlan, vf);
5527                 igb_set_vmolr(adapter, vf, true);
5528                 adapter->vf_data[vf].pf_vlan = 0;
5529                 adapter->vf_data[vf].pf_qos = 0;
5530        }
5531 out:
5532        return err;
5533 }
5534
5535 static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
5536 {
5537         int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
5538         int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);
5539
5540         return igb_vlvf_set(adapter, vid, add, vf);
5541 }
5542
5543 static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5544 {
5545         /* clear flags - except flag that indicates PF has set the MAC */
5546         adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5547         adapter->vf_data[vf].last_nack = jiffies;
5548
5549         /* reset offloads to defaults */
5550         igb_set_vmolr(adapter, vf, true);
5551
5552         /* reset vlans for device */
5553         igb_clear_vf_vfta(adapter, vf);
5554         if (adapter->vf_data[vf].pf_vlan)
5555                 igb_ndo_set_vf_vlan(adapter->netdev, vf,
5556                                     adapter->vf_data[vf].pf_vlan,
5557                                     adapter->vf_data[vf].pf_qos);
5558         else
5559                 igb_clear_vf_vfta(adapter, vf);
5560
5561         /* reset multicast table array for vf */
5562         adapter->vf_data[vf].num_vf_mc_hashes = 0;
5563
5564         /* Flush and reset the mta with the new values */
5565         igb_set_rx_mode(adapter->netdev);
5566 }
5567
5568 static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
5569 {
5570         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5571
5572         /* clear mac address as we were hotplug removed/added */
5573         if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
5574                 eth_zero_addr(vf_mac);
5575
5576         /* process remaining reset events */
5577         igb_vf_reset(adapter, vf);
5578 }
5579
5580 static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5581 {
5582         struct e1000_hw *hw = &adapter->hw;
5583         unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5584         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5585         u32 reg, msgbuf[3];
5586         u8 *addr = (u8 *)(&msgbuf[1]);
5587
5588         /* process all the same items cleared in a function level reset */
5589         igb_vf_reset(adapter, vf);
5590
5591         /* set vf mac address */
5592         igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5593
5594         /* enable transmit and receive for vf */
5595         reg = rd32(E1000_VFTE);
5596         wr32(E1000_VFTE, reg | (1 << vf));
5597         reg = rd32(E1000_VFRE);
5598         wr32(E1000_VFRE, reg | (1 << vf));
5599
5600         adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5601
5602         /* reply to reset with ack and vf mac address */
5603         msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
5604         memcpy(addr, vf_mac, 6);
5605         igb_write_mbx(hw, msgbuf, 3, vf);
5606 }
5607
5608 static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
5609 {
5610         /*
5611          * The VF MAC Address is stored in a packed array of bytes
5612          * starting at the second 32 bit word of the msg array
5613          */
5614         unsigned char *addr = (char *)&msg[1];
5615         int err = -1;
5616
5617         if (is_valid_ether_addr(addr))
5618                 err = igb_set_vf_mac(adapter, vf, addr);
5619
5620         return err;
5621 }
5622
5623 static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
5624 {
5625         struct e1000_hw *hw = &adapter->hw;
5626         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5627         u32 msg = E1000_VT_MSGTYPE_NACK;
5628
5629         /* if device isn't clear to send it shouldn't be reading either */
5630         if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
5631             time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5632                 igb_write_mbx(hw, &msg, 1, vf);
5633                 vf_data->last_nack = jiffies;
5634         }
5635 }
5636
5637 static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5638 {
5639         struct pci_dev *pdev = adapter->pdev;
5640         u32 msgbuf[E1000_VFMAILBOX_SIZE];
5641         struct e1000_hw *hw = &adapter->hw;
5642         struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5643         s32 retval;
5644
5645         retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5646
5647         if (retval) {
5648                 /* if receive failed revoke VF CTS stats and restart init */
5649                 dev_err(&pdev->dev, "Error receiving message from VF\n");
5650                 vf_data->flags &= ~IGB_VF_FLAG_CTS;
5651                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5652                         return;
5653                 goto out;
5654         }
5655
5656         /* this is a message we already processed, do nothing */
5657         if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5658                 return;
5659
5660         /*
5661          * until the vf completes a reset it should not be
5662          * allowed to start any configuration.
5663          */
5664
5665         if (msgbuf[0] == E1000_VF_RESET) {
5666                 igb_vf_reset_msg(adapter, vf);
5667                 return;
5668         }
5669
5670         if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5671                 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
5672                         return;
5673                 retval = -1;
5674                 goto out;
5675         }
5676
5677         switch ((msgbuf[0] & 0xFFFF)) {
5678         case E1000_VF_SET_MAC_ADDR:
5679                 retval = -EINVAL;
5680                 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
5681                         retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
5682                 else
5683                         dev_warn(&pdev->dev,
5684                                  "VF %d attempted to override administratively "
5685                                  "set MAC address\nReload the VF driver to "
5686                                  "resume operations\n", vf);
5687                 break;
5688         case E1000_VF_SET_PROMISC:
5689                 retval = igb_set_vf_promisc(adapter, msgbuf, vf);
5690                 break;
5691         case E1000_VF_SET_MULTICAST:
5692                 retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
5693                 break;
5694         case E1000_VF_SET_LPE:
5695                 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
5696                 break;
5697         case E1000_VF_SET_VLAN:
5698                 retval = -1;
5699                 if (vf_data->pf_vlan)
5700                         dev_warn(&pdev->dev,
5701                                  "VF %d attempted to override administratively "
5702                                  "set VLAN tag\nReload the VF driver to "
5703                                  "resume operations\n", vf);
5704                 else
5705                         retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5706                 break;
5707         default:
5708                 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5709                 retval = -1;
5710                 break;
5711         }
5712
5713         msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
5714 out:
5715         /* notify the VF of the results of what it sent us */
5716         if (retval)
5717                 msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
5718         else
5719                 msgbuf[0] |= E1000_VT_MSGTYPE_ACK;
5720
5721         igb_write_mbx(hw, msgbuf, 1, vf);
5722 }
5723
5724 static void igb_msg_task(struct igb_adapter *adapter)
5725 {
5726         struct e1000_hw *hw = &adapter->hw;
5727         u32 vf;
5728
5729         for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
5730                 /* process any reset requests */
5731                 if (!igb_check_for_rst(hw, vf))
5732                         igb_vf_reset_event(adapter, vf);
5733
5734                 /* process any messages pending */
5735                 if (!igb_check_for_msg(hw, vf))
5736                         igb_rcv_msg_from_vf(adapter, vf);
5737
5738                 /* process any acks */
5739                 if (!igb_check_for_ack(hw, vf))
5740                         igb_rcv_ack_from_vf(adapter, vf);
5741         }
5742 }
5743
5744 /**
5745  *  igb_set_uta - Set unicast filter table address
5746  *  @adapter: board private structure
5747  *
5748  *  The unicast table address is a register array of 32-bit registers.
5749  *  The table is meant to be used in a way similar to how the MTA is used
5750  *  however due to certain limitations in the hardware it is necessary to
5751  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
5752  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5753  **/
5754 static void igb_set_uta(struct igb_adapter *adapter)
5755 {
5756         struct e1000_hw *hw = &adapter->hw;
5757         int i;
5758
5759         /* The UTA table only exists on 82576 hardware and newer */
5760         if (hw->mac.type < e1000_82576)
5761                 return;
5762
5763         /* we only need to do this if VMDq is enabled */
5764         if (!adapter->vfs_allocated_count)
5765                 return;
5766
5767         for (i = 0; i < hw->mac.uta_reg_count; i++)
5768                 array_wr32(E1000_UTA, i, ~0);
5769 }
5770
5771 /**
5772  * igb_intr_msi - Interrupt Handler
5773  * @irq: interrupt number
5774  * @data: pointer to a network interface device structure
5775  **/
5776 static irqreturn_t igb_intr_msi(int irq, void *data)
5777 {
5778         struct igb_adapter *adapter = data;
5779         struct igb_q_vector *q_vector = adapter->q_vector[0];
5780         struct e1000_hw *hw = &adapter->hw;
5781         /* read ICR disables interrupts using IAM */
5782         u32 icr = rd32(E1000_ICR);
5783
5784         igb_write_itr(q_vector);
5785
5786         if (icr & E1000_ICR_DRSTA)
5787                 schedule_work(&adapter->reset_task);
5788
5789         if (icr & E1000_ICR_DOUTSYNC) {
5790                 /* HW is reporting DMA is out of sync */
5791                 adapter->stats.doosync++;
5792         }
5793
5794         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5795                 hw->mac.get_link_status = 1;
5796                 if (!test_bit(__IGB_DOWN, &adapter->state))
5797                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5798         }
5799
5800         if (icr & E1000_ICR_TS) {
5801                 u32 tsicr = rd32(E1000_TSICR);
5802
5803                 if (tsicr & E1000_TSICR_TXTS) {
5804                         /* acknowledge the interrupt */
5805                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5806                         /* retrieve hardware timestamp */
5807                         schedule_work(&adapter->ptp_tx_work);
5808                 }
5809         }
5810
5811         napi_schedule(&q_vector->napi);
5812
5813         return IRQ_HANDLED;
5814 }
5815
5816 /**
5817  * igb_intr - Legacy Interrupt Handler
5818  * @irq: interrupt number
5819  * @data: pointer to a network interface device structure
5820  **/
5821 static irqreturn_t igb_intr(int irq, void *data)
5822 {
5823         struct igb_adapter *adapter = data;
5824         struct igb_q_vector *q_vector = adapter->q_vector[0];
5825         struct e1000_hw *hw = &adapter->hw;
5826         /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
5827          * need for the IMC write */
5828         u32 icr = rd32(E1000_ICR);
5829
5830         /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
5831          * not set, then the adapter didn't send an interrupt */
5832         if (!(icr & E1000_ICR_INT_ASSERTED))
5833                 return IRQ_NONE;
5834
5835         igb_write_itr(q_vector);
5836
5837         if (icr & E1000_ICR_DRSTA)
5838                 schedule_work(&adapter->reset_task);
5839
5840         if (icr & E1000_ICR_DOUTSYNC) {
5841                 /* HW is reporting DMA is out of sync */
5842                 adapter->stats.doosync++;
5843         }
5844
5845         if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
5846                 hw->mac.get_link_status = 1;
5847                 /* guard against interrupt when we're going down */
5848                 if (!test_bit(__IGB_DOWN, &adapter->state))
5849                         mod_timer(&adapter->watchdog_timer, jiffies + 1);
5850         }
5851
5852         if (icr & E1000_ICR_TS) {
5853                 u32 tsicr = rd32(E1000_TSICR);
5854
5855                 if (tsicr & E1000_TSICR_TXTS) {
5856                         /* acknowledge the interrupt */
5857                         wr32(E1000_TSICR, E1000_TSICR_TXTS);
5858                         /* retrieve hardware timestamp */
5859                         schedule_work(&adapter->ptp_tx_work);
5860                 }
5861         }
5862
5863         napi_schedule(&q_vector->napi);
5864
5865         return IRQ_HANDLED;
5866 }
5867
5868 static void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5869 {
5870         struct igb_adapter *adapter = q_vector->adapter;
5871         struct e1000_hw *hw = &adapter->hw;
5872
5873         if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
5874             (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
5875                 if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
5876                         igb_set_itr(q_vector);
5877                 else
5878                         igb_update_ring_itr(q_vector);
5879         }
5880
5881         if (!test_bit(__IGB_DOWN, &adapter->state)) {
5882                 if (adapter->msix_entries)
5883                         wr32(E1000_EIMS, q_vector->eims_value);
5884                 else
5885                         igb_irq_enable(adapter);
5886         }
5887 }
5888
5889 /**
5890  * igb_poll - NAPI Rx polling callback
5891  * @napi: napi polling structure
5892  * @budget: count of how many packets we should handle
5893  **/
5894 static int igb_poll(struct napi_struct *napi, int budget)
5895 {
5896         struct igb_q_vector *q_vector = container_of(napi,
5897                                                      struct igb_q_vector,
5898                                                      napi);
5899         bool clean_complete = true;
5900
5901 #ifdef CONFIG_IGB_DCA
5902         if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
5903                 igb_update_dca(q_vector);
5904 #endif
5905         if (q_vector->tx.ring)
5906                 clean_complete = igb_clean_tx_irq(q_vector);
5907
5908         if (q_vector->rx.ring)
5909                 clean_complete &= igb_clean_rx_irq(q_vector, budget);
5910
5911         /* If all work not completed, return budget and keep polling */
5912         if (!clean_complete)
5913                 return budget;
5914
5915         /* If not enough Rx work done, exit the polling mode */
5916         napi_complete(napi);
5917         igb_ring_irq_enable(q_vector);
5918
5919         return 0;
5920 }
5921
5922 /**
5923  * igb_clean_tx_irq - Reclaim resources after transmit completes
5924  * @q_vector: pointer to q_vector containing needed info
5925  *
5926  * returns true if ring is completely cleaned
5927  **/
5928 static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5929 {
5930         struct igb_adapter *adapter = q_vector->adapter;
5931         struct igb_ring *tx_ring = q_vector->tx.ring;
5932         struct igb_tx_buffer *tx_buffer;
5933         union e1000_adv_tx_desc *tx_desc;
5934         unsigned int total_bytes = 0, total_packets = 0;
5935         unsigned int budget = q_vector->tx.work_limit;
5936         unsigned int i = tx_ring->next_to_clean;
5937
5938         if (test_bit(__IGB_DOWN, &adapter->state))
5939                 return true;
5940
5941         tx_buffer = &tx_ring->tx_buffer_info[i];
5942         tx_desc = IGB_TX_DESC(tx_ring, i);
5943         i -= tx_ring->count;
5944
5945         do {
5946                 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
5947
5948                 /* if next_to_watch is not set then there is no work pending */
5949                 if (!eop_desc)
5950                         break;
5951
5952                 /* prevent any other reads prior to eop_desc */
5953                 read_barrier_depends();
5954
5955                 /* if DD is not set pending work has not been completed */
5956                 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
5957                         break;
5958
5959                 /* clear next_to_watch to prevent false hangs */
5960                 tx_buffer->next_to_watch = NULL;
5961
5962                 /* update the statistics for this packet */
5963                 total_bytes += tx_buffer->bytecount;
5964                 total_packets += tx_buffer->gso_segs;
5965
5966                 /* free the skb */
5967                 dev_kfree_skb_any(tx_buffer->skb);
5968
5969                 /* unmap skb header data */
5970                 dma_unmap_single(tx_ring->dev,
5971                                  dma_unmap_addr(tx_buffer, dma),
5972                                  dma_unmap_len(tx_buffer, len),
5973                                  DMA_TO_DEVICE);
5974
5975                 /* clear tx_buffer data */
5976                 tx_buffer->skb = NULL;
5977                 dma_unmap_len_set(tx_buffer, len, 0);
5978
5979                 /* clear last DMA location and unmap remaining buffers */
5980                 while (tx_desc != eop_desc) {
5981                         tx_buffer++;
5982                         tx_desc++;
5983                         i++;
5984                         if (unlikely(!i)) {
5985                                 i -= tx_ring->count;
5986                                 tx_buffer = tx_ring->tx_buffer_info;
5987                                 tx_desc = IGB_TX_DESC(tx_ring, 0);
5988                         }
5989
5990                         /* unmap any remaining paged data */
5991                         if (dma_unmap_len(tx_buffer, len)) {
5992                                 dma_unmap_page(tx_ring->dev,
5993                                                dma_unmap_addr(tx_buffer, dma),
5994                                                dma_unmap_len(tx_buffer, len),
5995                                                DMA_TO_DEVICE);
5996                                 dma_unmap_len_set(tx_buffer, len, 0);
5997                         }
5998                 }
5999
6000                 /* move us one more past the eop_desc for start of next pkt */
6001                 tx_buffer++;
6002                 tx_desc++;
6003                 i++;
6004                 if (unlikely(!i)) {
6005                         i -= tx_ring->count;
6006                         tx_buffer = tx_ring->tx_buffer_info;
6007                         tx_desc = IGB_TX_DESC(tx_ring, 0);
6008                 }
6009
6010                 /* issue prefetch for next Tx descriptor */
6011                 prefetch(tx_desc);
6012
6013                 /* update budget accounting */
6014                 budget--;
6015         } while (likely(budget));
6016
6017         netdev_tx_completed_queue(txring_txq(tx_ring),
6018                                   total_packets, total_bytes);
6019         i += tx_ring->count;
6020         tx_ring->next_to_clean = i;
6021         u64_stats_update_begin(&tx_ring->tx_syncp);
6022         tx_ring->tx_stats.bytes += total_bytes;
6023         tx_ring->tx_stats.packets += total_packets;
6024         u64_stats_update_end(&tx_ring->tx_syncp);
6025         q_vector->tx.total_bytes += total_bytes;
6026         q_vector->tx.total_packets += total_packets;
6027
6028         if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
6029                 struct e1000_hw *hw = &adapter->hw;
6030
6031                 /* Detect a transmit hang in hardware, this serializes the
6032                  * check with the clearing of time_stamp and movement of i */
6033                 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
6034                 if (tx_buffer->next_to_watch &&
6035                     time_after(jiffies, tx_buffer->time_stamp +
6036                                (adapter->tx_timeout_factor * HZ)) &&
6037                     !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
6038
6039                         /* detected Tx unit hang */
6040                         dev_err(tx_ring->dev,
6041                                 "Detected Tx Unit Hang\n"
6042                                 "  Tx Queue             <%d>\n"
6043                                 "  TDH                  <%x>\n"
6044                                 "  TDT                  <%x>\n"
6045                                 "  next_to_use          <%x>\n"
6046                                 "  next_to_clean        <%x>\n"
6047                                 "buffer_info[next_to_clean]\n"
6048                                 "  time_stamp           <%lx>\n"
6049                                 "  next_to_watch        <%p>\n"
6050                                 "  jiffies              <%lx>\n"
6051                                 "  desc.status          <%x>\n",
6052                                 tx_ring->queue_index,
6053                                 rd32(E1000_TDH(tx_ring->reg_idx)),
6054                                 readl(tx_ring->tail),
6055                                 tx_ring->next_to_use,
6056                                 tx_ring->next_to_clean,
6057                                 tx_buffer->time_stamp,
6058                                 tx_buffer->next_to_watch,
6059                                 jiffies,
6060                                 tx_buffer->next_to_watch->wb.status);
6061                         netif_stop_subqueue(tx_ring->netdev,
6062                                             tx_ring->queue_index);
6063
6064                         /* we are about to reset, no point in enabling stuff */
6065                         return true;
6066                 }
6067         }
6068
6069 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6070         if (unlikely(total_packets &&
6071                      netif_carrier_ok(tx_ring->netdev) &&
6072                      igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) {
6073                 /* Make sure that anybody stopping the queue after this
6074                  * sees the new next_to_clean.
6075                  */
6076                 smp_mb();
6077                 if (__netif_subqueue_stopped(tx_ring->netdev,
6078                                              tx_ring->queue_index) &&
6079                     !(test_bit(__IGB_DOWN, &adapter->state))) {
6080                         netif_wake_subqueue(tx_ring->netdev,
6081                                             tx_ring->queue_index);
6082
6083                         u64_stats_update_begin(&tx_ring->tx_syncp);
6084                         tx_ring->tx_stats.restart_queue++;
6085                         u64_stats_update_end(&tx_ring->tx_syncp);
6086                 }
6087         }
6088
6089         return !!budget;
6090 }
6091
6092 /**
6093  * igb_reuse_rx_page - page flip buffer and store it back on the ring
6094  * @rx_ring: rx descriptor ring to store buffers on
6095  * @old_buff: donor buffer to have page reused
6096  *
6097  * Synchronizes page for reuse by the adapter
6098  **/
6099 static void igb_reuse_rx_page(struct igb_ring *rx_ring,
6100                               struct igb_rx_buffer *old_buff)
6101 {
6102         struct igb_rx_buffer *new_buff;
6103         u16 nta = rx_ring->next_to_alloc;
6104
6105         new_buff = &rx_ring->rx_buffer_info[nta];
6106
6107         /* update, and store next to alloc */
6108         nta++;
6109         rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
6110
6111         /* transfer page from old buffer to new buffer */
6112         memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer));
6113
6114         /* sync the buffer for use by the device */
6115         dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma,
6116                                          old_buff->page_offset,
6117                                          IGB_RX_BUFSZ,
6118                                          DMA_FROM_DEVICE);
6119 }
6120
6121 static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer,
6122                                   struct page *page,
6123                                   unsigned int truesize)
6124 {
6125         /* avoid re-using remote pages */
6126         if (unlikely(page_to_nid(page) != numa_node_id()))
6127                 return false;
6128
6129 #if (PAGE_SIZE < 8192)
6130         /* if we are only owner of page we can reuse it */
6131         if (unlikely(page_count(page) != 1))
6132                 return false;
6133
6134         /* flip page offset to other buffer */
6135         rx_buffer->page_offset ^= IGB_RX_BUFSZ;
6136
6137         /* since we are the only owner of the page and we need to
6138          * increment it, just set the value to 2 in order to avoid
6139          * an unnecessary locked operation
6140          */
6141         atomic_set(&page->_count, 2);
6142 #else
6143         /* move offset up to the next cache line */
6144         rx_buffer->page_offset += truesize;
6145
6146         if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ))
6147                 return false;
6148
6149         /* bump ref count on page before it is given to the stack */
6150         get_page(page);
6151 #endif
6152
6153         return true;
6154 }
6155
6156 /**
6157  * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6158  * @rx_ring: rx descriptor ring to transact packets on
6159  * @rx_buffer: buffer containing page to add
6160  * @rx_desc: descriptor containing length of buffer written by hardware
6161  * @skb: sk_buff to place the data into
6162  *
6163  * This function will add the data contained in rx_buffer->page to the skb.
6164  * This is done either through a direct copy if the data in the buffer is
6165  * less than the skb header size, otherwise it will just attach the page as
6166  * a frag to the skb.
6167  *
6168  * The function will then update the page offset if necessary and return
6169  * true if the buffer can be reused by the adapter.
6170  **/
6171 static bool igb_add_rx_frag(struct igb_ring *rx_ring,
6172                             struct igb_rx_buffer *rx_buffer,
6173                             union e1000_adv_rx_desc *rx_desc,
6174                             struct sk_buff *skb)
6175 {
6176         struct page *page = rx_buffer->page;
6177         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6178 #if (PAGE_SIZE < 8192)
6179         unsigned int truesize = IGB_RX_BUFSZ;
6180 #else
6181         unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
6182 #endif
6183
6184         if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) {
6185                 unsigned char *va = page_address(page) + rx_buffer->page_offset;
6186
6187                 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6188                         igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6189                         va += IGB_TS_HDR_LEN;
6190                         size -= IGB_TS_HDR_LEN;
6191                 }
6192
6193                 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
6194
6195                 /* we can reuse buffer as-is, just make sure it is local */
6196                 if (likely(page_to_nid(page) == numa_node_id()))
6197                         return true;
6198
6199                 /* this page cannot be reused so discard it */
6200                 put_page(page);
6201                 return false;
6202         }
6203
6204         skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
6205                         rx_buffer->page_offset, size, truesize);
6206
6207         return igb_can_reuse_rx_page(rx_buffer, page, truesize);
6208 }
6209
6210 static struct sk_buff *igb_build_rx_buffer(struct igb_ring *rx_ring,
6211                                            union e1000_adv_rx_desc *rx_desc)
6212 {
6213         struct igb_rx_buffer *rx_buffer;
6214         struct sk_buff *skb;
6215         struct page *page;
6216         void *page_addr;
6217         unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
6218 #if (PAGE_SIZE < 8192)
6219         unsigned int truesize = IGB_RX_BUFSZ;
6220 #else
6221         unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
6222                                 SKB_DATA_ALIGN(NET_SKB_PAD +
6223                                                NET_IP_ALIGN +
6224                                                size);
6225 #endif
6226
6227         /* If we spanned a buffer we have a huge mess so test for it */
6228         BUG_ON(unlikely(!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)));
6229
6230         /* Guarantee this function can be used by verifying buffer sizes */
6231         BUILD_BUG_ON(SKB_WITH_OVERHEAD(IGB_RX_BUFSZ) < (NET_SKB_PAD +
6232                                                         NET_IP_ALIGN +
6233                                                         IGB_TS_HDR_LEN +
6234                                                         ETH_FRAME_LEN +
6235                                                         ETH_FCS_LEN));
6236
6237         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6238         page = rx_buffer->page;
6239         prefetchw(page);
6240
6241         page_addr = page_address(page) + rx_buffer->page_offset;
6242
6243         /* prefetch first cache line of first page */
6244         prefetch(page_addr + NET_SKB_PAD + NET_IP_ALIGN);
6245 #if L1_CACHE_BYTES < 128
6246         prefetch(page_addr + L1_CACHE_BYTES + NET_SKB_PAD + NET_IP_ALIGN);
6247 #endif
6248
6249         /* build an skb to around the page buffer */
6250         skb = build_skb(page_addr, truesize);
6251         if (unlikely(!skb)) {
6252                 rx_ring->rx_stats.alloc_failed++;
6253                 return NULL;
6254         }
6255
6256         /* we are reusing so sync this buffer for CPU use */
6257         dma_sync_single_range_for_cpu(rx_ring->dev,
6258                                       rx_buffer->dma,
6259                                       rx_buffer->page_offset,
6260                                       IGB_RX_BUFSZ,
6261                                       DMA_FROM_DEVICE);
6262
6263         /* update pointers within the skb to store the data */
6264         skb_reserve(skb, NET_IP_ALIGN + NET_SKB_PAD);
6265         __skb_put(skb, size);
6266
6267         /* pull timestamp out of packet data */
6268         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6269                 igb_ptp_rx_pktstamp(rx_ring->q_vector, skb->data, skb);
6270                 __skb_pull(skb, IGB_TS_HDR_LEN);
6271         }
6272
6273         if (igb_can_reuse_rx_page(rx_buffer, page, truesize)) {
6274                 /* hand second half of page back to the ring */
6275                 igb_reuse_rx_page(rx_ring, rx_buffer);
6276         } else {
6277                 /* we are not reusing the buffer so unmap it */
6278                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6279                                PAGE_SIZE, DMA_FROM_DEVICE);
6280         }
6281
6282         /* clear contents of buffer_info */
6283         rx_buffer->dma = 0;
6284         rx_buffer->page = NULL;
6285
6286         return skb;
6287 }
6288
6289 static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring,
6290                                            union e1000_adv_rx_desc *rx_desc,
6291                                            struct sk_buff *skb)
6292 {
6293         struct igb_rx_buffer *rx_buffer;
6294         struct page *page;
6295
6296         rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
6297
6298         page = rx_buffer->page;
6299         prefetchw(page);
6300
6301         if (likely(!skb)) {
6302                 void *page_addr = page_address(page) +
6303                                   rx_buffer->page_offset;
6304
6305                 /* prefetch first cache line of first page */
6306                 prefetch(page_addr);
6307 #if L1_CACHE_BYTES < 128
6308                 prefetch(page_addr + L1_CACHE_BYTES);
6309 #endif
6310
6311                 /* allocate a skb to store the frags */
6312                 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
6313                                                 IGB_RX_HDR_LEN);
6314                 if (unlikely(!skb)) {
6315                         rx_ring->rx_stats.alloc_failed++;
6316                         return NULL;
6317                 }
6318
6319                 /*
6320                  * we will be copying header into skb->data in
6321                  * pskb_may_pull so it is in our interest to prefetch
6322                  * it now to avoid a possible cache miss
6323                  */
6324                 prefetchw(skb->data);
6325         }
6326
6327         /* we are reusing so sync this buffer for CPU use */
6328         dma_sync_single_range_for_cpu(rx_ring->dev,
6329                                       rx_buffer->dma,
6330                                       rx_buffer->page_offset,
6331                                       IGB_RX_BUFSZ,
6332                                       DMA_FROM_DEVICE);
6333
6334         /* pull page into skb */
6335         if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
6336                 /* hand second half of page back to the ring */
6337                 igb_reuse_rx_page(rx_ring, rx_buffer);
6338         } else {
6339                 /* we are not reusing the buffer so unmap it */
6340                 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
6341                                PAGE_SIZE, DMA_FROM_DEVICE);
6342         }
6343
6344         /* clear contents of rx_buffer */
6345         rx_buffer->page = NULL;
6346
6347         return skb;
6348 }
6349
6350 static inline void igb_rx_checksum(struct igb_ring *ring,
6351                                    union e1000_adv_rx_desc *rx_desc,
6352                                    struct sk_buff *skb)
6353 {
6354         skb_checksum_none_assert(skb);
6355
6356         /* Ignore Checksum bit is set */
6357         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
6358                 return;
6359
6360         /* Rx checksum disabled via ethtool */
6361         if (!(ring->netdev->features & NETIF_F_RXCSUM))
6362                 return;
6363
6364         /* TCP/UDP checksum error bit is set */
6365         if (igb_test_staterr(rx_desc,
6366                              E1000_RXDEXT_STATERR_TCPE |
6367                              E1000_RXDEXT_STATERR_IPE)) {
6368                 /*
6369                  * work around errata with sctp packets where the TCPE aka
6370                  * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6371                  * packets, (aka let the stack check the crc32c)
6372                  */
6373                 if (!((skb->len == 60) &&
6374                       test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
6375                         u64_stats_update_begin(&ring->rx_syncp);
6376                         ring->rx_stats.csum_err++;
6377                         u64_stats_update_end(&ring->rx_syncp);
6378                 }
6379                 /* let the stack verify checksum errors */
6380                 return;
6381         }
6382         /* It must be a TCP or UDP packet with a valid checksum */
6383         if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
6384                                       E1000_RXD_STAT_UDPCS))
6385                 skb->ip_summed = CHECKSUM_UNNECESSARY;
6386
6387         dev_dbg(ring->dev, "cksum success: bits %08X\n",
6388                 le32_to_cpu(rx_desc->wb.upper.status_error));
6389 }
6390
6391 static inline void igb_rx_hash(struct igb_ring *ring,
6392                                union e1000_adv_rx_desc *rx_desc,
6393                                struct sk_buff *skb)
6394 {
6395         if (ring->netdev->features & NETIF_F_RXHASH)
6396                 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
6397 }
6398
6399 /**
6400  * igb_is_non_eop - process handling of non-EOP buffers
6401  * @rx_ring: Rx ring being processed
6402  * @rx_desc: Rx descriptor for current buffer
6403  * @skb: current socket buffer containing buffer in progress
6404  *
6405  * This function updates next to clean.  If the buffer is an EOP buffer
6406  * this function exits returning false, otherwise it will place the
6407  * sk_buff in the next buffer to be chained and return true indicating
6408  * that this is in fact a non-EOP buffer.
6409  **/
6410 static bool igb_is_non_eop(struct igb_ring *rx_ring,
6411                            union e1000_adv_rx_desc *rx_desc)
6412 {
6413         u32 ntc = rx_ring->next_to_clean + 1;
6414
6415         /* fetch, update, and store next to clean */
6416         ntc = (ntc < rx_ring->count) ? ntc : 0;
6417         rx_ring->next_to_clean = ntc;
6418
6419         prefetch(IGB_RX_DESC(rx_ring, ntc));
6420
6421         if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)))
6422                 return false;
6423
6424         return true;
6425 }
6426
6427 /**
6428  * igb_get_headlen - determine size of header for LRO/GRO
6429  * @data: pointer to the start of the headers
6430  * @max_len: total length of section to find headers in
6431  *
6432  * This function is meant to determine the length of headers that will
6433  * be recognized by hardware for LRO, and GRO offloads.  The main
6434  * motivation of doing this is to only perform one pull for IPv4 TCP
6435  * packets so that we can do basic things like calculating the gso_size
6436  * based on the average data per packet.
6437  **/
6438 static unsigned int igb_get_headlen(unsigned char *data,
6439                                     unsigned int max_len)
6440 {
6441         union {
6442                 unsigned char *network;
6443                 /* l2 headers */
6444                 struct ethhdr *eth;
6445                 struct vlan_hdr *vlan;
6446                 /* l3 headers */
6447                 struct iphdr *ipv4;
6448                 struct ipv6hdr *ipv6;
6449         } hdr;
6450         __be16 protocol;
6451         u8 nexthdr = 0; /* default to not TCP */
6452         u8 hlen;
6453
6454         /* this should never happen, but better safe than sorry */
6455         if (max_len < ETH_HLEN)
6456                 return max_len;
6457
6458         /* initialize network frame pointer */
6459         hdr.network = data;
6460
6461         /* set first protocol and move network header forward */
6462         protocol = hdr.eth->h_proto;
6463         hdr.network += ETH_HLEN;
6464
6465         /* handle any vlan tag if present */
6466         if (protocol == __constant_htons(ETH_P_8021Q)) {
6467                 if ((hdr.network - data) > (max_len - VLAN_HLEN))
6468                         return max_len;
6469
6470                 protocol = hdr.vlan->h_vlan_encapsulated_proto;
6471                 hdr.network += VLAN_HLEN;
6472         }
6473
6474         /* handle L3 protocols */
6475         if (protocol == __constant_htons(ETH_P_IP)) {
6476                 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
6477                         return max_len;
6478
6479                 /* access ihl as a u8 to avoid unaligned access on ia64 */
6480                 hlen = (hdr.network[0] & 0x0F) << 2;
6481
6482                 /* verify hlen meets minimum size requirements */
6483                 if (hlen < sizeof(struct iphdr))
6484                         return hdr.network - data;
6485
6486                 /* record next protocol if header is present */
6487                 if (!hdr.ipv4->frag_off)
6488                         nexthdr = hdr.ipv4->protocol;
6489         } else if (protocol == __constant_htons(ETH_P_IPV6)) {
6490                 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
6491                         return max_len;
6492
6493                 /* record next protocol */
6494                 nexthdr = hdr.ipv6->nexthdr;
6495                 hlen = sizeof(struct ipv6hdr);
6496         } else {
6497                 return hdr.network - data;
6498         }
6499
6500         /* relocate pointer to start of L4 header */
6501         hdr.network += hlen;
6502
6503         /* finally sort out TCP */
6504         if (nexthdr == IPPROTO_TCP) {
6505                 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
6506                         return max_len;
6507
6508                 /* access doff as a u8 to avoid unaligned access on ia64 */
6509                 hlen = (hdr.network[12] & 0xF0) >> 2;
6510
6511                 /* verify hlen meets minimum size requirements */
6512                 if (hlen < sizeof(struct tcphdr))
6513                         return hdr.network - data;
6514
6515                 hdr.network += hlen;
6516         } else if (nexthdr == IPPROTO_UDP) {
6517                 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
6518                         return max_len;
6519
6520                 hdr.network += sizeof(struct udphdr);
6521         }
6522
6523         /*
6524          * If everything has gone correctly hdr.network should be the
6525          * data section of the packet and will be the end of the header.
6526          * If not then it probably represents the end of the last recognized
6527          * header.
6528          */
6529         if ((hdr.network - data) < max_len)
6530                 return hdr.network - data;
6531         else
6532                 return max_len;
6533 }
6534
6535 /**
6536  * igb_pull_tail - igb specific version of skb_pull_tail
6537  * @rx_ring: rx descriptor ring packet is being transacted on
6538  * @rx_desc: pointer to the EOP Rx descriptor
6539  * @skb: pointer to current skb being adjusted
6540  *
6541  * This function is an igb specific version of __pskb_pull_tail.  The
6542  * main difference between this version and the original function is that
6543  * this function can make several assumptions about the state of things
6544  * that allow for significant optimizations versus the standard function.
6545  * As a result we can do things like drop a frag and maintain an accurate
6546  * truesize for the skb.
6547  */
6548 static void igb_pull_tail(struct igb_ring *rx_ring,
6549                           union e1000_adv_rx_desc *rx_desc,
6550                           struct sk_buff *skb)
6551 {
6552         struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
6553         unsigned char *va;
6554         unsigned int pull_len;
6555
6556         /*
6557          * it is valid to use page_address instead of kmap since we are
6558          * working with pages allocated out of the lomem pool per
6559          * alloc_page(GFP_ATOMIC)
6560          */
6561         va = skb_frag_address(frag);
6562
6563         if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
6564                 /* retrieve timestamp from buffer */
6565                 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb);
6566
6567                 /* update pointers to remove timestamp header */
6568                 skb_frag_size_sub(frag, IGB_TS_HDR_LEN);
6569                 frag->page_offset += IGB_TS_HDR_LEN;
6570                 skb->data_len -= IGB_TS_HDR_LEN;
6571                 skb->len -= IGB_TS_HDR_LEN;
6572
6573                 /* move va to start of packet data */
6574                 va += IGB_TS_HDR_LEN;
6575         }
6576
6577         /*
6578          * we need the header to contain the greater of either ETH_HLEN or
6579          * 60 bytes if the skb->len is less than 60 for skb_pad.
6580          */
6581         pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
6582
6583         /* align pull length to size of long to optimize memcpy performance */
6584         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
6585
6586         /* update all of the pointers */
6587         skb_frag_size_sub(frag, pull_len);
6588         frag->page_offset += pull_len;
6589         skb->data_len -= pull_len;
6590         skb->tail += pull_len;
6591 }
6592
6593 /**
6594  * igb_cleanup_headers - Correct corrupted or empty headers
6595  * @rx_ring: rx descriptor ring packet is being transacted on
6596  * @rx_desc: pointer to the EOP Rx descriptor
6597  * @skb: pointer to current skb being fixed
6598  *
6599  * Address the case where we are pulling data in on pages only
6600  * and as such no data is present in the skb header.
6601  *
6602  * In addition if skb is not at least 60 bytes we need to pad it so that
6603  * it is large enough to qualify as a valid Ethernet frame.
6604  *
6605  * Returns true if an error was encountered and skb was freed.
6606  **/
6607 static bool igb_cleanup_headers(struct igb_ring *rx_ring,
6608                                 union e1000_adv_rx_desc *rx_desc,
6609                                 struct sk_buff *skb)
6610 {
6611
6612         if (unlikely((igb_test_staterr(rx_desc,
6613                                        E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6614                 struct net_device *netdev = rx_ring->netdev;
6615                 if (!(netdev->features & NETIF_F_RXALL)) {
6616                         dev_kfree_skb_any(skb);
6617                         return true;
6618                 }
6619         }
6620
6621         /* place header in linear portion of buffer */
6622         if (skb_is_nonlinear(skb))
6623                 igb_pull_tail(rx_ring, rx_desc, skb);
6624
6625         /* if skb_pad returns an error the skb was freed */
6626         if (unlikely(skb->len < 60)) {
6627                 int pad_len = 60 - skb->len;
6628
6629                 if (skb_pad(skb, pad_len))
6630                         return true;
6631                 __skb_put(skb, pad_len);
6632         }
6633
6634         return false;
6635 }
6636
6637 /**
6638  * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6639  * @rx_ring: rx descriptor ring packet is being transacted on
6640  * @rx_desc: pointer to the EOP Rx descriptor
6641  * @skb: pointer to current skb being populated
6642  *
6643  * This function checks the ring, descriptor, and packet information in
6644  * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6645  * other fields within the skb.
6646  **/
6647 static void igb_process_skb_fields(struct igb_ring *rx_ring,
6648                                    union e1000_adv_rx_desc *rx_desc,
6649                                    struct sk_buff *skb)
6650 {
6651         struct net_device *dev = rx_ring->netdev;
6652
6653         igb_rx_hash(rx_ring, rx_desc, skb);
6654
6655         igb_rx_checksum(rx_ring, rx_desc, skb);
6656
6657         igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
6658
6659         if ((dev->features & NETIF_F_HW_VLAN_RX) &&
6660             igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
6661                 u16 vid;
6662                 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) &&
6663                     test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
6664                         vid = be16_to_cpu(rx_desc->wb.upper.vlan);
6665                 else
6666                         vid = le16_to_cpu(rx_desc->wb.upper.vlan);
6667
6668                 __vlan_hwaccel_put_tag(skb, vid);
6669         }
6670
6671         skb_record_rx_queue(skb, rx_ring->queue_index);
6672
6673         skb->protocol = eth_type_trans(skb, rx_ring->netdev);
6674 }
6675
6676 static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget)
6677 {
6678         struct igb_ring *rx_ring = q_vector->rx.ring;
6679         struct sk_buff *skb = rx_ring->skb;
6680         unsigned int total_bytes = 0, total_packets = 0;
6681         u16 cleaned_count = igb_desc_unused(rx_ring);
6682
6683         do {
6684                 union e1000_adv_rx_desc *rx_desc;
6685
6686                 /* return some buffers to hardware, one at a time is too slow */
6687                 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
6688                         igb_alloc_rx_buffers(rx_ring, cleaned_count);
6689                         cleaned_count = 0;
6690                 }
6691
6692                 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean);
6693
6694                 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD))
6695                         break;
6696
6697                 /* This memory barrier is needed to keep us from reading
6698                  * any other fields out of the rx_desc until we know the
6699                  * RXD_STAT_DD bit is set
6700                  */
6701                 rmb();
6702
6703                 /* retrieve a buffer from the ring */
6704                 if (ring_uses_build_skb(rx_ring))
6705                         skb = igb_build_rx_buffer(rx_ring, rx_desc);
6706                 else
6707                         skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb);
6708
6709                 /* exit if we failed to retrieve a buffer */
6710                 if (!skb)
6711                         break;
6712
6713                 cleaned_count++;
6714
6715                 /* fetch next buffer in frame if non-eop */
6716                 if (igb_is_non_eop(rx_ring, rx_desc))
6717                         continue;
6718
6719                 /* verify the packet layout is correct */
6720                 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) {
6721                         skb = NULL;
6722                         continue;
6723                 }
6724
6725                 /* probably a little skewed due to removing CRC */
6726                 total_bytes += skb->len;
6727
6728                 /* populate checksum, timestamp, VLAN, and protocol */
6729                 igb_process_skb_fields(rx_ring, rx_desc, skb);
6730
6731                 napi_gro_receive(&q_vector->napi, skb);
6732
6733                 /* reset skb pointer */
6734                 skb = NULL;
6735
6736                 /* update budget accounting */
6737                 total_packets++;
6738         } while (likely(total_packets < budget));
6739
6740         /* place incomplete frames back on ring for completion */
6741         rx_ring->skb = skb;
6742
6743         u64_stats_update_begin(&rx_ring->rx_syncp);
6744         rx_ring->rx_stats.packets += total_packets;
6745         rx_ring->rx_stats.bytes += total_bytes;
6746         u64_stats_update_end(&rx_ring->rx_syncp);
6747         q_vector->rx.total_packets += total_packets;
6748         q_vector->rx.total_bytes += total_bytes;
6749
6750         if (cleaned_count)
6751                 igb_alloc_rx_buffers(rx_ring, cleaned_count);
6752
6753         return (total_packets < budget);
6754 }
6755
6756 static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6757                                   struct igb_rx_buffer *bi)
6758 {
6759         struct page *page = bi->page;
6760         dma_addr_t dma;
6761
6762         /* since we are recycling buffers we should seldom need to alloc */
6763         if (likely(page))
6764                 return true;
6765
6766         /* alloc new page for storage */
6767         page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL);
6768         if (unlikely(!page)) {
6769                 rx_ring->rx_stats.alloc_failed++;
6770                 return false;
6771         }
6772
6773         /* map page for use */
6774         dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
6775
6776         /*
6777          * if mapping failed free memory back to system since
6778          * there isn't much point in holding memory we can't use
6779          */
6780         if (dma_mapping_error(rx_ring->dev, dma)) {
6781                 __free_page(page);
6782
6783                 rx_ring->rx_stats.alloc_failed++;
6784                 return false;
6785         }
6786
6787         bi->dma = dma;
6788         bi->page = page;
6789         bi->page_offset = 0;
6790
6791         return true;
6792 }
6793
6794 static inline unsigned int igb_rx_offset(struct igb_ring *rx_ring)
6795 {
6796         if (ring_uses_build_skb(rx_ring))
6797                 return NET_SKB_PAD + NET_IP_ALIGN;
6798         else
6799                 return 0;
6800 }
6801
6802 /**
6803  * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6804  * @adapter: address of board private structure
6805  **/
6806 void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6807 {
6808         union e1000_adv_rx_desc *rx_desc;
6809         struct igb_rx_buffer *bi;
6810         u16 i = rx_ring->next_to_use;
6811
6812         /* nothing to do */
6813         if (!cleaned_count)
6814                 return;
6815
6816         rx_desc = IGB_RX_DESC(rx_ring, i);
6817         bi = &rx_ring->rx_buffer_info[i];
6818         i -= rx_ring->count;
6819
6820         do {
6821                 if (!igb_alloc_mapped_page(rx_ring, bi))
6822                         break;
6823
6824                 /*
6825                  * Refresh the desc even if buffer_addrs didn't change
6826                  * because each write-back erases this info.
6827                  */
6828                 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma +
6829                                                      bi->page_offset +
6830                                                      igb_rx_offset(rx_ring));
6831
6832                 rx_desc++;
6833                 bi++;
6834                 i++;
6835                 if (unlikely(!i)) {
6836                         rx_desc = IGB_RX_DESC(rx_ring, 0);
6837                         bi = rx_ring->rx_buffer_info;
6838                         i -= rx_ring->count;
6839                 }
6840
6841                 /* clear the hdr_addr for the next_to_use descriptor */
6842                 rx_desc->read.hdr_addr = 0;
6843
6844                 cleaned_count--;
6845         } while (cleaned_count);
6846
6847         i += rx_ring->count;
6848
6849         if (rx_ring->next_to_use != i) {
6850                 /* record the next descriptor to use */
6851                 rx_ring->next_to_use = i;
6852
6853                 /* update next to alloc since we have filled the ring */
6854                 rx_ring->next_to_alloc = i;
6855
6856                 /*
6857                  * Force memory writes to complete before letting h/w
6858                  * know there are new descriptors to fetch.  (Only
6859                  * applicable for weak-ordered memory model archs,
6860                  * such as IA-64).
6861                  */
6862                 wmb();
6863                 writel(i, rx_ring->tail);
6864         }
6865 }
6866
6867 /**
6868  * igb_mii_ioctl -
6869  * @netdev:
6870  * @ifreq:
6871  * @cmd:
6872  **/
6873 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6874 {
6875         struct igb_adapter *adapter = netdev_priv(netdev);
6876         struct mii_ioctl_data *data = if_mii(ifr);
6877
6878         if (adapter->hw.phy.media_type != e1000_media_type_copper)
6879                 return -EOPNOTSUPP;
6880
6881         switch (cmd) {
6882         case SIOCGMIIPHY:
6883                 data->phy_id = adapter->hw.phy.addr;
6884                 break;
6885         case SIOCGMIIREG:
6886                 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
6887                                      &data->val_out))
6888                         return -EIO;
6889                 break;
6890         case SIOCSMIIREG:
6891         default:
6892                 return -EOPNOTSUPP;
6893         }
6894         return 0;
6895 }
6896
6897 /**
6898  * igb_ioctl -
6899  * @netdev:
6900  * @ifreq:
6901  * @cmd:
6902  **/
6903 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6904 {
6905         switch (cmd) {
6906         case SIOCGMIIPHY:
6907         case SIOCGMIIREG:
6908         case SIOCSMIIREG:
6909                 return igb_mii_ioctl(netdev, ifr, cmd);
6910         case SIOCSHWTSTAMP:
6911                 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd);
6912         default:
6913                 return -EOPNOTSUPP;
6914         }
6915 }
6916
6917 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6918 {
6919         struct igb_adapter *adapter = hw->back;
6920
6921         if (pcie_capability_read_word(adapter->pdev, reg, value))
6922                 return -E1000_ERR_CONFIG;
6923
6924         return 0;
6925 }
6926
6927 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
6928 {
6929         struct igb_adapter *adapter = hw->back;
6930
6931         if (pcie_capability_write_word(adapter->pdev, reg, *value))
6932                 return -E1000_ERR_CONFIG;
6933
6934         return 0;
6935 }
6936
6937 static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features)
6938 {
6939         struct igb_adapter *adapter = netdev_priv(netdev);
6940         struct e1000_hw *hw = &adapter->hw;
6941         u32 ctrl, rctl;
6942         bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6943
6944         if (enable) {
6945                 /* enable VLAN tag insert/strip */
6946                 ctrl = rd32(E1000_CTRL);
6947                 ctrl |= E1000_CTRL_VME;
6948                 wr32(E1000_CTRL, ctrl);
6949
6950                 /* Disable CFI check */
6951                 rctl = rd32(E1000_RCTL);
6952                 rctl &= ~E1000_RCTL_CFIEN;
6953                 wr32(E1000_RCTL, rctl);
6954         } else {
6955                 /* disable VLAN tag insert/strip */
6956                 ctrl = rd32(E1000_CTRL);
6957                 ctrl &= ~E1000_CTRL_VME;
6958                 wr32(E1000_CTRL, ctrl);
6959         }
6960
6961         igb_rlpml_set(adapter);
6962 }
6963
6964 static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
6965 {
6966         struct igb_adapter *adapter = netdev_priv(netdev);
6967         struct e1000_hw *hw = &adapter->hw;
6968         int pf_id = adapter->vfs_allocated_count;
6969
6970         /* attempt to add filter to vlvf array */
6971         igb_vlvf_set(adapter, vid, true, pf_id);
6972
6973         /* add the filter since PF can receive vlans w/o entry in vlvf */
6974         igb_vfta_set(hw, vid, true);
6975
6976         set_bit(vid, adapter->active_vlans);
6977
6978         return 0;
6979 }
6980
6981 static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
6982 {
6983         struct igb_adapter *adapter = netdev_priv(netdev);
6984         struct e1000_hw *hw = &adapter->hw;
6985         int pf_id = adapter->vfs_allocated_count;
6986         s32 err;
6987
6988         /* remove vlan from VLVF table array */
6989         err = igb_vlvf_set(adapter, vid, false, pf_id);
6990
6991         /* if vid was not present in VLVF just remove it from table */
6992         if (err)
6993                 igb_vfta_set(hw, vid, false);
6994
6995         clear_bit(vid, adapter->active_vlans);
6996
6997         return 0;
6998 }
6999
7000 static void igb_restore_vlan(struct igb_adapter *adapter)
7001 {
7002         u16 vid;
7003
7004         igb_vlan_mode(adapter->netdev, adapter->netdev->features);
7005
7006         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
7007                 igb_vlan_rx_add_vid(adapter->netdev, vid);
7008 }
7009
7010 int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
7011 {
7012         struct pci_dev *pdev = adapter->pdev;
7013         struct e1000_mac_info *mac = &adapter->hw.mac;
7014
7015         mac->autoneg = 0;
7016
7017         /* Make sure dplx is at most 1 bit and lsb of speed is not set
7018          * for the switch() below to work */
7019         if ((spd & 1) || (dplx & ~1))
7020                 goto err_inval;
7021
7022         /* Fiber NIC's only allow 1000 Gbps Full duplex */
7023         if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
7024             spd != SPEED_1000 &&
7025             dplx != DUPLEX_FULL)
7026                 goto err_inval;
7027
7028         switch (spd + dplx) {
7029         case SPEED_10 + DUPLEX_HALF:
7030                 mac->forced_speed_duplex = ADVERTISE_10_HALF;
7031                 break;
7032         case SPEED_10 + DUPLEX_FULL:
7033                 mac->forced_speed_duplex = ADVERTISE_10_FULL;
7034                 break;
7035         case SPEED_100 + DUPLEX_HALF:
7036                 mac->forced_speed_duplex = ADVERTISE_100_HALF;
7037                 break;
7038         case SPEED_100 + DUPLEX_FULL:
7039                 mac->forced_speed_duplex = ADVERTISE_100_FULL;
7040                 break;
7041         case SPEED_1000 + DUPLEX_FULL:
7042                 mac->autoneg = 1;
7043                 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
7044                 break;
7045         case SPEED_1000 + DUPLEX_HALF: /* not supported */
7046         default:
7047                 goto err_inval;
7048         }
7049
7050         /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7051         adapter->hw.phy.mdix = AUTO_ALL_MODES;
7052
7053         return 0;
7054
7055 err_inval:
7056         dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
7057         return -EINVAL;
7058 }
7059
7060 static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake,
7061                           bool runtime)
7062 {
7063         struct net_device *netdev = pci_get_drvdata(pdev);
7064         struct igb_adapter *adapter = netdev_priv(netdev);
7065         struct e1000_hw *hw = &adapter->hw;
7066         u32 ctrl, rctl, status;
7067         u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
7068 #ifdef CONFIG_PM
7069         int retval = 0;
7070 #endif
7071
7072         netif_device_detach(netdev);
7073
7074         if (netif_running(netdev))
7075                 __igb_close(netdev, true);
7076
7077         igb_clear_interrupt_scheme(adapter);
7078
7079 #ifdef CONFIG_PM
7080         retval = pci_save_state(pdev);
7081         if (retval)
7082                 return retval;
7083 #endif
7084
7085         status = rd32(E1000_STATUS);
7086         if (status & E1000_STATUS_LU)
7087                 wufc &= ~E1000_WUFC_LNKC;
7088
7089         if (wufc) {
7090                 igb_setup_rctl(adapter);
7091                 igb_set_rx_mode(netdev);
7092
7093                 /* turn on all-multi mode if wake on multicast is enabled */
7094                 if (wufc & E1000_WUFC_MC) {
7095                         rctl = rd32(E1000_RCTL);
7096                         rctl |= E1000_RCTL_MPE;
7097                         wr32(E1000_RCTL, rctl);
7098                 }
7099
7100                 ctrl = rd32(E1000_CTRL);
7101                 /* advertise wake from D3Cold */
7102                 #define E1000_CTRL_ADVD3WUC 0x00100000
7103                 /* phy power management enable */
7104                 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7105                 ctrl |= E1000_CTRL_ADVD3WUC;
7106                 wr32(E1000_CTRL, ctrl);
7107
7108                 /* Allow time for pending master requests to run */
7109                 igb_disable_pcie_master(hw);
7110
7111                 wr32(E1000_WUC, E1000_WUC_PME_EN);
7112                 wr32(E1000_WUFC, wufc);
7113         } else {
7114                 wr32(E1000_WUC, 0);
7115                 wr32(E1000_WUFC, 0);
7116         }
7117
7118         *enable_wake = wufc || adapter->en_mng_pt;
7119         if (!*enable_wake)
7120                 igb_power_down_link(adapter);
7121         else
7122                 igb_power_up_link(adapter);
7123
7124         /* Release control of h/w to f/w.  If f/w is AMT enabled, this
7125          * would have already happened in close and is redundant. */
7126         igb_release_hw_control(adapter);
7127
7128         pci_disable_device(pdev);
7129
7130         return 0;
7131 }
7132
7133 #ifdef CONFIG_PM
7134 #ifdef CONFIG_PM_SLEEP
7135 static int igb_suspend(struct device *dev)
7136 {
7137         int retval;
7138         bool wake;
7139         struct pci_dev *pdev = to_pci_dev(dev);
7140
7141         retval = __igb_shutdown(pdev, &wake, 0);
7142         if (retval)
7143                 return retval;
7144
7145         if (wake) {
7146                 pci_prepare_to_sleep(pdev);
7147         } else {
7148                 pci_wake_from_d3(pdev, false);
7149                 pci_set_power_state(pdev, PCI_D3hot);
7150         }
7151
7152         return 0;
7153 }
7154 #endif /* CONFIG_PM_SLEEP */
7155
7156 static int igb_resume(struct device *dev)
7157 {
7158         struct pci_dev *pdev = to_pci_dev(dev);
7159         struct net_device *netdev = pci_get_drvdata(pdev);
7160         struct igb_adapter *adapter = netdev_priv(netdev);
7161         struct e1000_hw *hw = &adapter->hw;
7162         u32 err;
7163
7164         pci_set_power_state(pdev, PCI_D0);
7165         pci_restore_state(pdev);
7166         pci_save_state(pdev);
7167
7168         err = pci_enable_device_mem(pdev);
7169         if (err) {
7170                 dev_err(&pdev->dev,
7171                         "igb: Cannot enable PCI device from suspend\n");
7172                 return err;
7173         }
7174         pci_set_master(pdev);
7175
7176         pci_enable_wake(pdev, PCI_D3hot, 0);
7177         pci_enable_wake(pdev, PCI_D3cold, 0);
7178
7179         if (igb_init_interrupt_scheme(adapter, true)) {
7180                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7181                 return -ENOMEM;
7182         }
7183
7184         igb_reset(adapter);
7185
7186         /* let the f/w know that the h/w is now under the control of the
7187          * driver. */
7188         igb_get_hw_control(adapter);
7189
7190         wr32(E1000_WUS, ~0);
7191
7192         if (netdev->flags & IFF_UP) {
7193                 rtnl_lock();
7194                 err = __igb_open(netdev, true);
7195                 rtnl_unlock();
7196                 if (err)
7197                         return err;
7198         }
7199
7200         netif_device_attach(netdev);
7201         return 0;
7202 }
7203
7204 #ifdef CONFIG_PM_RUNTIME
7205 static int igb_runtime_idle(struct device *dev)
7206 {
7207         struct pci_dev *pdev = to_pci_dev(dev);
7208         struct net_device *netdev = pci_get_drvdata(pdev);
7209         struct igb_adapter *adapter = netdev_priv(netdev);
7210
7211         if (!igb_has_link(adapter))
7212                 pm_schedule_suspend(dev, MSEC_PER_SEC * 5);
7213
7214         return -EBUSY;
7215 }
7216
7217 static int igb_runtime_suspend(struct device *dev)
7218 {
7219         struct pci_dev *pdev = to_pci_dev(dev);
7220         int retval;
7221         bool wake;
7222
7223         retval = __igb_shutdown(pdev, &wake, 1);
7224         if (retval)
7225                 return retval;
7226
7227         if (wake) {
7228                 pci_prepare_to_sleep(pdev);
7229         } else {
7230                 pci_wake_from_d3(pdev, false);
7231                 pci_set_power_state(pdev, PCI_D3hot);
7232         }
7233
7234         return 0;
7235 }
7236
7237 static int igb_runtime_resume(struct device *dev)
7238 {
7239         return igb_resume(dev);
7240 }
7241 #endif /* CONFIG_PM_RUNTIME */
7242 #endif
7243
7244 static void igb_shutdown(struct pci_dev *pdev)
7245 {
7246         bool wake;
7247
7248         __igb_shutdown(pdev, &wake, 0);
7249
7250         if (system_state == SYSTEM_POWER_OFF) {
7251                 pci_wake_from_d3(pdev, wake);
7252                 pci_set_power_state(pdev, PCI_D3hot);
7253         }
7254 }
7255
7256 #ifdef CONFIG_PCI_IOV
7257 static int igb_sriov_reinit(struct pci_dev *dev)
7258 {
7259         struct net_device *netdev = pci_get_drvdata(dev);
7260         struct igb_adapter *adapter = netdev_priv(netdev);
7261         struct pci_dev *pdev = adapter->pdev;
7262
7263         rtnl_lock();
7264
7265         if (netif_running(netdev))
7266                 igb_close(netdev);
7267
7268         igb_clear_interrupt_scheme(adapter);
7269
7270         igb_init_queue_configuration(adapter);
7271
7272         if (igb_init_interrupt_scheme(adapter, true)) {
7273                 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
7274                 return -ENOMEM;
7275         }
7276
7277         if (netif_running(netdev))
7278                 igb_open(netdev);
7279
7280         rtnl_unlock();
7281
7282         return 0;
7283 }
7284
7285 static int igb_pci_disable_sriov(struct pci_dev *dev)
7286 {
7287         int err = igb_disable_sriov(dev);
7288
7289         if (!err)
7290                 err = igb_sriov_reinit(dev);
7291
7292         return err;
7293 }
7294
7295 static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs)
7296 {
7297         int err = igb_enable_sriov(dev, num_vfs);
7298
7299         if (err)
7300                 goto out;
7301
7302         err = igb_sriov_reinit(dev);
7303         if (!err)
7304                 return num_vfs;
7305
7306 out:
7307         return err;
7308 }
7309
7310 #endif
7311 static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs)
7312 {
7313 #ifdef CONFIG_PCI_IOV
7314         if (num_vfs == 0)
7315                 return igb_pci_disable_sriov(dev);
7316         else
7317                 return igb_pci_enable_sriov(dev, num_vfs);
7318 #endif
7319         return 0;
7320 }
7321
7322 #ifdef CONFIG_NET_POLL_CONTROLLER
7323 /*
7324  * Polling 'interrupt' - used by things like netconsole to send skbs
7325  * without having to re-enable interrupts. It's not called while
7326  * the interrupt routine is executing.
7327  */
7328 static void igb_netpoll(struct net_device *netdev)
7329 {
7330         struct igb_adapter *adapter = netdev_priv(netdev);
7331         struct e1000_hw *hw = &adapter->hw;
7332         struct igb_q_vector *q_vector;
7333         int i;
7334
7335         for (i = 0; i < adapter->num_q_vectors; i++) {
7336                 q_vector = adapter->q_vector[i];
7337                 if (adapter->msix_entries)
7338                         wr32(E1000_EIMC, q_vector->eims_value);
7339                 else
7340                         igb_irq_disable(adapter);
7341                 napi_schedule(&q_vector->napi);
7342         }
7343 }
7344 #endif /* CONFIG_NET_POLL_CONTROLLER */
7345
7346 /**
7347  * igb_io_error_detected - called when PCI error is detected
7348  * @pdev: Pointer to PCI device
7349  * @state: The current pci connection state
7350  *
7351  * This function is called after a PCI bus error affecting
7352  * this device has been detected.
7353  */
7354 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
7355                                               pci_channel_state_t state)
7356 {
7357         struct net_device *netdev = pci_get_drvdata(pdev);
7358         struct igb_adapter *adapter = netdev_priv(netdev);
7359
7360         netif_device_detach(netdev);
7361
7362         if (state == pci_channel_io_perm_failure)
7363                 return PCI_ERS_RESULT_DISCONNECT;
7364
7365         if (netif_running(netdev))
7366                 igb_down(adapter);
7367         pci_disable_device(pdev);
7368
7369         /* Request a slot slot reset. */
7370         return PCI_ERS_RESULT_NEED_RESET;
7371 }
7372
7373 /**
7374  * igb_io_slot_reset - called after the pci bus has been reset.
7375  * @pdev: Pointer to PCI device
7376  *
7377  * Restart the card from scratch, as if from a cold-boot. Implementation
7378  * resembles the first-half of the igb_resume routine.
7379  */
7380 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
7381 {
7382         struct net_device *netdev = pci_get_drvdata(pdev);
7383         struct igb_adapter *adapter = netdev_priv(netdev);
7384         struct e1000_hw *hw = &adapter->hw;
7385         pci_ers_result_t result;
7386         int err;
7387
7388         if (pci_enable_device_mem(pdev)) {
7389                 dev_err(&pdev->dev,
7390                         "Cannot re-enable PCI device after reset.\n");
7391                 result = PCI_ERS_RESULT_DISCONNECT;
7392         } else {
7393                 pci_set_master(pdev);
7394                 pci_restore_state(pdev);
7395                 pci_save_state(pdev);
7396
7397                 pci_enable_wake(pdev, PCI_D3hot, 0);
7398                 pci_enable_wake(pdev, PCI_D3cold, 0);
7399
7400                 igb_reset(adapter);
7401                 wr32(E1000_WUS, ~0);
7402                 result = PCI_ERS_RESULT_RECOVERED;
7403         }
7404
7405         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7406         if (err) {
7407                 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
7408                         "failed 0x%0x\n", err);
7409                 /* non-fatal, continue */
7410         }
7411
7412         return result;
7413 }
7414
7415 /**
7416  * igb_io_resume - called when traffic can start flowing again.
7417  * @pdev: Pointer to PCI device
7418  *
7419  * This callback is called when the error recovery driver tells us that
7420  * its OK to resume normal operation. Implementation resembles the
7421  * second-half of the igb_resume routine.
7422  */
7423 static void igb_io_resume(struct pci_dev *pdev)
7424 {
7425         struct net_device *netdev = pci_get_drvdata(pdev);
7426         struct igb_adapter *adapter = netdev_priv(netdev);
7427
7428         if (netif_running(netdev)) {
7429                 if (igb_up(adapter)) {
7430                         dev_err(&pdev->dev, "igb_up failed after reset\n");
7431                         return;
7432                 }
7433         }
7434
7435         netif_device_attach(netdev);
7436
7437         /* let the f/w know that the h/w is now under the control of the
7438          * driver. */
7439         igb_get_hw_control(adapter);
7440 }
7441
7442 static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
7443                              u8 qsel)
7444 {
7445         u32 rar_low, rar_high;
7446         struct e1000_hw *hw = &adapter->hw;
7447
7448         /* HW expects these in little endian so we reverse the byte order
7449          * from network order (big endian) to little endian
7450          */
7451         rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
7452                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
7453         rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
7454
7455         /* Indicate to hardware the Address is Valid. */
7456         rar_high |= E1000_RAH_AV;
7457
7458         if (hw->mac.type == e1000_82575)
7459                 rar_high |= E1000_RAH_POOL_1 * qsel;
7460         else
7461                 rar_high |= E1000_RAH_POOL_1 << qsel;
7462
7463         wr32(E1000_RAL(index), rar_low);
7464         wrfl();
7465         wr32(E1000_RAH(index), rar_high);
7466         wrfl();
7467 }
7468
7469 static int igb_set_vf_mac(struct igb_adapter *adapter,
7470                           int vf, unsigned char *mac_addr)
7471 {
7472         struct e1000_hw *hw = &adapter->hw;
7473         /* VF MAC addresses start at end of receive addresses and moves
7474          * torwards the first, as a result a collision should not be possible */
7475         int rar_entry = hw->mac.rar_entry_count - (vf + 1);
7476
7477         memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
7478
7479         igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
7480
7481         return 0;
7482 }
7483
7484 static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
7485 {
7486         struct igb_adapter *adapter = netdev_priv(netdev);
7487         if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
7488                 return -EINVAL;
7489         adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
7490         dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
7491         dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
7492                                       " change effective.");
7493         if (test_bit(__IGB_DOWN, &adapter->state)) {
7494                 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
7495                          " but the PF device is not up.\n");
7496                 dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
7497                          " attempting to use the VF device.\n");
7498         }
7499         return igb_set_vf_mac(adapter, vf, mac);
7500 }
7501
7502 static int igb_link_mbps(int internal_link_speed)
7503 {
7504         switch (internal_link_speed) {
7505         case SPEED_100:
7506                 return 100;
7507         case SPEED_1000:
7508                 return 1000;
7509         default:
7510                 return 0;
7511         }
7512 }
7513
7514 static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
7515                                   int link_speed)
7516 {
7517         int rf_dec, rf_int;
7518         u32 bcnrc_val;
7519
7520         if (tx_rate != 0) {
7521                 /* Calculate the rate factor values to set */
7522                 rf_int = link_speed / tx_rate;
7523                 rf_dec = (link_speed - (rf_int * tx_rate));
7524                 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;
7525
7526                 bcnrc_val = E1000_RTTBCNRC_RS_ENA;
7527                 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
7528                                E1000_RTTBCNRC_RF_INT_MASK);
7529                 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
7530         } else {
7531                 bcnrc_val = 0;
7532         }
7533
7534         wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
7535         /*
7536          * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7537          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7538          */
7539         wr32(E1000_RTTBCNRM, 0x14);
7540         wr32(E1000_RTTBCNRC, bcnrc_val);
7541 }
7542
7543 static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
7544 {
7545         int actual_link_speed, i;
7546         bool reset_rate = false;
7547
7548         /* VF TX rate limit was not set or not supported */
7549         if ((adapter->vf_rate_link_speed == 0) ||
7550             (adapter->hw.mac.type != e1000_82576))
7551                 return;
7552
7553         actual_link_speed = igb_link_mbps(adapter->link_speed);
7554         if (actual_link_speed != adapter->vf_rate_link_speed) {
7555                 reset_rate = true;
7556                 adapter->vf_rate_link_speed = 0;
7557                 dev_info(&adapter->pdev->dev,
7558                          "Link speed has been changed. VF Transmit "
7559                          "rate is disabled\n");
7560         }
7561
7562         for (i = 0; i < adapter->vfs_allocated_count; i++) {
7563                 if (reset_rate)
7564                         adapter->vf_data[i].tx_rate = 0;
7565
7566                 igb_set_vf_rate_limit(&adapter->hw, i,
7567                                       adapter->vf_data[i].tx_rate,
7568                                       actual_link_speed);
7569         }
7570 }
7571
7572 static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
7573 {
7574         struct igb_adapter *adapter = netdev_priv(netdev);
7575         struct e1000_hw *hw = &adapter->hw;
7576         int actual_link_speed;
7577
7578         if (hw->mac.type != e1000_82576)
7579                 return -EOPNOTSUPP;
7580
7581         actual_link_speed = igb_link_mbps(adapter->link_speed);
7582         if ((vf >= adapter->vfs_allocated_count) ||
7583             (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
7584             (tx_rate < 0) || (tx_rate > actual_link_speed))
7585                 return -EINVAL;
7586
7587         adapter->vf_rate_link_speed = actual_link_speed;
7588         adapter->vf_data[vf].tx_rate = (u16)tx_rate;
7589         igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);
7590
7591         return 0;
7592 }
7593
7594 static int igb_ndo_get_vf_config(struct net_device *netdev,
7595                                  int vf, struct ifla_vf_info *ivi)
7596 {
7597         struct igb_adapter *adapter = netdev_priv(netdev);
7598         if (vf >= adapter->vfs_allocated_count)
7599                 return -EINVAL;
7600         ivi->vf = vf;
7601         memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
7602         ivi->tx_rate = adapter->vf_data[vf].tx_rate;
7603         ivi->vlan = adapter->vf_data[vf].pf_vlan;
7604         ivi->qos = adapter->vf_data[vf].pf_qos;
7605         return 0;
7606 }
7607
7608 static void igb_vmm_control(struct igb_adapter *adapter)
7609 {
7610         struct e1000_hw *hw = &adapter->hw;
7611         u32 reg;
7612
7613         switch (hw->mac.type) {
7614         case e1000_82575:
7615         case e1000_i210:
7616         case e1000_i211:
7617         default:
7618                 /* replication is not supported for 82575 */
7619                 return;
7620         case e1000_82576:
7621                 /* notify HW that the MAC is adding vlan tags */
7622                 reg = rd32(E1000_DTXCTL);
7623                 reg |= E1000_DTXCTL_VLAN_ADDED;
7624                 wr32(E1000_DTXCTL, reg);
7625         case e1000_82580:
7626                 /* enable replication vlan tag stripping */
7627                 reg = rd32(E1000_RPLOLR);
7628                 reg |= E1000_RPLOLR_STRVLAN;
7629                 wr32(E1000_RPLOLR, reg);
7630         case e1000_i350:
7631                 /* none of the above registers are supported by i350 */
7632                 break;
7633         }
7634
7635         if (adapter->vfs_allocated_count) {
7636                 igb_vmdq_set_loopback_pf(hw, true);
7637                 igb_vmdq_set_replication_pf(hw, true);
7638                 igb_vmdq_set_anti_spoofing_pf(hw, true,
7639                                                 adapter->vfs_allocated_count);
7640         } else {
7641                 igb_vmdq_set_loopback_pf(hw, false);
7642                 igb_vmdq_set_replication_pf(hw, false);
7643         }
7644 }
7645
7646 static void igb_init_dmac(struct igb_adapter *adapter, u32 pba)
7647 {
7648         struct e1000_hw *hw = &adapter->hw;
7649         u32 dmac_thr;
7650         u16 hwm;
7651
7652         if (hw->mac.type > e1000_82580) {
7653                 if (adapter->flags & IGB_FLAG_DMAC) {
7654                         u32 reg;
7655
7656                         /* force threshold to 0. */
7657                         wr32(E1000_DMCTXTH, 0);
7658
7659                         /*
7660                          * DMA Coalescing high water mark needs to be greater
7661                          * than the Rx threshold. Set hwm to PBA - max frame
7662                          * size in 16B units, capping it at PBA - 6KB.
7663                          */
7664                         hwm = 64 * pba - adapter->max_frame_size / 16;
7665                         if (hwm < 64 * (pba - 6))
7666                                 hwm = 64 * (pba - 6);
7667                         reg = rd32(E1000_FCRTC);
7668                         reg &= ~E1000_FCRTC_RTH_COAL_MASK;
7669                         reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT)
7670                                 & E1000_FCRTC_RTH_COAL_MASK);
7671                         wr32(E1000_FCRTC, reg);
7672
7673                         /*
7674                          * Set the DMA Coalescing Rx threshold to PBA - 2 * max
7675                          * frame size, capping it at PBA - 10KB.
7676                          */
7677                         dmac_thr = pba - adapter->max_frame_size / 512;
7678                         if (dmac_thr < pba - 10)
7679                                 dmac_thr = pba - 10;
7680                         reg = rd32(E1000_DMACR);
7681                         reg &= ~E1000_DMACR_DMACTHR_MASK;
7682                         reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT)
7683                                 & E1000_DMACR_DMACTHR_MASK);
7684
7685                         /* transition to L0x or L1 if available..*/
7686                         reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
7687
7688                         /* watchdog timer= +-1000 usec in 32usec intervals */
7689                         reg |= (1000 >> 5);
7690
7691                         /* Disable BMC-to-OS Watchdog Enable */
7692                         reg &= ~E1000_DMACR_DC_BMC2OSW_EN;
7693                         wr32(E1000_DMACR, reg);
7694
7695                         /*
7696                          * no lower threshold to disable
7697                          * coalescing(smart fifb)-UTRESH=0
7698                          */
7699                         wr32(E1000_DMCRTRH, 0);
7700
7701                         reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4);
7702
7703                         wr32(E1000_DMCTLX, reg);
7704
7705                         /*
7706                          * free space in tx packet buffer to wake from
7707                          * DMA coal
7708                          */
7709                         wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE -
7710                              (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6);
7711
7712                         /*
7713                          * make low power state decision controlled
7714                          * by DMA coal
7715                          */
7716                         reg = rd32(E1000_PCIEMISC);
7717                         reg &= ~E1000_PCIEMISC_LX_DECISION;
7718                         wr32(E1000_PCIEMISC, reg);
7719                 } /* endif adapter->dmac is not disabled */
7720         } else if (hw->mac.type == e1000_82580) {
7721                 u32 reg = rd32(E1000_PCIEMISC);
7722                 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION);
7723                 wr32(E1000_DMACR, 0);
7724         }
7725 }
7726
7727 static DEFINE_SPINLOCK(i2c_clients_lock);
7728
7729 /*  igb_get_i2c_client - returns matching client
7730  *  in adapters's client list.
7731  *  @adapter: adapter struct
7732  *  @dev_addr: device address of i2c needed.
7733  */
7734 static struct i2c_client *
7735 igb_get_i2c_client(struct igb_adapter *adapter, u8 dev_addr)
7736 {
7737         ulong flags;
7738         struct igb_i2c_client_list *client_list;
7739         struct i2c_client *client = NULL;
7740         struct i2c_board_info client_info = {
7741                 I2C_BOARD_INFO("igb", 0x00),
7742         };
7743
7744         spin_lock_irqsave(&i2c_clients_lock, flags);
7745         client_list = adapter->i2c_clients;
7746
7747         /* See if we already have an i2c_client */
7748         while (client_list) {
7749                 if (client_list->client->addr == (dev_addr >> 1)) {
7750                         client = client_list->client;
7751                         goto exit;
7752                 } else {
7753                         client_list = client_list->next;
7754                 }
7755         }
7756
7757         /* no client_list found, create a new one */
7758         client_list = kzalloc(sizeof(*client_list), GFP_ATOMIC);
7759         if (client_list == NULL)
7760                 goto exit;
7761
7762         /* dev_addr passed to us is left-shifted by 1 bit
7763          * i2c_new_device call expects it to be flush to the right.
7764          */
7765         client_info.addr = dev_addr >> 1;
7766         client_info.platform_data = adapter;
7767         client_list->client = i2c_new_device(&adapter->i2c_adap, &client_info);
7768         if (client_list->client == NULL) {
7769                 dev_info(&adapter->pdev->dev,
7770                         "Failed to create new i2c device..\n");
7771                 goto err_no_client;
7772         }
7773
7774         /* insert new client at head of list */
7775         client_list->next = adapter->i2c_clients;
7776         adapter->i2c_clients = client_list;
7777
7778         client = client_list->client;
7779         goto exit;
7780
7781 err_no_client:
7782         kfree(client_list);
7783 exit:
7784         spin_unlock_irqrestore(&i2c_clients_lock, flags);
7785         return client;
7786 }
7787
7788 /*  igb_read_i2c_byte - Reads 8 bit word over I2C
7789  *  @hw: pointer to hardware structure
7790  *  @byte_offset: byte offset to read
7791  *  @dev_addr: device address
7792  *  @data: value read
7793  *
7794  *  Performs byte read operation over I2C interface at
7795  *  a specified device address.
7796  */
7797 s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7798                                 u8 dev_addr, u8 *data)
7799 {
7800         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7801         struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7802         s32 status;
7803         u16 swfw_mask = 0;
7804
7805         if (!this_client)
7806                 return E1000_ERR_I2C;
7807
7808         swfw_mask = E1000_SWFW_PHY0_SM;
7809
7810         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
7811             != E1000_SUCCESS)
7812                 return E1000_ERR_SWFW_SYNC;
7813
7814         status = i2c_smbus_read_byte_data(this_client, byte_offset);
7815         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7816
7817         if (status < 0)
7818                 return E1000_ERR_I2C;
7819         else {
7820                 *data = status;
7821                 return E1000_SUCCESS;
7822         }
7823 }
7824
7825 /*  igb_write_i2c_byte - Writes 8 bit word over I2C
7826  *  @hw: pointer to hardware structure
7827  *  @byte_offset: byte offset to write
7828  *  @dev_addr: device address
7829  *  @data: value to write
7830  *
7831  *  Performs byte write operation over I2C interface at
7832  *  a specified device address.
7833  */
7834 s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset,
7835                                  u8 dev_addr, u8 data)
7836 {
7837         struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw);
7838         struct i2c_client *this_client = igb_get_i2c_client(adapter, dev_addr);
7839         s32 status;
7840         u16 swfw_mask = E1000_SWFW_PHY0_SM;
7841
7842         if (!this_client)
7843                 return E1000_ERR_I2C;
7844
7845         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS)
7846                 return E1000_ERR_SWFW_SYNC;
7847         status = i2c_smbus_write_byte_data(this_client, byte_offset, data);
7848         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
7849
7850         if (status)
7851                 return E1000_ERR_I2C;
7852         else
7853                 return E1000_SUCCESS;
7854
7855 }
7856 /* igb_main.c */