1 /*******************************************************************************
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
29 /* Linux PRO/1000 Ethernet Driver main header file */
34 #include "e1000_mac.h"
35 #include "e1000_82575.h"
37 #include <linux/clocksource.h>
38 #include <linux/timecompare.h>
39 #include <linux/net_tstamp.h>
40 #include <linux/bitops.h>
41 #include <linux/if_vlan.h>
45 /* ((1000000000ns / (6000ints/s * 1024ns)) << 2 = 648 */
46 #define IGB_START_ITR 648
48 /* TX/RX descriptor defines */
49 #define IGB_DEFAULT_TXD 256
50 #define IGB_DEFAULT_TX_WORK 128
51 #define IGB_MIN_TXD 80
52 #define IGB_MAX_TXD 4096
54 #define IGB_DEFAULT_RXD 256
55 #define IGB_MIN_RXD 80
56 #define IGB_MAX_RXD 4096
58 #define IGB_DEFAULT_ITR 3 /* dynamic */
59 #define IGB_MAX_ITR_USECS 10000
60 #define IGB_MIN_ITR_USECS 10
61 #define NON_Q_VECTORS 1
62 #define MAX_Q_VECTORS 8
64 /* Transmit and receive queues */
65 #define IGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \
66 (hw->mac.type > e1000_82575 ? 8 : 4))
67 #define IGB_MAX_TX_QUEUES 16
69 #define IGB_MAX_VF_MC_ENTRIES 30
70 #define IGB_MAX_VF_FUNCTIONS 8
71 #define IGB_MAX_VFTA_ENTRIES 128
73 struct vf_data_storage {
74 unsigned char vf_mac_addresses[ETH_ALEN];
75 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
79 unsigned long last_nack;
80 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
85 #define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
86 #define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
87 #define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
88 #define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
90 /* RX descriptor control thresholds.
91 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
92 * descriptors available in its onboard memory.
93 * Setting this to 0 disables RX descriptor prefetch.
94 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
95 * available in host memory.
96 * If PTHRESH is 0, this should also be 0.
97 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
98 * descriptors until either it has this many to write back, or the
101 #define IGB_RX_PTHRESH 8
102 #define IGB_RX_HTHRESH 8
103 #define IGB_TX_PTHRESH 8
104 #define IGB_TX_HTHRESH 1
105 #define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
106 adapter->msix_entries) ? 1 : 4)
107 #define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
108 adapter->msix_entries) ? 1 : 16)
110 /* this is the size past which hardware will drop packets when setting LPE=0 */
111 #define MAXIMUM_ETHERNET_VLAN_SIZE 1522
113 /* Supported Rx Buffer Sizes */
114 #define IGB_RXBUFFER_512 512
115 #define IGB_RXBUFFER_16384 16384
116 #define IGB_RX_HDR_LEN IGB_RXBUFFER_512
118 /* How many Tx Descriptors do we need to call netif_wake_queue ? */
119 #define IGB_TX_QUEUE_WAKE 16
120 /* How many Rx Buffers do we bundle into one write to the hardware ? */
121 #define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
123 #define AUTO_ALL_MODES 0
124 #define IGB_EEPROM_APME 0x0400
126 #ifndef IGB_MASTER_SLAVE
127 /* Switch to override PHY master/slave setting */
128 #define IGB_MASTER_SLAVE e1000_ms_hw_default
131 #define IGB_MNG_VLAN_NONE -1
133 #define IGB_TX_FLAGS_CSUM 0x00000001
134 #define IGB_TX_FLAGS_VLAN 0x00000002
135 #define IGB_TX_FLAGS_TSO 0x00000004
136 #define IGB_TX_FLAGS_IPV4 0x00000008
137 #define IGB_TX_FLAGS_TSTAMP 0x00000010
138 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
139 #define IGB_TX_FLAGS_VLAN_SHIFT 16
141 /* wrapper around a pointer to a socket buffer,
142 * so a DMA handle can be stored along with the buffer */
143 struct igb_tx_buffer {
144 union e1000_adv_tx_desc *next_to_watch;
145 unsigned long time_stamp;
147 unsigned int bytecount;
155 struct igb_rx_buffer {
163 struct igb_tx_queue_stats {
170 struct igb_rx_queue_stats {
178 struct igb_q_vector {
179 struct igb_adapter *adapter; /* backlink */
180 struct igb_ring *rx_ring;
181 struct igb_ring *tx_ring;
182 struct napi_struct napi;
192 void __iomem *itr_register;
194 char name[IFNAMSIZ + 9];
198 struct igb_q_vector *q_vector; /* backlink to q_vector */
199 struct net_device *netdev; /* back pointer to net_device */
200 struct device *dev; /* device pointer for dma mapping */
201 union { /* array of buffer info structs */
202 struct igb_tx_buffer *tx_buffer_info;
203 struct igb_rx_buffer *rx_buffer_info;
205 void *desc; /* descriptor ring memory */
206 unsigned long flags; /* ring specific flags */
207 void __iomem *tail; /* pointer to ring tail register */
209 u16 count; /* number of desc. in the ring */
210 u8 queue_index; /* logical index of the ring*/
211 u8 reg_idx; /* physical index of the ring */
212 u32 size; /* length of desc. ring in bytes */
214 /* everything past this point are written often */
215 u16 next_to_clean ____cacheline_aligned_in_smp;
218 unsigned int total_bytes;
219 unsigned int total_packets;
224 struct igb_tx_queue_stats tx_stats;
225 struct u64_stats_sync tx_syncp;
226 struct u64_stats_sync tx_syncp2;
231 struct igb_rx_queue_stats rx_stats;
232 struct u64_stats_sync rx_syncp;
235 /* Items past this point are only used during ring alloc / free */
236 dma_addr_t dma; /* phys address of the ring */
237 int numa_node; /* node to alloc ring memory on */
240 enum e1000_ring_flags_t {
241 IGB_RING_FLAG_RX_CSUM,
242 IGB_RING_FLAG_RX_SCTP_CSUM,
243 IGB_RING_FLAG_TX_CTX_IDX,
244 IGB_RING_FLAG_TX_DETECT_HANG
247 #define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
249 #define IGB_RX_DESC(R, i) \
250 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
251 #define IGB_TX_DESC(R, i) \
252 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
253 #define IGB_TX_CTXTDESC(R, i) \
254 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
256 /* igb_desc_unused - calculate if we have unused descriptors */
257 static inline int igb_desc_unused(struct igb_ring *ring)
259 if (ring->next_to_clean > ring->next_to_use)
260 return ring->next_to_clean - ring->next_to_use - 1;
262 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
265 /* board specific private data structure */
267 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
269 struct net_device *netdev;
274 unsigned int num_q_vectors;
275 struct msix_entry *msix_entries;
277 /* Interrupt Throttle Rate */
285 u32 tx_timeout_count;
287 struct igb_ring *tx_ring[16];
291 struct igb_ring *rx_ring[16];
296 struct timer_list watchdog_timer;
297 struct timer_list phy_info_timer;
306 struct work_struct reset_task;
307 struct work_struct watchdog_task;
309 u8 tx_timeout_factor;
310 struct timer_list blink_timer;
311 unsigned long led_status;
313 /* OS defined structs */
314 struct pci_dev *pdev;
315 struct cyclecounter cycles;
316 struct timecounter clock;
317 struct timecompare compare;
318 struct hwtstamp_config hwtstamp_config;
320 spinlock_t stats64_lock;
321 struct rtnl_link_stats64 stats64;
323 /* structs defined in e1000_hw.h */
325 struct e1000_hw_stats stats;
326 struct e1000_phy_info phy_info;
327 struct e1000_phy_stats phy_stats;
330 struct igb_ring test_tx_ring;
331 struct igb_ring test_rx_ring;
335 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
336 u32 eims_enable_mask;
339 /* to not mess up cache alignment, always add to the bottom */
344 unsigned int vfs_allocated_count;
345 struct vf_data_storage *vf_data;
346 int vf_rate_link_speed;
352 #define IGB_FLAG_HAS_MSI (1 << 0)
353 #define IGB_FLAG_DCA_ENABLED (1 << 1)
354 #define IGB_FLAG_QUAD_PORT_A (1 << 2)
355 #define IGB_FLAG_QUEUE_PAIRS (1 << 3)
356 #define IGB_FLAG_DMAC (1 << 4)
358 /* DMA Coalescing defines */
359 #define IGB_MIN_TXPBSIZE 20408
360 #define IGB_TX_BUF_4096 4096
361 #define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
363 #define IGB_82576_TSYNC_SHIFT 19
364 #define IGB_82580_TSYNC_SHIFT 24
365 #define IGB_TS_HDR_LEN 16
376 extern char igb_driver_name[];
377 extern char igb_driver_version[];
379 extern int igb_up(struct igb_adapter *);
380 extern void igb_down(struct igb_adapter *);
381 extern void igb_reinit_locked(struct igb_adapter *);
382 extern void igb_reset(struct igb_adapter *);
383 extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
384 extern int igb_setup_tx_resources(struct igb_ring *);
385 extern int igb_setup_rx_resources(struct igb_ring *);
386 extern void igb_free_tx_resources(struct igb_ring *);
387 extern void igb_free_rx_resources(struct igb_ring *);
388 extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
389 extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
390 extern void igb_setup_tctl(struct igb_adapter *);
391 extern void igb_setup_rctl(struct igb_adapter *);
392 extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
393 extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
394 struct igb_tx_buffer *);
395 extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
396 extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
397 extern bool igb_has_link(struct igb_adapter *adapter);
398 extern void igb_set_ethtool_ops(struct net_device *);
399 extern void igb_power_up_link(struct igb_adapter *);
401 static inline s32 igb_reset_phy(struct e1000_hw *hw)
403 if (hw->phy.ops.reset)
404 return hw->phy.ops.reset(hw);
409 static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
411 if (hw->phy.ops.read_reg)
412 return hw->phy.ops.read_reg(hw, offset, data);
417 static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
419 if (hw->phy.ops.write_reg)
420 return hw->phy.ops.write_reg(hw, offset, data);
425 static inline s32 igb_get_phy_info(struct e1000_hw *hw)
427 if (hw->phy.ops.get_phy_info)
428 return hw->phy.ops.get_phy_info(hw);