1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
31 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
32 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
33 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
34 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
35 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
36 u16 *data, bool read, bool page_set);
37 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
38 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read);
41 /* Cable length tables */
42 static const u16 e1000_m88_cable_length_table[] = {
43 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
44 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
45 ARRAY_SIZE(e1000_m88_cable_length_table)
47 static const u16 e1000_igp_2_cable_length_table[] = {
48 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
49 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
50 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
51 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
52 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
53 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
54 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
57 ARRAY_SIZE(e1000_igp_2_cable_length_table)
59 #define BM_PHY_REG_PAGE(offset) \
60 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
61 #define BM_PHY_REG_NUM(offset) \
62 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
63 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
64 ~MAX_PHY_REG_ADDRESS)))
66 #define HV_INTC_FC_PAGE_START 768
67 #define I82578_ADDR_REG 29
68 #define I82577_ADDR_REG 16
69 #define I82577_CFG_REG 22
70 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
71 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
72 #define I82577_CTRL_REG 23
74 /* 82577 specific PHY registers */
75 #define I82577_PHY_CTRL_2 18
76 #define I82577_PHY_STATUS_2 26
77 #define I82577_PHY_DIAG_STATUS 31
79 /* I82577 PHY Status 2 */
80 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
81 #define I82577_PHY_STATUS2_MDIX 0x0800
82 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
83 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
85 /* I82577 PHY Control 2 */
86 #define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200
87 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400
88 #define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600
90 /* I82577 PHY Diagnostics Status */
91 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
92 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
94 /* BM PHY Copper Specific Control 1 */
95 #define BM_CS_CTRL1 16
97 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
98 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
99 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
102 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
103 * @hw: pointer to the HW structure
105 * Read the PHY management control register and check whether a PHY reset
106 * is blocked. If a reset is not blocked return 0, otherwise
107 * return E1000_BLK_PHY_RESET (12).
109 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
115 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
116 E1000_BLK_PHY_RESET : 0;
120 * e1000e_get_phy_id - Retrieve the PHY ID and revision
121 * @hw: pointer to the HW structure
123 * Reads the PHY registers and stores the PHY ID and possibly the PHY
124 * revision in the hardware structure.
126 s32 e1000e_get_phy_id(struct e1000_hw *hw)
128 struct e1000_phy_info *phy = &hw->phy;
133 if (!phy->ops.read_reg)
136 while (retry_count < 2) {
137 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
141 phy->id = (u32)(phy_id << 16);
143 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
147 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
148 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
150 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
160 * e1000e_phy_reset_dsp - Reset PHY DSP
161 * @hw: pointer to the HW structure
163 * Reset the digital signal processor.
165 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
169 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
173 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
177 * e1000e_read_phy_reg_mdic - Read MDI control register
178 * @hw: pointer to the HW structure
179 * @offset: register offset to be read
180 * @data: pointer to the read data
182 * Reads the MDI control register in the PHY at offset and stores the
183 * information read to data.
185 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
187 struct e1000_phy_info *phy = &hw->phy;
190 if (offset > MAX_PHY_REG_ADDRESS) {
191 e_dbg("PHY Address %d is out of range\n", offset);
192 return -E1000_ERR_PARAM;
195 /* Set up Op-code, Phy Address, and register offset in the MDI
196 * Control register. The MAC will take care of interfacing with the
197 * PHY to retrieve the desired data.
199 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
200 (phy->addr << E1000_MDIC_PHY_SHIFT) |
201 (E1000_MDIC_OP_READ));
205 /* Poll the ready bit to see if the MDI read completed
206 * Increasing the time out as testing showed failures with
209 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
212 if (mdic & E1000_MDIC_READY)
215 if (!(mdic & E1000_MDIC_READY)) {
216 e_dbg("MDI Read did not complete\n");
217 return -E1000_ERR_PHY;
219 if (mdic & E1000_MDIC_ERROR) {
220 e_dbg("MDI Error\n");
221 return -E1000_ERR_PHY;
225 /* Allow some time after each MDIC transaction to avoid
226 * reading duplicate data in the next MDIC transaction.
228 if (hw->mac.type == e1000_pch2lan)
235 * e1000e_write_phy_reg_mdic - Write MDI control register
236 * @hw: pointer to the HW structure
237 * @offset: register offset to write to
238 * @data: data to write to register at offset
240 * Writes data to MDI control register in the PHY at offset.
242 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
244 struct e1000_phy_info *phy = &hw->phy;
247 if (offset > MAX_PHY_REG_ADDRESS) {
248 e_dbg("PHY Address %d is out of range\n", offset);
249 return -E1000_ERR_PARAM;
252 /* Set up Op-code, Phy Address, and register offset in the MDI
253 * Control register. The MAC will take care of interfacing with the
254 * PHY to retrieve the desired data.
256 mdic = (((u32)data) |
257 (offset << E1000_MDIC_REG_SHIFT) |
258 (phy->addr << E1000_MDIC_PHY_SHIFT) |
259 (E1000_MDIC_OP_WRITE));
263 /* Poll the ready bit to see if the MDI read completed
264 * Increasing the time out as testing showed failures with
267 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
270 if (mdic & E1000_MDIC_READY)
273 if (!(mdic & E1000_MDIC_READY)) {
274 e_dbg("MDI Write did not complete\n");
275 return -E1000_ERR_PHY;
277 if (mdic & E1000_MDIC_ERROR) {
278 e_dbg("MDI Error\n");
279 return -E1000_ERR_PHY;
282 /* Allow some time after each MDIC transaction to avoid
283 * reading duplicate data in the next MDIC transaction.
285 if (hw->mac.type == e1000_pch2lan)
292 * e1000e_read_phy_reg_m88 - Read m88 PHY register
293 * @hw: pointer to the HW structure
294 * @offset: register offset to be read
295 * @data: pointer to the read data
297 * Acquires semaphore, if necessary, then reads the PHY register at offset
298 * and storing the retrieved information in data. Release any acquired
299 * semaphores before exiting.
301 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
305 ret_val = hw->phy.ops.acquire(hw);
309 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
312 hw->phy.ops.release(hw);
318 * e1000e_write_phy_reg_m88 - Write m88 PHY register
319 * @hw: pointer to the HW structure
320 * @offset: register offset to write to
321 * @data: data to write at register offset
323 * Acquires semaphore, if necessary, then writes the data to PHY register
324 * at the offset. Release any acquired semaphores before exiting.
326 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
330 ret_val = hw->phy.ops.acquire(hw);
334 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
337 hw->phy.ops.release(hw);
343 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
344 * @hw: pointer to the HW structure
345 * @page: page to set (shifted left when necessary)
347 * Sets PHY page required for PHY register access. Assumes semaphore is
348 * already acquired. Note, this function sets phy.addr to 1 so the caller
349 * must set it appropriately (if necessary) after this function returns.
351 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
353 e_dbg("Setting page 0x%x\n", page);
357 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
361 * __e1000e_read_phy_reg_igp - Read igp PHY register
362 * @hw: pointer to the HW structure
363 * @offset: register offset to be read
364 * @data: pointer to the read data
365 * @locked: semaphore has already been acquired or not
367 * Acquires semaphore, if necessary, then reads the PHY register at offset
368 * and stores the retrieved information in data. Release any acquired
369 * semaphores before exiting.
371 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
377 if (!hw->phy.ops.acquire)
380 ret_val = hw->phy.ops.acquire(hw);
385 if (offset > MAX_PHY_MULTI_PAGE_REG)
386 ret_val = e1000e_write_phy_reg_mdic(hw,
387 IGP01E1000_PHY_PAGE_SELECT,
390 ret_val = e1000e_read_phy_reg_mdic(hw,
391 MAX_PHY_REG_ADDRESS & offset,
394 hw->phy.ops.release(hw);
400 * e1000e_read_phy_reg_igp - Read igp PHY register
401 * @hw: pointer to the HW structure
402 * @offset: register offset to be read
403 * @data: pointer to the read data
405 * Acquires semaphore then reads the PHY register at offset and stores the
406 * retrieved information in data.
407 * Release the acquired semaphore before exiting.
409 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
411 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
415 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
416 * @hw: pointer to the HW structure
417 * @offset: register offset to be read
418 * @data: pointer to the read data
420 * Reads the PHY register at offset and stores the retrieved information
421 * in data. Assumes semaphore already acquired.
423 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
425 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
429 * e1000e_write_phy_reg_igp - Write igp PHY register
430 * @hw: pointer to the HW structure
431 * @offset: register offset to write to
432 * @data: data to write at register offset
433 * @locked: semaphore has already been acquired or not
435 * Acquires semaphore, if necessary, then writes the data to PHY register
436 * at the offset. Release any acquired semaphores before exiting.
438 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
444 if (!hw->phy.ops.acquire)
447 ret_val = hw->phy.ops.acquire(hw);
452 if (offset > MAX_PHY_MULTI_PAGE_REG)
453 ret_val = e1000e_write_phy_reg_mdic(hw,
454 IGP01E1000_PHY_PAGE_SELECT,
457 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
461 hw->phy.ops.release(hw);
467 * e1000e_write_phy_reg_igp - Write igp PHY register
468 * @hw: pointer to the HW structure
469 * @offset: register offset to write to
470 * @data: data to write at register offset
472 * Acquires semaphore then writes the data to PHY register
473 * at the offset. Release any acquired semaphores before exiting.
475 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
477 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
481 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
482 * @hw: pointer to the HW structure
483 * @offset: register offset to write to
484 * @data: data to write at register offset
486 * Writes the data to PHY register at the offset.
487 * Assumes semaphore already acquired.
489 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
491 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
495 * __e1000_read_kmrn_reg - Read kumeran register
496 * @hw: pointer to the HW structure
497 * @offset: register offset to be read
498 * @data: pointer to the read data
499 * @locked: semaphore has already been acquired or not
501 * Acquires semaphore, if necessary. Then reads the PHY register at offset
502 * using the kumeran interface. The information retrieved is stored in data.
503 * Release any acquired semaphores before exiting.
505 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
513 if (!hw->phy.ops.acquire)
516 ret_val = hw->phy.ops.acquire(hw);
521 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
522 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
523 ew32(KMRNCTRLSTA, kmrnctrlsta);
528 kmrnctrlsta = er32(KMRNCTRLSTA);
529 *data = (u16)kmrnctrlsta;
532 hw->phy.ops.release(hw);
538 * e1000e_read_kmrn_reg - Read kumeran register
539 * @hw: pointer to the HW structure
540 * @offset: register offset to be read
541 * @data: pointer to the read data
543 * Acquires semaphore then reads the PHY register at offset using the
544 * kumeran interface. The information retrieved is stored in data.
545 * Release the acquired semaphore before exiting.
547 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
549 return __e1000_read_kmrn_reg(hw, offset, data, false);
553 * e1000e_read_kmrn_reg_locked - Read kumeran register
554 * @hw: pointer to the HW structure
555 * @offset: register offset to be read
556 * @data: pointer to the read data
558 * Reads the PHY register at offset using the kumeran interface. The
559 * information retrieved is stored in data.
560 * Assumes semaphore already acquired.
562 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
564 return __e1000_read_kmrn_reg(hw, offset, data, true);
568 * __e1000_write_kmrn_reg - Write kumeran register
569 * @hw: pointer to the HW structure
570 * @offset: register offset to write to
571 * @data: data to write at register offset
572 * @locked: semaphore has already been acquired or not
574 * Acquires semaphore, if necessary. Then write the data to PHY register
575 * at the offset using the kumeran interface. Release any acquired semaphores
578 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
586 if (!hw->phy.ops.acquire)
589 ret_val = hw->phy.ops.acquire(hw);
594 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
595 E1000_KMRNCTRLSTA_OFFSET) | data;
596 ew32(KMRNCTRLSTA, kmrnctrlsta);
602 hw->phy.ops.release(hw);
608 * e1000e_write_kmrn_reg - Write kumeran register
609 * @hw: pointer to the HW structure
610 * @offset: register offset to write to
611 * @data: data to write at register offset
613 * Acquires semaphore then writes the data to the PHY register at the offset
614 * using the kumeran interface. Release the acquired semaphore before exiting.
616 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
618 return __e1000_write_kmrn_reg(hw, offset, data, false);
622 * e1000e_write_kmrn_reg_locked - Write kumeran register
623 * @hw: pointer to the HW structure
624 * @offset: register offset to write to
625 * @data: data to write at register offset
627 * Write the data to PHY register at the offset using the kumeran interface.
628 * Assumes semaphore already acquired.
630 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
632 return __e1000_write_kmrn_reg(hw, offset, data, true);
636 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
637 * @hw: pointer to the HW structure
639 * Sets up Master/slave mode
641 static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
646 /* Resolve Master/Slave mode */
647 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &phy_data);
651 /* load defaults for future use */
652 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
653 ((phy_data & CR_1000T_MS_VALUE) ?
654 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
656 switch (hw->phy.ms_type) {
657 case e1000_ms_force_master:
658 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
660 case e1000_ms_force_slave:
661 phy_data |= CR_1000T_MS_ENABLE;
662 phy_data &= ~(CR_1000T_MS_VALUE);
665 phy_data &= ~CR_1000T_MS_ENABLE;
671 return e1e_wphy(hw, PHY_1000T_CTRL, phy_data);
675 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
676 * @hw: pointer to the HW structure
678 * Sets up Carrier-sense on Transmit and downshift values.
680 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
685 /* Enable CRS on Tx. This must be set for half-duplex operation. */
686 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
690 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
692 /* Enable downshift */
693 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
695 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
699 /* Set MDI/MDIX mode */
700 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
703 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
709 switch (hw->phy.mdix) {
713 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
717 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
720 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
724 return e1000_set_master_slave_mode(hw);
728 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
729 * @hw: pointer to the HW structure
731 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
732 * and downshift values are set also.
734 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
736 struct e1000_phy_info *phy = &hw->phy;
740 /* Enable CRS on Tx. This must be set for half-duplex operation. */
741 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
745 /* For BM PHY this bit is downshift enable */
746 if (phy->type != e1000_phy_bm)
747 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
750 * MDI/MDI-X = 0 (default)
751 * 0 - Auto for all speeds
754 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
756 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
760 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
763 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
766 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
770 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
775 * disable_polarity_correction = 0 (default)
776 * Automatic Correction for Reversed Cable Polarity
780 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
781 if (phy->disable_polarity_correction)
782 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
784 /* Enable downshift on BM (disabled by default) */
785 if (phy->type == e1000_phy_bm) {
786 /* For 82574/82583, first disable then enable downshift */
787 if (phy->id == BME1000_E_PHY_ID_R2) {
788 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
789 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
793 /* Commit the changes. */
794 ret_val = e1000e_commit_phy(hw);
796 e_dbg("Error committing the PHY changes\n");
801 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
804 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
808 if ((phy->type == e1000_phy_m88) &&
809 (phy->revision < E1000_REVISION_4) &&
810 (phy->id != BME1000_E_PHY_ID_R2)) {
811 /* Force TX_CLK in the Extended PHY Specific Control Register
814 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
818 phy_data |= M88E1000_EPSCR_TX_CLK_25;
820 if ((phy->revision == 2) &&
821 (phy->id == M88E1111_I_PHY_ID)) {
822 /* 82573L PHY - set the downshift counter to 5x. */
823 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
824 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
826 /* Configure Master and Slave downshift values */
827 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
828 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
829 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
830 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
832 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
837 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
838 /* Set PHY page 0, register 29 to 0x0003 */
839 ret_val = e1e_wphy(hw, 29, 0x0003);
843 /* Set PHY page 0, register 30 to 0x0000 */
844 ret_val = e1e_wphy(hw, 30, 0x0000);
849 /* Commit the changes. */
850 ret_val = e1000e_commit_phy(hw);
852 e_dbg("Error committing the PHY changes\n");
856 if (phy->type == e1000_phy_82578) {
857 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
861 /* 82578 PHY - set the downshift count to 1x. */
862 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
863 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
864 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
873 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
874 * @hw: pointer to the HW structure
876 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
879 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
881 struct e1000_phy_info *phy = &hw->phy;
885 ret_val = e1000_phy_hw_reset(hw);
887 e_dbg("Error resetting the PHY.\n");
891 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
892 * timeout issues when LFS is enabled.
896 /* disable lplu d0 during driver init */
897 ret_val = e1000_set_d0_lplu_state(hw, false);
899 e_dbg("Error Disabling LPLU D0\n");
902 /* Configure mdi-mdix settings */
903 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
907 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
911 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
914 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
918 data |= IGP01E1000_PSCR_AUTO_MDIX;
921 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
925 /* set auto-master slave resolution settings */
926 if (hw->mac.autoneg) {
927 /* when autonegotiation advertisement is only 1000Mbps then we
928 * should disable SmartSpeed and enable Auto MasterSlave
929 * resolution as hardware default.
931 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
932 /* Disable SmartSpeed */
933 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
938 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
939 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
944 /* Set auto Master/Slave resolution process */
945 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
949 data &= ~CR_1000T_MS_ENABLE;
950 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
955 ret_val = e1000_set_master_slave_mode(hw);
962 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
963 * @hw: pointer to the HW structure
965 * Reads the MII auto-neg advertisement register and/or the 1000T control
966 * register and if the PHY is already setup for auto-negotiation, then
967 * return successful. Otherwise, setup advertisement and flow control to
968 * the appropriate values for the wanted auto-negotiation.
970 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
972 struct e1000_phy_info *phy = &hw->phy;
974 u16 mii_autoneg_adv_reg;
975 u16 mii_1000t_ctrl_reg = 0;
977 phy->autoneg_advertised &= phy->autoneg_mask;
979 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
980 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
984 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
985 /* Read the MII 1000Base-T Control Register (Address 9). */
986 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
991 /* Need to parse both autoneg_advertised and fc and set up
992 * the appropriate PHY registers. First we will parse for
993 * autoneg_advertised software override. Since we can advertise
994 * a plethora of combinations, we need to check each bit
998 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
999 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1000 * the 1000Base-T Control Register (Address 9).
1002 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1003 NWAY_AR_100TX_HD_CAPS |
1004 NWAY_AR_10T_FD_CAPS |
1005 NWAY_AR_10T_HD_CAPS);
1006 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1008 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
1010 /* Do we want to advertise 10 Mb Half Duplex? */
1011 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1012 e_dbg("Advertise 10mb Half duplex\n");
1013 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1016 /* Do we want to advertise 10 Mb Full Duplex? */
1017 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1018 e_dbg("Advertise 10mb Full duplex\n");
1019 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1022 /* Do we want to advertise 100 Mb Half Duplex? */
1023 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1024 e_dbg("Advertise 100mb Half duplex\n");
1025 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1028 /* Do we want to advertise 100 Mb Full Duplex? */
1029 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1030 e_dbg("Advertise 100mb Full duplex\n");
1031 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1034 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1035 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1036 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1038 /* Do we want to advertise 1000 Mb Full Duplex? */
1039 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1040 e_dbg("Advertise 1000mb Full duplex\n");
1041 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1044 /* Check for a software override of the flow control settings, and
1045 * setup the PHY advertisement registers accordingly. If
1046 * auto-negotiation is enabled, then software will have to set the
1047 * "PAUSE" bits to the correct value in the Auto-Negotiation
1048 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1051 * The possible values of the "fc" parameter are:
1052 * 0: Flow control is completely disabled
1053 * 1: Rx flow control is enabled (we can receive pause frames
1054 * but not send pause frames).
1055 * 2: Tx flow control is enabled (we can send pause frames
1056 * but we do not support receiving pause frames).
1057 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1058 * other: No software override. The flow control configuration
1059 * in the EEPROM is used.
1061 switch (hw->fc.current_mode) {
1063 /* Flow control (Rx & Tx) is completely disabled by a
1064 * software over-ride.
1066 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1068 case e1000_fc_rx_pause:
1069 /* Rx Flow control is enabled, and Tx Flow control is
1070 * disabled, by a software over-ride.
1072 * Since there really isn't a way to advertise that we are
1073 * capable of Rx Pause ONLY, we will advertise that we
1074 * support both symmetric and asymmetric Rx PAUSE. Later
1075 * (in e1000e_config_fc_after_link_up) we will disable the
1076 * hw's ability to send PAUSE frames.
1078 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1080 case e1000_fc_tx_pause:
1081 /* Tx Flow control is enabled, and Rx Flow control is
1082 * disabled, by a software over-ride.
1084 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1085 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1088 /* Flow control (both Rx and Tx) is enabled by a software
1091 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1094 e_dbg("Flow control param set incorrectly\n");
1095 return -E1000_ERR_CONFIG;
1098 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1102 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1104 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1105 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1111 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1112 * @hw: pointer to the HW structure
1114 * Performs initial bounds checking on autoneg advertisement parameter, then
1115 * configure to advertise the full capability. Setup the PHY to autoneg
1116 * and restart the negotiation process between the link partner. If
1117 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1119 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1121 struct e1000_phy_info *phy = &hw->phy;
1125 /* Perform some bounds checking on the autoneg advertisement
1128 phy->autoneg_advertised &= phy->autoneg_mask;
1130 /* If autoneg_advertised is zero, we assume it was not defaulted
1131 * by the calling code so we set to advertise full capability.
1133 if (!phy->autoneg_advertised)
1134 phy->autoneg_advertised = phy->autoneg_mask;
1136 e_dbg("Reconfiguring auto-neg advertisement params\n");
1137 ret_val = e1000_phy_setup_autoneg(hw);
1139 e_dbg("Error Setting up Auto-Negotiation\n");
1142 e_dbg("Restarting Auto-Neg\n");
1144 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1145 * the Auto Neg Restart bit in the PHY control register.
1147 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1151 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1152 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1156 /* Does the user want to wait for Auto-Neg to complete here, or
1157 * check at a later time (for example, callback routine).
1159 if (phy->autoneg_wait_to_complete) {
1160 ret_val = e1000_wait_autoneg(hw);
1162 e_dbg("Error while waiting for autoneg to complete\n");
1167 hw->mac.get_link_status = true;
1173 * e1000e_setup_copper_link - Configure copper link settings
1174 * @hw: pointer to the HW structure
1176 * Calls the appropriate function to configure the link for auto-neg or forced
1177 * speed and duplex. Then we check for link, once link is established calls
1178 * to configure collision distance and flow control are called. If link is
1179 * not established, we return -E1000_ERR_PHY (-2).
1181 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1186 if (hw->mac.autoneg) {
1187 /* Setup autoneg and flow control advertisement and perform
1190 ret_val = e1000_copper_link_autoneg(hw);
1194 /* PHY will be set to 10H, 10F, 100H or 100F
1195 * depending on user settings.
1197 e_dbg("Forcing Speed and Duplex\n");
1198 ret_val = e1000_phy_force_speed_duplex(hw);
1200 e_dbg("Error Forcing Speed and Duplex\n");
1205 /* Check link status. Wait up to 100 microseconds for link to become
1208 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1214 e_dbg("Valid link established!!!\n");
1215 hw->mac.ops.config_collision_dist(hw);
1216 ret_val = e1000e_config_fc_after_link_up(hw);
1218 e_dbg("Unable to establish link!!!\n");
1225 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1226 * @hw: pointer to the HW structure
1228 * Calls the PHY setup function to force speed and duplex. Clears the
1229 * auto-crossover to force MDI manually. Waits for link and returns
1230 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1232 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1234 struct e1000_phy_info *phy = &hw->phy;
1239 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1243 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1245 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1249 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1250 * forced whenever speed and duplex are forced.
1252 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1256 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1257 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1259 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1263 e_dbg("IGP PSCR: %X\n", phy_data);
1267 if (phy->autoneg_wait_to_complete) {
1268 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1270 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1276 e_dbg("Link taking longer than expected.\n");
1279 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1287 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1288 * @hw: pointer to the HW structure
1290 * Calls the PHY setup function to force speed and duplex. Clears the
1291 * auto-crossover to force MDI manually. Resets the PHY to commit the
1292 * changes. If time expires while waiting for link up, we reset the DSP.
1293 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1294 * successful completion, else return corresponding error code.
1296 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1298 struct e1000_phy_info *phy = &hw->phy;
1303 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1304 * forced whenever speed and duplex are forced.
1306 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1310 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1311 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1315 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1317 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1321 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1323 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1327 /* Reset the phy to commit changes. */
1328 ret_val = e1000e_commit_phy(hw);
1332 if (phy->autoneg_wait_to_complete) {
1333 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1335 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1341 if (hw->phy.type != e1000_phy_m88) {
1342 e_dbg("Link taking longer than expected.\n");
1344 /* We didn't get link.
1345 * Reset the DSP and cross our fingers.
1347 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1351 ret_val = e1000e_phy_reset_dsp(hw);
1358 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1364 if (hw->phy.type != e1000_phy_m88)
1367 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1371 /* Resetting the phy means we need to re-force TX_CLK in the
1372 * Extended PHY Specific Control Register to 25MHz clock from
1373 * the reset value of 2.5MHz.
1375 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1376 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1380 /* In addition, we must re-enable CRS on Tx for both half and full
1383 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1387 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1388 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1394 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1395 * @hw: pointer to the HW structure
1397 * Forces the speed and duplex settings of the PHY.
1398 * This is a function pointer entry point only called by
1399 * PHY setup routines.
1401 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1403 struct e1000_phy_info *phy = &hw->phy;
1408 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1412 e1000e_phy_force_speed_duplex_setup(hw, &data);
1414 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1418 /* Disable MDI-X support for 10/100 */
1419 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1423 data &= ~IFE_PMC_AUTO_MDIX;
1424 data &= ~IFE_PMC_FORCE_MDIX;
1426 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1430 e_dbg("IFE PMC: %X\n", data);
1434 if (phy->autoneg_wait_to_complete) {
1435 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1437 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1443 e_dbg("Link taking longer than expected.\n");
1446 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1456 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1457 * @hw: pointer to the HW structure
1458 * @phy_ctrl: pointer to current value of PHY_CONTROL
1460 * Forces speed and duplex on the PHY by doing the following: disable flow
1461 * control, force speed/duplex on the MAC, disable auto speed detection,
1462 * disable auto-negotiation, configure duplex, configure speed, configure
1463 * the collision distance, write configuration to CTRL register. The
1464 * caller must write to the PHY_CONTROL register for these settings to
1467 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1469 struct e1000_mac_info *mac = &hw->mac;
1472 /* Turn off flow control when forcing speed/duplex */
1473 hw->fc.current_mode = e1000_fc_none;
1475 /* Force speed/duplex on the mac */
1477 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1478 ctrl &= ~E1000_CTRL_SPD_SEL;
1480 /* Disable Auto Speed Detection */
1481 ctrl &= ~E1000_CTRL_ASDE;
1483 /* Disable autoneg on the phy */
1484 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1486 /* Forcing Full or Half Duplex? */
1487 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1488 ctrl &= ~E1000_CTRL_FD;
1489 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1490 e_dbg("Half Duplex\n");
1492 ctrl |= E1000_CTRL_FD;
1493 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1494 e_dbg("Full Duplex\n");
1497 /* Forcing 10mb or 100mb? */
1498 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1499 ctrl |= E1000_CTRL_SPD_100;
1500 *phy_ctrl |= MII_CR_SPEED_100;
1501 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1502 e_dbg("Forcing 100mb\n");
1504 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1505 *phy_ctrl |= MII_CR_SPEED_10;
1506 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1507 e_dbg("Forcing 10mb\n");
1510 hw->mac.ops.config_collision_dist(hw);
1516 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1517 * @hw: pointer to the HW structure
1518 * @active: boolean used to enable/disable lplu
1520 * Success returns 0, Failure returns 1
1522 * The low power link up (lplu) state is set to the power management level D3
1523 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1524 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1525 * is used during Dx states where the power conservation is most important.
1526 * During driver activity, SmartSpeed should be enabled so performance is
1529 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1531 struct e1000_phy_info *phy = &hw->phy;
1535 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1540 data &= ~IGP02E1000_PM_D3_LPLU;
1541 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1544 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1545 * during Dx states where the power conservation is most
1546 * important. During driver activity we should enable
1547 * SmartSpeed, so performance is maintained.
1549 if (phy->smart_speed == e1000_smart_speed_on) {
1550 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1555 data |= IGP01E1000_PSCFR_SMART_SPEED;
1556 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1560 } else if (phy->smart_speed == e1000_smart_speed_off) {
1561 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1566 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1567 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1572 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1573 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1574 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1575 data |= IGP02E1000_PM_D3_LPLU;
1576 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1580 /* When LPLU is enabled, we should disable SmartSpeed */
1581 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1585 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1586 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1593 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1594 * @hw: pointer to the HW structure
1596 * Success returns 0, Failure returns 1
1598 * A downshift is detected by querying the PHY link health.
1600 s32 e1000e_check_downshift(struct e1000_hw *hw)
1602 struct e1000_phy_info *phy = &hw->phy;
1604 u16 phy_data, offset, mask;
1606 switch (phy->type) {
1608 case e1000_phy_gg82563:
1610 case e1000_phy_82578:
1611 offset = M88E1000_PHY_SPEC_STATUS;
1612 mask = M88E1000_PSSR_DOWNSHIFT;
1614 case e1000_phy_igp_2:
1615 case e1000_phy_igp_3:
1616 offset = IGP01E1000_PHY_LINK_HEALTH;
1617 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1620 /* speed downshift not supported */
1621 phy->speed_downgraded = false;
1625 ret_val = e1e_rphy(hw, offset, &phy_data);
1628 phy->speed_downgraded = !!(phy_data & mask);
1634 * e1000_check_polarity_m88 - Checks the polarity.
1635 * @hw: pointer to the HW structure
1637 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1639 * Polarity is determined based on the PHY specific status register.
1641 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1643 struct e1000_phy_info *phy = &hw->phy;
1647 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1650 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1651 ? e1000_rev_polarity_reversed
1652 : e1000_rev_polarity_normal;
1658 * e1000_check_polarity_igp - Checks the polarity.
1659 * @hw: pointer to the HW structure
1661 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1663 * Polarity is determined based on the PHY port status register, and the
1664 * current speed (since there is no polarity at 100Mbps).
1666 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1668 struct e1000_phy_info *phy = &hw->phy;
1670 u16 data, offset, mask;
1672 /* Polarity is determined based on the speed of
1675 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1679 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1680 IGP01E1000_PSSR_SPEED_1000MBPS) {
1681 offset = IGP01E1000_PHY_PCS_INIT_REG;
1682 mask = IGP01E1000_PHY_POLARITY_MASK;
1684 /* This really only applies to 10Mbps since
1685 * there is no polarity for 100Mbps (always 0).
1687 offset = IGP01E1000_PHY_PORT_STATUS;
1688 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1691 ret_val = e1e_rphy(hw, offset, &data);
1694 phy->cable_polarity = (data & mask)
1695 ? e1000_rev_polarity_reversed
1696 : e1000_rev_polarity_normal;
1702 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1703 * @hw: pointer to the HW structure
1705 * Polarity is determined on the polarity reversal feature being enabled.
1707 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1709 struct e1000_phy_info *phy = &hw->phy;
1711 u16 phy_data, offset, mask;
1713 /* Polarity is determined based on the reversal feature being enabled.
1715 if (phy->polarity_correction) {
1716 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1717 mask = IFE_PESC_POLARITY_REVERSED;
1719 offset = IFE_PHY_SPECIAL_CONTROL;
1720 mask = IFE_PSC_FORCE_POLARITY;
1723 ret_val = e1e_rphy(hw, offset, &phy_data);
1726 phy->cable_polarity = (phy_data & mask)
1727 ? e1000_rev_polarity_reversed
1728 : e1000_rev_polarity_normal;
1734 * e1000_wait_autoneg - Wait for auto-neg completion
1735 * @hw: pointer to the HW structure
1737 * Waits for auto-negotiation to complete or for the auto-negotiation time
1738 * limit to expire, which ever happens first.
1740 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1745 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1746 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1747 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1750 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1753 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1758 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1765 * e1000e_phy_has_link_generic - Polls PHY for link
1766 * @hw: pointer to the HW structure
1767 * @iterations: number of times to poll for link
1768 * @usec_interval: delay between polling attempts
1769 * @success: pointer to whether polling was successful or not
1771 * Polls the PHY status register for link, 'iterations' number of times.
1773 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1774 u32 usec_interval, bool *success)
1779 for (i = 0; i < iterations; i++) {
1780 /* Some PHYs require the PHY_STATUS register to be read
1781 * twice due to the link bit being sticky. No harm doing
1782 * it across the board.
1784 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1786 /* If the first read fails, another entity may have
1787 * ownership of the resources, wait and try again to
1788 * see if they have relinquished the resources yet.
1790 udelay(usec_interval);
1791 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1794 if (phy_status & MII_SR_LINK_STATUS)
1796 if (usec_interval >= 1000)
1797 mdelay(usec_interval/1000);
1799 udelay(usec_interval);
1802 *success = (i < iterations);
1808 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1809 * @hw: pointer to the HW structure
1811 * Reads the PHY specific status register to retrieve the cable length
1812 * information. The cable length is determined by averaging the minimum and
1813 * maximum values to get the "average" cable length. The m88 PHY has four
1814 * possible cable length values, which are:
1815 * Register Value Cable Length
1819 * 3 110 - 140 meters
1822 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1824 struct e1000_phy_info *phy = &hw->phy;
1826 u16 phy_data, index;
1828 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1832 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1833 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1835 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1836 return -E1000_ERR_PHY;
1838 phy->min_cable_length = e1000_m88_cable_length_table[index];
1839 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1841 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1847 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1848 * @hw: pointer to the HW structure
1850 * The automatic gain control (agc) normalizes the amplitude of the
1851 * received signal, adjusting for the attenuation produced by the
1852 * cable. By reading the AGC registers, which represent the
1853 * combination of coarse and fine gain value, the value can be put
1854 * into a lookup table to obtain the approximate cable length
1857 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1859 struct e1000_phy_info *phy = &hw->phy;
1861 u16 phy_data, i, agc_value = 0;
1862 u16 cur_agc_index, max_agc_index = 0;
1863 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1864 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1865 IGP02E1000_PHY_AGC_A,
1866 IGP02E1000_PHY_AGC_B,
1867 IGP02E1000_PHY_AGC_C,
1868 IGP02E1000_PHY_AGC_D
1871 /* Read the AGC registers for all channels */
1872 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1873 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1877 /* Getting bits 15:9, which represent the combination of
1878 * coarse and fine gain values. The result is a number
1879 * that can be put into the lookup table to obtain the
1880 * approximate cable length.
1882 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1883 IGP02E1000_AGC_LENGTH_MASK;
1885 /* Array index bound check. */
1886 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1887 (cur_agc_index == 0))
1888 return -E1000_ERR_PHY;
1890 /* Remove min & max AGC values from calculation. */
1891 if (e1000_igp_2_cable_length_table[min_agc_index] >
1892 e1000_igp_2_cable_length_table[cur_agc_index])
1893 min_agc_index = cur_agc_index;
1894 if (e1000_igp_2_cable_length_table[max_agc_index] <
1895 e1000_igp_2_cable_length_table[cur_agc_index])
1896 max_agc_index = cur_agc_index;
1898 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1901 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1902 e1000_igp_2_cable_length_table[max_agc_index]);
1903 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1905 /* Calculate cable length with the error range of +/- 10 meters. */
1906 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1907 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1908 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1910 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1916 * e1000e_get_phy_info_m88 - Retrieve PHY information
1917 * @hw: pointer to the HW structure
1919 * Valid for only copper links. Read the PHY status register (sticky read)
1920 * to verify that link is up. Read the PHY special control register to
1921 * determine the polarity and 10base-T extended distance. Read the PHY
1922 * special status register to determine MDI/MDIx and current speed. If
1923 * speed is 1000, then determine cable length, local and remote receiver.
1925 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1927 struct e1000_phy_info *phy = &hw->phy;
1932 if (phy->media_type != e1000_media_type_copper) {
1933 e_dbg("Phy info is only valid for copper media\n");
1934 return -E1000_ERR_CONFIG;
1937 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1942 e_dbg("Phy info is only valid if link is up\n");
1943 return -E1000_ERR_CONFIG;
1946 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1950 phy->polarity_correction = !!(phy_data &
1951 M88E1000_PSCR_POLARITY_REVERSAL);
1953 ret_val = e1000_check_polarity_m88(hw);
1957 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1961 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1963 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1964 ret_val = e1000_get_cable_length(hw);
1968 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1972 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1973 ? e1000_1000t_rx_status_ok
1974 : e1000_1000t_rx_status_not_ok;
1976 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1977 ? e1000_1000t_rx_status_ok
1978 : e1000_1000t_rx_status_not_ok;
1980 /* Set values to "undefined" */
1981 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1982 phy->local_rx = e1000_1000t_rx_status_undefined;
1983 phy->remote_rx = e1000_1000t_rx_status_undefined;
1990 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1991 * @hw: pointer to the HW structure
1993 * Read PHY status to determine if link is up. If link is up, then
1994 * set/determine 10base-T extended distance and polarity correction. Read
1995 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1996 * determine on the cable length, local and remote receiver.
1998 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2000 struct e1000_phy_info *phy = &hw->phy;
2005 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2010 e_dbg("Phy info is only valid if link is up\n");
2011 return -E1000_ERR_CONFIG;
2014 phy->polarity_correction = true;
2016 ret_val = e1000_check_polarity_igp(hw);
2020 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2024 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
2026 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2027 IGP01E1000_PSSR_SPEED_1000MBPS) {
2028 ret_val = e1000_get_cable_length(hw);
2032 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2036 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2037 ? e1000_1000t_rx_status_ok
2038 : e1000_1000t_rx_status_not_ok;
2040 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2041 ? e1000_1000t_rx_status_ok
2042 : e1000_1000t_rx_status_not_ok;
2044 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2045 phy->local_rx = e1000_1000t_rx_status_undefined;
2046 phy->remote_rx = e1000_1000t_rx_status_undefined;
2053 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2054 * @hw: pointer to the HW structure
2056 * Populates "phy" structure with various feature states.
2058 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2060 struct e1000_phy_info *phy = &hw->phy;
2065 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2070 e_dbg("Phy info is only valid if link is up\n");
2071 return -E1000_ERR_CONFIG;
2074 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2077 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2079 if (phy->polarity_correction) {
2080 ret_val = e1000_check_polarity_ife(hw);
2084 /* Polarity is forced */
2085 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2086 ? e1000_rev_polarity_reversed
2087 : e1000_rev_polarity_normal;
2090 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2094 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2096 /* The following parameters are undefined for 10/100 operation. */
2097 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2098 phy->local_rx = e1000_1000t_rx_status_undefined;
2099 phy->remote_rx = e1000_1000t_rx_status_undefined;
2105 * e1000e_phy_sw_reset - PHY software reset
2106 * @hw: pointer to the HW structure
2108 * Does a software reset of the PHY by reading the PHY control register and
2109 * setting/write the control register reset bit to the PHY.
2111 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2116 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2120 phy_ctrl |= MII_CR_RESET;
2121 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2131 * e1000e_phy_hw_reset_generic - PHY hardware reset
2132 * @hw: pointer to the HW structure
2134 * Verify the reset block is not blocking us from resetting. Acquire
2135 * semaphore (if necessary) and read/set/write the device control reset
2136 * bit in the PHY. Wait the appropriate delay time for the device to
2137 * reset and release the semaphore (if necessary).
2139 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2141 struct e1000_phy_info *phy = &hw->phy;
2145 if (phy->ops.check_reset_block) {
2146 ret_val = phy->ops.check_reset_block(hw);
2151 ret_val = phy->ops.acquire(hw);
2156 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2159 udelay(phy->reset_delay_us);
2166 phy->ops.release(hw);
2168 return e1000_get_phy_cfg_done(hw);
2172 * e1000e_get_cfg_done - Generic configuration done
2173 * @hw: pointer to the HW structure
2175 * Generic function to wait 10 milli-seconds for configuration to complete
2176 * and return success.
2178 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2186 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2187 * @hw: pointer to the HW structure
2189 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2191 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2193 e_dbg("Running IGP 3 PHY init script\n");
2195 /* PHY init IGP 3 */
2196 /* Enable rise/fall, 10-mode work in class-A */
2197 e1e_wphy(hw, 0x2F5B, 0x9018);
2198 /* Remove all caps from Replica path filter */
2199 e1e_wphy(hw, 0x2F52, 0x0000);
2200 /* Bias trimming for ADC, AFE and Driver (Default) */
2201 e1e_wphy(hw, 0x2FB1, 0x8B24);
2202 /* Increase Hybrid poly bias */
2203 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2204 /* Add 4% to Tx amplitude in Gig mode */
2205 e1e_wphy(hw, 0x2010, 0x10B0);
2206 /* Disable trimming (TTT) */
2207 e1e_wphy(hw, 0x2011, 0x0000);
2208 /* Poly DC correction to 94.6% + 2% for all channels */
2209 e1e_wphy(hw, 0x20DD, 0x249A);
2210 /* ABS DC correction to 95.9% */
2211 e1e_wphy(hw, 0x20DE, 0x00D3);
2212 /* BG temp curve trim */
2213 e1e_wphy(hw, 0x28B4, 0x04CE);
2214 /* Increasing ADC OPAMP stage 1 currents to max */
2215 e1e_wphy(hw, 0x2F70, 0x29E4);
2216 /* Force 1000 ( required for enabling PHY regs configuration) */
2217 e1e_wphy(hw, 0x0000, 0x0140);
2218 /* Set upd_freq to 6 */
2219 e1e_wphy(hw, 0x1F30, 0x1606);
2221 e1e_wphy(hw, 0x1F31, 0xB814);
2222 /* Disable adaptive fixed FFE (Default) */
2223 e1e_wphy(hw, 0x1F35, 0x002A);
2224 /* Enable FFE hysteresis */
2225 e1e_wphy(hw, 0x1F3E, 0x0067);
2226 /* Fixed FFE for short cable lengths */
2227 e1e_wphy(hw, 0x1F54, 0x0065);
2228 /* Fixed FFE for medium cable lengths */
2229 e1e_wphy(hw, 0x1F55, 0x002A);
2230 /* Fixed FFE for long cable lengths */
2231 e1e_wphy(hw, 0x1F56, 0x002A);
2232 /* Enable Adaptive Clip Threshold */
2233 e1e_wphy(hw, 0x1F72, 0x3FB0);
2234 /* AHT reset limit to 1 */
2235 e1e_wphy(hw, 0x1F76, 0xC0FF);
2236 /* Set AHT master delay to 127 msec */
2237 e1e_wphy(hw, 0x1F77, 0x1DEC);
2238 /* Set scan bits for AHT */
2239 e1e_wphy(hw, 0x1F78, 0xF9EF);
2240 /* Set AHT Preset bits */
2241 e1e_wphy(hw, 0x1F79, 0x0210);
2242 /* Change integ_factor of channel A to 3 */
2243 e1e_wphy(hw, 0x1895, 0x0003);
2244 /* Change prop_factor of channels BCD to 8 */
2245 e1e_wphy(hw, 0x1796, 0x0008);
2246 /* Change cg_icount + enable integbp for channels BCD */
2247 e1e_wphy(hw, 0x1798, 0xD008);
2248 /* Change cg_icount + enable integbp + change prop_factor_master
2249 * to 8 for channel A
2251 e1e_wphy(hw, 0x1898, 0xD918);
2252 /* Disable AHT in Slave mode on channel A */
2253 e1e_wphy(hw, 0x187A, 0x0800);
2254 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2257 e1e_wphy(hw, 0x0019, 0x008D);
2258 /* Enable restart AN on an1000_dis change */
2259 e1e_wphy(hw, 0x001B, 0x2080);
2260 /* Enable wh_fifo read clock in 10/100 modes */
2261 e1e_wphy(hw, 0x0014, 0x0045);
2262 /* Restart AN, Speed selection is 1000 */
2263 e1e_wphy(hw, 0x0000, 0x1340);
2268 /* Internal function pointers */
2271 * e1000_get_phy_cfg_done - Generic PHY configuration done
2272 * @hw: pointer to the HW structure
2274 * Return success if silicon family did not implement a family specific
2275 * get_cfg_done function.
2277 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2279 if (hw->phy.ops.get_cfg_done)
2280 return hw->phy.ops.get_cfg_done(hw);
2286 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2287 * @hw: pointer to the HW structure
2289 * When the silicon family has not implemented a forced speed/duplex
2290 * function for the PHY, simply return 0.
2292 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2294 if (hw->phy.ops.force_speed_duplex)
2295 return hw->phy.ops.force_speed_duplex(hw);
2301 * e1000e_get_phy_type_from_id - Get PHY type from id
2302 * @phy_id: phy_id read from the phy
2304 * Returns the phy type from the id.
2306 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2308 enum e1000_phy_type phy_type = e1000_phy_unknown;
2311 case M88E1000_I_PHY_ID:
2312 case M88E1000_E_PHY_ID:
2313 case M88E1111_I_PHY_ID:
2314 case M88E1011_I_PHY_ID:
2315 phy_type = e1000_phy_m88;
2317 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2318 phy_type = e1000_phy_igp_2;
2320 case GG82563_E_PHY_ID:
2321 phy_type = e1000_phy_gg82563;
2323 case IGP03E1000_E_PHY_ID:
2324 phy_type = e1000_phy_igp_3;
2327 case IFE_PLUS_E_PHY_ID:
2328 case IFE_C_E_PHY_ID:
2329 phy_type = e1000_phy_ife;
2331 case BME1000_E_PHY_ID:
2332 case BME1000_E_PHY_ID_R2:
2333 phy_type = e1000_phy_bm;
2335 case I82578_E_PHY_ID:
2336 phy_type = e1000_phy_82578;
2338 case I82577_E_PHY_ID:
2339 phy_type = e1000_phy_82577;
2341 case I82579_E_PHY_ID:
2342 phy_type = e1000_phy_82579;
2345 phy_type = e1000_phy_i217;
2348 phy_type = e1000_phy_unknown;
2355 * e1000e_determine_phy_address - Determines PHY address.
2356 * @hw: pointer to the HW structure
2358 * This uses a trial and error method to loop through possible PHY
2359 * addresses. It tests each by reading the PHY ID registers and
2360 * checking for a match.
2362 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2366 enum e1000_phy_type phy_type = e1000_phy_unknown;
2368 hw->phy.id = phy_type;
2370 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2371 hw->phy.addr = phy_addr;
2375 e1000e_get_phy_id(hw);
2376 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2378 /* If phy_type is valid, break - we found our
2381 if (phy_type != e1000_phy_unknown)
2384 usleep_range(1000, 2000);
2389 return -E1000_ERR_PHY_TYPE;
2393 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2394 * @page: page to access
2396 * Returns the phy address for the page requested.
2398 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2402 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2409 * e1000e_write_phy_reg_bm - Write BM PHY register
2410 * @hw: pointer to the HW structure
2411 * @offset: register offset to write to
2412 * @data: data to write at register offset
2414 * Acquires semaphore, if necessary, then writes the data to PHY register
2415 * at the offset. Release any acquired semaphores before exiting.
2417 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2420 u32 page = offset >> IGP_PAGE_SHIFT;
2422 ret_val = hw->phy.ops.acquire(hw);
2426 /* Page 800 works differently than the rest so it has its own func */
2427 if (page == BM_WUC_PAGE) {
2428 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2433 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2435 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2436 u32 page_shift, page_select;
2438 /* Page select is register 31 for phy address 1 and 22 for
2439 * phy address 2 and 3. Page select is shifted only for
2442 if (hw->phy.addr == 1) {
2443 page_shift = IGP_PAGE_SHIFT;
2444 page_select = IGP01E1000_PHY_PAGE_SELECT;
2447 page_select = BM_PHY_PAGE_SELECT;
2450 /* Page is shifted left, PHY expects (page x 32) */
2451 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2452 (page << page_shift));
2457 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2461 hw->phy.ops.release(hw);
2466 * e1000e_read_phy_reg_bm - Read BM PHY register
2467 * @hw: pointer to the HW structure
2468 * @offset: register offset to be read
2469 * @data: pointer to the read data
2471 * Acquires semaphore, if necessary, then reads the PHY register at offset
2472 * and storing the retrieved information in data. Release any acquired
2473 * semaphores before exiting.
2475 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2478 u32 page = offset >> IGP_PAGE_SHIFT;
2480 ret_val = hw->phy.ops.acquire(hw);
2484 /* Page 800 works differently than the rest so it has its own func */
2485 if (page == BM_WUC_PAGE) {
2486 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2491 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2493 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2494 u32 page_shift, page_select;
2496 /* Page select is register 31 for phy address 1 and 22 for
2497 * phy address 2 and 3. Page select is shifted only for
2500 if (hw->phy.addr == 1) {
2501 page_shift = IGP_PAGE_SHIFT;
2502 page_select = IGP01E1000_PHY_PAGE_SELECT;
2505 page_select = BM_PHY_PAGE_SELECT;
2508 /* Page is shifted left, PHY expects (page x 32) */
2509 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2510 (page << page_shift));
2515 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2518 hw->phy.ops.release(hw);
2523 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2524 * @hw: pointer to the HW structure
2525 * @offset: register offset to be read
2526 * @data: pointer to the read data
2528 * Acquires semaphore, if necessary, then reads the PHY register at offset
2529 * and storing the retrieved information in data. Release any acquired
2530 * semaphores before exiting.
2532 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2535 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2537 ret_val = hw->phy.ops.acquire(hw);
2541 /* Page 800 works differently than the rest so it has its own func */
2542 if (page == BM_WUC_PAGE) {
2543 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2550 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2552 /* Page is shifted left, PHY expects (page x 32) */
2553 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2560 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2563 hw->phy.ops.release(hw);
2568 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2569 * @hw: pointer to the HW structure
2570 * @offset: register offset to write to
2571 * @data: data to write at register offset
2573 * Acquires semaphore, if necessary, then writes the data to PHY register
2574 * at the offset. Release any acquired semaphores before exiting.
2576 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2579 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2581 ret_val = hw->phy.ops.acquire(hw);
2585 /* Page 800 works differently than the rest so it has its own func */
2586 if (page == BM_WUC_PAGE) {
2587 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2594 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2595 /* Page is shifted left, PHY expects (page x 32) */
2596 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2603 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2607 hw->phy.ops.release(hw);
2612 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2613 * @hw: pointer to the HW structure
2614 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2616 * Assumes semaphore already acquired and phy_reg points to a valid memory
2617 * address to store contents of the BM_WUC_ENABLE_REG register.
2619 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2624 /* All page select, port ctrl and wakeup registers use phy address 1 */
2627 /* Select Port Control Registers page */
2628 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2630 e_dbg("Could not set Port Control page\n");
2634 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2636 e_dbg("Could not read PHY register %d.%d\n",
2637 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2641 /* Enable both PHY wakeup mode and Wakeup register page writes.
2642 * Prevent a power state change by disabling ME and Host PHY wakeup.
2645 temp |= BM_WUC_ENABLE_BIT;
2646 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2648 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2650 e_dbg("Could not write PHY register %d.%d\n",
2651 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2655 /* Select Host Wakeup Registers page - caller now able to write
2656 * registers on the Wakeup registers page
2658 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2662 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2663 * @hw: pointer to the HW structure
2664 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2666 * Restore BM_WUC_ENABLE_REG to its original value.
2668 * Assumes semaphore already acquired and *phy_reg is the contents of the
2669 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2672 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2676 /* Select Port Control Registers page */
2677 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2679 e_dbg("Could not set Port Control page\n");
2683 /* Restore 769.17 to its original value */
2684 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2686 e_dbg("Could not restore PHY register %d.%d\n",
2687 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2693 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2694 * @hw: pointer to the HW structure
2695 * @offset: register offset to be read or written
2696 * @data: pointer to the data to read or write
2697 * @read: determines if operation is read or write
2698 * @page_set: BM_WUC_PAGE already set and access enabled
2700 * Read the PHY register at offset and store the retrieved information in
2701 * data, or write data to PHY register at offset. Note the procedure to
2702 * access the PHY wakeup registers is different than reading the other PHY
2703 * registers. It works as such:
2704 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2705 * 2) Set page to 800 for host (801 if we were manageability)
2706 * 3) Write the address using the address opcode (0x11)
2707 * 4) Read or write the data using the data opcode (0x12)
2708 * 5) Restore 769.17.2 to its original value
2710 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2711 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2713 * Assumes semaphore is already acquired. When page_set==true, assumes
2714 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2715 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2717 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2718 u16 *data, bool read, bool page_set)
2721 u16 reg = BM_PHY_REG_NUM(offset);
2722 u16 page = BM_PHY_REG_PAGE(offset);
2725 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2726 if ((hw->mac.type == e1000_pchlan) &&
2727 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2728 e_dbg("Attempting to access page %d while gig enabled.\n",
2732 /* Enable access to PHY wakeup registers */
2733 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2735 e_dbg("Could not enable PHY wakeup reg access\n");
2740 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2742 /* Write the Wakeup register page offset value using opcode 0x11 */
2743 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2745 e_dbg("Could not write address opcode to page %d\n", page);
2750 /* Read the Wakeup register page value using opcode 0x12 */
2751 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2754 /* Write the Wakeup register page value using opcode 0x12 */
2755 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2760 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2765 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2771 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2772 * @hw: pointer to the HW structure
2774 * In the case of a PHY power down to save power, or to turn off link during a
2775 * driver unload, or wake on lan is not enabled, restore the link to previous
2778 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2782 /* The PHY will retain its settings across a power down/up cycle */
2783 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2784 mii_reg &= ~MII_CR_POWER_DOWN;
2785 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2789 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2790 * @hw: pointer to the HW structure
2792 * In the case of a PHY power down to save power, or to turn off link during a
2793 * driver unload, or wake on lan is not enabled, restore the link to previous
2796 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2800 /* The PHY will retain its settings across a power down/up cycle */
2801 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2802 mii_reg |= MII_CR_POWER_DOWN;
2803 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2804 usleep_range(1000, 2000);
2808 * e1000e_commit_phy - Soft PHY reset
2809 * @hw: pointer to the HW structure
2811 * Performs a soft PHY reset on those that apply. This is a function pointer
2812 * entry point called by drivers.
2814 s32 e1000e_commit_phy(struct e1000_hw *hw)
2816 if (hw->phy.ops.commit)
2817 return hw->phy.ops.commit(hw);
2823 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2824 * @hw: pointer to the HW structure
2825 * @active: boolean used to enable/disable lplu
2827 * Success returns 0, Failure returns 1
2829 * The low power link up (lplu) state is set to the power management level D0
2830 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2831 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2832 * is used during Dx states where the power conservation is most important.
2833 * During driver activity, SmartSpeed should be enabled so performance is
2834 * maintained. This is a function pointer entry point called by drivers.
2836 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2838 if (hw->phy.ops.set_d0_lplu_state)
2839 return hw->phy.ops.set_d0_lplu_state(hw, active);
2845 * __e1000_read_phy_reg_hv - Read HV PHY register
2846 * @hw: pointer to the HW structure
2847 * @offset: register offset to be read
2848 * @data: pointer to the read data
2849 * @locked: semaphore has already been acquired or not
2851 * Acquires semaphore, if necessary, then reads the PHY register at offset
2852 * and stores the retrieved information in data. Release any acquired
2853 * semaphore before exiting.
2855 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2856 bool locked, bool page_set)
2859 u16 page = BM_PHY_REG_PAGE(offset);
2860 u16 reg = BM_PHY_REG_NUM(offset);
2861 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2864 ret_val = hw->phy.ops.acquire(hw);
2869 /* Page 800 works differently than the rest so it has its own func */
2870 if (page == BM_WUC_PAGE) {
2871 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2876 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2877 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2883 if (page == HV_INTC_FC_PAGE_START)
2886 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2887 /* Page is shifted left, PHY expects (page x 32) */
2888 ret_val = e1000_set_page_igp(hw,
2889 (page << IGP_PAGE_SHIFT));
2891 hw->phy.addr = phy_addr;
2898 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2899 page << IGP_PAGE_SHIFT, reg);
2901 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2905 hw->phy.ops.release(hw);
2911 * e1000_read_phy_reg_hv - Read HV PHY register
2912 * @hw: pointer to the HW structure
2913 * @offset: register offset to be read
2914 * @data: pointer to the read data
2916 * Acquires semaphore then reads the PHY register at offset and stores
2917 * the retrieved information in data. Release the acquired semaphore
2920 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2922 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2926 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2927 * @hw: pointer to the HW structure
2928 * @offset: register offset to be read
2929 * @data: pointer to the read data
2931 * Reads the PHY register at offset and stores the retrieved information
2932 * in data. Assumes semaphore already acquired.
2934 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2936 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2940 * e1000_read_phy_reg_page_hv - Read HV PHY register
2941 * @hw: pointer to the HW structure
2942 * @offset: register offset to write to
2943 * @data: data to write at register offset
2945 * Reads the PHY register at offset and stores the retrieved information
2946 * in data. Assumes semaphore already acquired and page already set.
2948 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2950 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2954 * __e1000_write_phy_reg_hv - Write HV PHY register
2955 * @hw: pointer to the HW structure
2956 * @offset: register offset to write to
2957 * @data: data to write at register offset
2958 * @locked: semaphore has already been acquired or not
2960 * Acquires semaphore, if necessary, then writes the data to PHY register
2961 * at the offset. Release any acquired semaphores before exiting.
2963 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2964 bool locked, bool page_set)
2967 u16 page = BM_PHY_REG_PAGE(offset);
2968 u16 reg = BM_PHY_REG_NUM(offset);
2969 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2972 ret_val = hw->phy.ops.acquire(hw);
2977 /* Page 800 works differently than the rest so it has its own func */
2978 if (page == BM_WUC_PAGE) {
2979 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2984 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2985 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2991 if (page == HV_INTC_FC_PAGE_START)
2994 /* Workaround MDIO accesses being disabled after entering IEEE
2995 * Power Down (when bit 11 of the PHY Control register is set)
2997 if ((hw->phy.type == e1000_phy_82578) &&
2998 (hw->phy.revision >= 1) &&
2999 (hw->phy.addr == 2) &&
3000 !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) {
3002 ret_val = e1000_access_phy_debug_regs_hv(hw,
3009 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3010 /* Page is shifted left, PHY expects (page x 32) */
3011 ret_val = e1000_set_page_igp(hw,
3012 (page << IGP_PAGE_SHIFT));
3014 hw->phy.addr = phy_addr;
3021 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3022 page << IGP_PAGE_SHIFT, reg);
3024 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3029 hw->phy.ops.release(hw);
3035 * e1000_write_phy_reg_hv - Write HV PHY register
3036 * @hw: pointer to the HW structure
3037 * @offset: register offset to write to
3038 * @data: data to write at register offset
3040 * Acquires semaphore then writes the data to PHY register at the offset.
3041 * Release the acquired semaphores before exiting.
3043 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3045 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3049 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3050 * @hw: pointer to the HW structure
3051 * @offset: register offset to write to
3052 * @data: data to write at register offset
3054 * Writes the data to PHY register at the offset. Assumes semaphore
3057 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3059 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3063 * e1000_write_phy_reg_page_hv - Write HV PHY register
3064 * @hw: pointer to the HW structure
3065 * @offset: register offset to write to
3066 * @data: data to write at register offset
3068 * Writes the data to PHY register at the offset. Assumes semaphore
3069 * already acquired and page already set.
3071 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3073 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3077 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3078 * @page: page to be accessed
3080 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3084 if (page >= HV_INTC_FC_PAGE_START)
3091 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3092 * @hw: pointer to the HW structure
3093 * @offset: register offset to be read or written
3094 * @data: pointer to the data to be read or written
3095 * @read: determines if operation is read or write
3097 * Reads the PHY register at offset and stores the retreived information
3098 * in data. Assumes semaphore already acquired. Note that the procedure
3099 * to access these regs uses the address port and data port to read/write.
3100 * These accesses done with PHY address 2 and without using pages.
3102 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3103 u16 *data, bool read)
3109 /* This takes care of the difference with desktop vs mobile phy */
3110 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3111 I82578_ADDR_REG : I82577_ADDR_REG;
3112 data_reg = addr_reg + 1;
3114 /* All operations in this function are phy address 2 */
3117 /* masking with 0x3F to remove the page from offset */
3118 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3120 e_dbg("Could not write the Address Offset port register\n");
3124 /* Read or write the data value next */
3126 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3128 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3131 e_dbg("Could not access the Data port register\n");
3137 * e1000_link_stall_workaround_hv - Si workaround
3138 * @hw: pointer to the HW structure
3140 * This function works around a Si bug where the link partner can get
3141 * a link up indication before the PHY does. If small packets are sent
3142 * by the link partner they can be placed in the packet buffer without
3143 * being properly accounted for by the PHY and will stall preventing
3144 * further packets from being received. The workaround is to clear the
3145 * packet buffer after the PHY detects link up.
3147 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3152 if (hw->phy.type != e1000_phy_82578)
3155 /* Do not apply workaround if in PHY loopback bit 14 set */
3156 e1e_rphy(hw, PHY_CONTROL, &data);
3157 if (data & PHY_CONTROL_LB)
3160 /* check if link is up and at 1Gbps */
3161 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3165 data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3166 BM_CS_STATUS_SPEED_MASK;
3168 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3169 BM_CS_STATUS_SPEED_1000))
3174 /* flush the packets in the fifo buffer */
3175 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3176 HV_MUX_DATA_CTRL_FORCE_SPEED);
3180 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3184 * e1000_check_polarity_82577 - Checks the polarity.
3185 * @hw: pointer to the HW structure
3187 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3189 * Polarity is determined based on the PHY specific status register.
3191 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3193 struct e1000_phy_info *phy = &hw->phy;
3197 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3200 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3201 ? e1000_rev_polarity_reversed
3202 : e1000_rev_polarity_normal;
3208 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3209 * @hw: pointer to the HW structure
3211 * Calls the PHY setup function to force speed and duplex.
3213 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3215 struct e1000_phy_info *phy = &hw->phy;
3220 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3224 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3226 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3232 if (phy->autoneg_wait_to_complete) {
3233 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3235 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3241 e_dbg("Link taking longer than expected.\n");
3244 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3252 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3253 * @hw: pointer to the HW structure
3255 * Read PHY status to determine if link is up. If link is up, then
3256 * set/determine 10base-T extended distance and polarity correction. Read
3257 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3258 * determine on the cable length, local and remote receiver.
3260 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3262 struct e1000_phy_info *phy = &hw->phy;
3267 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3272 e_dbg("Phy info is only valid if link is up\n");
3273 return -E1000_ERR_CONFIG;
3276 phy->polarity_correction = true;
3278 ret_val = e1000_check_polarity_82577(hw);
3282 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3286 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3288 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3289 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3290 ret_val = hw->phy.ops.get_cable_length(hw);
3294 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3298 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3299 ? e1000_1000t_rx_status_ok
3300 : e1000_1000t_rx_status_not_ok;
3302 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3303 ? e1000_1000t_rx_status_ok
3304 : e1000_1000t_rx_status_not_ok;
3306 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3307 phy->local_rx = e1000_1000t_rx_status_undefined;
3308 phy->remote_rx = e1000_1000t_rx_status_undefined;
3315 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3316 * @hw: pointer to the HW structure
3318 * Reads the diagnostic status register and verifies result is valid before
3319 * placing it in the phy_cable_length field.
3321 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3323 struct e1000_phy_info *phy = &hw->phy;
3325 u16 phy_data, length;
3327 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3331 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3332 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3334 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3335 return -E1000_ERR_PHY;
3337 phy->cable_length = length;