drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 143
 144 /* EMI Registers */
 145 #define I82579_EMI_ADDR         0x10
 146 #define I82579_EMI_DATA         0x11
 147 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 148
 149 /* Strapping Option Register - RO */
 150 #define E1000_STRAP                     0x0000C
 151 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 152 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 153
 154 /* OEM Bits Phy Register */
 155 #define HV_OEM_BITS            PHY_REG(768, 25)
 156 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 157 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 158 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 159
 160 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 161 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 162
 163 /* KMRN Mode Control */
 164 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 165 #define HV_KMRN_MDIO_SLOW      0x0400
 166
 167 /* KMRN FIFO Control and Status */
 168 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 169 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 170 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 171
 172 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 173 /* Offset 04h HSFSTS */
 174 union ich8_hws_flash_status {
 175         struct ich8_hsfsts {
 176                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 177                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 178                 u16 dael       :1; /* bit 2 Direct Access error Log */
 179                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 180                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 181                 u16 reserved1  :2; /* bit 13:6 Reserved */
 182                 u16 reserved2  :6; /* bit 13:6 Reserved */
 183                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 184                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 185         } hsf_status;
 186         u16 regval;
 187 };
 188
 189 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 190 /* Offset 06h FLCTL */
 191 union ich8_hws_flash_ctrl {
 192         struct ich8_hsflctl {
 193                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 194                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 195                 u16 reserved   :5;   /* 7:3 Reserved  */
 196                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 197                 u16 flockdn    :6;   /* 15:10 Reserved */
 198         } hsf_ctrl;
 199         u16 regval;
 200 };
 201
 202 /* ICH Flash Region Access Permissions */
 203 union ich8_hws_flash_regacc {
 204         struct ich8_flracc {
 205                 u32 grra      :8; /* 0:7 GbE region Read Access */
 206                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 207                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 208                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 209         } hsf_flregacc;
 210         u16 regval;
 211 };
 212
 213 /* ICH Flash Protected Region */
 214 union ich8_flash_protected_range {
 215         struct ich8_pr {
 216                 u32 base:13;     /* 0:12 Protected Range Base */
 217                 u32 reserved1:2; /* 13:14 Reserved */
 218                 u32 rpe:1;       /* 15 Read Protection Enable */
 219                 u32 limit:13;    /* 16:28 Protected Range Limit */
 220                 u32 reserved2:2; /* 29:30 Reserved */
 221                 u32 wpe:1;       /* 31 Write Protection Enable */
 222         } range;
 223         u32 regval;
 224 };
 225
 226 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 227 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 228 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 229 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 230 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 231                                                 u32 offset, u8 byte);
 232 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 233                                          u8 *data);
 234 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 235                                          u16 *data);
 236 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 237                                          u8 size, u16 *data);
 238 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 239 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 240 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 241 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 242 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 244 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 245 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 246 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 247 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 248 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 249 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 250 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 251 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 252 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 253 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 254 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 255 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 256 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 257 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 258
 259 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 260 {
 261         return readw(hw->flash_address + reg);
 262 }
 263
 264 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 265 {
 266         return readl(hw->flash_address + reg);
 267 }
 268
 269 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 270 {
 271         writew(val, hw->flash_address + reg);
 272 }
 273
 274 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 275 {
 276         writel(val, hw->flash_address + reg);
 277 }
 278
 279 #define er16flash(reg)          __er16flash(hw, (reg))
 280 #define er32flash(reg)          __er32flash(hw, (reg))
 281 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 282 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 283
 284 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 285 {
 286         u32 ctrl;
 287
 288         ctrl = er32(CTRL);
 289         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 290         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 291         ew32(CTRL, ctrl);
 292         e1e_flush();
 293         udelay(10);
 294         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 295         ew32(CTRL, ctrl);
 296 }
 297
 298 /**
 299  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 300  *  @hw: pointer to the HW structure
 301  *
 302  *  Initialize family-specific PHY parameters and function pointers.
 303  **/
 304 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 305 {
 306         struct e1000_phy_info *phy = &hw->phy;
 307         u32 fwsm;
 308         s32 ret_val = 0;
 309
 310         phy->addr                     = 1;
 311         phy->reset_delay_us           = 100;
 312
 313         phy->ops.set_page             = e1000_set_page_igp;
 314         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 315         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 316         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 317         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 318         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 319         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 320         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 321         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 322         phy->ops.power_up             = e1000_power_up_phy_copper;
 323         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 324         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 325
 326         /*
 327          * The MAC-PHY interconnect may still be in SMBus mode
 328          * after Sx->S0.  If the manageability engine (ME) is
 329          * disabled, then toggle the LANPHYPC Value bit to force
 330          * the interconnect to PCIe mode.
 331          */
 332         fwsm = er32(FWSM);
 333         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
 334                 e1000_toggle_lanphypc_value_ich8lan(hw);
 335                 msleep(50);
 336
 337                 /*
 338                  * Gate automatic PHY configuration by hardware on
 339                  * non-managed 82579
 340                  */
 341                 if (hw->mac.type == e1000_pch2lan)
 342                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 343         }
 344
 345         /*
 346          * Reset the PHY before any access to it.  Doing so, ensures that
 347          * the PHY is in a known good state before we read/write PHY registers.
 348          * The generic reset is sufficient here, because we haven't determined
 349          * the PHY type yet.
 350          */
 351         ret_val = e1000e_phy_hw_reset_generic(hw);
 352         if (ret_val)
 353                 goto out;
 354
 355         /* Ungate automatic PHY configuration on non-managed 82579 */
 356         if ((hw->mac.type == e1000_pch2lan) &&
 357             !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 358                 usleep_range(10000, 20000);
 359                 e1000_gate_hw_phy_config_ich8lan(hw, false);
 360         }
 361
 362         phy->id = e1000_phy_unknown;
 363         switch (hw->mac.type) {
 364         default:
 365                 ret_val = e1000e_get_phy_id(hw);
 366                 if (ret_val)
 367                         goto out;
 368                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 369                         break;
 370                 /* fall-through */
 371         case e1000_pch2lan:
 372                 /*
 373                  * In case the PHY needs to be in mdio slow mode,
 374                  * set slow mode and try to get the PHY id again.
 375                  */
 376                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 377                 if (ret_val)
 378                         goto out;
 379                 ret_val = e1000e_get_phy_id(hw);
 380                 if (ret_val)
 381                         goto out;
 382                 break;
 383         }
 384         phy->type = e1000e_get_phy_type_from_id(phy->id);
 385
 386         switch (phy->type) {
 387         case e1000_phy_82577:
 388         case e1000_phy_82579:
 389                 phy->ops.check_polarity = e1000_check_polarity_82577;
 390                 phy->ops.force_speed_duplex =
 391                     e1000_phy_force_speed_duplex_82577;
 392                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 393                 phy->ops.get_info = e1000_get_phy_info_82577;
 394                 phy->ops.commit = e1000e_phy_sw_reset;
 395                 break;
 396         case e1000_phy_82578:
 397                 phy->ops.check_polarity = e1000_check_polarity_m88;
 398                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 399                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 400                 phy->ops.get_info = e1000e_get_phy_info_m88;
 401                 break;
 402         default:
 403                 ret_val = -E1000_ERR_PHY;
 404                 break;
 405         }
 406
 407 out:
 408         return ret_val;
 409 }
 410
 411 /**
 412  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 413  *  @hw: pointer to the HW structure
 414  *
 415  *  Initialize family-specific PHY parameters and function pointers.
 416  **/
 417 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 418 {
 419         struct e1000_phy_info *phy = &hw->phy;
 420         s32 ret_val;
 421         u16 i = 0;
 422
 423         phy->addr                       = 1;
 424         phy->reset_delay_us             = 100;
 425
 426         phy->ops.power_up               = e1000_power_up_phy_copper;
 427         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 428
 429         /*
 430          * We may need to do this twice - once for IGP and if that fails,
 431          * we'll set BM func pointers and try again
 432          */
 433         ret_val = e1000e_determine_phy_address(hw);
 434         if (ret_val) {
 435                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 436                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 437                 ret_val = e1000e_determine_phy_address(hw);
 438                 if (ret_val) {
 439                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 440                         return ret_val;
 441                 }
 442         }
 443
 444         phy->id = 0;
 445         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 446                (i++ < 100)) {
 447                 usleep_range(1000, 2000);
 448                 ret_val = e1000e_get_phy_id(hw);
 449                 if (ret_val)
 450                         return ret_val;
 451         }
 452
 453         /* Verify phy id */
 454         switch (phy->id) {
 455         case IGP03E1000_E_PHY_ID:
 456                 phy->type = e1000_phy_igp_3;
 457                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 458                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 459                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 460                 phy->ops.get_info = e1000e_get_phy_info_igp;
 461                 phy->ops.check_polarity = e1000_check_polarity_igp;
 462                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 463                 break;
 464         case IFE_E_PHY_ID:
 465         case IFE_PLUS_E_PHY_ID:
 466         case IFE_C_E_PHY_ID:
 467                 phy->type = e1000_phy_ife;
 468                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 469                 phy->ops.get_info = e1000_get_phy_info_ife;
 470                 phy->ops.check_polarity = e1000_check_polarity_ife;
 471                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 472                 break;
 473         case BME1000_E_PHY_ID:
 474                 phy->type = e1000_phy_bm;
 475                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 476                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 477                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 478                 phy->ops.commit = e1000e_phy_sw_reset;
 479                 phy->ops.get_info = e1000e_get_phy_info_m88;
 480                 phy->ops.check_polarity = e1000_check_polarity_m88;
 481                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 482                 break;
 483         default:
 484                 return -E1000_ERR_PHY;
 485                 break;
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 493  *  @hw: pointer to the HW structure
 494  *
 495  *  Initialize family-specific NVM parameters and function
 496  *  pointers.
 497  **/
 498 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 499 {
 500         struct e1000_nvm_info *nvm = &hw->nvm;
 501         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 502         u32 gfpreg, sector_base_addr, sector_end_addr;
 503         u16 i;
 504
 505         /* Can't read flash registers if the register set isn't mapped. */
 506         if (!hw->flash_address) {
 507                 e_dbg("ERROR: Flash registers not mapped\n");
 508                 return -E1000_ERR_CONFIG;
 509         }
 510
 511         nvm->type = e1000_nvm_flash_sw;
 512
 513         gfpreg = er32flash(ICH_FLASH_GFPREG);
 514
 515         /*
 516          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 517          * Add 1 to sector_end_addr since this sector is included in
 518          * the overall size.
 519          */
 520         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 521         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 522
 523         /* flash_base_addr is byte-aligned */
 524         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 525
 526         /*
 527          * find total size of the NVM, then cut in half since the total
 528          * size represents two separate NVM banks.
 529          */
 530         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 531                                 << FLASH_SECTOR_ADDR_SHIFT;
 532         nvm->flash_bank_size /= 2;
 533         /* Adjust to word count */
 534         nvm->flash_bank_size /= sizeof(u16);
 535
 536         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 537
 538         /* Clear shadow ram */
 539         for (i = 0; i < nvm->word_size; i++) {
 540                 dev_spec->shadow_ram[i].modified = false;
 541                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 542         }
 543
 544         return 0;
 545 }
 546
 547 /**
 548  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 549  *  @hw: pointer to the HW structure
 550  *
 551  *  Initialize family-specific MAC parameters and function
 552  *  pointers.
 553  **/
 554 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 555 {
 556         struct e1000_hw *hw = &adapter->hw;
 557         struct e1000_mac_info *mac = &hw->mac;
 558
 559         /* Set media type function pointer */
 560         hw->phy.media_type = e1000_media_type_copper;
 561
 562         /* Set mta register count */
 563         mac->mta_reg_count = 32;
 564         /* Set rar entry count */
 565         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 566         if (mac->type == e1000_ich8lan)
 567                 mac->rar_entry_count--;
 568         /* FWSM register */
 569         mac->has_fwsm = true;
 570         /* ARC subsystem not supported */
 571         mac->arc_subsystem_valid = false;
 572         /* Adaptive IFS supported */
 573         mac->adaptive_ifs = true;
 574
 575         /* LED operations */
 576         switch (mac->type) {
 577         case e1000_ich8lan:
 578         case e1000_ich9lan:
 579         case e1000_ich10lan:
 580                 /* check management mode */
 581                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 582                 /* ID LED init */
 583                 mac->ops.id_led_init = e1000e_id_led_init;
 584                 /* blink LED */
 585                 mac->ops.blink_led = e1000e_blink_led_generic;
 586                 /* setup LED */
 587                 mac->ops.setup_led = e1000e_setup_led_generic;
 588                 /* cleanup LED */
 589                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 590                 /* turn on/off LED */
 591                 mac->ops.led_on = e1000_led_on_ich8lan;
 592                 mac->ops.led_off = e1000_led_off_ich8lan;
 593                 break;
 594         case e1000_pchlan:
 595         case e1000_pch2lan:
 596                 /* check management mode */
 597                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 598                 /* ID LED init */
 599                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 600                 /* setup LED */
 601                 mac->ops.setup_led = e1000_setup_led_pchlan;
 602                 /* cleanup LED */
 603                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 604                 /* turn on/off LED */
 605                 mac->ops.led_on = e1000_led_on_pchlan;
 606                 mac->ops.led_off = e1000_led_off_pchlan;
 607                 break;
 608         default:
 609                 break;
 610         }
 611
 612         /* Enable PCS Lock-loss workaround for ICH8 */
 613         if (mac->type == e1000_ich8lan)
 614                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 615
 616         /* Gate automatic PHY configuration by hardware on managed 82579 */
 617         if ((mac->type == e1000_pch2lan) &&
 618             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 619                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 620
 621         return 0;
 622 }
 623
 624 /**
 625  *  e1000_set_eee_pchlan - Enable/disable EEE support
 626  *  @hw: pointer to the HW structure
 627  *
 628  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 629  *  the LPI Control register will remain set only if/when link is up.
 630  **/
 631 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 632 {
 633         s32 ret_val = 0;
 634         u16 phy_reg;
 635
 636         if (hw->phy.type != e1000_phy_82579)
 637                 goto out;
 638
 639         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 640         if (ret_val)
 641                 goto out;
 642
 643         if (hw->dev_spec.ich8lan.eee_disable)
 644                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 645         else
 646                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 647
 648         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 649 out:
 650         return ret_val;
 651 }
 652
 653 /**
 654  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 655  *  @hw: pointer to the HW structure
 656  *
 657  *  Checks to see of the link status of the hardware has changed.  If a
 658  *  change in link status has been detected, then we read the PHY registers
 659  *  to get the current speed/duplex if link exists.
 660  **/
 661 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 662 {
 663         struct e1000_mac_info *mac = &hw->mac;
 664         s32 ret_val;
 665         bool link;
 666         u16 phy_reg;
 667
 668         /*
 669          * We only want to go out to the PHY registers to see if Auto-Neg
 670          * has completed and/or if our link status has changed.  The
 671          * get_link_status flag is set upon receiving a Link Status
 672          * Change or Rx Sequence Error interrupt.
 673          */
 674         if (!mac->get_link_status) {
 675                 ret_val = 0;
 676                 goto out;
 677         }
 678
 679         /*
 680          * First we want to see if the MII Status Register reports
 681          * link.  If so, then we want to get the current speed/duplex
 682          * of the PHY.
 683          */
 684         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 685         if (ret_val)
 686                 goto out;
 687
 688         if (hw->mac.type == e1000_pchlan) {
 689                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 690                 if (ret_val)
 691                         goto out;
 692         }
 693
 694         if (!link)
 695                 goto out; /* No link detected */
 696
 697         mac->get_link_status = false;
 698
 699         switch (hw->mac.type) {
 700         case e1000_pch2lan:
 701                 ret_val = e1000_k1_workaround_lv(hw);
 702                 if (ret_val)
 703                         goto out;
 704                 /* fall-thru */
 705         case e1000_pchlan:
 706                 if (hw->phy.type == e1000_phy_82578) {
 707                         ret_val = e1000_link_stall_workaround_hv(hw);
 708                         if (ret_val)
 709                                 goto out;
 710                 }
 711
 712                 /*
 713                  * Workaround for PCHx parts in half-duplex:
 714                  * Set the number of preambles removed from the packet
 715                  * when it is passed from the PHY to the MAC to prevent
 716                  * the MAC from misinterpreting the packet type.
 717                  */
 718                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 719                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 720
 721                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 722                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 723
 724                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 725                 break;
 726         default:
 727                 break;
 728         }
 729
 730         /*
 731          * Check if there was DownShift, must be checked
 732          * immediately after link-up
 733          */
 734         e1000e_check_downshift(hw);
 735
 736         /* Enable/Disable EEE after link up */
 737         ret_val = e1000_set_eee_pchlan(hw);
 738         if (ret_val)
 739                 goto out;
 740
 741         /*
 742          * If we are forcing speed/duplex, then we simply return since
 743          * we have already determined whether we have link or not.
 744          */
 745         if (!mac->autoneg) {
 746                 ret_val = -E1000_ERR_CONFIG;
 747                 goto out;
 748         }
 749
 750         /*
 751          * Auto-Neg is enabled.  Auto Speed Detection takes care
 752          * of MAC speed/duplex configuration.  So we only need to
 753          * configure Collision Distance in the MAC.
 754          */
 755         e1000e_config_collision_dist(hw);
 756
 757         /*
 758          * Configure Flow Control now that Auto-Neg has completed.
 759          * First, we need to restore the desired flow control
 760          * settings because we may have had to re-autoneg with a
 761          * different link partner.
 762          */
 763         ret_val = e1000e_config_fc_after_link_up(hw);
 764         if (ret_val)
 765                 e_dbg("Error configuring flow control\n");
 766
 767 out:
 768         return ret_val;
 769 }
 770
 771 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 772 {
 773         struct e1000_hw *hw = &adapter->hw;
 774         s32 rc;
 775
 776         rc = e1000_init_mac_params_ich8lan(adapter);
 777         if (rc)
 778                 return rc;
 779
 780         rc = e1000_init_nvm_params_ich8lan(hw);
 781         if (rc)
 782                 return rc;
 783
 784         switch (hw->mac.type) {
 785         case e1000_ich8lan:
 786         case e1000_ich9lan:
 787         case e1000_ich10lan:
 788                 rc = e1000_init_phy_params_ich8lan(hw);
 789                 break;
 790         case e1000_pchlan:
 791         case e1000_pch2lan:
 792                 rc = e1000_init_phy_params_pchlan(hw);
 793                 break;
 794         default:
 795                 break;
 796         }
 797         if (rc)
 798                 return rc;
 799
 800         /*
 801          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 802          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 803          */
 804         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 805             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 806              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 807                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 808                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 809
 810                 hw->mac.ops.blink_led = NULL;
 811         }
 812
 813         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 814             (adapter->hw.phy.type != e1000_phy_ife))
 815                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 816
 817         /* Enable workaround for 82579 w/ ME enabled */
 818         if ((adapter->hw.mac.type == e1000_pch2lan) &&
 819             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 820                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
 821
 822         /* Disable EEE by default until IEEE802.3az spec is finalized */
 823         if (adapter->flags2 & FLAG2_HAS_EEE)
 824                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 825
 826         return 0;
 827 }
 828
 829 static DEFINE_MUTEX(nvm_mutex);
 830
 831 /**
 832  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 833  *  @hw: pointer to the HW structure
 834  *
 835  *  Acquires the mutex for performing NVM operations.
 836  **/
 837 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 838 {
 839         mutex_lock(&nvm_mutex);
 840
 841         return 0;
 842 }
 843
 844 /**
 845  *  e1000_release_nvm_ich8lan - Release NVM mutex
 846  *  @hw: pointer to the HW structure
 847  *
 848  *  Releases the mutex used while performing NVM operations.
 849  **/
 850 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 851 {
 852         mutex_unlock(&nvm_mutex);
 853 }
 854
 855 /**
 856  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 857  *  @hw: pointer to the HW structure
 858  *
 859  *  Acquires the software control flag for performing PHY and select
 860  *  MAC CSR accesses.
 861  **/
 862 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 863 {
 864         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 865         s32 ret_val = 0;
 866
 867         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
 868                              &hw->adapter->state)) {
 869                 e_dbg("contention for Phy access\n");
 870                 return -E1000_ERR_PHY;
 871         }
 872
 873         while (timeout) {
 874                 extcnf_ctrl = er32(EXTCNF_CTRL);
 875                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 876                         break;
 877
 878                 mdelay(1);
 879                 timeout--;
 880         }
 881
 882         if (!timeout) {
 883                 e_dbg("SW has already locked the resource.\n");
 884                 ret_val = -E1000_ERR_CONFIG;
 885                 goto out;
 886         }
 887
 888         timeout = SW_FLAG_TIMEOUT;
 889
 890         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 891         ew32(EXTCNF_CTRL, extcnf_ctrl);
 892
 893         while (timeout) {
 894                 extcnf_ctrl = er32(EXTCNF_CTRL);
 895                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 896                         break;
 897
 898                 mdelay(1);
 899                 timeout--;
 900         }
 901
 902         if (!timeout) {
 903                 e_dbg("Failed to acquire the semaphore, FW or HW has it: "
 904                       "FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
 905                       er32(FWSM), extcnf_ctrl);
 906                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 907                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 908                 ret_val = -E1000_ERR_CONFIG;
 909                 goto out;
 910         }
 911
 912 out:
 913         if (ret_val)
 914                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 915
 916         return ret_val;
 917 }
 918
 919 /**
 920  *  e1000_release_swflag_ich8lan - Release software control flag
 921  *  @hw: pointer to the HW structure
 922  *
 923  *  Releases the software control flag for performing PHY and select
 924  *  MAC CSR accesses.
 925  **/
 926 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 927 {
 928         u32 extcnf_ctrl;
 929
 930         extcnf_ctrl = er32(EXTCNF_CTRL);
 931
 932         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 933                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 934                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 935         } else {
 936                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 937         }
 938
 939         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 940 }
 941
 942 /**
 943  *  e1000_check_mng_mode_ich8lan - Checks management mode
 944  *  @hw: pointer to the HW structure
 945  *
 946  *  This checks if the adapter has any manageability enabled.
 947  *  This is a function pointer entry point only called by read/write
 948  *  routines for the PHY and NVM parts.
 949  **/
 950 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 951 {
 952         u32 fwsm;
 953
 954         fwsm = er32(FWSM);
 955         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 956                ((fwsm & E1000_FWSM_MODE_MASK) ==
 957                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 958 }
 959
 960 /**
 961  *  e1000_check_mng_mode_pchlan - Checks management mode
 962  *  @hw: pointer to the HW structure
 963  *
 964  *  This checks if the adapter has iAMT enabled.
 965  *  This is a function pointer entry point only called by read/write
 966  *  routines for the PHY and NVM parts.
 967  **/
 968 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 969 {
 970         u32 fwsm;
 971
 972         fwsm = er32(FWSM);
 973         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 974                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 975 }
 976
 977 /**
 978  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 979  *  @hw: pointer to the HW structure
 980  *
 981  *  Checks if firmware is blocking the reset of the PHY.
 982  *  This is a function pointer entry point only called by
 983  *  reset routines.
 984  **/
 985 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 986 {
 987         u32 fwsm;
 988
 989         fwsm = er32(FWSM);
 990
 991         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 992 }
 993
 994 /**
 995  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 996  *  @hw: pointer to the HW structure
 997  *
 998  *  Assumes semaphore already acquired.
 999  *
1000  **/
1001 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1002 {
1003         u16 phy_data;
1004         u32 strap = er32(STRAP);
1005         s32 ret_val = 0;
1006
1007         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1008
1009         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1010         if (ret_val)
1011                 goto out;
1012
1013         phy_data &= ~HV_SMB_ADDR_MASK;
1014         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1015         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1016         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1017
1018 out:
1019         return ret_val;
1020 }
1021
1022 /**
1023  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1024  *  @hw:   pointer to the HW structure
1025  *
1026  *  SW should configure the LCD from the NVM extended configuration region
1027  *  as a workaround for certain parts.
1028  **/
1029 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1030 {
1031         struct e1000_phy_info *phy = &hw->phy;
1032         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1033         s32 ret_val = 0;
1034         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1035
1036         /*
1037          * Initialize the PHY from the NVM on ICH platforms.  This
1038          * is needed due to an issue where the NVM configuration is
1039          * not properly autoloaded after power transitions.
1040          * Therefore, after each PHY reset, we will load the
1041          * configuration data out of the NVM manually.
1042          */
1043         switch (hw->mac.type) {
1044         case e1000_ich8lan:
1045                 if (phy->type != e1000_phy_igp_3)
1046                         return ret_val;
1047
1048                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1049                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1050                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1051                         break;
1052                 }
1053                 /* Fall-thru */
1054         case e1000_pchlan:
1055         case e1000_pch2lan:
1056                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1057                 break;
1058         default:
1059                 return ret_val;
1060         }
1061
1062         ret_val = hw->phy.ops.acquire(hw);
1063         if (ret_val)
1064                 return ret_val;
1065
1066         data = er32(FEXTNVM);
1067         if (!(data & sw_cfg_mask))
1068                 goto out;
1069
1070         /*
1071          * Make sure HW does not configure LCD from PHY
1072          * extended configuration before SW configuration
1073          */
1074         data = er32(EXTCNF_CTRL);
1075         if (!(hw->mac.type == e1000_pch2lan)) {
1076                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1077                         goto out;
1078         }
1079
1080         cnf_size = er32(EXTCNF_SIZE);
1081         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1082         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1083         if (!cnf_size)
1084                 goto out;
1085
1086         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1087         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1088
1089         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1090             (hw->mac.type == e1000_pchlan)) ||
1091              (hw->mac.type == e1000_pch2lan)) {
1092                 /*
1093                  * HW configures the SMBus address and LEDs when the
1094                  * OEM and LCD Write Enable bits are set in the NVM.
1095                  * When both NVM bits are cleared, SW will configure
1096                  * them instead.
1097                  */
1098                 ret_val = e1000_write_smbus_addr(hw);
1099                 if (ret_val)
1100                         goto out;
1101
1102                 data = er32(LEDCTL);
1103                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1104                                                         (u16)data);
1105                 if (ret_val)
1106                         goto out;
1107         }
1108
1109         /* Configure LCD from extended configuration region. */
1110
1111         /* cnf_base_addr is in DWORD */
1112         word_addr = (u16)(cnf_base_addr << 1);
1113
1114         for (i = 0; i < cnf_size; i++) {
1115                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1116                                          &reg_data);
1117                 if (ret_val)
1118                         goto out;
1119
1120                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1121                                          1, &reg_addr);
1122                 if (ret_val)
1123                         goto out;
1124
1125                 /* Save off the PHY page for future writes. */
1126                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1127                         phy_page = reg_data;
1128                         continue;
1129                 }
1130
1131                 reg_addr &= PHY_REG_MASK;
1132                 reg_addr |= phy_page;
1133
1134                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1135                                                     reg_data);
1136                 if (ret_val)
1137                         goto out;
1138         }
1139
1140 out:
1141         hw->phy.ops.release(hw);
1142         return ret_val;
1143 }
1144
1145 /**
1146  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1147  *  @hw:   pointer to the HW structure
1148  *  @link: link up bool flag
1149  *
1150  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1151  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1152  *  If link is down, the function will restore the default K1 setting located
1153  *  in the NVM.
1154  **/
1155 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1156 {
1157         s32 ret_val = 0;
1158         u16 status_reg = 0;
1159         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1160
1161         if (hw->mac.type != e1000_pchlan)
1162                 goto out;
1163
1164         /* Wrap the whole flow with the sw flag */
1165         ret_val = hw->phy.ops.acquire(hw);
1166         if (ret_val)
1167                 goto out;
1168
1169         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1170         if (link) {
1171                 if (hw->phy.type == e1000_phy_82578) {
1172                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1173                                                                   &status_reg);
1174                         if (ret_val)
1175                                 goto release;
1176
1177                         status_reg &= BM_CS_STATUS_LINK_UP |
1178                                       BM_CS_STATUS_RESOLVED |
1179                                       BM_CS_STATUS_SPEED_MASK;
1180
1181                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1182                                            BM_CS_STATUS_RESOLVED |
1183                                            BM_CS_STATUS_SPEED_1000))
1184                                 k1_enable = false;
1185                 }
1186
1187                 if (hw->phy.type == e1000_phy_82577) {
1188                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1189                                                                   &status_reg);
1190                         if (ret_val)
1191                                 goto release;
1192
1193                         status_reg &= HV_M_STATUS_LINK_UP |
1194                                       HV_M_STATUS_AUTONEG_COMPLETE |
1195                                       HV_M_STATUS_SPEED_MASK;
1196
1197                         if (status_reg == (HV_M_STATUS_LINK_UP |
1198                                            HV_M_STATUS_AUTONEG_COMPLETE |
1199                                            HV_M_STATUS_SPEED_1000))
1200                                 k1_enable = false;
1201                 }
1202
1203                 /* Link stall fix for link up */
1204                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1205                                                            0x0100);
1206                 if (ret_val)
1207                         goto release;
1208
1209         } else {
1210                 /* Link stall fix for link down */
1211                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1212                                                            0x4100);
1213                 if (ret_val)
1214                         goto release;
1215         }
1216
1217         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1218
1219 release:
1220         hw->phy.ops.release(hw);
1221 out:
1222         return ret_val;
1223 }
1224
1225 /**
1226  *  e1000_configure_k1_ich8lan - Configure K1 power state
1227  *  @hw: pointer to the HW structure
1228  *  @enable: K1 state to configure
1229  *
1230  *  Configure the K1 power state based on the provided parameter.
1231  *  Assumes semaphore already acquired.
1232  *
1233  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1234  **/
1235 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1236 {
1237         s32 ret_val = 0;
1238         u32 ctrl_reg = 0;
1239         u32 ctrl_ext = 0;
1240         u32 reg = 0;
1241         u16 kmrn_reg = 0;
1242
1243         ret_val = e1000e_read_kmrn_reg_locked(hw,
1244                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1245                                              &kmrn_reg);
1246         if (ret_val)
1247                 goto out;
1248
1249         if (k1_enable)
1250                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1251         else
1252                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1253
1254         ret_val = e1000e_write_kmrn_reg_locked(hw,
1255                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1256                                               kmrn_reg);
1257         if (ret_val)
1258                 goto out;
1259
1260         udelay(20);
1261         ctrl_ext = er32(CTRL_EXT);
1262         ctrl_reg = er32(CTRL);
1263
1264         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1265         reg |= E1000_CTRL_FRCSPD;
1266         ew32(CTRL, reg);
1267
1268         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1269         e1e_flush();
1270         udelay(20);
1271         ew32(CTRL, ctrl_reg);
1272         ew32(CTRL_EXT, ctrl_ext);
1273         e1e_flush();
1274         udelay(20);
1275
1276 out:
1277         return ret_val;
1278 }
1279
1280 /**
1281  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1282  *  @hw:       pointer to the HW structure
1283  *  @d0_state: boolean if entering d0 or d3 device state
1284  *
1285  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1286  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1287  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1288  **/
1289 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1290 {
1291         s32 ret_val = 0;
1292         u32 mac_reg;
1293         u16 oem_reg;
1294
1295         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1296                 return ret_val;
1297
1298         ret_val = hw->phy.ops.acquire(hw);
1299         if (ret_val)
1300                 return ret_val;
1301
1302         if (!(hw->mac.type == e1000_pch2lan)) {
1303                 mac_reg = er32(EXTCNF_CTRL);
1304                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1305                         goto out;
1306         }
1307
1308         mac_reg = er32(FEXTNVM);
1309         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1310                 goto out;
1311
1312         mac_reg = er32(PHY_CTRL);
1313
1314         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1315         if (ret_val)
1316                 goto out;
1317
1318         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1319
1320         if (d0_state) {
1321                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1322                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1323
1324                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1325                         oem_reg |= HV_OEM_BITS_LPLU;
1326
1327                 /* Set Restart auto-neg to activate the bits */
1328                 if (!e1000_check_reset_block(hw))
1329                         oem_reg |= HV_OEM_BITS_RESTART_AN;
1330         } else {
1331                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1332                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1333                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1334
1335                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1336                                E1000_PHY_CTRL_NOND0A_LPLU))
1337                         oem_reg |= HV_OEM_BITS_LPLU;
1338         }
1339
1340         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1341
1342 out:
1343         hw->phy.ops.release(hw);
1344
1345         return ret_val;
1346 }
1347
1348
1349 /**
1350  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1351  *  @hw:   pointer to the HW structure
1352  **/
1353 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1354 {
1355         s32 ret_val;
1356         u16 data;
1357
1358         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1359         if (ret_val)
1360                 return ret_val;
1361
1362         data |= HV_KMRN_MDIO_SLOW;
1363
1364         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1365
1366         return ret_val;
1367 }
1368
1369 /**
1370  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1371  *  done after every PHY reset.
1372  **/
1373 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1374 {
1375         s32 ret_val = 0;
1376         u16 phy_data;
1377
1378         if (hw->mac.type != e1000_pchlan)
1379                 return ret_val;
1380
1381         /* Set MDIO slow mode before any other MDIO access */
1382         if (hw->phy.type == e1000_phy_82577) {
1383                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1384                 if (ret_val)
1385                         goto out;
1386         }
1387
1388         if (((hw->phy.type == e1000_phy_82577) &&
1389              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1390             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1391                 /* Disable generation of early preamble */
1392                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1393                 if (ret_val)
1394                         return ret_val;
1395
1396                 /* Preamble tuning for SSC */
1397                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1398                 if (ret_val)
1399                         return ret_val;
1400         }
1401
1402         if (hw->phy.type == e1000_phy_82578) {
1403                 /*
1404                  * Return registers to default by doing a soft reset then
1405                  * writing 0x3140 to the control register.
1406                  */
1407                 if (hw->phy.revision < 2) {
1408                         e1000e_phy_sw_reset(hw);
1409                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1410                 }
1411         }
1412
1413         /* Select page 0 */
1414         ret_val = hw->phy.ops.acquire(hw);
1415         if (ret_val)
1416                 return ret_val;
1417
1418         hw->phy.addr = 1;
1419         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1420         hw->phy.ops.release(hw);
1421         if (ret_val)
1422                 goto out;
1423
1424         /*
1425          * Configure the K1 Si workaround during phy reset assuming there is
1426          * link so that it disables K1 if link is in 1Gbps.
1427          */
1428         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1429         if (ret_val)
1430                 goto out;
1431
1432         /* Workaround for link disconnects on a busy hub in half duplex */
1433         ret_val = hw->phy.ops.acquire(hw);
1434         if (ret_val)
1435                 goto out;
1436         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1437         if (ret_val)
1438                 goto release;
1439         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1440                                                phy_data & 0x00FF);
1441 release:
1442         hw->phy.ops.release(hw);
1443 out:
1444         return ret_val;
1445 }
1446
1447 /**
1448  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1449  *  @hw:   pointer to the HW structure
1450  **/
1451 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1452 {
1453         u32 mac_reg;
1454         u16 i, phy_reg = 0;
1455         s32 ret_val;
1456
1457         ret_val = hw->phy.ops.acquire(hw);
1458         if (ret_val)
1459                 return;
1460         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1461         if (ret_val)
1462                 goto release;
1463
1464         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1465         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1466                 mac_reg = er32(RAL(i));
1467                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1468                                            (u16)(mac_reg & 0xFFFF));
1469                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1470                                            (u16)((mac_reg >> 16) & 0xFFFF));
1471
1472                 mac_reg = er32(RAH(i));
1473                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1474                                            (u16)(mac_reg & 0xFFFF));
1475                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1476                                            (u16)((mac_reg & E1000_RAH_AV)
1477                                                  >> 16));
1478         }
1479
1480         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1481
1482 release:
1483         hw->phy.ops.release(hw);
1484 }
1485
1486 /**
1487  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1488  *  with 82579 PHY
1489  *  @hw: pointer to the HW structure
1490  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1491  **/
1492 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1493 {
1494         s32 ret_val = 0;
1495         u16 phy_reg, data;
1496         u32 mac_reg;
1497         u16 i;
1498
1499         if (hw->mac.type != e1000_pch2lan)
1500                 goto out;
1501
1502         /* disable Rx path while enabling/disabling workaround */
1503         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1504         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1505         if (ret_val)
1506                 goto out;
1507
1508         if (enable) {
1509                 /*
1510                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1511                  * SHRAL/H) and initial CRC values to the MAC
1512                  */
1513                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1514                         u8 mac_addr[ETH_ALEN] = {0};
1515                         u32 addr_high, addr_low;
1516
1517                         addr_high = er32(RAH(i));
1518                         if (!(addr_high & E1000_RAH_AV))
1519                                 continue;
1520                         addr_low = er32(RAL(i));
1521                         mac_addr[0] = (addr_low & 0xFF);
1522                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1523                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1524                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1525                         mac_addr[4] = (addr_high & 0xFF);
1526                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1527
1528                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1529                 }
1530
1531                 /* Write Rx addresses to the PHY */
1532                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1533
1534                 /* Enable jumbo frame workaround in the MAC */
1535                 mac_reg = er32(FFLT_DBG);
1536                 mac_reg &= ~(1 << 14);
1537                 mac_reg |= (7 << 15);
1538                 ew32(FFLT_DBG, mac_reg);
1539
1540                 mac_reg = er32(RCTL);
1541                 mac_reg |= E1000_RCTL_SECRC;
1542                 ew32(RCTL, mac_reg);
1543
1544                 ret_val = e1000e_read_kmrn_reg(hw,
1545                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1546                                                 &data);
1547                 if (ret_val)
1548                         goto out;
1549                 ret_val = e1000e_write_kmrn_reg(hw,
1550                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1551                                                 data | (1 << 0));
1552                 if (ret_val)
1553                         goto out;
1554                 ret_val = e1000e_read_kmrn_reg(hw,
1555                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1556                                                 &data);
1557                 if (ret_val)
1558                         goto out;
1559                 data &= ~(0xF << 8);
1560                 data |= (0xB << 8);
1561                 ret_val = e1000e_write_kmrn_reg(hw,
1562                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1563                                                 data);
1564                 if (ret_val)
1565                         goto out;
1566
1567                 /* Enable jumbo frame workaround in the PHY */
1568                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1569                 data &= ~(0x7F << 5);
1570                 data |= (0x37 << 5);
1571                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1572                 if (ret_val)
1573                         goto out;
1574                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1575                 data &= ~(1 << 13);
1576                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1577                 if (ret_val)
1578                         goto out;
1579                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1580                 data &= ~(0x3FF << 2);
1581                 data |= (0x1A << 2);
1582                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1583                 if (ret_val)
1584                         goto out;
1585                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1586                 if (ret_val)
1587                         goto out;
1588                 e1e_rphy(hw, HV_PM_CTRL, &data);
1589                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1590                 if (ret_val)
1591                         goto out;
1592         } else {
1593                 /* Write MAC register values back to h/w defaults */
1594                 mac_reg = er32(FFLT_DBG);
1595                 mac_reg &= ~(0xF << 14);
1596                 ew32(FFLT_DBG, mac_reg);
1597
1598                 mac_reg = er32(RCTL);
1599                 mac_reg &= ~E1000_RCTL_SECRC;
1600                 ew32(RCTL, mac_reg);
1601
1602                 ret_val = e1000e_read_kmrn_reg(hw,
1603                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1604                                                 &data);
1605                 if (ret_val)
1606                         goto out;
1607                 ret_val = e1000e_write_kmrn_reg(hw,
1608                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1609                                                 data & ~(1 << 0));
1610                 if (ret_val)
1611                         goto out;
1612                 ret_val = e1000e_read_kmrn_reg(hw,
1613                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1614                                                 &data);
1615                 if (ret_val)
1616                         goto out;
1617                 data &= ~(0xF << 8);
1618                 data |= (0xB << 8);
1619                 ret_val = e1000e_write_kmrn_reg(hw,
1620                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1621                                                 data);
1622                 if (ret_val)
1623                         goto out;
1624
1625                 /* Write PHY register values back to h/w defaults */
1626                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1627                 data &= ~(0x7F << 5);
1628                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1629                 if (ret_val)
1630                         goto out;
1631                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1632                 data |= (1 << 13);
1633                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1634                 if (ret_val)
1635                         goto out;
1636                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1637                 data &= ~(0x3FF << 2);
1638                 data |= (0x8 << 2);
1639                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1640                 if (ret_val)
1641                         goto out;
1642                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1643                 if (ret_val)
1644                         goto out;
1645                 e1e_rphy(hw, HV_PM_CTRL, &data);
1646                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1647                 if (ret_val)
1648                         goto out;
1649         }
1650
1651         /* re-enable Rx path after enabling/disabling workaround */
1652         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1653
1654 out:
1655         return ret_val;
1656 }
1657
1658 /**
1659  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1660  *  done after every PHY reset.
1661  **/
1662 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1663 {
1664         s32 ret_val = 0;
1665
1666         if (hw->mac.type != e1000_pch2lan)
1667                 goto out;
1668
1669         /* Set MDIO slow mode before any other MDIO access */
1670         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1671
1672 out:
1673         return ret_val;
1674 }
1675
1676 /**
1677  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1678  *  @hw:   pointer to the HW structure
1679  *
1680  *  Workaround to set the K1 beacon duration for 82579 parts
1681  **/
1682 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1683 {
1684         s32 ret_val = 0;
1685         u16 status_reg = 0;
1686         u32 mac_reg;
1687         u16 phy_reg;
1688
1689         if (hw->mac.type != e1000_pch2lan)
1690                 goto out;
1691
1692         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1693         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1694         if (ret_val)
1695                 goto out;
1696
1697         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1698             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1699                 mac_reg = er32(FEXTNVM4);
1700                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1701
1702                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1703                 if (ret_val)
1704                         goto out;
1705
1706                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1707                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1708                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1709                 } else {
1710                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1711                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1712                 }
1713                 ew32(FEXTNVM4, mac_reg);
1714                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1715         }
1716
1717 out:
1718         return ret_val;
1719 }
1720
1721 /**
1722  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1723  *  @hw:   pointer to the HW structure
1724  *  @gate: boolean set to true to gate, false to ungate
1725  *
1726  *  Gate/ungate the automatic PHY configuration via hardware; perform
1727  *  the configuration via software instead.
1728  **/
1729 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1730 {
1731         u32 extcnf_ctrl;
1732
1733         if (hw->mac.type != e1000_pch2lan)
1734                 return;
1735
1736         extcnf_ctrl = er32(EXTCNF_CTRL);
1737
1738         if (gate)
1739                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1740         else
1741                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1742
1743         ew32(EXTCNF_CTRL, extcnf_ctrl);
1744         return;
1745 }
1746
1747 /**
1748  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1749  *  @hw: pointer to the HW structure
1750  *
1751  *  Check the appropriate indication the MAC has finished configuring the
1752  *  PHY after a software reset.
1753  **/
1754 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1755 {
1756         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1757
1758         /* Wait for basic configuration completes before proceeding */
1759         do {
1760                 data = er32(STATUS);
1761                 data &= E1000_STATUS_LAN_INIT_DONE;
1762                 udelay(100);
1763         } while ((!data) && --loop);
1764
1765         /*
1766          * If basic configuration is incomplete before the above loop
1767          * count reaches 0, loading the configuration from NVM will
1768          * leave the PHY in a bad state possibly resulting in no link.
1769          */
1770         if (loop == 0)
1771                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1772
1773         /* Clear the Init Done bit for the next init event */
1774         data = er32(STATUS);
1775         data &= ~E1000_STATUS_LAN_INIT_DONE;
1776         ew32(STATUS, data);
1777 }
1778
1779 /**
1780  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1781  *  @hw: pointer to the HW structure
1782  **/
1783 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1784 {
1785         s32 ret_val = 0;
1786         u16 reg;
1787
1788         if (e1000_check_reset_block(hw))
1789                 goto out;
1790
1791         /* Allow time for h/w to get to quiescent state after reset */
1792         usleep_range(10000, 20000);
1793
1794         /* Perform any necessary post-reset workarounds */
1795         switch (hw->mac.type) {
1796         case e1000_pchlan:
1797                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1798                 if (ret_val)
1799                         goto out;
1800                 break;
1801         case e1000_pch2lan:
1802                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1803                 if (ret_val)
1804                         goto out;
1805                 break;
1806         default:
1807                 break;
1808         }
1809
1810         /* Clear the host wakeup bit after lcd reset */
1811         if (hw->mac.type >= e1000_pchlan) {
1812                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1813                 reg &= ~BM_WUC_HOST_WU_BIT;
1814                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1815         }
1816
1817         /* Configure the LCD with the extended configuration region in NVM */
1818         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1819         if (ret_val)
1820                 goto out;
1821
1822         /* Configure the LCD with the OEM bits in NVM */
1823         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1824
1825         if (hw->mac.type == e1000_pch2lan) {
1826                 /* Ungate automatic PHY configuration on non-managed 82579 */
1827                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1828                         usleep_range(10000, 20000);
1829                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1830                 }
1831
1832                 /* Set EEE LPI Update Timer to 200usec */
1833                 ret_val = hw->phy.ops.acquire(hw);
1834                 if (ret_val)
1835                         goto out;
1836                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1837                                                        I82579_LPI_UPDATE_TIMER);
1838                 if (ret_val)
1839                         goto release;
1840                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1841                                                        0x1387);
1842 release:
1843                 hw->phy.ops.release(hw);
1844         }
1845
1846 out:
1847         return ret_val;
1848 }
1849
1850 /**
1851  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1852  *  @hw: pointer to the HW structure
1853  *
1854  *  Resets the PHY
1855  *  This is a function pointer entry point called by drivers
1856  *  or other shared routines.
1857  **/
1858 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1859 {
1860         s32 ret_val = 0;
1861
1862         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1863         if ((hw->mac.type == e1000_pch2lan) &&
1864             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1865                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1866
1867         ret_val = e1000e_phy_hw_reset_generic(hw);
1868         if (ret_val)
1869                 goto out;
1870
1871         ret_val = e1000_post_phy_reset_ich8lan(hw);
1872
1873 out:
1874         return ret_val;
1875 }
1876
1877 /**
1878  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1879  *  @hw: pointer to the HW structure
1880  *  @active: true to enable LPLU, false to disable
1881  *
1882  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1883  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1884  *  the phy speed. This function will manually set the LPLU bit and restart
1885  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1886  *  since it configures the same bit.
1887  **/
1888 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1889 {
1890         s32 ret_val = 0;
1891         u16 oem_reg;
1892
1893         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1894         if (ret_val)
1895                 goto out;
1896
1897         if (active)
1898                 oem_reg |= HV_OEM_BITS_LPLU;
1899         else
1900                 oem_reg &= ~HV_OEM_BITS_LPLU;
1901
1902         oem_reg |= HV_OEM_BITS_RESTART_AN;
1903         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1904
1905 out:
1906         return ret_val;
1907 }
1908
1909 /**
1910  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1911  *  @hw: pointer to the HW structure
1912  *  @active: true to enable LPLU, false to disable
1913  *
1914  *  Sets the LPLU D0 state according to the active flag.  When
1915  *  activating LPLU this function also disables smart speed
1916  *  and vice versa.  LPLU will not be activated unless the
1917  *  device autonegotiation advertisement meets standards of
1918  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1919  *  This is a function pointer entry point only called by
1920  *  PHY setup routines.
1921  **/
1922 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1923 {
1924         struct e1000_phy_info *phy = &hw->phy;
1925         u32 phy_ctrl;
1926         s32 ret_val = 0;
1927         u16 data;
1928
1929         if (phy->type == e1000_phy_ife)
1930                 return ret_val;
1931
1932         phy_ctrl = er32(PHY_CTRL);
1933
1934         if (active) {
1935                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1936                 ew32(PHY_CTRL, phy_ctrl);
1937
1938                 if (phy->type != e1000_phy_igp_3)
1939                         return 0;
1940
1941                 /*
1942                  * Call gig speed drop workaround on LPLU before accessing
1943                  * any PHY registers
1944                  */
1945                 if (hw->mac.type == e1000_ich8lan)
1946                         e1000e_gig_downshift_workaround_ich8lan(hw);
1947
1948                 /* When LPLU is enabled, we should disable SmartSpeed */
1949                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1950                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1951                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1952                 if (ret_val)
1953                         return ret_val;
1954         } else {
1955                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1956                 ew32(PHY_CTRL, phy_ctrl);
1957
1958                 if (phy->type != e1000_phy_igp_3)
1959                         return 0;
1960
1961                 /*
1962                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1963                  * during Dx states where the power conservation is most
1964                  * important.  During driver activity we should enable
1965                  * SmartSpeed, so performance is maintained.
1966                  */
1967                 if (phy->smart_speed == e1000_smart_speed_on) {
1968                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1969                                            &data);
1970                         if (ret_val)
1971                                 return ret_val;
1972
1973                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1974                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1975                                            data);
1976                         if (ret_val)
1977                                 return ret_val;
1978                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1979                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1980                                            &data);
1981                         if (ret_val)
1982                                 return ret_val;
1983
1984                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1985                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1986                                            data);
1987                         if (ret_val)
1988                                 return ret_val;
1989                 }
1990         }
1991
1992         return 0;
1993 }
1994
1995 /**
1996  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1997  *  @hw: pointer to the HW structure
1998  *  @active: true to enable LPLU, false to disable
1999  *
2000  *  Sets the LPLU D3 state according to the active flag.  When
2001  *  activating LPLU this function also disables smart speed
2002  *  and vice versa.  LPLU will not be activated unless the
2003  *  device autonegotiation advertisement meets standards of
2004  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2005  *  This is a function pointer entry point only called by
2006  *  PHY setup routines.
2007  **/
2008 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2009 {
2010         struct e1000_phy_info *phy = &hw->phy;
2011         u32 phy_ctrl;
2012         s32 ret_val;
2013         u16 data;
2014
2015         phy_ctrl = er32(PHY_CTRL);
2016
2017         if (!active) {
2018                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2019                 ew32(PHY_CTRL, phy_ctrl);
2020
2021                 if (phy->type != e1000_phy_igp_3)
2022                         return 0;
2023
2024                 /*
2025                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2026                  * during Dx states where the power conservation is most
2027                  * important.  During driver activity we should enable
2028                  * SmartSpeed, so performance is maintained.
2029                  */
2030                 if (phy->smart_speed == e1000_smart_speed_on) {
2031                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2032                                            &data);
2033                         if (ret_val)
2034                                 return ret_val;
2035
2036                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2037                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2038                                            data);
2039                         if (ret_val)
2040                                 return ret_val;
2041                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2042                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2043                                            &data);
2044                         if (ret_val)
2045                                 return ret_val;
2046
2047                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2048                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2049                                            data);
2050                         if (ret_val)
2051                                 return ret_val;
2052                 }
2053         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2054                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2055                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2056                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2057                 ew32(PHY_CTRL, phy_ctrl);
2058
2059                 if (phy->type != e1000_phy_igp_3)
2060                         return 0;
2061
2062                 /*
2063                  * Call gig speed drop workaround on LPLU before accessing
2064                  * any PHY registers
2065                  */
2066                 if (hw->mac.type == e1000_ich8lan)
2067                         e1000e_gig_downshift_workaround_ich8lan(hw);
2068
2069                 /* When LPLU is enabled, we should disable SmartSpeed */
2070                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2071                 if (ret_val)
2072                         return ret_val;
2073
2074                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2075                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2076         }
2077
2078         return 0;
2079 }
2080
2081 /**
2082  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2083  *  @hw: pointer to the HW structure
2084  *  @bank:  pointer to the variable that returns the active bank
2085  *
2086  *  Reads signature byte from the NVM using the flash access registers.
2087  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2088  **/
2089 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2090 {
2091         u32 eecd;
2092         struct e1000_nvm_info *nvm = &hw->nvm;
2093         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2094         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2095         u8 sig_byte = 0;
2096         s32 ret_val = 0;
2097
2098         switch (hw->mac.type) {
2099         case e1000_ich8lan:
2100         case e1000_ich9lan:
2101                 eecd = er32(EECD);
2102                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2103                     E1000_EECD_SEC1VAL_VALID_MASK) {
2104                         if (eecd & E1000_EECD_SEC1VAL)
2105                                 *bank = 1;
2106                         else
2107                                 *bank = 0;
2108
2109                         return 0;
2110                 }
2111                 e_dbg("Unable to determine valid NVM bank via EEC - "
2112                        "reading flash signature\n");
2113                 /* fall-thru */
2114         default:
2115                 /* set bank to 0 in case flash read fails */
2116                 *bank = 0;
2117
2118                 /* Check bank 0 */
2119                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2120                                                         &sig_byte);
2121                 if (ret_val)
2122                         return ret_val;
2123                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2124                     E1000_ICH_NVM_SIG_VALUE) {
2125                         *bank = 0;
2126                         return 0;
2127                 }
2128
2129                 /* Check bank 1 */
2130                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2131                                                         bank1_offset,
2132                                                         &sig_byte);
2133                 if (ret_val)
2134                         return ret_val;
2135                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2136                     E1000_ICH_NVM_SIG_VALUE) {
2137                         *bank = 1;
2138                         return 0;
2139                 }
2140
2141                 e_dbg("ERROR: No valid NVM bank present\n");
2142                 return -E1000_ERR_NVM;
2143         }
2144
2145         return 0;
2146 }
2147
2148 /**
2149  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2150  *  @hw: pointer to the HW structure
2151  *  @offset: The offset (in bytes) of the word(s) to read.
2152  *  @words: Size of data to read in words
2153  *  @data: Pointer to the word(s) to read at offset.
2154  *
2155  *  Reads a word(s) from the NVM using the flash access registers.
2156  **/
2157 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2158                                   u16 *data)
2159 {
2160         struct e1000_nvm_info *nvm = &hw->nvm;
2161         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2162         u32 act_offset;
2163         s32 ret_val = 0;
2164         u32 bank = 0;
2165         u16 i, word;
2166
2167         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2168             (words == 0)) {
2169                 e_dbg("nvm parameter(s) out of bounds\n");
2170                 ret_val = -E1000_ERR_NVM;
2171                 goto out;
2172         }
2173
2174         nvm->ops.acquire(hw);
2175
2176         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2177         if (ret_val) {
2178                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2179                 bank = 0;
2180         }
2181
2182         act_offset = (bank) ? nvm->flash_bank_size : 0;
2183         act_offset += offset;
2184
2185         ret_val = 0;
2186         for (i = 0; i < words; i++) {
2187                 if (dev_spec->shadow_ram[offset+i].modified) {
2188                         data[i] = dev_spec->shadow_ram[offset+i].value;
2189                 } else {
2190                         ret_val = e1000_read_flash_word_ich8lan(hw,
2191                                                                 act_offset + i,
2192                                                                 &word);
2193                         if (ret_val)
2194                                 break;
2195                         data[i] = word;
2196                 }
2197         }
2198
2199         nvm->ops.release(hw);
2200
2201 out:
2202         if (ret_val)
2203                 e_dbg("NVM read error: %d\n", ret_val);
2204
2205         return ret_val;
2206 }
2207
2208 /**
2209  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2210  *  @hw: pointer to the HW structure
2211  *
2212  *  This function does initial flash setup so that a new read/write/erase cycle
2213  *  can be started.
2214  **/
2215 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2216 {
2217         union ich8_hws_flash_status hsfsts;
2218         s32 ret_val = -E1000_ERR_NVM;
2219
2220         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2221
2222         /* Check if the flash descriptor is valid */
2223         if (hsfsts.hsf_status.fldesvalid == 0) {
2224                 e_dbg("Flash descriptor invalid.  "
2225                          "SW Sequencing must be used.\n");
2226                 return -E1000_ERR_NVM;
2227         }
2228
2229         /* Clear FCERR and DAEL in hw status by writing 1 */
2230         hsfsts.hsf_status.flcerr = 1;
2231         hsfsts.hsf_status.dael = 1;
2232
2233         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2234
2235         /*
2236          * Either we should have a hardware SPI cycle in progress
2237          * bit to check against, in order to start a new cycle or
2238          * FDONE bit should be changed in the hardware so that it
2239          * is 1 after hardware reset, which can then be used as an
2240          * indication whether a cycle is in progress or has been
2241          * completed.
2242          */
2243
2244         if (hsfsts.hsf_status.flcinprog == 0) {
2245                 /*
2246                  * There is no cycle running at present,
2247                  * so we can start a cycle.
2248                  * Begin by setting Flash Cycle Done.
2249                  */
2250                 hsfsts.hsf_status.flcdone = 1;
2251                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2252                 ret_val = 0;
2253         } else {
2254                 s32 i = 0;
2255
2256                 /*
2257                  * Otherwise poll for sometime so the current
2258                  * cycle has a chance to end before giving up.
2259                  */
2260                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2261                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2262                         if (hsfsts.hsf_status.flcinprog == 0) {
2263                                 ret_val = 0;
2264                                 break;
2265                         }
2266                         udelay(1);
2267                 }
2268                 if (ret_val == 0) {
2269                         /*
2270                          * Successful in waiting for previous cycle to timeout,
2271                          * now set the Flash Cycle Done.
2272                          */
2273                         hsfsts.hsf_status.flcdone = 1;
2274                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2275                 } else {
2276                         e_dbg("Flash controller busy, cannot get access\n");
2277                 }
2278         }
2279
2280         return ret_val;
2281 }
2282
2283 /**
2284  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2285  *  @hw: pointer to the HW structure
2286  *  @timeout: maximum time to wait for completion
2287  *
2288  *  This function starts a flash cycle and waits for its completion.
2289  **/
2290 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2291 {
2292         union ich8_hws_flash_ctrl hsflctl;
2293         union ich8_hws_flash_status hsfsts;
2294         s32 ret_val = -E1000_ERR_NVM;
2295         u32 i = 0;
2296
2297         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2298         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2299         hsflctl.hsf_ctrl.flcgo = 1;
2300         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2301
2302         /* wait till FDONE bit is set to 1 */
2303         do {
2304                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2305                 if (hsfsts.hsf_status.flcdone == 1)
2306                         break;
2307                 udelay(1);
2308         } while (i++ < timeout);
2309
2310         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2311                 return 0;
2312
2313         return ret_val;
2314 }
2315
2316 /**
2317  *  e1000_read_flash_word_ich8lan - Read word from flash
2318  *  @hw: pointer to the HW structure
2319  *  @offset: offset to data location
2320  *  @data: pointer to the location for storing the data
2321  *
2322  *  Reads the flash word at offset into data.  Offset is converted
2323  *  to bytes before read.
2324  **/
2325 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2326                                          u16 *data)
2327 {
2328         /* Must convert offset into bytes. */
2329         offset <<= 1;
2330
2331         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2332 }
2333
2334 /**
2335  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2336  *  @hw: pointer to the HW structure
2337  *  @offset: The offset of the byte to read.
2338  *  @data: Pointer to a byte to store the value read.
2339  *
2340  *  Reads a single byte from the NVM using the flash access registers.
2341  **/
2342 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2343                                          u8 *data)
2344 {
2345         s32 ret_val;
2346         u16 word = 0;
2347
2348         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2349         if (ret_val)
2350                 return ret_val;
2351
2352         *data = (u8)word;
2353
2354         return 0;
2355 }
2356
2357 /**
2358  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2359  *  @hw: pointer to the HW structure
2360  *  @offset: The offset (in bytes) of the byte or word to read.
2361  *  @size: Size of data to read, 1=byte 2=word
2362  *  @data: Pointer to the word to store the value read.
2363  *
2364  *  Reads a byte or word from the NVM using the flash access registers.
2365  **/
2366 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2367                                          u8 size, u16 *data)
2368 {
2369         union ich8_hws_flash_status hsfsts;
2370         union ich8_hws_flash_ctrl hsflctl;
2371         u32 flash_linear_addr;
2372         u32 flash_data = 0;
2373         s32 ret_val = -E1000_ERR_NVM;
2374         u8 count = 0;
2375
2376         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2377                 return -E1000_ERR_NVM;
2378
2379         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2380                             hw->nvm.flash_base_addr;
2381
2382         do {
2383                 udelay(1);
2384                 /* Steps */
2385                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2386                 if (ret_val != 0)
2387                         break;
2388
2389                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2390                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2391                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2392                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2393                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2394
2395                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2396
2397                 ret_val = e1000_flash_cycle_ich8lan(hw,
2398                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2399
2400                 /*
2401                  * Check if FCERR is set to 1, if set to 1, clear it
2402                  * and try the whole sequence a few more times, else
2403                  * read in (shift in) the Flash Data0, the order is
2404                  * least significant byte first msb to lsb
2405                  */
2406                 if (ret_val == 0) {
2407                         flash_data = er32flash(ICH_FLASH_FDATA0);
2408                         if (size == 1)
2409                                 *data = (u8)(flash_data & 0x000000FF);
2410                         else if (size == 2)
2411                                 *data = (u16)(flash_data & 0x0000FFFF);
2412                         break;
2413                 } else {
2414                         /*
2415                          * If we've gotten here, then things are probably
2416                          * completely hosed, but if the error condition is
2417                          * detected, it won't hurt to give it another try...
2418                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2419                          */
2420                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2421                         if (hsfsts.hsf_status.flcerr == 1) {
2422                                 /* Repeat for some time before giving up. */
2423                                 continue;
2424                         } else if (hsfsts.hsf_status.flcdone == 0) {
2425                                 e_dbg("Timeout error - flash cycle "
2426                                          "did not complete.\n");
2427                                 break;
2428                         }
2429                 }
2430         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2431
2432         return ret_val;
2433 }
2434
2435 /**
2436  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2437  *  @hw: pointer to the HW structure
2438  *  @offset: The offset (in bytes) of the word(s) to write.
2439  *  @words: Size of data to write in words
2440  *  @data: Pointer to the word(s) to write at offset.
2441  *
2442  *  Writes a byte or word to the NVM using the flash access registers.
2443  **/
2444 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2445                                    u16 *data)
2446 {
2447         struct e1000_nvm_info *nvm = &hw->nvm;
2448         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2449         u16 i;
2450
2451         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2452             (words == 0)) {
2453                 e_dbg("nvm parameter(s) out of bounds\n");
2454                 return -E1000_ERR_NVM;
2455         }
2456
2457         nvm->ops.acquire(hw);
2458
2459         for (i = 0; i < words; i++) {
2460                 dev_spec->shadow_ram[offset+i].modified = true;
2461                 dev_spec->shadow_ram[offset+i].value = data[i];
2462         }
2463
2464         nvm->ops.release(hw);
2465
2466         return 0;
2467 }
2468
2469 /**
2470  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2471  *  @hw: pointer to the HW structure
2472  *
2473  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2474  *  which writes the checksum to the shadow ram.  The changes in the shadow
2475  *  ram are then committed to the EEPROM by processing each bank at a time
2476  *  checking for the modified bit and writing only the pending changes.
2477  *  After a successful commit, the shadow ram is cleared and is ready for
2478  *  future writes.
2479  **/
2480 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2481 {
2482         struct e1000_nvm_info *nvm = &hw->nvm;
2483         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2484         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2485         s32 ret_val;
2486         u16 data;
2487
2488         ret_val = e1000e_update_nvm_checksum_generic(hw);
2489         if (ret_val)
2490                 goto out;
2491
2492         if (nvm->type != e1000_nvm_flash_sw)
2493                 goto out;
2494
2495         nvm->ops.acquire(hw);
2496
2497         /*
2498          * We're writing to the opposite bank so if we're on bank 1,
2499          * write to bank 0 etc.  We also need to erase the segment that
2500          * is going to be written
2501          */
2502         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2503         if (ret_val) {
2504                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2505                 bank = 0;
2506         }
2507
2508         if (bank == 0) {
2509                 new_bank_offset = nvm->flash_bank_size;
2510                 old_bank_offset = 0;
2511                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2512                 if (ret_val)
2513                         goto release;
2514         } else {
2515                 old_bank_offset = nvm->flash_bank_size;
2516                 new_bank_offset = 0;
2517                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2518                 if (ret_val)
2519                         goto release;
2520         }
2521
2522         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2523                 /*
2524                  * Determine whether to write the value stored
2525                  * in the other NVM bank or a modified value stored
2526                  * in the shadow RAM
2527                  */
2528                 if (dev_spec->shadow_ram[i].modified) {
2529                         data = dev_spec->shadow_ram[i].value;
2530                 } else {
2531                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2532                                                                 old_bank_offset,
2533                                                                 &data);
2534                         if (ret_val)
2535                                 break;
2536                 }
2537
2538                 /*
2539                  * If the word is 0x13, then make sure the signature bits
2540                  * (15:14) are 11b until the commit has completed.
2541                  * This will allow us to write 10b which indicates the
2542                  * signature is valid.  We want to do this after the write
2543                  * has completed so that we don't mark the segment valid
2544                  * while the write is still in progress
2545                  */
2546                 if (i == E1000_ICH_NVM_SIG_WORD)
2547                         data |= E1000_ICH_NVM_SIG_MASK;
2548
2549                 /* Convert offset to bytes. */
2550                 act_offset = (i + new_bank_offset) << 1;
2551
2552                 udelay(100);
2553                 /* Write the bytes to the new bank. */
2554                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2555                                                                act_offset,
2556                                                                (u8)data);
2557                 if (ret_val)
2558                         break;
2559
2560                 udelay(100);
2561                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2562                                                           act_offset + 1,
2563                                                           (u8)(data >> 8));
2564                 if (ret_val)
2565                         break;
2566         }
2567
2568         /*
2569          * Don't bother writing the segment valid bits if sector
2570          * programming failed.
2571          */
2572         if (ret_val) {
2573                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2574                 e_dbg("Flash commit failed.\n");
2575                 goto release;
2576         }
2577
2578         /*
2579          * Finally validate the new segment by setting bit 15:14
2580          * to 10b in word 0x13 , this can be done without an
2581          * erase as well since these bits are 11 to start with
2582          * and we need to change bit 14 to 0b
2583          */
2584         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2585         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2586         if (ret_val)
2587                 goto release;
2588
2589         data &= 0xBFFF;
2590         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2591                                                        act_offset * 2 + 1,
2592                                                        (u8)(data >> 8));
2593         if (ret_val)
2594                 goto release;
2595
2596         /*
2597          * And invalidate the previously valid segment by setting
2598          * its signature word (0x13) high_byte to 0b. This can be
2599          * done without an erase because flash erase sets all bits
2600          * to 1's. We can write 1's to 0's without an erase
2601          */
2602         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2603         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2604         if (ret_val)
2605                 goto release;
2606
2607         /* Great!  Everything worked, we can now clear the cached entries. */
2608         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2609                 dev_spec->shadow_ram[i].modified = false;
2610                 dev_spec->shadow_ram[i].value = 0xFFFF;
2611         }
2612
2613 release:
2614         nvm->ops.release(hw);
2615
2616         /*
2617          * Reload the EEPROM, or else modifications will not appear
2618          * until after the next adapter reset.
2619          */
2620         if (!ret_val) {
2621                 e1000e_reload_nvm(hw);
2622                 usleep_range(10000, 20000);
2623         }
2624
2625 out:
2626         if (ret_val)
2627                 e_dbg("NVM update error: %d\n", ret_val);
2628
2629         return ret_val;
2630 }
2631
2632 /**
2633  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2634  *  @hw: pointer to the HW structure
2635  *
2636  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2637  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2638  *  calculated, in which case we need to calculate the checksum and set bit 6.
2639  **/
2640 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2641 {
2642         s32 ret_val;
2643         u16 data;
2644
2645         /*
2646          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2647          * needs to be fixed.  This bit is an indication that the NVM
2648          * was prepared by OEM software and did not calculate the
2649          * checksum...a likely scenario.
2650          */
2651         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2652         if (ret_val)
2653                 return ret_val;
2654
2655         if ((data & 0x40) == 0) {
2656                 data |= 0x40;
2657                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2658                 if (ret_val)
2659                         return ret_val;
2660                 ret_val = e1000e_update_nvm_checksum(hw);
2661                 if (ret_val)
2662                         return ret_val;
2663         }
2664
2665         return e1000e_validate_nvm_checksum_generic(hw);
2666 }
2667
2668 /**
2669  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2670  *  @hw: pointer to the HW structure
2671  *
2672  *  To prevent malicious write/erase of the NVM, set it to be read-only
2673  *  so that the hardware ignores all write/erase cycles of the NVM via
2674  *  the flash control registers.  The shadow-ram copy of the NVM will
2675  *  still be updated, however any updates to this copy will not stick
2676  *  across driver reloads.
2677  **/
2678 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2679 {
2680         struct e1000_nvm_info *nvm = &hw->nvm;
2681         union ich8_flash_protected_range pr0;
2682         union ich8_hws_flash_status hsfsts;
2683         u32 gfpreg;
2684
2685         nvm->ops.acquire(hw);
2686
2687         gfpreg = er32flash(ICH_FLASH_GFPREG);
2688
2689         /* Write-protect GbE Sector of NVM */
2690         pr0.regval = er32flash(ICH_FLASH_PR0);
2691         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2692         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2693         pr0.range.wpe = true;
2694         ew32flash(ICH_FLASH_PR0, pr0.regval);
2695
2696         /*
2697          * Lock down a subset of GbE Flash Control Registers, e.g.
2698          * PR0 to prevent the write-protection from being lifted.
2699          * Once FLOCKDN is set, the registers protected by it cannot
2700          * be written until FLOCKDN is cleared by a hardware reset.
2701          */
2702         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2703         hsfsts.hsf_status.flockdn = true;
2704         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2705
2706         nvm->ops.release(hw);
2707 }
2708
2709 /**
2710  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2711  *  @hw: pointer to the HW structure
2712  *  @offset: The offset (in bytes) of the byte/word to read.
2713  *  @size: Size of data to read, 1=byte 2=word
2714  *  @data: The byte(s) to write to the NVM.
2715  *
2716  *  Writes one/two bytes to the NVM using the flash access registers.
2717  **/
2718 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2719                                           u8 size, u16 data)
2720 {
2721         union ich8_hws_flash_status hsfsts;
2722         union ich8_hws_flash_ctrl hsflctl;
2723         u32 flash_linear_addr;
2724         u32 flash_data = 0;
2725         s32 ret_val;
2726         u8 count = 0;
2727
2728         if (size < 1 || size > 2 || data > size * 0xff ||
2729             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2730                 return -E1000_ERR_NVM;
2731
2732         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2733                             hw->nvm.flash_base_addr;
2734
2735         do {
2736                 udelay(1);
2737                 /* Steps */
2738                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2739                 if (ret_val)
2740                         break;
2741
2742                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2743                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2744                 hsflctl.hsf_ctrl.fldbcount = size -1;
2745                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2746                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2747
2748                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2749
2750                 if (size == 1)
2751                         flash_data = (u32)data & 0x00FF;
2752                 else
2753                         flash_data = (u32)data;
2754
2755                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2756
2757                 /*
2758                  * check if FCERR is set to 1 , if set to 1, clear it
2759                  * and try the whole sequence a few more times else done
2760                  */
2761                 ret_val = e1000_flash_cycle_ich8lan(hw,
2762                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2763                 if (!ret_val)
2764                         break;
2765
2766                 /*
2767                  * If we're here, then things are most likely
2768                  * completely hosed, but if the error condition
2769                  * is detected, it won't hurt to give it another
2770                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2771                  */
2772                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2773                 if (hsfsts.hsf_status.flcerr == 1)
2774                         /* Repeat for some time before giving up. */
2775                         continue;
2776                 if (hsfsts.hsf_status.flcdone == 0) {
2777                         e_dbg("Timeout error - flash cycle "
2778                                  "did not complete.");
2779                         break;
2780                 }
2781         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2782
2783         return ret_val;
2784 }
2785
2786 /**
2787  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2788  *  @hw: pointer to the HW structure
2789  *  @offset: The index of the byte to read.
2790  *  @data: The byte to write to the NVM.
2791  *
2792  *  Writes a single byte to the NVM using the flash access registers.
2793  **/
2794 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2795                                           u8 data)
2796 {
2797         u16 word = (u16)data;
2798
2799         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2800 }
2801
2802 /**
2803  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2804  *  @hw: pointer to the HW structure
2805  *  @offset: The offset of the byte to write.
2806  *  @byte: The byte to write to the NVM.
2807  *
2808  *  Writes a single byte to the NVM using the flash access registers.
2809  *  Goes through a retry algorithm before giving up.
2810  **/
2811 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2812                                                 u32 offset, u8 byte)
2813 {
2814         s32 ret_val;
2815         u16 program_retries;
2816
2817         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2818         if (!ret_val)
2819                 return ret_val;
2820
2821         for (program_retries = 0; program_retries < 100; program_retries++) {
2822                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2823                 udelay(100);
2824                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2825                 if (!ret_val)
2826                         break;
2827         }
2828         if (program_retries == 100)
2829                 return -E1000_ERR_NVM;
2830
2831         return 0;
2832 }
2833
2834 /**
2835  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2836  *  @hw: pointer to the HW structure
2837  *  @bank: 0 for first bank, 1 for second bank, etc.
2838  *
2839  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2840  *  bank N is 4096 * N + flash_reg_addr.
2841  **/
2842 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2843 {
2844         struct e1000_nvm_info *nvm = &hw->nvm;
2845         union ich8_hws_flash_status hsfsts;
2846         union ich8_hws_flash_ctrl hsflctl;
2847         u32 flash_linear_addr;
2848         /* bank size is in 16bit words - adjust to bytes */
2849         u32 flash_bank_size = nvm->flash_bank_size * 2;
2850         s32 ret_val;
2851         s32 count = 0;
2852         s32 j, iteration, sector_size;
2853
2854         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2855
2856         /*
2857          * Determine HW Sector size: Read BERASE bits of hw flash status
2858          * register
2859          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2860          *     consecutive sectors.  The start index for the nth Hw sector
2861          *     can be calculated as = bank * 4096 + n * 256
2862          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2863          *     The start index for the nth Hw sector can be calculated
2864          *     as = bank * 4096
2865          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2866          *     (ich9 only, otherwise error condition)
2867          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2868          */
2869         switch (hsfsts.hsf_status.berasesz) {
2870         case 0:
2871                 /* Hw sector size 256 */
2872                 sector_size = ICH_FLASH_SEG_SIZE_256;
2873                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2874                 break;
2875         case 1:
2876                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2877                 iteration = 1;
2878                 break;
2879         case 2:
2880                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2881                 iteration = 1;
2882                 break;
2883         case 3:
2884                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2885                 iteration = 1;
2886                 break;
2887         default:
2888                 return -E1000_ERR_NVM;
2889         }
2890
2891         /* Start with the base address, then add the sector offset. */
2892         flash_linear_addr = hw->nvm.flash_base_addr;
2893         flash_linear_addr += (bank) ? flash_bank_size : 0;
2894
2895         for (j = 0; j < iteration ; j++) {
2896                 do {
2897                         /* Steps */
2898                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2899                         if (ret_val)
2900                                 return ret_val;
2901
2902                         /*
2903                          * Write a value 11 (block Erase) in Flash
2904                          * Cycle field in hw flash control
2905                          */
2906                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2907                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2908                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2909
2910                         /*
2911                          * Write the last 24 bits of an index within the
2912                          * block into Flash Linear address field in Flash
2913                          * Address.
2914                          */
2915                         flash_linear_addr += (j * sector_size);
2916                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2917
2918                         ret_val = e1000_flash_cycle_ich8lan(hw,
2919                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2920                         if (ret_val == 0)
2921                                 break;
2922
2923                         /*
2924                          * Check if FCERR is set to 1.  If 1,
2925                          * clear it and try the whole sequence
2926                          * a few more times else Done
2927                          */
2928                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2929                         if (hsfsts.hsf_status.flcerr == 1)
2930                                 /* repeat for some time before giving up */
2931                                 continue;
2932                         else if (hsfsts.hsf_status.flcdone == 0)
2933                                 return ret_val;
2934                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2935         }
2936
2937         return 0;
2938 }
2939
2940 /**
2941  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2942  *  @hw: pointer to the HW structure
2943  *  @data: Pointer to the LED settings
2944  *
2945  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2946  *  settings is all 0's or F's, set the LED default to a valid LED default
2947  *  setting.
2948  **/
2949 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2950 {
2951         s32 ret_val;
2952
2953         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2954         if (ret_val) {
2955                 e_dbg("NVM Read Error\n");
2956                 return ret_val;
2957         }
2958
2959         if (*data == ID_LED_RESERVED_0000 ||
2960             *data == ID_LED_RESERVED_FFFF)
2961                 *data = ID_LED_DEFAULT_ICH8LAN;
2962
2963         return 0;
2964 }
2965
2966 /**
2967  *  e1000_id_led_init_pchlan - store LED configurations
2968  *  @hw: pointer to the HW structure
2969  *
2970  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2971  *  the PHY LED configuration register.
2972  *
2973  *  PCH also does not have an "always on" or "always off" mode which
2974  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2975  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2976  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2977  *  link based on logic in e1000_led_[on|off]_pchlan().
2978  **/
2979 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2980 {
2981         struct e1000_mac_info *mac = &hw->mac;
2982         s32 ret_val;
2983         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2984         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2985         u16 data, i, temp, shift;
2986
2987         /* Get default ID LED modes */
2988         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2989         if (ret_val)
2990                 goto out;
2991
2992         mac->ledctl_default = er32(LEDCTL);
2993         mac->ledctl_mode1 = mac->ledctl_default;
2994         mac->ledctl_mode2 = mac->ledctl_default;
2995
2996         for (i = 0; i < 4; i++) {
2997                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2998                 shift = (i * 5);
2999                 switch (temp) {
3000                 case ID_LED_ON1_DEF2:
3001                 case ID_LED_ON1_ON2:
3002                 case ID_LED_ON1_OFF2:
3003                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3004                         mac->ledctl_mode1 |= (ledctl_on << shift);
3005                         break;
3006                 case ID_LED_OFF1_DEF2:
3007                 case ID_LED_OFF1_ON2:
3008                 case ID_LED_OFF1_OFF2:
3009                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3010                         mac->ledctl_mode1 |= (ledctl_off << shift);
3011                         break;
3012                 default:
3013                         /* Do nothing */
3014                         break;
3015                 }
3016                 switch (temp) {
3017                 case ID_LED_DEF1_ON2:
3018                 case ID_LED_ON1_ON2:
3019                 case ID_LED_OFF1_ON2:
3020                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3021                         mac->ledctl_mode2 |= (ledctl_on << shift);
3022                         break;
3023                 case ID_LED_DEF1_OFF2:
3024                 case ID_LED_ON1_OFF2:
3025                 case ID_LED_OFF1_OFF2:
3026                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3027                         mac->ledctl_mode2 |= (ledctl_off << shift);
3028                         break;
3029                 default:
3030                         /* Do nothing */
3031                         break;
3032                 }
3033         }
3034
3035 out:
3036         return ret_val;
3037 }
3038
3039 /**
3040  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3041  *  @hw: pointer to the HW structure
3042  *
3043  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3044  *  register, so the the bus width is hard coded.
3045  **/
3046 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3047 {
3048         struct e1000_bus_info *bus = &hw->bus;
3049         s32 ret_val;
3050
3051         ret_val = e1000e_get_bus_info_pcie(hw);
3052
3053         /*
3054          * ICH devices are "PCI Express"-ish.  They have
3055          * a configuration space, but do not contain
3056          * PCI Express Capability registers, so bus width
3057          * must be hardcoded.
3058          */
3059         if (bus->width == e1000_bus_width_unknown)
3060                 bus->width = e1000_bus_width_pcie_x1;
3061
3062         return ret_val;
3063 }
3064
3065 /**
3066  *  e1000_reset_hw_ich8lan - Reset the hardware
3067  *  @hw: pointer to the HW structure
3068  *
3069  *  Does a full reset of the hardware which includes a reset of the PHY and
3070  *  MAC.
3071  **/
3072 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3073 {
3074         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3075         u16 reg;
3076         u32 ctrl, kab;
3077         s32 ret_val;
3078
3079         /*
3080          * Prevent the PCI-E bus from sticking if there is no TLP connection
3081          * on the last TLP read/write transaction when MAC is reset.
3082          */
3083         ret_val = e1000e_disable_pcie_master(hw);
3084         if (ret_val)
3085                 e_dbg("PCI-E Master disable polling has failed.\n");
3086
3087         e_dbg("Masking off all interrupts\n");
3088         ew32(IMC, 0xffffffff);
3089
3090         /*
3091          * Disable the Transmit and Receive units.  Then delay to allow
3092          * any pending transactions to complete before we hit the MAC
3093          * with the global reset.
3094          */
3095         ew32(RCTL, 0);
3096         ew32(TCTL, E1000_TCTL_PSP);
3097         e1e_flush();
3098
3099         usleep_range(10000, 20000);
3100
3101         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3102         if (hw->mac.type == e1000_ich8lan) {
3103                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3104                 ew32(PBA, E1000_PBA_8K);
3105                 /* Set Packet Buffer Size to 16k. */
3106                 ew32(PBS, E1000_PBS_16K);
3107         }
3108
3109         if (hw->mac.type == e1000_pchlan) {
3110                 /* Save the NVM K1 bit setting*/
3111                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3112                 if (ret_val)
3113                         return ret_val;
3114
3115                 if (reg & E1000_NVM_K1_ENABLE)
3116                         dev_spec->nvm_k1_enabled = true;
3117                 else
3118                         dev_spec->nvm_k1_enabled = false;
3119         }
3120
3121         ctrl = er32(CTRL);
3122
3123         if (!e1000_check_reset_block(hw)) {
3124                 /*
3125                  * Full-chip reset requires MAC and PHY reset at the same
3126                  * time to make sure the interface between MAC and the
3127                  * external PHY is reset.
3128                  */
3129                 ctrl |= E1000_CTRL_PHY_RST;
3130
3131                 /*
3132                  * Gate automatic PHY configuration by hardware on
3133                  * non-managed 82579
3134                  */
3135                 if ((hw->mac.type == e1000_pch2lan) &&
3136                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3137                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3138         }
3139         ret_val = e1000_acquire_swflag_ich8lan(hw);
3140         e_dbg("Issuing a global reset to ich8lan\n");
3141         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3142         /* cannot issue a flush here because it hangs the hardware */
3143         msleep(20);
3144
3145         if (!ret_val)
3146                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3147
3148         if (ctrl & E1000_CTRL_PHY_RST) {
3149                 ret_val = hw->phy.ops.get_cfg_done(hw);
3150                 if (ret_val)
3151                         goto out;
3152
3153                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3154                 if (ret_val)
3155                         goto out;
3156         }
3157
3158         /*
3159          * For PCH, this write will make sure that any noise
3160          * will be detected as a CRC error and be dropped rather than show up
3161          * as a bad packet to the DMA engine.
3162          */
3163         if (hw->mac.type == e1000_pchlan)
3164                 ew32(CRC_OFFSET, 0x65656565);
3165
3166         ew32(IMC, 0xffffffff);
3167         er32(ICR);
3168
3169         kab = er32(KABGTXD);
3170         kab |= E1000_KABGTXD_BGSQLBIAS;
3171         ew32(KABGTXD, kab);
3172
3173 out:
3174         return ret_val;
3175 }
3176
3177 /**
3178  *  e1000_init_hw_ich8lan - Initialize the hardware
3179  *  @hw: pointer to the HW structure
3180  *
3181  *  Prepares the hardware for transmit and receive by doing the following:
3182  *   - initialize hardware bits
3183  *   - initialize LED identification
3184  *   - setup receive address registers
3185  *   - setup flow control
3186  *   - setup transmit descriptors
3187  *   - clear statistics
3188  **/
3189 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3190 {
3191         struct e1000_mac_info *mac = &hw->mac;
3192         u32 ctrl_ext, txdctl, snoop;
3193         s32 ret_val;
3194         u16 i;
3195
3196         e1000_initialize_hw_bits_ich8lan(hw);
3197
3198         /* Initialize identification LED */
3199         ret_val = mac->ops.id_led_init(hw);
3200         if (ret_val)
3201                 e_dbg("Error initializing identification LED\n");
3202                 /* This is not fatal and we should not stop init due to this */
3203
3204         /* Setup the receive address. */
3205         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3206
3207         /* Zero out the Multicast HASH table */
3208         e_dbg("Zeroing the MTA\n");
3209         for (i = 0; i < mac->mta_reg_count; i++)
3210                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3211
3212         /*
3213          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3214          * the ME.  Disable wakeup by clearing the host wakeup bit.
3215          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3216          */
3217         if (hw->phy.type == e1000_phy_82578) {
3218                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3219                 i &= ~BM_WUC_HOST_WU_BIT;
3220                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3221                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3222                 if (ret_val)
3223                         return ret_val;
3224         }
3225
3226         /* Setup link and flow control */
3227         ret_val = e1000_setup_link_ich8lan(hw);
3228
3229         /* Set the transmit descriptor write-back policy for both queues */
3230         txdctl = er32(TXDCTL(0));
3231         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3232                  E1000_TXDCTL_FULL_TX_DESC_WB;
3233         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3234                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3235         ew32(TXDCTL(0), txdctl);
3236         txdctl = er32(TXDCTL(1));
3237         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3238                  E1000_TXDCTL_FULL_TX_DESC_WB;
3239         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3240                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3241         ew32(TXDCTL(1), txdctl);
3242
3243         /*
3244          * ICH8 has opposite polarity of no_snoop bits.
3245          * By default, we should use snoop behavior.
3246          */
3247         if (mac->type == e1000_ich8lan)
3248                 snoop = PCIE_ICH8_SNOOP_ALL;
3249         else
3250                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3251         e1000e_set_pcie_no_snoop(hw, snoop);
3252
3253         ctrl_ext = er32(CTRL_EXT);
3254         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3255         ew32(CTRL_EXT, ctrl_ext);
3256
3257         /*
3258          * Clear all of the statistics registers (clear on read).  It is
3259          * important that we do this after we have tried to establish link
3260          * because the symbol error count will increment wildly if there
3261          * is no link.
3262          */
3263         e1000_clear_hw_cntrs_ich8lan(hw);
3264
3265         return 0;
3266 }
3267 /**
3268  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3269  *  @hw: pointer to the HW structure
3270  *
3271  *  Sets/Clears required hardware bits necessary for correctly setting up the
3272  *  hardware for transmit and receive.
3273  **/
3274 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3275 {
3276         u32 reg;
3277
3278         /* Extended Device Control */
3279         reg = er32(CTRL_EXT);
3280         reg |= (1 << 22);
3281         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3282         if (hw->mac.type >= e1000_pchlan)
3283                 reg |= E1000_CTRL_EXT_PHYPDEN;
3284         ew32(CTRL_EXT, reg);
3285
3286         /* Transmit Descriptor Control 0 */
3287         reg = er32(TXDCTL(0));
3288         reg |= (1 << 22);
3289         ew32(TXDCTL(0), reg);
3290
3291         /* Transmit Descriptor Control 1 */
3292         reg = er32(TXDCTL(1));
3293         reg |= (1 << 22);
3294         ew32(TXDCTL(1), reg);
3295
3296         /* Transmit Arbitration Control 0 */
3297         reg = er32(TARC(0));
3298         if (hw->mac.type == e1000_ich8lan)
3299                 reg |= (1 << 28) | (1 << 29);
3300         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3301         ew32(TARC(0), reg);
3302
3303         /* Transmit Arbitration Control 1 */
3304         reg = er32(TARC(1));
3305         if (er32(TCTL) & E1000_TCTL_MULR)
3306                 reg &= ~(1 << 28);
3307         else
3308                 reg |= (1 << 28);
3309         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3310         ew32(TARC(1), reg);
3311
3312         /* Device Status */
3313         if (hw->mac.type == e1000_ich8lan) {
3314                 reg = er32(STATUS);
3315                 reg &= ~(1 << 31);
3316                 ew32(STATUS, reg);
3317         }
3318
3319         /*
3320          * work-around descriptor data corruption issue during nfs v2 udp
3321          * traffic, just disable the nfs filtering capability
3322          */
3323         reg = er32(RFCTL);
3324         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3325         ew32(RFCTL, reg);
3326 }
3327
3328 /**
3329  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3330  *  @hw: pointer to the HW structure
3331  *
3332  *  Determines which flow control settings to use, then configures flow
3333  *  control.  Calls the appropriate media-specific link configuration
3334  *  function.  Assuming the adapter has a valid link partner, a valid link
3335  *  should be established.  Assumes the hardware has previously been reset
3336  *  and the transmitter and receiver are not enabled.
3337  **/
3338 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3339 {
3340         s32 ret_val;
3341
3342         if (e1000_check_reset_block(hw))
3343                 return 0;
3344
3345         /*
3346          * ICH parts do not have a word in the NVM to determine
3347          * the default flow control setting, so we explicitly
3348          * set it to full.
3349          */
3350         if (hw->fc.requested_mode == e1000_fc_default) {
3351                 /* Workaround h/w hang when Tx flow control enabled */
3352                 if (hw->mac.type == e1000_pchlan)
3353                         hw->fc.requested_mode = e1000_fc_rx_pause;
3354                 else
3355                         hw->fc.requested_mode = e1000_fc_full;
3356         }
3357
3358         /*
3359          * Save off the requested flow control mode for use later.  Depending
3360          * on the link partner's capabilities, we may or may not use this mode.
3361          */
3362         hw->fc.current_mode = hw->fc.requested_mode;
3363
3364         e_dbg("After fix-ups FlowControl is now = %x\n",
3365                 hw->fc.current_mode);
3366
3367         /* Continue to configure the copper link. */
3368         ret_val = e1000_setup_copper_link_ich8lan(hw);
3369         if (ret_val)
3370                 return ret_val;
3371
3372         ew32(FCTTV, hw->fc.pause_time);
3373         if ((hw->phy.type == e1000_phy_82578) ||
3374             (hw->phy.type == e1000_phy_82579) ||
3375             (hw->phy.type == e1000_phy_82577)) {
3376                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3377
3378                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3379                                    hw->fc.pause_time);
3380                 if (ret_val)
3381                         return ret_val;
3382         }
3383
3384         return e1000e_set_fc_watermarks(hw);
3385 }
3386
3387 /**
3388  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3389  *  @hw: pointer to the HW structure
3390  *
3391  *  Configures the kumeran interface to the PHY to wait the appropriate time
3392  *  when polling the PHY, then call the generic setup_copper_link to finish
3393  *  configuring the copper link.
3394  **/
3395 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3396 {
3397         u32 ctrl;
3398         s32 ret_val;
3399         u16 reg_data;
3400
3401         ctrl = er32(CTRL);
3402         ctrl |= E1000_CTRL_SLU;
3403         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3404         ew32(CTRL, ctrl);
3405
3406         /*
3407          * Set the mac to wait the maximum time between each iteration
3408          * and increase the max iterations when polling the phy;
3409          * this fixes erroneous timeouts at 10Mbps.
3410          */
3411         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3412         if (ret_val)
3413                 return ret_val;
3414         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3415                                        &reg_data);
3416         if (ret_val)
3417                 return ret_val;
3418         reg_data |= 0x3F;
3419         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3420                                         reg_data);
3421         if (ret_val)
3422                 return ret_val;
3423
3424         switch (hw->phy.type) {
3425         case e1000_phy_igp_3:
3426                 ret_val = e1000e_copper_link_setup_igp(hw);
3427                 if (ret_val)
3428                         return ret_val;
3429                 break;
3430         case e1000_phy_bm:
3431         case e1000_phy_82578:
3432                 ret_val = e1000e_copper_link_setup_m88(hw);
3433                 if (ret_val)
3434                         return ret_val;
3435                 break;
3436         case e1000_phy_82577:
3437         case e1000_phy_82579:
3438                 ret_val = e1000_copper_link_setup_82577(hw);
3439                 if (ret_val)
3440                         return ret_val;
3441                 break;
3442         case e1000_phy_ife:
3443                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3444                 if (ret_val)
3445                         return ret_val;
3446
3447                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3448
3449                 switch (hw->phy.mdix) {
3450                 case 1:
3451                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3452                         break;
3453                 case 2:
3454                         reg_data |= IFE_PMC_FORCE_MDIX;
3455                         break;
3456                 case 0:
3457                 default:
3458                         reg_data |= IFE_PMC_AUTO_MDIX;
3459                         break;
3460                 }
3461                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3462                 if (ret_val)
3463                         return ret_val;
3464                 break;
3465         default:
3466                 break;
3467         }
3468         return e1000e_setup_copper_link(hw);
3469 }
3470
3471 /**
3472  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3473  *  @hw: pointer to the HW structure
3474  *  @speed: pointer to store current link speed
3475  *  @duplex: pointer to store the current link duplex
3476  *
3477  *  Calls the generic get_speed_and_duplex to retrieve the current link
3478  *  information and then calls the Kumeran lock loss workaround for links at
3479  *  gigabit speeds.
3480  **/
3481 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3482                                           u16 *duplex)
3483 {
3484         s32 ret_val;
3485
3486         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3487         if (ret_val)
3488                 return ret_val;
3489
3490         if ((hw->mac.type == e1000_ich8lan) &&
3491             (hw->phy.type == e1000_phy_igp_3) &&
3492             (*speed == SPEED_1000)) {
3493                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3494         }
3495
3496         return ret_val;
3497 }
3498
3499 /**
3500  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3501  *  @hw: pointer to the HW structure
3502  *
3503  *  Work-around for 82566 Kumeran PCS lock loss:
3504  *  On link status change (i.e. PCI reset, speed change) and link is up and
3505  *  speed is gigabit-
3506  *    0) if workaround is optionally disabled do nothing
3507  *    1) wait 1ms for Kumeran link to come up
3508  *    2) check Kumeran Diagnostic register PCS lock loss bit
3509  *    3) if not set the link is locked (all is good), otherwise...
3510  *    4) reset the PHY
3511  *    5) repeat up to 10 times
3512  *  Note: this is only called for IGP3 copper when speed is 1gb.
3513  **/
3514 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3515 {
3516         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3517         u32 phy_ctrl;
3518         s32 ret_val;
3519         u16 i, data;
3520         bool link;
3521
3522         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3523                 return 0;
3524
3525         /*
3526          * Make sure link is up before proceeding.  If not just return.
3527          * Attempting this while link is negotiating fouled up link
3528          * stability
3529          */
3530         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3531         if (!link)
3532                 return 0;
3533
3534         for (i = 0; i < 10; i++) {
3535                 /* read once to clear */
3536                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3537                 if (ret_val)
3538                         return ret_val;
3539                 /* and again to get new status */
3540                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3541                 if (ret_val)
3542                         return ret_val;
3543
3544                 /* check for PCS lock */
3545                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3546                         return 0;
3547
3548                 /* Issue PHY reset */
3549                 e1000_phy_hw_reset(hw);
3550                 mdelay(5);
3551         }
3552         /* Disable GigE link negotiation */
3553         phy_ctrl = er32(PHY_CTRL);
3554         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3555                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3556         ew32(PHY_CTRL, phy_ctrl);
3557
3558         /*
3559          * Call gig speed drop workaround on Gig disable before accessing
3560          * any PHY registers
3561          */
3562         e1000e_gig_downshift_workaround_ich8lan(hw);
3563
3564         /* unable to acquire PCS lock */
3565         return -E1000_ERR_PHY;
3566 }
3567
3568 /**
3569  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3570  *  @hw: pointer to the HW structure
3571  *  @state: boolean value used to set the current Kumeran workaround state
3572  *
3573  *  If ICH8, set the current Kumeran workaround state (enabled - true
3574  *  /disabled - false).
3575  **/
3576 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3577                                                  bool state)
3578 {
3579         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3580
3581         if (hw->mac.type != e1000_ich8lan) {
3582                 e_dbg("Workaround applies to ICH8 only.\n");
3583                 return;
3584         }
3585
3586         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3587 }
3588
3589 /**
3590  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3591  *  @hw: pointer to the HW structure
3592  *
3593  *  Workaround for 82566 power-down on D3 entry:
3594  *    1) disable gigabit link
3595  *    2) write VR power-down enable
3596  *    3) read it back
3597  *  Continue if successful, else issue LCD reset and repeat
3598  **/
3599 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3600 {
3601         u32 reg;
3602         u16 data;
3603         u8  retry = 0;
3604
3605         if (hw->phy.type != e1000_phy_igp_3)
3606                 return;
3607
3608         /* Try the workaround twice (if needed) */
3609         do {
3610                 /* Disable link */
3611                 reg = er32(PHY_CTRL);
3612                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3613                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3614                 ew32(PHY_CTRL, reg);
3615
3616                 /*
3617                  * Call gig speed drop workaround on Gig disable before
3618                  * accessing any PHY registers
3619                  */
3620                 if (hw->mac.type == e1000_ich8lan)
3621                         e1000e_gig_downshift_workaround_ich8lan(hw);
3622
3623                 /* Write VR power-down enable */
3624                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3625                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3626                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3627
3628                 /* Read it back and test */
3629                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3630                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3631                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3632                         break;
3633
3634                 /* Issue PHY reset and repeat at most one more time */
3635                 reg = er32(CTRL);
3636                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3637                 retry++;
3638         } while (retry);
3639 }
3640
3641 /**
3642  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3643  *  @hw: pointer to the HW structure
3644  *
3645  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3646  *  LPLU, Gig disable, MDIC PHY reset):
3647  *    1) Set Kumeran Near-end loopback
3648  *    2) Clear Kumeran Near-end loopback
3649  *  Should only be called for ICH8[m] devices with any 1G Phy.
3650  **/
3651 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3652 {
3653         s32 ret_val;
3654         u16 reg_data;
3655
3656         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3657                 return;
3658
3659         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3660                                       &reg_data);
3661         if (ret_val)
3662                 return;
3663         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3664         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3665                                        reg_data);
3666         if (ret_val)
3667                 return;
3668         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3669         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3670                                        reg_data);
3671 }
3672
3673 /**
3674  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3675  *  @hw: pointer to the HW structure
3676  *
3677  *  During S0 to Sx transition, it is possible the link remains at gig
3678  *  instead of negotiating to a lower speed.  Before going to Sx, set
3679  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3680  *  to a lower speed.  For PCH and newer parts, the OEM bits PHY register
3681  *  (LED, GbE disable and LPLU configurations) also needs to be written.
3682  **/
3683 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3684 {
3685         u32 phy_ctrl;
3686         s32 ret_val;
3687
3688         phy_ctrl = er32(PHY_CTRL);
3689         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3690         ew32(PHY_CTRL, phy_ctrl);
3691
3692         if (hw->mac.type == e1000_ich8lan)
3693                 e1000e_gig_downshift_workaround_ich8lan(hw);
3694
3695         if (hw->mac.type >= e1000_pchlan) {
3696                 e1000_oem_bits_config_ich8lan(hw, false);
3697                 e1000_phy_hw_reset_ich8lan(hw);
3698                 ret_val = hw->phy.ops.acquire(hw);
3699                 if (ret_val)
3700                         return;
3701                 e1000_write_smbus_addr(hw);
3702                 hw->phy.ops.release(hw);
3703         }
3704 }
3705
3706 /**
3707  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3708  *  @hw: pointer to the HW structure
3709  *
3710  *  During Sx to S0 transitions on non-managed devices or managed devices
3711  *  on which PHY resets are not blocked, if the PHY registers cannot be
3712  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3713  *  the PHY.
3714  **/
3715 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3716 {
3717         u32 fwsm;
3718
3719         if (hw->mac.type != e1000_pch2lan)
3720                 return;
3721
3722         fwsm = er32(FWSM);
3723         if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3724                 u16 phy_id1, phy_id2;
3725                 s32 ret_val;
3726
3727                 ret_val = hw->phy.ops.acquire(hw);
3728                 if (ret_val) {
3729                         e_dbg("Failed to acquire PHY semaphore in resume\n");
3730                         return;
3731                 }
3732
3733                 /* Test access to the PHY registers by reading the ID regs */
3734                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3735                 if (ret_val)
3736                         goto release;
3737                 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3738                 if (ret_val)
3739                         goto release;
3740
3741                 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3742                                    (u32)(phy_id2 & PHY_REVISION_MASK)))
3743                         goto release;
3744
3745                 e1000_toggle_lanphypc_value_ich8lan(hw);
3746
3747                 hw->phy.ops.release(hw);
3748                 msleep(50);
3749                 e1000_phy_hw_reset(hw);
3750                 msleep(50);
3751                 return;
3752         }
3753
3754 release:
3755         hw->phy.ops.release(hw);
3756
3757         return;
3758 }
3759
3760 /**
3761  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3762  *  @hw: pointer to the HW structure
3763  *
3764  *  Return the LED back to the default configuration.
3765  **/
3766 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3767 {
3768         if (hw->phy.type == e1000_phy_ife)
3769                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3770
3771         ew32(LEDCTL, hw->mac.ledctl_default);
3772         return 0;
3773 }
3774
3775 /**
3776  *  e1000_led_on_ich8lan - Turn LEDs on
3777  *  @hw: pointer to the HW structure
3778  *
3779  *  Turn on the LEDs.
3780  **/
3781 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3782 {
3783         if (hw->phy.type == e1000_phy_ife)
3784                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3785                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3786
3787         ew32(LEDCTL, hw->mac.ledctl_mode2);
3788         return 0;
3789 }
3790
3791 /**
3792  *  e1000_led_off_ich8lan - Turn LEDs off
3793  *  @hw: pointer to the HW structure
3794  *
3795  *  Turn off the LEDs.
3796  **/
3797 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3798 {
3799         if (hw->phy.type == e1000_phy_ife)
3800                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3801                                 (IFE_PSCL_PROBE_MODE |
3802                                  IFE_PSCL_PROBE_LEDS_OFF));
3803
3804         ew32(LEDCTL, hw->mac.ledctl_mode1);
3805         return 0;
3806 }
3807
3808 /**
3809  *  e1000_setup_led_pchlan - Configures SW controllable LED
3810  *  @hw: pointer to the HW structure
3811  *
3812  *  This prepares the SW controllable LED for use.
3813  **/
3814 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3815 {
3816         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3817 }
3818
3819 /**
3820  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3821  *  @hw: pointer to the HW structure
3822  *
3823  *  Return the LED back to the default configuration.
3824  **/
3825 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3826 {
3827         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3828 }
3829
3830 /**
3831  *  e1000_led_on_pchlan - Turn LEDs on
3832  *  @hw: pointer to the HW structure
3833  *
3834  *  Turn on the LEDs.
3835  **/
3836 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3837 {
3838         u16 data = (u16)hw->mac.ledctl_mode2;
3839         u32 i, led;
3840
3841         /*
3842          * If no link, then turn LED on by setting the invert bit
3843          * for each LED that's mode is "link_up" in ledctl_mode2.
3844          */
3845         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3846                 for (i = 0; i < 3; i++) {
3847                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3848                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3849                             E1000_LEDCTL_MODE_LINK_UP)
3850                                 continue;
3851                         if (led & E1000_PHY_LED0_IVRT)
3852                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3853                         else
3854                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3855                 }
3856         }
3857
3858         return e1e_wphy(hw, HV_LED_CONFIG, data);
3859 }
3860
3861 /**
3862  *  e1000_led_off_pchlan - Turn LEDs off
3863  *  @hw: pointer to the HW structure
3864  *
3865  *  Turn off the LEDs.
3866  **/
3867 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3868 {
3869         u16 data = (u16)hw->mac.ledctl_mode1;
3870         u32 i, led;
3871
3872         /*
3873          * If no link, then turn LED off by clearing the invert bit
3874          * for each LED that's mode is "link_up" in ledctl_mode1.
3875          */
3876         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3877                 for (i = 0; i < 3; i++) {
3878                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3879                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3880                             E1000_LEDCTL_MODE_LINK_UP)
3881                                 continue;
3882                         if (led & E1000_PHY_LED0_IVRT)
3883                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3884                         else
3885                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3886                 }
3887         }
3888
3889         return e1e_wphy(hw, HV_LED_CONFIG, data);
3890 }
3891
3892 /**
3893  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3894  *  @hw: pointer to the HW structure
3895  *
3896  *  Read appropriate register for the config done bit for completion status
3897  *  and configure the PHY through s/w for EEPROM-less parts.
3898  *
3899  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3900  *  config done bit, so only an error is logged and continues.  If we were
3901  *  to return with error, EEPROM-less silicon would not be able to be reset
3902  *  or change link.
3903  **/
3904 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3905 {
3906         s32 ret_val = 0;
3907         u32 bank = 0;
3908         u32 status;
3909
3910         e1000e_get_cfg_done(hw);
3911
3912         /* Wait for indication from h/w that it has completed basic config */
3913         if (hw->mac.type >= e1000_ich10lan) {
3914                 e1000_lan_init_done_ich8lan(hw);
3915         } else {
3916                 ret_val = e1000e_get_auto_rd_done(hw);
3917                 if (ret_val) {
3918                         /*
3919                          * When auto config read does not complete, do not
3920                          * return with an error. This can happen in situations
3921                          * where there is no eeprom and prevents getting link.
3922                          */
3923                         e_dbg("Auto Read Done did not complete\n");
3924                         ret_val = 0;
3925                 }
3926         }
3927
3928         /* Clear PHY Reset Asserted bit */
3929         status = er32(STATUS);
3930         if (status & E1000_STATUS_PHYRA)
3931                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3932         else
3933                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3934
3935         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3936         if (hw->mac.type <= e1000_ich9lan) {
3937                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3938                     (hw->phy.type == e1000_phy_igp_3)) {
3939                         e1000e_phy_init_script_igp3(hw);
3940                 }
3941         } else {
3942                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3943                         /* Maybe we should do a basic PHY config */
3944                         e_dbg("EEPROM not present\n");
3945                         ret_val = -E1000_ERR_CONFIG;
3946                 }
3947         }
3948
3949         return ret_val;
3950 }
3951
3952 /**
3953  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3954  * @hw: pointer to the HW structure
3955  *
3956  * In the case of a PHY power down to save power, or to turn off link during a
3957  * driver unload, or wake on lan is not enabled, remove the link.
3958  **/
3959 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3960 {
3961         /* If the management interface is not enabled, then power down */
3962         if (!(hw->mac.ops.check_mng_mode(hw) ||
3963               hw->phy.ops.check_reset_block(hw)))
3964                 e1000_power_down_phy_copper(hw);
3965 }
3966
3967 /**
3968  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3969  *  @hw: pointer to the HW structure
3970  *
3971  *  Clears hardware counters specific to the silicon family and calls
3972  *  clear_hw_cntrs_generic to clear all general purpose counters.
3973  **/
3974 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3975 {
3976         u16 phy_data;
3977         s32 ret_val;
3978
3979         e1000e_clear_hw_cntrs_base(hw);
3980
3981         er32(ALGNERRC);
3982         er32(RXERRC);
3983         er32(TNCRS);
3984         er32(CEXTERR);
3985         er32(TSCTC);
3986         er32(TSCTFC);
3987
3988         er32(MGTPRC);
3989         er32(MGTPDC);
3990         er32(MGTPTC);
3991
3992         er32(IAC);
3993         er32(ICRXOC);
3994
3995         /* Clear PHY statistics registers */
3996         if ((hw->phy.type == e1000_phy_82578) ||
3997             (hw->phy.type == e1000_phy_82579) ||
3998             (hw->phy.type == e1000_phy_82577)) {
3999                 ret_val = hw->phy.ops.acquire(hw);
4000                 if (ret_val)
4001                         return;
4002                 ret_val = hw->phy.ops.set_page(hw,
4003                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4004                 if (ret_val)
4005                         goto release;
4006                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4007                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4008                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4009                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4010                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4011                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4012                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4013                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4014                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4015                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4016                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4017                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4018                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4019                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4020 release:
4021                 hw->phy.ops.release(hw);
4022         }
4023 }
4024
4025 static const struct e1000_mac_operations ich8_mac_ops = {
4026         .id_led_init            = e1000e_id_led_init,
4027         /* check_mng_mode dependent on mac type */
4028         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4029         /* cleanup_led dependent on mac type */
4030         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4031         .get_bus_info           = e1000_get_bus_info_ich8lan,
4032         .set_lan_id             = e1000_set_lan_id_single_port,
4033         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4034         /* led_on dependent on mac type */
4035         /* led_off dependent on mac type */
4036         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4037         .reset_hw               = e1000_reset_hw_ich8lan,
4038         .init_hw                = e1000_init_hw_ich8lan,
4039         .setup_link             = e1000_setup_link_ich8lan,
4040         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4041         /* id_led_init dependent on mac type */
4042 };
4043
4044 static const struct e1000_phy_operations ich8_phy_ops = {
4045         .acquire                = e1000_acquire_swflag_ich8lan,
4046         .check_reset_block      = e1000_check_reset_block_ich8lan,
4047         .commit                 = NULL,
4048         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4049         .get_cable_length       = e1000e_get_cable_length_igp_2,
4050         .read_reg               = e1000e_read_phy_reg_igp,
4051         .release                = e1000_release_swflag_ich8lan,
4052         .reset                  = e1000_phy_hw_reset_ich8lan,
4053         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4054         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4055         .write_reg              = e1000e_write_phy_reg_igp,
4056 };
4057
4058 static const struct e1000_nvm_operations ich8_nvm_ops = {
4059         .acquire                = e1000_acquire_nvm_ich8lan,
4060         .read                   = e1000_read_nvm_ich8lan,
4061         .release                = e1000_release_nvm_ich8lan,
4062         .update                 = e1000_update_nvm_checksum_ich8lan,
4063         .valid_led_default      = e1000_valid_led_default_ich8lan,
4064         .validate               = e1000_validate_nvm_checksum_ich8lan,
4065         .write                  = e1000_write_nvm_ich8lan,
4066 };
4067
4068 const struct e1000_info e1000_ich8_info = {
4069         .mac                    = e1000_ich8lan,
4070         .flags                  = FLAG_HAS_WOL
4071                                   | FLAG_IS_ICH
4072                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4073                                   | FLAG_HAS_AMT
4074                                   | FLAG_HAS_FLASH
4075                                   | FLAG_APME_IN_WUC,
4076         .pba                    = 8,
4077         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4078         .get_variants           = e1000_get_variants_ich8lan,
4079         .mac_ops                = &ich8_mac_ops,
4080         .phy_ops                = &ich8_phy_ops,
4081         .nvm_ops                = &ich8_nvm_ops,
4082 };
4083
4084 const struct e1000_info e1000_ich9_info = {
4085         .mac                    = e1000_ich9lan,
4086         .flags                  = FLAG_HAS_JUMBO_FRAMES
4087                                   | FLAG_IS_ICH
4088                                   | FLAG_HAS_WOL
4089                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4090                                   | FLAG_HAS_AMT
4091                                   | FLAG_HAS_ERT
4092                                   | FLAG_HAS_FLASH
4093                                   | FLAG_APME_IN_WUC,
4094         .pba                    = 10,
4095         .max_hw_frame_size      = DEFAULT_JUMBO,
4096         .get_variants           = e1000_get_variants_ich8lan,
4097         .mac_ops                = &ich8_mac_ops,
4098         .phy_ops                = &ich8_phy_ops,
4099         .nvm_ops                = &ich8_nvm_ops,
4100 };
4101
4102 const struct e1000_info e1000_ich10_info = {
4103         .mac                    = e1000_ich10lan,
4104         .flags                  = FLAG_HAS_JUMBO_FRAMES
4105                                   | FLAG_IS_ICH
4106                                   | FLAG_HAS_WOL
4107                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4108                                   | FLAG_HAS_AMT
4109                                   | FLAG_HAS_ERT
4110                                   | FLAG_HAS_FLASH
4111                                   | FLAG_APME_IN_WUC,
4112         .pba                    = 10,
4113         .max_hw_frame_size      = DEFAULT_JUMBO,
4114         .get_variants           = e1000_get_variants_ich8lan,
4115         .mac_ops                = &ich8_mac_ops,
4116         .phy_ops                = &ich8_phy_ops,
4117         .nvm_ops                = &ich8_nvm_ops,
4118 };
4119
4120 const struct e1000_info e1000_pch_info = {
4121         .mac                    = e1000_pchlan,
4122         .flags                  = FLAG_IS_ICH
4123                                   | FLAG_HAS_WOL
4124                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4125                                   | FLAG_HAS_AMT
4126                                   | FLAG_HAS_FLASH
4127                                   | FLAG_HAS_JUMBO_FRAMES
4128                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4129                                   | FLAG_APME_IN_WUC,
4130         .flags2                 = FLAG2_HAS_PHY_STATS,
4131         .pba                    = 26,
4132         .max_hw_frame_size      = 4096,
4133         .get_variants           = e1000_get_variants_ich8lan,
4134         .mac_ops                = &ich8_mac_ops,
4135         .phy_ops                = &ich8_phy_ops,
4136         .nvm_ops                = &ich8_nvm_ops,
4137 };
4138
4139 const struct e1000_info e1000_pch2_info = {
4140         .mac                    = e1000_pch2lan,
4141         .flags                  = FLAG_IS_ICH
4142                                   | FLAG_HAS_WOL
4143                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4144                                   | FLAG_HAS_AMT
4145                                   | FLAG_HAS_FLASH
4146                                   | FLAG_HAS_JUMBO_FRAMES
4147                                   | FLAG_APME_IN_WUC,
4148         .flags2                 = FLAG2_HAS_PHY_STATS
4149                                   | FLAG2_HAS_EEE,
4150         .pba                    = 26,
4151         .max_hw_frame_size      = DEFAULT_JUMBO,
4152         .get_variants           = e1000_get_variants_ich8lan,
4153         .mac_ops                = &ich8_mac_ops,
4154         .phy_ops                = &ich8_phy_ops,
4155         .nvm_ops                = &ich8_nvm_ops,
4156 };