drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2012 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 143
 144 /* EMI Registers */
 145 #define I82579_EMI_ADDR         0x10
 146 #define I82579_EMI_DATA         0x11
 147 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 148 #define I82579_MSE_THRESHOLD    0x084F  /* Mean Square Error Threshold */
 149 #define I82579_MSE_LINK_DOWN    0x2411  /* MSE count before dropping link */
 150
 151 /* Strapping Option Register - RO */
 152 #define E1000_STRAP                     0x0000C
 153 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 154 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 155
 156 /* OEM Bits Phy Register */
 157 #define HV_OEM_BITS            PHY_REG(768, 25)
 158 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 159 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 160 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 161
 162 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 163 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 164
 165 /* KMRN Mode Control */
 166 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 167 #define HV_KMRN_MDIO_SLOW      0x0400
 168
 169 /* KMRN FIFO Control and Status */
 170 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 171 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 172 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 173
 174 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 175 /* Offset 04h HSFSTS */
 176 union ich8_hws_flash_status {
 177         struct ich8_hsfsts {
 178                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 179                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 180                 u16 dael       :1; /* bit 2 Direct Access error Log */
 181                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 182                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 183                 u16 reserved1  :2; /* bit 13:6 Reserved */
 184                 u16 reserved2  :6; /* bit 13:6 Reserved */
 185                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 186                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 187         } hsf_status;
 188         u16 regval;
 189 };
 190
 191 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 192 /* Offset 06h FLCTL */
 193 union ich8_hws_flash_ctrl {
 194         struct ich8_hsflctl {
 195                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 196                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 197                 u16 reserved   :5;   /* 7:3 Reserved  */
 198                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 199                 u16 flockdn    :6;   /* 15:10 Reserved */
 200         } hsf_ctrl;
 201         u16 regval;
 202 };
 203
 204 /* ICH Flash Region Access Permissions */
 205 union ich8_hws_flash_regacc {
 206         struct ich8_flracc {
 207                 u32 grra      :8; /* 0:7 GbE region Read Access */
 208                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 209                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 210                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 211         } hsf_flregacc;
 212         u16 regval;
 213 };
 214
 215 /* ICH Flash Protected Region */
 216 union ich8_flash_protected_range {
 217         struct ich8_pr {
 218                 u32 base:13;     /* 0:12 Protected Range Base */
 219                 u32 reserved1:2; /* 13:14 Reserved */
 220                 u32 rpe:1;       /* 15 Read Protection Enable */
 221                 u32 limit:13;    /* 16:28 Protected Range Limit */
 222                 u32 reserved2:2; /* 29:30 Reserved */
 223                 u32 wpe:1;       /* 31 Write Protection Enable */
 224         } range;
 225         u32 regval;
 226 };
 227
 228 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 229 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 230 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 231 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 232 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 233                                                 u32 offset, u8 byte);
 234 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 235                                          u8 *data);
 236 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 237                                          u16 *data);
 238 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 239                                          u8 size, u16 *data);
 240 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 241 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 242 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 244 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 245 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 246 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 247 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 248 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 249 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 250 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 251 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 252 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 253 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 254 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 255 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 256 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 257 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 258 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 259 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 260
 261 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 262 {
 263         return readw(hw->flash_address + reg);
 264 }
 265
 266 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 267 {
 268         return readl(hw->flash_address + reg);
 269 }
 270
 271 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 272 {
 273         writew(val, hw->flash_address + reg);
 274 }
 275
 276 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 277 {
 278         writel(val, hw->flash_address + reg);
 279 }
 280
 281 #define er16flash(reg)          __er16flash(hw, (reg))
 282 #define er32flash(reg)          __er32flash(hw, (reg))
 283 #define ew16flash(reg, val)     __ew16flash(hw, (reg), (val))
 284 #define ew32flash(reg, val)     __ew32flash(hw, (reg), (val))
 285
 286 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 287 {
 288         u32 ctrl;
 289
 290         ctrl = er32(CTRL);
 291         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 292         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 293         ew32(CTRL, ctrl);
 294         e1e_flush();
 295         udelay(10);
 296         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 297         ew32(CTRL, ctrl);
 298 }
 299
 300 /**
 301  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 302  *  @hw: pointer to the HW structure
 303  *
 304  *  Initialize family-specific PHY parameters and function pointers.
 305  **/
 306 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 307 {
 308         struct e1000_phy_info *phy = &hw->phy;
 309         s32 ret_val = 0;
 310
 311         phy->addr                     = 1;
 312         phy->reset_delay_us           = 100;
 313
 314         phy->ops.set_page             = e1000_set_page_igp;
 315         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 316         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 317         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 318         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 319         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 320         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 321         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 322         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 323         phy->ops.power_up             = e1000_power_up_phy_copper;
 324         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 325         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 326
 327         if (!e1000_check_reset_block(hw)) {
 328                 u32 fwsm = er32(FWSM);
 329
 330                 /*
 331                  * The MAC-PHY interconnect may still be in SMBus mode after
 332                  * Sx->S0.  If resetting the PHY is not blocked, toggle the
 333                  * LANPHYPC Value bit to force the interconnect to PCIe mode.
 334                  */
 335                 e1000_toggle_lanphypc_value_ich8lan(hw);
 336                 msleep(50);
 337
 338                 /*
 339                  * Gate automatic PHY configuration by hardware on
 340                  * non-managed 82579
 341                  */
 342                 if ((hw->mac.type == e1000_pch2lan) &&
 343                     !(fwsm & E1000_ICH_FWSM_FW_VALID))
 344                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 345
 346                 /*
 347                  * Reset the PHY before any access to it.  Doing so, ensures
 348                  * that the PHY is in a known good state before we read/write
 349                  * PHY registers.  The generic reset is sufficient here,
 350                  * because we haven't determined the PHY type yet.
 351                  */
 352                 ret_val = e1000e_phy_hw_reset_generic(hw);
 353                 if (ret_val)
 354                         goto out;
 355
 356                 /* Ungate automatic PHY configuration on non-managed 82579 */
 357                 if ((hw->mac.type == e1000_pch2lan) &&
 358                     !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 359                         usleep_range(10000, 20000);
 360                         e1000_gate_hw_phy_config_ich8lan(hw, false);
 361                 }
 362         }
 363
 364         phy->id = e1000_phy_unknown;
 365         switch (hw->mac.type) {
 366         default:
 367                 ret_val = e1000e_get_phy_id(hw);
 368                 if (ret_val)
 369                         goto out;
 370                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 371                         break;
 372                 /* fall-through */
 373         case e1000_pch2lan:
 374                 /*
 375                  * In case the PHY needs to be in mdio slow mode,
 376                  * set slow mode and try to get the PHY id again.
 377                  */
 378                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 379                 if (ret_val)
 380                         goto out;
 381                 ret_val = e1000e_get_phy_id(hw);
 382                 if (ret_val)
 383                         goto out;
 384                 break;
 385         }
 386         phy->type = e1000e_get_phy_type_from_id(phy->id);
 387
 388         switch (phy->type) {
 389         case e1000_phy_82577:
 390         case e1000_phy_82579:
 391                 phy->ops.check_polarity = e1000_check_polarity_82577;
 392                 phy->ops.force_speed_duplex =
 393                     e1000_phy_force_speed_duplex_82577;
 394                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 395                 phy->ops.get_info = e1000_get_phy_info_82577;
 396                 phy->ops.commit = e1000e_phy_sw_reset;
 397                 break;
 398         case e1000_phy_82578:
 399                 phy->ops.check_polarity = e1000_check_polarity_m88;
 400                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 401                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 402                 phy->ops.get_info = e1000e_get_phy_info_m88;
 403                 break;
 404         default:
 405                 ret_val = -E1000_ERR_PHY;
 406                 break;
 407         }
 408
 409 out:
 410         return ret_val;
 411 }
 412
 413 /**
 414  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 415  *  @hw: pointer to the HW structure
 416  *
 417  *  Initialize family-specific PHY parameters and function pointers.
 418  **/
 419 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 420 {
 421         struct e1000_phy_info *phy = &hw->phy;
 422         s32 ret_val;
 423         u16 i = 0;
 424
 425         phy->addr                       = 1;
 426         phy->reset_delay_us             = 100;
 427
 428         phy->ops.power_up               = e1000_power_up_phy_copper;
 429         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 430
 431         /*
 432          * We may need to do this twice - once for IGP and if that fails,
 433          * we'll set BM func pointers and try again
 434          */
 435         ret_val = e1000e_determine_phy_address(hw);
 436         if (ret_val) {
 437                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 438                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 439                 ret_val = e1000e_determine_phy_address(hw);
 440                 if (ret_val) {
 441                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 442                         return ret_val;
 443                 }
 444         }
 445
 446         phy->id = 0;
 447         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 448                (i++ < 100)) {
 449                 usleep_range(1000, 2000);
 450                 ret_val = e1000e_get_phy_id(hw);
 451                 if (ret_val)
 452                         return ret_val;
 453         }
 454
 455         /* Verify phy id */
 456         switch (phy->id) {
 457         case IGP03E1000_E_PHY_ID:
 458                 phy->type = e1000_phy_igp_3;
 459                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 460                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 461                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 462                 phy->ops.get_info = e1000e_get_phy_info_igp;
 463                 phy->ops.check_polarity = e1000_check_polarity_igp;
 464                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 465                 break;
 466         case IFE_E_PHY_ID:
 467         case IFE_PLUS_E_PHY_ID:
 468         case IFE_C_E_PHY_ID:
 469                 phy->type = e1000_phy_ife;
 470                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 471                 phy->ops.get_info = e1000_get_phy_info_ife;
 472                 phy->ops.check_polarity = e1000_check_polarity_ife;
 473                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 474                 break;
 475         case BME1000_E_PHY_ID:
 476                 phy->type = e1000_phy_bm;
 477                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 478                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 479                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 480                 phy->ops.commit = e1000e_phy_sw_reset;
 481                 phy->ops.get_info = e1000e_get_phy_info_m88;
 482                 phy->ops.check_polarity = e1000_check_polarity_m88;
 483                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 484                 break;
 485         default:
 486                 return -E1000_ERR_PHY;
 487                 break;
 488         }
 489
 490         return 0;
 491 }
 492
 493 /**
 494  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 495  *  @hw: pointer to the HW structure
 496  *
 497  *  Initialize family-specific NVM parameters and function
 498  *  pointers.
 499  **/
 500 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 501 {
 502         struct e1000_nvm_info *nvm = &hw->nvm;
 503         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 504         u32 gfpreg, sector_base_addr, sector_end_addr;
 505         u16 i;
 506
 507         /* Can't read flash registers if the register set isn't mapped. */
 508         if (!hw->flash_address) {
 509                 e_dbg("ERROR: Flash registers not mapped\n");
 510                 return -E1000_ERR_CONFIG;
 511         }
 512
 513         nvm->type = e1000_nvm_flash_sw;
 514
 515         gfpreg = er32flash(ICH_FLASH_GFPREG);
 516
 517         /*
 518          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 519          * Add 1 to sector_end_addr since this sector is included in
 520          * the overall size.
 521          */
 522         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 523         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 524
 525         /* flash_base_addr is byte-aligned */
 526         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 527
 528         /*
 529          * find total size of the NVM, then cut in half since the total
 530          * size represents two separate NVM banks.
 531          */
 532         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 533                                 << FLASH_SECTOR_ADDR_SHIFT;
 534         nvm->flash_bank_size /= 2;
 535         /* Adjust to word count */
 536         nvm->flash_bank_size /= sizeof(u16);
 537
 538         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 539
 540         /* Clear shadow ram */
 541         for (i = 0; i < nvm->word_size; i++) {
 542                 dev_spec->shadow_ram[i].modified = false;
 543                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 544         }
 545
 546         return 0;
 547 }
 548
 549 /**
 550  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 551  *  @hw: pointer to the HW structure
 552  *
 553  *  Initialize family-specific MAC parameters and function
 554  *  pointers.
 555  **/
 556 static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
 557 {
 558         struct e1000_mac_info *mac = &hw->mac;
 559
 560         /* Set media type function pointer */
 561         hw->phy.media_type = e1000_media_type_copper;
 562
 563         /* Set mta register count */
 564         mac->mta_reg_count = 32;
 565         /* Set rar entry count */
 566         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 567         if (mac->type == e1000_ich8lan)
 568                 mac->rar_entry_count--;
 569         /* FWSM register */
 570         mac->has_fwsm = true;
 571         /* ARC subsystem not supported */
 572         mac->arc_subsystem_valid = false;
 573         /* Adaptive IFS supported */
 574         mac->adaptive_ifs = true;
 575
 576         /* LED operations */
 577         switch (mac->type) {
 578         case e1000_ich8lan:
 579         case e1000_ich9lan:
 580         case e1000_ich10lan:
 581                 /* check management mode */
 582                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 583                 /* ID LED init */
 584                 mac->ops.id_led_init = e1000e_id_led_init;
 585                 /* blink LED */
 586                 mac->ops.blink_led = e1000e_blink_led_generic;
 587                 /* setup LED */
 588                 mac->ops.setup_led = e1000e_setup_led_generic;
 589                 /* cleanup LED */
 590                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 591                 /* turn on/off LED */
 592                 mac->ops.led_on = e1000_led_on_ich8lan;
 593                 mac->ops.led_off = e1000_led_off_ich8lan;
 594                 break;
 595         case e1000_pchlan:
 596         case e1000_pch2lan:
 597                 /* check management mode */
 598                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 599                 /* ID LED init */
 600                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 601                 /* setup LED */
 602                 mac->ops.setup_led = e1000_setup_led_pchlan;
 603                 /* cleanup LED */
 604                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 605                 /* turn on/off LED */
 606                 mac->ops.led_on = e1000_led_on_pchlan;
 607                 mac->ops.led_off = e1000_led_off_pchlan;
 608                 break;
 609         default:
 610                 break;
 611         }
 612
 613         /* Enable PCS Lock-loss workaround for ICH8 */
 614         if (mac->type == e1000_ich8lan)
 615                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 616
 617         /* Gate automatic PHY configuration by hardware on managed 82579 */
 618         if ((mac->type == e1000_pch2lan) &&
 619             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 620                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 621
 622         return 0;
 623 }
 624
 625 /**
 626  *  e1000_set_eee_pchlan - Enable/disable EEE support
 627  *  @hw: pointer to the HW structure
 628  *
 629  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 630  *  the LPI Control register will remain set only if/when link is up.
 631  **/
 632 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 633 {
 634         s32 ret_val = 0;
 635         u16 phy_reg;
 636
 637         if (hw->phy.type != e1000_phy_82579)
 638                 goto out;
 639
 640         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 641         if (ret_val)
 642                 goto out;
 643
 644         if (hw->dev_spec.ich8lan.eee_disable)
 645                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 646         else
 647                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 648
 649         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 650 out:
 651         return ret_val;
 652 }
 653
 654 /**
 655  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 656  *  @hw: pointer to the HW structure
 657  *
 658  *  Checks to see of the link status of the hardware has changed.  If a
 659  *  change in link status has been detected, then we read the PHY registers
 660  *  to get the current speed/duplex if link exists.
 661  **/
 662 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 663 {
 664         struct e1000_mac_info *mac = &hw->mac;
 665         s32 ret_val;
 666         bool link;
 667         u16 phy_reg;
 668
 669         /*
 670          * We only want to go out to the PHY registers to see if Auto-Neg
 671          * has completed and/or if our link status has changed.  The
 672          * get_link_status flag is set upon receiving a Link Status
 673          * Change or Rx Sequence Error interrupt.
 674          */
 675         if (!mac->get_link_status) {
 676                 ret_val = 0;
 677                 goto out;
 678         }
 679
 680         /*
 681          * First we want to see if the MII Status Register reports
 682          * link.  If so, then we want to get the current speed/duplex
 683          * of the PHY.
 684          */
 685         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 686         if (ret_val)
 687                 goto out;
 688
 689         if (hw->mac.type == e1000_pchlan) {
 690                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 691                 if (ret_val)
 692                         goto out;
 693         }
 694
 695         if (!link)
 696                 goto out; /* No link detected */
 697
 698         mac->get_link_status = false;
 699
 700         switch (hw->mac.type) {
 701         case e1000_pch2lan:
 702                 ret_val = e1000_k1_workaround_lv(hw);
 703                 if (ret_val)
 704                         goto out;
 705                 /* fall-thru */
 706         case e1000_pchlan:
 707                 if (hw->phy.type == e1000_phy_82578) {
 708                         ret_val = e1000_link_stall_workaround_hv(hw);
 709                         if (ret_val)
 710                                 goto out;
 711                 }
 712
 713                 /*
 714                  * Workaround for PCHx parts in half-duplex:
 715                  * Set the number of preambles removed from the packet
 716                  * when it is passed from the PHY to the MAC to prevent
 717                  * the MAC from misinterpreting the packet type.
 718                  */
 719                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 720                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 721
 722                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 723                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 724
 725                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 726                 break;
 727         default:
 728                 break;
 729         }
 730
 731         /*
 732          * Check if there was DownShift, must be checked
 733          * immediately after link-up
 734          */
 735         e1000e_check_downshift(hw);
 736
 737         /* Enable/Disable EEE after link up */
 738         ret_val = e1000_set_eee_pchlan(hw);
 739         if (ret_val)
 740                 goto out;
 741
 742         /*
 743          * If we are forcing speed/duplex, then we simply return since
 744          * we have already determined whether we have link or not.
 745          */
 746         if (!mac->autoneg) {
 747                 ret_val = -E1000_ERR_CONFIG;
 748                 goto out;
 749         }
 750
 751         /*
 752          * Auto-Neg is enabled.  Auto Speed Detection takes care
 753          * of MAC speed/duplex configuration.  So we only need to
 754          * configure Collision Distance in the MAC.
 755          */
 756         e1000e_config_collision_dist(hw);
 757
 758         /*
 759          * Configure Flow Control now that Auto-Neg has completed.
 760          * First, we need to restore the desired flow control
 761          * settings because we may have had to re-autoneg with a
 762          * different link partner.
 763          */
 764         ret_val = e1000e_config_fc_after_link_up(hw);
 765         if (ret_val)
 766                 e_dbg("Error configuring flow control\n");
 767
 768 out:
 769         return ret_val;
 770 }
 771
 772 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 773 {
 774         struct e1000_hw *hw = &adapter->hw;
 775         s32 rc;
 776
 777         rc = e1000_init_mac_params_ich8lan(hw);
 778         if (rc)
 779                 return rc;
 780
 781         rc = e1000_init_nvm_params_ich8lan(hw);
 782         if (rc)
 783                 return rc;
 784
 785         switch (hw->mac.type) {
 786         case e1000_ich8lan:
 787         case e1000_ich9lan:
 788         case e1000_ich10lan:
 789                 rc = e1000_init_phy_params_ich8lan(hw);
 790                 break;
 791         case e1000_pchlan:
 792         case e1000_pch2lan:
 793                 rc = e1000_init_phy_params_pchlan(hw);
 794                 break;
 795         default:
 796                 break;
 797         }
 798         if (rc)
 799                 return rc;
 800
 801         /*
 802          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 803          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 804          */
 805         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 806             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 807              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 808                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 809                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 810
 811                 hw->mac.ops.blink_led = NULL;
 812         }
 813
 814         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 815             (adapter->hw.phy.type != e1000_phy_ife))
 816                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 817
 818         /* Enable workaround for 82579 w/ ME enabled */
 819         if ((adapter->hw.mac.type == e1000_pch2lan) &&
 820             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 821                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
 822
 823         /* Disable EEE by default until IEEE802.3az spec is finalized */
 824         if (adapter->flags2 & FLAG2_HAS_EEE)
 825                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 826
 827         return 0;
 828 }
 829
 830 static DEFINE_MUTEX(nvm_mutex);
 831
 832 /**
 833  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 834  *  @hw: pointer to the HW structure
 835  *
 836  *  Acquires the mutex for performing NVM operations.
 837  **/
 838 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 839 {
 840         mutex_lock(&nvm_mutex);
 841
 842         return 0;
 843 }
 844
 845 /**
 846  *  e1000_release_nvm_ich8lan - Release NVM mutex
 847  *  @hw: pointer to the HW structure
 848  *
 849  *  Releases the mutex used while performing NVM operations.
 850  **/
 851 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 852 {
 853         mutex_unlock(&nvm_mutex);
 854 }
 855
 856 /**
 857  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 858  *  @hw: pointer to the HW structure
 859  *
 860  *  Acquires the software control flag for performing PHY and select
 861  *  MAC CSR accesses.
 862  **/
 863 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 864 {
 865         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 866         s32 ret_val = 0;
 867
 868         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
 869                              &hw->adapter->state)) {
 870                 e_dbg("contention for Phy access\n");
 871                 return -E1000_ERR_PHY;
 872         }
 873
 874         while (timeout) {
 875                 extcnf_ctrl = er32(EXTCNF_CTRL);
 876                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 877                         break;
 878
 879                 mdelay(1);
 880                 timeout--;
 881         }
 882
 883         if (!timeout) {
 884                 e_dbg("SW has already locked the resource.\n");
 885                 ret_val = -E1000_ERR_CONFIG;
 886                 goto out;
 887         }
 888
 889         timeout = SW_FLAG_TIMEOUT;
 890
 891         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 892         ew32(EXTCNF_CTRL, extcnf_ctrl);
 893
 894         while (timeout) {
 895                 extcnf_ctrl = er32(EXTCNF_CTRL);
 896                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 897                         break;
 898
 899                 mdelay(1);
 900                 timeout--;
 901         }
 902
 903         if (!timeout) {
 904                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
 905                       er32(FWSM), extcnf_ctrl);
 906                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 907                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 908                 ret_val = -E1000_ERR_CONFIG;
 909                 goto out;
 910         }
 911
 912 out:
 913         if (ret_val)
 914                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 915
 916         return ret_val;
 917 }
 918
 919 /**
 920  *  e1000_release_swflag_ich8lan - Release software control flag
 921  *  @hw: pointer to the HW structure
 922  *
 923  *  Releases the software control flag for performing PHY and select
 924  *  MAC CSR accesses.
 925  **/
 926 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 927 {
 928         u32 extcnf_ctrl;
 929
 930         extcnf_ctrl = er32(EXTCNF_CTRL);
 931
 932         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 933                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 934                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 935         } else {
 936                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 937         }
 938
 939         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 940 }
 941
 942 /**
 943  *  e1000_check_mng_mode_ich8lan - Checks management mode
 944  *  @hw: pointer to the HW structure
 945  *
 946  *  This checks if the adapter has any manageability enabled.
 947  *  This is a function pointer entry point only called by read/write
 948  *  routines for the PHY and NVM parts.
 949  **/
 950 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 951 {
 952         u32 fwsm;
 953
 954         fwsm = er32(FWSM);
 955         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 956                ((fwsm & E1000_FWSM_MODE_MASK) ==
 957                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 958 }
 959
 960 /**
 961  *  e1000_check_mng_mode_pchlan - Checks management mode
 962  *  @hw: pointer to the HW structure
 963  *
 964  *  This checks if the adapter has iAMT enabled.
 965  *  This is a function pointer entry point only called by read/write
 966  *  routines for the PHY and NVM parts.
 967  **/
 968 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 969 {
 970         u32 fwsm;
 971
 972         fwsm = er32(FWSM);
 973         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 974                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 975 }
 976
 977 /**
 978  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 979  *  @hw: pointer to the HW structure
 980  *
 981  *  Checks if firmware is blocking the reset of the PHY.
 982  *  This is a function pointer entry point only called by
 983  *  reset routines.
 984  **/
 985 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 986 {
 987         u32 fwsm;
 988
 989         fwsm = er32(FWSM);
 990
 991         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 992 }
 993
 994 /**
 995  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 996  *  @hw: pointer to the HW structure
 997  *
 998  *  Assumes semaphore already acquired.
 999  *
1000  **/
1001 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1002 {
1003         u16 phy_data;
1004         u32 strap = er32(STRAP);
1005         s32 ret_val = 0;
1006
1007         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1008
1009         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1010         if (ret_val)
1011                 goto out;
1012
1013         phy_data &= ~HV_SMB_ADDR_MASK;
1014         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1015         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1016         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1017
1018 out:
1019         return ret_val;
1020 }
1021
1022 /**
1023  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1024  *  @hw:   pointer to the HW structure
1025  *
1026  *  SW should configure the LCD from the NVM extended configuration region
1027  *  as a workaround for certain parts.
1028  **/
1029 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1030 {
1031         struct e1000_phy_info *phy = &hw->phy;
1032         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1033         s32 ret_val = 0;
1034         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1035
1036         /*
1037          * Initialize the PHY from the NVM on ICH platforms.  This
1038          * is needed due to an issue where the NVM configuration is
1039          * not properly autoloaded after power transitions.
1040          * Therefore, after each PHY reset, we will load the
1041          * configuration data out of the NVM manually.
1042          */
1043         switch (hw->mac.type) {
1044         case e1000_ich8lan:
1045                 if (phy->type != e1000_phy_igp_3)
1046                         return ret_val;
1047
1048                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1049                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1050                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1051                         break;
1052                 }
1053                 /* Fall-thru */
1054         case e1000_pchlan:
1055         case e1000_pch2lan:
1056                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1057                 break;
1058         default:
1059                 return ret_val;
1060         }
1061
1062         ret_val = hw->phy.ops.acquire(hw);
1063         if (ret_val)
1064                 return ret_val;
1065
1066         data = er32(FEXTNVM);
1067         if (!(data & sw_cfg_mask))
1068                 goto release;
1069
1070         /*
1071          * Make sure HW does not configure LCD from PHY
1072          * extended configuration before SW configuration
1073          */
1074         data = er32(EXTCNF_CTRL);
1075         if (!(hw->mac.type == e1000_pch2lan)) {
1076                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1077                         goto release;
1078         }
1079
1080         cnf_size = er32(EXTCNF_SIZE);
1081         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1082         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1083         if (!cnf_size)
1084                 goto release;
1085
1086         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1087         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1088
1089         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1090             (hw->mac.type == e1000_pchlan)) ||
1091              (hw->mac.type == e1000_pch2lan)) {
1092                 /*
1093                  * HW configures the SMBus address and LEDs when the
1094                  * OEM and LCD Write Enable bits are set in the NVM.
1095                  * When both NVM bits are cleared, SW will configure
1096                  * them instead.
1097                  */
1098                 ret_val = e1000_write_smbus_addr(hw);
1099                 if (ret_val)
1100                         goto release;
1101
1102                 data = er32(LEDCTL);
1103                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1104                                                         (u16)data);
1105                 if (ret_val)
1106                         goto release;
1107         }
1108
1109         /* Configure LCD from extended configuration region. */
1110
1111         /* cnf_base_addr is in DWORD */
1112         word_addr = (u16)(cnf_base_addr << 1);
1113
1114         for (i = 0; i < cnf_size; i++) {
1115                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1116                                          &reg_data);
1117                 if (ret_val)
1118                         goto release;
1119
1120                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1121                                          1, &reg_addr);
1122                 if (ret_val)
1123                         goto release;
1124
1125                 /* Save off the PHY page for future writes. */
1126                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1127                         phy_page = reg_data;
1128                         continue;
1129                 }
1130
1131                 reg_addr &= PHY_REG_MASK;
1132                 reg_addr |= phy_page;
1133
1134                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1135                                                     reg_data);
1136                 if (ret_val)
1137                         goto release;
1138         }
1139
1140 release:
1141         hw->phy.ops.release(hw);
1142         return ret_val;
1143 }
1144
1145 /**
1146  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1147  *  @hw:   pointer to the HW structure
1148  *  @link: link up bool flag
1149  *
1150  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1151  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1152  *  If link is down, the function will restore the default K1 setting located
1153  *  in the NVM.
1154  **/
1155 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1156 {
1157         s32 ret_val = 0;
1158         u16 status_reg = 0;
1159         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1160
1161         if (hw->mac.type != e1000_pchlan)
1162                 goto out;
1163
1164         /* Wrap the whole flow with the sw flag */
1165         ret_val = hw->phy.ops.acquire(hw);
1166         if (ret_val)
1167                 goto out;
1168
1169         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1170         if (link) {
1171                 if (hw->phy.type == e1000_phy_82578) {
1172                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1173                                                                   &status_reg);
1174                         if (ret_val)
1175                                 goto release;
1176
1177                         status_reg &= BM_CS_STATUS_LINK_UP |
1178                                       BM_CS_STATUS_RESOLVED |
1179                                       BM_CS_STATUS_SPEED_MASK;
1180
1181                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1182                                            BM_CS_STATUS_RESOLVED |
1183                                            BM_CS_STATUS_SPEED_1000))
1184                                 k1_enable = false;
1185                 }
1186
1187                 if (hw->phy.type == e1000_phy_82577) {
1188                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1189                                                                   &status_reg);
1190                         if (ret_val)
1191                                 goto release;
1192
1193                         status_reg &= HV_M_STATUS_LINK_UP |
1194                                       HV_M_STATUS_AUTONEG_COMPLETE |
1195                                       HV_M_STATUS_SPEED_MASK;
1196
1197                         if (status_reg == (HV_M_STATUS_LINK_UP |
1198                                            HV_M_STATUS_AUTONEG_COMPLETE |
1199                                            HV_M_STATUS_SPEED_1000))
1200                                 k1_enable = false;
1201                 }
1202
1203                 /* Link stall fix for link up */
1204                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1205                                                            0x0100);
1206                 if (ret_val)
1207                         goto release;
1208
1209         } else {
1210                 /* Link stall fix for link down */
1211                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1212                                                            0x4100);
1213                 if (ret_val)
1214                         goto release;
1215         }
1216
1217         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1218
1219 release:
1220         hw->phy.ops.release(hw);
1221 out:
1222         return ret_val;
1223 }
1224
1225 /**
1226  *  e1000_configure_k1_ich8lan - Configure K1 power state
1227  *  @hw: pointer to the HW structure
1228  *  @enable: K1 state to configure
1229  *
1230  *  Configure the K1 power state based on the provided parameter.
1231  *  Assumes semaphore already acquired.
1232  *
1233  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1234  **/
1235 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1236 {
1237         s32 ret_val = 0;
1238         u32 ctrl_reg = 0;
1239         u32 ctrl_ext = 0;
1240         u32 reg = 0;
1241         u16 kmrn_reg = 0;
1242
1243         ret_val = e1000e_read_kmrn_reg_locked(hw,
1244                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1245                                              &kmrn_reg);
1246         if (ret_val)
1247                 goto out;
1248
1249         if (k1_enable)
1250                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1251         else
1252                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1253
1254         ret_val = e1000e_write_kmrn_reg_locked(hw,
1255                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1256                                               kmrn_reg);
1257         if (ret_val)
1258                 goto out;
1259
1260         udelay(20);
1261         ctrl_ext = er32(CTRL_EXT);
1262         ctrl_reg = er32(CTRL);
1263
1264         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1265         reg |= E1000_CTRL_FRCSPD;
1266         ew32(CTRL, reg);
1267
1268         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1269         e1e_flush();
1270         udelay(20);
1271         ew32(CTRL, ctrl_reg);
1272         ew32(CTRL_EXT, ctrl_ext);
1273         e1e_flush();
1274         udelay(20);
1275
1276 out:
1277         return ret_val;
1278 }
1279
1280 /**
1281  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1282  *  @hw:       pointer to the HW structure
1283  *  @d0_state: boolean if entering d0 or d3 device state
1284  *
1285  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1286  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1287  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1288  **/
1289 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1290 {
1291         s32 ret_val = 0;
1292         u32 mac_reg;
1293         u16 oem_reg;
1294
1295         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1296                 return ret_val;
1297
1298         ret_val = hw->phy.ops.acquire(hw);
1299         if (ret_val)
1300                 return ret_val;
1301
1302         if (!(hw->mac.type == e1000_pch2lan)) {
1303                 mac_reg = er32(EXTCNF_CTRL);
1304                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1305                         goto release;
1306         }
1307
1308         mac_reg = er32(FEXTNVM);
1309         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1310                 goto release;
1311
1312         mac_reg = er32(PHY_CTRL);
1313
1314         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1315         if (ret_val)
1316                 goto release;
1317
1318         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1319
1320         if (d0_state) {
1321                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1322                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1323
1324                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1325                         oem_reg |= HV_OEM_BITS_LPLU;
1326
1327                 /* Set Restart auto-neg to activate the bits */
1328                 if (!e1000_check_reset_block(hw))
1329                         oem_reg |= HV_OEM_BITS_RESTART_AN;
1330         } else {
1331                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1332                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1333                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1334
1335                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1336                                E1000_PHY_CTRL_NOND0A_LPLU))
1337                         oem_reg |= HV_OEM_BITS_LPLU;
1338         }
1339
1340         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1341
1342 release:
1343         hw->phy.ops.release(hw);
1344
1345         return ret_val;
1346 }
1347
1348
1349 /**
1350  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1351  *  @hw:   pointer to the HW structure
1352  **/
1353 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1354 {
1355         s32 ret_val;
1356         u16 data;
1357
1358         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1359         if (ret_val)
1360                 return ret_val;
1361
1362         data |= HV_KMRN_MDIO_SLOW;
1363
1364         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1365
1366         return ret_val;
1367 }
1368
1369 /**
1370  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1371  *  done after every PHY reset.
1372  **/
1373 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1374 {
1375         s32 ret_val = 0;
1376         u16 phy_data;
1377
1378         if (hw->mac.type != e1000_pchlan)
1379                 return ret_val;
1380
1381         /* Set MDIO slow mode before any other MDIO access */
1382         if (hw->phy.type == e1000_phy_82577) {
1383                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1384                 if (ret_val)
1385                         goto out;
1386         }
1387
1388         if (((hw->phy.type == e1000_phy_82577) &&
1389              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1390             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1391                 /* Disable generation of early preamble */
1392                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1393                 if (ret_val)
1394                         return ret_val;
1395
1396                 /* Preamble tuning for SSC */
1397                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1398                 if (ret_val)
1399                         return ret_val;
1400         }
1401
1402         if (hw->phy.type == e1000_phy_82578) {
1403                 /*
1404                  * Return registers to default by doing a soft reset then
1405                  * writing 0x3140 to the control register.
1406                  */
1407                 if (hw->phy.revision < 2) {
1408                         e1000e_phy_sw_reset(hw);
1409                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1410                 }
1411         }
1412
1413         /* Select page 0 */
1414         ret_val = hw->phy.ops.acquire(hw);
1415         if (ret_val)
1416                 return ret_val;
1417
1418         hw->phy.addr = 1;
1419         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1420         hw->phy.ops.release(hw);
1421         if (ret_val)
1422                 goto out;
1423
1424         /*
1425          * Configure the K1 Si workaround during phy reset assuming there is
1426          * link so that it disables K1 if link is in 1Gbps.
1427          */
1428         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1429         if (ret_val)
1430                 goto out;
1431
1432         /* Workaround for link disconnects on a busy hub in half duplex */
1433         ret_val = hw->phy.ops.acquire(hw);
1434         if (ret_val)
1435                 goto out;
1436         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1437         if (ret_val)
1438                 goto release;
1439         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1440                                                phy_data & 0x00FF);
1441 release:
1442         hw->phy.ops.release(hw);
1443 out:
1444         return ret_val;
1445 }
1446
1447 /**
1448  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1449  *  @hw:   pointer to the HW structure
1450  **/
1451 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1452 {
1453         u32 mac_reg;
1454         u16 i, phy_reg = 0;
1455         s32 ret_val;
1456
1457         ret_val = hw->phy.ops.acquire(hw);
1458         if (ret_val)
1459                 return;
1460         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1461         if (ret_val)
1462                 goto release;
1463
1464         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1465         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1466                 mac_reg = er32(RAL(i));
1467                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1468                                            (u16)(mac_reg & 0xFFFF));
1469                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1470                                            (u16)((mac_reg >> 16) & 0xFFFF));
1471
1472                 mac_reg = er32(RAH(i));
1473                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1474                                            (u16)(mac_reg & 0xFFFF));
1475                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1476                                            (u16)((mac_reg & E1000_RAH_AV)
1477                                                  >> 16));
1478         }
1479
1480         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1481
1482 release:
1483         hw->phy.ops.release(hw);
1484 }
1485
1486 /**
1487  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1488  *  with 82579 PHY
1489  *  @hw: pointer to the HW structure
1490  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1491  **/
1492 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1493 {
1494         s32 ret_val = 0;
1495         u16 phy_reg, data;
1496         u32 mac_reg;
1497         u16 i;
1498
1499         if (hw->mac.type != e1000_pch2lan)
1500                 goto out;
1501
1502         /* disable Rx path while enabling/disabling workaround */
1503         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1504         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1505         if (ret_val)
1506                 goto out;
1507
1508         if (enable) {
1509                 /*
1510                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1511                  * SHRAL/H) and initial CRC values to the MAC
1512                  */
1513                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1514                         u8 mac_addr[ETH_ALEN] = {0};
1515                         u32 addr_high, addr_low;
1516
1517                         addr_high = er32(RAH(i));
1518                         if (!(addr_high & E1000_RAH_AV))
1519                                 continue;
1520                         addr_low = er32(RAL(i));
1521                         mac_addr[0] = (addr_low & 0xFF);
1522                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1523                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1524                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1525                         mac_addr[4] = (addr_high & 0xFF);
1526                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1527
1528                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1529                 }
1530
1531                 /* Write Rx addresses to the PHY */
1532                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1533
1534                 /* Enable jumbo frame workaround in the MAC */
1535                 mac_reg = er32(FFLT_DBG);
1536                 mac_reg &= ~(1 << 14);
1537                 mac_reg |= (7 << 15);
1538                 ew32(FFLT_DBG, mac_reg);
1539
1540                 mac_reg = er32(RCTL);
1541                 mac_reg |= E1000_RCTL_SECRC;
1542                 ew32(RCTL, mac_reg);
1543
1544                 ret_val = e1000e_read_kmrn_reg(hw,
1545                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1546                                                 &data);
1547                 if (ret_val)
1548                         goto out;
1549                 ret_val = e1000e_write_kmrn_reg(hw,
1550                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1551                                                 data | (1 << 0));
1552                 if (ret_val)
1553                         goto out;
1554                 ret_val = e1000e_read_kmrn_reg(hw,
1555                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1556                                                 &data);
1557                 if (ret_val)
1558                         goto out;
1559                 data &= ~(0xF << 8);
1560                 data |= (0xB << 8);
1561                 ret_val = e1000e_write_kmrn_reg(hw,
1562                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1563                                                 data);
1564                 if (ret_val)
1565                         goto out;
1566
1567                 /* Enable jumbo frame workaround in the PHY */
1568                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1569                 data &= ~(0x7F << 5);
1570                 data |= (0x37 << 5);
1571                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1572                 if (ret_val)
1573                         goto out;
1574                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1575                 data &= ~(1 << 13);
1576                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1577                 if (ret_val)
1578                         goto out;
1579                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1580                 data &= ~(0x3FF << 2);
1581                 data |= (0x1A << 2);
1582                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1583                 if (ret_val)
1584                         goto out;
1585                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1586                 if (ret_val)
1587                         goto out;
1588                 e1e_rphy(hw, HV_PM_CTRL, &data);
1589                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1590                 if (ret_val)
1591                         goto out;
1592         } else {
1593                 /* Write MAC register values back to h/w defaults */
1594                 mac_reg = er32(FFLT_DBG);
1595                 mac_reg &= ~(0xF << 14);
1596                 ew32(FFLT_DBG, mac_reg);
1597
1598                 mac_reg = er32(RCTL);
1599                 mac_reg &= ~E1000_RCTL_SECRC;
1600                 ew32(RCTL, mac_reg);
1601
1602                 ret_val = e1000e_read_kmrn_reg(hw,
1603                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1604                                                 &data);
1605                 if (ret_val)
1606                         goto out;
1607                 ret_val = e1000e_write_kmrn_reg(hw,
1608                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1609                                                 data & ~(1 << 0));
1610                 if (ret_val)
1611                         goto out;
1612                 ret_val = e1000e_read_kmrn_reg(hw,
1613                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1614                                                 &data);
1615                 if (ret_val)
1616                         goto out;
1617                 data &= ~(0xF << 8);
1618                 data |= (0xB << 8);
1619                 ret_val = e1000e_write_kmrn_reg(hw,
1620                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1621                                                 data);
1622                 if (ret_val)
1623                         goto out;
1624
1625                 /* Write PHY register values back to h/w defaults */
1626                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1627                 data &= ~(0x7F << 5);
1628                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1629                 if (ret_val)
1630                         goto out;
1631                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1632                 data |= (1 << 13);
1633                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1634                 if (ret_val)
1635                         goto out;
1636                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1637                 data &= ~(0x3FF << 2);
1638                 data |= (0x8 << 2);
1639                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1640                 if (ret_val)
1641                         goto out;
1642                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1643                 if (ret_val)
1644                         goto out;
1645                 e1e_rphy(hw, HV_PM_CTRL, &data);
1646                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1647                 if (ret_val)
1648                         goto out;
1649         }
1650
1651         /* re-enable Rx path after enabling/disabling workaround */
1652         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1653
1654 out:
1655         return ret_val;
1656 }
1657
1658 /**
1659  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1660  *  done after every PHY reset.
1661  **/
1662 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1663 {
1664         s32 ret_val = 0;
1665
1666         if (hw->mac.type != e1000_pch2lan)
1667                 goto out;
1668
1669         /* Set MDIO slow mode before any other MDIO access */
1670         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1671
1672         ret_val = hw->phy.ops.acquire(hw);
1673         if (ret_val)
1674                 goto out;
1675         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1676                                                I82579_MSE_THRESHOLD);
1677         if (ret_val)
1678                 goto release;
1679         /* set MSE higher to enable link to stay up when noise is high */
1680         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034);
1681         if (ret_val)
1682                 goto release;
1683         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1684                                                I82579_MSE_LINK_DOWN);
1685         if (ret_val)
1686                 goto release;
1687         /* drop link after 5 times MSE threshold was reached */
1688         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005);
1689 release:
1690         hw->phy.ops.release(hw);
1691
1692 out:
1693         return ret_val;
1694 }
1695
1696 /**
1697  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1698  *  @hw:   pointer to the HW structure
1699  *
1700  *  Workaround to set the K1 beacon duration for 82579 parts
1701  **/
1702 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1703 {
1704         s32 ret_val = 0;
1705         u16 status_reg = 0;
1706         u32 mac_reg;
1707         u16 phy_reg;
1708
1709         if (hw->mac.type != e1000_pch2lan)
1710                 goto out;
1711
1712         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1713         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1714         if (ret_val)
1715                 goto out;
1716
1717         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1718             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1719                 mac_reg = er32(FEXTNVM4);
1720                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1721
1722                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1723                 if (ret_val)
1724                         goto out;
1725
1726                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1727                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1728                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1729                 } else {
1730                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1731                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1732                 }
1733                 ew32(FEXTNVM4, mac_reg);
1734                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1735         }
1736
1737 out:
1738         return ret_val;
1739 }
1740
1741 /**
1742  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1743  *  @hw:   pointer to the HW structure
1744  *  @gate: boolean set to true to gate, false to ungate
1745  *
1746  *  Gate/ungate the automatic PHY configuration via hardware; perform
1747  *  the configuration via software instead.
1748  **/
1749 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1750 {
1751         u32 extcnf_ctrl;
1752
1753         if (hw->mac.type != e1000_pch2lan)
1754                 return;
1755
1756         extcnf_ctrl = er32(EXTCNF_CTRL);
1757
1758         if (gate)
1759                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1760         else
1761                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1762
1763         ew32(EXTCNF_CTRL, extcnf_ctrl);
1764 }
1765
1766 /**
1767  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1768  *  @hw: pointer to the HW structure
1769  *
1770  *  Check the appropriate indication the MAC has finished configuring the
1771  *  PHY after a software reset.
1772  **/
1773 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1774 {
1775         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1776
1777         /* Wait for basic configuration completes before proceeding */
1778         do {
1779                 data = er32(STATUS);
1780                 data &= E1000_STATUS_LAN_INIT_DONE;
1781                 udelay(100);
1782         } while ((!data) && --loop);
1783
1784         /*
1785          * If basic configuration is incomplete before the above loop
1786          * count reaches 0, loading the configuration from NVM will
1787          * leave the PHY in a bad state possibly resulting in no link.
1788          */
1789         if (loop == 0)
1790                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1791
1792         /* Clear the Init Done bit for the next init event */
1793         data = er32(STATUS);
1794         data &= ~E1000_STATUS_LAN_INIT_DONE;
1795         ew32(STATUS, data);
1796 }
1797
1798 /**
1799  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1800  *  @hw: pointer to the HW structure
1801  **/
1802 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1803 {
1804         s32 ret_val = 0;
1805         u16 reg;
1806
1807         if (e1000_check_reset_block(hw))
1808                 goto out;
1809
1810         /* Allow time for h/w to get to quiescent state after reset */
1811         usleep_range(10000, 20000);
1812
1813         /* Perform any necessary post-reset workarounds */
1814         switch (hw->mac.type) {
1815         case e1000_pchlan:
1816                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1817                 if (ret_val)
1818                         goto out;
1819                 break;
1820         case e1000_pch2lan:
1821                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1822                 if (ret_val)
1823                         goto out;
1824                 break;
1825         default:
1826                 break;
1827         }
1828
1829         /* Clear the host wakeup bit after lcd reset */
1830         if (hw->mac.type >= e1000_pchlan) {
1831                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1832                 reg &= ~BM_WUC_HOST_WU_BIT;
1833                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1834         }
1835
1836         /* Configure the LCD with the extended configuration region in NVM */
1837         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1838         if (ret_val)
1839                 goto out;
1840
1841         /* Configure the LCD with the OEM bits in NVM */
1842         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1843
1844         if (hw->mac.type == e1000_pch2lan) {
1845                 /* Ungate automatic PHY configuration on non-managed 82579 */
1846                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1847                         usleep_range(10000, 20000);
1848                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1849                 }
1850
1851                 /* Set EEE LPI Update Timer to 200usec */
1852                 ret_val = hw->phy.ops.acquire(hw);
1853                 if (ret_val)
1854                         goto out;
1855                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1856                                                        I82579_LPI_UPDATE_TIMER);
1857                 if (ret_val)
1858                         goto release;
1859                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1860                                                        0x1387);
1861 release:
1862                 hw->phy.ops.release(hw);
1863         }
1864
1865 out:
1866         return ret_val;
1867 }
1868
1869 /**
1870  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1871  *  @hw: pointer to the HW structure
1872  *
1873  *  Resets the PHY
1874  *  This is a function pointer entry point called by drivers
1875  *  or other shared routines.
1876  **/
1877 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1878 {
1879         s32 ret_val = 0;
1880
1881         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1882         if ((hw->mac.type == e1000_pch2lan) &&
1883             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1884                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1885
1886         ret_val = e1000e_phy_hw_reset_generic(hw);
1887         if (ret_val)
1888                 goto out;
1889
1890         ret_val = e1000_post_phy_reset_ich8lan(hw);
1891
1892 out:
1893         return ret_val;
1894 }
1895
1896 /**
1897  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1898  *  @hw: pointer to the HW structure
1899  *  @active: true to enable LPLU, false to disable
1900  *
1901  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1902  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1903  *  the phy speed. This function will manually set the LPLU bit and restart
1904  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1905  *  since it configures the same bit.
1906  **/
1907 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1908 {
1909         s32 ret_val = 0;
1910         u16 oem_reg;
1911
1912         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1913         if (ret_val)
1914                 goto out;
1915
1916         if (active)
1917                 oem_reg |= HV_OEM_BITS_LPLU;
1918         else
1919                 oem_reg &= ~HV_OEM_BITS_LPLU;
1920
1921         if (!e1000_check_reset_block(hw))
1922                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1923
1924         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1925
1926 out:
1927         return ret_val;
1928 }
1929
1930 /**
1931  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1932  *  @hw: pointer to the HW structure
1933  *  @active: true to enable LPLU, false to disable
1934  *
1935  *  Sets the LPLU D0 state according to the active flag.  When
1936  *  activating LPLU this function also disables smart speed
1937  *  and vice versa.  LPLU will not be activated unless the
1938  *  device autonegotiation advertisement meets standards of
1939  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1940  *  This is a function pointer entry point only called by
1941  *  PHY setup routines.
1942  **/
1943 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1944 {
1945         struct e1000_phy_info *phy = &hw->phy;
1946         u32 phy_ctrl;
1947         s32 ret_val = 0;
1948         u16 data;
1949
1950         if (phy->type == e1000_phy_ife)
1951                 return 0;
1952
1953         phy_ctrl = er32(PHY_CTRL);
1954
1955         if (active) {
1956                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1957                 ew32(PHY_CTRL, phy_ctrl);
1958
1959                 if (phy->type != e1000_phy_igp_3)
1960                         return 0;
1961
1962                 /*
1963                  * Call gig speed drop workaround on LPLU before accessing
1964                  * any PHY registers
1965                  */
1966                 if (hw->mac.type == e1000_ich8lan)
1967                         e1000e_gig_downshift_workaround_ich8lan(hw);
1968
1969                 /* When LPLU is enabled, we should disable SmartSpeed */
1970                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1971                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1972                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1973                 if (ret_val)
1974                         return ret_val;
1975         } else {
1976                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1977                 ew32(PHY_CTRL, phy_ctrl);
1978
1979                 if (phy->type != e1000_phy_igp_3)
1980                         return 0;
1981
1982                 /*
1983                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1984                  * during Dx states where the power conservation is most
1985                  * important.  During driver activity we should enable
1986                  * SmartSpeed, so performance is maintained.
1987                  */
1988                 if (phy->smart_speed == e1000_smart_speed_on) {
1989                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1990                                            &data);
1991                         if (ret_val)
1992                                 return ret_val;
1993
1994                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1995                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1996                                            data);
1997                         if (ret_val)
1998                                 return ret_val;
1999                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2000                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2001                                            &data);
2002                         if (ret_val)
2003                                 return ret_val;
2004
2005                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2006                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2007                                            data);
2008                         if (ret_val)
2009                                 return ret_val;
2010                 }
2011         }
2012
2013         return 0;
2014 }
2015
2016 /**
2017  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2018  *  @hw: pointer to the HW structure
2019  *  @active: true to enable LPLU, false to disable
2020  *
2021  *  Sets the LPLU D3 state according to the active flag.  When
2022  *  activating LPLU this function also disables smart speed
2023  *  and vice versa.  LPLU will not be activated unless the
2024  *  device autonegotiation advertisement meets standards of
2025  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2026  *  This is a function pointer entry point only called by
2027  *  PHY setup routines.
2028  **/
2029 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2030 {
2031         struct e1000_phy_info *phy = &hw->phy;
2032         u32 phy_ctrl;
2033         s32 ret_val = 0;
2034         u16 data;
2035
2036         phy_ctrl = er32(PHY_CTRL);
2037
2038         if (!active) {
2039                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2040                 ew32(PHY_CTRL, phy_ctrl);
2041
2042                 if (phy->type != e1000_phy_igp_3)
2043                         return 0;
2044
2045                 /*
2046                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2047                  * during Dx states where the power conservation is most
2048                  * important.  During driver activity we should enable
2049                  * SmartSpeed, so performance is maintained.
2050                  */
2051                 if (phy->smart_speed == e1000_smart_speed_on) {
2052                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2053                                            &data);
2054                         if (ret_val)
2055                                 return ret_val;
2056
2057                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2058                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2059                                            data);
2060                         if (ret_val)
2061                                 return ret_val;
2062                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2063                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2064                                            &data);
2065                         if (ret_val)
2066                                 return ret_val;
2067
2068                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2069                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2070                                            data);
2071                         if (ret_val)
2072                                 return ret_val;
2073                 }
2074         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2075                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2076                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2077                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2078                 ew32(PHY_CTRL, phy_ctrl);
2079
2080                 if (phy->type != e1000_phy_igp_3)
2081                         return 0;
2082
2083                 /*
2084                  * Call gig speed drop workaround on LPLU before accessing
2085                  * any PHY registers
2086                  */
2087                 if (hw->mac.type == e1000_ich8lan)
2088                         e1000e_gig_downshift_workaround_ich8lan(hw);
2089
2090                 /* When LPLU is enabled, we should disable SmartSpeed */
2091                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2092                 if (ret_val)
2093                         return ret_val;
2094
2095                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2096                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2097         }
2098
2099         return ret_val;
2100 }
2101
2102 /**
2103  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2104  *  @hw: pointer to the HW structure
2105  *  @bank:  pointer to the variable that returns the active bank
2106  *
2107  *  Reads signature byte from the NVM using the flash access registers.
2108  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2109  **/
2110 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2111 {
2112         u32 eecd;
2113         struct e1000_nvm_info *nvm = &hw->nvm;
2114         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2115         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2116         u8 sig_byte = 0;
2117         s32 ret_val = 0;
2118
2119         switch (hw->mac.type) {
2120         case e1000_ich8lan:
2121         case e1000_ich9lan:
2122                 eecd = er32(EECD);
2123                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2124                     E1000_EECD_SEC1VAL_VALID_MASK) {
2125                         if (eecd & E1000_EECD_SEC1VAL)
2126                                 *bank = 1;
2127                         else
2128                                 *bank = 0;
2129
2130                         return 0;
2131                 }
2132                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2133                 /* fall-thru */
2134         default:
2135                 /* set bank to 0 in case flash read fails */
2136                 *bank = 0;
2137
2138                 /* Check bank 0 */
2139                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2140                                                         &sig_byte);
2141                 if (ret_val)
2142                         return ret_val;
2143                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2144                     E1000_ICH_NVM_SIG_VALUE) {
2145                         *bank = 0;
2146                         return 0;
2147                 }
2148
2149                 /* Check bank 1 */
2150                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2151                                                         bank1_offset,
2152                                                         &sig_byte);
2153                 if (ret_val)
2154                         return ret_val;
2155                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2156                     E1000_ICH_NVM_SIG_VALUE) {
2157                         *bank = 1;
2158                         return 0;
2159                 }
2160
2161                 e_dbg("ERROR: No valid NVM bank present\n");
2162                 return -E1000_ERR_NVM;
2163         }
2164
2165         return 0;
2166 }
2167
2168 /**
2169  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2170  *  @hw: pointer to the HW structure
2171  *  @offset: The offset (in bytes) of the word(s) to read.
2172  *  @words: Size of data to read in words
2173  *  @data: Pointer to the word(s) to read at offset.
2174  *
2175  *  Reads a word(s) from the NVM using the flash access registers.
2176  **/
2177 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2178                                   u16 *data)
2179 {
2180         struct e1000_nvm_info *nvm = &hw->nvm;
2181         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2182         u32 act_offset;
2183         s32 ret_val = 0;
2184         u32 bank = 0;
2185         u16 i, word;
2186
2187         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2188             (words == 0)) {
2189                 e_dbg("nvm parameter(s) out of bounds\n");
2190                 ret_val = -E1000_ERR_NVM;
2191                 goto out;
2192         }
2193
2194         nvm->ops.acquire(hw);
2195
2196         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2197         if (ret_val) {
2198                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2199                 bank = 0;
2200         }
2201
2202         act_offset = (bank) ? nvm->flash_bank_size : 0;
2203         act_offset += offset;
2204
2205         ret_val = 0;
2206         for (i = 0; i < words; i++) {
2207                 if (dev_spec->shadow_ram[offset+i].modified) {
2208                         data[i] = dev_spec->shadow_ram[offset+i].value;
2209                 } else {
2210                         ret_val = e1000_read_flash_word_ich8lan(hw,
2211                                                                 act_offset + i,
2212                                                                 &word);
2213                         if (ret_val)
2214                                 break;
2215                         data[i] = word;
2216                 }
2217         }
2218
2219         nvm->ops.release(hw);
2220
2221 out:
2222         if (ret_val)
2223                 e_dbg("NVM read error: %d\n", ret_val);
2224
2225         return ret_val;
2226 }
2227
2228 /**
2229  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2230  *  @hw: pointer to the HW structure
2231  *
2232  *  This function does initial flash setup so that a new read/write/erase cycle
2233  *  can be started.
2234  **/
2235 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2236 {
2237         union ich8_hws_flash_status hsfsts;
2238         s32 ret_val = -E1000_ERR_NVM;
2239
2240         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2241
2242         /* Check if the flash descriptor is valid */
2243         if (hsfsts.hsf_status.fldesvalid == 0) {
2244                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2245                 return -E1000_ERR_NVM;
2246         }
2247
2248         /* Clear FCERR and DAEL in hw status by writing 1 */
2249         hsfsts.hsf_status.flcerr = 1;
2250         hsfsts.hsf_status.dael = 1;
2251
2252         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2253
2254         /*
2255          * Either we should have a hardware SPI cycle in progress
2256          * bit to check against, in order to start a new cycle or
2257          * FDONE bit should be changed in the hardware so that it
2258          * is 1 after hardware reset, which can then be used as an
2259          * indication whether a cycle is in progress or has been
2260          * completed.
2261          */
2262
2263         if (hsfsts.hsf_status.flcinprog == 0) {
2264                 /*
2265                  * There is no cycle running at present,
2266                  * so we can start a cycle.
2267                  * Begin by setting Flash Cycle Done.
2268                  */
2269                 hsfsts.hsf_status.flcdone = 1;
2270                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2271                 ret_val = 0;
2272         } else {
2273                 s32 i = 0;
2274
2275                 /*
2276                  * Otherwise poll for sometime so the current
2277                  * cycle has a chance to end before giving up.
2278                  */
2279                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2280                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2281                         if (hsfsts.hsf_status.flcinprog == 0) {
2282                                 ret_val = 0;
2283                                 break;
2284                         }
2285                         udelay(1);
2286                 }
2287                 if (!ret_val) {
2288                         /*
2289                          * Successful in waiting for previous cycle to timeout,
2290                          * now set the Flash Cycle Done.
2291                          */
2292                         hsfsts.hsf_status.flcdone = 1;
2293                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2294                 } else {
2295                         e_dbg("Flash controller busy, cannot get access\n");
2296                 }
2297         }
2298
2299         return ret_val;
2300 }
2301
2302 /**
2303  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2304  *  @hw: pointer to the HW structure
2305  *  @timeout: maximum time to wait for completion
2306  *
2307  *  This function starts a flash cycle and waits for its completion.
2308  **/
2309 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2310 {
2311         union ich8_hws_flash_ctrl hsflctl;
2312         union ich8_hws_flash_status hsfsts;
2313         s32 ret_val = -E1000_ERR_NVM;
2314         u32 i = 0;
2315
2316         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2317         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2318         hsflctl.hsf_ctrl.flcgo = 1;
2319         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2320
2321         /* wait till FDONE bit is set to 1 */
2322         do {
2323                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2324                 if (hsfsts.hsf_status.flcdone == 1)
2325                         break;
2326                 udelay(1);
2327         } while (i++ < timeout);
2328
2329         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2330                 return 0;
2331
2332         return ret_val;
2333 }
2334
2335 /**
2336  *  e1000_read_flash_word_ich8lan - Read word from flash
2337  *  @hw: pointer to the HW structure
2338  *  @offset: offset to data location
2339  *  @data: pointer to the location for storing the data
2340  *
2341  *  Reads the flash word at offset into data.  Offset is converted
2342  *  to bytes before read.
2343  **/
2344 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2345                                          u16 *data)
2346 {
2347         /* Must convert offset into bytes. */
2348         offset <<= 1;
2349
2350         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2351 }
2352
2353 /**
2354  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2355  *  @hw: pointer to the HW structure
2356  *  @offset: The offset of the byte to read.
2357  *  @data: Pointer to a byte to store the value read.
2358  *
2359  *  Reads a single byte from the NVM using the flash access registers.
2360  **/
2361 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2362                                          u8 *data)
2363 {
2364         s32 ret_val;
2365         u16 word = 0;
2366
2367         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2368         if (ret_val)
2369                 return ret_val;
2370
2371         *data = (u8)word;
2372
2373         return 0;
2374 }
2375
2376 /**
2377  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2378  *  @hw: pointer to the HW structure
2379  *  @offset: The offset (in bytes) of the byte or word to read.
2380  *  @size: Size of data to read, 1=byte 2=word
2381  *  @data: Pointer to the word to store the value read.
2382  *
2383  *  Reads a byte or word from the NVM using the flash access registers.
2384  **/
2385 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2386                                          u8 size, u16 *data)
2387 {
2388         union ich8_hws_flash_status hsfsts;
2389         union ich8_hws_flash_ctrl hsflctl;
2390         u32 flash_linear_addr;
2391         u32 flash_data = 0;
2392         s32 ret_val = -E1000_ERR_NVM;
2393         u8 count = 0;
2394
2395         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2396                 return -E1000_ERR_NVM;
2397
2398         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2399                             hw->nvm.flash_base_addr;
2400
2401         do {
2402                 udelay(1);
2403                 /* Steps */
2404                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2405                 if (ret_val)
2406                         break;
2407
2408                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2409                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2410                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2411                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2412                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2413
2414                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2415
2416                 ret_val = e1000_flash_cycle_ich8lan(hw,
2417                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2418
2419                 /*
2420                  * Check if FCERR is set to 1, if set to 1, clear it
2421                  * and try the whole sequence a few more times, else
2422                  * read in (shift in) the Flash Data0, the order is
2423                  * least significant byte first msb to lsb
2424                  */
2425                 if (!ret_val) {
2426                         flash_data = er32flash(ICH_FLASH_FDATA0);
2427                         if (size == 1)
2428                                 *data = (u8)(flash_data & 0x000000FF);
2429                         else if (size == 2)
2430                                 *data = (u16)(flash_data & 0x0000FFFF);
2431                         break;
2432                 } else {
2433                         /*
2434                          * If we've gotten here, then things are probably
2435                          * completely hosed, but if the error condition is
2436                          * detected, it won't hurt to give it another try...
2437                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2438                          */
2439                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2440                         if (hsfsts.hsf_status.flcerr == 1) {
2441                                 /* Repeat for some time before giving up. */
2442                                 continue;
2443                         } else if (hsfsts.hsf_status.flcdone == 0) {
2444                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2445                                 break;
2446                         }
2447                 }
2448         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2449
2450         return ret_val;
2451 }
2452
2453 /**
2454  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2455  *  @hw: pointer to the HW structure
2456  *  @offset: The offset (in bytes) of the word(s) to write.
2457  *  @words: Size of data to write in words
2458  *  @data: Pointer to the word(s) to write at offset.
2459  *
2460  *  Writes a byte or word to the NVM using the flash access registers.
2461  **/
2462 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2463                                    u16 *data)
2464 {
2465         struct e1000_nvm_info *nvm = &hw->nvm;
2466         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2467         u16 i;
2468
2469         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2470             (words == 0)) {
2471                 e_dbg("nvm parameter(s) out of bounds\n");
2472                 return -E1000_ERR_NVM;
2473         }
2474
2475         nvm->ops.acquire(hw);
2476
2477         for (i = 0; i < words; i++) {
2478                 dev_spec->shadow_ram[offset+i].modified = true;
2479                 dev_spec->shadow_ram[offset+i].value = data[i];
2480         }
2481
2482         nvm->ops.release(hw);
2483
2484         return 0;
2485 }
2486
2487 /**
2488  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2489  *  @hw: pointer to the HW structure
2490  *
2491  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2492  *  which writes the checksum to the shadow ram.  The changes in the shadow
2493  *  ram are then committed to the EEPROM by processing each bank at a time
2494  *  checking for the modified bit and writing only the pending changes.
2495  *  After a successful commit, the shadow ram is cleared and is ready for
2496  *  future writes.
2497  **/
2498 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2499 {
2500         struct e1000_nvm_info *nvm = &hw->nvm;
2501         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2502         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2503         s32 ret_val;
2504         u16 data;
2505
2506         ret_val = e1000e_update_nvm_checksum_generic(hw);
2507         if (ret_val)
2508                 goto out;
2509
2510         if (nvm->type != e1000_nvm_flash_sw)
2511                 goto out;
2512
2513         nvm->ops.acquire(hw);
2514
2515         /*
2516          * We're writing to the opposite bank so if we're on bank 1,
2517          * write to bank 0 etc.  We also need to erase the segment that
2518          * is going to be written
2519          */
2520         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2521         if (ret_val) {
2522                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2523                 bank = 0;
2524         }
2525
2526         if (bank == 0) {
2527                 new_bank_offset = nvm->flash_bank_size;
2528                 old_bank_offset = 0;
2529                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2530                 if (ret_val)
2531                         goto release;
2532         } else {
2533                 old_bank_offset = nvm->flash_bank_size;
2534                 new_bank_offset = 0;
2535                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2536                 if (ret_val)
2537                         goto release;
2538         }
2539
2540         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2541                 /*
2542                  * Determine whether to write the value stored
2543                  * in the other NVM bank or a modified value stored
2544                  * in the shadow RAM
2545                  */
2546                 if (dev_spec->shadow_ram[i].modified) {
2547                         data = dev_spec->shadow_ram[i].value;
2548                 } else {
2549                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2550                                                                 old_bank_offset,
2551                                                                 &data);
2552                         if (ret_val)
2553                                 break;
2554                 }
2555
2556                 /*
2557                  * If the word is 0x13, then make sure the signature bits
2558                  * (15:14) are 11b until the commit has completed.
2559                  * This will allow us to write 10b which indicates the
2560                  * signature is valid.  We want to do this after the write
2561                  * has completed so that we don't mark the segment valid
2562                  * while the write is still in progress
2563                  */
2564                 if (i == E1000_ICH_NVM_SIG_WORD)
2565                         data |= E1000_ICH_NVM_SIG_MASK;
2566
2567                 /* Convert offset to bytes. */
2568                 act_offset = (i + new_bank_offset) << 1;
2569
2570                 udelay(100);
2571                 /* Write the bytes to the new bank. */
2572                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2573                                                                act_offset,
2574                                                                (u8)data);
2575                 if (ret_val)
2576                         break;
2577
2578                 udelay(100);
2579                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2580                                                           act_offset + 1,
2581                                                           (u8)(data >> 8));
2582                 if (ret_val)
2583                         break;
2584         }
2585
2586         /*
2587          * Don't bother writing the segment valid bits if sector
2588          * programming failed.
2589          */
2590         if (ret_val) {
2591                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2592                 e_dbg("Flash commit failed.\n");
2593                 goto release;
2594         }
2595
2596         /*
2597          * Finally validate the new segment by setting bit 15:14
2598          * to 10b in word 0x13 , this can be done without an
2599          * erase as well since these bits are 11 to start with
2600          * and we need to change bit 14 to 0b
2601          */
2602         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2603         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2604         if (ret_val)
2605                 goto release;
2606
2607         data &= 0xBFFF;
2608         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2609                                                        act_offset * 2 + 1,
2610                                                        (u8)(data >> 8));
2611         if (ret_val)
2612                 goto release;
2613
2614         /*
2615          * And invalidate the previously valid segment by setting
2616          * its signature word (0x13) high_byte to 0b. This can be
2617          * done without an erase because flash erase sets all bits
2618          * to 1's. We can write 1's to 0's without an erase
2619          */
2620         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2621         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2622         if (ret_val)
2623                 goto release;
2624
2625         /* Great!  Everything worked, we can now clear the cached entries. */
2626         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2627                 dev_spec->shadow_ram[i].modified = false;
2628                 dev_spec->shadow_ram[i].value = 0xFFFF;
2629         }
2630
2631 release:
2632         nvm->ops.release(hw);
2633
2634         /*
2635          * Reload the EEPROM, or else modifications will not appear
2636          * until after the next adapter reset.
2637          */
2638         if (!ret_val) {
2639                 e1000e_reload_nvm(hw);
2640                 usleep_range(10000, 20000);
2641         }
2642
2643 out:
2644         if (ret_val)
2645                 e_dbg("NVM update error: %d\n", ret_val);
2646
2647         return ret_val;
2648 }
2649
2650 /**
2651  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2652  *  @hw: pointer to the HW structure
2653  *
2654  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2655  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2656  *  calculated, in which case we need to calculate the checksum and set bit 6.
2657  **/
2658 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2659 {
2660         s32 ret_val;
2661         u16 data;
2662
2663         /*
2664          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2665          * needs to be fixed.  This bit is an indication that the NVM
2666          * was prepared by OEM software and did not calculate the
2667          * checksum...a likely scenario.
2668          */
2669         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2670         if (ret_val)
2671                 return ret_val;
2672
2673         if ((data & 0x40) == 0) {
2674                 data |= 0x40;
2675                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2676                 if (ret_val)
2677                         return ret_val;
2678                 ret_val = e1000e_update_nvm_checksum(hw);
2679                 if (ret_val)
2680                         return ret_val;
2681         }
2682
2683         return e1000e_validate_nvm_checksum_generic(hw);
2684 }
2685
2686 /**
2687  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2688  *  @hw: pointer to the HW structure
2689  *
2690  *  To prevent malicious write/erase of the NVM, set it to be read-only
2691  *  so that the hardware ignores all write/erase cycles of the NVM via
2692  *  the flash control registers.  The shadow-ram copy of the NVM will
2693  *  still be updated, however any updates to this copy will not stick
2694  *  across driver reloads.
2695  **/
2696 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2697 {
2698         struct e1000_nvm_info *nvm = &hw->nvm;
2699         union ich8_flash_protected_range pr0;
2700         union ich8_hws_flash_status hsfsts;
2701         u32 gfpreg;
2702
2703         nvm->ops.acquire(hw);
2704
2705         gfpreg = er32flash(ICH_FLASH_GFPREG);
2706
2707         /* Write-protect GbE Sector of NVM */
2708         pr0.regval = er32flash(ICH_FLASH_PR0);
2709         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2710         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2711         pr0.range.wpe = true;
2712         ew32flash(ICH_FLASH_PR0, pr0.regval);
2713
2714         /*
2715          * Lock down a subset of GbE Flash Control Registers, e.g.
2716          * PR0 to prevent the write-protection from being lifted.
2717          * Once FLOCKDN is set, the registers protected by it cannot
2718          * be written until FLOCKDN is cleared by a hardware reset.
2719          */
2720         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2721         hsfsts.hsf_status.flockdn = true;
2722         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2723
2724         nvm->ops.release(hw);
2725 }
2726
2727 /**
2728  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2729  *  @hw: pointer to the HW structure
2730  *  @offset: The offset (in bytes) of the byte/word to read.
2731  *  @size: Size of data to read, 1=byte 2=word
2732  *  @data: The byte(s) to write to the NVM.
2733  *
2734  *  Writes one/two bytes to the NVM using the flash access registers.
2735  **/
2736 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2737                                           u8 size, u16 data)
2738 {
2739         union ich8_hws_flash_status hsfsts;
2740         union ich8_hws_flash_ctrl hsflctl;
2741         u32 flash_linear_addr;
2742         u32 flash_data = 0;
2743         s32 ret_val;
2744         u8 count = 0;
2745
2746         if (size < 1 || size > 2 || data > size * 0xff ||
2747             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2748                 return -E1000_ERR_NVM;
2749
2750         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2751                             hw->nvm.flash_base_addr;
2752
2753         do {
2754                 udelay(1);
2755                 /* Steps */
2756                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2757                 if (ret_val)
2758                         break;
2759
2760                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2761                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2762                 hsflctl.hsf_ctrl.fldbcount = size -1;
2763                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2764                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2765
2766                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2767
2768                 if (size == 1)
2769                         flash_data = (u32)data & 0x00FF;
2770                 else
2771                         flash_data = (u32)data;
2772
2773                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2774
2775                 /*
2776                  * check if FCERR is set to 1 , if set to 1, clear it
2777                  * and try the whole sequence a few more times else done
2778                  */
2779                 ret_val = e1000_flash_cycle_ich8lan(hw,
2780                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2781                 if (!ret_val)
2782                         break;
2783
2784                 /*
2785                  * If we're here, then things are most likely
2786                  * completely hosed, but if the error condition
2787                  * is detected, it won't hurt to give it another
2788                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2789                  */
2790                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2791                 if (hsfsts.hsf_status.flcerr == 1)
2792                         /* Repeat for some time before giving up. */
2793                         continue;
2794                 if (hsfsts.hsf_status.flcdone == 0) {
2795                         e_dbg("Timeout error - flash cycle did not complete.\n");
2796                         break;
2797                 }
2798         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2799
2800         return ret_val;
2801 }
2802
2803 /**
2804  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2805  *  @hw: pointer to the HW structure
2806  *  @offset: The index of the byte to read.
2807  *  @data: The byte to write to the NVM.
2808  *
2809  *  Writes a single byte to the NVM using the flash access registers.
2810  **/
2811 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2812                                           u8 data)
2813 {
2814         u16 word = (u16)data;
2815
2816         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2817 }
2818
2819 /**
2820  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2821  *  @hw: pointer to the HW structure
2822  *  @offset: The offset of the byte to write.
2823  *  @byte: The byte to write to the NVM.
2824  *
2825  *  Writes a single byte to the NVM using the flash access registers.
2826  *  Goes through a retry algorithm before giving up.
2827  **/
2828 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2829                                                 u32 offset, u8 byte)
2830 {
2831         s32 ret_val;
2832         u16 program_retries;
2833
2834         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2835         if (!ret_val)
2836                 return ret_val;
2837
2838         for (program_retries = 0; program_retries < 100; program_retries++) {
2839                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2840                 udelay(100);
2841                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2842                 if (!ret_val)
2843                         break;
2844         }
2845         if (program_retries == 100)
2846                 return -E1000_ERR_NVM;
2847
2848         return 0;
2849 }
2850
2851 /**
2852  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2853  *  @hw: pointer to the HW structure
2854  *  @bank: 0 for first bank, 1 for second bank, etc.
2855  *
2856  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2857  *  bank N is 4096 * N + flash_reg_addr.
2858  **/
2859 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2860 {
2861         struct e1000_nvm_info *nvm = &hw->nvm;
2862         union ich8_hws_flash_status hsfsts;
2863         union ich8_hws_flash_ctrl hsflctl;
2864         u32 flash_linear_addr;
2865         /* bank size is in 16bit words - adjust to bytes */
2866         u32 flash_bank_size = nvm->flash_bank_size * 2;
2867         s32 ret_val;
2868         s32 count = 0;
2869         s32 j, iteration, sector_size;
2870
2871         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2872
2873         /*
2874          * Determine HW Sector size: Read BERASE bits of hw flash status
2875          * register
2876          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2877          *     consecutive sectors.  The start index for the nth Hw sector
2878          *     can be calculated as = bank * 4096 + n * 256
2879          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2880          *     The start index for the nth Hw sector can be calculated
2881          *     as = bank * 4096
2882          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2883          *     (ich9 only, otherwise error condition)
2884          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2885          */
2886         switch (hsfsts.hsf_status.berasesz) {
2887         case 0:
2888                 /* Hw sector size 256 */
2889                 sector_size = ICH_FLASH_SEG_SIZE_256;
2890                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2891                 break;
2892         case 1:
2893                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2894                 iteration = 1;
2895                 break;
2896         case 2:
2897                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2898                 iteration = 1;
2899                 break;
2900         case 3:
2901                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2902                 iteration = 1;
2903                 break;
2904         default:
2905                 return -E1000_ERR_NVM;
2906         }
2907
2908         /* Start with the base address, then add the sector offset. */
2909         flash_linear_addr = hw->nvm.flash_base_addr;
2910         flash_linear_addr += (bank) ? flash_bank_size : 0;
2911
2912         for (j = 0; j < iteration ; j++) {
2913                 do {
2914                         /* Steps */
2915                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2916                         if (ret_val)
2917                                 return ret_val;
2918
2919                         /*
2920                          * Write a value 11 (block Erase) in Flash
2921                          * Cycle field in hw flash control
2922                          */
2923                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2924                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2925                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2926
2927                         /*
2928                          * Write the last 24 bits of an index within the
2929                          * block into Flash Linear address field in Flash
2930                          * Address.
2931                          */
2932                         flash_linear_addr += (j * sector_size);
2933                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2934
2935                         ret_val = e1000_flash_cycle_ich8lan(hw,
2936                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2937                         if (!ret_val)
2938                                 break;
2939
2940                         /*
2941                          * Check if FCERR is set to 1.  If 1,
2942                          * clear it and try the whole sequence
2943                          * a few more times else Done
2944                          */
2945                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2946                         if (hsfsts.hsf_status.flcerr == 1)
2947                                 /* repeat for some time before giving up */
2948                                 continue;
2949                         else if (hsfsts.hsf_status.flcdone == 0)
2950                                 return ret_val;
2951                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2952         }
2953
2954         return 0;
2955 }
2956
2957 /**
2958  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2959  *  @hw: pointer to the HW structure
2960  *  @data: Pointer to the LED settings
2961  *
2962  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2963  *  settings is all 0's or F's, set the LED default to a valid LED default
2964  *  setting.
2965  **/
2966 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2967 {
2968         s32 ret_val;
2969
2970         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2971         if (ret_val) {
2972                 e_dbg("NVM Read Error\n");
2973                 return ret_val;
2974         }
2975
2976         if (*data == ID_LED_RESERVED_0000 ||
2977             *data == ID_LED_RESERVED_FFFF)
2978                 *data = ID_LED_DEFAULT_ICH8LAN;
2979
2980         return 0;
2981 }
2982
2983 /**
2984  *  e1000_id_led_init_pchlan - store LED configurations
2985  *  @hw: pointer to the HW structure
2986  *
2987  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2988  *  the PHY LED configuration register.
2989  *
2990  *  PCH also does not have an "always on" or "always off" mode which
2991  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2992  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2993  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2994  *  link based on logic in e1000_led_[on|off]_pchlan().
2995  **/
2996 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2997 {
2998         struct e1000_mac_info *mac = &hw->mac;
2999         s32 ret_val;
3000         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3001         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3002         u16 data, i, temp, shift;
3003
3004         /* Get default ID LED modes */
3005         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3006         if (ret_val)
3007                 goto out;
3008
3009         mac->ledctl_default = er32(LEDCTL);
3010         mac->ledctl_mode1 = mac->ledctl_default;
3011         mac->ledctl_mode2 = mac->ledctl_default;
3012
3013         for (i = 0; i < 4; i++) {
3014                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3015                 shift = (i * 5);
3016                 switch (temp) {
3017                 case ID_LED_ON1_DEF2:
3018                 case ID_LED_ON1_ON2:
3019                 case ID_LED_ON1_OFF2:
3020                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3021                         mac->ledctl_mode1 |= (ledctl_on << shift);
3022                         break;
3023                 case ID_LED_OFF1_DEF2:
3024                 case ID_LED_OFF1_ON2:
3025                 case ID_LED_OFF1_OFF2:
3026                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3027                         mac->ledctl_mode1 |= (ledctl_off << shift);
3028                         break;
3029                 default:
3030                         /* Do nothing */
3031                         break;
3032                 }
3033                 switch (temp) {
3034                 case ID_LED_DEF1_ON2:
3035                 case ID_LED_ON1_ON2:
3036                 case ID_LED_OFF1_ON2:
3037                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3038                         mac->ledctl_mode2 |= (ledctl_on << shift);
3039                         break;
3040                 case ID_LED_DEF1_OFF2:
3041                 case ID_LED_ON1_OFF2:
3042                 case ID_LED_OFF1_OFF2:
3043                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3044                         mac->ledctl_mode2 |= (ledctl_off << shift);
3045                         break;
3046                 default:
3047                         /* Do nothing */
3048                         break;
3049                 }
3050         }
3051
3052 out:
3053         return ret_val;
3054 }
3055
3056 /**
3057  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3058  *  @hw: pointer to the HW structure
3059  *
3060  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3061  *  register, so the the bus width is hard coded.
3062  **/
3063 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3064 {
3065         struct e1000_bus_info *bus = &hw->bus;
3066         s32 ret_val;
3067
3068         ret_val = e1000e_get_bus_info_pcie(hw);
3069
3070         /*
3071          * ICH devices are "PCI Express"-ish.  They have
3072          * a configuration space, but do not contain
3073          * PCI Express Capability registers, so bus width
3074          * must be hardcoded.
3075          */
3076         if (bus->width == e1000_bus_width_unknown)
3077                 bus->width = e1000_bus_width_pcie_x1;
3078
3079         return ret_val;
3080 }
3081
3082 /**
3083  *  e1000_reset_hw_ich8lan - Reset the hardware
3084  *  @hw: pointer to the HW structure
3085  *
3086  *  Does a full reset of the hardware which includes a reset of the PHY and
3087  *  MAC.
3088  **/
3089 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3090 {
3091         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3092         u16 reg;
3093         u32 ctrl, kab;
3094         s32 ret_val;
3095
3096         /*
3097          * Prevent the PCI-E bus from sticking if there is no TLP connection
3098          * on the last TLP read/write transaction when MAC is reset.
3099          */
3100         ret_val = e1000e_disable_pcie_master(hw);
3101         if (ret_val)
3102                 e_dbg("PCI-E Master disable polling has failed.\n");
3103
3104         e_dbg("Masking off all interrupts\n");
3105         ew32(IMC, 0xffffffff);
3106
3107         /*
3108          * Disable the Transmit and Receive units.  Then delay to allow
3109          * any pending transactions to complete before we hit the MAC
3110          * with the global reset.
3111          */
3112         ew32(RCTL, 0);
3113         ew32(TCTL, E1000_TCTL_PSP);
3114         e1e_flush();
3115
3116         usleep_range(10000, 20000);
3117
3118         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3119         if (hw->mac.type == e1000_ich8lan) {
3120                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3121                 ew32(PBA, E1000_PBA_8K);
3122                 /* Set Packet Buffer Size to 16k. */
3123                 ew32(PBS, E1000_PBS_16K);
3124         }
3125
3126         if (hw->mac.type == e1000_pchlan) {
3127                 /* Save the NVM K1 bit setting*/
3128                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3129                 if (ret_val)
3130                         return ret_val;
3131
3132                 if (reg & E1000_NVM_K1_ENABLE)
3133                         dev_spec->nvm_k1_enabled = true;
3134                 else
3135                         dev_spec->nvm_k1_enabled = false;
3136         }
3137
3138         ctrl = er32(CTRL);
3139
3140         if (!e1000_check_reset_block(hw)) {
3141                 /*
3142                  * Full-chip reset requires MAC and PHY reset at the same
3143                  * time to make sure the interface between MAC and the
3144                  * external PHY is reset.
3145                  */
3146                 ctrl |= E1000_CTRL_PHY_RST;
3147
3148                 /*
3149                  * Gate automatic PHY configuration by hardware on
3150                  * non-managed 82579
3151                  */
3152                 if ((hw->mac.type == e1000_pch2lan) &&
3153                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3154                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3155         }
3156         ret_val = e1000_acquire_swflag_ich8lan(hw);
3157         e_dbg("Issuing a global reset to ich8lan\n");
3158         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3159         /* cannot issue a flush here because it hangs the hardware */
3160         msleep(20);
3161
3162         if (!ret_val)
3163                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3164
3165         if (ctrl & E1000_CTRL_PHY_RST) {
3166                 ret_val = hw->phy.ops.get_cfg_done(hw);
3167                 if (ret_val)
3168                         goto out;
3169
3170                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3171                 if (ret_val)
3172                         goto out;
3173         }
3174
3175         /*
3176          * For PCH, this write will make sure that any noise
3177          * will be detected as a CRC error and be dropped rather than show up
3178          * as a bad packet to the DMA engine.
3179          */
3180         if (hw->mac.type == e1000_pchlan)
3181                 ew32(CRC_OFFSET, 0x65656565);
3182
3183         ew32(IMC, 0xffffffff);
3184         er32(ICR);
3185
3186         kab = er32(KABGTXD);
3187         kab |= E1000_KABGTXD_BGSQLBIAS;
3188         ew32(KABGTXD, kab);
3189
3190 out:
3191         return ret_val;
3192 }
3193
3194 /**
3195  *  e1000_init_hw_ich8lan - Initialize the hardware
3196  *  @hw: pointer to the HW structure
3197  *
3198  *  Prepares the hardware for transmit and receive by doing the following:
3199  *   - initialize hardware bits
3200  *   - initialize LED identification
3201  *   - setup receive address registers
3202  *   - setup flow control
3203  *   - setup transmit descriptors
3204  *   - clear statistics
3205  **/
3206 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3207 {
3208         struct e1000_mac_info *mac = &hw->mac;
3209         u32 ctrl_ext, txdctl, snoop;
3210         s32 ret_val;
3211         u16 i;
3212
3213         e1000_initialize_hw_bits_ich8lan(hw);
3214
3215         /* Initialize identification LED */
3216         ret_val = mac->ops.id_led_init(hw);
3217         if (ret_val)
3218                 e_dbg("Error initializing identification LED\n");
3219                 /* This is not fatal and we should not stop init due to this */
3220
3221         /* Setup the receive address. */
3222         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3223
3224         /* Zero out the Multicast HASH table */
3225         e_dbg("Zeroing the MTA\n");
3226         for (i = 0; i < mac->mta_reg_count; i++)
3227                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3228
3229         /*
3230          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3231          * the ME.  Disable wakeup by clearing the host wakeup bit.
3232          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3233          */
3234         if (hw->phy.type == e1000_phy_82578) {
3235                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3236                 i &= ~BM_WUC_HOST_WU_BIT;
3237                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3238                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3239                 if (ret_val)
3240                         return ret_val;
3241         }
3242
3243         /* Setup link and flow control */
3244         ret_val = e1000_setup_link_ich8lan(hw);
3245
3246         /* Set the transmit descriptor write-back policy for both queues */
3247         txdctl = er32(TXDCTL(0));
3248         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3249                  E1000_TXDCTL_FULL_TX_DESC_WB;
3250         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3251                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3252         ew32(TXDCTL(0), txdctl);
3253         txdctl = er32(TXDCTL(1));
3254         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3255                  E1000_TXDCTL_FULL_TX_DESC_WB;
3256         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3257                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3258         ew32(TXDCTL(1), txdctl);
3259
3260         /*
3261          * ICH8 has opposite polarity of no_snoop bits.
3262          * By default, we should use snoop behavior.
3263          */
3264         if (mac->type == e1000_ich8lan)
3265                 snoop = PCIE_ICH8_SNOOP_ALL;
3266         else
3267                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3268         e1000e_set_pcie_no_snoop(hw, snoop);
3269
3270         ctrl_ext = er32(CTRL_EXT);
3271         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3272         ew32(CTRL_EXT, ctrl_ext);
3273
3274         /*
3275          * Clear all of the statistics registers (clear on read).  It is
3276          * important that we do this after we have tried to establish link
3277          * because the symbol error count will increment wildly if there
3278          * is no link.
3279          */
3280         e1000_clear_hw_cntrs_ich8lan(hw);
3281
3282         return 0;
3283 }
3284 /**
3285  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3286  *  @hw: pointer to the HW structure
3287  *
3288  *  Sets/Clears required hardware bits necessary for correctly setting up the
3289  *  hardware for transmit and receive.
3290  **/
3291 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3292 {
3293         u32 reg;
3294
3295         /* Extended Device Control */
3296         reg = er32(CTRL_EXT);
3297         reg |= (1 << 22);
3298         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3299         if (hw->mac.type >= e1000_pchlan)
3300                 reg |= E1000_CTRL_EXT_PHYPDEN;
3301         ew32(CTRL_EXT, reg);
3302
3303         /* Transmit Descriptor Control 0 */
3304         reg = er32(TXDCTL(0));
3305         reg |= (1 << 22);
3306         ew32(TXDCTL(0), reg);
3307
3308         /* Transmit Descriptor Control 1 */
3309         reg = er32(TXDCTL(1));
3310         reg |= (1 << 22);
3311         ew32(TXDCTL(1), reg);
3312
3313         /* Transmit Arbitration Control 0 */
3314         reg = er32(TARC(0));
3315         if (hw->mac.type == e1000_ich8lan)
3316                 reg |= (1 << 28) | (1 << 29);
3317         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3318         ew32(TARC(0), reg);
3319
3320         /* Transmit Arbitration Control 1 */
3321         reg = er32(TARC(1));
3322         if (er32(TCTL) & E1000_TCTL_MULR)
3323                 reg &= ~(1 << 28);
3324         else
3325                 reg |= (1 << 28);
3326         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3327         ew32(TARC(1), reg);
3328
3329         /* Device Status */
3330         if (hw->mac.type == e1000_ich8lan) {
3331                 reg = er32(STATUS);
3332                 reg &= ~(1 << 31);
3333                 ew32(STATUS, reg);
3334         }
3335
3336         /*
3337          * work-around descriptor data corruption issue during nfs v2 udp
3338          * traffic, just disable the nfs filtering capability
3339          */
3340         reg = er32(RFCTL);
3341         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3342         ew32(RFCTL, reg);
3343 }
3344
3345 /**
3346  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3347  *  @hw: pointer to the HW structure
3348  *
3349  *  Determines which flow control settings to use, then configures flow
3350  *  control.  Calls the appropriate media-specific link configuration
3351  *  function.  Assuming the adapter has a valid link partner, a valid link
3352  *  should be established.  Assumes the hardware has previously been reset
3353  *  and the transmitter and receiver are not enabled.
3354  **/
3355 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3356 {
3357         s32 ret_val;
3358
3359         if (e1000_check_reset_block(hw))
3360                 return 0;
3361
3362         /*
3363          * ICH parts do not have a word in the NVM to determine
3364          * the default flow control setting, so we explicitly
3365          * set it to full.
3366          */
3367         if (hw->fc.requested_mode == e1000_fc_default) {
3368                 /* Workaround h/w hang when Tx flow control enabled */
3369                 if (hw->mac.type == e1000_pchlan)
3370                         hw->fc.requested_mode = e1000_fc_rx_pause;
3371                 else
3372                         hw->fc.requested_mode = e1000_fc_full;
3373         }
3374
3375         /*
3376          * Save off the requested flow control mode for use later.  Depending
3377          * on the link partner's capabilities, we may or may not use this mode.
3378          */
3379         hw->fc.current_mode = hw->fc.requested_mode;
3380
3381         e_dbg("After fix-ups FlowControl is now = %x\n",
3382                 hw->fc.current_mode);
3383
3384         /* Continue to configure the copper link. */
3385         ret_val = e1000_setup_copper_link_ich8lan(hw);
3386         if (ret_val)
3387                 return ret_val;
3388
3389         ew32(FCTTV, hw->fc.pause_time);
3390         if ((hw->phy.type == e1000_phy_82578) ||
3391             (hw->phy.type == e1000_phy_82579) ||
3392             (hw->phy.type == e1000_phy_82577)) {
3393                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3394
3395                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3396                                    hw->fc.pause_time);
3397                 if (ret_val)
3398                         return ret_val;
3399         }
3400
3401         return e1000e_set_fc_watermarks(hw);
3402 }
3403
3404 /**
3405  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3406  *  @hw: pointer to the HW structure
3407  *
3408  *  Configures the kumeran interface to the PHY to wait the appropriate time
3409  *  when polling the PHY, then call the generic setup_copper_link to finish
3410  *  configuring the copper link.
3411  **/
3412 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3413 {
3414         u32 ctrl;
3415         s32 ret_val;
3416         u16 reg_data;
3417
3418         ctrl = er32(CTRL);
3419         ctrl |= E1000_CTRL_SLU;
3420         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3421         ew32(CTRL, ctrl);
3422
3423         /*
3424          * Set the mac to wait the maximum time between each iteration
3425          * and increase the max iterations when polling the phy;
3426          * this fixes erroneous timeouts at 10Mbps.
3427          */
3428         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3429         if (ret_val)
3430                 return ret_val;
3431         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3432                                        &reg_data);
3433         if (ret_val)
3434                 return ret_val;
3435         reg_data |= 0x3F;
3436         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3437                                         reg_data);
3438         if (ret_val)
3439                 return ret_val;
3440
3441         switch (hw->phy.type) {
3442         case e1000_phy_igp_3:
3443                 ret_val = e1000e_copper_link_setup_igp(hw);
3444                 if (ret_val)
3445                         return ret_val;
3446                 break;
3447         case e1000_phy_bm:
3448         case e1000_phy_82578:
3449                 ret_val = e1000e_copper_link_setup_m88(hw);
3450                 if (ret_val)
3451                         return ret_val;
3452                 break;
3453         case e1000_phy_82577:
3454         case e1000_phy_82579:
3455                 ret_val = e1000_copper_link_setup_82577(hw);
3456                 if (ret_val)
3457                         return ret_val;
3458                 break;
3459         case e1000_phy_ife:
3460                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3461                 if (ret_val)
3462                         return ret_val;
3463
3464                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3465
3466                 switch (hw->phy.mdix) {
3467                 case 1:
3468                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3469                         break;
3470                 case 2:
3471                         reg_data |= IFE_PMC_FORCE_MDIX;
3472                         break;
3473                 case 0:
3474                 default:
3475                         reg_data |= IFE_PMC_AUTO_MDIX;
3476                         break;
3477                 }
3478                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3479                 if (ret_val)
3480                         return ret_val;
3481                 break;
3482         default:
3483                 break;
3484         }
3485         return e1000e_setup_copper_link(hw);
3486 }
3487
3488 /**
3489  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3490  *  @hw: pointer to the HW structure
3491  *  @speed: pointer to store current link speed
3492  *  @duplex: pointer to store the current link duplex
3493  *
3494  *  Calls the generic get_speed_and_duplex to retrieve the current link
3495  *  information and then calls the Kumeran lock loss workaround for links at
3496  *  gigabit speeds.
3497  **/
3498 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3499                                           u16 *duplex)
3500 {
3501         s32 ret_val;
3502
3503         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3504         if (ret_val)
3505                 return ret_val;
3506
3507         if ((hw->mac.type == e1000_ich8lan) &&
3508             (hw->phy.type == e1000_phy_igp_3) &&
3509             (*speed == SPEED_1000)) {
3510                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3511         }
3512
3513         return ret_val;
3514 }
3515
3516 /**
3517  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3518  *  @hw: pointer to the HW structure
3519  *
3520  *  Work-around for 82566 Kumeran PCS lock loss:
3521  *  On link status change (i.e. PCI reset, speed change) and link is up and
3522  *  speed is gigabit-
3523  *    0) if workaround is optionally disabled do nothing
3524  *    1) wait 1ms for Kumeran link to come up
3525  *    2) check Kumeran Diagnostic register PCS lock loss bit
3526  *    3) if not set the link is locked (all is good), otherwise...
3527  *    4) reset the PHY
3528  *    5) repeat up to 10 times
3529  *  Note: this is only called for IGP3 copper when speed is 1gb.
3530  **/
3531 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3532 {
3533         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3534         u32 phy_ctrl;
3535         s32 ret_val;
3536         u16 i, data;
3537         bool link;
3538
3539         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3540                 return 0;
3541
3542         /*
3543          * Make sure link is up before proceeding.  If not just return.
3544          * Attempting this while link is negotiating fouled up link
3545          * stability
3546          */
3547         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3548         if (!link)
3549                 return 0;
3550
3551         for (i = 0; i < 10; i++) {
3552                 /* read once to clear */
3553                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3554                 if (ret_val)
3555                         return ret_val;
3556                 /* and again to get new status */
3557                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3558                 if (ret_val)
3559                         return ret_val;
3560
3561                 /* check for PCS lock */
3562                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3563                         return 0;
3564
3565                 /* Issue PHY reset */
3566                 e1000_phy_hw_reset(hw);
3567                 mdelay(5);
3568         }
3569         /* Disable GigE link negotiation */
3570         phy_ctrl = er32(PHY_CTRL);
3571         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3572                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3573         ew32(PHY_CTRL, phy_ctrl);
3574
3575         /*
3576          * Call gig speed drop workaround on Gig disable before accessing
3577          * any PHY registers
3578          */
3579         e1000e_gig_downshift_workaround_ich8lan(hw);
3580
3581         /* unable to acquire PCS lock */
3582         return -E1000_ERR_PHY;
3583 }
3584
3585 /**
3586  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3587  *  @hw: pointer to the HW structure
3588  *  @state: boolean value used to set the current Kumeran workaround state
3589  *
3590  *  If ICH8, set the current Kumeran workaround state (enabled - true
3591  *  /disabled - false).
3592  **/
3593 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3594                                                  bool state)
3595 {
3596         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3597
3598         if (hw->mac.type != e1000_ich8lan) {
3599                 e_dbg("Workaround applies to ICH8 only.\n");
3600                 return;
3601         }
3602
3603         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3604 }
3605
3606 /**
3607  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3608  *  @hw: pointer to the HW structure
3609  *
3610  *  Workaround for 82566 power-down on D3 entry:
3611  *    1) disable gigabit link
3612  *    2) write VR power-down enable
3613  *    3) read it back
3614  *  Continue if successful, else issue LCD reset and repeat
3615  **/
3616 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3617 {
3618         u32 reg;
3619         u16 data;
3620         u8  retry = 0;
3621
3622         if (hw->phy.type != e1000_phy_igp_3)
3623                 return;
3624
3625         /* Try the workaround twice (if needed) */
3626         do {
3627                 /* Disable link */
3628                 reg = er32(PHY_CTRL);
3629                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3630                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3631                 ew32(PHY_CTRL, reg);
3632
3633                 /*
3634                  * Call gig speed drop workaround on Gig disable before
3635                  * accessing any PHY registers
3636                  */
3637                 if (hw->mac.type == e1000_ich8lan)
3638                         e1000e_gig_downshift_workaround_ich8lan(hw);
3639
3640                 /* Write VR power-down enable */
3641                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3642                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3643                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3644
3645                 /* Read it back and test */
3646                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3647                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3648                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3649                         break;
3650
3651                 /* Issue PHY reset and repeat at most one more time */
3652                 reg = er32(CTRL);
3653                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3654                 retry++;
3655         } while (retry);
3656 }
3657
3658 /**
3659  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3660  *  @hw: pointer to the HW structure
3661  *
3662  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3663  *  LPLU, Gig disable, MDIC PHY reset):
3664  *    1) Set Kumeran Near-end loopback
3665  *    2) Clear Kumeran Near-end loopback
3666  *  Should only be called for ICH8[m] devices with any 1G Phy.
3667  **/
3668 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3669 {
3670         s32 ret_val;
3671         u16 reg_data;
3672
3673         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3674                 return;
3675
3676         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3677                                       &reg_data);
3678         if (ret_val)
3679                 return;
3680         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3681         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3682                                        reg_data);
3683         if (ret_val)
3684                 return;
3685         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3686         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3687                                        reg_data);
3688 }
3689
3690 /**
3691  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3692  *  @hw: pointer to the HW structure
3693  *
3694  *  During S0 to Sx transition, it is possible the link remains at gig
3695  *  instead of negotiating to a lower speed.  Before going to Sx, set
3696  *  'Gig Disable' to force link speed negotiation to a lower speed based on
3697  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
3698  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3699  *  needs to be written.
3700  **/
3701 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3702 {
3703         u32 phy_ctrl;
3704         s32 ret_val;
3705
3706         phy_ctrl = er32(PHY_CTRL);
3707         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
3708         ew32(PHY_CTRL, phy_ctrl);
3709
3710         if (hw->mac.type == e1000_ich8lan)
3711                 e1000e_gig_downshift_workaround_ich8lan(hw);
3712
3713         if (hw->mac.type >= e1000_pchlan) {
3714                 e1000_oem_bits_config_ich8lan(hw, false);
3715                 e1000_phy_hw_reset_ich8lan(hw);
3716                 ret_val = hw->phy.ops.acquire(hw);
3717                 if (ret_val)
3718                         return;
3719                 e1000_write_smbus_addr(hw);
3720                 hw->phy.ops.release(hw);
3721         }
3722 }
3723
3724 /**
3725  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3726  *  @hw: pointer to the HW structure
3727  *
3728  *  During Sx to S0 transitions on non-managed devices or managed devices
3729  *  on which PHY resets are not blocked, if the PHY registers cannot be
3730  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3731  *  the PHY.
3732  **/
3733 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3734 {
3735         u16 phy_id1, phy_id2;
3736         s32 ret_val;
3737
3738         if ((hw->mac.type != e1000_pch2lan) || e1000_check_reset_block(hw))
3739                 return;
3740
3741         ret_val = hw->phy.ops.acquire(hw);
3742         if (ret_val) {
3743                 e_dbg("Failed to acquire PHY semaphore in resume\n");
3744                 return;
3745         }
3746
3747         /* Test access to the PHY registers by reading the ID regs */
3748         ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3749         if (ret_val)
3750                 goto release;
3751         ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3752         if (ret_val)
3753                 goto release;
3754
3755         if (hw->phy.id == ((u32)(phy_id1 << 16) |
3756                            (u32)(phy_id2 & PHY_REVISION_MASK)))
3757                 goto release;
3758
3759         e1000_toggle_lanphypc_value_ich8lan(hw);
3760
3761         hw->phy.ops.release(hw);
3762         msleep(50);
3763         e1000_phy_hw_reset(hw);
3764         msleep(50);
3765         return;
3766
3767 release:
3768         hw->phy.ops.release(hw);
3769 }
3770
3771 /**
3772  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3773  *  @hw: pointer to the HW structure
3774  *
3775  *  Return the LED back to the default configuration.
3776  **/
3777 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3778 {
3779         if (hw->phy.type == e1000_phy_ife)
3780                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3781
3782         ew32(LEDCTL, hw->mac.ledctl_default);
3783         return 0;
3784 }
3785
3786 /**
3787  *  e1000_led_on_ich8lan - Turn LEDs on
3788  *  @hw: pointer to the HW structure
3789  *
3790  *  Turn on the LEDs.
3791  **/
3792 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3793 {
3794         if (hw->phy.type == e1000_phy_ife)
3795                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3796                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3797
3798         ew32(LEDCTL, hw->mac.ledctl_mode2);
3799         return 0;
3800 }
3801
3802 /**
3803  *  e1000_led_off_ich8lan - Turn LEDs off
3804  *  @hw: pointer to the HW structure
3805  *
3806  *  Turn off the LEDs.
3807  **/
3808 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3809 {
3810         if (hw->phy.type == e1000_phy_ife)
3811                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3812                                 (IFE_PSCL_PROBE_MODE |
3813                                  IFE_PSCL_PROBE_LEDS_OFF));
3814
3815         ew32(LEDCTL, hw->mac.ledctl_mode1);
3816         return 0;
3817 }
3818
3819 /**
3820  *  e1000_setup_led_pchlan - Configures SW controllable LED
3821  *  @hw: pointer to the HW structure
3822  *
3823  *  This prepares the SW controllable LED for use.
3824  **/
3825 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3826 {
3827         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3828 }
3829
3830 /**
3831  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3832  *  @hw: pointer to the HW structure
3833  *
3834  *  Return the LED back to the default configuration.
3835  **/
3836 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3837 {
3838         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3839 }
3840
3841 /**
3842  *  e1000_led_on_pchlan - Turn LEDs on
3843  *  @hw: pointer to the HW structure
3844  *
3845  *  Turn on the LEDs.
3846  **/
3847 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3848 {
3849         u16 data = (u16)hw->mac.ledctl_mode2;
3850         u32 i, led;
3851
3852         /*
3853          * If no link, then turn LED on by setting the invert bit
3854          * for each LED that's mode is "link_up" in ledctl_mode2.
3855          */
3856         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3857                 for (i = 0; i < 3; i++) {
3858                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3859                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3860                             E1000_LEDCTL_MODE_LINK_UP)
3861                                 continue;
3862                         if (led & E1000_PHY_LED0_IVRT)
3863                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3864                         else
3865                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3866                 }
3867         }
3868
3869         return e1e_wphy(hw, HV_LED_CONFIG, data);
3870 }
3871
3872 /**
3873  *  e1000_led_off_pchlan - Turn LEDs off
3874  *  @hw: pointer to the HW structure
3875  *
3876  *  Turn off the LEDs.
3877  **/
3878 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3879 {
3880         u16 data = (u16)hw->mac.ledctl_mode1;
3881         u32 i, led;
3882
3883         /*
3884          * If no link, then turn LED off by clearing the invert bit
3885          * for each LED that's mode is "link_up" in ledctl_mode1.
3886          */
3887         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3888                 for (i = 0; i < 3; i++) {
3889                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3890                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3891                             E1000_LEDCTL_MODE_LINK_UP)
3892                                 continue;
3893                         if (led & E1000_PHY_LED0_IVRT)
3894                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3895                         else
3896                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3897                 }
3898         }
3899
3900         return e1e_wphy(hw, HV_LED_CONFIG, data);
3901 }
3902
3903 /**
3904  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3905  *  @hw: pointer to the HW structure
3906  *
3907  *  Read appropriate register for the config done bit for completion status
3908  *  and configure the PHY through s/w for EEPROM-less parts.
3909  *
3910  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3911  *  config done bit, so only an error is logged and continues.  If we were
3912  *  to return with error, EEPROM-less silicon would not be able to be reset
3913  *  or change link.
3914  **/
3915 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3916 {
3917         s32 ret_val = 0;
3918         u32 bank = 0;
3919         u32 status;
3920
3921         e1000e_get_cfg_done(hw);
3922
3923         /* Wait for indication from h/w that it has completed basic config */
3924         if (hw->mac.type >= e1000_ich10lan) {
3925                 e1000_lan_init_done_ich8lan(hw);
3926         } else {
3927                 ret_val = e1000e_get_auto_rd_done(hw);
3928                 if (ret_val) {
3929                         /*
3930                          * When auto config read does not complete, do not
3931                          * return with an error. This can happen in situations
3932                          * where there is no eeprom and prevents getting link.
3933                          */
3934                         e_dbg("Auto Read Done did not complete\n");
3935                         ret_val = 0;
3936                 }
3937         }
3938
3939         /* Clear PHY Reset Asserted bit */
3940         status = er32(STATUS);
3941         if (status & E1000_STATUS_PHYRA)
3942                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3943         else
3944                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3945
3946         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3947         if (hw->mac.type <= e1000_ich9lan) {
3948                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3949                     (hw->phy.type == e1000_phy_igp_3)) {
3950                         e1000e_phy_init_script_igp3(hw);
3951                 }
3952         } else {
3953                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3954                         /* Maybe we should do a basic PHY config */
3955                         e_dbg("EEPROM not present\n");
3956                         ret_val = -E1000_ERR_CONFIG;
3957                 }
3958         }
3959
3960         return ret_val;
3961 }
3962
3963 /**
3964  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3965  * @hw: pointer to the HW structure
3966  *
3967  * In the case of a PHY power down to save power, or to turn off link during a
3968  * driver unload, or wake on lan is not enabled, remove the link.
3969  **/
3970 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3971 {
3972         /* If the management interface is not enabled, then power down */
3973         if (!(hw->mac.ops.check_mng_mode(hw) ||
3974               hw->phy.ops.check_reset_block(hw)))
3975                 e1000_power_down_phy_copper(hw);
3976 }
3977
3978 /**
3979  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3980  *  @hw: pointer to the HW structure
3981  *
3982  *  Clears hardware counters specific to the silicon family and calls
3983  *  clear_hw_cntrs_generic to clear all general purpose counters.
3984  **/
3985 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3986 {
3987         u16 phy_data;
3988         s32 ret_val;
3989
3990         e1000e_clear_hw_cntrs_base(hw);
3991
3992         er32(ALGNERRC);
3993         er32(RXERRC);
3994         er32(TNCRS);
3995         er32(CEXTERR);
3996         er32(TSCTC);
3997         er32(TSCTFC);
3998
3999         er32(MGTPRC);
4000         er32(MGTPDC);
4001         er32(MGTPTC);
4002
4003         er32(IAC);
4004         er32(ICRXOC);
4005
4006         /* Clear PHY statistics registers */
4007         if ((hw->phy.type == e1000_phy_82578) ||
4008             (hw->phy.type == e1000_phy_82579) ||
4009             (hw->phy.type == e1000_phy_82577)) {
4010                 ret_val = hw->phy.ops.acquire(hw);
4011                 if (ret_val)
4012                         return;
4013                 ret_val = hw->phy.ops.set_page(hw,
4014                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4015                 if (ret_val)
4016                         goto release;
4017                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4018                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4019                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4020                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4021                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4022                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4023                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4024                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4025                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4026                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4027                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4028                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4029                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4030                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4031 release:
4032                 hw->phy.ops.release(hw);
4033         }
4034 }
4035
4036 static const struct e1000_mac_operations ich8_mac_ops = {
4037         .id_led_init            = e1000e_id_led_init,
4038         /* check_mng_mode dependent on mac type */
4039         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4040         /* cleanup_led dependent on mac type */
4041         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4042         .get_bus_info           = e1000_get_bus_info_ich8lan,
4043         .set_lan_id             = e1000_set_lan_id_single_port,
4044         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4045         /* led_on dependent on mac type */
4046         /* led_off dependent on mac type */
4047         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4048         .reset_hw               = e1000_reset_hw_ich8lan,
4049         .init_hw                = e1000_init_hw_ich8lan,
4050         .setup_link             = e1000_setup_link_ich8lan,
4051         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4052         /* id_led_init dependent on mac type */
4053 };
4054
4055 static const struct e1000_phy_operations ich8_phy_ops = {
4056         .acquire                = e1000_acquire_swflag_ich8lan,
4057         .check_reset_block      = e1000_check_reset_block_ich8lan,
4058         .commit                 = NULL,
4059         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4060         .get_cable_length       = e1000e_get_cable_length_igp_2,
4061         .read_reg               = e1000e_read_phy_reg_igp,
4062         .release                = e1000_release_swflag_ich8lan,
4063         .reset                  = e1000_phy_hw_reset_ich8lan,
4064         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4065         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4066         .write_reg              = e1000e_write_phy_reg_igp,
4067 };
4068
4069 static const struct e1000_nvm_operations ich8_nvm_ops = {
4070         .acquire                = e1000_acquire_nvm_ich8lan,
4071         .read                   = e1000_read_nvm_ich8lan,
4072         .release                = e1000_release_nvm_ich8lan,
4073         .update                 = e1000_update_nvm_checksum_ich8lan,
4074         .valid_led_default      = e1000_valid_led_default_ich8lan,
4075         .validate               = e1000_validate_nvm_checksum_ich8lan,
4076         .write                  = e1000_write_nvm_ich8lan,
4077 };
4078
4079 const struct e1000_info e1000_ich8_info = {
4080         .mac                    = e1000_ich8lan,
4081         .flags                  = FLAG_HAS_WOL
4082                                   | FLAG_IS_ICH
4083                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4084                                   | FLAG_HAS_AMT
4085                                   | FLAG_HAS_FLASH
4086                                   | FLAG_APME_IN_WUC,
4087         .pba                    = 8,
4088         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4089         .get_variants           = e1000_get_variants_ich8lan,
4090         .mac_ops                = &ich8_mac_ops,
4091         .phy_ops                = &ich8_phy_ops,
4092         .nvm_ops                = &ich8_nvm_ops,
4093 };
4094
4095 const struct e1000_info e1000_ich9_info = {
4096         .mac                    = e1000_ich9lan,
4097         .flags                  = FLAG_HAS_JUMBO_FRAMES
4098                                   | FLAG_IS_ICH
4099                                   | FLAG_HAS_WOL
4100                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4101                                   | FLAG_HAS_AMT
4102                                   | FLAG_HAS_FLASH
4103                                   | FLAG_APME_IN_WUC,
4104         .pba                    = 18,
4105         .max_hw_frame_size      = DEFAULT_JUMBO,
4106         .get_variants           = e1000_get_variants_ich8lan,
4107         .mac_ops                = &ich8_mac_ops,
4108         .phy_ops                = &ich8_phy_ops,
4109         .nvm_ops                = &ich8_nvm_ops,
4110 };
4111
4112 const struct e1000_info e1000_ich10_info = {
4113         .mac                    = e1000_ich10lan,
4114         .flags                  = FLAG_HAS_JUMBO_FRAMES
4115                                   | FLAG_IS_ICH
4116                                   | FLAG_HAS_WOL
4117                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4118                                   | FLAG_HAS_AMT
4119                                   | FLAG_HAS_FLASH
4120                                   | FLAG_APME_IN_WUC,
4121         .pba                    = 18,
4122         .max_hw_frame_size      = DEFAULT_JUMBO,
4123         .get_variants           = e1000_get_variants_ich8lan,
4124         .mac_ops                = &ich8_mac_ops,
4125         .phy_ops                = &ich8_phy_ops,
4126         .nvm_ops                = &ich8_nvm_ops,
4127 };
4128
4129 const struct e1000_info e1000_pch_info = {
4130         .mac                    = e1000_pchlan,
4131         .flags                  = FLAG_IS_ICH
4132                                   | FLAG_HAS_WOL
4133                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4134                                   | FLAG_HAS_AMT
4135                                   | FLAG_HAS_FLASH
4136                                   | FLAG_HAS_JUMBO_FRAMES
4137                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4138                                   | FLAG_APME_IN_WUC,
4139         .flags2                 = FLAG2_HAS_PHY_STATS,
4140         .pba                    = 26,
4141         .max_hw_frame_size      = 4096,
4142         .get_variants           = e1000_get_variants_ich8lan,
4143         .mac_ops                = &ich8_mac_ops,
4144         .phy_ops                = &ich8_phy_ops,
4145         .nvm_ops                = &ich8_nvm_ops,
4146 };
4147
4148 const struct e1000_info e1000_pch2_info = {
4149         .mac                    = e1000_pch2lan,
4150         .flags                  = FLAG_IS_ICH
4151                                   | FLAG_HAS_WOL
4152                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4153                                   | FLAG_HAS_AMT
4154                                   | FLAG_HAS_FLASH
4155                                   | FLAG_HAS_JUMBO_FRAMES
4156                                   | FLAG_APME_IN_WUC,
4157         .flags2                 = FLAG2_HAS_PHY_STATS
4158                                   | FLAG2_HAS_EEE,
4159         .pba                    = 26,
4160         .max_hw_frame_size      = DEFAULT_JUMBO,
4161         .get_variants           = e1000_get_variants_ich8lan,
4162         .mac_ops                = &ich8_mac_ops,
4163         .phy_ops                = &ich8_phy_ops,
4164         .nvm_ops                = &ich8_nvm_ops,
4165 };