drivers/net/ethernet/intel/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK    0x7
 109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC   0x7
 110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC  0x3
 111
 112 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 113
 114 #define E1000_ICH_RAR_ENTRIES           7
 115
 116 #define PHY_PAGE_SHIFT 5
 117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 118                            ((reg) & MAX_PHY_REG_ADDRESS))
 119 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 120 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 121
 122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 124 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 125
 126 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 127
 128 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 129
 130 /* SMBus Address Phy Register */
 131 #define HV_SMB_ADDR            PHY_REG(768, 26)
 132 #define HV_SMB_ADDR_MASK       0x007F
 133 #define HV_SMB_ADDR_PEC_EN     0x0200
 134 #define HV_SMB_ADDR_VALID      0x0080
 135
 136 /* PHY Power Management Control */
 137 #define HV_PM_CTRL              PHY_REG(770, 17)
 138
 139 /* PHY Low Power Idle Control */
 140 #define I82579_LPI_CTRL                         PHY_REG(772, 20)
 141 #define I82579_LPI_CTRL_ENABLE_MASK             0x6000
 142 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT    0x80
 143
 144 /* EMI Registers */
 145 #define I82579_EMI_ADDR         0x10
 146 #define I82579_EMI_DATA         0x11
 147 #define I82579_LPI_UPDATE_TIMER 0x4805  /* in 40ns units + 40 ns base value */
 148 #define I82579_MSE_THRESHOLD    0x084F  /* Mean Square Error Threshold */
 149 #define I82579_MSE_LINK_DOWN    0x2411  /* MSE count before dropping link */
 150
 151 /* Strapping Option Register - RO */
 152 #define E1000_STRAP                     0x0000C
 153 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 154 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 155
 156 /* OEM Bits Phy Register */
 157 #define HV_OEM_BITS            PHY_REG(768, 25)
 158 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 159 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 160 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 161
 162 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 163 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 164
 165 /* KMRN Mode Control */
 166 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 167 #define HV_KMRN_MDIO_SLOW      0x0400
 168
 169 /* KMRN FIFO Control and Status */
 170 #define HV_KMRN_FIFO_CTRLSTA                  PHY_REG(770, 16)
 171 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK    0x7000
 172 #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT   12
 173
 174 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 175 /* Offset 04h HSFSTS */
 176 union ich8_hws_flash_status {
 177         struct ich8_hsfsts {
 178                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 179                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 180                 u16 dael       :1; /* bit 2 Direct Access error Log */
 181                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 182                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 183                 u16 reserved1  :2; /* bit 13:6 Reserved */
 184                 u16 reserved2  :6; /* bit 13:6 Reserved */
 185                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 186                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 187         } hsf_status;
 188         u16 regval;
 189 };
 190
 191 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 192 /* Offset 06h FLCTL */
 193 union ich8_hws_flash_ctrl {
 194         struct ich8_hsflctl {
 195                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 196                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 197                 u16 reserved   :5;   /* 7:3 Reserved  */
 198                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 199                 u16 flockdn    :6;   /* 15:10 Reserved */
 200         } hsf_ctrl;
 201         u16 regval;
 202 };
 203
 204 /* ICH Flash Region Access Permissions */
 205 union ich8_hws_flash_regacc {
 206         struct ich8_flracc {
 207                 u32 grra      :8; /* 0:7 GbE region Read Access */
 208                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 209                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 210                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 211         } hsf_flregacc;
 212         u16 regval;
 213 };
 214
 215 /* ICH Flash Protected Region */
 216 union ich8_flash_protected_range {
 217         struct ich8_pr {
 218                 u32 base:13;     /* 0:12 Protected Range Base */
 219                 u32 reserved1:2; /* 13:14 Reserved */
 220                 u32 rpe:1;       /* 15 Read Protection Enable */
 221                 u32 limit:13;    /* 16:28 Protected Range Limit */
 222                 u32 reserved2:2; /* 29:30 Reserved */
 223                 u32 wpe:1;       /* 31 Write Protection Enable */
 224         } range;
 225         u32 regval;
 226 };
 227
 228 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 229 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 230 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 231 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 232 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 233                                                 u32 offset, u8 byte);
 234 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 235                                          u8 *data);
 236 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 237                                          u16 *data);
 238 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 239                                          u8 size, u16 *data);
 240 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 241 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 242 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 243 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 244 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 245 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 246 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 247 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 248 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 249 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 250 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 251 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 252 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 253 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 254 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 255 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 256 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 257 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 258 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
 259 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
 260
 261 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 262 {
 263         return readw(hw->flash_address + reg);
 264 }
 265
 266 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 267 {
 268         return readl(hw->flash_address + reg);
 269 }
 270
 271 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 272 {
 273         writew(val, hw->flash_address + reg);
 274 }
 275
 276 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 277 {
 278         writel(val, hw->flash_address + reg);
 279 }
 280
 281 #define er16flash(reg)          __er16flash(hw, (reg))
 282 #define er32flash(reg)          __er32flash(hw, (reg))
 283 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 284 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 285
 286 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
 287 {
 288         u32 ctrl;
 289
 290         ctrl = er32(CTRL);
 291         ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
 292         ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 293         ew32(CTRL, ctrl);
 294         e1e_flush();
 295         udelay(10);
 296         ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 297         ew32(CTRL, ctrl);
 298 }
 299
 300 /**
 301  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 302  *  @hw: pointer to the HW structure
 303  *
 304  *  Initialize family-specific PHY parameters and function pointers.
 305  **/
 306 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 307 {
 308         struct e1000_phy_info *phy = &hw->phy;
 309         s32 ret_val = 0;
 310
 311         phy->addr                     = 1;
 312         phy->reset_delay_us           = 100;
 313
 314         phy->ops.set_page             = e1000_set_page_igp;
 315         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 316         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 317         phy->ops.read_reg_page        = e1000_read_phy_reg_page_hv;
 318         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 319         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 320         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 321         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 322         phy->ops.write_reg_page       = e1000_write_phy_reg_page_hv;
 323         phy->ops.power_up             = e1000_power_up_phy_copper;
 324         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 325         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 326
 327         if (!e1000_check_reset_block(hw)) {
 328                 u32 fwsm = er32(FWSM);
 329
 330                 /*
 331                  * The MAC-PHY interconnect may still be in SMBus mode after
 332                  * Sx->S0.  If resetting the PHY is not blocked, toggle the
 333                  * LANPHYPC Value bit to force the interconnect to PCIe mode.
 334                  */
 335                 e1000_toggle_lanphypc_value_ich8lan(hw);
 336                 msleep(50);
 337
 338                 /*
 339                  * Gate automatic PHY configuration by hardware on
 340                  * non-managed 82579
 341                  */
 342                 if ((hw->mac.type == e1000_pch2lan) &&
 343                     !(fwsm & E1000_ICH_FWSM_FW_VALID))
 344                         e1000_gate_hw_phy_config_ich8lan(hw, true);
 345
 346                 /*
 347                  * Reset the PHY before any access to it.  Doing so, ensures
 348                  * that the PHY is in a known good state before we read/write
 349                  * PHY registers.  The generic reset is sufficient here,
 350                  * because we haven't determined the PHY type yet.
 351                  */
 352                 ret_val = e1000e_phy_hw_reset_generic(hw);
 353                 if (ret_val)
 354                         goto out;
 355
 356                 /* Ungate automatic PHY configuration on non-managed 82579 */
 357                 if ((hw->mac.type == e1000_pch2lan) &&
 358                     !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
 359                         usleep_range(10000, 20000);
 360                         e1000_gate_hw_phy_config_ich8lan(hw, false);
 361                 }
 362         }
 363
 364         phy->id = e1000_phy_unknown;
 365         switch (hw->mac.type) {
 366         default:
 367                 ret_val = e1000e_get_phy_id(hw);
 368                 if (ret_val)
 369                         goto out;
 370                 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
 371                         break;
 372                 /* fall-through */
 373         case e1000_pch2lan:
 374                 /*
 375                  * In case the PHY needs to be in mdio slow mode,
 376                  * set slow mode and try to get the PHY id again.
 377                  */
 378                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 379                 if (ret_val)
 380                         goto out;
 381                 ret_val = e1000e_get_phy_id(hw);
 382                 if (ret_val)
 383                         goto out;
 384                 break;
 385         }
 386         phy->type = e1000e_get_phy_type_from_id(phy->id);
 387
 388         switch (phy->type) {
 389         case e1000_phy_82577:
 390         case e1000_phy_82579:
 391                 phy->ops.check_polarity = e1000_check_polarity_82577;
 392                 phy->ops.force_speed_duplex =
 393                     e1000_phy_force_speed_duplex_82577;
 394                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 395                 phy->ops.get_info = e1000_get_phy_info_82577;
 396                 phy->ops.commit = e1000e_phy_sw_reset;
 397                 break;
 398         case e1000_phy_82578:
 399                 phy->ops.check_polarity = e1000_check_polarity_m88;
 400                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 401                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 402                 phy->ops.get_info = e1000e_get_phy_info_m88;
 403                 break;
 404         default:
 405                 ret_val = -E1000_ERR_PHY;
 406                 break;
 407         }
 408
 409 out:
 410         return ret_val;
 411 }
 412
 413 /**
 414  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 415  *  @hw: pointer to the HW structure
 416  *
 417  *  Initialize family-specific PHY parameters and function pointers.
 418  **/
 419 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 420 {
 421         struct e1000_phy_info *phy = &hw->phy;
 422         s32 ret_val;
 423         u16 i = 0;
 424
 425         phy->addr                       = 1;
 426         phy->reset_delay_us             = 100;
 427
 428         phy->ops.power_up               = e1000_power_up_phy_copper;
 429         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 430
 431         /*
 432          * We may need to do this twice - once for IGP and if that fails,
 433          * we'll set BM func pointers and try again
 434          */
 435         ret_val = e1000e_determine_phy_address(hw);
 436         if (ret_val) {
 437                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 438                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 439                 ret_val = e1000e_determine_phy_address(hw);
 440                 if (ret_val) {
 441                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 442                         return ret_val;
 443                 }
 444         }
 445
 446         phy->id = 0;
 447         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 448                (i++ < 100)) {
 449                 usleep_range(1000, 2000);
 450                 ret_val = e1000e_get_phy_id(hw);
 451                 if (ret_val)
 452                         return ret_val;
 453         }
 454
 455         /* Verify phy id */
 456         switch (phy->id) {
 457         case IGP03E1000_E_PHY_ID:
 458                 phy->type = e1000_phy_igp_3;
 459                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 460                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 461                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 462                 phy->ops.get_info = e1000e_get_phy_info_igp;
 463                 phy->ops.check_polarity = e1000_check_polarity_igp;
 464                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 465                 break;
 466         case IFE_E_PHY_ID:
 467         case IFE_PLUS_E_PHY_ID:
 468         case IFE_C_E_PHY_ID:
 469                 phy->type = e1000_phy_ife;
 470                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 471                 phy->ops.get_info = e1000_get_phy_info_ife;
 472                 phy->ops.check_polarity = e1000_check_polarity_ife;
 473                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 474                 break;
 475         case BME1000_E_PHY_ID:
 476                 phy->type = e1000_phy_bm;
 477                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 478                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 479                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 480                 phy->ops.commit = e1000e_phy_sw_reset;
 481                 phy->ops.get_info = e1000e_get_phy_info_m88;
 482                 phy->ops.check_polarity = e1000_check_polarity_m88;
 483                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 484                 break;
 485         default:
 486                 return -E1000_ERR_PHY;
 487                 break;
 488         }
 489
 490         return 0;
 491 }
 492
 493 /**
 494  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 495  *  @hw: pointer to the HW structure
 496  *
 497  *  Initialize family-specific NVM parameters and function
 498  *  pointers.
 499  **/
 500 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 501 {
 502         struct e1000_nvm_info *nvm = &hw->nvm;
 503         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 504         u32 gfpreg, sector_base_addr, sector_end_addr;
 505         u16 i;
 506
 507         /* Can't read flash registers if the register set isn't mapped. */
 508         if (!hw->flash_address) {
 509                 e_dbg("ERROR: Flash registers not mapped\n");
 510                 return -E1000_ERR_CONFIG;
 511         }
 512
 513         nvm->type = e1000_nvm_flash_sw;
 514
 515         gfpreg = er32flash(ICH_FLASH_GFPREG);
 516
 517         /*
 518          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 519          * Add 1 to sector_end_addr since this sector is included in
 520          * the overall size.
 521          */
 522         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 523         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 524
 525         /* flash_base_addr is byte-aligned */
 526         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 527
 528         /*
 529          * find total size of the NVM, then cut in half since the total
 530          * size represents two separate NVM banks.
 531          */
 532         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 533                                 << FLASH_SECTOR_ADDR_SHIFT;
 534         nvm->flash_bank_size /= 2;
 535         /* Adjust to word count */
 536         nvm->flash_bank_size /= sizeof(u16);
 537
 538         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 539
 540         /* Clear shadow ram */
 541         for (i = 0; i < nvm->word_size; i++) {
 542                 dev_spec->shadow_ram[i].modified = false;
 543                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 544         }
 545
 546         return 0;
 547 }
 548
 549 /**
 550  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 551  *  @hw: pointer to the HW structure
 552  *
 553  *  Initialize family-specific MAC parameters and function
 554  *  pointers.
 555  **/
 556 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 557 {
 558         struct e1000_hw *hw = &adapter->hw;
 559         struct e1000_mac_info *mac = &hw->mac;
 560
 561         /* Set media type function pointer */
 562         hw->phy.media_type = e1000_media_type_copper;
 563
 564         /* Set mta register count */
 565         mac->mta_reg_count = 32;
 566         /* Set rar entry count */
 567         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 568         if (mac->type == e1000_ich8lan)
 569                 mac->rar_entry_count--;
 570         /* FWSM register */
 571         mac->has_fwsm = true;
 572         /* ARC subsystem not supported */
 573         mac->arc_subsystem_valid = false;
 574         /* Adaptive IFS supported */
 575         mac->adaptive_ifs = true;
 576
 577         /* LED operations */
 578         switch (mac->type) {
 579         case e1000_ich8lan:
 580         case e1000_ich9lan:
 581         case e1000_ich10lan:
 582                 /* check management mode */
 583                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 584                 /* ID LED init */
 585                 mac->ops.id_led_init = e1000e_id_led_init;
 586                 /* blink LED */
 587                 mac->ops.blink_led = e1000e_blink_led_generic;
 588                 /* setup LED */
 589                 mac->ops.setup_led = e1000e_setup_led_generic;
 590                 /* cleanup LED */
 591                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 592                 /* turn on/off LED */
 593                 mac->ops.led_on = e1000_led_on_ich8lan;
 594                 mac->ops.led_off = e1000_led_off_ich8lan;
 595                 break;
 596         case e1000_pchlan:
 597         case e1000_pch2lan:
 598                 /* check management mode */
 599                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 600                 /* ID LED init */
 601                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 602                 /* setup LED */
 603                 mac->ops.setup_led = e1000_setup_led_pchlan;
 604                 /* cleanup LED */
 605                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 606                 /* turn on/off LED */
 607                 mac->ops.led_on = e1000_led_on_pchlan;
 608                 mac->ops.led_off = e1000_led_off_pchlan;
 609                 break;
 610         default:
 611                 break;
 612         }
 613
 614         /* Enable PCS Lock-loss workaround for ICH8 */
 615         if (mac->type == e1000_ich8lan)
 616                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 617
 618         /* Gate automatic PHY configuration by hardware on managed 82579 */
 619         if ((mac->type == e1000_pch2lan) &&
 620             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 621                 e1000_gate_hw_phy_config_ich8lan(hw, true);
 622
 623         return 0;
 624 }
 625
 626 /**
 627  *  e1000_set_eee_pchlan - Enable/disable EEE support
 628  *  @hw: pointer to the HW structure
 629  *
 630  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 631  *  the LPI Control register will remain set only if/when link is up.
 632  **/
 633 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 634 {
 635         s32 ret_val = 0;
 636         u16 phy_reg;
 637
 638         if (hw->phy.type != e1000_phy_82579)
 639                 goto out;
 640
 641         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 642         if (ret_val)
 643                 goto out;
 644
 645         if (hw->dev_spec.ich8lan.eee_disable)
 646                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 647         else
 648                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 649
 650         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 651 out:
 652         return ret_val;
 653 }
 654
 655 /**
 656  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 657  *  @hw: pointer to the HW structure
 658  *
 659  *  Checks to see of the link status of the hardware has changed.  If a
 660  *  change in link status has been detected, then we read the PHY registers
 661  *  to get the current speed/duplex if link exists.
 662  **/
 663 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 664 {
 665         struct e1000_mac_info *mac = &hw->mac;
 666         s32 ret_val;
 667         bool link;
 668         u16 phy_reg;
 669
 670         /*
 671          * We only want to go out to the PHY registers to see if Auto-Neg
 672          * has completed and/or if our link status has changed.  The
 673          * get_link_status flag is set upon receiving a Link Status
 674          * Change or Rx Sequence Error interrupt.
 675          */
 676         if (!mac->get_link_status) {
 677                 ret_val = 0;
 678                 goto out;
 679         }
 680
 681         /*
 682          * First we want to see if the MII Status Register reports
 683          * link.  If so, then we want to get the current speed/duplex
 684          * of the PHY.
 685          */
 686         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 687         if (ret_val)
 688                 goto out;
 689
 690         if (hw->mac.type == e1000_pchlan) {
 691                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 692                 if (ret_val)
 693                         goto out;
 694         }
 695
 696         if (!link)
 697                 goto out; /* No link detected */
 698
 699         mac->get_link_status = false;
 700
 701         switch (hw->mac.type) {
 702         case e1000_pch2lan:
 703                 ret_val = e1000_k1_workaround_lv(hw);
 704                 if (ret_val)
 705                         goto out;
 706                 /* fall-thru */
 707         case e1000_pchlan:
 708                 if (hw->phy.type == e1000_phy_82578) {
 709                         ret_val = e1000_link_stall_workaround_hv(hw);
 710                         if (ret_val)
 711                                 goto out;
 712                 }
 713
 714                 /*
 715                  * Workaround for PCHx parts in half-duplex:
 716                  * Set the number of preambles removed from the packet
 717                  * when it is passed from the PHY to the MAC to prevent
 718                  * the MAC from misinterpreting the packet type.
 719                  */
 720                 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
 721                 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
 722
 723                 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
 724                         phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
 725
 726                 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
 727                 break;
 728         default:
 729                 break;
 730         }
 731
 732         /*
 733          * Check if there was DownShift, must be checked
 734          * immediately after link-up
 735          */
 736         e1000e_check_downshift(hw);
 737
 738         /* Enable/Disable EEE after link up */
 739         ret_val = e1000_set_eee_pchlan(hw);
 740         if (ret_val)
 741                 goto out;
 742
 743         /*
 744          * If we are forcing speed/duplex, then we simply return since
 745          * we have already determined whether we have link or not.
 746          */
 747         if (!mac->autoneg) {
 748                 ret_val = -E1000_ERR_CONFIG;
 749                 goto out;
 750         }
 751
 752         /*
 753          * Auto-Neg is enabled.  Auto Speed Detection takes care
 754          * of MAC speed/duplex configuration.  So we only need to
 755          * configure Collision Distance in the MAC.
 756          */
 757         e1000e_config_collision_dist(hw);
 758
 759         /*
 760          * Configure Flow Control now that Auto-Neg has completed.
 761          * First, we need to restore the desired flow control
 762          * settings because we may have had to re-autoneg with a
 763          * different link partner.
 764          */
 765         ret_val = e1000e_config_fc_after_link_up(hw);
 766         if (ret_val)
 767                 e_dbg("Error configuring flow control\n");
 768
 769 out:
 770         return ret_val;
 771 }
 772
 773 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 774 {
 775         struct e1000_hw *hw = &adapter->hw;
 776         s32 rc;
 777
 778         rc = e1000_init_mac_params_ich8lan(adapter);
 779         if (rc)
 780                 return rc;
 781
 782         rc = e1000_init_nvm_params_ich8lan(hw);
 783         if (rc)
 784                 return rc;
 785
 786         switch (hw->mac.type) {
 787         case e1000_ich8lan:
 788         case e1000_ich9lan:
 789         case e1000_ich10lan:
 790                 rc = e1000_init_phy_params_ich8lan(hw);
 791                 break;
 792         case e1000_pchlan:
 793         case e1000_pch2lan:
 794                 rc = e1000_init_phy_params_pchlan(hw);
 795                 break;
 796         default:
 797                 break;
 798         }
 799         if (rc)
 800                 return rc;
 801
 802         /*
 803          * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
 804          * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
 805          */
 806         if ((adapter->hw.phy.type == e1000_phy_ife) ||
 807             ((adapter->hw.mac.type >= e1000_pch2lan) &&
 808              (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
 809                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 810                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 811
 812                 hw->mac.ops.blink_led = NULL;
 813         }
 814
 815         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 816             (adapter->hw.phy.type != e1000_phy_ife))
 817                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 818
 819         /* Enable workaround for 82579 w/ ME enabled */
 820         if ((adapter->hw.mac.type == e1000_pch2lan) &&
 821             (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
 822                 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
 823
 824         /* Disable EEE by default until IEEE802.3az spec is finalized */
 825         if (adapter->flags2 & FLAG2_HAS_EEE)
 826                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 827
 828         return 0;
 829 }
 830
 831 static DEFINE_MUTEX(nvm_mutex);
 832
 833 /**
 834  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 835  *  @hw: pointer to the HW structure
 836  *
 837  *  Acquires the mutex for performing NVM operations.
 838  **/
 839 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 840 {
 841         mutex_lock(&nvm_mutex);
 842
 843         return 0;
 844 }
 845
 846 /**
 847  *  e1000_release_nvm_ich8lan - Release NVM mutex
 848  *  @hw: pointer to the HW structure
 849  *
 850  *  Releases the mutex used while performing NVM operations.
 851  **/
 852 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 853 {
 854         mutex_unlock(&nvm_mutex);
 855 }
 856
 857 /**
 858  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 859  *  @hw: pointer to the HW structure
 860  *
 861  *  Acquires the software control flag for performing PHY and select
 862  *  MAC CSR accesses.
 863  **/
 864 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 865 {
 866         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 867         s32 ret_val = 0;
 868
 869         if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
 870                              &hw->adapter->state)) {
 871                 e_dbg("contention for Phy access\n");
 872                 return -E1000_ERR_PHY;
 873         }
 874
 875         while (timeout) {
 876                 extcnf_ctrl = er32(EXTCNF_CTRL);
 877                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 878                         break;
 879
 880                 mdelay(1);
 881                 timeout--;
 882         }
 883
 884         if (!timeout) {
 885                 e_dbg("SW has already locked the resource.\n");
 886                 ret_val = -E1000_ERR_CONFIG;
 887                 goto out;
 888         }
 889
 890         timeout = SW_FLAG_TIMEOUT;
 891
 892         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 893         ew32(EXTCNF_CTRL, extcnf_ctrl);
 894
 895         while (timeout) {
 896                 extcnf_ctrl = er32(EXTCNF_CTRL);
 897                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 898                         break;
 899
 900                 mdelay(1);
 901                 timeout--;
 902         }
 903
 904         if (!timeout) {
 905                 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
 906                       er32(FWSM), extcnf_ctrl);
 907                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 908                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 909                 ret_val = -E1000_ERR_CONFIG;
 910                 goto out;
 911         }
 912
 913 out:
 914         if (ret_val)
 915                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 916
 917         return ret_val;
 918 }
 919
 920 /**
 921  *  e1000_release_swflag_ich8lan - Release software control flag
 922  *  @hw: pointer to the HW structure
 923  *
 924  *  Releases the software control flag for performing PHY and select
 925  *  MAC CSR accesses.
 926  **/
 927 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 928 {
 929         u32 extcnf_ctrl;
 930
 931         extcnf_ctrl = er32(EXTCNF_CTRL);
 932
 933         if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
 934                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 935                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 936         } else {
 937                 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
 938         }
 939
 940         clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
 941 }
 942
 943 /**
 944  *  e1000_check_mng_mode_ich8lan - Checks management mode
 945  *  @hw: pointer to the HW structure
 946  *
 947  *  This checks if the adapter has any manageability enabled.
 948  *  This is a function pointer entry point only called by read/write
 949  *  routines for the PHY and NVM parts.
 950  **/
 951 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 952 {
 953         u32 fwsm;
 954
 955         fwsm = er32(FWSM);
 956         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 957                ((fwsm & E1000_FWSM_MODE_MASK) ==
 958                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 959 }
 960
 961 /**
 962  *  e1000_check_mng_mode_pchlan - Checks management mode
 963  *  @hw: pointer to the HW structure
 964  *
 965  *  This checks if the adapter has iAMT enabled.
 966  *  This is a function pointer entry point only called by read/write
 967  *  routines for the PHY and NVM parts.
 968  **/
 969 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 970 {
 971         u32 fwsm;
 972
 973         fwsm = er32(FWSM);
 974         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 975                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 976 }
 977
 978 /**
 979  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 980  *  @hw: pointer to the HW structure
 981  *
 982  *  Checks if firmware is blocking the reset of the PHY.
 983  *  This is a function pointer entry point only called by
 984  *  reset routines.
 985  **/
 986 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 987 {
 988         u32 fwsm;
 989
 990         fwsm = er32(FWSM);
 991
 992         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 993 }
 994
 995 /**
 996  *  e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
 997  *  @hw: pointer to the HW structure
 998  *
 999  *  Assumes semaphore already acquired.
1000  *
1001  **/
1002 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
1003 {
1004         u16 phy_data;
1005         u32 strap = er32(STRAP);
1006         s32 ret_val = 0;
1007
1008         strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
1009
1010         ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
1011         if (ret_val)
1012                 goto out;
1013
1014         phy_data &= ~HV_SMB_ADDR_MASK;
1015         phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
1016         phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
1017         ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
1018
1019 out:
1020         return ret_val;
1021 }
1022
1023 /**
1024  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
1025  *  @hw:   pointer to the HW structure
1026  *
1027  *  SW should configure the LCD from the NVM extended configuration region
1028  *  as a workaround for certain parts.
1029  **/
1030 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
1031 {
1032         struct e1000_phy_info *phy = &hw->phy;
1033         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
1034         s32 ret_val = 0;
1035         u16 word_addr, reg_data, reg_addr, phy_page = 0;
1036
1037         /*
1038          * Initialize the PHY from the NVM on ICH platforms.  This
1039          * is needed due to an issue where the NVM configuration is
1040          * not properly autoloaded after power transitions.
1041          * Therefore, after each PHY reset, we will load the
1042          * configuration data out of the NVM manually.
1043          */
1044         switch (hw->mac.type) {
1045         case e1000_ich8lan:
1046                 if (phy->type != e1000_phy_igp_3)
1047                         return ret_val;
1048
1049                 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1050                     (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1051                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1052                         break;
1053                 }
1054                 /* Fall-thru */
1055         case e1000_pchlan:
1056         case e1000_pch2lan:
1057                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1058                 break;
1059         default:
1060                 return ret_val;
1061         }
1062
1063         ret_val = hw->phy.ops.acquire(hw);
1064         if (ret_val)
1065                 return ret_val;
1066
1067         data = er32(FEXTNVM);
1068         if (!(data & sw_cfg_mask))
1069                 goto out;
1070
1071         /*
1072          * Make sure HW does not configure LCD from PHY
1073          * extended configuration before SW configuration
1074          */
1075         data = er32(EXTCNF_CTRL);
1076         if (!(hw->mac.type == e1000_pch2lan)) {
1077                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1078                         goto out;
1079         }
1080
1081         cnf_size = er32(EXTCNF_SIZE);
1082         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1083         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1084         if (!cnf_size)
1085                 goto out;
1086
1087         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1088         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1089
1090         if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1091             (hw->mac.type == e1000_pchlan)) ||
1092              (hw->mac.type == e1000_pch2lan)) {
1093                 /*
1094                  * HW configures the SMBus address and LEDs when the
1095                  * OEM and LCD Write Enable bits are set in the NVM.
1096                  * When both NVM bits are cleared, SW will configure
1097                  * them instead.
1098                  */
1099                 ret_val = e1000_write_smbus_addr(hw);
1100                 if (ret_val)
1101                         goto out;
1102
1103                 data = er32(LEDCTL);
1104                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1105                                                         (u16)data);
1106                 if (ret_val)
1107                         goto out;
1108         }
1109
1110         /* Configure LCD from extended configuration region. */
1111
1112         /* cnf_base_addr is in DWORD */
1113         word_addr = (u16)(cnf_base_addr << 1);
1114
1115         for (i = 0; i < cnf_size; i++) {
1116                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1117                                          &reg_data);
1118                 if (ret_val)
1119                         goto out;
1120
1121                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1122                                          1, &reg_addr);
1123                 if (ret_val)
1124                         goto out;
1125
1126                 /* Save off the PHY page for future writes. */
1127                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1128                         phy_page = reg_data;
1129                         continue;
1130                 }
1131
1132                 reg_addr &= PHY_REG_MASK;
1133                 reg_addr |= phy_page;
1134
1135                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1136                                                     reg_data);
1137                 if (ret_val)
1138                         goto out;
1139         }
1140
1141 out:
1142         hw->phy.ops.release(hw);
1143         return ret_val;
1144 }
1145
1146 /**
1147  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1148  *  @hw:   pointer to the HW structure
1149  *  @link: link up bool flag
1150  *
1151  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1152  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1153  *  If link is down, the function will restore the default K1 setting located
1154  *  in the NVM.
1155  **/
1156 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1157 {
1158         s32 ret_val = 0;
1159         u16 status_reg = 0;
1160         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1161
1162         if (hw->mac.type != e1000_pchlan)
1163                 goto out;
1164
1165         /* Wrap the whole flow with the sw flag */
1166         ret_val = hw->phy.ops.acquire(hw);
1167         if (ret_val)
1168                 goto out;
1169
1170         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1171         if (link) {
1172                 if (hw->phy.type == e1000_phy_82578) {
1173                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1174                                                                   &status_reg);
1175                         if (ret_val)
1176                                 goto release;
1177
1178                         status_reg &= BM_CS_STATUS_LINK_UP |
1179                                       BM_CS_STATUS_RESOLVED |
1180                                       BM_CS_STATUS_SPEED_MASK;
1181
1182                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1183                                            BM_CS_STATUS_RESOLVED |
1184                                            BM_CS_STATUS_SPEED_1000))
1185                                 k1_enable = false;
1186                 }
1187
1188                 if (hw->phy.type == e1000_phy_82577) {
1189                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1190                                                                   &status_reg);
1191                         if (ret_val)
1192                                 goto release;
1193
1194                         status_reg &= HV_M_STATUS_LINK_UP |
1195                                       HV_M_STATUS_AUTONEG_COMPLETE |
1196                                       HV_M_STATUS_SPEED_MASK;
1197
1198                         if (status_reg == (HV_M_STATUS_LINK_UP |
1199                                            HV_M_STATUS_AUTONEG_COMPLETE |
1200                                            HV_M_STATUS_SPEED_1000))
1201                                 k1_enable = false;
1202                 }
1203
1204                 /* Link stall fix for link up */
1205                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1206                                                            0x0100);
1207                 if (ret_val)
1208                         goto release;
1209
1210         } else {
1211                 /* Link stall fix for link down */
1212                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1213                                                            0x4100);
1214                 if (ret_val)
1215                         goto release;
1216         }
1217
1218         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1219
1220 release:
1221         hw->phy.ops.release(hw);
1222 out:
1223         return ret_val;
1224 }
1225
1226 /**
1227  *  e1000_configure_k1_ich8lan - Configure K1 power state
1228  *  @hw: pointer to the HW structure
1229  *  @enable: K1 state to configure
1230  *
1231  *  Configure the K1 power state based on the provided parameter.
1232  *  Assumes semaphore already acquired.
1233  *
1234  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1235  **/
1236 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1237 {
1238         s32 ret_val = 0;
1239         u32 ctrl_reg = 0;
1240         u32 ctrl_ext = 0;
1241         u32 reg = 0;
1242         u16 kmrn_reg = 0;
1243
1244         ret_val = e1000e_read_kmrn_reg_locked(hw,
1245                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1246                                              &kmrn_reg);
1247         if (ret_val)
1248                 goto out;
1249
1250         if (k1_enable)
1251                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1252         else
1253                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1254
1255         ret_val = e1000e_write_kmrn_reg_locked(hw,
1256                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1257                                               kmrn_reg);
1258         if (ret_val)
1259                 goto out;
1260
1261         udelay(20);
1262         ctrl_ext = er32(CTRL_EXT);
1263         ctrl_reg = er32(CTRL);
1264
1265         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1266         reg |= E1000_CTRL_FRCSPD;
1267         ew32(CTRL, reg);
1268
1269         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1270         e1e_flush();
1271         udelay(20);
1272         ew32(CTRL, ctrl_reg);
1273         ew32(CTRL_EXT, ctrl_ext);
1274         e1e_flush();
1275         udelay(20);
1276
1277 out:
1278         return ret_val;
1279 }
1280
1281 /**
1282  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1283  *  @hw:       pointer to the HW structure
1284  *  @d0_state: boolean if entering d0 or d3 device state
1285  *
1286  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1287  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1288  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1289  **/
1290 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1291 {
1292         s32 ret_val = 0;
1293         u32 mac_reg;
1294         u16 oem_reg;
1295
1296         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1297                 return ret_val;
1298
1299         ret_val = hw->phy.ops.acquire(hw);
1300         if (ret_val)
1301                 return ret_val;
1302
1303         if (!(hw->mac.type == e1000_pch2lan)) {
1304                 mac_reg = er32(EXTCNF_CTRL);
1305                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1306                         goto out;
1307         }
1308
1309         mac_reg = er32(FEXTNVM);
1310         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1311                 goto out;
1312
1313         mac_reg = er32(PHY_CTRL);
1314
1315         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1316         if (ret_val)
1317                 goto out;
1318
1319         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1320
1321         if (d0_state) {
1322                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1323                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1324
1325                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1326                         oem_reg |= HV_OEM_BITS_LPLU;
1327
1328                 /* Set Restart auto-neg to activate the bits */
1329                 if (!e1000_check_reset_block(hw))
1330                         oem_reg |= HV_OEM_BITS_RESTART_AN;
1331         } else {
1332                 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
1333                                E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
1334                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1335
1336                 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
1337                                E1000_PHY_CTRL_NOND0A_LPLU))
1338                         oem_reg |= HV_OEM_BITS_LPLU;
1339         }
1340
1341         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1342
1343 out:
1344         hw->phy.ops.release(hw);
1345
1346         return ret_val;
1347 }
1348
1349
1350 /**
1351  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1352  *  @hw:   pointer to the HW structure
1353  **/
1354 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1355 {
1356         s32 ret_val;
1357         u16 data;
1358
1359         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1360         if (ret_val)
1361                 return ret_val;
1362
1363         data |= HV_KMRN_MDIO_SLOW;
1364
1365         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1366
1367         return ret_val;
1368 }
1369
1370 /**
1371  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1372  *  done after every PHY reset.
1373  **/
1374 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1375 {
1376         s32 ret_val = 0;
1377         u16 phy_data;
1378
1379         if (hw->mac.type != e1000_pchlan)
1380                 return ret_val;
1381
1382         /* Set MDIO slow mode before any other MDIO access */
1383         if (hw->phy.type == e1000_phy_82577) {
1384                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1385                 if (ret_val)
1386                         goto out;
1387         }
1388
1389         if (((hw->phy.type == e1000_phy_82577) &&
1390              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1391             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1392                 /* Disable generation of early preamble */
1393                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1394                 if (ret_val)
1395                         return ret_val;
1396
1397                 /* Preamble tuning for SSC */
1398                 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
1399                 if (ret_val)
1400                         return ret_val;
1401         }
1402
1403         if (hw->phy.type == e1000_phy_82578) {
1404                 /*
1405                  * Return registers to default by doing a soft reset then
1406                  * writing 0x3140 to the control register.
1407                  */
1408                 if (hw->phy.revision < 2) {
1409                         e1000e_phy_sw_reset(hw);
1410                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1411                 }
1412         }
1413
1414         /* Select page 0 */
1415         ret_val = hw->phy.ops.acquire(hw);
1416         if (ret_val)
1417                 return ret_val;
1418
1419         hw->phy.addr = 1;
1420         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1421         hw->phy.ops.release(hw);
1422         if (ret_val)
1423                 goto out;
1424
1425         /*
1426          * Configure the K1 Si workaround during phy reset assuming there is
1427          * link so that it disables K1 if link is in 1Gbps.
1428          */
1429         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1430         if (ret_val)
1431                 goto out;
1432
1433         /* Workaround for link disconnects on a busy hub in half duplex */
1434         ret_val = hw->phy.ops.acquire(hw);
1435         if (ret_val)
1436                 goto out;
1437         ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1438         if (ret_val)
1439                 goto release;
1440         ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1441                                                phy_data & 0x00FF);
1442 release:
1443         hw->phy.ops.release(hw);
1444 out:
1445         return ret_val;
1446 }
1447
1448 /**
1449  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1450  *  @hw:   pointer to the HW structure
1451  **/
1452 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1453 {
1454         u32 mac_reg;
1455         u16 i, phy_reg = 0;
1456         s32 ret_val;
1457
1458         ret_val = hw->phy.ops.acquire(hw);
1459         if (ret_val)
1460                 return;
1461         ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1462         if (ret_val)
1463                 goto release;
1464
1465         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1466         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1467                 mac_reg = er32(RAL(i));
1468                 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1469                                            (u16)(mac_reg & 0xFFFF));
1470                 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1471                                            (u16)((mac_reg >> 16) & 0xFFFF));
1472
1473                 mac_reg = er32(RAH(i));
1474                 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1475                                            (u16)(mac_reg & 0xFFFF));
1476                 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1477                                            (u16)((mac_reg & E1000_RAH_AV)
1478                                                  >> 16));
1479         }
1480
1481         e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1482
1483 release:
1484         hw->phy.ops.release(hw);
1485 }
1486
1487 /**
1488  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1489  *  with 82579 PHY
1490  *  @hw: pointer to the HW structure
1491  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1492  **/
1493 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1494 {
1495         s32 ret_val = 0;
1496         u16 phy_reg, data;
1497         u32 mac_reg;
1498         u16 i;
1499
1500         if (hw->mac.type != e1000_pch2lan)
1501                 goto out;
1502
1503         /* disable Rx path while enabling/disabling workaround */
1504         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1505         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1506         if (ret_val)
1507                 goto out;
1508
1509         if (enable) {
1510                 /*
1511                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1512                  * SHRAL/H) and initial CRC values to the MAC
1513                  */
1514                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1515                         u8 mac_addr[ETH_ALEN] = {0};
1516                         u32 addr_high, addr_low;
1517
1518                         addr_high = er32(RAH(i));
1519                         if (!(addr_high & E1000_RAH_AV))
1520                                 continue;
1521                         addr_low = er32(RAL(i));
1522                         mac_addr[0] = (addr_low & 0xFF);
1523                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1524                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1525                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1526                         mac_addr[4] = (addr_high & 0xFF);
1527                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1528
1529                         ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1530                 }
1531
1532                 /* Write Rx addresses to the PHY */
1533                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1534
1535                 /* Enable jumbo frame workaround in the MAC */
1536                 mac_reg = er32(FFLT_DBG);
1537                 mac_reg &= ~(1 << 14);
1538                 mac_reg |= (7 << 15);
1539                 ew32(FFLT_DBG, mac_reg);
1540
1541                 mac_reg = er32(RCTL);
1542                 mac_reg |= E1000_RCTL_SECRC;
1543                 ew32(RCTL, mac_reg);
1544
1545                 ret_val = e1000e_read_kmrn_reg(hw,
1546                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1547                                                 &data);
1548                 if (ret_val)
1549                         goto out;
1550                 ret_val = e1000e_write_kmrn_reg(hw,
1551                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1552                                                 data | (1 << 0));
1553                 if (ret_val)
1554                         goto out;
1555                 ret_val = e1000e_read_kmrn_reg(hw,
1556                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1557                                                 &data);
1558                 if (ret_val)
1559                         goto out;
1560                 data &= ~(0xF << 8);
1561                 data |= (0xB << 8);
1562                 ret_val = e1000e_write_kmrn_reg(hw,
1563                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1564                                                 data);
1565                 if (ret_val)
1566                         goto out;
1567
1568                 /* Enable jumbo frame workaround in the PHY */
1569                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1570                 data &= ~(0x7F << 5);
1571                 data |= (0x37 << 5);
1572                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1573                 if (ret_val)
1574                         goto out;
1575                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1576                 data &= ~(1 << 13);
1577                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1578                 if (ret_val)
1579                         goto out;
1580                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1581                 data &= ~(0x3FF << 2);
1582                 data |= (0x1A << 2);
1583                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1584                 if (ret_val)
1585                         goto out;
1586                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
1587                 if (ret_val)
1588                         goto out;
1589                 e1e_rphy(hw, HV_PM_CTRL, &data);
1590                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1591                 if (ret_val)
1592                         goto out;
1593         } else {
1594                 /* Write MAC register values back to h/w defaults */
1595                 mac_reg = er32(FFLT_DBG);
1596                 mac_reg &= ~(0xF << 14);
1597                 ew32(FFLT_DBG, mac_reg);
1598
1599                 mac_reg = er32(RCTL);
1600                 mac_reg &= ~E1000_RCTL_SECRC;
1601                 ew32(RCTL, mac_reg);
1602
1603                 ret_val = e1000e_read_kmrn_reg(hw,
1604                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1605                                                 &data);
1606                 if (ret_val)
1607                         goto out;
1608                 ret_val = e1000e_write_kmrn_reg(hw,
1609                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1610                                                 data & ~(1 << 0));
1611                 if (ret_val)
1612                         goto out;
1613                 ret_val = e1000e_read_kmrn_reg(hw,
1614                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1615                                                 &data);
1616                 if (ret_val)
1617                         goto out;
1618                 data &= ~(0xF << 8);
1619                 data |= (0xB << 8);
1620                 ret_val = e1000e_write_kmrn_reg(hw,
1621                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1622                                                 data);
1623                 if (ret_val)
1624                         goto out;
1625
1626                 /* Write PHY register values back to h/w defaults */
1627                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1628                 data &= ~(0x7F << 5);
1629                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1630                 if (ret_val)
1631                         goto out;
1632                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1633                 data |= (1 << 13);
1634                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1635                 if (ret_val)
1636                         goto out;
1637                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1638                 data &= ~(0x3FF << 2);
1639                 data |= (0x8 << 2);
1640                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1641                 if (ret_val)
1642                         goto out;
1643                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1644                 if (ret_val)
1645                         goto out;
1646                 e1e_rphy(hw, HV_PM_CTRL, &data);
1647                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1648                 if (ret_val)
1649                         goto out;
1650         }
1651
1652         /* re-enable Rx path after enabling/disabling workaround */
1653         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1654
1655 out:
1656         return ret_val;
1657 }
1658
1659 /**
1660  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1661  *  done after every PHY reset.
1662  **/
1663 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1664 {
1665         s32 ret_val = 0;
1666
1667         if (hw->mac.type != e1000_pch2lan)
1668                 goto out;
1669
1670         /* Set MDIO slow mode before any other MDIO access */
1671         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1672
1673         ret_val = hw->phy.ops.acquire(hw);
1674         if (ret_val)
1675                 goto out;
1676         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1677                                                I82579_MSE_THRESHOLD);
1678         if (ret_val)
1679                 goto release;
1680         /* set MSE higher to enable link to stay up when noise is high */
1681         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0034);
1682         if (ret_val)
1683                 goto release;
1684         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1685                                                I82579_MSE_LINK_DOWN);
1686         if (ret_val)
1687                 goto release;
1688         /* drop link after 5 times MSE threshold was reached */
1689         ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA, 0x0005);
1690 release:
1691         hw->phy.ops.release(hw);
1692
1693 out:
1694         return ret_val;
1695 }
1696
1697 /**
1698  *  e1000_k1_gig_workaround_lv - K1 Si workaround
1699  *  @hw:   pointer to the HW structure
1700  *
1701  *  Workaround to set the K1 beacon duration for 82579 parts
1702  **/
1703 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1704 {
1705         s32 ret_val = 0;
1706         u16 status_reg = 0;
1707         u32 mac_reg;
1708         u16 phy_reg;
1709
1710         if (hw->mac.type != e1000_pch2lan)
1711                 goto out;
1712
1713         /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1714         ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1715         if (ret_val)
1716                 goto out;
1717
1718         if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1719             == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1720                 mac_reg = er32(FEXTNVM4);
1721                 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1722
1723                 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
1724                 if (ret_val)
1725                         goto out;
1726
1727                 if (status_reg & HV_M_STATUS_SPEED_1000) {
1728                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1729                         phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1730                 } else {
1731                         mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1732                         phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT;
1733                 }
1734                 ew32(FEXTNVM4, mac_reg);
1735                 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
1736         }
1737
1738 out:
1739         return ret_val;
1740 }
1741
1742 /**
1743  *  e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1744  *  @hw:   pointer to the HW structure
1745  *  @gate: boolean set to true to gate, false to ungate
1746  *
1747  *  Gate/ungate the automatic PHY configuration via hardware; perform
1748  *  the configuration via software instead.
1749  **/
1750 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1751 {
1752         u32 extcnf_ctrl;
1753
1754         if (hw->mac.type != e1000_pch2lan)
1755                 return;
1756
1757         extcnf_ctrl = er32(EXTCNF_CTRL);
1758
1759         if (gate)
1760                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1761         else
1762                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1763
1764         ew32(EXTCNF_CTRL, extcnf_ctrl);
1765         return;
1766 }
1767
1768 /**
1769  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1770  *  @hw: pointer to the HW structure
1771  *
1772  *  Check the appropriate indication the MAC has finished configuring the
1773  *  PHY after a software reset.
1774  **/
1775 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1776 {
1777         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1778
1779         /* Wait for basic configuration completes before proceeding */
1780         do {
1781                 data = er32(STATUS);
1782                 data &= E1000_STATUS_LAN_INIT_DONE;
1783                 udelay(100);
1784         } while ((!data) && --loop);
1785
1786         /*
1787          * If basic configuration is incomplete before the above loop
1788          * count reaches 0, loading the configuration from NVM will
1789          * leave the PHY in a bad state possibly resulting in no link.
1790          */
1791         if (loop == 0)
1792                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1793
1794         /* Clear the Init Done bit for the next init event */
1795         data = er32(STATUS);
1796         data &= ~E1000_STATUS_LAN_INIT_DONE;
1797         ew32(STATUS, data);
1798 }
1799
1800 /**
1801  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1802  *  @hw: pointer to the HW structure
1803  **/
1804 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1805 {
1806         s32 ret_val = 0;
1807         u16 reg;
1808
1809         if (e1000_check_reset_block(hw))
1810                 goto out;
1811
1812         /* Allow time for h/w to get to quiescent state after reset */
1813         usleep_range(10000, 20000);
1814
1815         /* Perform any necessary post-reset workarounds */
1816         switch (hw->mac.type) {
1817         case e1000_pchlan:
1818                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1819                 if (ret_val)
1820                         goto out;
1821                 break;
1822         case e1000_pch2lan:
1823                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1824                 if (ret_val)
1825                         goto out;
1826                 break;
1827         default:
1828                 break;
1829         }
1830
1831         /* Clear the host wakeup bit after lcd reset */
1832         if (hw->mac.type >= e1000_pchlan) {
1833                 e1e_rphy(hw, BM_PORT_GEN_CFG, &reg);
1834                 reg &= ~BM_WUC_HOST_WU_BIT;
1835                 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1836         }
1837
1838         /* Configure the LCD with the extended configuration region in NVM */
1839         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1840         if (ret_val)
1841                 goto out;
1842
1843         /* Configure the LCD with the OEM bits in NVM */
1844         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1845
1846         if (hw->mac.type == e1000_pch2lan) {
1847                 /* Ungate automatic PHY configuration on non-managed 82579 */
1848                 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1849                         usleep_range(10000, 20000);
1850                         e1000_gate_hw_phy_config_ich8lan(hw, false);
1851                 }
1852
1853                 /* Set EEE LPI Update Timer to 200usec */
1854                 ret_val = hw->phy.ops.acquire(hw);
1855                 if (ret_val)
1856                         goto out;
1857                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1858                                                        I82579_LPI_UPDATE_TIMER);
1859                 if (ret_val)
1860                         goto release;
1861                 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1862                                                        0x1387);
1863 release:
1864                 hw->phy.ops.release(hw);
1865         }
1866
1867 out:
1868         return ret_val;
1869 }
1870
1871 /**
1872  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1873  *  @hw: pointer to the HW structure
1874  *
1875  *  Resets the PHY
1876  *  This is a function pointer entry point called by drivers
1877  *  or other shared routines.
1878  **/
1879 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1880 {
1881         s32 ret_val = 0;
1882
1883         /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1884         if ((hw->mac.type == e1000_pch2lan) &&
1885             !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1886                 e1000_gate_hw_phy_config_ich8lan(hw, true);
1887
1888         ret_val = e1000e_phy_hw_reset_generic(hw);
1889         if (ret_val)
1890                 goto out;
1891
1892         ret_val = e1000_post_phy_reset_ich8lan(hw);
1893
1894 out:
1895         return ret_val;
1896 }
1897
1898 /**
1899  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1900  *  @hw: pointer to the HW structure
1901  *  @active: true to enable LPLU, false to disable
1902  *
1903  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1904  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1905  *  the phy speed. This function will manually set the LPLU bit and restart
1906  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1907  *  since it configures the same bit.
1908  **/
1909 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1910 {
1911         s32 ret_val = 0;
1912         u16 oem_reg;
1913
1914         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1915         if (ret_val)
1916                 goto out;
1917
1918         if (active)
1919                 oem_reg |= HV_OEM_BITS_LPLU;
1920         else
1921                 oem_reg &= ~HV_OEM_BITS_LPLU;
1922
1923         if (!e1000_check_reset_block(hw))
1924                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1925
1926         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1927
1928 out:
1929         return ret_val;
1930 }
1931
1932 /**
1933  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1934  *  @hw: pointer to the HW structure
1935  *  @active: true to enable LPLU, false to disable
1936  *
1937  *  Sets the LPLU D0 state according to the active flag.  When
1938  *  activating LPLU this function also disables smart speed
1939  *  and vice versa.  LPLU will not be activated unless the
1940  *  device autonegotiation advertisement meets standards of
1941  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1942  *  This is a function pointer entry point only called by
1943  *  PHY setup routines.
1944  **/
1945 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1946 {
1947         struct e1000_phy_info *phy = &hw->phy;
1948         u32 phy_ctrl;
1949         s32 ret_val = 0;
1950         u16 data;
1951
1952         if (phy->type == e1000_phy_ife)
1953                 return ret_val;
1954
1955         phy_ctrl = er32(PHY_CTRL);
1956
1957         if (active) {
1958                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1959                 ew32(PHY_CTRL, phy_ctrl);
1960
1961                 if (phy->type != e1000_phy_igp_3)
1962                         return 0;
1963
1964                 /*
1965                  * Call gig speed drop workaround on LPLU before accessing
1966                  * any PHY registers
1967                  */
1968                 if (hw->mac.type == e1000_ich8lan)
1969                         e1000e_gig_downshift_workaround_ich8lan(hw);
1970
1971                 /* When LPLU is enabled, we should disable SmartSpeed */
1972                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1973                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1974                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1975                 if (ret_val)
1976                         return ret_val;
1977         } else {
1978                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1979                 ew32(PHY_CTRL, phy_ctrl);
1980
1981                 if (phy->type != e1000_phy_igp_3)
1982                         return 0;
1983
1984                 /*
1985                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1986                  * during Dx states where the power conservation is most
1987                  * important.  During driver activity we should enable
1988                  * SmartSpeed, so performance is maintained.
1989                  */
1990                 if (phy->smart_speed == e1000_smart_speed_on) {
1991                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1992                                            &data);
1993                         if (ret_val)
1994                                 return ret_val;
1995
1996                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1997                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1998                                            data);
1999                         if (ret_val)
2000                                 return ret_val;
2001                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2002                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2003                                            &data);
2004                         if (ret_val)
2005                                 return ret_val;
2006
2007                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2008                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2009                                            data);
2010                         if (ret_val)
2011                                 return ret_val;
2012                 }
2013         }
2014
2015         return 0;
2016 }
2017
2018 /**
2019  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
2020  *  @hw: pointer to the HW structure
2021  *  @active: true to enable LPLU, false to disable
2022  *
2023  *  Sets the LPLU D3 state according to the active flag.  When
2024  *  activating LPLU this function also disables smart speed
2025  *  and vice versa.  LPLU will not be activated unless the
2026  *  device autonegotiation advertisement meets standards of
2027  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
2028  *  This is a function pointer entry point only called by
2029  *  PHY setup routines.
2030  **/
2031 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2032 {
2033         struct e1000_phy_info *phy = &hw->phy;
2034         u32 phy_ctrl;
2035         s32 ret_val;
2036         u16 data;
2037
2038         phy_ctrl = er32(PHY_CTRL);
2039
2040         if (!active) {
2041                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
2042                 ew32(PHY_CTRL, phy_ctrl);
2043
2044                 if (phy->type != e1000_phy_igp_3)
2045                         return 0;
2046
2047                 /*
2048                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
2049                  * during Dx states where the power conservation is most
2050                  * important.  During driver activity we should enable
2051                  * SmartSpeed, so performance is maintained.
2052                  */
2053                 if (phy->smart_speed == e1000_smart_speed_on) {
2054                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2055                                            &data);
2056                         if (ret_val)
2057                                 return ret_val;
2058
2059                         data |= IGP01E1000_PSCFR_SMART_SPEED;
2060                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2061                                            data);
2062                         if (ret_val)
2063                                 return ret_val;
2064                 } else if (phy->smart_speed == e1000_smart_speed_off) {
2065                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2066                                            &data);
2067                         if (ret_val)
2068                                 return ret_val;
2069
2070                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2071                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2072                                            data);
2073                         if (ret_val)
2074                                 return ret_val;
2075                 }
2076         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2077                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2078                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2079                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2080                 ew32(PHY_CTRL, phy_ctrl);
2081
2082                 if (phy->type != e1000_phy_igp_3)
2083                         return 0;
2084
2085                 /*
2086                  * Call gig speed drop workaround on LPLU before accessing
2087                  * any PHY registers
2088                  */
2089                 if (hw->mac.type == e1000_ich8lan)
2090                         e1000e_gig_downshift_workaround_ich8lan(hw);
2091
2092                 /* When LPLU is enabled, we should disable SmartSpeed */
2093                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2094                 if (ret_val)
2095                         return ret_val;
2096
2097                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2098                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2099         }
2100
2101         return 0;
2102 }
2103
2104 /**
2105  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2106  *  @hw: pointer to the HW structure
2107  *  @bank:  pointer to the variable that returns the active bank
2108  *
2109  *  Reads signature byte from the NVM using the flash access registers.
2110  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2111  **/
2112 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2113 {
2114         u32 eecd;
2115         struct e1000_nvm_info *nvm = &hw->nvm;
2116         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2117         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2118         u8 sig_byte = 0;
2119         s32 ret_val = 0;
2120
2121         switch (hw->mac.type) {
2122         case e1000_ich8lan:
2123         case e1000_ich9lan:
2124                 eecd = er32(EECD);
2125                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2126                     E1000_EECD_SEC1VAL_VALID_MASK) {
2127                         if (eecd & E1000_EECD_SEC1VAL)
2128                                 *bank = 1;
2129                         else
2130                                 *bank = 0;
2131
2132                         return 0;
2133                 }
2134                 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
2135                 /* fall-thru */
2136         default:
2137                 /* set bank to 0 in case flash read fails */
2138                 *bank = 0;
2139
2140                 /* Check bank 0 */
2141                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2142                                                         &sig_byte);
2143                 if (ret_val)
2144                         return ret_val;
2145                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2146                     E1000_ICH_NVM_SIG_VALUE) {
2147                         *bank = 0;
2148                         return 0;
2149                 }
2150
2151                 /* Check bank 1 */
2152                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2153                                                         bank1_offset,
2154                                                         &sig_byte);
2155                 if (ret_val)
2156                         return ret_val;
2157                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2158                     E1000_ICH_NVM_SIG_VALUE) {
2159                         *bank = 1;
2160                         return 0;
2161                 }
2162
2163                 e_dbg("ERROR: No valid NVM bank present\n");
2164                 return -E1000_ERR_NVM;
2165         }
2166
2167         return 0;
2168 }
2169
2170 /**
2171  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
2172  *  @hw: pointer to the HW structure
2173  *  @offset: The offset (in bytes) of the word(s) to read.
2174  *  @words: Size of data to read in words
2175  *  @data: Pointer to the word(s) to read at offset.
2176  *
2177  *  Reads a word(s) from the NVM using the flash access registers.
2178  **/
2179 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2180                                   u16 *data)
2181 {
2182         struct e1000_nvm_info *nvm = &hw->nvm;
2183         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2184         u32 act_offset;
2185         s32 ret_val = 0;
2186         u32 bank = 0;
2187         u16 i, word;
2188
2189         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2190             (words == 0)) {
2191                 e_dbg("nvm parameter(s) out of bounds\n");
2192                 ret_val = -E1000_ERR_NVM;
2193                 goto out;
2194         }
2195
2196         nvm->ops.acquire(hw);
2197
2198         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2199         if (ret_val) {
2200                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2201                 bank = 0;
2202         }
2203
2204         act_offset = (bank) ? nvm->flash_bank_size : 0;
2205         act_offset += offset;
2206
2207         ret_val = 0;
2208         for (i = 0; i < words; i++) {
2209                 if (dev_spec->shadow_ram[offset+i].modified) {
2210                         data[i] = dev_spec->shadow_ram[offset+i].value;
2211                 } else {
2212                         ret_val = e1000_read_flash_word_ich8lan(hw,
2213                                                                 act_offset + i,
2214                                                                 &word);
2215                         if (ret_val)
2216                                 break;
2217                         data[i] = word;
2218                 }
2219         }
2220
2221         nvm->ops.release(hw);
2222
2223 out:
2224         if (ret_val)
2225                 e_dbg("NVM read error: %d\n", ret_val);
2226
2227         return ret_val;
2228 }
2229
2230 /**
2231  *  e1000_flash_cycle_init_ich8lan - Initialize flash
2232  *  @hw: pointer to the HW structure
2233  *
2234  *  This function does initial flash setup so that a new read/write/erase cycle
2235  *  can be started.
2236  **/
2237 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2238 {
2239         union ich8_hws_flash_status hsfsts;
2240         s32 ret_val = -E1000_ERR_NVM;
2241
2242         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2243
2244         /* Check if the flash descriptor is valid */
2245         if (hsfsts.hsf_status.fldesvalid == 0) {
2246                 e_dbg("Flash descriptor invalid.  SW Sequencing must be used.\n");
2247                 return -E1000_ERR_NVM;
2248         }
2249
2250         /* Clear FCERR and DAEL in hw status by writing 1 */
2251         hsfsts.hsf_status.flcerr = 1;
2252         hsfsts.hsf_status.dael = 1;
2253
2254         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2255
2256         /*
2257          * Either we should have a hardware SPI cycle in progress
2258          * bit to check against, in order to start a new cycle or
2259          * FDONE bit should be changed in the hardware so that it
2260          * is 1 after hardware reset, which can then be used as an
2261          * indication whether a cycle is in progress or has been
2262          * completed.
2263          */
2264
2265         if (hsfsts.hsf_status.flcinprog == 0) {
2266                 /*
2267                  * There is no cycle running at present,
2268                  * so we can start a cycle.
2269                  * Begin by setting Flash Cycle Done.
2270                  */
2271                 hsfsts.hsf_status.flcdone = 1;
2272                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2273                 ret_val = 0;
2274         } else {
2275                 s32 i = 0;
2276
2277                 /*
2278                  * Otherwise poll for sometime so the current
2279                  * cycle has a chance to end before giving up.
2280                  */
2281                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2282                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2283                         if (hsfsts.hsf_status.flcinprog == 0) {
2284                                 ret_val = 0;
2285                                 break;
2286                         }
2287                         udelay(1);
2288                 }
2289                 if (ret_val == 0) {
2290                         /*
2291                          * Successful in waiting for previous cycle to timeout,
2292                          * now set the Flash Cycle Done.
2293                          */
2294                         hsfsts.hsf_status.flcdone = 1;
2295                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2296                 } else {
2297                         e_dbg("Flash controller busy, cannot get access\n");
2298                 }
2299         }
2300
2301         return ret_val;
2302 }
2303
2304 /**
2305  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2306  *  @hw: pointer to the HW structure
2307  *  @timeout: maximum time to wait for completion
2308  *
2309  *  This function starts a flash cycle and waits for its completion.
2310  **/
2311 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2312 {
2313         union ich8_hws_flash_ctrl hsflctl;
2314         union ich8_hws_flash_status hsfsts;
2315         s32 ret_val = -E1000_ERR_NVM;
2316         u32 i = 0;
2317
2318         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2319         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2320         hsflctl.hsf_ctrl.flcgo = 1;
2321         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2322
2323         /* wait till FDONE bit is set to 1 */
2324         do {
2325                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2326                 if (hsfsts.hsf_status.flcdone == 1)
2327                         break;
2328                 udelay(1);
2329         } while (i++ < timeout);
2330
2331         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2332                 return 0;
2333
2334         return ret_val;
2335 }
2336
2337 /**
2338  *  e1000_read_flash_word_ich8lan - Read word from flash
2339  *  @hw: pointer to the HW structure
2340  *  @offset: offset to data location
2341  *  @data: pointer to the location for storing the data
2342  *
2343  *  Reads the flash word at offset into data.  Offset is converted
2344  *  to bytes before read.
2345  **/
2346 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2347                                          u16 *data)
2348 {
2349         /* Must convert offset into bytes. */
2350         offset <<= 1;
2351
2352         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2353 }
2354
2355 /**
2356  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2357  *  @hw: pointer to the HW structure
2358  *  @offset: The offset of the byte to read.
2359  *  @data: Pointer to a byte to store the value read.
2360  *
2361  *  Reads a single byte from the NVM using the flash access registers.
2362  **/
2363 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2364                                          u8 *data)
2365 {
2366         s32 ret_val;
2367         u16 word = 0;
2368
2369         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2370         if (ret_val)
2371                 return ret_val;
2372
2373         *data = (u8)word;
2374
2375         return 0;
2376 }
2377
2378 /**
2379  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2380  *  @hw: pointer to the HW structure
2381  *  @offset: The offset (in bytes) of the byte or word to read.
2382  *  @size: Size of data to read, 1=byte 2=word
2383  *  @data: Pointer to the word to store the value read.
2384  *
2385  *  Reads a byte or word from the NVM using the flash access registers.
2386  **/
2387 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2388                                          u8 size, u16 *data)
2389 {
2390         union ich8_hws_flash_status hsfsts;
2391         union ich8_hws_flash_ctrl hsflctl;
2392         u32 flash_linear_addr;
2393         u32 flash_data = 0;
2394         s32 ret_val = -E1000_ERR_NVM;
2395         u8 count = 0;
2396
2397         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2398                 return -E1000_ERR_NVM;
2399
2400         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2401                             hw->nvm.flash_base_addr;
2402
2403         do {
2404                 udelay(1);
2405                 /* Steps */
2406                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2407                 if (ret_val != 0)
2408                         break;
2409
2410                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2411                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2412                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2413                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2414                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2415
2416                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2417
2418                 ret_val = e1000_flash_cycle_ich8lan(hw,
2419                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2420
2421                 /*
2422                  * Check if FCERR is set to 1, if set to 1, clear it
2423                  * and try the whole sequence a few more times, else
2424                  * read in (shift in) the Flash Data0, the order is
2425                  * least significant byte first msb to lsb
2426                  */
2427                 if (ret_val == 0) {
2428                         flash_data = er32flash(ICH_FLASH_FDATA0);
2429                         if (size == 1)
2430                                 *data = (u8)(flash_data & 0x000000FF);
2431                         else if (size == 2)
2432                                 *data = (u16)(flash_data & 0x0000FFFF);
2433                         break;
2434                 } else {
2435                         /*
2436                          * If we've gotten here, then things are probably
2437                          * completely hosed, but if the error condition is
2438                          * detected, it won't hurt to give it another try...
2439                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2440                          */
2441                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2442                         if (hsfsts.hsf_status.flcerr == 1) {
2443                                 /* Repeat for some time before giving up. */
2444                                 continue;
2445                         } else if (hsfsts.hsf_status.flcdone == 0) {
2446                                 e_dbg("Timeout error - flash cycle did not complete.\n");
2447                                 break;
2448                         }
2449                 }
2450         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2451
2452         return ret_val;
2453 }
2454
2455 /**
2456  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2457  *  @hw: pointer to the HW structure
2458  *  @offset: The offset (in bytes) of the word(s) to write.
2459  *  @words: Size of data to write in words
2460  *  @data: Pointer to the word(s) to write at offset.
2461  *
2462  *  Writes a byte or word to the NVM using the flash access registers.
2463  **/
2464 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2465                                    u16 *data)
2466 {
2467         struct e1000_nvm_info *nvm = &hw->nvm;
2468         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2469         u16 i;
2470
2471         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2472             (words == 0)) {
2473                 e_dbg("nvm parameter(s) out of bounds\n");
2474                 return -E1000_ERR_NVM;
2475         }
2476
2477         nvm->ops.acquire(hw);
2478
2479         for (i = 0; i < words; i++) {
2480                 dev_spec->shadow_ram[offset+i].modified = true;
2481                 dev_spec->shadow_ram[offset+i].value = data[i];
2482         }
2483
2484         nvm->ops.release(hw);
2485
2486         return 0;
2487 }
2488
2489 /**
2490  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2491  *  @hw: pointer to the HW structure
2492  *
2493  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2494  *  which writes the checksum to the shadow ram.  The changes in the shadow
2495  *  ram are then committed to the EEPROM by processing each bank at a time
2496  *  checking for the modified bit and writing only the pending changes.
2497  *  After a successful commit, the shadow ram is cleared and is ready for
2498  *  future writes.
2499  **/
2500 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2501 {
2502         struct e1000_nvm_info *nvm = &hw->nvm;
2503         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2504         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2505         s32 ret_val;
2506         u16 data;
2507
2508         ret_val = e1000e_update_nvm_checksum_generic(hw);
2509         if (ret_val)
2510                 goto out;
2511
2512         if (nvm->type != e1000_nvm_flash_sw)
2513                 goto out;
2514
2515         nvm->ops.acquire(hw);
2516
2517         /*
2518          * We're writing to the opposite bank so if we're on bank 1,
2519          * write to bank 0 etc.  We also need to erase the segment that
2520          * is going to be written
2521          */
2522         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2523         if (ret_val) {
2524                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2525                 bank = 0;
2526         }
2527
2528         if (bank == 0) {
2529                 new_bank_offset = nvm->flash_bank_size;
2530                 old_bank_offset = 0;
2531                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2532                 if (ret_val)
2533                         goto release;
2534         } else {
2535                 old_bank_offset = nvm->flash_bank_size;
2536                 new_bank_offset = 0;
2537                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2538                 if (ret_val)
2539                         goto release;
2540         }
2541
2542         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2543                 /*
2544                  * Determine whether to write the value stored
2545                  * in the other NVM bank or a modified value stored
2546                  * in the shadow RAM
2547                  */
2548                 if (dev_spec->shadow_ram[i].modified) {
2549                         data = dev_spec->shadow_ram[i].value;
2550                 } else {
2551                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2552                                                                 old_bank_offset,
2553                                                                 &data);
2554                         if (ret_val)
2555                                 break;
2556                 }
2557
2558                 /*
2559                  * If the word is 0x13, then make sure the signature bits
2560                  * (15:14) are 11b until the commit has completed.
2561                  * This will allow us to write 10b which indicates the
2562                  * signature is valid.  We want to do this after the write
2563                  * has completed so that we don't mark the segment valid
2564                  * while the write is still in progress
2565                  */
2566                 if (i == E1000_ICH_NVM_SIG_WORD)
2567                         data |= E1000_ICH_NVM_SIG_MASK;
2568
2569                 /* Convert offset to bytes. */
2570                 act_offset = (i + new_bank_offset) << 1;
2571
2572                 udelay(100);
2573                 /* Write the bytes to the new bank. */
2574                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2575                                                                act_offset,
2576                                                                (u8)data);
2577                 if (ret_val)
2578                         break;
2579
2580                 udelay(100);
2581                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2582                                                           act_offset + 1,
2583                                                           (u8)(data >> 8));
2584                 if (ret_val)
2585                         break;
2586         }
2587
2588         /*
2589          * Don't bother writing the segment valid bits if sector
2590          * programming failed.
2591          */
2592         if (ret_val) {
2593                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2594                 e_dbg("Flash commit failed.\n");
2595                 goto release;
2596         }
2597
2598         /*
2599          * Finally validate the new segment by setting bit 15:14
2600          * to 10b in word 0x13 , this can be done without an
2601          * erase as well since these bits are 11 to start with
2602          * and we need to change bit 14 to 0b
2603          */
2604         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2605         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2606         if (ret_val)
2607                 goto release;
2608
2609         data &= 0xBFFF;
2610         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2611                                                        act_offset * 2 + 1,
2612                                                        (u8)(data >> 8));
2613         if (ret_val)
2614                 goto release;
2615
2616         /*
2617          * And invalidate the previously valid segment by setting
2618          * its signature word (0x13) high_byte to 0b. This can be
2619          * done without an erase because flash erase sets all bits
2620          * to 1's. We can write 1's to 0's without an erase
2621          */
2622         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2623         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2624         if (ret_val)
2625                 goto release;
2626
2627         /* Great!  Everything worked, we can now clear the cached entries. */
2628         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2629                 dev_spec->shadow_ram[i].modified = false;
2630                 dev_spec->shadow_ram[i].value = 0xFFFF;
2631         }
2632
2633 release:
2634         nvm->ops.release(hw);
2635
2636         /*
2637          * Reload the EEPROM, or else modifications will not appear
2638          * until after the next adapter reset.
2639          */
2640         if (!ret_val) {
2641                 e1000e_reload_nvm(hw);
2642                 usleep_range(10000, 20000);
2643         }
2644
2645 out:
2646         if (ret_val)
2647                 e_dbg("NVM update error: %d\n", ret_val);
2648
2649         return ret_val;
2650 }
2651
2652 /**
2653  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2654  *  @hw: pointer to the HW structure
2655  *
2656  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2657  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2658  *  calculated, in which case we need to calculate the checksum and set bit 6.
2659  **/
2660 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2661 {
2662         s32 ret_val;
2663         u16 data;
2664
2665         /*
2666          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2667          * needs to be fixed.  This bit is an indication that the NVM
2668          * was prepared by OEM software and did not calculate the
2669          * checksum...a likely scenario.
2670          */
2671         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2672         if (ret_val)
2673                 return ret_val;
2674
2675         if ((data & 0x40) == 0) {
2676                 data |= 0x40;
2677                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2678                 if (ret_val)
2679                         return ret_val;
2680                 ret_val = e1000e_update_nvm_checksum(hw);
2681                 if (ret_val)
2682                         return ret_val;
2683         }
2684
2685         return e1000e_validate_nvm_checksum_generic(hw);
2686 }
2687
2688 /**
2689  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2690  *  @hw: pointer to the HW structure
2691  *
2692  *  To prevent malicious write/erase of the NVM, set it to be read-only
2693  *  so that the hardware ignores all write/erase cycles of the NVM via
2694  *  the flash control registers.  The shadow-ram copy of the NVM will
2695  *  still be updated, however any updates to this copy will not stick
2696  *  across driver reloads.
2697  **/
2698 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2699 {
2700         struct e1000_nvm_info *nvm = &hw->nvm;
2701         union ich8_flash_protected_range pr0;
2702         union ich8_hws_flash_status hsfsts;
2703         u32 gfpreg;
2704
2705         nvm->ops.acquire(hw);
2706
2707         gfpreg = er32flash(ICH_FLASH_GFPREG);
2708
2709         /* Write-protect GbE Sector of NVM */
2710         pr0.regval = er32flash(ICH_FLASH_PR0);
2711         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2712         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2713         pr0.range.wpe = true;
2714         ew32flash(ICH_FLASH_PR0, pr0.regval);
2715
2716         /*
2717          * Lock down a subset of GbE Flash Control Registers, e.g.
2718          * PR0 to prevent the write-protection from being lifted.
2719          * Once FLOCKDN is set, the registers protected by it cannot
2720          * be written until FLOCKDN is cleared by a hardware reset.
2721          */
2722         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2723         hsfsts.hsf_status.flockdn = true;
2724         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2725
2726         nvm->ops.release(hw);
2727 }
2728
2729 /**
2730  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2731  *  @hw: pointer to the HW structure
2732  *  @offset: The offset (in bytes) of the byte/word to read.
2733  *  @size: Size of data to read, 1=byte 2=word
2734  *  @data: The byte(s) to write to the NVM.
2735  *
2736  *  Writes one/two bytes to the NVM using the flash access registers.
2737  **/
2738 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2739                                           u8 size, u16 data)
2740 {
2741         union ich8_hws_flash_status hsfsts;
2742         union ich8_hws_flash_ctrl hsflctl;
2743         u32 flash_linear_addr;
2744         u32 flash_data = 0;
2745         s32 ret_val;
2746         u8 count = 0;
2747
2748         if (size < 1 || size > 2 || data > size * 0xff ||
2749             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2750                 return -E1000_ERR_NVM;
2751
2752         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2753                             hw->nvm.flash_base_addr;
2754
2755         do {
2756                 udelay(1);
2757                 /* Steps */
2758                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2759                 if (ret_val)
2760                         break;
2761
2762                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2763                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2764                 hsflctl.hsf_ctrl.fldbcount = size -1;
2765                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2766                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2767
2768                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2769
2770                 if (size == 1)
2771                         flash_data = (u32)data & 0x00FF;
2772                 else
2773                         flash_data = (u32)data;
2774
2775                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2776
2777                 /*
2778                  * check if FCERR is set to 1 , if set to 1, clear it
2779                  * and try the whole sequence a few more times else done
2780                  */
2781                 ret_val = e1000_flash_cycle_ich8lan(hw,
2782                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2783                 if (!ret_val)
2784                         break;
2785
2786                 /*
2787                  * If we're here, then things are most likely
2788                  * completely hosed, but if the error condition
2789                  * is detected, it won't hurt to give it another
2790                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2791                  */
2792                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2793                 if (hsfsts.hsf_status.flcerr == 1)
2794                         /* Repeat for some time before giving up. */
2795                         continue;
2796                 if (hsfsts.hsf_status.flcdone == 0) {
2797                         e_dbg("Timeout error - flash cycle did not complete.\n");
2798                         break;
2799                 }
2800         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2801
2802         return ret_val;
2803 }
2804
2805 /**
2806  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2807  *  @hw: pointer to the HW structure
2808  *  @offset: The index of the byte to read.
2809  *  @data: The byte to write to the NVM.
2810  *
2811  *  Writes a single byte to the NVM using the flash access registers.
2812  **/
2813 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2814                                           u8 data)
2815 {
2816         u16 word = (u16)data;
2817
2818         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2819 }
2820
2821 /**
2822  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2823  *  @hw: pointer to the HW structure
2824  *  @offset: The offset of the byte to write.
2825  *  @byte: The byte to write to the NVM.
2826  *
2827  *  Writes a single byte to the NVM using the flash access registers.
2828  *  Goes through a retry algorithm before giving up.
2829  **/
2830 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2831                                                 u32 offset, u8 byte)
2832 {
2833         s32 ret_val;
2834         u16 program_retries;
2835
2836         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2837         if (!ret_val)
2838                 return ret_val;
2839
2840         for (program_retries = 0; program_retries < 100; program_retries++) {
2841                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2842                 udelay(100);
2843                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2844                 if (!ret_val)
2845                         break;
2846         }
2847         if (program_retries == 100)
2848                 return -E1000_ERR_NVM;
2849
2850         return 0;
2851 }
2852
2853 /**
2854  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2855  *  @hw: pointer to the HW structure
2856  *  @bank: 0 for first bank, 1 for second bank, etc.
2857  *
2858  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2859  *  bank N is 4096 * N + flash_reg_addr.
2860  **/
2861 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2862 {
2863         struct e1000_nvm_info *nvm = &hw->nvm;
2864         union ich8_hws_flash_status hsfsts;
2865         union ich8_hws_flash_ctrl hsflctl;
2866         u32 flash_linear_addr;
2867         /* bank size is in 16bit words - adjust to bytes */
2868         u32 flash_bank_size = nvm->flash_bank_size * 2;
2869         s32 ret_val;
2870         s32 count = 0;
2871         s32 j, iteration, sector_size;
2872
2873         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2874
2875         /*
2876          * Determine HW Sector size: Read BERASE bits of hw flash status
2877          * register
2878          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2879          *     consecutive sectors.  The start index for the nth Hw sector
2880          *     can be calculated as = bank * 4096 + n * 256
2881          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2882          *     The start index for the nth Hw sector can be calculated
2883          *     as = bank * 4096
2884          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2885          *     (ich9 only, otherwise error condition)
2886          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2887          */
2888         switch (hsfsts.hsf_status.berasesz) {
2889         case 0:
2890                 /* Hw sector size 256 */
2891                 sector_size = ICH_FLASH_SEG_SIZE_256;
2892                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2893                 break;
2894         case 1:
2895                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2896                 iteration = 1;
2897                 break;
2898         case 2:
2899                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2900                 iteration = 1;
2901                 break;
2902         case 3:
2903                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2904                 iteration = 1;
2905                 break;
2906         default:
2907                 return -E1000_ERR_NVM;
2908         }
2909
2910         /* Start with the base address, then add the sector offset. */
2911         flash_linear_addr = hw->nvm.flash_base_addr;
2912         flash_linear_addr += (bank) ? flash_bank_size : 0;
2913
2914         for (j = 0; j < iteration ; j++) {
2915                 do {
2916                         /* Steps */
2917                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2918                         if (ret_val)
2919                                 return ret_val;
2920
2921                         /*
2922                          * Write a value 11 (block Erase) in Flash
2923                          * Cycle field in hw flash control
2924                          */
2925                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2926                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2927                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2928
2929                         /*
2930                          * Write the last 24 bits of an index within the
2931                          * block into Flash Linear address field in Flash
2932                          * Address.
2933                          */
2934                         flash_linear_addr += (j * sector_size);
2935                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2936
2937                         ret_val = e1000_flash_cycle_ich8lan(hw,
2938                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2939                         if (ret_val == 0)
2940                                 break;
2941
2942                         /*
2943                          * Check if FCERR is set to 1.  If 1,
2944                          * clear it and try the whole sequence
2945                          * a few more times else Done
2946                          */
2947                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2948                         if (hsfsts.hsf_status.flcerr == 1)
2949                                 /* repeat for some time before giving up */
2950                                 continue;
2951                         else if (hsfsts.hsf_status.flcdone == 0)
2952                                 return ret_val;
2953                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2954         }
2955
2956         return 0;
2957 }
2958
2959 /**
2960  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2961  *  @hw: pointer to the HW structure
2962  *  @data: Pointer to the LED settings
2963  *
2964  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2965  *  settings is all 0's or F's, set the LED default to a valid LED default
2966  *  setting.
2967  **/
2968 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2969 {
2970         s32 ret_val;
2971
2972         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2973         if (ret_val) {
2974                 e_dbg("NVM Read Error\n");
2975                 return ret_val;
2976         }
2977
2978         if (*data == ID_LED_RESERVED_0000 ||
2979             *data == ID_LED_RESERVED_FFFF)
2980                 *data = ID_LED_DEFAULT_ICH8LAN;
2981
2982         return 0;
2983 }
2984
2985 /**
2986  *  e1000_id_led_init_pchlan - store LED configurations
2987  *  @hw: pointer to the HW structure
2988  *
2989  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2990  *  the PHY LED configuration register.
2991  *
2992  *  PCH also does not have an "always on" or "always off" mode which
2993  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2994  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2995  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2996  *  link based on logic in e1000_led_[on|off]_pchlan().
2997  **/
2998 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2999 {
3000         struct e1000_mac_info *mac = &hw->mac;
3001         s32 ret_val;
3002         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
3003         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
3004         u16 data, i, temp, shift;
3005
3006         /* Get default ID LED modes */
3007         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
3008         if (ret_val)
3009                 goto out;
3010
3011         mac->ledctl_default = er32(LEDCTL);
3012         mac->ledctl_mode1 = mac->ledctl_default;
3013         mac->ledctl_mode2 = mac->ledctl_default;
3014
3015         for (i = 0; i < 4; i++) {
3016                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
3017                 shift = (i * 5);
3018                 switch (temp) {
3019                 case ID_LED_ON1_DEF2:
3020                 case ID_LED_ON1_ON2:
3021                 case ID_LED_ON1_OFF2:
3022                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3023                         mac->ledctl_mode1 |= (ledctl_on << shift);
3024                         break;
3025                 case ID_LED_OFF1_DEF2:
3026                 case ID_LED_OFF1_ON2:
3027                 case ID_LED_OFF1_OFF2:
3028                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
3029                         mac->ledctl_mode1 |= (ledctl_off << shift);
3030                         break;
3031                 default:
3032                         /* Do nothing */
3033                         break;
3034                 }
3035                 switch (temp) {
3036                 case ID_LED_DEF1_ON2:
3037                 case ID_LED_ON1_ON2:
3038                 case ID_LED_OFF1_ON2:
3039                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3040                         mac->ledctl_mode2 |= (ledctl_on << shift);
3041                         break;
3042                 case ID_LED_DEF1_OFF2:
3043                 case ID_LED_ON1_OFF2:
3044                 case ID_LED_OFF1_OFF2:
3045                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
3046                         mac->ledctl_mode2 |= (ledctl_off << shift);
3047                         break;
3048                 default:
3049                         /* Do nothing */
3050                         break;
3051                 }
3052         }
3053
3054 out:
3055         return ret_val;
3056 }
3057
3058 /**
3059  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
3060  *  @hw: pointer to the HW structure
3061  *
3062  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
3063  *  register, so the the bus width is hard coded.
3064  **/
3065 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
3066 {
3067         struct e1000_bus_info *bus = &hw->bus;
3068         s32 ret_val;
3069
3070         ret_val = e1000e_get_bus_info_pcie(hw);
3071
3072         /*
3073          * ICH devices are "PCI Express"-ish.  They have
3074          * a configuration space, but do not contain
3075          * PCI Express Capability registers, so bus width
3076          * must be hardcoded.
3077          */
3078         if (bus->width == e1000_bus_width_unknown)
3079                 bus->width = e1000_bus_width_pcie_x1;
3080
3081         return ret_val;
3082 }
3083
3084 /**
3085  *  e1000_reset_hw_ich8lan - Reset the hardware
3086  *  @hw: pointer to the HW structure
3087  *
3088  *  Does a full reset of the hardware which includes a reset of the PHY and
3089  *  MAC.
3090  **/
3091 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3092 {
3093         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3094         u16 reg;
3095         u32 ctrl, kab;
3096         s32 ret_val;
3097
3098         /*
3099          * Prevent the PCI-E bus from sticking if there is no TLP connection
3100          * on the last TLP read/write transaction when MAC is reset.
3101          */
3102         ret_val = e1000e_disable_pcie_master(hw);
3103         if (ret_val)
3104                 e_dbg("PCI-E Master disable polling has failed.\n");
3105
3106         e_dbg("Masking off all interrupts\n");
3107         ew32(IMC, 0xffffffff);
3108
3109         /*
3110          * Disable the Transmit and Receive units.  Then delay to allow
3111          * any pending transactions to complete before we hit the MAC
3112          * with the global reset.
3113          */
3114         ew32(RCTL, 0);
3115         ew32(TCTL, E1000_TCTL_PSP);
3116         e1e_flush();
3117
3118         usleep_range(10000, 20000);
3119
3120         /* Workaround for ICH8 bit corruption issue in FIFO memory */
3121         if (hw->mac.type == e1000_ich8lan) {
3122                 /* Set Tx and Rx buffer allocation to 8k apiece. */
3123                 ew32(PBA, E1000_PBA_8K);
3124                 /* Set Packet Buffer Size to 16k. */
3125                 ew32(PBS, E1000_PBS_16K);
3126         }
3127
3128         if (hw->mac.type == e1000_pchlan) {
3129                 /* Save the NVM K1 bit setting*/
3130                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
3131                 if (ret_val)
3132                         return ret_val;
3133
3134                 if (reg & E1000_NVM_K1_ENABLE)
3135                         dev_spec->nvm_k1_enabled = true;
3136                 else
3137                         dev_spec->nvm_k1_enabled = false;
3138         }
3139
3140         ctrl = er32(CTRL);
3141
3142         if (!e1000_check_reset_block(hw)) {
3143                 /*
3144                  * Full-chip reset requires MAC and PHY reset at the same
3145                  * time to make sure the interface between MAC and the
3146                  * external PHY is reset.
3147                  */
3148                 ctrl |= E1000_CTRL_PHY_RST;
3149
3150                 /*
3151                  * Gate automatic PHY configuration by hardware on
3152                  * non-managed 82579
3153                  */
3154                 if ((hw->mac.type == e1000_pch2lan) &&
3155                     !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3156                         e1000_gate_hw_phy_config_ich8lan(hw, true);
3157         }
3158         ret_val = e1000_acquire_swflag_ich8lan(hw);
3159         e_dbg("Issuing a global reset to ich8lan\n");
3160         ew32(CTRL, (ctrl | E1000_CTRL_RST));
3161         /* cannot issue a flush here because it hangs the hardware */
3162         msleep(20);
3163
3164         if (!ret_val)
3165                 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
3166
3167         if (ctrl & E1000_CTRL_PHY_RST) {
3168                 ret_val = hw->phy.ops.get_cfg_done(hw);
3169                 if (ret_val)
3170                         goto out;
3171
3172                 ret_val = e1000_post_phy_reset_ich8lan(hw);
3173                 if (ret_val)
3174                         goto out;
3175         }
3176
3177         /*
3178          * For PCH, this write will make sure that any noise
3179          * will be detected as a CRC error and be dropped rather than show up
3180          * as a bad packet to the DMA engine.
3181          */
3182         if (hw->mac.type == e1000_pchlan)
3183                 ew32(CRC_OFFSET, 0x65656565);
3184
3185         ew32(IMC, 0xffffffff);
3186         er32(ICR);
3187
3188         kab = er32(KABGTXD);
3189         kab |= E1000_KABGTXD_BGSQLBIAS;
3190         ew32(KABGTXD, kab);
3191
3192 out:
3193         return ret_val;
3194 }
3195
3196 /**
3197  *  e1000_init_hw_ich8lan - Initialize the hardware
3198  *  @hw: pointer to the HW structure
3199  *
3200  *  Prepares the hardware for transmit and receive by doing the following:
3201  *   - initialize hardware bits
3202  *   - initialize LED identification
3203  *   - setup receive address registers
3204  *   - setup flow control
3205  *   - setup transmit descriptors
3206  *   - clear statistics
3207  **/
3208 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3209 {
3210         struct e1000_mac_info *mac = &hw->mac;
3211         u32 ctrl_ext, txdctl, snoop;
3212         s32 ret_val;
3213         u16 i;
3214
3215         e1000_initialize_hw_bits_ich8lan(hw);
3216
3217         /* Initialize identification LED */
3218         ret_val = mac->ops.id_led_init(hw);
3219         if (ret_val)
3220                 e_dbg("Error initializing identification LED\n");
3221                 /* This is not fatal and we should not stop init due to this */
3222
3223         /* Setup the receive address. */
3224         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3225
3226         /* Zero out the Multicast HASH table */
3227         e_dbg("Zeroing the MTA\n");
3228         for (i = 0; i < mac->mta_reg_count; i++)
3229                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3230
3231         /*
3232          * The 82578 Rx buffer will stall if wakeup is enabled in host and
3233          * the ME.  Disable wakeup by clearing the host wakeup bit.
3234          * Reset the phy after disabling host wakeup to reset the Rx buffer.
3235          */
3236         if (hw->phy.type == e1000_phy_82578) {
3237                 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3238                 i &= ~BM_WUC_HOST_WU_BIT;
3239                 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3240                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3241                 if (ret_val)
3242                         return ret_val;
3243         }
3244
3245         /* Setup link and flow control */
3246         ret_val = e1000_setup_link_ich8lan(hw);
3247
3248         /* Set the transmit descriptor write-back policy for both queues */
3249         txdctl = er32(TXDCTL(0));
3250         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3251                  E1000_TXDCTL_FULL_TX_DESC_WB;
3252         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3253                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3254         ew32(TXDCTL(0), txdctl);
3255         txdctl = er32(TXDCTL(1));
3256         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3257                  E1000_TXDCTL_FULL_TX_DESC_WB;
3258         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3259                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3260         ew32(TXDCTL(1), txdctl);
3261
3262         /*
3263          * ICH8 has opposite polarity of no_snoop bits.
3264          * By default, we should use snoop behavior.
3265          */
3266         if (mac->type == e1000_ich8lan)
3267                 snoop = PCIE_ICH8_SNOOP_ALL;
3268         else
3269                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3270         e1000e_set_pcie_no_snoop(hw, snoop);
3271
3272         ctrl_ext = er32(CTRL_EXT);
3273         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3274         ew32(CTRL_EXT, ctrl_ext);
3275
3276         /*
3277          * Clear all of the statistics registers (clear on read).  It is
3278          * important that we do this after we have tried to establish link
3279          * because the symbol error count will increment wildly if there
3280          * is no link.
3281          */
3282         e1000_clear_hw_cntrs_ich8lan(hw);
3283
3284         return 0;
3285 }
3286 /**
3287  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3288  *  @hw: pointer to the HW structure
3289  *
3290  *  Sets/Clears required hardware bits necessary for correctly setting up the
3291  *  hardware for transmit and receive.
3292  **/
3293 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3294 {
3295         u32 reg;
3296
3297         /* Extended Device Control */
3298         reg = er32(CTRL_EXT);
3299         reg |= (1 << 22);
3300         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3301         if (hw->mac.type >= e1000_pchlan)
3302                 reg |= E1000_CTRL_EXT_PHYPDEN;
3303         ew32(CTRL_EXT, reg);
3304
3305         /* Transmit Descriptor Control 0 */
3306         reg = er32(TXDCTL(0));
3307         reg |= (1 << 22);
3308         ew32(TXDCTL(0), reg);
3309
3310         /* Transmit Descriptor Control 1 */
3311         reg = er32(TXDCTL(1));
3312         reg |= (1 << 22);
3313         ew32(TXDCTL(1), reg);
3314
3315         /* Transmit Arbitration Control 0 */
3316         reg = er32(TARC(0));
3317         if (hw->mac.type == e1000_ich8lan)
3318                 reg |= (1 << 28) | (1 << 29);
3319         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3320         ew32(TARC(0), reg);
3321
3322         /* Transmit Arbitration Control 1 */
3323         reg = er32(TARC(1));
3324         if (er32(TCTL) & E1000_TCTL_MULR)
3325                 reg &= ~(1 << 28);
3326         else
3327                 reg |= (1 << 28);
3328         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3329         ew32(TARC(1), reg);
3330
3331         /* Device Status */
3332         if (hw->mac.type == e1000_ich8lan) {
3333                 reg = er32(STATUS);
3334                 reg &= ~(1 << 31);
3335                 ew32(STATUS, reg);
3336         }
3337
3338         /*
3339          * work-around descriptor data corruption issue during nfs v2 udp
3340          * traffic, just disable the nfs filtering capability
3341          */
3342         reg = er32(RFCTL);
3343         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3344         ew32(RFCTL, reg);
3345 }
3346
3347 /**
3348  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3349  *  @hw: pointer to the HW structure
3350  *
3351  *  Determines which flow control settings to use, then configures flow
3352  *  control.  Calls the appropriate media-specific link configuration
3353  *  function.  Assuming the adapter has a valid link partner, a valid link
3354  *  should be established.  Assumes the hardware has previously been reset
3355  *  and the transmitter and receiver are not enabled.
3356  **/
3357 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3358 {
3359         s32 ret_val;
3360
3361         if (e1000_check_reset_block(hw))
3362                 return 0;
3363
3364         /*
3365          * ICH parts do not have a word in the NVM to determine
3366          * the default flow control setting, so we explicitly
3367          * set it to full.
3368          */
3369         if (hw->fc.requested_mode == e1000_fc_default) {
3370                 /* Workaround h/w hang when Tx flow control enabled */
3371                 if (hw->mac.type == e1000_pchlan)
3372                         hw->fc.requested_mode = e1000_fc_rx_pause;
3373                 else
3374                         hw->fc.requested_mode = e1000_fc_full;
3375         }
3376
3377         /*
3378          * Save off the requested flow control mode for use later.  Depending
3379          * on the link partner's capabilities, we may or may not use this mode.
3380          */
3381         hw->fc.current_mode = hw->fc.requested_mode;
3382
3383         e_dbg("After fix-ups FlowControl is now = %x\n",
3384                 hw->fc.current_mode);
3385
3386         /* Continue to configure the copper link. */
3387         ret_val = e1000_setup_copper_link_ich8lan(hw);
3388         if (ret_val)
3389                 return ret_val;
3390
3391         ew32(FCTTV, hw->fc.pause_time);
3392         if ((hw->phy.type == e1000_phy_82578) ||
3393             (hw->phy.type == e1000_phy_82579) ||
3394             (hw->phy.type == e1000_phy_82577)) {
3395                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3396
3397                 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3398                                    hw->fc.pause_time);
3399                 if (ret_val)
3400                         return ret_val;
3401         }
3402
3403         return e1000e_set_fc_watermarks(hw);
3404 }
3405
3406 /**
3407  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3408  *  @hw: pointer to the HW structure
3409  *
3410  *  Configures the kumeran interface to the PHY to wait the appropriate time
3411  *  when polling the PHY, then call the generic setup_copper_link to finish
3412  *  configuring the copper link.
3413  **/
3414 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3415 {
3416         u32 ctrl;
3417         s32 ret_val;
3418         u16 reg_data;
3419
3420         ctrl = er32(CTRL);
3421         ctrl |= E1000_CTRL_SLU;
3422         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3423         ew32(CTRL, ctrl);
3424
3425         /*
3426          * Set the mac to wait the maximum time between each iteration
3427          * and increase the max iterations when polling the phy;
3428          * this fixes erroneous timeouts at 10Mbps.
3429          */
3430         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3431         if (ret_val)
3432                 return ret_val;
3433         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3434                                        &reg_data);
3435         if (ret_val)
3436                 return ret_val;
3437         reg_data |= 0x3F;
3438         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3439                                         reg_data);
3440         if (ret_val)
3441                 return ret_val;
3442
3443         switch (hw->phy.type) {
3444         case e1000_phy_igp_3:
3445                 ret_val = e1000e_copper_link_setup_igp(hw);
3446                 if (ret_val)
3447                         return ret_val;
3448                 break;
3449         case e1000_phy_bm:
3450         case e1000_phy_82578:
3451                 ret_val = e1000e_copper_link_setup_m88(hw);
3452                 if (ret_val)
3453                         return ret_val;
3454                 break;
3455         case e1000_phy_82577:
3456         case e1000_phy_82579:
3457                 ret_val = e1000_copper_link_setup_82577(hw);
3458                 if (ret_val)
3459                         return ret_val;
3460                 break;
3461         case e1000_phy_ife:
3462                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
3463                 if (ret_val)
3464                         return ret_val;
3465
3466                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3467
3468                 switch (hw->phy.mdix) {
3469                 case 1:
3470                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3471                         break;
3472                 case 2:
3473                         reg_data |= IFE_PMC_FORCE_MDIX;
3474                         break;
3475                 case 0:
3476                 default:
3477                         reg_data |= IFE_PMC_AUTO_MDIX;
3478                         break;
3479                 }
3480                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3481                 if (ret_val)
3482                         return ret_val;
3483                 break;
3484         default:
3485                 break;
3486         }
3487         return e1000e_setup_copper_link(hw);
3488 }
3489
3490 /**
3491  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3492  *  @hw: pointer to the HW structure
3493  *  @speed: pointer to store current link speed
3494  *  @duplex: pointer to store the current link duplex
3495  *
3496  *  Calls the generic get_speed_and_duplex to retrieve the current link
3497  *  information and then calls the Kumeran lock loss workaround for links at
3498  *  gigabit speeds.
3499  **/
3500 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3501                                           u16 *duplex)
3502 {
3503         s32 ret_val;
3504
3505         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3506         if (ret_val)
3507                 return ret_val;
3508
3509         if ((hw->mac.type == e1000_ich8lan) &&
3510             (hw->phy.type == e1000_phy_igp_3) &&
3511             (*speed == SPEED_1000)) {
3512                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3513         }
3514
3515         return ret_val;
3516 }
3517
3518 /**
3519  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3520  *  @hw: pointer to the HW structure
3521  *
3522  *  Work-around for 82566 Kumeran PCS lock loss:
3523  *  On link status change (i.e. PCI reset, speed change) and link is up and
3524  *  speed is gigabit-
3525  *    0) if workaround is optionally disabled do nothing
3526  *    1) wait 1ms for Kumeran link to come up
3527  *    2) check Kumeran Diagnostic register PCS lock loss bit
3528  *    3) if not set the link is locked (all is good), otherwise...
3529  *    4) reset the PHY
3530  *    5) repeat up to 10 times
3531  *  Note: this is only called for IGP3 copper when speed is 1gb.
3532  **/
3533 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3534 {
3535         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3536         u32 phy_ctrl;
3537         s32 ret_val;
3538         u16 i, data;
3539         bool link;
3540
3541         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3542                 return 0;
3543
3544         /*
3545          * Make sure link is up before proceeding.  If not just return.
3546          * Attempting this while link is negotiating fouled up link
3547          * stability
3548          */
3549         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3550         if (!link)
3551                 return 0;
3552
3553         for (i = 0; i < 10; i++) {
3554                 /* read once to clear */
3555                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3556                 if (ret_val)
3557                         return ret_val;
3558                 /* and again to get new status */
3559                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3560                 if (ret_val)
3561                         return ret_val;
3562
3563                 /* check for PCS lock */
3564                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3565                         return 0;
3566
3567                 /* Issue PHY reset */
3568                 e1000_phy_hw_reset(hw);
3569                 mdelay(5);
3570         }
3571         /* Disable GigE link negotiation */
3572         phy_ctrl = er32(PHY_CTRL);
3573         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3574                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3575         ew32(PHY_CTRL, phy_ctrl);
3576
3577         /*
3578          * Call gig speed drop workaround on Gig disable before accessing
3579          * any PHY registers
3580          */
3581         e1000e_gig_downshift_workaround_ich8lan(hw);
3582
3583         /* unable to acquire PCS lock */
3584         return -E1000_ERR_PHY;
3585 }
3586
3587 /**
3588  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3589  *  @hw: pointer to the HW structure
3590  *  @state: boolean value used to set the current Kumeran workaround state
3591  *
3592  *  If ICH8, set the current Kumeran workaround state (enabled - true
3593  *  /disabled - false).
3594  **/
3595 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3596                                                  bool state)
3597 {
3598         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3599
3600         if (hw->mac.type != e1000_ich8lan) {
3601                 e_dbg("Workaround applies to ICH8 only.\n");
3602                 return;
3603         }
3604
3605         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3606 }
3607
3608 /**
3609  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3610  *  @hw: pointer to the HW structure
3611  *
3612  *  Workaround for 82566 power-down on D3 entry:
3613  *    1) disable gigabit link
3614  *    2) write VR power-down enable
3615  *    3) read it back
3616  *  Continue if successful, else issue LCD reset and repeat
3617  **/
3618 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3619 {
3620         u32 reg;
3621         u16 data;
3622         u8  retry = 0;
3623
3624         if (hw->phy.type != e1000_phy_igp_3)
3625                 return;
3626
3627         /* Try the workaround twice (if needed) */
3628         do {
3629                 /* Disable link */
3630                 reg = er32(PHY_CTRL);
3631                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3632                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3633                 ew32(PHY_CTRL, reg);
3634
3635                 /*
3636                  * Call gig speed drop workaround on Gig disable before
3637                  * accessing any PHY registers
3638                  */
3639                 if (hw->mac.type == e1000_ich8lan)
3640                         e1000e_gig_downshift_workaround_ich8lan(hw);
3641
3642                 /* Write VR power-down enable */
3643                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3644                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3645                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3646
3647                 /* Read it back and test */
3648                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3649                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3650                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3651                         break;
3652
3653                 /* Issue PHY reset and repeat at most one more time */
3654                 reg = er32(CTRL);
3655                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3656                 retry++;
3657         } while (retry);
3658 }
3659
3660 /**
3661  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3662  *  @hw: pointer to the HW structure
3663  *
3664  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3665  *  LPLU, Gig disable, MDIC PHY reset):
3666  *    1) Set Kumeran Near-end loopback
3667  *    2) Clear Kumeran Near-end loopback
3668  *  Should only be called for ICH8[m] devices with any 1G Phy.
3669  **/
3670 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3671 {
3672         s32 ret_val;
3673         u16 reg_data;
3674
3675         if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
3676                 return;
3677
3678         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3679                                       &reg_data);
3680         if (ret_val)
3681                 return;
3682         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3683         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3684                                        reg_data);
3685         if (ret_val)
3686                 return;
3687         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3688         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3689                                        reg_data);
3690 }
3691
3692 /**
3693  *  e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3694  *  @hw: pointer to the HW structure
3695  *
3696  *  During S0 to Sx transition, it is possible the link remains at gig
3697  *  instead of negotiating to a lower speed.  Before going to Sx, set
3698  *  'Gig Disable' to force link speed negotiation to a lower speed based on
3699  *  the LPLU setting in the NVM or custom setting.  For PCH and newer parts,
3700  *  the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
3701  *  needs to be written.
3702  **/
3703 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3704 {
3705         u32 phy_ctrl;
3706         s32 ret_val;
3707
3708         phy_ctrl = er32(PHY_CTRL);
3709         phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
3710         ew32(PHY_CTRL, phy_ctrl);
3711
3712         if (hw->mac.type == e1000_ich8lan)
3713                 e1000e_gig_downshift_workaround_ich8lan(hw);
3714
3715         if (hw->mac.type >= e1000_pchlan) {
3716                 e1000_oem_bits_config_ich8lan(hw, false);
3717                 e1000_phy_hw_reset_ich8lan(hw);
3718                 ret_val = hw->phy.ops.acquire(hw);
3719                 if (ret_val)
3720                         return;
3721                 e1000_write_smbus_addr(hw);
3722                 hw->phy.ops.release(hw);
3723         }
3724 }
3725
3726 /**
3727  *  e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3728  *  @hw: pointer to the HW structure
3729  *
3730  *  During Sx to S0 transitions on non-managed devices or managed devices
3731  *  on which PHY resets are not blocked, if the PHY registers cannot be
3732  *  accessed properly by the s/w toggle the LANPHYPC value to power cycle
3733  *  the PHY.
3734  **/
3735 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3736 {
3737         u16 phy_id1, phy_id2;
3738         s32 ret_val;
3739
3740         if ((hw->mac.type != e1000_pch2lan) || e1000_check_reset_block(hw))
3741                 return;
3742
3743         ret_val = hw->phy.ops.acquire(hw);
3744         if (ret_val) {
3745                 e_dbg("Failed to acquire PHY semaphore in resume\n");
3746                 return;
3747         }
3748
3749         /* Test access to the PHY registers by reading the ID regs */
3750         ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3751         if (ret_val)
3752                 goto release;
3753         ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3754         if (ret_val)
3755                 goto release;
3756
3757         if (hw->phy.id == ((u32)(phy_id1 << 16) |
3758                            (u32)(phy_id2 & PHY_REVISION_MASK)))
3759                 goto release;
3760
3761         e1000_toggle_lanphypc_value_ich8lan(hw);
3762
3763         hw->phy.ops.release(hw);
3764         msleep(50);
3765         e1000_phy_hw_reset(hw);
3766         msleep(50);
3767         return;
3768
3769 release:
3770         hw->phy.ops.release(hw);
3771
3772         return;
3773 }
3774
3775 /**
3776  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3777  *  @hw: pointer to the HW structure
3778  *
3779  *  Return the LED back to the default configuration.
3780  **/
3781 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3782 {
3783         if (hw->phy.type == e1000_phy_ife)
3784                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3785
3786         ew32(LEDCTL, hw->mac.ledctl_default);
3787         return 0;
3788 }
3789
3790 /**
3791  *  e1000_led_on_ich8lan - Turn LEDs on
3792  *  @hw: pointer to the HW structure
3793  *
3794  *  Turn on the LEDs.
3795  **/
3796 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3797 {
3798         if (hw->phy.type == e1000_phy_ife)
3799                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3800                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3801
3802         ew32(LEDCTL, hw->mac.ledctl_mode2);
3803         return 0;
3804 }
3805
3806 /**
3807  *  e1000_led_off_ich8lan - Turn LEDs off
3808  *  @hw: pointer to the HW structure
3809  *
3810  *  Turn off the LEDs.
3811  **/
3812 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3813 {
3814         if (hw->phy.type == e1000_phy_ife)
3815                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3816                                 (IFE_PSCL_PROBE_MODE |
3817                                  IFE_PSCL_PROBE_LEDS_OFF));
3818
3819         ew32(LEDCTL, hw->mac.ledctl_mode1);
3820         return 0;
3821 }
3822
3823 /**
3824  *  e1000_setup_led_pchlan - Configures SW controllable LED
3825  *  @hw: pointer to the HW structure
3826  *
3827  *  This prepares the SW controllable LED for use.
3828  **/
3829 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3830 {
3831         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3832 }
3833
3834 /**
3835  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3836  *  @hw: pointer to the HW structure
3837  *
3838  *  Return the LED back to the default configuration.
3839  **/
3840 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3841 {
3842         return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3843 }
3844
3845 /**
3846  *  e1000_led_on_pchlan - Turn LEDs on
3847  *  @hw: pointer to the HW structure
3848  *
3849  *  Turn on the LEDs.
3850  **/
3851 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3852 {
3853         u16 data = (u16)hw->mac.ledctl_mode2;
3854         u32 i, led;
3855
3856         /*
3857          * If no link, then turn LED on by setting the invert bit
3858          * for each LED that's mode is "link_up" in ledctl_mode2.
3859          */
3860         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3861                 for (i = 0; i < 3; i++) {
3862                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3863                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3864                             E1000_LEDCTL_MODE_LINK_UP)
3865                                 continue;
3866                         if (led & E1000_PHY_LED0_IVRT)
3867                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3868                         else
3869                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3870                 }
3871         }
3872
3873         return e1e_wphy(hw, HV_LED_CONFIG, data);
3874 }
3875
3876 /**
3877  *  e1000_led_off_pchlan - Turn LEDs off
3878  *  @hw: pointer to the HW structure
3879  *
3880  *  Turn off the LEDs.
3881  **/
3882 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3883 {
3884         u16 data = (u16)hw->mac.ledctl_mode1;
3885         u32 i, led;
3886
3887         /*
3888          * If no link, then turn LED off by clearing the invert bit
3889          * for each LED that's mode is "link_up" in ledctl_mode1.
3890          */
3891         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3892                 for (i = 0; i < 3; i++) {
3893                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3894                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3895                             E1000_LEDCTL_MODE_LINK_UP)
3896                                 continue;
3897                         if (led & E1000_PHY_LED0_IVRT)
3898                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3899                         else
3900                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3901                 }
3902         }
3903
3904         return e1e_wphy(hw, HV_LED_CONFIG, data);
3905 }
3906
3907 /**
3908  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3909  *  @hw: pointer to the HW structure
3910  *
3911  *  Read appropriate register for the config done bit for completion status
3912  *  and configure the PHY through s/w for EEPROM-less parts.
3913  *
3914  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3915  *  config done bit, so only an error is logged and continues.  If we were
3916  *  to return with error, EEPROM-less silicon would not be able to be reset
3917  *  or change link.
3918  **/
3919 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3920 {
3921         s32 ret_val = 0;
3922         u32 bank = 0;
3923         u32 status;
3924
3925         e1000e_get_cfg_done(hw);
3926
3927         /* Wait for indication from h/w that it has completed basic config */
3928         if (hw->mac.type >= e1000_ich10lan) {
3929                 e1000_lan_init_done_ich8lan(hw);
3930         } else {
3931                 ret_val = e1000e_get_auto_rd_done(hw);
3932                 if (ret_val) {
3933                         /*
3934                          * When auto config read does not complete, do not
3935                          * return with an error. This can happen in situations
3936                          * where there is no eeprom and prevents getting link.
3937                          */
3938                         e_dbg("Auto Read Done did not complete\n");
3939                         ret_val = 0;
3940                 }
3941         }
3942
3943         /* Clear PHY Reset Asserted bit */
3944         status = er32(STATUS);
3945         if (status & E1000_STATUS_PHYRA)
3946                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3947         else
3948                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3949
3950         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3951         if (hw->mac.type <= e1000_ich9lan) {
3952                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3953                     (hw->phy.type == e1000_phy_igp_3)) {
3954                         e1000e_phy_init_script_igp3(hw);
3955                 }
3956         } else {
3957                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3958                         /* Maybe we should do a basic PHY config */
3959                         e_dbg("EEPROM not present\n");
3960                         ret_val = -E1000_ERR_CONFIG;
3961                 }
3962         }
3963
3964         return ret_val;
3965 }
3966
3967 /**
3968  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3969  * @hw: pointer to the HW structure
3970  *
3971  * In the case of a PHY power down to save power, or to turn off link during a
3972  * driver unload, or wake on lan is not enabled, remove the link.
3973  **/
3974 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3975 {
3976         /* If the management interface is not enabled, then power down */
3977         if (!(hw->mac.ops.check_mng_mode(hw) ||
3978               hw->phy.ops.check_reset_block(hw)))
3979                 e1000_power_down_phy_copper(hw);
3980 }
3981
3982 /**
3983  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3984  *  @hw: pointer to the HW structure
3985  *
3986  *  Clears hardware counters specific to the silicon family and calls
3987  *  clear_hw_cntrs_generic to clear all general purpose counters.
3988  **/
3989 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3990 {
3991         u16 phy_data;
3992         s32 ret_val;
3993
3994         e1000e_clear_hw_cntrs_base(hw);
3995
3996         er32(ALGNERRC);
3997         er32(RXERRC);
3998         er32(TNCRS);
3999         er32(CEXTERR);
4000         er32(TSCTC);
4001         er32(TSCTFC);
4002
4003         er32(MGTPRC);
4004         er32(MGTPDC);
4005         er32(MGTPTC);
4006
4007         er32(IAC);
4008         er32(ICRXOC);
4009
4010         /* Clear PHY statistics registers */
4011         if ((hw->phy.type == e1000_phy_82578) ||
4012             (hw->phy.type == e1000_phy_82579) ||
4013             (hw->phy.type == e1000_phy_82577)) {
4014                 ret_val = hw->phy.ops.acquire(hw);
4015                 if (ret_val)
4016                         return;
4017                 ret_val = hw->phy.ops.set_page(hw,
4018                                                HV_STATS_PAGE << IGP_PAGE_SHIFT);
4019                 if (ret_val)
4020                         goto release;
4021                 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4022                 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4023                 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4024                 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4025                 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4026                 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4027                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4028                 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4029                 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4030                 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4031                 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4032                 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4033                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4034                 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4035 release:
4036                 hw->phy.ops.release(hw);
4037         }
4038 }
4039
4040 static const struct e1000_mac_operations ich8_mac_ops = {
4041         .id_led_init            = e1000e_id_led_init,
4042         /* check_mng_mode dependent on mac type */
4043         .check_for_link         = e1000_check_for_copper_link_ich8lan,
4044         /* cleanup_led dependent on mac type */
4045         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
4046         .get_bus_info           = e1000_get_bus_info_ich8lan,
4047         .set_lan_id             = e1000_set_lan_id_single_port,
4048         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
4049         /* led_on dependent on mac type */
4050         /* led_off dependent on mac type */
4051         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
4052         .reset_hw               = e1000_reset_hw_ich8lan,
4053         .init_hw                = e1000_init_hw_ich8lan,
4054         .setup_link             = e1000_setup_link_ich8lan,
4055         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
4056         /* id_led_init dependent on mac type */
4057 };
4058
4059 static const struct e1000_phy_operations ich8_phy_ops = {
4060         .acquire                = e1000_acquire_swflag_ich8lan,
4061         .check_reset_block      = e1000_check_reset_block_ich8lan,
4062         .commit                 = NULL,
4063         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
4064         .get_cable_length       = e1000e_get_cable_length_igp_2,
4065         .read_reg               = e1000e_read_phy_reg_igp,
4066         .release                = e1000_release_swflag_ich8lan,
4067         .reset                  = e1000_phy_hw_reset_ich8lan,
4068         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
4069         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
4070         .write_reg              = e1000e_write_phy_reg_igp,
4071 };
4072
4073 static const struct e1000_nvm_operations ich8_nvm_ops = {
4074         .acquire                = e1000_acquire_nvm_ich8lan,
4075         .read                   = e1000_read_nvm_ich8lan,
4076         .release                = e1000_release_nvm_ich8lan,
4077         .update                 = e1000_update_nvm_checksum_ich8lan,
4078         .valid_led_default      = e1000_valid_led_default_ich8lan,
4079         .validate               = e1000_validate_nvm_checksum_ich8lan,
4080         .write                  = e1000_write_nvm_ich8lan,
4081 };
4082
4083 const struct e1000_info e1000_ich8_info = {
4084         .mac                    = e1000_ich8lan,
4085         .flags                  = FLAG_HAS_WOL
4086                                   | FLAG_IS_ICH
4087                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4088                                   | FLAG_HAS_AMT
4089                                   | FLAG_HAS_FLASH
4090                                   | FLAG_APME_IN_WUC,
4091         .pba                    = 8,
4092         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
4093         .get_variants           = e1000_get_variants_ich8lan,
4094         .mac_ops                = &ich8_mac_ops,
4095         .phy_ops                = &ich8_phy_ops,
4096         .nvm_ops                = &ich8_nvm_ops,
4097 };
4098
4099 const struct e1000_info e1000_ich9_info = {
4100         .mac                    = e1000_ich9lan,
4101         .flags                  = FLAG_HAS_JUMBO_FRAMES
4102                                   | FLAG_IS_ICH
4103                                   | FLAG_HAS_WOL
4104                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4105                                   | FLAG_HAS_AMT
4106                                   | FLAG_HAS_FLASH
4107                                   | FLAG_APME_IN_WUC,
4108         .pba                    = 18,
4109         .max_hw_frame_size      = DEFAULT_JUMBO,
4110         .get_variants           = e1000_get_variants_ich8lan,
4111         .mac_ops                = &ich8_mac_ops,
4112         .phy_ops                = &ich8_phy_ops,
4113         .nvm_ops                = &ich8_nvm_ops,
4114 };
4115
4116 const struct e1000_info e1000_ich10_info = {
4117         .mac                    = e1000_ich10lan,
4118         .flags                  = FLAG_HAS_JUMBO_FRAMES
4119                                   | FLAG_IS_ICH
4120                                   | FLAG_HAS_WOL
4121                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4122                                   | FLAG_HAS_AMT
4123                                   | FLAG_HAS_FLASH
4124                                   | FLAG_APME_IN_WUC,
4125         .pba                    = 18,
4126         .max_hw_frame_size      = DEFAULT_JUMBO,
4127         .get_variants           = e1000_get_variants_ich8lan,
4128         .mac_ops                = &ich8_mac_ops,
4129         .phy_ops                = &ich8_phy_ops,
4130         .nvm_ops                = &ich8_nvm_ops,
4131 };
4132
4133 const struct e1000_info e1000_pch_info = {
4134         .mac                    = e1000_pchlan,
4135         .flags                  = FLAG_IS_ICH
4136                                   | FLAG_HAS_WOL
4137                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4138                                   | FLAG_HAS_AMT
4139                                   | FLAG_HAS_FLASH
4140                                   | FLAG_HAS_JUMBO_FRAMES
4141                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4142                                   | FLAG_APME_IN_WUC,
4143         .flags2                 = FLAG2_HAS_PHY_STATS,
4144         .pba                    = 26,
4145         .max_hw_frame_size      = 4096,
4146         .get_variants           = e1000_get_variants_ich8lan,
4147         .mac_ops                = &ich8_mac_ops,
4148         .phy_ops                = &ich8_phy_ops,
4149         .nvm_ops                = &ich8_nvm_ops,
4150 };
4151
4152 const struct e1000_info e1000_pch2_info = {
4153         .mac                    = e1000_pch2lan,
4154         .flags                  = FLAG_IS_ICH
4155                                   | FLAG_HAS_WOL
4156                                   | FLAG_HAS_CTRLEXT_ON_LOAD
4157                                   | FLAG_HAS_AMT
4158                                   | FLAG_HAS_FLASH
4159                                   | FLAG_HAS_JUMBO_FRAMES
4160                                   | FLAG_APME_IN_WUC,
4161         .flags2                 = FLAG2_HAS_PHY_STATS
4162                                   | FLAG2_HAS_EEE,
4163         .pba                    = 26,
4164         .max_hw_frame_size      = DEFAULT_JUMBO,
4165         .get_variants           = e1000_get_variants_ich8lan,
4166         .mac_ops                = &ich8_mac_ops,
4167         .phy_ops                = &ich8_phy_ops,
4168         .nvm_ops                = &ich8_nvm_ops,
4169 };