1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
30 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
35 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
36 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
37 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10
38 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F
40 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
42 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
44 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
45 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000
46 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000
48 #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C
49 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004
51 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
52 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000
54 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
55 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9
57 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
58 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disab. */
59 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
60 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
61 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
62 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
64 /* PHY Specific Control Register 2 (Page 0, Register 26) */
65 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000
66 /* 1=Reverse Auto-Negotiation */
68 /* MAC Specific Control Register (Page 2, Register 21) */
69 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
70 #define GG82563_MSCR_TX_CLK_MASK 0x0007
71 #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
72 #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
73 #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007
75 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */
77 /* DSP Distance Register (Page 5, Register 26) */
78 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M
85 /* Kumeran Mode Control Register (Page 193, Register 16) */
86 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800
88 /* Max number of times Kumeran read/write should be validated */
89 #define GG82563_MAX_KMRN_RETRY 0x5
91 /* Power Management Control Register (Page 193, Register 20) */
92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001
93 /* 1=Enable SERDES Electrical Idle */
95 /* In-Band Control Register (Page 194, Register 18) */
96 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */
98 /* A table for the GG82563 cable length where the range is defined
99 * with a lower bound at "index" and the upper bound at
102 static const u16 e1000_gg82563_cable_length_table[] = {
103 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
104 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
105 ARRAY_SIZE(e1000_gg82563_cable_length_table)
107 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
108 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
109 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
110 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
111 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
112 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
113 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
114 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
116 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
118 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
121 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
122 * @hw: pointer to the HW structure
124 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
126 struct e1000_phy_info *phy = &hw->phy;
129 if (hw->phy.media_type != e1000_media_type_copper) {
130 phy->type = e1000_phy_none;
133 phy->ops.power_up = e1000_power_up_phy_copper;
134 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
138 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
139 phy->reset_delay_us = 100;
140 phy->type = e1000_phy_gg82563;
142 /* This can only be done after all function pointers are setup. */
143 ret_val = e1000e_get_phy_id(hw);
146 if (phy->id != GG82563_E_PHY_ID)
147 return -E1000_ERR_PHY;
153 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
154 * @hw: pointer to the HW structure
156 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
158 struct e1000_nvm_info *nvm = &hw->nvm;
159 u32 eecd = er32(EECD);
162 nvm->opcode_bits = 8;
164 switch (nvm->override) {
165 case e1000_nvm_override_spi_large:
167 nvm->address_bits = 16;
169 case e1000_nvm_override_spi_small:
171 nvm->address_bits = 8;
174 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
175 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
179 nvm->type = e1000_nvm_eeprom_spi;
181 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
182 E1000_EECD_SIZE_EX_SHIFT);
184 /* Added to a constant, "size" becomes the left-shift value
185 * for setting word_size.
187 size += NVM_WORD_SIZE_BASE_SHIFT;
189 /* EEPROM access above 16k is unsupported */
192 nvm->word_size = 1 << size;
198 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
199 * @hw: pointer to the HW structure
201 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
203 struct e1000_mac_info *mac = &hw->mac;
205 /* Set media type and media-dependent function pointers */
206 switch (hw->adapter->pdev->device) {
207 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
208 hw->phy.media_type = e1000_media_type_internal_serdes;
209 mac->ops.check_for_link = e1000e_check_for_serdes_link;
210 mac->ops.setup_physical_interface =
211 e1000e_setup_fiber_serdes_link;
214 hw->phy.media_type = e1000_media_type_copper;
215 mac->ops.check_for_link = e1000e_check_for_copper_link;
216 mac->ops.setup_physical_interface =
217 e1000_setup_copper_link_80003es2lan;
221 /* Set mta register count */
222 mac->mta_reg_count = 128;
223 /* Set rar entry count */
224 mac->rar_entry_count = E1000_RAR_ENTRIES;
226 mac->has_fwsm = true;
227 /* ARC supported; valid only if manageability features are enabled. */
228 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
229 /* Adaptive IFS not supported */
230 mac->adaptive_ifs = false;
232 /* set lan id for port to determine which phy lock to use */
233 hw->mac.ops.set_lan_id(hw);
238 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
240 struct e1000_hw *hw = &adapter->hw;
243 rc = e1000_init_mac_params_80003es2lan(hw);
247 rc = e1000_init_nvm_params_80003es2lan(hw);
251 rc = e1000_init_phy_params_80003es2lan(hw);
259 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
260 * @hw: pointer to the HW structure
262 * A wrapper to acquire access rights to the correct PHY.
264 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
268 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
269 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
273 * e1000_release_phy_80003es2lan - Release rights to access PHY
274 * @hw: pointer to the HW structure
276 * A wrapper to release access rights to the correct PHY.
278 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
282 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
283 e1000_release_swfw_sync_80003es2lan(hw, mask);
287 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
288 * @hw: pointer to the HW structure
290 * Acquire the semaphore to access the Kumeran interface.
293 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
297 mask = E1000_SWFW_CSR_SM;
299 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
303 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
304 * @hw: pointer to the HW structure
306 * Release the semaphore used to access the Kumeran interface
308 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
312 mask = E1000_SWFW_CSR_SM;
314 e1000_release_swfw_sync_80003es2lan(hw, mask);
318 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
319 * @hw: pointer to the HW structure
321 * Acquire the semaphore to access the EEPROM.
323 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
327 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
331 ret_val = e1000e_acquire_nvm(hw);
334 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
340 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
341 * @hw: pointer to the HW structure
343 * Release the semaphore used to access the EEPROM.
345 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
347 e1000e_release_nvm(hw);
348 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
352 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
353 * @hw: pointer to the HW structure
354 * @mask: specifies which semaphore to acquire
356 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
357 * will also specify which port we're acquiring the lock for.
359 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
363 u32 fwmask = mask << 16;
367 while (i < timeout) {
368 if (e1000e_get_hw_semaphore(hw))
369 return -E1000_ERR_SWFW_SYNC;
371 swfw_sync = er32(SW_FW_SYNC);
372 if (!(swfw_sync & (fwmask | swmask)))
375 /* Firmware currently using resource (fwmask)
376 * or other software thread using resource (swmask)
378 e1000e_put_hw_semaphore(hw);
384 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
385 return -E1000_ERR_SWFW_SYNC;
389 ew32(SW_FW_SYNC, swfw_sync);
391 e1000e_put_hw_semaphore(hw);
397 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
398 * @hw: pointer to the HW structure
399 * @mask: specifies which semaphore to acquire
401 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
402 * will also specify which port we're releasing the lock for.
404 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
408 while (e1000e_get_hw_semaphore(hw) != 0)
411 swfw_sync = er32(SW_FW_SYNC);
413 ew32(SW_FW_SYNC, swfw_sync);
415 e1000e_put_hw_semaphore(hw);
419 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
420 * @hw: pointer to the HW structure
421 * @offset: offset of the register to read
422 * @data: pointer to the data returned from the operation
424 * Read the GG82563 PHY register.
426 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
427 u32 offset, u16 *data)
433 ret_val = e1000_acquire_phy_80003es2lan(hw);
437 /* Select Configuration Page */
438 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
439 page_select = GG82563_PHY_PAGE_SELECT;
441 /* Use Alternative Page Select register to access
442 * registers 30 and 31
444 page_select = GG82563_PHY_PAGE_SELECT_ALT;
447 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
448 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
450 e1000_release_phy_80003es2lan(hw);
454 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
455 /* The "ready" bit in the MDIC register may be incorrectly set
456 * before the device has completed the "Page Select" MDI
457 * transaction. So we wait 200us after each MDI command...
461 /* ...and verify the command was successful. */
462 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
464 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
465 e1000_release_phy_80003es2lan(hw);
466 return -E1000_ERR_PHY;
471 ret_val = e1000e_read_phy_reg_mdic(hw,
472 MAX_PHY_REG_ADDRESS & offset,
477 ret_val = e1000e_read_phy_reg_mdic(hw,
478 MAX_PHY_REG_ADDRESS & offset,
482 e1000_release_phy_80003es2lan(hw);
488 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
489 * @hw: pointer to the HW structure
490 * @offset: offset of the register to read
491 * @data: value to write to the register
493 * Write to the GG82563 PHY register.
495 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
496 u32 offset, u16 data)
502 ret_val = e1000_acquire_phy_80003es2lan(hw);
506 /* Select Configuration Page */
507 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
508 page_select = GG82563_PHY_PAGE_SELECT;
510 /* Use Alternative Page Select register to access
511 * registers 30 and 31
513 page_select = GG82563_PHY_PAGE_SELECT_ALT;
516 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
517 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
519 e1000_release_phy_80003es2lan(hw);
523 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
524 /* The "ready" bit in the MDIC register may be incorrectly set
525 * before the device has completed the "Page Select" MDI
526 * transaction. So we wait 200us after each MDI command...
530 /* ...and verify the command was successful. */
531 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
533 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
534 e1000_release_phy_80003es2lan(hw);
535 return -E1000_ERR_PHY;
540 ret_val = e1000e_write_phy_reg_mdic(hw,
541 MAX_PHY_REG_ADDRESS & offset,
546 ret_val = e1000e_write_phy_reg_mdic(hw,
547 MAX_PHY_REG_ADDRESS & offset,
551 e1000_release_phy_80003es2lan(hw);
557 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
558 * @hw: pointer to the HW structure
559 * @offset: offset of the register to read
560 * @words: number of words to write
561 * @data: buffer of data to write to the NVM
563 * Write "words" of data to the ESB2 NVM.
565 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
566 u16 words, u16 *data)
568 return e1000e_write_nvm_spi(hw, offset, words, data);
572 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
573 * @hw: pointer to the HW structure
575 * Wait a specific amount of time for manageability processes to complete.
576 * This is a function pointer entry point called by the phy module.
578 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
580 s32 timeout = PHY_CFG_TIMEOUT;
581 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
583 if (hw->bus.func == 1)
584 mask = E1000_NVM_CFG_DONE_PORT_1;
587 if (er32(EEMNGCTL) & mask)
589 usleep_range(1000, 2000);
593 e_dbg("MNG configuration cycle has not completed.\n");
594 return -E1000_ERR_RESET;
601 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
602 * @hw: pointer to the HW structure
604 * Force the speed and duplex settings onto the PHY. This is a
605 * function pointer entry point called by the phy module.
607 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
613 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
614 * forced whenever speed and duplex are forced.
616 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
620 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
621 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
625 e_dbg("GG82563 PSCR: %X\n", phy_data);
627 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
631 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
633 /* Reset the phy to commit changes. */
634 phy_data |= MII_CR_RESET;
636 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
642 if (hw->phy.autoneg_wait_to_complete) {
643 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
645 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
651 /* We didn't get link.
652 * Reset the DSP and cross our fingers.
654 ret_val = e1000e_phy_reset_dsp(hw);
660 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
666 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
670 /* Resetting the phy means we need to verify the TX_CLK corresponds
671 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
673 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
674 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
675 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
677 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
679 /* In addition, we must re-enable CRS on Tx for both half and full
682 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
683 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
689 * e1000_get_cable_length_80003es2lan - Set approximate cable length
690 * @hw: pointer to the HW structure
692 * Find the approximate cable length as measured by the GG82563 PHY.
693 * This is a function pointer entry point called by the phy module.
695 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
697 struct e1000_phy_info *phy = &hw->phy;
701 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
705 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
707 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
708 return -E1000_ERR_PHY;
710 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
711 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
713 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
719 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
720 * @hw: pointer to the HW structure
721 * @speed: pointer to speed buffer
722 * @duplex: pointer to duplex buffer
724 * Retrieve the current speed and duplex configuration.
726 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
731 if (hw->phy.media_type == e1000_media_type_copper) {
732 ret_val = e1000e_get_speed_and_duplex_copper(hw,
735 hw->phy.ops.cfg_on_link_up(hw);
737 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
746 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
747 * @hw: pointer to the HW structure
749 * Perform a global reset to the ESB2 controller.
751 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
757 /* Prevent the PCI-E bus from sticking if there is no TLP connection
758 * on the last TLP read/write transaction when MAC is reset.
760 ret_val = e1000e_disable_pcie_master(hw);
762 e_dbg("PCI-E Master disable polling has failed.\n");
764 e_dbg("Masking off all interrupts\n");
765 ew32(IMC, 0xffffffff);
768 ew32(TCTL, E1000_TCTL_PSP);
771 usleep_range(10000, 20000);
775 ret_val = e1000_acquire_phy_80003es2lan(hw);
779 e_dbg("Issuing a global reset to MAC\n");
780 ew32(CTRL, ctrl | E1000_CTRL_RST);
781 e1000_release_phy_80003es2lan(hw);
783 /* Disable IBIST slave mode (far-end loopback) */
784 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
786 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
787 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
790 ret_val = e1000e_get_auto_rd_done(hw);
792 /* We don't want to continue accessing MAC registers. */
795 /* Clear any pending interrupt events. */
796 ew32(IMC, 0xffffffff);
799 return e1000_check_alt_mac_addr_generic(hw);
803 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
804 * @hw: pointer to the HW structure
806 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
808 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
810 struct e1000_mac_info *mac = &hw->mac;
816 e1000_initialize_hw_bits_80003es2lan(hw);
818 /* Initialize identification LED */
819 ret_val = mac->ops.id_led_init(hw);
821 e_dbg("Error initializing identification LED\n");
822 /* This is not fatal and we should not stop init due to this */
824 /* Disabling VLAN filtering */
825 e_dbg("Initializing the IEEE VLAN\n");
826 mac->ops.clear_vfta(hw);
828 /* Setup the receive address. */
829 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
831 /* Zero out the Multicast HASH table */
832 e_dbg("Zeroing the MTA\n");
833 for (i = 0; i < mac->mta_reg_count; i++)
834 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
836 /* Setup link and flow control */
837 ret_val = mac->ops.setup_link(hw);
841 /* Disable IBIST slave mode (far-end loopback) */
842 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
844 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
845 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
848 /* Set the transmit descriptor write-back policy */
849 reg_data = er32(TXDCTL(0));
850 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
851 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
852 ew32(TXDCTL(0), reg_data);
854 /* ...for both queues. */
855 reg_data = er32(TXDCTL(1));
856 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
857 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
858 ew32(TXDCTL(1), reg_data);
860 /* Enable retransmit on late collisions */
861 reg_data = er32(TCTL);
862 reg_data |= E1000_TCTL_RTLC;
863 ew32(TCTL, reg_data);
865 /* Configure Gigabit Carry Extend Padding */
866 reg_data = er32(TCTL_EXT);
867 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
868 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
869 ew32(TCTL_EXT, reg_data);
871 /* Configure Transmit Inter-Packet Gap */
872 reg_data = er32(TIPG);
873 reg_data &= ~E1000_TIPG_IPGT_MASK;
874 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
875 ew32(TIPG, reg_data);
877 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
878 reg_data &= ~0x00100000;
879 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
881 /* default to true to enable the MDIC W/A */
882 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
884 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
885 E1000_KMRNCTRLSTA_OFFSET >>
886 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
889 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
890 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
891 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
894 /* Clear all of the statistics registers (clear on read). It is
895 * important that we do this after we have tried to establish link
896 * because the symbol error count will increment wildly if there
899 e1000_clear_hw_cntrs_80003es2lan(hw);
905 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
906 * @hw: pointer to the HW structure
908 * Initializes required hardware-dependent bits needed for normal operation.
910 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
914 /* Transmit Descriptor Control 0 */
915 reg = er32(TXDCTL(0));
917 ew32(TXDCTL(0), reg);
919 /* Transmit Descriptor Control 1 */
920 reg = er32(TXDCTL(1));
922 ew32(TXDCTL(1), reg);
924 /* Transmit Arbitration Control 0 */
926 reg &= ~(0xF << 27); /* 30:27 */
927 if (hw->phy.media_type != e1000_media_type_copper)
931 /* Transmit Arbitration Control 1 */
933 if (er32(TCTL) & E1000_TCTL_MULR)
939 /* Disable IPv6 extension header parsing because some malformed
940 * IPv6 headers can hang the Rx.
943 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
948 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
949 * @hw: pointer to the HW structure
951 * Setup some GG82563 PHY registers for obtaining link
953 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
955 struct e1000_phy_info *phy = &hw->phy;
960 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
964 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
965 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
966 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
968 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
973 * MDI/MDI-X = 0 (default)
974 * 0 - Auto for all speeds
977 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
979 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
983 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
987 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
990 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
994 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
999 * disable_polarity_correction = 0 (default)
1000 * Automatic Correction for Reversed Cable Polarity
1004 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1005 if (phy->disable_polarity_correction)
1006 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1008 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1012 /* SW Reset the PHY so all changes take effect */
1013 ret_val = e1000e_commit_phy(hw);
1015 e_dbg("Error Resetting the PHY\n");
1019 /* Bypass Rx and Tx FIFO's */
1020 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1021 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1022 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1023 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1027 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1028 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1032 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1033 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1034 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1039 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1043 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1044 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1048 ctrl_ext = er32(CTRL_EXT);
1049 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1050 ew32(CTRL_EXT, ctrl_ext);
1052 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1056 /* Do not init these registers when the HW is in IAMT mode, since the
1057 * firmware will have already initialized them. We only initialize
1058 * them if the HW is not in IAMT mode.
1060 if (!hw->mac.ops.check_mng_mode(hw)) {
1061 /* Enable Electrical Idle on the PHY */
1062 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1063 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1067 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1071 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1072 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1077 /* Workaround: Disable padding in Kumeran interface in the MAC
1078 * and in the PHY to avoid CRC errors.
1080 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1084 data |= GG82563_ICR_DIS_PADDING;
1085 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1093 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1094 * @hw: pointer to the HW structure
1096 * Essentially a wrapper for setting up all things "copper" related.
1097 * This is a function pointer entry point called by the mac module.
1099 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1106 ctrl |= E1000_CTRL_SLU;
1107 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1110 /* Set the mac to wait the maximum time between each
1111 * iteration and increase the max iterations when
1112 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1114 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1118 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1123 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1127 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1128 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1132 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1133 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1134 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1139 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1143 return e1000e_setup_copper_link(hw);
1147 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1148 * @hw: pointer to the HW structure
1149 * @duplex: current duplex setting
1151 * Configure the KMRN interface by applying last minute quirks for
1154 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1160 if (hw->phy.media_type == e1000_media_type_copper) {
1161 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1166 if (speed == SPEED_1000)
1167 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1169 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1176 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1177 * @hw: pointer to the HW structure
1178 * @duplex: current duplex setting
1180 * Configure the KMRN interface by applying last minute quirks for
1183 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1188 u16 reg_data, reg_data2;
1190 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1191 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1192 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1197 /* Configure Transmit Inter-Packet Gap */
1199 tipg &= ~E1000_TIPG_IPGT_MASK;
1200 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1204 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1208 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1212 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1214 if (duplex == HALF_DUPLEX)
1215 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1217 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1219 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1223 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1224 * @hw: pointer to the HW structure
1226 * Configure the KMRN interface by applying last minute quirks for
1227 * gigabit operation.
1229 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1232 u16 reg_data, reg_data2;
1236 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1237 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1238 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1243 /* Configure Transmit Inter-Packet Gap */
1245 tipg &= ~E1000_TIPG_IPGT_MASK;
1246 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1250 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1254 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1258 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1260 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1262 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1266 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1267 * @hw: pointer to the HW structure
1268 * @offset: register offset to be read
1269 * @data: pointer to the read data
1271 * Acquire semaphore, then read the PHY register at offset
1272 * using the kumeran interface. The information retrieved is stored in data.
1273 * Release the semaphore before exiting.
1275 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1281 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1285 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1286 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1287 ew32(KMRNCTRLSTA, kmrnctrlsta);
1292 kmrnctrlsta = er32(KMRNCTRLSTA);
1293 *data = (u16)kmrnctrlsta;
1295 e1000_release_mac_csr_80003es2lan(hw);
1301 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1302 * @hw: pointer to the HW structure
1303 * @offset: register offset to write to
1304 * @data: data to write at register offset
1306 * Acquire semaphore, then write the data to PHY register
1307 * at the offset using the kumeran interface. Release semaphore
1310 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1316 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1320 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1321 E1000_KMRNCTRLSTA_OFFSET) | data;
1322 ew32(KMRNCTRLSTA, kmrnctrlsta);
1327 e1000_release_mac_csr_80003es2lan(hw);
1333 * e1000_read_mac_addr_80003es2lan - Read device MAC address
1334 * @hw: pointer to the HW structure
1336 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1340 /* If there's an alternate MAC address place it in RAR0
1341 * so that it will override the Si installed default perm
1344 ret_val = e1000_check_alt_mac_addr_generic(hw);
1348 return e1000_read_mac_addr_generic(hw);
1352 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1353 * @hw: pointer to the HW structure
1355 * In the case of a PHY power down to save power, or to turn off link during a
1356 * driver unload, or wake on lan is not enabled, remove the link.
1358 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1360 /* If the management interface is not enabled, then power down */
1361 if (!(hw->mac.ops.check_mng_mode(hw) ||
1362 hw->phy.ops.check_reset_block(hw)))
1363 e1000_power_down_phy_copper(hw);
1367 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1368 * @hw: pointer to the HW structure
1370 * Clears the hardware counters by reading the counter registers.
1372 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1374 e1000e_clear_hw_cntrs_base(hw);
1412 static const struct e1000_mac_operations es2_mac_ops = {
1413 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1414 .id_led_init = e1000e_id_led_init_generic,
1415 .blink_led = e1000e_blink_led_generic,
1416 .check_mng_mode = e1000e_check_mng_mode_generic,
1417 /* check_for_link dependent on media type */
1418 .cleanup_led = e1000e_cleanup_led_generic,
1419 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1420 .get_bus_info = e1000e_get_bus_info_pcie,
1421 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1422 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1423 .led_on = e1000e_led_on_generic,
1424 .led_off = e1000e_led_off_generic,
1425 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1426 .write_vfta = e1000_write_vfta_generic,
1427 .clear_vfta = e1000_clear_vfta_generic,
1428 .reset_hw = e1000_reset_hw_80003es2lan,
1429 .init_hw = e1000_init_hw_80003es2lan,
1430 .setup_link = e1000e_setup_link_generic,
1431 /* setup_physical_interface dependent on media type */
1432 .setup_led = e1000e_setup_led_generic,
1433 .config_collision_dist = e1000e_config_collision_dist_generic,
1434 .rar_set = e1000e_rar_set_generic,
1437 static const struct e1000_phy_operations es2_phy_ops = {
1438 .acquire = e1000_acquire_phy_80003es2lan,
1439 .check_polarity = e1000_check_polarity_m88,
1440 .check_reset_block = e1000e_check_reset_block_generic,
1441 .commit = e1000e_phy_sw_reset,
1442 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1443 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1444 .get_cable_length = e1000_get_cable_length_80003es2lan,
1445 .get_info = e1000e_get_phy_info_m88,
1446 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1447 .release = e1000_release_phy_80003es2lan,
1448 .reset = e1000e_phy_hw_reset_generic,
1449 .set_d0_lplu_state = NULL,
1450 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1451 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1452 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1455 static const struct e1000_nvm_operations es2_nvm_ops = {
1456 .acquire = e1000_acquire_nvm_80003es2lan,
1457 .read = e1000e_read_nvm_eerd,
1458 .release = e1000_release_nvm_80003es2lan,
1459 .reload = e1000e_reload_nvm_generic,
1460 .update = e1000e_update_nvm_checksum_generic,
1461 .valid_led_default = e1000e_valid_led_default,
1462 .validate = e1000e_validate_nvm_checksum_generic,
1463 .write = e1000_write_nvm_80003es2lan,
1466 const struct e1000_info e1000_es2_info = {
1467 .mac = e1000_80003es2lan,
1468 .flags = FLAG_HAS_HW_VLAN_FILTER
1469 | FLAG_HAS_JUMBO_FRAMES
1471 | FLAG_APME_IN_CTRL3
1472 | FLAG_HAS_CTRLEXT_ON_LOAD
1473 | FLAG_RX_NEEDS_RESTART /* errata */
1474 | FLAG_TARC_SET_BIT_ZERO /* errata */
1475 | FLAG_APME_CHECK_PORT_B
1476 | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1477 .flags2 = FLAG2_DMA_BURST,
1479 .max_hw_frame_size = DEFAULT_JUMBO,
1480 .get_variants = e1000_get_variants_80003es2lan,
1481 .mac_ops = &es2_mac_ops,
1482 .phy_ops = &es2_phy_ops,
1483 .nvm_ops = &es2_nvm_ops,