2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/cdev.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <asm/cacheflush.h>
17 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_platform.h>
21 #include <linux/of_irq.h>
22 #include <linux/spinlock.h>
24 #include "hns_dsaf_main.h"
25 #include "hns_dsaf_ppe.h"
26 #include "hns_dsaf_rcb.h"
28 #define RCB_COMMON_REG_OFFSET 0x80000
32 #define RCB_RESET_WAIT_TIMES 30
33 #define RCB_RESET_TRY_TIMES 10
36 *hns_rcb_wait_fbd_clean - clean fbd
37 *@qs: ring struct pointer array
41 void hns_rcb_wait_fbd_clean(struct hnae_queue **qs, int q_num, u32 flag)
46 for (wait_cnt = i = 0; i < q_num; wait_cnt++) {
47 usleep_range(200, 300);
49 if (flag & RCB_INT_FLAG_TX)
50 fbd_num += dsaf_read_dev(qs[i],
51 RCB_RING_TX_RING_FBDNUM_REG);
52 if (flag & RCB_INT_FLAG_RX)
53 fbd_num += dsaf_read_dev(qs[i],
54 RCB_RING_RX_RING_FBDNUM_REG);
57 if (wait_cnt >= 10000)
62 dev_err(qs[i]->handle->owner_dev,
63 "queue(%d) wait fbd(%d) clean fail!!\n", i, fbd_num);
67 *hns_rcb_reset_ring_hw - ring reset
68 *@q: ring struct pointer
70 void hns_rcb_reset_ring_hw(struct hnae_queue *q)
78 while (try_cnt++ < RCB_RESET_TRY_TIMES) {
79 usleep_range(100, 200);
80 tx_fbd_num = dsaf_read_dev(q, RCB_RING_TX_RING_FBDNUM_REG);
84 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, 0);
86 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
89 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
92 while (!could_ret && (wait_cnt < RCB_RESET_WAIT_TIMES)) {
93 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
95 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 1);
98 could_ret = dsaf_read_dev(q, RCB_RING_COULD_BE_RST);
103 dsaf_write_dev(q, RCB_RING_T0_BE_RST, 0);
109 if (try_cnt >= RCB_RESET_TRY_TIMES)
110 dev_err(q->dev->dev, "port%d reset ring fail\n",
111 hns_ae_get_vf_cb(q->handle)->port_index);
115 *hns_rcb_int_ctrl_hw - rcb irq enable control
116 *@q: hnae queue struct pointer
117 *@flag:ring flag tx or rx
120 void hns_rcb_int_ctrl_hw(struct hnae_queue *q, u32 flag, u32 mask)
122 u32 int_mask_en = !!mask;
124 if (flag & RCB_INT_FLAG_TX) {
125 dsaf_write_dev(q, RCB_RING_INTMSK_TXWL_REG, int_mask_en);
126 dsaf_write_dev(q, RCB_RING_INTMSK_TX_OVERTIME_REG,
130 if (flag & RCB_INT_FLAG_RX) {
131 dsaf_write_dev(q, RCB_RING_INTMSK_RXWL_REG, int_mask_en);
132 dsaf_write_dev(q, RCB_RING_INTMSK_RX_OVERTIME_REG,
137 void hns_rcb_int_clr_hw(struct hnae_queue *q, u32 flag)
141 if (flag & RCB_INT_FLAG_TX) {
142 dsaf_write_dev(q, RCB_RING_INTSTS_TX_RING_REG, clr);
143 dsaf_write_dev(q, RCB_RING_INTSTS_TX_OVERTIME_REG, clr);
146 if (flag & RCB_INT_FLAG_RX) {
147 dsaf_write_dev(q, RCB_RING_INTSTS_RX_RING_REG, clr);
148 dsaf_write_dev(q, RCB_RING_INTSTS_RX_OVERTIME_REG, clr);
153 *hns_rcb_ring_enable_hw - enable ring
156 void hns_rcb_ring_enable_hw(struct hnae_queue *q, u32 val)
158 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val);
161 void hns_rcb_start(struct hnae_queue *q, u32 val)
163 hns_rcb_ring_enable_hw(q, val);
167 *hns_rcb_common_init_commit_hw - make rcb common init completed
168 *@rcb_common: rcb common device
170 void hns_rcb_common_init_commit_hw(struct rcb_common_cb *rcb_common)
172 wmb(); /* Sync point before breakpoint */
173 dsaf_write_dev(rcb_common, RCB_COM_CFG_SYS_FSH_REG, 1);
174 wmb(); /* Sync point after breakpoint */
178 *hns_rcb_ring_init - init rcb ring
179 *@ring_pair: ring pair control block
180 *@ring_type: ring type, RX_RING or TX_RING
182 static void hns_rcb_ring_init(struct ring_pair_cb *ring_pair, int ring_type)
184 struct hnae_queue *q = &ring_pair->q;
185 struct rcb_common_cb *rcb_common = ring_pair->rcb_common;
186 u32 bd_size_type = rcb_common->dsaf_dev->buf_size_type;
187 struct hnae_ring *ring =
188 (ring_type == RX_RING) ? &q->rx_ring : &q->tx_ring;
189 dma_addr_t dma = ring->desc_dma_addr;
191 if (ring_type == RX_RING) {
192 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_L_REG,
194 dsaf_write_dev(q, RCB_RING_RX_RING_BASEADDR_H_REG,
195 (u32)((dma >> 31) >> 1));
196 dsaf_write_dev(q, RCB_RING_RX_RING_BD_LEN_REG,
198 dsaf_write_dev(q, RCB_RING_RX_RING_BD_NUM_REG,
199 ring_pair->port_id_in_dsa);
200 dsaf_write_dev(q, RCB_RING_RX_RING_PKTLINE_REG,
201 ring_pair->port_id_in_dsa);
203 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_L_REG,
205 dsaf_write_dev(q, RCB_RING_TX_RING_BASEADDR_H_REG,
206 (u32)((dma >> 31) >> 1));
207 dsaf_write_dev(q, RCB_RING_TX_RING_BD_LEN_REG,
209 dsaf_write_dev(q, RCB_RING_TX_RING_BD_NUM_REG,
210 ring_pair->port_id_in_dsa);
211 dsaf_write_dev(q, RCB_RING_TX_RING_PKTLINE_REG,
212 ring_pair->port_id_in_dsa);
217 *hns_rcb_init_hw - init rcb hardware
220 void hns_rcb_init_hw(struct ring_pair_cb *ring)
222 hns_rcb_ring_init(ring, RX_RING);
223 hns_rcb_ring_init(ring, TX_RING);
227 *hns_rcb_set_port_desc_cnt - set rcb port description num
228 *@rcb_common: rcb_common device
229 *@port_idx:port index
232 static void hns_rcb_set_port_desc_cnt(struct rcb_common_cb *rcb_common,
233 u32 port_idx, u32 desc_cnt)
235 if (port_idx >= HNS_RCB_SERVICE_NW_ENGINE_NUM)
238 dsaf_write_dev(rcb_common, RCB_CFG_BD_NUM_REG + port_idx * 4,
243 *hns_rcb_set_port_coalesced_frames - set rcb port coalesced frames
244 *@rcb_common: rcb_common device
245 *@port_idx:port index
246 *@coalesced_frames:BD num for coalesced frames
248 static int hns_rcb_set_port_coalesced_frames(struct rcb_common_cb *rcb_common,
250 u32 coalesced_frames)
252 if (port_idx >= HNS_RCB_SERVICE_NW_ENGINE_NUM)
254 if (coalesced_frames >= rcb_common->desc_num ||
255 coalesced_frames > HNS_RCB_MAX_COALESCED_FRAMES)
258 dsaf_write_dev(rcb_common, RCB_CFG_PKTLINE_REG + port_idx * 4,
264 *hns_rcb_get_port_coalesced_frames - set rcb port coalesced frames
265 *@rcb_common: rcb_common device
266 *@port_idx:port index
267 * return coaleseced frames value
269 static u32 hns_rcb_get_port_coalesced_frames(struct rcb_common_cb *rcb_common,
272 if (port_idx >= HNS_RCB_SERVICE_NW_ENGINE_NUM)
275 return dsaf_read_dev(rcb_common,
276 RCB_CFG_PKTLINE_REG + port_idx * 4);
280 *hns_rcb_set_timeout - set rcb port coalesced time_out
281 *@rcb_common: rcb_common device
282 *@time_out:time for coalesced time_out
284 static void hns_rcb_set_timeout(struct rcb_common_cb *rcb_common,
287 dsaf_write_dev(rcb_common, RCB_CFG_OVERTIME_REG, timeout);
290 static int hns_rcb_common_get_port_num(struct rcb_common_cb *rcb_common)
292 if (rcb_common->comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX)
293 return HNS_RCB_SERVICE_NW_ENGINE_NUM;
295 return HNS_RCB_DEBUG_NW_ENGINE_NUM;
298 /*clr rcb comm exception irq**/
299 static void hns_rcb_comm_exc_irq_en(
300 struct rcb_common_cb *rcb_common, int en)
302 u32 clr_vlue = 0xfffffffful;
303 u32 msk_vlue = en ? 0 : 0xfffffffful;
306 dsaf_write_dev(rcb_common, RCB_COM_INTSTS_ECC_ERR_REG, clr_vlue);
308 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_RING_STS, clr_vlue);
310 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_BD_RINT_STS, clr_vlue);
312 dsaf_write_dev(rcb_common, RCB_COM_RINT_TX_PKT_REG, clr_vlue);
313 dsaf_write_dev(rcb_common, RCB_COM_AXI_ERR_STS, clr_vlue);
316 dsaf_write_dev(rcb_common, RCB_COM_INTMASK_ECC_ERR_REG, msk_vlue);
318 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_RING, msk_vlue);
320 /*for tx bd neednot cacheline, so msk sf_txring_fbd_intmask (bit 1)**/
321 dsaf_write_dev(rcb_common, RCB_COM_SF_CFG_INTMASK_BD, msk_vlue | 2);
323 dsaf_write_dev(rcb_common, RCB_COM_INTMSK_TX_PKT_REG, msk_vlue);
324 dsaf_write_dev(rcb_common, RCB_COM_AXI_WR_ERR_INTMASK, msk_vlue);
328 *hns_rcb_common_init_hw - init rcb common hardware
329 *@rcb_common: rcb_common device
330 *retuen 0 - success , negative --fail
332 int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common)
336 int port_num = hns_rcb_common_get_port_num(rcb_common);
338 hns_rcb_comm_exc_irq_en(rcb_common, 0);
340 reg_val = dsaf_read_dev(rcb_common, RCB_COM_CFG_INIT_FLAG_REG);
341 if (0x1 != (reg_val & 0x1)) {
342 dev_err(rcb_common->dsaf_dev->dev,
343 "RCB_COM_CFG_INIT_FLAG_REG reg = 0x%x\n", reg_val);
347 for (i = 0; i < port_num; i++) {
348 hns_rcb_set_port_desc_cnt(rcb_common, i, rcb_common->desc_num);
349 (void)hns_rcb_set_port_coalesced_frames(
350 rcb_common, i, rcb_common->coalesced_frames);
352 hns_rcb_set_timeout(rcb_common, rcb_common->timeout);
354 dsaf_write_dev(rcb_common, RCB_COM_CFG_ENDIAN_REG,
355 HNS_RCB_COMMON_ENDIAN);
360 int hns_rcb_buf_size2type(u32 buf_size)
366 bd_size_type = HNS_BD_SIZE_512_TYPE;
369 bd_size_type = HNS_BD_SIZE_1024_TYPE;
372 bd_size_type = HNS_BD_SIZE_2048_TYPE;
375 bd_size_type = HNS_BD_SIZE_4096_TYPE;
378 bd_size_type = -EINVAL;
384 static void hns_rcb_ring_get_cfg(struct hnae_queue *q, int ring_type)
386 struct hnae_ring *ring;
387 struct rcb_common_cb *rcb_common;
388 struct ring_pair_cb *ring_pair_cb;
393 ring_pair_cb = container_of(q, struct ring_pair_cb, q);
394 if (ring_type == RX_RING) {
396 ring->io_base = ring_pair_cb->q.io_base;
397 irq_idx = HNS_RCB_IRQ_IDX_RX;
400 ring->io_base = (u8 __iomem *)ring_pair_cb->q.io_base +
401 HNS_RCB_TX_REG_OFFSET;
402 irq_idx = HNS_RCB_IRQ_IDX_TX;
405 rcb_common = ring_pair_cb->rcb_common;
406 buf_size = rcb_common->dsaf_dev->buf_size;
407 desc_num = rcb_common->dsaf_dev->desc_num;
410 ring->desc_cb = NULL;
412 ring->irq = ring_pair_cb->virq[irq_idx];
413 ring->desc_dma_addr = 0;
415 ring->buf_size = buf_size;
416 ring->desc_num = desc_num;
417 ring->max_desc_num_per_pkt = HNS_RCB_RING_MAX_BD_PER_PKT;
418 ring->max_raw_data_sz_per_desc = HNS_RCB_MAX_PKT_SIZE;
419 ring->max_pkt_size = HNS_RCB_MAX_PKT_SIZE;
420 ring->next_to_use = 0;
421 ring->next_to_clean = 0;
424 static void hns_rcb_ring_pair_get_cfg(struct ring_pair_cb *ring_pair_cb)
426 ring_pair_cb->q.handle = NULL;
428 hns_rcb_ring_get_cfg(&ring_pair_cb->q, RX_RING);
429 hns_rcb_ring_get_cfg(&ring_pair_cb->q, TX_RING);
432 static int hns_rcb_get_port(struct rcb_common_cb *rcb_common, int ring_idx)
434 int comm_index = rcb_common->comm_index;
438 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
439 q_num = (int)rcb_common->max_q_per_vf * rcb_common->max_vfn;
440 port = ring_idx / q_num;
442 port = HNS_RCB_SERVICE_NW_ENGINE_NUM + comm_index - 1;
448 static int hns_rcb_get_base_irq_idx(struct rcb_common_cb *rcb_common)
450 int comm_index = rcb_common->comm_index;
452 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX)
453 return HNS_SERVICE_RING_IRQ_IDX;
455 return HNS_DEBUG_RING_IRQ_IDX + (comm_index - 1) * 2;
458 #define RCB_COMM_BASE_TO_RING_BASE(base, ringid)\
459 ((base) + 0x10000 + HNS_RCB_REG_OFFSET * (ringid))
461 *hns_rcb_get_cfg - get rcb config
462 *@rcb_common: rcb common device
464 void hns_rcb_get_cfg(struct rcb_common_cb *rcb_common)
466 struct ring_pair_cb *ring_pair_cb;
468 u32 ring_num = rcb_common->ring_num;
469 int base_irq_idx = hns_rcb_get_base_irq_idx(rcb_common);
470 struct device_node *np = rcb_common->dsaf_dev->dev->of_node;
472 for (i = 0; i < ring_num; i++) {
473 ring_pair_cb = &rcb_common->ring_pair_cb[i];
474 ring_pair_cb->rcb_common = rcb_common;
475 ring_pair_cb->dev = rcb_common->dsaf_dev->dev;
476 ring_pair_cb->index = i;
477 ring_pair_cb->q.io_base =
478 RCB_COMM_BASE_TO_RING_BASE(rcb_common->io_base, i);
479 ring_pair_cb->port_id_in_dsa = hns_rcb_get_port(rcb_common, i);
480 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_TX]
481 = irq_of_parse_and_map(np, base_irq_idx + i * 2);
482 ring_pair_cb->virq[HNS_RCB_IRQ_IDX_RX]
483 = irq_of_parse_and_map(np, base_irq_idx + i * 2 + 1);
484 ring_pair_cb->q.phy_base =
485 RCB_COMM_BASE_TO_RING_BASE(rcb_common->phy_base, i);
486 hns_rcb_ring_pair_get_cfg(ring_pair_cb);
491 *hns_rcb_get_coalesced_frames - get rcb port coalesced frames
492 *@rcb_common: rcb_common device
493 *@comm_index:port index
494 *return coalesced_frames
496 u32 hns_rcb_get_coalesced_frames(struct dsaf_device *dsaf_dev, int port)
498 int comm_index = hns_dsaf_get_comm_idx_by_port(port);
499 struct rcb_common_cb *rcb_comm = dsaf_dev->rcb_common[comm_index];
501 return hns_rcb_get_port_coalesced_frames(rcb_comm, port);
505 *hns_rcb_get_coalesce_usecs - get rcb port coalesced time_out
506 *@rcb_common: rcb_common device
507 *@comm_index:port index
510 u32 hns_rcb_get_coalesce_usecs(struct dsaf_device *dsaf_dev, int comm_index)
512 struct rcb_common_cb *rcb_comm = dsaf_dev->rcb_common[comm_index];
514 return rcb_comm->timeout;
518 *hns_rcb_set_coalesce_usecs - set rcb port coalesced time_out
519 *@rcb_common: rcb_common device
520 *@comm_index: comm :index
521 *@etx_usecs:tx time for coalesced time_out
522 *@rx_usecs:rx time for coalesced time_out
524 void hns_rcb_set_coalesce_usecs(struct dsaf_device *dsaf_dev,
525 int port, u32 timeout)
527 int comm_index = hns_dsaf_get_comm_idx_by_port(port);
528 struct rcb_common_cb *rcb_comm = dsaf_dev->rcb_common[comm_index];
530 if (rcb_comm->timeout == timeout)
533 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
534 dev_err(dsaf_dev->dev,
535 "error: not support coalesce_usecs setting!\n");
538 rcb_comm->timeout = timeout;
539 hns_rcb_set_timeout(rcb_comm, rcb_comm->timeout);
543 *hns_rcb_set_coalesced_frames - set rcb coalesced frames
544 *@rcb_common: rcb_common device
545 *@tx_frames:tx BD num for coalesced frames
546 *@rx_frames:rx BD num for coalesced frames
547 *Return 0 on success, negative on failure
549 int hns_rcb_set_coalesced_frames(struct dsaf_device *dsaf_dev,
550 int port, u32 coalesced_frames)
552 int comm_index = hns_dsaf_get_comm_idx_by_port(port);
553 struct rcb_common_cb *rcb_comm = dsaf_dev->rcb_common[comm_index];
554 u32 coalesced_reg_val;
557 coalesced_reg_val = hns_rcb_get_port_coalesced_frames(rcb_comm, port);
559 if (coalesced_reg_val == coalesced_frames)
562 if (coalesced_frames >= HNS_RCB_MIN_COALESCED_FRAMES) {
563 ret = hns_rcb_set_port_coalesced_frames(rcb_comm, port,
572 *hns_rcb_get_queue_mode - get max VM number and max ring number per VM
573 * accordding to dsaf mode
574 *@dsaf_mode: dsaf mode
575 *@max_vfn : max vfn number
576 *@max_q_per_vf:max ring number per vm
578 static void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, int comm_index,
579 u16 *max_vfn, u16 *max_q_per_vf)
581 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
583 case DSAF_MODE_DISABLE_6PORT_0VM:
587 case DSAF_MODE_DISABLE_FIX:
591 case DSAF_MODE_DISABLE_2PORT_64VM:
595 case DSAF_MODE_DISABLE_6PORT_16VM:
610 int hns_rcb_get_ring_num(struct dsaf_device *dsaf_dev, int comm_index)
612 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
613 switch (dsaf_dev->dsaf_mode) {
614 case DSAF_MODE_ENABLE_FIX:
617 case DSAF_MODE_DISABLE_FIX:
620 case DSAF_MODE_ENABLE_0VM:
623 case DSAF_MODE_DISABLE_6PORT_0VM:
624 case DSAF_MODE_ENABLE_16VM:
625 case DSAF_MODE_DISABLE_6PORT_2VM:
626 case DSAF_MODE_DISABLE_6PORT_16VM:
627 case DSAF_MODE_DISABLE_6PORT_4VM:
628 case DSAF_MODE_ENABLE_8VM:
631 case DSAF_MODE_DISABLE_2PORT_16VM:
632 case DSAF_MODE_DISABLE_2PORT_8VM:
633 case DSAF_MODE_ENABLE_32VM:
634 case DSAF_MODE_DISABLE_2PORT_64VM:
635 case DSAF_MODE_ENABLE_128VM:
639 dev_warn(dsaf_dev->dev,
640 "get ring num fail,use default!dsaf_mode=%d\n",
641 dsaf_dev->dsaf_mode);
649 void __iomem *hns_rcb_common_get_vaddr(struct dsaf_device *dsaf_dev,
652 void __iomem *base_addr;
654 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX)
655 base_addr = dsaf_dev->ppe_base + RCB_COMMON_REG_OFFSET;
657 base_addr = dsaf_dev->sds_base
658 + (comm_index - 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET
659 + RCB_COMMON_REG_OFFSET;
664 static phys_addr_t hns_rcb_common_get_paddr(struct dsaf_device *dsaf_dev,
667 struct device_node *np = dsaf_dev->dev->of_node;
668 phys_addr_t phy_addr;
669 const __be32 *tmp_addr;
674 if (comm_index == HNS_DSAF_COMM_SERVICE_NW_IDX) {
676 addr_offset = RCB_COMMON_REG_OFFSET;
679 addr_offset = (comm_index - 1) * HNS_DSAF_DEBUG_NW_REG_OFFSET +
680 RCB_COMMON_REG_OFFSET;
682 tmp_addr = of_get_address(np, index, &size, NULL);
683 phy_addr = of_translate_address(np, tmp_addr);
684 return phy_addr + addr_offset;
687 int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev,
690 struct rcb_common_cb *rcb_common;
691 enum dsaf_mode dsaf_mode = dsaf_dev->dsaf_mode;
694 int ring_num = hns_rcb_get_ring_num(dsaf_dev, comm_index);
697 devm_kzalloc(dsaf_dev->dev, sizeof(*rcb_common) +
698 ring_num * sizeof(struct ring_pair_cb), GFP_KERNEL);
700 dev_err(dsaf_dev->dev, "rcb common devm_kzalloc fail!\n");
703 rcb_common->comm_index = comm_index;
704 rcb_common->ring_num = ring_num;
705 rcb_common->dsaf_dev = dsaf_dev;
707 rcb_common->desc_num = dsaf_dev->desc_num;
708 rcb_common->coalesced_frames = HNS_RCB_DEF_COALESCED_FRAMES;
709 rcb_common->timeout = HNS_RCB_MAX_TIME_OUT;
711 hns_rcb_get_queue_mode(dsaf_mode, comm_index, &max_vfn, &max_q_per_vf);
712 rcb_common->max_vfn = max_vfn;
713 rcb_common->max_q_per_vf = max_q_per_vf;
715 rcb_common->io_base = hns_rcb_common_get_vaddr(dsaf_dev, comm_index);
716 rcb_common->phy_base = hns_rcb_common_get_paddr(dsaf_dev, comm_index);
718 dsaf_dev->rcb_common[comm_index] = rcb_common;
722 void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev,
725 dsaf_dev->rcb_common[comm_index] = NULL;
728 void hns_rcb_update_stats(struct hnae_queue *queue)
730 struct ring_pair_cb *ring =
731 container_of(queue, struct ring_pair_cb, q);
732 struct dsaf_device *dsaf_dev = ring->rcb_common->dsaf_dev;
733 struct ppe_common_cb *ppe_common
734 = dsaf_dev->ppe_common[ring->rcb_common->comm_index];
735 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
737 hw_stats->rx_pkts += dsaf_read_dev(queue,
738 RCB_RING_RX_RING_PKTNUM_RECORD_REG);
739 dsaf_write_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG, 0x1);
741 hw_stats->ppe_rx_ok_pkts += dsaf_read_dev(ppe_common,
742 PPE_COM_HIS_RX_PKT_QID_OK_CNT_REG + 4 * ring->index);
743 hw_stats->ppe_rx_drop_pkts += dsaf_read_dev(ppe_common,
744 PPE_COM_HIS_RX_PKT_QID_DROP_CNT_REG + 4 * ring->index);
746 hw_stats->tx_pkts += dsaf_read_dev(queue,
747 RCB_RING_TX_RING_PKTNUM_RECORD_REG);
748 dsaf_write_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG, 0x1);
750 hw_stats->ppe_tx_ok_pkts += dsaf_read_dev(ppe_common,
751 PPE_COM_HIS_TX_PKT_QID_OK_CNT_REG + 4 * ring->index);
752 hw_stats->ppe_tx_drop_pkts += dsaf_read_dev(ppe_common,
753 PPE_COM_HIS_TX_PKT_QID_ERR_CNT_REG + 4 * ring->index);
757 *hns_rcb_get_stats - get rcb statistic
759 *@data:statistic value
761 void hns_rcb_get_stats(struct hnae_queue *queue, u64 *data)
763 u64 *regs_buff = data;
764 struct ring_pair_cb *ring =
765 container_of(queue, struct ring_pair_cb, q);
766 struct hns_ring_hw_stats *hw_stats = &ring->hw_stats;
768 regs_buff[0] = hw_stats->tx_pkts;
769 regs_buff[1] = hw_stats->ppe_tx_ok_pkts;
770 regs_buff[2] = hw_stats->ppe_tx_drop_pkts;
772 dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
774 regs_buff[4] = queue->tx_ring.stats.tx_pkts;
775 regs_buff[5] = queue->tx_ring.stats.tx_bytes;
776 regs_buff[6] = queue->tx_ring.stats.tx_err_cnt;
777 regs_buff[7] = queue->tx_ring.stats.io_err_cnt;
778 regs_buff[8] = queue->tx_ring.stats.sw_err_cnt;
779 regs_buff[9] = queue->tx_ring.stats.seg_pkt_cnt;
780 regs_buff[10] = queue->tx_ring.stats.restart_queue;
781 regs_buff[11] = queue->tx_ring.stats.tx_busy;
783 regs_buff[12] = hw_stats->rx_pkts;
784 regs_buff[13] = hw_stats->ppe_rx_ok_pkts;
785 regs_buff[14] = hw_stats->ppe_rx_drop_pkts;
787 dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
789 regs_buff[16] = queue->rx_ring.stats.rx_pkts;
790 regs_buff[17] = queue->rx_ring.stats.rx_bytes;
791 regs_buff[18] = queue->rx_ring.stats.rx_err_cnt;
792 regs_buff[19] = queue->rx_ring.stats.io_err_cnt;
793 regs_buff[20] = queue->rx_ring.stats.sw_err_cnt;
794 regs_buff[21] = queue->rx_ring.stats.seg_pkt_cnt;
795 regs_buff[22] = queue->rx_ring.stats.reuse_pg_cnt;
796 regs_buff[23] = queue->rx_ring.stats.err_pkt_len;
797 regs_buff[24] = queue->rx_ring.stats.non_vld_descs;
798 regs_buff[25] = queue->rx_ring.stats.err_bd_num;
799 regs_buff[26] = queue->rx_ring.stats.l2_err;
800 regs_buff[27] = queue->rx_ring.stats.l3l4_csum_err;
804 *hns_rcb_get_ring_sset_count - rcb string set count
805 *@stringset:ethtool cmd
806 *return rcb ring string set count
808 int hns_rcb_get_ring_sset_count(int stringset)
810 if (stringset == ETH_SS_STATS)
811 return HNS_RING_STATIC_REG_NUM;
817 *hns_rcb_get_common_regs_count - rcb common regs count
820 int hns_rcb_get_common_regs_count(void)
822 return HNS_RCB_COMMON_DUMP_REG_NUM;
826 *rcb_get_sset_count - rcb ring regs count
829 int hns_rcb_get_ring_regs_count(void)
831 return HNS_RCB_RING_DUMP_REG_NUM;
835 *hns_rcb_get_strings - get rcb string set
836 *@stringset:string set index
837 *@data:strings name value
840 void hns_rcb_get_strings(int stringset, u8 *data, int index)
842 char *buff = (char *)data;
844 if (stringset != ETH_SS_STATS)
847 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_rcb_pkt_num", index);
848 buff = buff + ETH_GSTRING_LEN;
849 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_tx_pkt_num", index);
850 buff = buff + ETH_GSTRING_LEN;
851 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_ppe_drop_pkt_num", index);
852 buff = buff + ETH_GSTRING_LEN;
853 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_fbd_num", index);
854 buff = buff + ETH_GSTRING_LEN;
856 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_pkt_num", index);
857 buff = buff + ETH_GSTRING_LEN;
858 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_bytes", index);
859 buff = buff + ETH_GSTRING_LEN;
860 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_err_cnt", index);
861 buff = buff + ETH_GSTRING_LEN;
862 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_io_err", index);
863 buff = buff + ETH_GSTRING_LEN;
864 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_sw_err", index);
865 buff = buff + ETH_GSTRING_LEN;
866 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_seg_pkt", index);
867 buff = buff + ETH_GSTRING_LEN;
868 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_restart_queue", index);
869 buff = buff + ETH_GSTRING_LEN;
870 snprintf(buff, ETH_GSTRING_LEN, "tx_ring%d_tx_busy", index);
871 buff = buff + ETH_GSTRING_LEN;
873 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_rcb_pkt_num", index);
874 buff = buff + ETH_GSTRING_LEN;
875 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_pkt_num", index);
876 buff = buff + ETH_GSTRING_LEN;
877 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_ppe_drop_pkt_num", index);
878 buff = buff + ETH_GSTRING_LEN;
879 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_fbd_num", index);
880 buff = buff + ETH_GSTRING_LEN;
882 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_pkt_num", index);
883 buff = buff + ETH_GSTRING_LEN;
884 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bytes", index);
885 buff = buff + ETH_GSTRING_LEN;
886 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_err_cnt", index);
887 buff = buff + ETH_GSTRING_LEN;
888 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_io_err", index);
889 buff = buff + ETH_GSTRING_LEN;
890 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_sw_err", index);
891 buff = buff + ETH_GSTRING_LEN;
892 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_seg_pkt", index);
893 buff = buff + ETH_GSTRING_LEN;
894 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_reuse_pg", index);
895 buff = buff + ETH_GSTRING_LEN;
896 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_len_err", index);
897 buff = buff + ETH_GSTRING_LEN;
898 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_non_vld_desc_err", index);
899 buff = buff + ETH_GSTRING_LEN;
900 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_bd_num_err", index);
901 buff = buff + ETH_GSTRING_LEN;
902 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l2_err", index);
903 buff = buff + ETH_GSTRING_LEN;
904 snprintf(buff, ETH_GSTRING_LEN, "rx_ring%d_l3l4csum_err", index);
907 void hns_rcb_get_common_regs(struct rcb_common_cb *rcb_com, void *data)
912 /*rcb common registers */
913 regs[0] = dsaf_read_dev(rcb_com, RCB_COM_CFG_ENDIAN_REG);
914 regs[1] = dsaf_read_dev(rcb_com, RCB_COM_CFG_SYS_FSH_REG);
915 regs[2] = dsaf_read_dev(rcb_com, RCB_COM_CFG_INIT_FLAG_REG);
917 regs[3] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_REG);
918 regs[4] = dsaf_read_dev(rcb_com, RCB_COM_CFG_RINVLD_REG);
919 regs[5] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FNA_REG);
920 regs[6] = dsaf_read_dev(rcb_com, RCB_COM_CFG_FA_REG);
921 regs[7] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PKT_TC_BP_REG);
922 regs[8] = dsaf_read_dev(rcb_com, RCB_COM_CFG_PPE_TNL_CLKEN_REG);
924 regs[9] = dsaf_read_dev(rcb_com, RCB_COM_INTMSK_TX_PKT_REG);
925 regs[10] = dsaf_read_dev(rcb_com, RCB_COM_RINT_TX_PKT_REG);
926 regs[11] = dsaf_read_dev(rcb_com, RCB_COM_INTMASK_ECC_ERR_REG);
927 regs[12] = dsaf_read_dev(rcb_com, RCB_COM_INTSTS_ECC_ERR_REG);
928 regs[13] = dsaf_read_dev(rcb_com, RCB_COM_EBD_SRAM_ERR_REG);
929 regs[14] = dsaf_read_dev(rcb_com, RCB_COM_RXRING_ERR_REG);
930 regs[15] = dsaf_read_dev(rcb_com, RCB_COM_TXRING_ERR_REG);
931 regs[16] = dsaf_read_dev(rcb_com, RCB_COM_TX_FBD_ERR_REG);
932 regs[17] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK_EN_REG);
933 regs[18] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK0_REG);
934 regs[19] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK1_REG);
935 regs[20] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK2_REG);
936 regs[21] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK3_REG);
937 regs[22] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK4_REG);
938 regs[23] = dsaf_read_dev(rcb_com, RCB_SRAM_ECC_CHK5_REG);
939 regs[24] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR0_REG);
940 regs[25] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR3_REG);
941 regs[26] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR4_REG);
942 regs[27] = dsaf_read_dev(rcb_com, RCB_ECC_ERR_ADDR5_REG);
944 regs[28] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_RING);
945 regs[29] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING_STS);
946 regs[30] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_RING);
947 regs[31] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_INTMASK_BD);
948 regs[32] = dsaf_read_dev(rcb_com, RCB_COM_SF_CFG_BD_RINT_STS);
949 regs[33] = dsaf_read_dev(rcb_com, RCB_COM_RCB_RD_BD_BUSY);
950 regs[34] = dsaf_read_dev(rcb_com, RCB_COM_RCB_FBD_CRT_EN);
951 regs[35] = dsaf_read_dev(rcb_com, RCB_COM_AXI_WR_ERR_INTMASK);
952 regs[36] = dsaf_read_dev(rcb_com, RCB_COM_AXI_ERR_STS);
953 regs[37] = dsaf_read_dev(rcb_com, RCB_COM_CHK_TX_FBD_NUM_REG);
955 /* rcb common entry registers */
956 for (i = 0; i < 16; i++) { /* total 16 model registers */
958 = dsaf_read_dev(rcb_com, RCB_CFG_BD_NUM_REG + 4 * i);
960 = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_REG + 4 * i);
963 regs[70] = dsaf_read_dev(rcb_com, RCB_CFG_OVERTIME_REG);
964 regs[71] = dsaf_read_dev(rcb_com, RCB_CFG_PKTLINE_INT_NUM_REG);
965 regs[72] = dsaf_read_dev(rcb_com, RCB_CFG_OVERTIME_INT_NUM_REG);
967 /* mark end of rcb common regs */
968 for (i = 73; i < 80; i++)
969 regs[i] = 0xcccccccc;
972 void hns_rcb_get_ring_regs(struct hnae_queue *queue, void *data)
975 struct ring_pair_cb *ring_pair
976 = container_of(queue, struct ring_pair_cb, q);
979 /*rcb ring registers */
980 regs[0] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_L_REG);
981 regs[1] = dsaf_read_dev(queue, RCB_RING_RX_RING_BASEADDR_H_REG);
982 regs[2] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_NUM_REG);
983 regs[3] = dsaf_read_dev(queue, RCB_RING_RX_RING_BD_LEN_REG);
984 regs[4] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTLINE_REG);
985 regs[5] = dsaf_read_dev(queue, RCB_RING_RX_RING_TAIL_REG);
986 regs[6] = dsaf_read_dev(queue, RCB_RING_RX_RING_HEAD_REG);
987 regs[7] = dsaf_read_dev(queue, RCB_RING_RX_RING_FBDNUM_REG);
988 regs[8] = dsaf_read_dev(queue, RCB_RING_RX_RING_PKTNUM_RECORD_REG);
990 regs[9] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_L_REG);
991 regs[10] = dsaf_read_dev(queue, RCB_RING_TX_RING_BASEADDR_H_REG);
992 regs[11] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_NUM_REG);
993 regs[12] = dsaf_read_dev(queue, RCB_RING_TX_RING_BD_LEN_REG);
994 regs[13] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTLINE_REG);
995 regs[15] = dsaf_read_dev(queue, RCB_RING_TX_RING_TAIL_REG);
996 regs[16] = dsaf_read_dev(queue, RCB_RING_TX_RING_HEAD_REG);
997 regs[17] = dsaf_read_dev(queue, RCB_RING_TX_RING_FBDNUM_REG);
998 regs[18] = dsaf_read_dev(queue, RCB_RING_TX_RING_OFFSET_REG);
999 regs[19] = dsaf_read_dev(queue, RCB_RING_TX_RING_PKTNUM_RECORD_REG);
1001 regs[20] = dsaf_read_dev(queue, RCB_RING_PREFETCH_EN_REG);
1002 regs[21] = dsaf_read_dev(queue, RCB_RING_CFG_VF_NUM_REG);
1003 regs[22] = dsaf_read_dev(queue, RCB_RING_ASID_REG);
1004 regs[23] = dsaf_read_dev(queue, RCB_RING_RX_VM_REG);
1005 regs[24] = dsaf_read_dev(queue, RCB_RING_T0_BE_RST);
1006 regs[25] = dsaf_read_dev(queue, RCB_RING_COULD_BE_RST);
1007 regs[26] = dsaf_read_dev(queue, RCB_RING_WRR_WEIGHT_REG);
1009 regs[27] = dsaf_read_dev(queue, RCB_RING_INTMSK_RXWL_REG);
1010 regs[28] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_RING_REG);
1011 regs[29] = dsaf_read_dev(queue, RCB_RING_INTMSK_TXWL_REG);
1012 regs[30] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_RING_REG);
1013 regs[31] = dsaf_read_dev(queue, RCB_RING_INTMSK_RX_OVERTIME_REG);
1014 regs[32] = dsaf_read_dev(queue, RCB_RING_INTSTS_RX_OVERTIME_REG);
1015 regs[33] = dsaf_read_dev(queue, RCB_RING_INTMSK_TX_OVERTIME_REG);
1016 regs[34] = dsaf_read_dev(queue, RCB_RING_INTSTS_TX_OVERTIME_REG);
1018 /* mark end of ring regs */
1019 for (i = 35; i < 40; i++)
1020 regs[i] = 0xcccccc00 + ring_pair->index;