2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60 #include <linux/prefetch.h>
62 #include <asm/cacheflush.h>
66 static void set_multicast_list(struct net_device *ndev);
67 static void fec_enet_itr_coal_init(struct net_device *ndev);
69 #define DRIVER_NAME "fec"
71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 static struct platform_device_id fec_devtype[] = {
83 /* keep it for coldfire */
88 .driver_data = FEC_QUIRK_USE_GASKET,
94 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME |
95 FEC_QUIRK_SINGLE_MDIO,
98 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
99 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
100 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
102 .name = "mvf600-fec",
103 .driver_data = FEC_QUIRK_ENET_MAC,
105 .name = "imx6sx-fec",
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
107 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
108 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
109 FEC_QUIRK_ERR007885 | FEC_QUIRK_BUG_CAPTURE,
114 MODULE_DEVICE_TABLE(platform, fec_devtype);
117 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
118 IMX27_FEC, /* runs on i.mx27/35/51 */
125 static const struct of_device_id fec_dt_ids[] = {
126 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
127 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
128 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
129 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
130 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
131 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
134 MODULE_DEVICE_TABLE(of, fec_dt_ids);
136 static unsigned char macaddr[ETH_ALEN];
137 module_param_array(macaddr, byte, NULL, 0);
138 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
140 #if defined(CONFIG_M5272)
142 * Some hardware gets it MAC address out of local flash memory.
143 * if this is non-zero then assume it is the address to get MAC from.
145 #if defined(CONFIG_NETtel)
146 #define FEC_FLASHMAC 0xf0006006
147 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
148 #define FEC_FLASHMAC 0xf0006000
149 #elif defined(CONFIG_CANCam)
150 #define FEC_FLASHMAC 0xf0020000
151 #elif defined (CONFIG_M5272C3)
152 #define FEC_FLASHMAC (0xffe04000 + 4)
153 #elif defined(CONFIG_MOD5272)
154 #define FEC_FLASHMAC 0xffc0406b
156 #define FEC_FLASHMAC 0
158 #endif /* CONFIG_M5272 */
160 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
162 #define PKT_MAXBUF_SIZE 1522
163 #define PKT_MINBUF_SIZE 64
164 #define PKT_MAXBLR_SIZE 1536
166 /* FEC receive acceleration */
167 #define FEC_RACC_IPDIS (1 << 1)
168 #define FEC_RACC_PRODIS (1 << 2)
169 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
172 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
173 * size bits. Other FEC hardware does not, so we need to take that into
174 * account when setting it.
176 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
177 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
178 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
180 #define OPT_FRAME_SIZE 0
183 /* FEC MII MMFR bits definition */
184 #define FEC_MMFR_ST (1 << 30)
185 #define FEC_MMFR_OP_READ (2 << 28)
186 #define FEC_MMFR_OP_WRITE (1 << 28)
187 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
188 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
189 #define FEC_MMFR_TA (2 << 16)
190 #define FEC_MMFR_DATA(v) (v & 0xffff)
191 /* FEC ECR bits definition */
192 #define FEC_ECR_MAGICEN (1 << 2)
193 #define FEC_ECR_SLEEP (1 << 3)
195 #define FEC_MII_TIMEOUT 30000 /* us */
197 /* Transmitter timeout */
198 #define TX_TIMEOUT (2 * HZ)
200 #define FEC_PAUSE_FLAG_AUTONEG 0x1
201 #define FEC_PAUSE_FLAG_ENABLE 0x2
202 #define FEC_WOL_HAS_MAGIC_PACKET (0x1 << 0)
203 #define FEC_WOL_FLAG_ENABLE (0x1 << 1)
204 #define FEC_WOL_FLAG_SLEEP_ON (0x1 << 2)
206 #define COPYBREAK_DEFAULT 256
208 #define TSO_HEADER_SIZE 128
209 /* Max number of allowed TCP segments for software TSO */
210 #define FEC_MAX_TSO_SEGS 100
211 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
213 #define IS_TSO_HEADER(txq, addr) \
214 ((addr >= txq->tso_hdrs_dma) && \
215 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
220 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
221 struct fec_enet_private *fep,
224 struct bufdesc *new_bd = bdp + 1;
225 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
226 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
227 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
228 struct bufdesc_ex *ex_base;
229 struct bufdesc *base;
232 if (bdp >= txq->tx_bd_base) {
233 base = txq->tx_bd_base;
234 ring_size = txq->tx_ring_size;
235 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
237 base = rxq->rx_bd_base;
238 ring_size = rxq->rx_ring_size;
239 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
243 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
244 ex_base : ex_new_bd);
246 return (new_bd >= (base + ring_size)) ?
251 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
252 struct fec_enet_private *fep,
255 struct bufdesc *new_bd = bdp - 1;
256 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
257 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
258 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
259 struct bufdesc_ex *ex_base;
260 struct bufdesc *base;
263 if (bdp >= txq->tx_bd_base) {
264 base = txq->tx_bd_base;
265 ring_size = txq->tx_ring_size;
266 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
268 base = rxq->rx_bd_base;
269 ring_size = rxq->rx_ring_size;
270 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
274 return (struct bufdesc *)((ex_new_bd < ex_base) ?
275 (ex_new_bd + ring_size) : ex_new_bd);
277 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
280 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
281 struct fec_enet_private *fep)
283 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
286 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
287 struct fec_enet_priv_tx_q *txq)
291 entries = ((const char *)txq->dirty_tx -
292 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
294 return entries > 0 ? entries : entries + txq->tx_ring_size;
297 static void swap_buffer(void *bufaddr, int len)
300 unsigned int *buf = bufaddr;
302 for (i = 0; i < len; i += 4, buf++)
306 static void swap_buffer2(void *dst_buf, void *src_buf, int len)
309 unsigned int *src = src_buf;
310 unsigned int *dst = dst_buf;
312 for (i = 0; i < len; i += 4, src++, dst++)
316 static void fec_dump(struct net_device *ndev)
318 struct fec_enet_private *fep = netdev_priv(ndev);
320 struct fec_enet_priv_tx_q *txq;
323 netdev_info(ndev, "TX ring dump\n");
324 pr_info("Nr SC addr len SKB\n");
326 txq = fep->tx_queue[0];
327 bdp = txq->tx_bd_base;
330 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
332 bdp == txq->cur_tx ? 'S' : ' ',
333 bdp == txq->dirty_tx ? 'H' : ' ',
334 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
335 txq->tx_skbuff[index]);
336 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
338 } while (bdp != txq->tx_bd_base);
341 static inline bool is_ipv4_pkt(struct sk_buff *skb)
343 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
347 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
349 /* Only run for packets requiring a checksum. */
350 if (skb->ip_summed != CHECKSUM_PARTIAL)
353 if (unlikely(skb_cow_head(skb, 0)))
356 if (is_ipv4_pkt(skb))
357 ip_hdr(skb)->check = 0;
358 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
364 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
366 struct net_device *ndev)
368 struct fec_enet_private *fep = netdev_priv(ndev);
369 struct bufdesc *bdp = txq->cur_tx;
370 struct bufdesc_ex *ebdp;
371 int nr_frags = skb_shinfo(skb)->nr_frags;
372 unsigned short queue = skb_get_queue_mapping(skb);
374 unsigned short status;
375 unsigned int estatus = 0;
376 skb_frag_t *this_frag;
382 for (frag = 0; frag < nr_frags; frag++) {
383 this_frag = &skb_shinfo(skb)->frags[frag];
384 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
385 ebdp = (struct bufdesc_ex *)bdp;
387 status = bdp->cbd_sc;
388 status &= ~BD_ENET_TX_STATS;
389 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
390 frag_len = skb_shinfo(skb)->frags[frag].size;
392 /* Handle the last BD specially */
393 if (frag == nr_frags - 1) {
394 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
395 if (fep->bufdesc_ex) {
396 estatus |= BD_ENET_TX_INT;
397 if (unlikely(skb_shinfo(skb)->tx_flags &
398 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
399 estatus |= BD_ENET_TX_TS;
403 if (fep->bufdesc_ex) {
404 if (fep->quirks & FEC_QUIRK_HAS_AVB)
405 estatus |= FEC_TX_BD_FTYPE(queue);
406 if (skb->ip_summed == CHECKSUM_PARTIAL)
407 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
409 ebdp->cbd_esc = estatus;
412 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
414 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
415 if (((unsigned long) bufaddr) & fep->tx_align ||
416 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
417 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
418 bufaddr = txq->tx_bounce[index];
420 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
421 swap_buffer(bufaddr, frag_len);
424 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
426 if (dma_mapping_error(&fep->pdev->dev, addr)) {
427 dev_kfree_skb_any(skb);
429 netdev_err(ndev, "Tx DMA memory map failed\n");
430 goto dma_mapping_error;
433 bdp->cbd_bufaddr = addr;
434 bdp->cbd_datlen = frag_len;
435 bdp->cbd_sc = status;
444 for (i = 0; i < frag; i++) {
445 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
446 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
447 bdp->cbd_datlen, DMA_TO_DEVICE);
452 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
453 struct sk_buff *skb, struct net_device *ndev)
455 struct fec_enet_private *fep = netdev_priv(ndev);
456 int nr_frags = skb_shinfo(skb)->nr_frags;
457 struct bufdesc *bdp, *last_bdp;
460 unsigned short status;
461 unsigned short buflen;
462 unsigned short queue;
463 unsigned int estatus = 0;
468 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
469 if (entries_free < MAX_SKB_FRAGS + 1) {
470 dev_kfree_skb_any(skb);
472 netdev_err(ndev, "NOT enough BD for SG!\n");
476 /* Protocol checksum off-load for TCP and UDP. */
477 if (fec_enet_clear_csum(skb, ndev)) {
478 dev_kfree_skb_any(skb);
482 /* Fill in a Tx ring entry */
484 status = bdp->cbd_sc;
485 status &= ~BD_ENET_TX_STATS;
487 /* Set buffer length and buffer pointer */
489 buflen = skb_headlen(skb);
491 queue = skb_get_queue_mapping(skb);
492 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
493 if (((unsigned long) bufaddr) & fep->tx_align ||
494 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
495 memcpy(txq->tx_bounce[index], skb->data, buflen);
496 bufaddr = txq->tx_bounce[index];
498 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
499 swap_buffer(bufaddr, buflen);
502 /* Push the data cache so the CPM does not get stale memory data. */
503 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
504 if (dma_mapping_error(&fep->pdev->dev, addr)) {
505 dev_kfree_skb_any(skb);
507 netdev_err(ndev, "Tx DMA memory map failed\n");
512 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
516 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
517 if (fep->bufdesc_ex) {
518 estatus = BD_ENET_TX_INT;
519 if (unlikely(skb_shinfo(skb)->tx_flags &
520 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
521 estatus |= BD_ENET_TX_TS;
525 if (fep->bufdesc_ex) {
527 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
529 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
531 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
533 if (fep->quirks & FEC_QUIRK_HAS_AVB)
534 estatus |= FEC_TX_BD_FTYPE(queue);
536 if (skb->ip_summed == CHECKSUM_PARTIAL)
537 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
540 ebdp->cbd_esc = estatus;
543 last_bdp = txq->cur_tx;
544 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
545 /* Save skb pointer */
546 txq->tx_skbuff[index] = skb;
548 bdp->cbd_datlen = buflen;
549 bdp->cbd_bufaddr = addr;
551 /* Send it on its way. Tell FEC it's ready, interrupt when done,
552 * it's the last BD of the frame, and to put the CRC on the end.
554 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
555 bdp->cbd_sc = status;
557 /* If this was the last BD in the ring, start at the beginning again. */
558 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
560 skb_tx_timestamp(skb);
564 /* Trigger transmission start */
565 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
571 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
572 struct net_device *ndev,
573 struct bufdesc *bdp, int index, char *data,
574 int size, bool last_tcp, bool is_last)
576 struct fec_enet_private *fep = netdev_priv(ndev);
577 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
578 unsigned short queue = skb_get_queue_mapping(skb);
579 unsigned short status;
580 unsigned int estatus = 0;
583 status = bdp->cbd_sc;
584 status &= ~BD_ENET_TX_STATS;
586 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
588 if (((unsigned long) data) & fep->tx_align ||
589 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
590 memcpy(txq->tx_bounce[index], data, size);
591 data = txq->tx_bounce[index];
593 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
594 swap_buffer(data, size);
597 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
598 if (dma_mapping_error(&fep->pdev->dev, addr)) {
599 dev_kfree_skb_any(skb);
601 netdev_err(ndev, "Tx DMA memory map failed\n");
602 return NETDEV_TX_BUSY;
605 bdp->cbd_datlen = size;
606 bdp->cbd_bufaddr = addr;
608 if (fep->bufdesc_ex) {
609 if (fep->quirks & FEC_QUIRK_HAS_AVB)
610 estatus |= FEC_TX_BD_FTYPE(queue);
611 if (skb->ip_summed == CHECKSUM_PARTIAL)
612 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
614 ebdp->cbd_esc = estatus;
617 /* Handle the last BD specially */
619 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
621 status |= BD_ENET_TX_INTR;
623 ebdp->cbd_esc |= BD_ENET_TX_INT;
626 bdp->cbd_sc = status;
632 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
633 struct sk_buff *skb, struct net_device *ndev,
634 struct bufdesc *bdp, int index)
636 struct fec_enet_private *fep = netdev_priv(ndev);
637 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
638 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
639 unsigned short queue = skb_get_queue_mapping(skb);
641 unsigned long dmabuf;
642 unsigned short status;
643 unsigned int estatus = 0;
645 status = bdp->cbd_sc;
646 status &= ~BD_ENET_TX_STATS;
647 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
649 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
650 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
651 if (((unsigned long)bufaddr) & fep->tx_align ||
652 fep->quirks & FEC_QUIRK_SWAP_FRAME) {
653 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
654 bufaddr = txq->tx_bounce[index];
656 if (fep->quirks & FEC_QUIRK_SWAP_FRAME)
657 swap_buffer(bufaddr, hdr_len);
659 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
660 hdr_len, DMA_TO_DEVICE);
661 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
662 dev_kfree_skb_any(skb);
664 netdev_err(ndev, "Tx DMA memory map failed\n");
665 return NETDEV_TX_BUSY;
669 bdp->cbd_bufaddr = dmabuf;
670 bdp->cbd_datlen = hdr_len;
672 if (fep->bufdesc_ex) {
673 if (fep->quirks & FEC_QUIRK_HAS_AVB)
674 estatus |= FEC_TX_BD_FTYPE(queue);
675 if (skb->ip_summed == CHECKSUM_PARTIAL)
676 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
678 ebdp->cbd_esc = estatus;
681 bdp->cbd_sc = status;
686 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
688 struct net_device *ndev)
690 struct fec_enet_private *fep = netdev_priv(ndev);
691 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
692 int total_len, data_left;
693 struct bufdesc *bdp = txq->cur_tx;
694 unsigned short queue = skb_get_queue_mapping(skb);
696 unsigned int index = 0;
699 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
700 dev_kfree_skb_any(skb);
702 netdev_err(ndev, "NOT enough BD for TSO!\n");
706 /* Protocol checksum off-load for TCP and UDP. */
707 if (fec_enet_clear_csum(skb, ndev)) {
708 dev_kfree_skb_any(skb);
712 /* Initialize the TSO handler, and prepare the first payload */
713 tso_start(skb, &tso);
715 total_len = skb->len - hdr_len;
716 while (total_len > 0) {
719 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
720 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
721 total_len -= data_left;
723 /* prepare packet headers: MAC + IP + TCP */
724 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
725 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
726 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
730 while (data_left > 0) {
733 size = min_t(int, tso.size, data_left);
734 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
735 index = fec_enet_get_bd_index(txq->tx_bd_base,
737 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
746 tso_build_data(skb, &tso, size);
749 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
752 /* Save skb pointer */
753 txq->tx_skbuff[index] = skb;
755 skb_tx_timestamp(skb);
758 /* Trigger transmission start */
759 if (!(fep->quirks & FEC_QUIRK_ERR007885) ||
760 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
761 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
762 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
763 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
764 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
769 /* TODO: Release all used data descriptors for TSO */
774 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
776 struct fec_enet_private *fep = netdev_priv(ndev);
778 unsigned short queue;
779 struct fec_enet_priv_tx_q *txq;
780 struct netdev_queue *nq;
783 queue = skb_get_queue_mapping(skb);
784 txq = fep->tx_queue[queue];
785 nq = netdev_get_tx_queue(ndev, queue);
788 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
790 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
794 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
795 if (entries_free <= txq->tx_stop_threshold)
796 netif_tx_stop_queue(nq);
801 /* Init RX & TX buffer descriptors
803 static void fec_enet_bd_init(struct net_device *dev)
805 struct fec_enet_private *fep = netdev_priv(dev);
806 struct fec_enet_priv_tx_q *txq;
807 struct fec_enet_priv_rx_q *rxq;
812 for (q = 0; q < fep->num_rx_queues; q++) {
813 /* Initialize the receive buffer descriptors. */
814 rxq = fep->rx_queue[q];
815 bdp = rxq->rx_bd_base;
817 for (i = 0; i < rxq->rx_ring_size; i++) {
819 /* Initialize the BD for every fragment in the page. */
820 if (bdp->cbd_bufaddr)
821 bdp->cbd_sc = BD_ENET_RX_EMPTY;
824 bdp = fec_enet_get_nextdesc(bdp, fep, q);
827 /* Set the last buffer to wrap */
828 bdp = fec_enet_get_prevdesc(bdp, fep, q);
829 bdp->cbd_sc |= BD_SC_WRAP;
831 rxq->cur_rx = rxq->rx_bd_base;
834 for (q = 0; q < fep->num_tx_queues; q++) {
835 /* ...and the same for transmit */
836 txq = fep->tx_queue[q];
837 bdp = txq->tx_bd_base;
840 for (i = 0; i < txq->tx_ring_size; i++) {
841 /* Initialize the BD for every fragment in the page. */
843 if (txq->tx_skbuff[i]) {
844 dev_kfree_skb_any(txq->tx_skbuff[i]);
845 txq->tx_skbuff[i] = NULL;
847 bdp->cbd_bufaddr = 0;
848 bdp = fec_enet_get_nextdesc(bdp, fep, q);
851 /* Set the last buffer to wrap */
852 bdp = fec_enet_get_prevdesc(bdp, fep, q);
853 bdp->cbd_sc |= BD_SC_WRAP;
858 static void fec_enet_active_rxring(struct net_device *ndev)
860 struct fec_enet_private *fep = netdev_priv(ndev);
863 for (i = 0; i < fep->num_rx_queues; i++)
864 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
867 static void fec_enet_enable_ring(struct net_device *ndev)
869 struct fec_enet_private *fep = netdev_priv(ndev);
870 struct fec_enet_priv_tx_q *txq;
871 struct fec_enet_priv_rx_q *rxq;
874 for (i = 0; i < fep->num_rx_queues; i++) {
875 rxq = fep->rx_queue[i];
876 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
877 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE(i));
881 writel(RCMR_MATCHEN | RCMR_CMP(i),
882 fep->hwp + FEC_RCMR(i));
885 for (i = 0; i < fep->num_tx_queues; i++) {
886 txq = fep->tx_queue[i];
887 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
891 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
892 fep->hwp + FEC_DMA_CFG(i));
896 static void fec_enet_reset_skb(struct net_device *ndev)
898 struct fec_enet_private *fep = netdev_priv(ndev);
899 struct fec_enet_priv_tx_q *txq;
902 for (i = 0; i < fep->num_tx_queues; i++) {
903 txq = fep->tx_queue[i];
905 for (j = 0; j < txq->tx_ring_size; j++) {
906 if (txq->tx_skbuff[j]) {
907 dev_kfree_skb_any(txq->tx_skbuff[j]);
908 txq->tx_skbuff[j] = NULL;
915 * This function is called to start or restart the FEC during a link
916 * change, transmit timeout, or to reconfigure the FEC. The network
917 * packet processing for this device must be stopped before this call.
920 fec_restart(struct net_device *ndev)
922 struct fec_enet_private *fep = netdev_priv(ndev);
925 u32 rcntl = OPT_FRAME_SIZE | 0x04;
926 u32 ecntl = 0x2; /* ETHEREN */
928 /* Whack a reset. We should wait for this.
929 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
930 * instead of reset MAC itself.
932 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
933 writel(0, fep->hwp + FEC_ECNTRL);
935 writel(1, fep->hwp + FEC_ECNTRL);
940 * enet-mac reset will reset mac address registers too,
941 * so need to reconfigure it.
943 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
944 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
945 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
946 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
949 /* Clear any outstanding interrupt. */
950 writel(0xffffffff, fep->hwp + FEC_IEVENT);
952 fec_enet_bd_init(ndev);
954 fec_enet_enable_ring(ndev);
956 /* Reset tx SKB buffers. */
957 fec_enet_reset_skb(ndev);
959 /* Enable MII mode */
960 if (fep->full_duplex == DUPLEX_FULL) {
962 writel(0x04, fep->hwp + FEC_X_CNTRL);
966 writel(0x0, fep->hwp + FEC_X_CNTRL);
970 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
972 #if !defined(CONFIG_M5272)
973 /* set RX checksum */
974 val = readl(fep->hwp + FEC_RACC);
975 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
976 val |= FEC_RACC_OPTIONS;
978 val &= ~FEC_RACC_OPTIONS;
979 writel(val, fep->hwp + FEC_RACC);
983 * The phy interface and speed need to get configured
984 * differently on enet-mac.
986 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
987 /* Enable flow control and length check */
988 rcntl |= 0x40000000 | 0x00000020;
990 /* RGMII, RMII or MII */
991 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
993 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
998 /* 1G, 100M or 10M */
1000 if (fep->phy_dev->speed == SPEED_1000)
1002 else if (fep->phy_dev->speed == SPEED_100)
1008 #ifdef FEC_MIIGSK_ENR
1009 if (fep->quirks & FEC_QUIRK_USE_GASKET) {
1011 /* disable the gasket and wait */
1012 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1013 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1017 * configure the gasket:
1018 * RMII, 50 MHz, no loopback, no echo
1019 * MII, 25 MHz, no loopback, no echo
1021 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1022 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1023 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1024 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1025 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1027 /* re-enable the gasket */
1028 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1033 #if !defined(CONFIG_M5272)
1034 /* enable pause frame*/
1035 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1036 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1037 fep->phy_dev && fep->phy_dev->pause)) {
1038 rcntl |= FEC_ENET_FCE;
1040 /* set FIFO threshold parameter to reduce overrun */
1041 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1042 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1043 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1044 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1047 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1049 rcntl &= ~FEC_ENET_FCE;
1051 #endif /* !defined(CONFIG_M5272) */
1053 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1055 /* Setup multicast filter. */
1056 set_multicast_list(ndev);
1057 #ifndef CONFIG_M5272
1058 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1059 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1062 if (fep->quirks & FEC_QUIRK_ENET_MAC) {
1063 /* enable ENET endian swap */
1065 /* enable ENET store and forward mode */
1066 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1069 if (fep->bufdesc_ex)
1072 #ifndef CONFIG_M5272
1073 /* Enable the MIB statistic event counters */
1074 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1077 /* And last, enable the transmit and receive processing */
1078 writel(ecntl, fep->hwp + FEC_ECNTRL);
1079 fec_enet_active_rxring(ndev);
1081 if (fep->bufdesc_ex)
1082 fec_ptp_start_cyclecounter(ndev);
1084 /* Enable interrupts we wish to service */
1086 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1088 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1090 /* Init the interrupt coalescing */
1091 fec_enet_itr_coal_init(ndev);
1096 fec_stop(struct net_device *ndev)
1098 struct fec_enet_private *fep = netdev_priv(ndev);
1099 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
1100 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1103 /* We cannot expect a graceful transmit stop without link !!! */
1105 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1107 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1108 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1111 /* Whack a reset. We should wait for this.
1112 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1113 * instead of reset MAC itself.
1115 if (!(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1116 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
1117 writel(0, fep->hwp + FEC_ECNTRL);
1119 writel(1, fep->hwp + FEC_ECNTRL);
1122 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1124 writel(FEC_DEFAULT_IMASK | FEC_ENET_WAKEUP, fep->hwp + FEC_IMASK);
1125 val = readl(fep->hwp + FEC_ECNTRL);
1126 val |= (FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
1127 writel(val, fep->hwp + FEC_ECNTRL);
1129 if (pdata && pdata->sleep_mode_enable)
1130 pdata->sleep_mode_enable(true);
1132 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1134 /* We have to keep ENET enabled to have MII interrupt stay working */
1135 if (fep->quirks & FEC_QUIRK_ENET_MAC &&
1136 !(fep->wol_flag & FEC_WOL_FLAG_SLEEP_ON)) {
1137 writel(2, fep->hwp + FEC_ECNTRL);
1138 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1144 fec_timeout(struct net_device *ndev)
1146 struct fec_enet_private *fep = netdev_priv(ndev);
1150 ndev->stats.tx_errors++;
1152 schedule_work(&fep->tx_timeout_work);
1155 static void fec_enet_timeout_work(struct work_struct *work)
1157 struct fec_enet_private *fep =
1158 container_of(work, struct fec_enet_private, tx_timeout_work);
1159 struct net_device *ndev = fep->netdev;
1162 if (netif_device_present(ndev) || netif_running(ndev)) {
1163 napi_disable(&fep->napi);
1164 netif_tx_lock_bh(ndev);
1166 netif_wake_queue(ndev);
1167 netif_tx_unlock_bh(ndev);
1168 napi_enable(&fep->napi);
1174 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1175 struct skb_shared_hwtstamps *hwtstamps)
1177 unsigned long flags;
1180 spin_lock_irqsave(&fep->tmreg_lock, flags);
1181 ns = timecounter_cyc2time(&fep->tc, ts);
1182 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1184 memset(hwtstamps, 0, sizeof(*hwtstamps));
1185 hwtstamps->hwtstamp = ns_to_ktime(ns);
1189 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1191 struct fec_enet_private *fep;
1192 struct bufdesc *bdp;
1193 unsigned short status;
1194 struct sk_buff *skb;
1195 struct fec_enet_priv_tx_q *txq;
1196 struct netdev_queue *nq;
1200 fep = netdev_priv(ndev);
1202 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1204 txq = fep->tx_queue[queue_id];
1205 /* get next bdp of dirty_tx */
1206 nq = netdev_get_tx_queue(ndev, queue_id);
1207 bdp = txq->dirty_tx;
1209 /* get next bdp of dirty_tx */
1210 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1212 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1214 /* current queue is empty */
1215 if (bdp == txq->cur_tx)
1218 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1220 skb = txq->tx_skbuff[index];
1221 txq->tx_skbuff[index] = NULL;
1222 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1223 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1224 bdp->cbd_datlen, DMA_TO_DEVICE);
1225 bdp->cbd_bufaddr = 0;
1227 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1231 /* Check for errors. */
1232 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1233 BD_ENET_TX_RL | BD_ENET_TX_UN |
1235 ndev->stats.tx_errors++;
1236 if (status & BD_ENET_TX_HB) /* No heartbeat */
1237 ndev->stats.tx_heartbeat_errors++;
1238 if (status & BD_ENET_TX_LC) /* Late collision */
1239 ndev->stats.tx_window_errors++;
1240 if (status & BD_ENET_TX_RL) /* Retrans limit */
1241 ndev->stats.tx_aborted_errors++;
1242 if (status & BD_ENET_TX_UN) /* Underrun */
1243 ndev->stats.tx_fifo_errors++;
1244 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1245 ndev->stats.tx_carrier_errors++;
1247 ndev->stats.tx_packets++;
1248 ndev->stats.tx_bytes += skb->len;
1251 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1253 struct skb_shared_hwtstamps shhwtstamps;
1254 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1256 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1257 skb_tstamp_tx(skb, &shhwtstamps);
1260 /* Deferred means some collisions occurred during transmit,
1261 * but we eventually sent the packet OK.
1263 if (status & BD_ENET_TX_DEF)
1264 ndev->stats.collisions++;
1266 /* Free the sk buffer associated with this last transmit */
1267 dev_kfree_skb_any(skb);
1269 txq->dirty_tx = bdp;
1271 /* Update pointer to next buffer descriptor to be transmitted */
1272 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1274 /* Since we have freed up a buffer, the ring is no longer full
1276 if (netif_queue_stopped(ndev)) {
1277 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1278 if (entries_free >= txq->tx_wake_threshold)
1279 netif_tx_wake_queue(nq);
1283 /* ERR006538: Keep the transmitter going */
1284 if (bdp != txq->cur_tx &&
1285 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1286 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1290 fec_enet_tx(struct net_device *ndev)
1292 struct fec_enet_private *fep = netdev_priv(ndev);
1294 /* First process class A queue, then Class B and Best Effort queue */
1295 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1296 clear_bit(queue_id, &fep->work_tx);
1297 fec_enet_tx_queue(ndev, queue_id);
1303 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1305 struct fec_enet_private *fep = netdev_priv(ndev);
1308 off = ((unsigned long)skb->data) & fep->rx_align;
1310 skb_reserve(skb, fep->rx_align + 1 - off);
1312 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1313 FEC_ENET_RX_FRSIZE - fep->rx_align,
1315 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1316 if (net_ratelimit())
1317 netdev_err(ndev, "Rx DMA memory map failed\n");
1324 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1325 struct bufdesc *bdp, u32 length, bool swap)
1327 struct fec_enet_private *fep = netdev_priv(ndev);
1328 struct sk_buff *new_skb;
1330 if (length > fep->rx_copybreak)
1333 new_skb = netdev_alloc_skb(ndev, length);
1337 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1338 FEC_ENET_RX_FRSIZE - fep->rx_align,
1341 memcpy(new_skb->data, (*skb)->data, length);
1343 swap_buffer2(new_skb->data, (*skb)->data, length);
1349 /* During a receive, the cur_rx points to the current incoming buffer.
1350 * When we update through the ring, if the next incoming buffer has
1351 * not been given to the system, we just set the empty indicator,
1352 * effectively tossing the packet.
1355 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1357 struct fec_enet_private *fep = netdev_priv(ndev);
1358 struct fec_enet_priv_rx_q *rxq;
1359 struct bufdesc *bdp;
1360 unsigned short status;
1361 struct sk_buff *skb_new = NULL;
1362 struct sk_buff *skb;
1365 int pkt_received = 0;
1366 struct bufdesc_ex *ebdp = NULL;
1367 bool vlan_packet_rcvd = false;
1371 bool need_swap = fep->quirks & FEC_QUIRK_SWAP_FRAME;
1376 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1377 rxq = fep->rx_queue[queue_id];
1379 /* First, grab all of the stats for the incoming packet.
1380 * These get messed up if we get called due to a busy condition.
1384 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1386 if (pkt_received >= budget)
1390 /* Since we have allocated space to hold a complete frame,
1391 * the last indicator should be set.
1393 if ((status & BD_ENET_RX_LAST) == 0)
1394 netdev_err(ndev, "rcv is not +last\n");
1397 /* Check for errors. */
1398 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1399 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1400 ndev->stats.rx_errors++;
1401 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1402 /* Frame too long or too short. */
1403 ndev->stats.rx_length_errors++;
1405 if (status & BD_ENET_RX_NO) /* Frame alignment */
1406 ndev->stats.rx_frame_errors++;
1407 if (status & BD_ENET_RX_CR) /* CRC Error */
1408 ndev->stats.rx_crc_errors++;
1409 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1410 ndev->stats.rx_fifo_errors++;
1413 /* Report late collisions as a frame error.
1414 * On this error, the BD is closed, but we don't know what we
1415 * have in the buffer. So, just drop this frame on the floor.
1417 if (status & BD_ENET_RX_CL) {
1418 ndev->stats.rx_errors++;
1419 ndev->stats.rx_frame_errors++;
1420 goto rx_processing_done;
1423 /* Process the incoming frame. */
1424 ndev->stats.rx_packets++;
1425 pkt_len = bdp->cbd_datlen;
1426 ndev->stats.rx_bytes += pkt_len;
1428 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1429 skb = rxq->rx_skbuff[index];
1431 /* The packet length includes FCS, but we don't want to
1432 * include that when passing upstream as it messes up
1433 * bridging applications.
1435 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4,
1437 if (!is_copybreak) {
1438 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1439 if (unlikely(!skb_new)) {
1440 ndev->stats.rx_dropped++;
1441 goto rx_processing_done;
1443 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1444 FEC_ENET_RX_FRSIZE - fep->rx_align,
1448 prefetch(skb->data - NET_IP_ALIGN);
1449 skb_put(skb, pkt_len - 4);
1451 if (!is_copybreak && need_swap)
1452 swap_buffer(data, pkt_len);
1454 /* Extract the enhanced buffer descriptor */
1456 if (fep->bufdesc_ex)
1457 ebdp = (struct bufdesc_ex *)bdp;
1459 /* If this is a VLAN packet remove the VLAN Tag */
1460 vlan_packet_rcvd = false;
1461 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1462 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1463 /* Push and remove the vlan tag */
1464 struct vlan_hdr *vlan_header =
1465 (struct vlan_hdr *) (data + ETH_HLEN);
1466 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1468 vlan_packet_rcvd = true;
1470 memmove(skb->data + VLAN_HLEN, data, ETH_ALEN * 2);
1471 skb_pull(skb, VLAN_HLEN);
1474 skb->protocol = eth_type_trans(skb, ndev);
1476 /* Get receive timestamp from the skb */
1477 if (fep->hwts_rx_en && fep->bufdesc_ex)
1478 fec_enet_hwtstamp(fep, ebdp->ts,
1479 skb_hwtstamps(skb));
1481 if (fep->bufdesc_ex &&
1482 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1483 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1484 /* don't check it */
1485 skb->ip_summed = CHECKSUM_UNNECESSARY;
1487 skb_checksum_none_assert(skb);
1491 /* Handle received VLAN packets */
1492 if (vlan_packet_rcvd)
1493 __vlan_hwaccel_put_tag(skb,
1497 napi_gro_receive(&fep->napi, skb);
1500 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1501 FEC_ENET_RX_FRSIZE - fep->rx_align,
1504 rxq->rx_skbuff[index] = skb_new;
1505 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1509 /* Clear the status flags for this buffer */
1510 status &= ~BD_ENET_RX_STATS;
1512 /* Mark the buffer empty */
1513 status |= BD_ENET_RX_EMPTY;
1514 bdp->cbd_sc = status;
1516 if (fep->bufdesc_ex) {
1517 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1519 ebdp->cbd_esc = BD_ENET_RX_INT;
1524 /* Update BD pointer to next entry */
1525 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1527 /* Doing this here will keep the FEC running while we process
1528 * incoming frames. On a heavily loaded network, we should be
1529 * able to keep up at the expense of system resources.
1531 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1534 return pkt_received;
1538 fec_enet_rx(struct net_device *ndev, int budget)
1540 int pkt_received = 0;
1542 struct fec_enet_private *fep = netdev_priv(ndev);
1544 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1545 clear_bit(queue_id, &fep->work_rx);
1546 pkt_received += fec_enet_rx_queue(ndev,
1547 budget - pkt_received, queue_id);
1549 return pkt_received;
1553 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1555 if (int_events == 0)
1558 if (int_events & FEC_ENET_RXF)
1559 fep->work_rx |= (1 << 2);
1560 if (int_events & FEC_ENET_RXF_1)
1561 fep->work_rx |= (1 << 0);
1562 if (int_events & FEC_ENET_RXF_2)
1563 fep->work_rx |= (1 << 1);
1565 if (int_events & FEC_ENET_TXF)
1566 fep->work_tx |= (1 << 2);
1567 if (int_events & FEC_ENET_TXF_1)
1568 fep->work_tx |= (1 << 0);
1569 if (int_events & FEC_ENET_TXF_2)
1570 fep->work_tx |= (1 << 1);
1576 fec_enet_interrupt(int irq, void *dev_id)
1578 struct net_device *ndev = dev_id;
1579 struct fec_enet_private *fep = netdev_priv(ndev);
1581 irqreturn_t ret = IRQ_NONE;
1583 int_events = readl(fep->hwp + FEC_IEVENT);
1584 writel(int_events, fep->hwp + FEC_IEVENT);
1585 fec_enet_collect_events(fep, int_events);
1587 if ((fep->work_tx || fep->work_rx) && fep->link) {
1590 if (napi_schedule_prep(&fep->napi)) {
1591 /* Disable the NAPI interrupts */
1592 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1593 __napi_schedule(&fep->napi);
1597 if (int_events & FEC_ENET_MII) {
1599 complete(&fep->mdio_done);
1603 fec_ptp_check_pps_event(fep);
1608 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1610 struct net_device *ndev = napi->dev;
1611 struct fec_enet_private *fep = netdev_priv(ndev);
1614 pkts = fec_enet_rx(ndev, budget);
1618 if (pkts < budget) {
1619 napi_complete(napi);
1620 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1625 /* ------------------------------------------------------------------------- */
1626 static void fec_get_mac(struct net_device *ndev)
1628 struct fec_enet_private *fep = netdev_priv(ndev);
1629 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1630 unsigned char *iap, tmpaddr[ETH_ALEN];
1633 * try to get mac address in following order:
1635 * 1) module parameter via kernel command line in form
1636 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1641 * 2) from device tree data
1643 if (!is_valid_ether_addr(iap)) {
1644 struct device_node *np = fep->pdev->dev.of_node;
1646 const char *mac = of_get_mac_address(np);
1648 iap = (unsigned char *) mac;
1653 * 3) from flash or fuse (via platform data)
1655 if (!is_valid_ether_addr(iap)) {
1658 iap = (unsigned char *)FEC_FLASHMAC;
1661 iap = (unsigned char *)&pdata->mac;
1666 * 4) FEC mac registers set by bootloader
1668 if (!is_valid_ether_addr(iap)) {
1669 *((__be32 *) &tmpaddr[0]) =
1670 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1671 *((__be16 *) &tmpaddr[4]) =
1672 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1677 * 5) random mac address
1679 if (!is_valid_ether_addr(iap)) {
1680 /* Report it and use a random ethernet address instead */
1681 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1682 eth_hw_addr_random(ndev);
1683 netdev_info(ndev, "Using random MAC address: %pM\n",
1688 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1690 /* Adjust MAC if using macaddr */
1692 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1695 /* ------------------------------------------------------------------------- */
1700 static void fec_enet_adjust_link(struct net_device *ndev)
1702 struct fec_enet_private *fep = netdev_priv(ndev);
1703 struct phy_device *phy_dev = fep->phy_dev;
1704 int status_change = 0;
1706 /* Prevent a state halted on mii error */
1707 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1708 phy_dev->state = PHY_RESUMING;
1713 * If the netdev is down, or is going down, we're not interested
1714 * in link state events, so just mark our idea of the link as down
1715 * and ignore the event.
1717 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1719 } else if (phy_dev->link) {
1721 fep->link = phy_dev->link;
1725 if (fep->full_duplex != phy_dev->duplex) {
1726 fep->full_duplex = phy_dev->duplex;
1730 if (phy_dev->speed != fep->speed) {
1731 fep->speed = phy_dev->speed;
1735 /* if any of the above changed restart the FEC */
1736 if (status_change) {
1737 napi_disable(&fep->napi);
1738 netif_tx_lock_bh(ndev);
1740 netif_wake_queue(ndev);
1741 netif_tx_unlock_bh(ndev);
1742 napi_enable(&fep->napi);
1746 napi_disable(&fep->napi);
1747 netif_tx_lock_bh(ndev);
1749 netif_tx_unlock_bh(ndev);
1750 napi_enable(&fep->napi);
1751 fep->link = phy_dev->link;
1757 phy_print_status(phy_dev);
1760 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1762 struct fec_enet_private *fep = bus->priv;
1763 unsigned long time_left;
1765 fep->mii_timeout = 0;
1766 init_completion(&fep->mdio_done);
1768 /* start a read op */
1769 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1770 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1771 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1773 /* wait for end of transfer */
1774 time_left = wait_for_completion_timeout(&fep->mdio_done,
1775 usecs_to_jiffies(FEC_MII_TIMEOUT));
1776 if (time_left == 0) {
1777 fep->mii_timeout = 1;
1778 netdev_err(fep->netdev, "MDIO read timeout\n");
1783 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1786 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1789 struct fec_enet_private *fep = bus->priv;
1790 unsigned long time_left;
1792 fep->mii_timeout = 0;
1793 init_completion(&fep->mdio_done);
1795 /* start a write op */
1796 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1797 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1798 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1799 fep->hwp + FEC_MII_DATA);
1801 /* wait for end of transfer */
1802 time_left = wait_for_completion_timeout(&fep->mdio_done,
1803 usecs_to_jiffies(FEC_MII_TIMEOUT));
1804 if (time_left == 0) {
1805 fep->mii_timeout = 1;
1806 netdev_err(fep->netdev, "MDIO write timeout\n");
1813 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1815 struct fec_enet_private *fep = netdev_priv(ndev);
1819 ret = clk_prepare_enable(fep->clk_ahb);
1822 ret = clk_prepare_enable(fep->clk_ipg);
1824 goto failed_clk_ipg;
1825 if (fep->clk_enet_out) {
1826 ret = clk_prepare_enable(fep->clk_enet_out);
1828 goto failed_clk_enet_out;
1831 mutex_lock(&fep->ptp_clk_mutex);
1832 ret = clk_prepare_enable(fep->clk_ptp);
1834 mutex_unlock(&fep->ptp_clk_mutex);
1835 goto failed_clk_ptp;
1837 fep->ptp_clk_on = true;
1839 mutex_unlock(&fep->ptp_clk_mutex);
1842 ret = clk_prepare_enable(fep->clk_ref);
1844 goto failed_clk_ref;
1847 clk_disable_unprepare(fep->clk_ahb);
1848 clk_disable_unprepare(fep->clk_ipg);
1849 if (fep->clk_enet_out)
1850 clk_disable_unprepare(fep->clk_enet_out);
1852 mutex_lock(&fep->ptp_clk_mutex);
1853 clk_disable_unprepare(fep->clk_ptp);
1854 fep->ptp_clk_on = false;
1855 mutex_unlock(&fep->ptp_clk_mutex);
1858 clk_disable_unprepare(fep->clk_ref);
1865 clk_disable_unprepare(fep->clk_ref);
1867 if (fep->clk_enet_out)
1868 clk_disable_unprepare(fep->clk_enet_out);
1869 failed_clk_enet_out:
1870 clk_disable_unprepare(fep->clk_ipg);
1872 clk_disable_unprepare(fep->clk_ahb);
1877 static int fec_enet_mii_probe(struct net_device *ndev)
1879 struct fec_enet_private *fep = netdev_priv(ndev);
1880 struct phy_device *phy_dev = NULL;
1881 char mdio_bus_id[MII_BUS_ID_SIZE];
1882 char phy_name[MII_BUS_ID_SIZE + 3];
1884 int dev_id = fep->dev_id;
1886 fep->phy_dev = NULL;
1888 if (fep->phy_node) {
1889 phy_dev = of_phy_connect(ndev, fep->phy_node,
1890 &fec_enet_adjust_link, 0,
1891 fep->phy_interface);
1895 /* check for attached phy */
1896 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1897 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1899 if (fep->mii_bus->phy_map[phy_id] == NULL)
1901 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1905 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1909 if (phy_id >= PHY_MAX_ADDR) {
1910 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1911 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1915 snprintf(phy_name, sizeof(phy_name),
1916 PHY_ID_FMT, mdio_bus_id, phy_id);
1917 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1918 fep->phy_interface);
1921 if (IS_ERR(phy_dev)) {
1922 netdev_err(ndev, "could not attach to PHY\n");
1923 return PTR_ERR(phy_dev);
1926 /* mask with MAC supported features */
1927 if (fep->quirks & FEC_QUIRK_HAS_GBIT) {
1928 phy_dev->supported &= PHY_GBIT_FEATURES;
1929 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1930 #if !defined(CONFIG_M5272)
1931 phy_dev->supported |= SUPPORTED_Pause;
1935 phy_dev->supported &= PHY_BASIC_FEATURES;
1937 phy_dev->advertising = phy_dev->supported;
1939 fep->phy_dev = phy_dev;
1941 fep->full_duplex = 0;
1943 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1944 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1950 static int fec_enet_mii_init(struct platform_device *pdev)
1952 static struct mii_bus *fec0_mii_bus;
1953 struct net_device *ndev = platform_get_drvdata(pdev);
1954 struct fec_enet_private *fep = netdev_priv(ndev);
1955 struct device_node *node;
1956 int err = -ENXIO, i;
1959 * The i.MX28 dual fec interfaces are not equal.
1960 * Here are the differences:
1962 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1963 * - fec0 acts as the 1588 time master while fec1 is slave
1964 * - external phys can only be configured by fec0
1966 * That is to say fec1 can not work independently. It only works
1967 * when fec0 is working. The reason behind this design is that the
1968 * second interface is added primarily for Switch mode.
1970 * Because of the last point above, both phys are attached on fec0
1971 * mdio interface in board design, and need to be configured by
1974 if ((fep->quirks & FEC_QUIRK_SINGLE_MDIO) && fep->dev_id > 0) {
1975 /* fec1 uses fec0 mii_bus */
1976 if (mii_cnt && fec0_mii_bus) {
1977 fep->mii_bus = fec0_mii_bus;
1984 fep->mii_timeout = 0;
1987 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1989 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1990 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1991 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1994 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
1995 if (fep->quirks & FEC_QUIRK_ENET_MAC)
1997 fep->phy_speed <<= 1;
1998 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2000 fep->mii_bus = mdiobus_alloc();
2001 if (fep->mii_bus == NULL) {
2006 fep->mii_bus->name = "fec_enet_mii_bus";
2007 fep->mii_bus->read = fec_enet_mdio_read;
2008 fep->mii_bus->write = fec_enet_mdio_write;
2009 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2010 pdev->name, fep->dev_id + 1);
2011 fep->mii_bus->priv = fep;
2012 fep->mii_bus->parent = &pdev->dev;
2014 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2015 if (!fep->mii_bus->irq) {
2017 goto err_out_free_mdiobus;
2020 for (i = 0; i < PHY_MAX_ADDR; i++)
2021 fep->mii_bus->irq[i] = PHY_POLL;
2023 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2025 err = of_mdiobus_register(fep->mii_bus, node);
2028 err = mdiobus_register(fep->mii_bus);
2032 goto err_out_free_mdio_irq;
2036 /* save fec0 mii_bus */
2037 if (fep->quirks & FEC_QUIRK_SINGLE_MDIO)
2038 fec0_mii_bus = fep->mii_bus;
2042 err_out_free_mdio_irq:
2043 kfree(fep->mii_bus->irq);
2044 err_out_free_mdiobus:
2045 mdiobus_free(fep->mii_bus);
2050 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2052 if (--mii_cnt == 0) {
2053 mdiobus_unregister(fep->mii_bus);
2054 kfree(fep->mii_bus->irq);
2055 mdiobus_free(fep->mii_bus);
2059 static int fec_enet_get_settings(struct net_device *ndev,
2060 struct ethtool_cmd *cmd)
2062 struct fec_enet_private *fep = netdev_priv(ndev);
2063 struct phy_device *phydev = fep->phy_dev;
2068 return phy_ethtool_gset(phydev, cmd);
2071 static int fec_enet_set_settings(struct net_device *ndev,
2072 struct ethtool_cmd *cmd)
2074 struct fec_enet_private *fep = netdev_priv(ndev);
2075 struct phy_device *phydev = fep->phy_dev;
2080 return phy_ethtool_sset(phydev, cmd);
2083 static void fec_enet_get_drvinfo(struct net_device *ndev,
2084 struct ethtool_drvinfo *info)
2086 struct fec_enet_private *fep = netdev_priv(ndev);
2088 strlcpy(info->driver, fep->pdev->dev.driver->name,
2089 sizeof(info->driver));
2090 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2091 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2094 static int fec_enet_get_ts_info(struct net_device *ndev,
2095 struct ethtool_ts_info *info)
2097 struct fec_enet_private *fep = netdev_priv(ndev);
2099 if (fep->bufdesc_ex) {
2101 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2102 SOF_TIMESTAMPING_RX_SOFTWARE |
2103 SOF_TIMESTAMPING_SOFTWARE |
2104 SOF_TIMESTAMPING_TX_HARDWARE |
2105 SOF_TIMESTAMPING_RX_HARDWARE |
2106 SOF_TIMESTAMPING_RAW_HARDWARE;
2108 info->phc_index = ptp_clock_index(fep->ptp_clock);
2110 info->phc_index = -1;
2112 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2113 (1 << HWTSTAMP_TX_ON);
2115 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2116 (1 << HWTSTAMP_FILTER_ALL);
2119 return ethtool_op_get_ts_info(ndev, info);
2123 #if !defined(CONFIG_M5272)
2125 static void fec_enet_get_pauseparam(struct net_device *ndev,
2126 struct ethtool_pauseparam *pause)
2128 struct fec_enet_private *fep = netdev_priv(ndev);
2130 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2131 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2132 pause->rx_pause = pause->tx_pause;
2135 static int fec_enet_set_pauseparam(struct net_device *ndev,
2136 struct ethtool_pauseparam *pause)
2138 struct fec_enet_private *fep = netdev_priv(ndev);
2143 if (pause->tx_pause != pause->rx_pause) {
2145 "hardware only support enable/disable both tx and rx");
2149 fep->pause_flag = 0;
2151 /* tx pause must be same as rx pause */
2152 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2153 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2155 if (pause->rx_pause || pause->autoneg) {
2156 fep->phy_dev->supported |= ADVERTISED_Pause;
2157 fep->phy_dev->advertising |= ADVERTISED_Pause;
2159 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2160 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2163 if (pause->autoneg) {
2164 if (netif_running(ndev))
2166 phy_start_aneg(fep->phy_dev);
2168 if (netif_running(ndev)) {
2169 napi_disable(&fep->napi);
2170 netif_tx_lock_bh(ndev);
2172 netif_wake_queue(ndev);
2173 netif_tx_unlock_bh(ndev);
2174 napi_enable(&fep->napi);
2180 static const struct fec_stat {
2181 char name[ETH_GSTRING_LEN];
2185 { "tx_dropped", RMON_T_DROP },
2186 { "tx_packets", RMON_T_PACKETS },
2187 { "tx_broadcast", RMON_T_BC_PKT },
2188 { "tx_multicast", RMON_T_MC_PKT },
2189 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2190 { "tx_undersize", RMON_T_UNDERSIZE },
2191 { "tx_oversize", RMON_T_OVERSIZE },
2192 { "tx_fragment", RMON_T_FRAG },
2193 { "tx_jabber", RMON_T_JAB },
2194 { "tx_collision", RMON_T_COL },
2195 { "tx_64byte", RMON_T_P64 },
2196 { "tx_65to127byte", RMON_T_P65TO127 },
2197 { "tx_128to255byte", RMON_T_P128TO255 },
2198 { "tx_256to511byte", RMON_T_P256TO511 },
2199 { "tx_512to1023byte", RMON_T_P512TO1023 },
2200 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2201 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2202 { "tx_octets", RMON_T_OCTETS },
2205 { "IEEE_tx_drop", IEEE_T_DROP },
2206 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2207 { "IEEE_tx_1col", IEEE_T_1COL },
2208 { "IEEE_tx_mcol", IEEE_T_MCOL },
2209 { "IEEE_tx_def", IEEE_T_DEF },
2210 { "IEEE_tx_lcol", IEEE_T_LCOL },
2211 { "IEEE_tx_excol", IEEE_T_EXCOL },
2212 { "IEEE_tx_macerr", IEEE_T_MACERR },
2213 { "IEEE_tx_cserr", IEEE_T_CSERR },
2214 { "IEEE_tx_sqe", IEEE_T_SQE },
2215 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2216 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2219 { "rx_packets", RMON_R_PACKETS },
2220 { "rx_broadcast", RMON_R_BC_PKT },
2221 { "rx_multicast", RMON_R_MC_PKT },
2222 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2223 { "rx_undersize", RMON_R_UNDERSIZE },
2224 { "rx_oversize", RMON_R_OVERSIZE },
2225 { "rx_fragment", RMON_R_FRAG },
2226 { "rx_jabber", RMON_R_JAB },
2227 { "rx_64byte", RMON_R_P64 },
2228 { "rx_65to127byte", RMON_R_P65TO127 },
2229 { "rx_128to255byte", RMON_R_P128TO255 },
2230 { "rx_256to511byte", RMON_R_P256TO511 },
2231 { "rx_512to1023byte", RMON_R_P512TO1023 },
2232 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2233 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2234 { "rx_octets", RMON_R_OCTETS },
2237 { "IEEE_rx_drop", IEEE_R_DROP },
2238 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2239 { "IEEE_rx_crc", IEEE_R_CRC },
2240 { "IEEE_rx_align", IEEE_R_ALIGN },
2241 { "IEEE_rx_macerr", IEEE_R_MACERR },
2242 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2243 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2246 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2247 struct ethtool_stats *stats, u64 *data)
2249 struct fec_enet_private *fep = netdev_priv(dev);
2252 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2253 data[i] = readl(fep->hwp + fec_stats[i].offset);
2256 static void fec_enet_get_strings(struct net_device *netdev,
2257 u32 stringset, u8 *data)
2260 switch (stringset) {
2262 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2263 memcpy(data + i * ETH_GSTRING_LEN,
2264 fec_stats[i].name, ETH_GSTRING_LEN);
2269 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2273 return ARRAY_SIZE(fec_stats);
2278 #endif /* !defined(CONFIG_M5272) */
2280 static int fec_enet_nway_reset(struct net_device *dev)
2282 struct fec_enet_private *fep = netdev_priv(dev);
2283 struct phy_device *phydev = fep->phy_dev;
2288 return genphy_restart_aneg(phydev);
2291 /* ITR clock source is enet system clock (clk_ahb).
2292 * TCTT unit is cycle_ns * 64 cycle
2293 * So, the ICTT value = X us / (cycle_ns * 64)
2295 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2297 struct fec_enet_private *fep = netdev_priv(ndev);
2299 return us * (fep->itr_clk_rate / 64000) / 1000;
2302 /* Set threshold for interrupt coalescing */
2303 static void fec_enet_itr_coal_set(struct net_device *ndev)
2305 struct fec_enet_private *fep = netdev_priv(ndev);
2308 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2311 /* Must be greater than zero to avoid unpredictable behavior */
2312 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2313 !fep->tx_time_itr || !fep->tx_pkts_itr)
2316 /* Select enet system clock as Interrupt Coalescing
2317 * timer Clock Source
2319 rx_itr = FEC_ITR_CLK_SEL;
2320 tx_itr = FEC_ITR_CLK_SEL;
2322 /* set ICFT and ICTT */
2323 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2324 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2325 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2326 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2328 rx_itr |= FEC_ITR_EN;
2329 tx_itr |= FEC_ITR_EN;
2331 writel(tx_itr, fep->hwp + FEC_TXIC0);
2332 writel(rx_itr, fep->hwp + FEC_RXIC0);
2333 writel(tx_itr, fep->hwp + FEC_TXIC1);
2334 writel(rx_itr, fep->hwp + FEC_RXIC1);
2335 writel(tx_itr, fep->hwp + FEC_TXIC2);
2336 writel(rx_itr, fep->hwp + FEC_RXIC2);
2340 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2342 struct fec_enet_private *fep = netdev_priv(ndev);
2344 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2347 ec->rx_coalesce_usecs = fep->rx_time_itr;
2348 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2350 ec->tx_coalesce_usecs = fep->tx_time_itr;
2351 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2357 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2359 struct fec_enet_private *fep = netdev_priv(ndev);
2362 if (!(fep->quirks & FEC_QUIRK_HAS_AVB))
2365 if (ec->rx_max_coalesced_frames > 255) {
2366 pr_err("Rx coalesced frames exceed hardware limiation");
2370 if (ec->tx_max_coalesced_frames > 255) {
2371 pr_err("Tx coalesced frame exceed hardware limiation");
2375 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2376 if (cycle > 0xFFFF) {
2377 pr_err("Rx coalesed usec exceeed hardware limiation");
2381 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2382 if (cycle > 0xFFFF) {
2383 pr_err("Rx coalesed usec exceeed hardware limiation");
2387 fep->rx_time_itr = ec->rx_coalesce_usecs;
2388 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2390 fep->tx_time_itr = ec->tx_coalesce_usecs;
2391 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2393 fec_enet_itr_coal_set(ndev);
2398 static void fec_enet_itr_coal_init(struct net_device *ndev)
2400 struct ethtool_coalesce ec;
2402 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2403 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2405 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2406 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2408 fec_enet_set_coalesce(ndev, &ec);
2411 static int fec_enet_get_tunable(struct net_device *netdev,
2412 const struct ethtool_tunable *tuna,
2415 struct fec_enet_private *fep = netdev_priv(netdev);
2419 case ETHTOOL_RX_COPYBREAK:
2420 *(u32 *)data = fep->rx_copybreak;
2430 static int fec_enet_set_tunable(struct net_device *netdev,
2431 const struct ethtool_tunable *tuna,
2434 struct fec_enet_private *fep = netdev_priv(netdev);
2438 case ETHTOOL_RX_COPYBREAK:
2439 fep->rx_copybreak = *(u32 *)data;
2450 fec_enet_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2452 struct fec_enet_private *fep = netdev_priv(ndev);
2454 if (fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET) {
2455 wol->supported = WAKE_MAGIC;
2456 wol->wolopts = fep->wol_flag & FEC_WOL_FLAG_ENABLE ? WAKE_MAGIC : 0;
2458 wol->supported = wol->wolopts = 0;
2463 fec_enet_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2465 struct fec_enet_private *fep = netdev_priv(ndev);
2467 if (!(fep->wol_flag & FEC_WOL_HAS_MAGIC_PACKET))
2470 if (wol->wolopts & ~WAKE_MAGIC)
2473 device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
2474 if (device_may_wakeup(&ndev->dev)) {
2475 fep->wol_flag |= FEC_WOL_FLAG_ENABLE;
2476 if (fep->irq[0] > 0)
2477 enable_irq_wake(fep->irq[0]);
2479 fep->wol_flag &= (~FEC_WOL_FLAG_ENABLE);
2480 if (fep->irq[0] > 0)
2481 disable_irq_wake(fep->irq[0]);
2487 static const struct ethtool_ops fec_enet_ethtool_ops = {
2488 .get_settings = fec_enet_get_settings,
2489 .set_settings = fec_enet_set_settings,
2490 .get_drvinfo = fec_enet_get_drvinfo,
2491 .nway_reset = fec_enet_nway_reset,
2492 .get_link = ethtool_op_get_link,
2493 .get_coalesce = fec_enet_get_coalesce,
2494 .set_coalesce = fec_enet_set_coalesce,
2495 #ifndef CONFIG_M5272
2496 .get_pauseparam = fec_enet_get_pauseparam,
2497 .set_pauseparam = fec_enet_set_pauseparam,
2498 .get_strings = fec_enet_get_strings,
2499 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2500 .get_sset_count = fec_enet_get_sset_count,
2502 .get_ts_info = fec_enet_get_ts_info,
2503 .get_tunable = fec_enet_get_tunable,
2504 .set_tunable = fec_enet_set_tunable,
2505 .get_wol = fec_enet_get_wol,
2506 .set_wol = fec_enet_set_wol,
2509 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2511 struct fec_enet_private *fep = netdev_priv(ndev);
2512 struct phy_device *phydev = fep->phy_dev;
2514 if (!netif_running(ndev))
2520 if (fep->bufdesc_ex) {
2521 if (cmd == SIOCSHWTSTAMP)
2522 return fec_ptp_set(ndev, rq);
2523 if (cmd == SIOCGHWTSTAMP)
2524 return fec_ptp_get(ndev, rq);
2527 return phy_mii_ioctl(phydev, rq, cmd);
2530 static void fec_enet_free_buffers(struct net_device *ndev)
2532 struct fec_enet_private *fep = netdev_priv(ndev);
2534 struct sk_buff *skb;
2535 struct bufdesc *bdp;
2536 struct fec_enet_priv_tx_q *txq;
2537 struct fec_enet_priv_rx_q *rxq;
2540 for (q = 0; q < fep->num_rx_queues; q++) {
2541 rxq = fep->rx_queue[q];
2542 bdp = rxq->rx_bd_base;
2543 for (i = 0; i < rxq->rx_ring_size; i++) {
2544 skb = rxq->rx_skbuff[i];
2545 rxq->rx_skbuff[i] = NULL;
2547 dma_unmap_single(&fep->pdev->dev,
2549 FEC_ENET_RX_FRSIZE - fep->rx_align,
2553 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2557 for (q = 0; q < fep->num_tx_queues; q++) {
2558 txq = fep->tx_queue[q];
2559 bdp = txq->tx_bd_base;
2560 for (i = 0; i < txq->tx_ring_size; i++) {
2561 kfree(txq->tx_bounce[i]);
2562 txq->tx_bounce[i] = NULL;
2563 skb = txq->tx_skbuff[i];
2564 txq->tx_skbuff[i] = NULL;
2570 static void fec_enet_free_queue(struct net_device *ndev)
2572 struct fec_enet_private *fep = netdev_priv(ndev);
2574 struct fec_enet_priv_tx_q *txq;
2576 for (i = 0; i < fep->num_tx_queues; i++)
2577 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2578 txq = fep->tx_queue[i];
2579 dma_free_coherent(NULL,
2580 txq->tx_ring_size * TSO_HEADER_SIZE,
2585 for (i = 0; i < fep->num_rx_queues; i++)
2586 kfree(fep->rx_queue[i]);
2587 for (i = 0; i < fep->num_tx_queues; i++)
2588 kfree(fep->tx_queue[i]);
2591 static int fec_enet_alloc_queue(struct net_device *ndev)
2593 struct fec_enet_private *fep = netdev_priv(ndev);
2596 struct fec_enet_priv_tx_q *txq;
2598 for (i = 0; i < fep->num_tx_queues; i++) {
2599 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2605 fep->tx_queue[i] = txq;
2606 txq->tx_ring_size = TX_RING_SIZE;
2607 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2609 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2610 txq->tx_wake_threshold =
2611 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2613 txq->tso_hdrs = dma_alloc_coherent(NULL,
2614 txq->tx_ring_size * TSO_HEADER_SIZE,
2617 if (!txq->tso_hdrs) {
2623 for (i = 0; i < fep->num_rx_queues; i++) {
2624 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2626 if (!fep->rx_queue[i]) {
2631 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2632 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2637 fec_enet_free_queue(ndev);
2642 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2644 struct fec_enet_private *fep = netdev_priv(ndev);
2646 struct sk_buff *skb;
2647 struct bufdesc *bdp;
2648 struct fec_enet_priv_rx_q *rxq;
2650 rxq = fep->rx_queue[queue];
2651 bdp = rxq->rx_bd_base;
2652 for (i = 0; i < rxq->rx_ring_size; i++) {
2653 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2657 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2662 rxq->rx_skbuff[i] = skb;
2663 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2665 if (fep->bufdesc_ex) {
2666 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2667 ebdp->cbd_esc = BD_ENET_RX_INT;
2670 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2673 /* Set the last buffer to wrap. */
2674 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2675 bdp->cbd_sc |= BD_SC_WRAP;
2679 fec_enet_free_buffers(ndev);
2684 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2686 struct fec_enet_private *fep = netdev_priv(ndev);
2688 struct bufdesc *bdp;
2689 struct fec_enet_priv_tx_q *txq;
2691 txq = fep->tx_queue[queue];
2692 bdp = txq->tx_bd_base;
2693 for (i = 0; i < txq->tx_ring_size; i++) {
2694 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2695 if (!txq->tx_bounce[i])
2699 bdp->cbd_bufaddr = 0;
2701 if (fep->bufdesc_ex) {
2702 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2703 ebdp->cbd_esc = BD_ENET_TX_INT;
2706 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2709 /* Set the last buffer to wrap. */
2710 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2711 bdp->cbd_sc |= BD_SC_WRAP;
2716 fec_enet_free_buffers(ndev);
2720 static int fec_enet_alloc_buffers(struct net_device *ndev)
2722 struct fec_enet_private *fep = netdev_priv(ndev);
2725 for (i = 0; i < fep->num_rx_queues; i++)
2726 if (fec_enet_alloc_rxq_buffers(ndev, i))
2729 for (i = 0; i < fep->num_tx_queues; i++)
2730 if (fec_enet_alloc_txq_buffers(ndev, i))
2736 fec_enet_open(struct net_device *ndev)
2738 struct fec_enet_private *fep = netdev_priv(ndev);
2741 pinctrl_pm_select_default_state(&fep->pdev->dev);
2742 ret = fec_enet_clk_enable(ndev, true);
2746 /* I should reset the ring buffers here, but I don't yet know
2747 * a simple way to do that.
2750 ret = fec_enet_alloc_buffers(ndev);
2752 goto err_enet_alloc;
2754 /* Probe and connect to PHY when open the interface */
2755 ret = fec_enet_mii_probe(ndev);
2757 goto err_enet_mii_probe;
2760 napi_enable(&fep->napi);
2761 phy_start(fep->phy_dev);
2762 netif_tx_start_all_queues(ndev);
2764 device_set_wakeup_enable(&ndev->dev, fep->wol_flag &
2765 FEC_WOL_FLAG_ENABLE);
2770 fec_enet_free_buffers(ndev);
2772 fec_enet_clk_enable(ndev, false);
2773 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2778 fec_enet_close(struct net_device *ndev)
2780 struct fec_enet_private *fep = netdev_priv(ndev);
2782 phy_stop(fep->phy_dev);
2784 if (netif_device_present(ndev)) {
2785 napi_disable(&fep->napi);
2786 netif_tx_disable(ndev);
2790 phy_disconnect(fep->phy_dev);
2791 fep->phy_dev = NULL;
2793 fec_enet_clk_enable(ndev, false);
2794 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2795 fec_enet_free_buffers(ndev);
2800 /* Set or clear the multicast filter for this adaptor.
2801 * Skeleton taken from sunlance driver.
2802 * The CPM Ethernet implementation allows Multicast as well as individual
2803 * MAC address filtering. Some of the drivers check to make sure it is
2804 * a group multicast address, and discard those that are not. I guess I
2805 * will do the same for now, but just remove the test if you want
2806 * individual filtering as well (do the upper net layers want or support
2807 * this kind of feature?).
2810 #define HASH_BITS 6 /* #bits in hash */
2811 #define CRC32_POLY 0xEDB88320
2813 static void set_multicast_list(struct net_device *ndev)
2815 struct fec_enet_private *fep = netdev_priv(ndev);
2816 struct netdev_hw_addr *ha;
2817 unsigned int i, bit, data, crc, tmp;
2820 if (ndev->flags & IFF_PROMISC) {
2821 tmp = readl(fep->hwp + FEC_R_CNTRL);
2823 writel(tmp, fep->hwp + FEC_R_CNTRL);
2827 tmp = readl(fep->hwp + FEC_R_CNTRL);
2829 writel(tmp, fep->hwp + FEC_R_CNTRL);
2831 if (ndev->flags & IFF_ALLMULTI) {
2832 /* Catch all multicast addresses, so set the
2835 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2836 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2841 /* Clear filter and add the addresses in hash register
2843 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2844 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2846 netdev_for_each_mc_addr(ha, ndev) {
2847 /* calculate crc32 value of mac address */
2850 for (i = 0; i < ndev->addr_len; i++) {
2852 for (bit = 0; bit < 8; bit++, data >>= 1) {
2854 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2858 /* only upper 6 bits (HASH_BITS) are used
2859 * which point to specific bit in he hash registers
2861 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2864 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2865 tmp |= 1 << (hash - 32);
2866 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2868 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2870 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2875 /* Set a MAC change in hardware. */
2877 fec_set_mac_address(struct net_device *ndev, void *p)
2879 struct fec_enet_private *fep = netdev_priv(ndev);
2880 struct sockaddr *addr = p;
2883 if (!is_valid_ether_addr(addr->sa_data))
2884 return -EADDRNOTAVAIL;
2885 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2888 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2889 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2890 fep->hwp + FEC_ADDR_LOW);
2891 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2892 fep->hwp + FEC_ADDR_HIGH);
2896 #ifdef CONFIG_NET_POLL_CONTROLLER
2898 * fec_poll_controller - FEC Poll controller function
2899 * @dev: The FEC network adapter
2901 * Polled functionality used by netconsole and others in non interrupt mode
2904 static void fec_poll_controller(struct net_device *dev)
2907 struct fec_enet_private *fep = netdev_priv(dev);
2909 for (i = 0; i < FEC_IRQ_NUM; i++) {
2910 if (fep->irq[i] > 0) {
2911 disable_irq(fep->irq[i]);
2912 fec_enet_interrupt(fep->irq[i], dev);
2913 enable_irq(fep->irq[i]);
2919 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2920 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2921 netdev_features_t features)
2923 struct fec_enet_private *fep = netdev_priv(netdev);
2924 netdev_features_t changed = features ^ netdev->features;
2926 netdev->features = features;
2928 /* Receive checksum has been changed */
2929 if (changed & NETIF_F_RXCSUM) {
2930 if (features & NETIF_F_RXCSUM)
2931 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2933 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2937 static int fec_set_features(struct net_device *netdev,
2938 netdev_features_t features)
2940 struct fec_enet_private *fep = netdev_priv(netdev);
2941 netdev_features_t changed = features ^ netdev->features;
2943 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2944 napi_disable(&fep->napi);
2945 netif_tx_lock_bh(netdev);
2947 fec_enet_set_netdev_features(netdev, features);
2948 fec_restart(netdev);
2949 netif_tx_wake_all_queues(netdev);
2950 netif_tx_unlock_bh(netdev);
2951 napi_enable(&fep->napi);
2953 fec_enet_set_netdev_features(netdev, features);
2959 static const struct net_device_ops fec_netdev_ops = {
2960 .ndo_open = fec_enet_open,
2961 .ndo_stop = fec_enet_close,
2962 .ndo_start_xmit = fec_enet_start_xmit,
2963 .ndo_set_rx_mode = set_multicast_list,
2964 .ndo_change_mtu = eth_change_mtu,
2965 .ndo_validate_addr = eth_validate_addr,
2966 .ndo_tx_timeout = fec_timeout,
2967 .ndo_set_mac_address = fec_set_mac_address,
2968 .ndo_do_ioctl = fec_enet_ioctl,
2969 #ifdef CONFIG_NET_POLL_CONTROLLER
2970 .ndo_poll_controller = fec_poll_controller,
2972 .ndo_set_features = fec_set_features,
2976 * XXX: We need to clean up on failure exits here.
2979 static int fec_enet_init(struct net_device *ndev)
2981 struct fec_enet_private *fep = netdev_priv(ndev);
2982 struct fec_enet_priv_tx_q *txq;
2983 struct fec_enet_priv_rx_q *rxq;
2984 struct bufdesc *cbd_base;
2989 #if defined(CONFIG_ARM)
2990 fep->rx_align = 0xf;
2991 fep->tx_align = 0xf;
2993 fep->rx_align = 0x3;
2994 fep->tx_align = 0x3;
2997 fec_enet_alloc_queue(ndev);
2999 if (fep->bufdesc_ex)
3000 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3002 fep->bufdesc_size = sizeof(struct bufdesc);
3003 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3006 /* Allocate memory for buffer descriptors. */
3007 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
3013 memset(cbd_base, 0, bd_size);
3015 /* Get the Ethernet address */
3017 /* make sure MAC we just acquired is programmed into the hw */
3018 fec_set_mac_address(ndev, NULL);
3020 /* Set receive and transmit descriptor base. */
3021 for (i = 0; i < fep->num_rx_queues; i++) {
3022 rxq = fep->rx_queue[i];
3024 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3025 rxq->bd_dma = bd_dma;
3026 if (fep->bufdesc_ex) {
3027 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3028 cbd_base = (struct bufdesc *)
3029 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3031 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3032 cbd_base += rxq->rx_ring_size;
3036 for (i = 0; i < fep->num_tx_queues; i++) {
3037 txq = fep->tx_queue[i];
3039 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3040 txq->bd_dma = bd_dma;
3041 if (fep->bufdesc_ex) {
3042 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3043 cbd_base = (struct bufdesc *)
3044 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3046 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3047 cbd_base += txq->tx_ring_size;
3052 /* The FEC Ethernet specific entries in the device structure */
3053 ndev->watchdog_timeo = TX_TIMEOUT;
3054 ndev->netdev_ops = &fec_netdev_ops;
3055 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3057 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3058 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3060 if (fep->quirks & FEC_QUIRK_HAS_VLAN)
3061 /* enable hw VLAN support */
3062 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3064 if (fep->quirks & FEC_QUIRK_HAS_CSUM) {
3065 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3067 /* enable hw accelerator */
3068 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3069 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3070 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3073 if (fep->quirks & FEC_QUIRK_HAS_AVB) {
3075 fep->rx_align = 0x3f;
3078 ndev->hw_features = ndev->features;
3086 static void fec_reset_phy(struct platform_device *pdev)
3090 struct device_node *np = pdev->dev.of_node;
3095 of_property_read_u32(np, "phy-reset-duration", &msec);
3096 /* A sane reset duration should not be longer than 1s */
3100 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3101 if (!gpio_is_valid(phy_reset))
3104 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3105 GPIOF_OUT_INIT_LOW, "phy-reset");
3107 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3111 gpio_set_value(phy_reset, 1);
3113 #else /* CONFIG_OF */
3114 static void fec_reset_phy(struct platform_device *pdev)
3117 * In case of platform probe, the reset has been done
3121 #endif /* CONFIG_OF */
3124 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3126 struct device_node *np = pdev->dev.of_node;
3129 *num_tx = *num_rx = 1;
3131 if (!np || !of_device_is_available(np))
3134 /* parse the num of tx and rx queues */
3135 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3139 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3143 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3144 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3150 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3151 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3160 fec_probe(struct platform_device *pdev)
3162 struct fec_enet_private *fep;
3163 struct fec_platform_data *pdata;
3164 struct net_device *ndev;
3165 int i, irq, ret = 0;
3167 const struct of_device_id *of_id;
3169 struct device_node *np = pdev->dev.of_node, *phy_node;
3173 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3175 /* Init network device */
3176 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3177 num_tx_qs, num_rx_qs);
3181 SET_NETDEV_DEV(ndev, &pdev->dev);
3183 /* setup board info structure */
3184 fep = netdev_priv(ndev);
3186 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3188 pdev->id_entry = of_id->data;
3189 fep->quirks = pdev->id_entry->driver_data;
3192 fep->num_rx_queues = num_rx_qs;
3193 fep->num_tx_queues = num_tx_qs;
3195 #if !defined(CONFIG_M5272)
3196 /* default enable pause frame auto negotiation */
3197 if (fep->quirks & FEC_QUIRK_HAS_GBIT)
3198 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3201 /* Select default pin state */
3202 pinctrl_pm_select_default_state(&pdev->dev);
3204 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3205 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3206 if (IS_ERR(fep->hwp)) {
3207 ret = PTR_ERR(fep->hwp);
3208 goto failed_ioremap;
3212 fep->dev_id = dev_id++;
3214 platform_set_drvdata(pdev, ndev);
3216 if (of_get_property(np, "fsl,magic-packet", NULL))
3217 fep->wol_flag |= FEC_WOL_HAS_MAGIC_PACKET;
3219 phy_node = of_parse_phandle(np, "phy-handle", 0);
3220 if (!phy_node && of_phy_is_fixed_link(np)) {
3221 ret = of_phy_register_fixed_link(np);
3224 "broken fixed-link specification\n");
3227 phy_node = of_node_get(np);
3229 fep->phy_node = phy_node;
3231 ret = of_get_phy_mode(pdev->dev.of_node);
3233 pdata = dev_get_platdata(&pdev->dev);
3235 fep->phy_interface = pdata->phy;
3237 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3239 fep->phy_interface = ret;
3242 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3243 if (IS_ERR(fep->clk_ipg)) {
3244 ret = PTR_ERR(fep->clk_ipg);
3248 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3249 if (IS_ERR(fep->clk_ahb)) {
3250 ret = PTR_ERR(fep->clk_ahb);
3254 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3256 /* enet_out is optional, depends on board */
3257 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3258 if (IS_ERR(fep->clk_enet_out))
3259 fep->clk_enet_out = NULL;
3261 fep->ptp_clk_on = false;
3262 mutex_init(&fep->ptp_clk_mutex);
3264 /* clk_ref is optional, depends on board */
3265 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3266 if (IS_ERR(fep->clk_ref))
3267 fep->clk_ref = NULL;
3269 fep->bufdesc_ex = fep->quirks & FEC_QUIRK_HAS_BUFDESC_EX;
3270 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3271 if (IS_ERR(fep->clk_ptp)) {
3272 fep->clk_ptp = NULL;
3273 fep->bufdesc_ex = false;
3276 ret = fec_enet_clk_enable(ndev, true);
3280 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3281 if (!IS_ERR(fep->reg_phy)) {
3282 ret = regulator_enable(fep->reg_phy);
3285 "Failed to enable phy regulator: %d\n", ret);
3286 goto failed_regulator;
3289 fep->reg_phy = NULL;
3292 fec_reset_phy(pdev);
3294 if (fep->bufdesc_ex)
3297 ret = fec_enet_init(ndev);
3301 for (i = 0; i < FEC_IRQ_NUM; i++) {
3302 irq = platform_get_irq(pdev, i);
3309 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3310 0, pdev->name, ndev);
3317 init_completion(&fep->mdio_done);
3318 ret = fec_enet_mii_init(pdev);
3320 goto failed_mii_init;
3322 /* Carrier starts down, phylib will bring it up */
3323 netif_carrier_off(ndev);
3324 fec_enet_clk_enable(ndev, false);
3325 pinctrl_pm_select_sleep_state(&pdev->dev);
3327 ret = register_netdev(ndev);
3329 goto failed_register;
3331 device_init_wakeup(&ndev->dev, fep->wol_flag &
3332 FEC_WOL_HAS_MAGIC_PACKET);
3334 if (fep->bufdesc_ex && fep->ptp_clock)
3335 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3337 fep->rx_copybreak = COPYBREAK_DEFAULT;
3338 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3342 fec_enet_mii_remove(fep);
3347 regulator_disable(fep->reg_phy);
3349 fec_enet_clk_enable(ndev, false);
3352 of_node_put(phy_node);
3360 fec_drv_remove(struct platform_device *pdev)
3362 struct net_device *ndev = platform_get_drvdata(pdev);
3363 struct fec_enet_private *fep = netdev_priv(ndev);
3365 cancel_delayed_work_sync(&fep->time_keep);
3366 cancel_work_sync(&fep->tx_timeout_work);
3367 unregister_netdev(ndev);
3368 fec_enet_mii_remove(fep);
3370 regulator_disable(fep->reg_phy);
3372 ptp_clock_unregister(fep->ptp_clock);
3373 of_node_put(fep->phy_node);
3379 static int __maybe_unused fec_suspend(struct device *dev)
3381 struct net_device *ndev = dev_get_drvdata(dev);
3382 struct fec_enet_private *fep = netdev_priv(ndev);
3385 if (netif_running(ndev)) {
3386 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE)
3387 fep->wol_flag |= FEC_WOL_FLAG_SLEEP_ON;
3388 phy_stop(fep->phy_dev);
3389 napi_disable(&fep->napi);
3390 netif_tx_lock_bh(ndev);
3391 netif_device_detach(ndev);
3392 netif_tx_unlock_bh(ndev);
3394 fec_enet_clk_enable(ndev, false);
3395 if (!(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3396 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3400 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE))
3401 regulator_disable(fep->reg_phy);
3403 /* SOC supply clock to phy, when clock is disabled, phy link down
3404 * SOC control phy regulator, when regulator is disabled, phy link down
3406 if (fep->clk_enet_out || fep->reg_phy)
3412 static int __maybe_unused fec_resume(struct device *dev)
3414 struct net_device *ndev = dev_get_drvdata(dev);
3415 struct fec_enet_private *fep = netdev_priv(ndev);
3416 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
3420 if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
3421 ret = regulator_enable(fep->reg_phy);
3427 if (netif_running(ndev)) {
3428 ret = fec_enet_clk_enable(ndev, true);
3433 if (fep->wol_flag & FEC_WOL_FLAG_ENABLE) {
3434 if (pdata && pdata->sleep_mode_enable)
3435 pdata->sleep_mode_enable(false);
3436 val = readl(fep->hwp + FEC_ECNTRL);
3437 val &= ~(FEC_ECR_MAGICEN | FEC_ECR_SLEEP);
3438 writel(val, fep->hwp + FEC_ECNTRL);
3439 fep->wol_flag &= ~FEC_WOL_FLAG_SLEEP_ON;
3441 pinctrl_pm_select_default_state(&fep->pdev->dev);
3444 netif_tx_lock_bh(ndev);
3445 netif_device_attach(ndev);
3446 netif_tx_unlock_bh(ndev);
3447 napi_enable(&fep->napi);
3448 phy_start(fep->phy_dev);
3456 regulator_disable(fep->reg_phy);
3460 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3462 static struct platform_driver fec_driver = {
3464 .name = DRIVER_NAME,
3466 .of_match_table = fec_dt_ids,
3468 .id_table = fec_devtype,
3470 .remove = fec_drv_remove,
3473 module_platform_driver(fec_driver);
3475 MODULE_ALIAS("platform:"DRIVER_NAME);
3476 MODULE_LICENSE("GPL");