2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
35 #include <linux/netdevice.h>
36 #include <linux/etherdevice.h>
37 #include <linux/skbuff.h>
38 #include <linux/spinlock.h>
39 #include <linux/workqueue.h>
40 #include <linux/bitops.h>
42 #include <linux/irq.h>
43 #include <linux/clk.h>
44 #include <linux/platform_device.h>
45 #include <linux/phy.h>
46 #include <linux/fec.h>
48 #include <linux/of_device.h>
49 #include <linux/of_gpio.h>
50 #include <linux/of_net.h>
51 #include <linux/pinctrl/consumer.h>
52 #include <linux/regulator/consumer.h>
54 #include <asm/cacheflush.h>
57 #include <asm/coldfire.h>
58 #include <asm/mcfsim.h>
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
66 #define FEC_ALIGNMENT 0x3
69 #define DRIVER_NAME "fec"
70 #define FEC_NAPI_WEIGHT 64
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 static struct platform_device_id fec_devtype[] = {
93 /* keep it for coldfire */
98 .driver_data = FEC_QUIRK_USE_GASKET,
104 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
107 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
108 FEC_QUIRK_HAS_BUFDESC_EX,
113 MODULE_DEVICE_TABLE(platform, fec_devtype);
116 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
117 IMX27_FEC, /* runs on i.mx27/35/51 */
122 static const struct of_device_id fec_dt_ids[] = {
123 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
124 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
125 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
126 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
129 MODULE_DEVICE_TABLE(of, fec_dt_ids);
131 static unsigned char macaddr[ETH_ALEN];
132 module_param_array(macaddr, byte, NULL, 0);
133 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
135 #if defined(CONFIG_M5272)
137 * Some hardware gets it MAC address out of local flash memory.
138 * if this is non-zero then assume it is the address to get MAC from.
140 #if defined(CONFIG_NETtel)
141 #define FEC_FLASHMAC 0xf0006006
142 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
143 #define FEC_FLASHMAC 0xf0006000
144 #elif defined(CONFIG_CANCam)
145 #define FEC_FLASHMAC 0xf0020000
146 #elif defined (CONFIG_M5272C3)
147 #define FEC_FLASHMAC (0xffe04000 + 4)
148 #elif defined(CONFIG_MOD5272)
149 #define FEC_FLASHMAC 0xffc0406b
151 #define FEC_FLASHMAC 0
153 #endif /* CONFIG_M5272 */
155 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
156 #error "FEC: descriptor ring size constants too large"
159 /* Interrupt events/masks. */
160 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
161 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
162 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
163 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
164 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
165 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
166 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
167 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
168 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
169 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
171 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
172 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
174 /* The FEC stores dest/src/type, data, and checksum for receive packets.
176 #define PKT_MAXBUF_SIZE 1518
177 #define PKT_MINBUF_SIZE 64
178 #define PKT_MAXBLR_SIZE 1520
181 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
182 * size bits. Other FEC hardware does not, so we need to take that into
183 * account when setting it.
185 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
186 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
187 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
189 #define OPT_FRAME_SIZE 0
192 /* FEC MII MMFR bits definition */
193 #define FEC_MMFR_ST (1 << 30)
194 #define FEC_MMFR_OP_READ (2 << 28)
195 #define FEC_MMFR_OP_WRITE (1 << 28)
196 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
197 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
198 #define FEC_MMFR_TA (2 << 16)
199 #define FEC_MMFR_DATA(v) (v & 0xffff)
201 #define FEC_MII_TIMEOUT 30000 /* us */
203 /* Transmitter timeout */
204 #define TX_TIMEOUT (2 * HZ)
206 #define FEC_PAUSE_FLAG_AUTONEG 0x1
207 #define FEC_PAUSE_FLAG_ENABLE 0x2
211 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
213 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
215 return (struct bufdesc *)(ex + 1);
220 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
222 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
224 return (struct bufdesc *)(ex - 1);
229 static void *swap_buffer(void *bufaddr, int len)
232 unsigned int *buf = bufaddr;
234 for (i = 0; i < (len + 3) / 4; i++, buf++)
235 *buf = cpu_to_be32(*buf);
241 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
243 struct fec_enet_private *fep = netdev_priv(ndev);
244 const struct platform_device_id *id_entry =
245 platform_get_device_id(fep->pdev);
248 unsigned short status;
252 /* Link is down or autonegotiation is in progress. */
253 return NETDEV_TX_BUSY;
256 /* Fill in a Tx ring entry */
259 status = bdp->cbd_sc;
261 if (status & BD_ENET_TX_READY) {
262 /* Ooops. All transmit buffers are full. Bail out.
263 * This should not happen, since ndev->tbusy should be set.
265 printk("%s: tx queue full!.\n", ndev->name);
266 return NETDEV_TX_BUSY;
269 /* Clear all of the status flags */
270 status &= ~BD_ENET_TX_STATS;
272 /* Set buffer length and buffer pointer */
274 bdp->cbd_datlen = skb->len;
277 * On some FEC implementations data must be aligned on
278 * 4-byte boundaries. Use bounce buffers to copy data
279 * and get it aligned. Ugh.
282 index = (struct bufdesc_ex *)bdp -
283 (struct bufdesc_ex *)fep->tx_bd_base;
285 index = bdp - fep->tx_bd_base;
287 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
288 memcpy(fep->tx_bounce[index], skb->data, skb->len);
289 bufaddr = fep->tx_bounce[index];
293 * Some design made an incorrect assumption on endian mode of
294 * the system that it's running on. As the result, driver has to
295 * swap every frame going to and coming from the controller.
297 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
298 swap_buffer(bufaddr, skb->len);
300 /* Save skb pointer */
301 fep->tx_skbuff[index] = skb;
303 /* Push the data cache so the CPM does not get stale memory
306 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
307 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
309 /* Send it on its way. Tell FEC it's ready, interrupt when done,
310 * it's the last BD of the frame, and to put the CRC on the end.
312 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
313 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
314 bdp->cbd_sc = status;
316 if (fep->bufdesc_ex) {
318 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
320 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
322 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
323 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
326 ebdp->cbd_esc = BD_ENET_TX_INT;
329 /* If this was the last BD in the ring, start at the beginning again. */
330 if (status & BD_ENET_TX_WRAP)
331 bdp = fep->tx_bd_base;
333 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
337 if (fep->cur_tx == fep->dirty_tx)
338 netif_stop_queue(ndev);
340 /* Trigger transmission start */
341 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
343 skb_tx_timestamp(skb);
348 /* This function is called to start or restart the FEC during a link
349 * change. This only happens when switching between half and full
353 fec_restart(struct net_device *ndev, int duplex)
355 struct fec_enet_private *fep = netdev_priv(ndev);
356 const struct platform_device_id *id_entry =
357 platform_get_device_id(fep->pdev);
360 u32 rcntl = OPT_FRAME_SIZE | 0x04;
361 u32 ecntl = 0x2; /* ETHEREN */
363 /* Whack a reset. We should wait for this. */
364 writel(1, fep->hwp + FEC_ECNTRL);
368 * enet-mac reset will reset mac address registers too,
369 * so need to reconfigure it.
371 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
372 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
373 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
374 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
377 /* Clear any outstanding interrupt. */
378 writel(0xffc00000, fep->hwp + FEC_IEVENT);
380 /* Reset all multicast. */
381 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
382 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
384 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
385 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
388 /* Set maximum receive buffer size. */
389 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
391 /* Set receive and transmit descriptor base. */
392 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
394 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
395 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
397 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
398 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
400 fep->cur_rx = fep->rx_bd_base;
402 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
403 if (fep->tx_skbuff[i]) {
404 dev_kfree_skb_any(fep->tx_skbuff[i]);
405 fep->tx_skbuff[i] = NULL;
409 /* Enable MII mode */
412 writel(0x04, fep->hwp + FEC_X_CNTRL);
416 writel(0x0, fep->hwp + FEC_X_CNTRL);
419 fep->full_duplex = duplex;
422 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
425 * The phy interface and speed need to get configured
426 * differently on enet-mac.
428 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
429 /* Enable flow control and length check */
430 rcntl |= 0x40000000 | 0x00000020;
432 /* RGMII, RMII or MII */
433 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
435 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
440 /* 1G, 100M or 10M */
442 if (fep->phy_dev->speed == SPEED_1000)
444 else if (fep->phy_dev->speed == SPEED_100)
450 #ifdef FEC_MIIGSK_ENR
451 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
453 /* disable the gasket and wait */
454 writel(0, fep->hwp + FEC_MIIGSK_ENR);
455 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
459 * configure the gasket:
460 * RMII, 50 MHz, no loopback, no echo
461 * MII, 25 MHz, no loopback, no echo
463 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
464 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
465 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
466 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
467 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
469 /* re-enable the gasket */
470 writel(2, fep->hwp + FEC_MIIGSK_ENR);
475 /* enable pause frame*/
476 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
477 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
478 fep->phy_dev && fep->phy_dev->pause)) {
479 rcntl |= FEC_ENET_FCE;
481 /* set FIFO thresh hold parameter to reduce overrun */
482 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
483 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
484 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
485 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
488 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
490 rcntl &= ~FEC_ENET_FCE;
493 writel(rcntl, fep->hwp + FEC_R_CNTRL);
495 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
496 /* enable ENET endian swap */
498 /* enable ENET store and forward mode */
499 writel(1 << 8, fep->hwp + FEC_X_WMRK);
505 /* And last, enable the transmit and receive processing */
506 writel(ecntl, fep->hwp + FEC_ECNTRL);
507 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
510 fec_ptp_start_cyclecounter(ndev);
512 /* Enable interrupts we wish to service */
513 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
517 fec_stop(struct net_device *ndev)
519 struct fec_enet_private *fep = netdev_priv(ndev);
520 const struct platform_device_id *id_entry =
521 platform_get_device_id(fep->pdev);
522 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
524 /* We cannot expect a graceful transmit stop without link !!! */
526 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
528 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
529 printk("fec_stop : Graceful transmit stop did not complete !\n");
532 /* Whack a reset. We should wait for this. */
533 writel(1, fep->hwp + FEC_ECNTRL);
535 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
536 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
538 /* We have to keep ENET enabled to have MII interrupt stay working */
539 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
540 writel(2, fep->hwp + FEC_ECNTRL);
541 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
547 fec_timeout(struct net_device *ndev)
549 struct fec_enet_private *fep = netdev_priv(ndev);
551 ndev->stats.tx_errors++;
553 fec_restart(ndev, fep->full_duplex);
554 netif_wake_queue(ndev);
558 fec_enet_tx(struct net_device *ndev)
560 struct fec_enet_private *fep;
562 unsigned short status;
566 fep = netdev_priv(ndev);
569 /* get next bdp of dirty_tx */
570 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
571 bdp = fep->tx_bd_base;
573 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
575 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
577 /* current queue is empty */
578 if (bdp == fep->cur_tx)
582 index = (struct bufdesc_ex *)bdp -
583 (struct bufdesc_ex *)fep->tx_bd_base;
585 index = bdp - fep->tx_bd_base;
587 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
588 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
589 bdp->cbd_bufaddr = 0;
591 skb = fep->tx_skbuff[index];
593 /* Check for errors. */
594 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
595 BD_ENET_TX_RL | BD_ENET_TX_UN |
597 ndev->stats.tx_errors++;
598 if (status & BD_ENET_TX_HB) /* No heartbeat */
599 ndev->stats.tx_heartbeat_errors++;
600 if (status & BD_ENET_TX_LC) /* Late collision */
601 ndev->stats.tx_window_errors++;
602 if (status & BD_ENET_TX_RL) /* Retrans limit */
603 ndev->stats.tx_aborted_errors++;
604 if (status & BD_ENET_TX_UN) /* Underrun */
605 ndev->stats.tx_fifo_errors++;
606 if (status & BD_ENET_TX_CSL) /* Carrier lost */
607 ndev->stats.tx_carrier_errors++;
609 ndev->stats.tx_packets++;
612 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
614 struct skb_shared_hwtstamps shhwtstamps;
616 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
618 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
619 spin_lock_irqsave(&fep->tmreg_lock, flags);
620 shhwtstamps.hwtstamp = ns_to_ktime(
621 timecounter_cyc2time(&fep->tc, ebdp->ts));
622 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
623 skb_tstamp_tx(skb, &shhwtstamps);
626 if (status & BD_ENET_TX_READY)
627 printk("HEY! Enet xmit interrupt and TX_READY.\n");
629 /* Deferred means some collisions occurred during transmit,
630 * but we eventually sent the packet OK.
632 if (status & BD_ENET_TX_DEF)
633 ndev->stats.collisions++;
635 /* Free the sk buffer associated with this last transmit */
636 dev_kfree_skb_any(skb);
637 fep->tx_skbuff[index] = NULL;
641 /* Update pointer to next buffer descriptor to be transmitted */
642 if (status & BD_ENET_TX_WRAP)
643 bdp = fep->tx_bd_base;
645 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
647 /* Since we have freed up a buffer, the ring is no longer full
649 if (fep->dirty_tx != fep->cur_tx) {
650 if (netif_queue_stopped(ndev))
651 netif_wake_queue(ndev);
658 /* During a receive, the cur_rx points to the current incoming buffer.
659 * When we update through the ring, if the next incoming buffer has
660 * not been given to the system, we just set the empty indicator,
661 * effectively tossing the packet.
664 fec_enet_rx(struct net_device *ndev, int budget)
666 struct fec_enet_private *fep = netdev_priv(ndev);
667 const struct platform_device_id *id_entry =
668 platform_get_device_id(fep->pdev);
670 unsigned short status;
674 int pkt_received = 0;
680 /* First, grab all of the stats for the incoming packet.
681 * These get messed up if we get called due to a busy condition.
685 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
687 if (pkt_received >= budget)
691 /* Since we have allocated space to hold a complete frame,
692 * the last indicator should be set.
694 if ((status & BD_ENET_RX_LAST) == 0)
695 printk("FEC ENET: rcv is not +last\n");
698 goto rx_processing_done;
700 /* Check for errors. */
701 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
702 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
703 ndev->stats.rx_errors++;
704 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
705 /* Frame too long or too short. */
706 ndev->stats.rx_length_errors++;
708 if (status & BD_ENET_RX_NO) /* Frame alignment */
709 ndev->stats.rx_frame_errors++;
710 if (status & BD_ENET_RX_CR) /* CRC Error */
711 ndev->stats.rx_crc_errors++;
712 if (status & BD_ENET_RX_OV) /* FIFO overrun */
713 ndev->stats.rx_fifo_errors++;
716 /* Report late collisions as a frame error.
717 * On this error, the BD is closed, but we don't know what we
718 * have in the buffer. So, just drop this frame on the floor.
720 if (status & BD_ENET_RX_CL) {
721 ndev->stats.rx_errors++;
722 ndev->stats.rx_frame_errors++;
723 goto rx_processing_done;
726 /* Process the incoming frame. */
727 ndev->stats.rx_packets++;
728 pkt_len = bdp->cbd_datlen;
729 ndev->stats.rx_bytes += pkt_len;
730 data = (__u8*)__va(bdp->cbd_bufaddr);
732 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
733 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
735 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
736 swap_buffer(data, pkt_len);
738 /* This does 16 byte alignment, exactly what we need.
739 * The packet length includes FCS, but we don't want to
740 * include that when passing upstream as it messes up
741 * bridging applications.
743 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
745 if (unlikely(!skb)) {
746 printk("%s: Memory squeeze, dropping packet.\n",
748 ndev->stats.rx_dropped++;
750 skb_reserve(skb, NET_IP_ALIGN);
751 skb_put(skb, pkt_len - 4); /* Make room */
752 skb_copy_to_linear_data(skb, data, pkt_len - 4);
753 skb->protocol = eth_type_trans(skb, ndev);
755 /* Get receive timestamp from the skb */
756 if (fep->hwts_rx_en && fep->bufdesc_ex) {
757 struct skb_shared_hwtstamps *shhwtstamps =
760 struct bufdesc_ex *ebdp =
761 (struct bufdesc_ex *)bdp;
763 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
765 spin_lock_irqsave(&fep->tmreg_lock, flags);
766 shhwtstamps->hwtstamp = ns_to_ktime(
767 timecounter_cyc2time(&fep->tc, ebdp->ts));
768 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
771 if (!skb_defer_rx_timestamp(skb))
772 napi_gro_receive(&fep->napi, skb);
775 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
776 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
778 /* Clear the status flags for this buffer */
779 status &= ~BD_ENET_RX_STATS;
781 /* Mark the buffer empty */
782 status |= BD_ENET_RX_EMPTY;
783 bdp->cbd_sc = status;
785 if (fep->bufdesc_ex) {
786 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
788 ebdp->cbd_esc = BD_ENET_RX_INT;
793 /* Update BD pointer to next entry */
794 if (status & BD_ENET_RX_WRAP)
795 bdp = fep->rx_bd_base;
797 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
798 /* Doing this here will keep the FEC running while we process
799 * incoming frames. On a heavily loaded network, we should be
800 * able to keep up at the expense of system resources.
802 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
810 fec_enet_interrupt(int irq, void *dev_id)
812 struct net_device *ndev = dev_id;
813 struct fec_enet_private *fep = netdev_priv(ndev);
815 irqreturn_t ret = IRQ_NONE;
818 int_events = readl(fep->hwp + FEC_IEVENT);
819 writel(int_events, fep->hwp + FEC_IEVENT);
821 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
824 /* Disable the RX interrupt */
825 if (napi_schedule_prep(&fep->napi)) {
826 writel(FEC_RX_DISABLED_IMASK,
827 fep->hwp + FEC_IMASK);
828 __napi_schedule(&fep->napi);
832 if (int_events & FEC_ENET_MII) {
834 complete(&fep->mdio_done);
836 } while (int_events);
841 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
843 struct net_device *ndev = napi->dev;
844 int pkts = fec_enet_rx(ndev, budget);
845 struct fec_enet_private *fep = netdev_priv(ndev);
851 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
856 /* ------------------------------------------------------------------------- */
857 static void fec_get_mac(struct net_device *ndev)
859 struct fec_enet_private *fep = netdev_priv(ndev);
860 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
861 unsigned char *iap, tmpaddr[ETH_ALEN];
864 * try to get mac address in following order:
866 * 1) module parameter via kernel command line in form
867 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
873 * 2) from device tree data
875 if (!is_valid_ether_addr(iap)) {
876 struct device_node *np = fep->pdev->dev.of_node;
878 const char *mac = of_get_mac_address(np);
880 iap = (unsigned char *) mac;
886 * 3) from flash or fuse (via platform data)
888 if (!is_valid_ether_addr(iap)) {
891 iap = (unsigned char *)FEC_FLASHMAC;
894 iap = (unsigned char *)&pdata->mac;
899 * 4) FEC mac registers set by bootloader
901 if (!is_valid_ether_addr(iap)) {
902 *((unsigned long *) &tmpaddr[0]) =
903 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
904 *((unsigned short *) &tmpaddr[4]) =
905 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
909 memcpy(ndev->dev_addr, iap, ETH_ALEN);
911 /* Adjust MAC if using macaddr */
913 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
916 /* ------------------------------------------------------------------------- */
921 static void fec_enet_adjust_link(struct net_device *ndev)
923 struct fec_enet_private *fep = netdev_priv(ndev);
924 struct phy_device *phy_dev = fep->phy_dev;
927 int status_change = 0;
929 spin_lock_irqsave(&fep->hw_lock, flags);
931 /* Prevent a state halted on mii error */
932 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
933 phy_dev->state = PHY_RESUMING;
937 /* Duplex link change */
939 if (fep->full_duplex != phy_dev->duplex) {
940 fec_restart(ndev, phy_dev->duplex);
941 /* prevent unnecessary second fec_restart() below */
942 fep->link = phy_dev->link;
947 /* Link on or off change */
948 if (phy_dev->link != fep->link) {
949 fep->link = phy_dev->link;
951 fec_restart(ndev, phy_dev->duplex);
958 spin_unlock_irqrestore(&fep->hw_lock, flags);
961 phy_print_status(phy_dev);
964 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
966 struct fec_enet_private *fep = bus->priv;
967 unsigned long time_left;
969 fep->mii_timeout = 0;
970 init_completion(&fep->mdio_done);
972 /* start a read op */
973 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
974 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
975 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
977 /* wait for end of transfer */
978 time_left = wait_for_completion_timeout(&fep->mdio_done,
979 usecs_to_jiffies(FEC_MII_TIMEOUT));
980 if (time_left == 0) {
981 fep->mii_timeout = 1;
982 printk(KERN_ERR "FEC: MDIO read timeout\n");
987 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
990 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
993 struct fec_enet_private *fep = bus->priv;
994 unsigned long time_left;
996 fep->mii_timeout = 0;
997 init_completion(&fep->mdio_done);
999 /* start a write op */
1000 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1001 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1002 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1003 fep->hwp + FEC_MII_DATA);
1005 /* wait for end of transfer */
1006 time_left = wait_for_completion_timeout(&fep->mdio_done,
1007 usecs_to_jiffies(FEC_MII_TIMEOUT));
1008 if (time_left == 0) {
1009 fep->mii_timeout = 1;
1010 printk(KERN_ERR "FEC: MDIO write timeout\n");
1017 static int fec_enet_mdio_reset(struct mii_bus *bus)
1022 static int fec_enet_mii_probe(struct net_device *ndev)
1024 struct fec_enet_private *fep = netdev_priv(ndev);
1025 const struct platform_device_id *id_entry =
1026 platform_get_device_id(fep->pdev);
1027 struct phy_device *phy_dev = NULL;
1028 char mdio_bus_id[MII_BUS_ID_SIZE];
1029 char phy_name[MII_BUS_ID_SIZE + 3];
1031 int dev_id = fep->dev_id;
1033 fep->phy_dev = NULL;
1035 /* check for attached phy */
1036 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1037 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1039 if (fep->mii_bus->phy_map[phy_id] == NULL)
1041 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1045 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1049 if (phy_id >= PHY_MAX_ADDR) {
1051 "%s: no PHY, assuming direct connection to switch\n",
1053 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1057 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1058 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1059 fep->phy_interface);
1060 if (IS_ERR(phy_dev)) {
1061 printk(KERN_ERR "%s: could not attach to PHY\n", ndev->name);
1062 return PTR_ERR(phy_dev);
1065 /* mask with MAC supported features */
1066 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1067 phy_dev->supported &= PHY_GBIT_FEATURES;
1068 phy_dev->supported |= SUPPORTED_Pause;
1071 phy_dev->supported &= PHY_BASIC_FEATURES;
1073 phy_dev->advertising = phy_dev->supported;
1075 fep->phy_dev = phy_dev;
1077 fep->full_duplex = 0;
1080 "%s: Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1082 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1088 static int fec_enet_mii_init(struct platform_device *pdev)
1090 static struct mii_bus *fec0_mii_bus;
1091 struct net_device *ndev = platform_get_drvdata(pdev);
1092 struct fec_enet_private *fep = netdev_priv(ndev);
1093 const struct platform_device_id *id_entry =
1094 platform_get_device_id(fep->pdev);
1095 int err = -ENXIO, i;
1098 * The dual fec interfaces are not equivalent with enet-mac.
1099 * Here are the differences:
1101 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1102 * - fec0 acts as the 1588 time master while fec1 is slave
1103 * - external phys can only be configured by fec0
1105 * That is to say fec1 can not work independently. It only works
1106 * when fec0 is working. The reason behind this design is that the
1107 * second interface is added primarily for Switch mode.
1109 * Because of the last point above, both phys are attached on fec0
1110 * mdio interface in board design, and need to be configured by
1113 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1114 /* fec1 uses fec0 mii_bus */
1115 if (mii_cnt && fec0_mii_bus) {
1116 fep->mii_bus = fec0_mii_bus;
1123 fep->mii_timeout = 0;
1126 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1128 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1129 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1130 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1133 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1134 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1136 fep->phy_speed <<= 1;
1137 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1139 fep->mii_bus = mdiobus_alloc();
1140 if (fep->mii_bus == NULL) {
1145 fep->mii_bus->name = "fec_enet_mii_bus";
1146 fep->mii_bus->read = fec_enet_mdio_read;
1147 fep->mii_bus->write = fec_enet_mdio_write;
1148 fep->mii_bus->reset = fec_enet_mdio_reset;
1149 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1150 pdev->name, fep->dev_id + 1);
1151 fep->mii_bus->priv = fep;
1152 fep->mii_bus->parent = &pdev->dev;
1154 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1155 if (!fep->mii_bus->irq) {
1157 goto err_out_free_mdiobus;
1160 for (i = 0; i < PHY_MAX_ADDR; i++)
1161 fep->mii_bus->irq[i] = PHY_POLL;
1163 if (mdiobus_register(fep->mii_bus))
1164 goto err_out_free_mdio_irq;
1168 /* save fec0 mii_bus */
1169 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1170 fec0_mii_bus = fep->mii_bus;
1174 err_out_free_mdio_irq:
1175 kfree(fep->mii_bus->irq);
1176 err_out_free_mdiobus:
1177 mdiobus_free(fep->mii_bus);
1182 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1184 if (--mii_cnt == 0) {
1185 mdiobus_unregister(fep->mii_bus);
1186 kfree(fep->mii_bus->irq);
1187 mdiobus_free(fep->mii_bus);
1191 static int fec_enet_get_settings(struct net_device *ndev,
1192 struct ethtool_cmd *cmd)
1194 struct fec_enet_private *fep = netdev_priv(ndev);
1195 struct phy_device *phydev = fep->phy_dev;
1200 return phy_ethtool_gset(phydev, cmd);
1203 static int fec_enet_set_settings(struct net_device *ndev,
1204 struct ethtool_cmd *cmd)
1206 struct fec_enet_private *fep = netdev_priv(ndev);
1207 struct phy_device *phydev = fep->phy_dev;
1212 return phy_ethtool_sset(phydev, cmd);
1215 static void fec_enet_get_drvinfo(struct net_device *ndev,
1216 struct ethtool_drvinfo *info)
1218 struct fec_enet_private *fep = netdev_priv(ndev);
1220 strlcpy(info->driver, fep->pdev->dev.driver->name,
1221 sizeof(info->driver));
1222 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1223 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1226 static int fec_enet_get_ts_info(struct net_device *ndev,
1227 struct ethtool_ts_info *info)
1229 struct fec_enet_private *fep = netdev_priv(ndev);
1231 if (fep->bufdesc_ex) {
1233 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1234 SOF_TIMESTAMPING_RX_SOFTWARE |
1235 SOF_TIMESTAMPING_SOFTWARE |
1236 SOF_TIMESTAMPING_TX_HARDWARE |
1237 SOF_TIMESTAMPING_RX_HARDWARE |
1238 SOF_TIMESTAMPING_RAW_HARDWARE;
1240 info->phc_index = ptp_clock_index(fep->ptp_clock);
1242 info->phc_index = -1;
1244 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1245 (1 << HWTSTAMP_TX_ON);
1247 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1248 (1 << HWTSTAMP_FILTER_ALL);
1251 return ethtool_op_get_ts_info(ndev, info);
1255 static void fec_enet_get_pauseparam(struct net_device *ndev,
1256 struct ethtool_pauseparam *pause)
1258 struct fec_enet_private *fep = netdev_priv(ndev);
1260 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1261 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1262 pause->rx_pause = pause->tx_pause;
1265 static int fec_enet_set_pauseparam(struct net_device *ndev,
1266 struct ethtool_pauseparam *pause)
1268 struct fec_enet_private *fep = netdev_priv(ndev);
1270 if (pause->tx_pause != pause->rx_pause) {
1272 "hardware only support enable/disable both tx and rx");
1276 fep->pause_flag = 0;
1278 /* tx pause must be same as rx pause */
1279 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1280 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1282 if (pause->rx_pause || pause->autoneg) {
1283 fep->phy_dev->supported |= ADVERTISED_Pause;
1284 fep->phy_dev->advertising |= ADVERTISED_Pause;
1286 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1287 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1290 if (pause->autoneg) {
1291 if (netif_running(ndev))
1293 phy_start_aneg(fep->phy_dev);
1295 if (netif_running(ndev))
1296 fec_restart(ndev, 0);
1301 static const struct ethtool_ops fec_enet_ethtool_ops = {
1302 .get_pauseparam = fec_enet_get_pauseparam,
1303 .set_pauseparam = fec_enet_set_pauseparam,
1304 .get_settings = fec_enet_get_settings,
1305 .set_settings = fec_enet_set_settings,
1306 .get_drvinfo = fec_enet_get_drvinfo,
1307 .get_link = ethtool_op_get_link,
1308 .get_ts_info = fec_enet_get_ts_info,
1311 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1313 struct fec_enet_private *fep = netdev_priv(ndev);
1314 struct phy_device *phydev = fep->phy_dev;
1316 if (!netif_running(ndev))
1322 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1323 return fec_ptp_ioctl(ndev, rq, cmd);
1325 return phy_mii_ioctl(phydev, rq, cmd);
1328 static void fec_enet_free_buffers(struct net_device *ndev)
1330 struct fec_enet_private *fep = netdev_priv(ndev);
1332 struct sk_buff *skb;
1333 struct bufdesc *bdp;
1335 bdp = fep->rx_bd_base;
1336 for (i = 0; i < RX_RING_SIZE; i++) {
1337 skb = fep->rx_skbuff[i];
1339 if (bdp->cbd_bufaddr)
1340 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1341 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1344 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1347 bdp = fep->tx_bd_base;
1348 for (i = 0; i < TX_RING_SIZE; i++)
1349 kfree(fep->tx_bounce[i]);
1352 static int fec_enet_alloc_buffers(struct net_device *ndev)
1354 struct fec_enet_private *fep = netdev_priv(ndev);
1356 struct sk_buff *skb;
1357 struct bufdesc *bdp;
1359 bdp = fep->rx_bd_base;
1360 for (i = 0; i < RX_RING_SIZE; i++) {
1361 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1363 fec_enet_free_buffers(ndev);
1366 fep->rx_skbuff[i] = skb;
1368 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1369 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1370 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1372 if (fep->bufdesc_ex) {
1373 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1374 ebdp->cbd_esc = BD_ENET_RX_INT;
1377 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1380 /* Set the last buffer to wrap. */
1381 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1382 bdp->cbd_sc |= BD_SC_WRAP;
1384 bdp = fep->tx_bd_base;
1385 for (i = 0; i < TX_RING_SIZE; i++) {
1386 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1389 bdp->cbd_bufaddr = 0;
1391 if (fep->bufdesc_ex) {
1392 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1393 ebdp->cbd_esc = BD_ENET_RX_INT;
1396 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1399 /* Set the last buffer to wrap. */
1400 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1401 bdp->cbd_sc |= BD_SC_WRAP;
1407 fec_enet_open(struct net_device *ndev)
1409 struct fec_enet_private *fep = netdev_priv(ndev);
1412 napi_enable(&fep->napi);
1414 /* I should reset the ring buffers here, but I don't yet know
1415 * a simple way to do that.
1418 ret = fec_enet_alloc_buffers(ndev);
1422 /* Probe and connect to PHY when open the interface */
1423 ret = fec_enet_mii_probe(ndev);
1425 fec_enet_free_buffers(ndev);
1428 phy_start(fep->phy_dev);
1429 netif_start_queue(ndev);
1435 fec_enet_close(struct net_device *ndev)
1437 struct fec_enet_private *fep = netdev_priv(ndev);
1439 /* Don't know what to do yet. */
1441 netif_stop_queue(ndev);
1445 phy_stop(fep->phy_dev);
1446 phy_disconnect(fep->phy_dev);
1449 fec_enet_free_buffers(ndev);
1454 /* Set or clear the multicast filter for this adaptor.
1455 * Skeleton taken from sunlance driver.
1456 * The CPM Ethernet implementation allows Multicast as well as individual
1457 * MAC address filtering. Some of the drivers check to make sure it is
1458 * a group multicast address, and discard those that are not. I guess I
1459 * will do the same for now, but just remove the test if you want
1460 * individual filtering as well (do the upper net layers want or support
1461 * this kind of feature?).
1464 #define HASH_BITS 6 /* #bits in hash */
1465 #define CRC32_POLY 0xEDB88320
1467 static void set_multicast_list(struct net_device *ndev)
1469 struct fec_enet_private *fep = netdev_priv(ndev);
1470 struct netdev_hw_addr *ha;
1471 unsigned int i, bit, data, crc, tmp;
1474 if (ndev->flags & IFF_PROMISC) {
1475 tmp = readl(fep->hwp + FEC_R_CNTRL);
1477 writel(tmp, fep->hwp + FEC_R_CNTRL);
1481 tmp = readl(fep->hwp + FEC_R_CNTRL);
1483 writel(tmp, fep->hwp + FEC_R_CNTRL);
1485 if (ndev->flags & IFF_ALLMULTI) {
1486 /* Catch all multicast addresses, so set the
1489 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1490 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1495 /* Clear filter and add the addresses in hash register
1497 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1498 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1500 netdev_for_each_mc_addr(ha, ndev) {
1501 /* calculate crc32 value of mac address */
1504 for (i = 0; i < ndev->addr_len; i++) {
1506 for (bit = 0; bit < 8; bit++, data >>= 1) {
1508 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1512 /* only upper 6 bits (HASH_BITS) are used
1513 * which point to specific bit in he hash registers
1515 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1518 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1519 tmp |= 1 << (hash - 32);
1520 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1522 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1524 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1529 /* Set a MAC change in hardware. */
1531 fec_set_mac_address(struct net_device *ndev, void *p)
1533 struct fec_enet_private *fep = netdev_priv(ndev);
1534 struct sockaddr *addr = p;
1536 if (!is_valid_ether_addr(addr->sa_data))
1537 return -EADDRNOTAVAIL;
1539 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1541 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1542 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1543 fep->hwp + FEC_ADDR_LOW);
1544 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1545 fep->hwp + FEC_ADDR_HIGH);
1549 #ifdef CONFIG_NET_POLL_CONTROLLER
1551 * fec_poll_controller - FEC Poll controller function
1552 * @dev: The FEC network adapter
1554 * Polled functionality used by netconsole and others in non interrupt mode
1557 void fec_poll_controller(struct net_device *dev)
1560 struct fec_enet_private *fep = netdev_priv(dev);
1562 for (i = 0; i < FEC_IRQ_NUM; i++) {
1563 if (fep->irq[i] > 0) {
1564 disable_irq(fep->irq[i]);
1565 fec_enet_interrupt(fep->irq[i], dev);
1566 enable_irq(fep->irq[i]);
1572 static const struct net_device_ops fec_netdev_ops = {
1573 .ndo_open = fec_enet_open,
1574 .ndo_stop = fec_enet_close,
1575 .ndo_start_xmit = fec_enet_start_xmit,
1576 .ndo_set_rx_mode = set_multicast_list,
1577 .ndo_change_mtu = eth_change_mtu,
1578 .ndo_validate_addr = eth_validate_addr,
1579 .ndo_tx_timeout = fec_timeout,
1580 .ndo_set_mac_address = fec_set_mac_address,
1581 .ndo_do_ioctl = fec_enet_ioctl,
1582 #ifdef CONFIG_NET_POLL_CONTROLLER
1583 .ndo_poll_controller = fec_poll_controller,
1588 * XXX: We need to clean up on failure exits here.
1591 static int fec_enet_init(struct net_device *ndev)
1593 struct fec_enet_private *fep = netdev_priv(ndev);
1594 struct bufdesc *cbd_base;
1595 struct bufdesc *bdp;
1598 /* Allocate memory for buffer descriptors. */
1599 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1602 printk("FEC: allocate descriptor memory failed?\n");
1606 spin_lock_init(&fep->hw_lock);
1610 /* Get the Ethernet address */
1613 /* Set receive and transmit descriptor base. */
1614 fep->rx_bd_base = cbd_base;
1615 if (fep->bufdesc_ex)
1616 fep->tx_bd_base = (struct bufdesc *)
1617 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1619 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1621 /* The FEC Ethernet specific entries in the device structure */
1622 ndev->watchdog_timeo = TX_TIMEOUT;
1623 ndev->netdev_ops = &fec_netdev_ops;
1624 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1626 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1627 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1629 /* Initialize the receive buffer descriptors. */
1630 bdp = fep->rx_bd_base;
1631 for (i = 0; i < RX_RING_SIZE; i++) {
1633 /* Initialize the BD for every fragment in the page. */
1635 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1638 /* Set the last buffer to wrap */
1639 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1640 bdp->cbd_sc |= BD_SC_WRAP;
1642 /* ...and the same for transmit */
1643 bdp = fep->tx_bd_base;
1645 for (i = 0; i < TX_RING_SIZE; i++) {
1647 /* Initialize the BD for every fragment in the page. */
1649 bdp->cbd_bufaddr = 0;
1650 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1653 /* Set the last buffer to wrap */
1654 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1655 bdp->cbd_sc |= BD_SC_WRAP;
1656 fep->dirty_tx = bdp;
1658 fec_restart(ndev, 0);
1664 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1666 struct device_node *np = pdev->dev.of_node;
1669 return of_get_phy_mode(np);
1674 static void fec_reset_phy(struct platform_device *pdev)
1678 struct device_node *np = pdev->dev.of_node;
1683 of_property_read_u32(np, "phy-reset-duration", &msec);
1684 /* A sane reset duration should not be longer than 1s */
1688 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1689 if (!gpio_is_valid(phy_reset))
1692 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1693 GPIOF_OUT_INIT_LOW, "phy-reset");
1695 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1699 gpio_set_value(phy_reset, 1);
1701 #else /* CONFIG_OF */
1702 static int fec_get_phy_mode_dt(struct platform_device *pdev)
1707 static void fec_reset_phy(struct platform_device *pdev)
1710 * In case of platform probe, the reset has been done
1714 #endif /* CONFIG_OF */
1717 fec_probe(struct platform_device *pdev)
1719 struct fec_enet_private *fep;
1720 struct fec_platform_data *pdata;
1721 struct net_device *ndev;
1722 int i, irq, ret = 0;
1724 const struct of_device_id *of_id;
1726 struct pinctrl *pinctrl;
1727 struct regulator *reg_phy;
1729 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1731 pdev->id_entry = of_id->data;
1733 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1737 r = request_mem_region(r->start, resource_size(r), pdev->name);
1741 /* Init network device */
1742 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1745 goto failed_alloc_etherdev;
1748 SET_NETDEV_DEV(ndev, &pdev->dev);
1750 /* setup board info structure */
1751 fep = netdev_priv(ndev);
1753 /* default enable pause frame auto negotiation */
1754 if (pdev->id_entry &&
1755 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1756 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1758 fep->hwp = ioremap(r->start, resource_size(r));
1760 fep->dev_id = dev_id++;
1762 fep->bufdesc_ex = 0;
1766 goto failed_ioremap;
1769 platform_set_drvdata(pdev, ndev);
1771 ret = fec_get_phy_mode_dt(pdev);
1773 pdata = pdev->dev.platform_data;
1775 fep->phy_interface = pdata->phy;
1777 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1779 fep->phy_interface = ret;
1782 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1783 if (IS_ERR(pinctrl)) {
1784 ret = PTR_ERR(pinctrl);
1788 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1789 if (IS_ERR(fep->clk_ipg)) {
1790 ret = PTR_ERR(fep->clk_ipg);
1794 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1795 if (IS_ERR(fep->clk_ahb)) {
1796 ret = PTR_ERR(fep->clk_ahb);
1800 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1802 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1803 if (IS_ERR(fep->clk_ptp)) {
1804 ret = PTR_ERR(fep->clk_ptp);
1805 fep->bufdesc_ex = 0;
1808 clk_prepare_enable(fep->clk_ahb);
1809 clk_prepare_enable(fep->clk_ipg);
1810 if (!IS_ERR(fep->clk_ptp))
1811 clk_prepare_enable(fep->clk_ptp);
1813 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1814 if (!IS_ERR(reg_phy)) {
1815 ret = regulator_enable(reg_phy);
1818 "Failed to enable phy regulator: %d\n", ret);
1819 goto failed_regulator;
1823 fec_reset_phy(pdev);
1825 if (fep->bufdesc_ex)
1826 fec_ptp_init(ndev, pdev);
1828 ret = fec_enet_init(ndev);
1832 for (i = 0; i < FEC_IRQ_NUM; i++) {
1833 irq = platform_get_irq(pdev, i);
1840 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1843 irq = platform_get_irq(pdev, i);
1844 free_irq(irq, ndev);
1850 ret = fec_enet_mii_init(pdev);
1852 goto failed_mii_init;
1854 /* Carrier starts down, phylib will bring it up */
1855 netif_carrier_off(ndev);
1857 ret = register_netdev(ndev);
1859 goto failed_register;
1864 fec_enet_mii_remove(fep);
1867 for (i = 0; i < FEC_IRQ_NUM; i++) {
1868 irq = platform_get_irq(pdev, i);
1870 free_irq(irq, ndev);
1874 clk_disable_unprepare(fep->clk_ahb);
1875 clk_disable_unprepare(fep->clk_ipg);
1876 if (!IS_ERR(fep->clk_ptp))
1877 clk_disable_unprepare(fep->clk_ptp);
1883 failed_alloc_etherdev:
1884 release_mem_region(r->start, resource_size(r));
1890 fec_drv_remove(struct platform_device *pdev)
1892 struct net_device *ndev = platform_get_drvdata(pdev);
1893 struct fec_enet_private *fep = netdev_priv(ndev);
1897 unregister_netdev(ndev);
1898 fec_enet_mii_remove(fep);
1899 del_timer_sync(&fep->time_keep);
1900 clk_disable_unprepare(fep->clk_ptp);
1902 ptp_clock_unregister(fep->ptp_clock);
1903 clk_disable_unprepare(fep->clk_ahb);
1904 clk_disable_unprepare(fep->clk_ipg);
1905 for (i = 0; i < FEC_IRQ_NUM; i++) {
1906 int irq = platform_get_irq(pdev, i);
1908 free_irq(irq, ndev);
1913 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1915 release_mem_region(r->start, resource_size(r));
1917 platform_set_drvdata(pdev, NULL);
1924 fec_suspend(struct device *dev)
1926 struct net_device *ndev = dev_get_drvdata(dev);
1927 struct fec_enet_private *fep = netdev_priv(ndev);
1929 if (netif_running(ndev)) {
1931 netif_device_detach(ndev);
1933 clk_disable_unprepare(fep->clk_ahb);
1934 clk_disable_unprepare(fep->clk_ipg);
1940 fec_resume(struct device *dev)
1942 struct net_device *ndev = dev_get_drvdata(dev);
1943 struct fec_enet_private *fep = netdev_priv(ndev);
1945 clk_prepare_enable(fep->clk_ahb);
1946 clk_prepare_enable(fep->clk_ipg);
1947 if (netif_running(ndev)) {
1948 fec_restart(ndev, fep->full_duplex);
1949 netif_device_attach(ndev);
1955 static const struct dev_pm_ops fec_pm_ops = {
1956 .suspend = fec_suspend,
1957 .resume = fec_resume,
1958 .freeze = fec_suspend,
1960 .poweroff = fec_suspend,
1961 .restore = fec_resume,
1965 static struct platform_driver fec_driver = {
1967 .name = DRIVER_NAME,
1968 .owner = THIS_MODULE,
1972 .of_match_table = fec_dt_ids,
1974 .id_table = fec_devtype,
1976 .remove = fec_drv_remove,
1979 module_platform_driver(fec_driver);
1981 MODULE_LICENSE("GPL");