1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
4 Copyright 1994, 1995 Digital Equipment Corporation.
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
9 The author may be reached at davies@maniac.ultranet.com.
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
38 DE500 10/100 PCI Fasternet
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
50 So far the driver is known to work with the following cards:
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
82 Up to 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
99 To utilise this ability, you have to do 8 things:
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
108 insmod de4x5 io=0xghh where g = bus number
111 NB: autoprobing for modules is now supported by default. You may just
116 to load all available boards. For a specific board, still use
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
207 autosense to set the media/speed; with the following
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
244 Version Date Description
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
368 Fix type1_infoblock() bug introduced in 0.53, from
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/pci.h>
454 #include <linux/eisa.h>
455 #include <linux/delay.h>
456 #include <linux/init.h>
457 #include <linux/spinlock.h>
458 #include <linux/crc32.h>
459 #include <linux/netdevice.h>
460 #include <linux/etherdevice.h>
461 #include <linux/skbuff.h>
462 #include <linux/time.h>
463 #include <linux/types.h>
464 #include <linux/unistd.h>
465 #include <linux/ctype.h>
466 #include <linux/dma-mapping.h>
467 #include <linux/moduleparam.h>
468 #include <linux/bitops.h>
469 #include <linux/gfp.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
482 static const char version[] =
483 KERN_INFO "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
485 #define c_char const char
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
520 #define DE4X5_MAX_PHY 8 /* Allow up to 8 attached PHY devices per board */
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
554 ** Define special SROM detection cases
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
578 static int de4x5_debug = DE4X5_DEBUG;
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
585 ** Allow per adapter set up. For modules this is simply a command line
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
594 static char *args = DE4X5_PARM;
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
609 ** Ethernet PROM defines
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
641 ** Ethernet PROM defines for DC21040
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
675 static int dec_only = 1;
679 ** DE4X5 IRQ ENABLE/DISABLE
681 #define ENABLE_IRQs { \
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
726 #define DE4X5_AUTOSENSE_MS 250
732 char sub_vendor_id[2];
733 char sub_system_id[2];
738 char num_controllers;
743 #define SUB_VENDOR_ID 0x500a
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
759 volatile __le32 status;
767 ** The DE4X5 private structure
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
778 u_int excessive_collisions;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 bool fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 bool tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff_head queue; /* Save the (re-ordered) skb's */
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 bool useSROM; /* For non-DEC card use SROM */
842 bool useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
878 u_char addr[ETH_ALEN];
882 ** The transmit ring full condition is described by the tx_old and tx_new
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
897 static int de4x5_open(struct net_device *dev);
898 static netdev_tx_t de4x5_queue_pkt(struct sk_buff *skb,
899 struct net_device *dev);
900 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
901 static int de4x5_close(struct net_device *dev);
902 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
903 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
904 static void set_multicast_list(struct net_device *dev);
905 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
910 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
911 static int de4x5_init(struct net_device *dev);
912 static int de4x5_sw_reset(struct net_device *dev);
913 static int de4x5_rx(struct net_device *dev);
914 static int de4x5_tx(struct net_device *dev);
915 static void de4x5_ast(struct net_device *dev);
916 static int de4x5_txur(struct net_device *dev);
917 static int de4x5_rx_ovfc(struct net_device *dev);
919 static int autoconf_media(struct net_device *dev);
920 static void create_packet(struct net_device *dev, char *frame, int len);
921 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
922 static int dc21040_autoconf(struct net_device *dev);
923 static int dc21041_autoconf(struct net_device *dev);
924 static int dc21140m_autoconf(struct net_device *dev);
925 static int dc2114x_autoconf(struct net_device *dev);
926 static int srom_autoconf(struct net_device *dev);
927 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
928 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
929 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
930 static int test_for_100Mb(struct net_device *dev, int msec);
931 static int wait_for_link(struct net_device *dev);
932 static int test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec);
933 static int is_spd_100(struct net_device *dev);
934 static int is_100_up(struct net_device *dev);
935 static int is_10_up(struct net_device *dev);
936 static int is_anc_capable(struct net_device *dev);
937 static int ping_media(struct net_device *dev, int msec);
938 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
939 static void de4x5_free_rx_buffs(struct net_device *dev);
940 static void de4x5_free_tx_buffs(struct net_device *dev);
941 static void de4x5_save_skbs(struct net_device *dev);
942 static void de4x5_rst_desc_ring(struct net_device *dev);
943 static void de4x5_cache_state(struct net_device *dev, int flag);
944 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
945 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
946 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
947 static void de4x5_setup_intr(struct net_device *dev);
948 static void de4x5_init_connection(struct net_device *dev);
949 static int de4x5_reset_phy(struct net_device *dev);
950 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
951 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
952 static int test_tp(struct net_device *dev, s32 msec);
953 static int EISA_signature(char *name, struct device *device);
954 static int PCI_signature(char *name, struct de4x5_private *lp);
955 static void DevicePresent(struct net_device *dev, u_long iobase);
956 static void enet_addr_rst(u_long aprom_addr);
957 static int de4x5_bad_srom(struct de4x5_private *lp);
958 static short srom_rd(u_long address, u_char offset);
959 static void srom_latch(u_int command, u_long address);
960 static void srom_command(u_int command, u_long address);
961 static void srom_address(u_int command, u_long address, u_char offset);
962 static short srom_data(u_int command, u_long address);
963 /*static void srom_busy(u_int command, u_long address);*/
964 static void sendto_srom(u_int command, u_long addr);
965 static int getfrom_srom(u_long addr);
966 static int srom_map_media(struct net_device *dev);
967 static int srom_infoleaf_info(struct net_device *dev);
968 static void srom_init(struct net_device *dev);
969 static void srom_exec(struct net_device *dev, u_char *p);
970 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
972 static int mii_rdata(u_long ioaddr);
973 static void mii_wdata(int data, int len, u_long ioaddr);
974 static void mii_ta(u_long rw, u_long ioaddr);
975 static int mii_swap(int data, int len);
976 static void mii_address(u_char addr, u_long ioaddr);
977 static void sendto_mii(u32 command, int data, u_long ioaddr);
978 static int getfrom_mii(u32 command, u_long ioaddr);
979 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
980 static int mii_get_phy(struct net_device *dev);
981 static void SetMulticastFilter(struct net_device *dev);
982 static int get_hw_addr(struct net_device *dev);
983 static void srom_repair(struct net_device *dev, int card);
984 static int test_bad_enet(struct net_device *dev, int status);
985 static int an_exception(struct de4x5_private *lp);
986 static char *build_setup_frame(struct net_device *dev, int mode);
987 static void disable_ast(struct net_device *dev);
988 static long de4x5_switch_mac_port(struct net_device *dev);
989 static int gep_rd(struct net_device *dev);
990 static void gep_wr(s32 data, struct net_device *dev);
991 static void yawn(struct net_device *dev, int state);
992 static void de4x5_parse_params(struct net_device *dev);
993 static void de4x5_dbg_open(struct net_device *dev);
994 static void de4x5_dbg_mii(struct net_device *dev, int k);
995 static void de4x5_dbg_media(struct net_device *dev);
996 static void de4x5_dbg_srom(struct de4x5_srom *p);
997 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
998 static int de4x5_strncmp(char *a, char *b, int n);
999 static int dc21041_infoleaf(struct net_device *dev);
1000 static int dc21140_infoleaf(struct net_device *dev);
1001 static int dc21142_infoleaf(struct net_device *dev);
1002 static int dc21143_infoleaf(struct net_device *dev);
1003 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1004 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1009 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1012 ** Note now that module autoprobing is allowed under EISA and PCI. The
1013 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1014 ** to "do the right thing".
1017 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1019 module_param(io, int, 0);
1020 module_param(de4x5_debug, int, 0);
1021 module_param(dec_only, int, 0);
1022 module_param(args, charp, 0);
1024 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1025 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1026 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1027 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1028 MODULE_LICENSE("GPL");
1031 ** List the SROM infoleaf functions and chipsets
1035 int (*fn)(struct net_device *);
1037 static struct InfoLeaf infoleaf_array[] = {
1038 {DC21041, dc21041_infoleaf},
1039 {DC21140, dc21140_infoleaf},
1040 {DC21142, dc21142_infoleaf},
1041 {DC21143, dc21143_infoleaf}
1043 #define INFOLEAF_SIZE ARRAY_SIZE(infoleaf_array)
1046 ** List the SROM info block functions
1048 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1058 #define COMPACT (ARRAY_SIZE(dc_infoblock) - 1)
1061 ** Miscellaneous defines...
1063 #define RESET_DE4X5 {\
1067 outl(i | BMR_SWR, DE4X5_BMR);\
1069 outl(i, DE4X5_BMR);\
1071 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1075 #define PHY_HARD_RESET {\
1076 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1077 mdelay(1); /* Assert for 1ms */\
1078 outl(0x00, DE4X5_GEP);\
1079 mdelay(2); /* Wait for 2ms */\
1082 static const struct net_device_ops de4x5_netdev_ops = {
1083 .ndo_open = de4x5_open,
1084 .ndo_stop = de4x5_close,
1085 .ndo_start_xmit = de4x5_queue_pkt,
1086 .ndo_get_stats = de4x5_get_stats,
1087 .ndo_set_rx_mode = set_multicast_list,
1088 .ndo_do_ioctl = de4x5_ioctl,
1089 .ndo_change_mtu = eth_change_mtu,
1090 .ndo_set_mac_address= eth_mac_addr,
1091 .ndo_validate_addr = eth_validate_addr,
1096 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1098 char name[DE4X5_NAME_LENGTH + 1];
1099 struct de4x5_private *lp = netdev_priv(dev);
1100 struct pci_dev *pdev = NULL;
1103 dev_set_drvdata(gendev, dev);
1105 /* Ensure we're not sleeping */
1106 if (lp->bus == EISA) {
1107 outb(WAKEUP, PCI_CFPM);
1109 pdev = to_pci_dev (gendev);
1110 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1116 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1117 return -ENXIO; /* Hardware could not reset */
1121 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1123 lp->useSROM = false;
1124 if (lp->bus == PCI) {
1125 PCI_signature(name, lp);
1127 EISA_signature(name, gendev);
1130 if (*name == '\0') { /* Not found a board signature */
1134 dev->base_addr = iobase;
1135 printk ("%s: %s at 0x%04lx", dev_name(gendev), name, iobase);
1137 status = get_hw_addr(dev);
1138 printk(", h/w address %pM\n", dev->dev_addr);
1141 printk(" which has an Ethernet PROM CRC error.\n");
1144 skb_queue_head_init(&lp->cache.queue);
1145 lp->cache.gepc = GEP_INIT;
1146 lp->asBit = GEP_SLNK;
1147 lp->asPolarity = GEP_SLNK;
1148 lp->asBitValid = ~0;
1150 lp->gendev = gendev;
1151 spin_lock_init(&lp->lock);
1152 init_timer(&lp->timer);
1153 lp->timer.function = (void (*)(unsigned long))de4x5_ast;
1154 lp->timer.data = (unsigned long)dev;
1155 de4x5_parse_params(dev);
1158 ** Choose correct autosensing in case someone messed up
1160 lp->autosense = lp->params.autosense;
1161 if (lp->chipset != DC21140) {
1162 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1163 lp->params.autosense = TP;
1165 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1166 lp->params.autosense = BNC;
1169 lp->fdx = lp->params.fdx;
1170 sprintf(lp->adapter_name,"%s (%s)", name, dev_name(gendev));
1172 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1173 #if defined(__alpha__) || defined(__powerpc__) || defined(CONFIG_SPARC) || defined(DE4X5_DO_MEMCPY)
1174 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1176 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1177 &lp->dma_rings, GFP_ATOMIC);
1178 if (lp->rx_ring == NULL) {
1182 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1185 ** Set up the RX descriptor ring (Intels)
1186 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1188 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
1189 for (i=0; i<NUM_RX_DESC; i++) {
1190 lp->rx_ring[i].status = 0;
1191 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1192 lp->rx_ring[i].buf = 0;
1193 lp->rx_ring[i].next = 0;
1194 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1199 dma_addr_t dma_rx_bufs;
1201 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1202 * sizeof(struct de4x5_desc);
1203 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1204 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1205 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1206 for (i=0; i<NUM_RX_DESC; i++) {
1207 lp->rx_ring[i].status = 0;
1208 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1209 lp->rx_ring[i].buf =
1210 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1211 lp->rx_ring[i].next = 0;
1212 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1220 lp->rxRingSize = NUM_RX_DESC;
1221 lp->txRingSize = NUM_TX_DESC;
1223 /* Write the end of list marker to the descriptor lists */
1224 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1225 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1227 /* Tell the adapter where the TX/RX rings are located. */
1228 outl(lp->dma_rings, DE4X5_RRBA);
1229 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1232 /* Initialise the IRQ mask and Enable/Disable */
1233 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1234 lp->irq_en = IMR_NIM | IMR_AIM;
1236 /* Create a loopback packet frame for later media probing */
1237 create_packet(dev, lp->frame, sizeof(lp->frame));
1239 /* Check if the RX overflow bug needs testing for */
1240 i = lp->cfrv & 0x000000fe;
1241 if ((lp->chipset == DC21140) && (i == 0x20)) {
1245 /* Initialise the SROM pointers if possible */
1247 lp->state = INITIALISED;
1248 if (srom_infoleaf_info(dev)) {
1249 dma_free_coherent (gendev, lp->dma_size,
1250 lp->rx_ring, lp->dma_rings);
1259 ** Check for an MII interface
1261 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1265 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1266 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1269 if (de4x5_debug & DEBUG_VERSION) {
1273 /* The DE4X5-specific entries in the device structure. */
1274 SET_NETDEV_DEV(dev, gendev);
1275 dev->netdev_ops = &de4x5_netdev_ops;
1278 /* Fill in the generic fields of the device structure. */
1279 if ((status = register_netdev (dev))) {
1280 dma_free_coherent (gendev, lp->dma_size,
1281 lp->rx_ring, lp->dma_rings);
1285 /* Let the adapter sleep to save power */
1293 de4x5_open(struct net_device *dev)
1295 struct de4x5_private *lp = netdev_priv(dev);
1296 u_long iobase = dev->base_addr;
1300 /* Allocate the RX buffers */
1301 for (i=0; i<lp->rxRingSize; i++) {
1302 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1303 de4x5_free_rx_buffs(dev);
1309 ** Wake up the adapter
1314 ** Re-initialize the DE4X5...
1316 status = de4x5_init(dev);
1317 spin_lock_init(&lp->lock);
1319 de4x5_dbg_open(dev);
1321 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1322 lp->adapter_name, dev)) {
1323 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1324 if (request_irq(dev->irq, de4x5_interrupt, IRQF_SHARED,
1325 lp->adapter_name, dev)) {
1326 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1328 de4x5_free_rx_buffs(dev);
1329 de4x5_free_tx_buffs(dev);
1334 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1335 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1339 lp->interrupt = UNMASK_INTERRUPTS;
1340 dev->trans_start = jiffies; /* prevent tx timeout */
1344 de4x5_setup_intr(dev);
1346 if (de4x5_debug & DEBUG_OPEN) {
1347 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1348 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1349 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1350 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1351 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1352 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1353 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1354 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1361 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1362 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1363 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1364 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1365 ** to be data corruption problems if it is larger (UDP errors seen from a
1369 de4x5_init(struct net_device *dev)
1371 /* Lock out other processes whilst setting up the hardware */
1372 netif_stop_queue(dev);
1374 de4x5_sw_reset(dev);
1376 /* Autoconfigure the connected port */
1377 autoconf_media(dev);
1383 de4x5_sw_reset(struct net_device *dev)
1385 struct de4x5_private *lp = netdev_priv(dev);
1386 u_long iobase = dev->base_addr;
1387 int i, j, status = 0;
1390 /* Select the MII or SRL port now and RESET the MAC */
1392 if (lp->phy[lp->active].id != 0) {
1393 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1395 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1397 de4x5_switch_mac_port(dev);
1401 ** Set the programmable burst length to 8 longwords for all the DC21140
1402 ** Fasternet chips and 4 longwords for all others: DMA errors result
1403 ** without these values. Cache align 16 long.
1405 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1406 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1407 outl(bmr, DE4X5_BMR);
1409 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1410 if (lp->chipset == DC21140) {
1411 omr |= (OMR_SDP | OMR_SB);
1413 lp->setup_f = PERFECT;
1414 outl(lp->dma_rings, DE4X5_RRBA);
1415 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1418 lp->rx_new = lp->rx_old = 0;
1419 lp->tx_new = lp->tx_old = 0;
1421 for (i = 0; i < lp->rxRingSize; i++) {
1422 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1425 for (i = 0; i < lp->txRingSize; i++) {
1426 lp->tx_ring[i].status = cpu_to_le32(0);
1431 /* Build the setup frame depending on filtering mode */
1432 SetMulticastFilter(dev);
1434 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1435 outl(omr|OMR_ST, DE4X5_OMR);
1437 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1439 for (j=0, i=0;(i<500) && (j==0);i++) { /* Up to 500ms delay */
1441 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1443 outl(omr, DE4X5_OMR); /* Stop everything! */
1446 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1451 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1452 lp->tx_old = lp->tx_new;
1458 ** Writes a socket buffer address to the next available transmit descriptor.
1461 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1463 struct de4x5_private *lp = netdev_priv(dev);
1464 u_long iobase = dev->base_addr;
1467 netif_stop_queue(dev);
1468 if (!lp->tx_enable) /* Cannot send for now */
1469 return NETDEV_TX_LOCKED;
1472 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1473 ** interrupts are lost by delayed descriptor status updates relative to
1474 ** the irq assertion, especially with a busy PCI bus.
1476 spin_lock_irqsave(&lp->lock, flags);
1478 spin_unlock_irqrestore(&lp->lock, flags);
1480 /* Test if cache is already locked - requeue skb if so */
1481 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1482 return NETDEV_TX_LOCKED;
1484 /* Transmit descriptor ring full or stale skb */
1485 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1486 if (lp->interrupt) {
1487 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1489 de4x5_put_cache(dev, skb);
1491 if (de4x5_debug & DEBUG_TX) {
1492 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1494 } else if (skb->len > 0) {
1495 /* If we already have stuff queued locally, use that first */
1496 if (!skb_queue_empty(&lp->cache.queue) && !lp->interrupt) {
1497 de4x5_put_cache(dev, skb);
1498 skb = de4x5_get_cache(dev);
1501 while (skb && !netif_queue_stopped(dev) &&
1502 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1503 spin_lock_irqsave(&lp->lock, flags);
1504 netif_stop_queue(dev);
1505 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1506 lp->stats.tx_bytes += skb->len;
1507 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1509 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1511 if (TX_BUFFS_AVAIL) {
1512 netif_start_queue(dev); /* Another pkt may be queued */
1514 skb = de4x5_get_cache(dev);
1515 spin_unlock_irqrestore(&lp->lock, flags);
1517 if (skb) de4x5_putb_cache(dev, skb);
1522 return NETDEV_TX_OK;
1526 ** The DE4X5 interrupt handler.
1528 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1529 ** so that the asserted interrupt always has some real data to work with -
1530 ** if these I/O accesses are ever changed to memory accesses, ensure the
1531 ** STS write is read immediately to complete the transaction if the adapter
1532 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1533 ** is high and descriptor status bits cannot be set before the associated
1534 ** interrupt is asserted and this routine entered.
1537 de4x5_interrupt(int irq, void *dev_id)
1539 struct net_device *dev = dev_id;
1540 struct de4x5_private *lp;
1541 s32 imr, omr, sts, limit;
1543 unsigned int handled = 0;
1545 lp = netdev_priv(dev);
1546 spin_lock(&lp->lock);
1547 iobase = dev->base_addr;
1549 DISABLE_IRQs; /* Ensure non re-entrancy */
1551 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1552 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1554 synchronize_irq(dev->irq);
1556 for (limit=0; limit<8; limit++) {
1557 sts = inl(DE4X5_STS); /* Read IRQ status */
1558 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1560 if (!(sts & lp->irq_mask)) break;/* All done */
1563 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1566 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1569 if (sts & STS_LNF) { /* TP Link has failed */
1570 lp->irq_mask &= ~IMR_LFM;
1573 if (sts & STS_UNF) { /* Transmit underrun */
1577 if (sts & STS_SE) { /* Bus Error */
1579 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1581 spin_unlock(&lp->lock);
1586 /* Load the TX ring with any locally stored packets */
1587 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1588 while (!skb_queue_empty(&lp->cache.queue) && !netif_queue_stopped(dev) && lp->tx_enable) {
1589 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1594 lp->interrupt = UNMASK_INTERRUPTS;
1596 spin_unlock(&lp->lock);
1598 return IRQ_RETVAL(handled);
1602 de4x5_rx(struct net_device *dev)
1604 struct de4x5_private *lp = netdev_priv(dev);
1605 u_long iobase = dev->base_addr;
1609 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1611 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1614 if (inl(DE4X5_MFC) & MFC_FOCM) {
1620 if (status & RD_FS) { /* Remember the start of frame */
1624 if (status & RD_LS) { /* Valid frame status */
1625 if (lp->tx_enable) lp->linkOK++;
1626 if (status & RD_ES) { /* There was an error. */
1627 lp->stats.rx_errors++; /* Update the error stats. */
1628 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1629 if (status & RD_CE) lp->stats.rx_crc_errors++;
1630 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1631 if (status & RD_TL) lp->stats.rx_length_errors++;
1632 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1633 if (status & RD_CS) lp->pktStats.rx_collision++;
1634 if (status & RD_DB) lp->pktStats.rx_dribble++;
1635 if (status & RD_OF) lp->pktStats.rx_overflow++;
1636 } else { /* A valid frame received */
1637 struct sk_buff *skb;
1638 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1641 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1642 printk("%s: Insufficient memory; nuking packet.\n",
1644 lp->stats.rx_dropped++;
1646 de4x5_dbg_rx(skb, pkt_len);
1648 /* Push up the protocol stack */
1649 skb->protocol=eth_type_trans(skb,dev);
1650 de4x5_local_stats(dev, skb->data, pkt_len);
1654 lp->stats.rx_packets++;
1655 lp->stats.rx_bytes += pkt_len;
1659 /* Change buffer ownership for this frame, back to the adapter */
1660 for (;lp->rx_old!=entry;lp->rx_old=(lp->rx_old + 1)%lp->rxRingSize) {
1661 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1664 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1669 ** Update entry information
1671 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1678 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1680 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1681 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1683 if ((u_long) lp->tx_skb[entry] > 1)
1684 dev_kfree_skb_irq(lp->tx_skb[entry]);
1685 lp->tx_skb[entry] = NULL;
1689 ** Buffer sent - check for TX buffer errors.
1692 de4x5_tx(struct net_device *dev)
1694 struct de4x5_private *lp = netdev_priv(dev);
1695 u_long iobase = dev->base_addr;
1699 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1700 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1701 if (status < 0) { /* Buffer not sent yet */
1703 } else if (status != 0x7fffffff) { /* Not setup frame */
1704 if (status & TD_ES) { /* An error happened */
1705 lp->stats.tx_errors++;
1706 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1707 if (status & TD_LC) lp->stats.tx_window_errors++;
1708 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1709 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1710 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1712 if (TX_PKT_PENDING) {
1713 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1715 } else { /* Packet sent */
1716 lp->stats.tx_packets++;
1717 if (lp->tx_enable) lp->linkOK++;
1719 /* Update the collision counter */
1720 lp->stats.collisions += ((status & TD_EC) ? 16 :
1721 ((status & TD_CC) >> 3));
1723 /* Free the buffer. */
1724 if (lp->tx_skb[entry] != NULL)
1725 de4x5_free_tx_buff(lp, entry);
1728 /* Update all the pointers */
1729 lp->tx_old = (lp->tx_old + 1) % lp->txRingSize;
1732 /* Any resources available? */
1733 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1735 netif_wake_queue(dev);
1737 netif_start_queue(dev);
1744 de4x5_ast(struct net_device *dev)
1746 struct de4x5_private *lp = netdev_priv(dev);
1747 int next_tick = DE4X5_AUTOSENSE_MS;
1751 next_tick = srom_autoconf(dev);
1752 else if (lp->chipset == DC21140)
1753 next_tick = dc21140m_autoconf(dev);
1754 else if (lp->chipset == DC21041)
1755 next_tick = dc21041_autoconf(dev);
1756 else if (lp->chipset == DC21040)
1757 next_tick = dc21040_autoconf(dev);
1760 dt = (next_tick * HZ) / 1000;
1765 mod_timer(&lp->timer, jiffies + dt);
1769 de4x5_txur(struct net_device *dev)
1771 struct de4x5_private *lp = netdev_priv(dev);
1772 u_long iobase = dev->base_addr;
1775 omr = inl(DE4X5_OMR);
1776 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1777 omr &= ~(OMR_ST|OMR_SR);
1778 outl(omr, DE4X5_OMR);
1779 while (inl(DE4X5_STS) & STS_TS);
1780 if ((omr & OMR_TR) < OMR_TR) {
1785 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1792 de4x5_rx_ovfc(struct net_device *dev)
1794 struct de4x5_private *lp = netdev_priv(dev);
1795 u_long iobase = dev->base_addr;
1798 omr = inl(DE4X5_OMR);
1799 outl(omr & ~OMR_SR, DE4X5_OMR);
1800 while (inl(DE4X5_STS) & STS_RS);
1802 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1803 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1804 lp->rx_new = (lp->rx_new + 1) % lp->rxRingSize;
1807 outl(omr, DE4X5_OMR);
1813 de4x5_close(struct net_device *dev)
1815 struct de4x5_private *lp = netdev_priv(dev);
1816 u_long iobase = dev->base_addr;
1821 netif_stop_queue(dev);
1823 if (de4x5_debug & DEBUG_CLOSE) {
1824 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1825 dev->name, inl(DE4X5_STS));
1829 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1834 /* Free the associated irq */
1835 free_irq(dev->irq, dev);
1838 /* Free any socket buffers */
1839 de4x5_free_rx_buffs(dev);
1840 de4x5_free_tx_buffs(dev);
1842 /* Put the adapter to sleep to save power */
1848 static struct net_device_stats *
1849 de4x5_get_stats(struct net_device *dev)
1851 struct de4x5_private *lp = netdev_priv(dev);
1852 u_long iobase = dev->base_addr;
1854 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1860 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1862 struct de4x5_private *lp = netdev_priv(dev);
1865 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1866 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1867 lp->pktStats.bins[i]++;
1868 i = DE4X5_PKT_STAT_SZ;
1871 if (is_multicast_ether_addr(buf)) {
1872 if (is_broadcast_ether_addr(buf)) {
1873 lp->pktStats.broadcast++;
1875 lp->pktStats.multicast++;
1877 } else if (ether_addr_equal(buf, dev->dev_addr)) {
1878 lp->pktStats.unicast++;
1881 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1882 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1883 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1888 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1889 ** If the flag is changed on a descriptor that is being read by the hardware,
1890 ** I assume PCI transaction ordering will mean you are either successful or
1891 ** just miss asserting the change to the hardware. Anyway you're messing with
1892 ** a descriptor you don't own, but this shouldn't kill the chip provided
1893 ** the descriptor register is read only to the hardware.
1896 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1898 struct de4x5_private *lp = netdev_priv(dev);
1899 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1900 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1902 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1903 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1904 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1905 lp->tx_skb[lp->tx_new] = skb;
1906 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1909 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1914 ** Set or clear the multicast filter for this adaptor.
1917 set_multicast_list(struct net_device *dev)
1919 struct de4x5_private *lp = netdev_priv(dev);
1920 u_long iobase = dev->base_addr;
1922 /* First, double check that the adapter is open */
1923 if (lp->state == OPEN) {
1924 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1926 omr = inl(DE4X5_OMR);
1928 outl(omr, DE4X5_OMR);
1930 SetMulticastFilter(dev);
1931 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1932 SETUP_FRAME_LEN, (struct sk_buff *)1);
1934 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
1935 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1936 dev->trans_start = jiffies; /* prevent tx timeout */
1942 ** Calculate the hash code and update the logical address filter
1943 ** from a list of ethernet multicast addresses.
1944 ** Little endian crc one liner from Matt Thomas, DEC.
1947 SetMulticastFilter(struct net_device *dev)
1949 struct de4x5_private *lp = netdev_priv(dev);
1950 struct netdev_hw_addr *ha;
1951 u_long iobase = dev->base_addr;
1956 unsigned char *addrs;
1958 omr = inl(DE4X5_OMR);
1959 omr &= ~(OMR_PR | OMR_PM);
1960 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1962 if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 14)) {
1963 omr |= OMR_PM; /* Pass all multicasts */
1964 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1965 netdev_for_each_mc_addr(ha, dev) {
1966 crc = ether_crc_le(ETH_ALEN, ha->addr);
1967 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1969 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1970 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1972 byte <<= 1; /* calc offset into setup frame */
1976 lp->setup_frame[byte] |= bit;
1978 } else { /* Perfect filtering */
1979 netdev_for_each_mc_addr(ha, dev) {
1981 for (i=0; i<ETH_ALEN; i++) {
1982 *(pa + (i&1)) = *addrs++;
1983 if (i & 0x01) pa += 4;
1987 outl(omr, DE4X5_OMR);
1992 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
1994 static int __init de4x5_eisa_probe (struct device *gendev)
1996 struct eisa_device *edev;
2002 struct net_device *dev;
2003 struct de4x5_private *lp;
2005 edev = to_eisa_device (gendev);
2006 iobase = edev->base_addr;
2008 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2011 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2012 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2017 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2021 lp = netdev_priv(dev);
2023 cfid = (u32) inl(PCI_CFID);
2024 lp->cfrv = (u_short) inl(PCI_CFRV);
2025 device = (cfid >> 8) & 0x00ffff00;
2026 vendor = (u_short) cfid;
2028 /* Read the EISA Configuration Registers */
2029 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2031 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2032 * care about the EISA configuration, and thus doesn't
2033 * configure the PLX bridge properly. Oh well... Simply mimic
2034 * the EISA config file to sort it out. */
2036 /* EISA REG1: Assert DecChip 21040 HW Reset */
2037 outb (ER1_IAM | 1, EISA_REG1);
2040 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2041 outb (ER1_IAM, EISA_REG1);
2044 /* EISA REG3: R/W Burst Transfer Enable */
2045 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2047 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2048 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2050 irq = de4x5_irq[(regval >> 1) & 0x03];
2053 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2055 lp->chipset = device;
2058 /* Write the PCI Configuration Registers */
2059 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2060 outl(0x00006000, PCI_CFLT);
2061 outl(iobase, PCI_CBIO);
2063 DevicePresent(dev, EISA_APROM);
2067 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2073 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2075 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2080 static int de4x5_eisa_remove(struct device *device)
2082 struct net_device *dev;
2085 dev = dev_get_drvdata(device);
2086 iobase = dev->base_addr;
2088 unregister_netdev (dev);
2090 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2091 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2096 static struct eisa_device_id de4x5_eisa_ids[] = {
2097 { "DEC4250", 0 }, /* 0 is the board name index... */
2100 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2102 static struct eisa_driver de4x5_eisa_driver = {
2103 .id_table = de4x5_eisa_ids,
2106 .probe = de4x5_eisa_probe,
2107 .remove = de4x5_eisa_remove,
2110 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2116 ** This function searches the current bus (which is >0) for a DECchip with an
2117 ** SROM, so that in multiport cards that have one SROM shared between multiple
2118 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2119 ** For single port cards this is a time waster...
2122 srom_search(struct net_device *dev, struct pci_dev *pdev)
2125 u_short vendor, status;
2126 u_int irq = 0, device;
2127 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2129 struct de4x5_private *lp = netdev_priv(dev);
2130 struct pci_dev *this_dev;
2132 list_for_each_entry(this_dev, &pdev->bus->devices, bus_list) {
2133 vendor = this_dev->vendor;
2134 device = this_dev->device << 8;
2135 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2137 /* Get the chip configuration revision register */
2138 pb = this_dev->bus->number;
2140 /* Set the device number information */
2141 lp->device = PCI_SLOT(this_dev->devfn);
2144 /* Set the chipset information */
2146 device = ((this_dev->revision & CFRV_RN) < DC2114x_BRK
2147 ? DC21142 : DC21143);
2149 lp->chipset = device;
2151 /* Get the board I/O address (64 bits on sparc64) */
2152 iobase = pci_resource_start(this_dev, 0);
2154 /* Fetch the IRQ to be used */
2155 irq = this_dev->irq;
2156 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2158 /* Check if I/O accesses are enabled */
2159 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2160 if (!(status & PCI_COMMAND_IO)) continue;
2162 /* Search for a valid SROM attached to this DECchip */
2163 DevicePresent(dev, DE4X5_APROM);
2164 for (j=0, i=0; i<ETH_ALEN; i++) {
2165 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2167 if (j != 0 && j != 6 * 0xff) {
2168 last.chipset = device;
2171 for (i=0; i<ETH_ALEN; i++) {
2172 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2180 ** PCI bus I/O device probe
2181 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2182 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2183 ** enabled by the user first in the set up utility. Hence we just check for
2184 ** enabled features and silently ignore the card if they're not.
2186 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2187 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2188 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2189 ** PC doesn't conform to the PCI standard)!
2191 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2192 ** kernels use the V0.535[n] drivers.
2195 static int de4x5_pci_probe(struct pci_dev *pdev,
2196 const struct pci_device_id *ent)
2198 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2199 u_short vendor, status;
2200 u_int irq = 0, device;
2201 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2203 struct net_device *dev;
2204 struct de4x5_private *lp;
2206 dev_num = PCI_SLOT(pdev->devfn);
2207 pb = pdev->bus->number;
2209 if (io) { /* probe a single PCI device */
2210 pbus = (u_short)(io >> 8);
2211 dnum = (u_short)(io & 0xff);
2212 if ((pbus != pb) || (dnum != dev_num))
2216 vendor = pdev->vendor;
2217 device = pdev->device << 8;
2218 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2221 /* Ok, the device seems to be for us. */
2222 if ((error = pci_enable_device (pdev)))
2225 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2230 lp = netdev_priv(dev);
2234 /* Search for an SROM on this bus */
2235 if (lp->bus_num != pb) {
2237 srom_search(dev, pdev);
2240 /* Get the chip configuration revision register */
2241 lp->cfrv = pdev->revision;
2243 /* Set the device number information */
2244 lp->device = dev_num;
2247 /* Set the chipset information */
2249 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2251 lp->chipset = device;
2253 /* Get the board I/O address (64 bits on sparc64) */
2254 iobase = pci_resource_start(pdev, 0);
2256 /* Fetch the IRQ to be used */
2258 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2263 /* Check if I/O accesses and Bus Mastering are enabled */
2264 pci_read_config_word(pdev, PCI_COMMAND, &status);
2266 if (!(status & PCI_COMMAND_IO)) {
2267 status |= PCI_COMMAND_IO;
2268 pci_write_config_word(pdev, PCI_COMMAND, status);
2269 pci_read_config_word(pdev, PCI_COMMAND, &status);
2271 #endif /* __powerpc__ */
2272 if (!(status & PCI_COMMAND_IO)) {
2277 if (!(status & PCI_COMMAND_MASTER)) {
2278 status |= PCI_COMMAND_MASTER;
2279 pci_write_config_word(pdev, PCI_COMMAND, status);
2280 pci_read_config_word(pdev, PCI_COMMAND, &status);
2282 if (!(status & PCI_COMMAND_MASTER)) {
2287 /* Check the latency timer for values >= 0x60 */
2288 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2290 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2293 DevicePresent(dev, DE4X5_APROM);
2295 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2302 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2309 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2313 pci_disable_device (pdev);
2317 static void de4x5_pci_remove(struct pci_dev *pdev)
2319 struct net_device *dev;
2322 dev = pci_get_drvdata(pdev);
2323 iobase = dev->base_addr;
2325 unregister_netdev (dev);
2327 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2328 pci_disable_device (pdev);
2331 static DEFINE_PCI_DEVICE_TABLE(de4x5_pci_tbl) = {
2332 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2333 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2334 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2335 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2336 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2337 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2338 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2339 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2343 static struct pci_driver de4x5_pci_driver = {
2345 .id_table = de4x5_pci_tbl,
2346 .probe = de4x5_pci_probe,
2347 .remove = de4x5_pci_remove,
2353 ** Auto configure the media here rather than setting the port at compile
2354 ** time. This routine is called by de4x5_init() and when a loss of media is
2355 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2356 ** [TP] or no recent receive activity) to check whether the user has been
2357 ** sneaky and changed the port on us.
2360 autoconf_media(struct net_device *dev)
2362 struct de4x5_private *lp = netdev_priv(dev);
2363 u_long iobase = dev->base_addr;
2367 lp->c_media = AUTO; /* Bogus last media */
2368 inl(DE4X5_MFC); /* Zero the lost frames counter */
2378 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2379 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2380 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2381 ** The only way to test for that is to place a loopback packet onto the
2382 ** network and watch for errors. Since we're messing with the interrupt mask
2383 ** register, disable the board interrupts and do not allow any more packets to
2384 ** be queued to the hardware. Re-enable everything only when the media is
2386 ** I may have to "age out" locally queued packets so that the higher layer
2387 ** timeouts don't effectively duplicate packets on the network.
2390 dc21040_autoconf(struct net_device *dev)
2392 struct de4x5_private *lp = netdev_priv(dev);
2393 u_long iobase = dev->base_addr;
2394 int next_tick = DE4X5_AUTOSENSE_MS;
2397 switch (lp->media) {
2400 lp->tx_enable = false;
2402 de4x5_save_skbs(dev);
2403 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2405 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2406 lp->media = BNC_AUI;
2407 } else if (lp->autosense == EXT_SIA) {
2408 lp->media = EXT_SIA;
2412 lp->local_state = 0;
2413 next_tick = dc21040_autoconf(dev);
2417 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2418 TP_SUSPECT, test_tp);
2422 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2428 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2429 BNC_AUI_SUSPECT, ping_media);
2432 case BNC_AUI_SUSPECT:
2433 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2437 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2438 NC, EXT_SIA_SUSPECT, ping_media);
2441 case EXT_SIA_SUSPECT:
2442 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2446 /* default to TP for all */
2447 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2448 if (lp->media != lp->c_media) {
2449 de4x5_dbg_media(dev);
2450 lp->c_media = lp->media;
2453 lp->tx_enable = false;
2461 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2462 int next_state, int suspect_state,
2463 int (*fn)(struct net_device *, int))
2465 struct de4x5_private *lp = netdev_priv(dev);
2466 int next_tick = DE4X5_AUTOSENSE_MS;
2469 switch (lp->local_state) {
2471 reset_init_sia(dev, csr13, csr14, csr15);
2477 if (!lp->tx_enable) {
2478 linkBad = fn(dev, timeout);
2480 next_tick = linkBad & ~TIMER_CB;
2482 if (linkBad && (lp->autosense == AUTO)) {
2483 lp->local_state = 0;
2484 lp->media = next_state;
2486 de4x5_init_connection(dev);
2489 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2490 lp->media = suspect_state;
2500 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2501 int (*fn)(struct net_device *, int),
2502 int (*asfn)(struct net_device *))
2504 struct de4x5_private *lp = netdev_priv(dev);
2505 int next_tick = DE4X5_AUTOSENSE_MS;
2508 switch (lp->local_state) {
2511 lp->media = prev_state;
2514 next_tick = asfn(dev);
2519 linkBad = fn(dev, timeout);
2521 next_tick = linkBad & ~TIMER_CB;
2522 } else if (!linkBad) {
2524 lp->media = prev_state;
2535 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2536 ** before BNC, because the BNC port will indicate activity if it's not
2537 ** terminated correctly. The only way to test for that is to place a loopback
2538 ** packet onto the network and watch for errors. Since we're messing with
2539 ** the interrupt mask register, disable the board interrupts and do not allow
2540 ** any more packets to be queued to the hardware. Re-enable everything only
2541 ** when the media is found.
2544 dc21041_autoconf(struct net_device *dev)
2546 struct de4x5_private *lp = netdev_priv(dev);
2547 u_long iobase = dev->base_addr;
2548 s32 sts, irqs, irq_mask, imr, omr;
2549 int next_tick = DE4X5_AUTOSENSE_MS;
2551 switch (lp->media) {
2554 lp->tx_enable = false;
2556 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2557 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2558 lp->media = TP; /* On chip auto negotiation is broken */
2559 } else if (lp->autosense == TP) {
2561 } else if (lp->autosense == BNC) {
2563 } else if (lp->autosense == AUI) {
2568 lp->local_state = 0;
2569 next_tick = dc21041_autoconf(dev);
2573 if (lp->timeout < 0) {
2574 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2575 outl(omr | OMR_FDX, DE4X5_OMR);
2577 irqs = STS_LNF | STS_LNP;
2578 irq_mask = IMR_LFM | IMR_LPM;
2579 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2581 next_tick = sts & ~TIMER_CB;
2583 if (sts & STS_LNP) {
2588 next_tick = dc21041_autoconf(dev);
2593 if (!lp->tx_enable) {
2596 sts = test_ans(dev, irqs, irq_mask, 3000);
2598 next_tick = sts & ~TIMER_CB;
2600 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2602 next_tick = dc21041_autoconf(dev);
2604 lp->local_state = 1;
2605 de4x5_init_connection(dev);
2608 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2609 lp->media = ANS_SUSPECT;
2615 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2619 if (!lp->tx_enable) {
2620 if (lp->timeout < 0) {
2621 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2622 outl(omr & ~OMR_FDX, DE4X5_OMR);
2624 irqs = STS_LNF | STS_LNP;
2625 irq_mask = IMR_LFM | IMR_LPM;
2626 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2628 next_tick = sts & ~TIMER_CB;
2630 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2631 if (inl(DE4X5_SISR) & SISR_NRA) {
2632 lp->media = AUI; /* Non selected port activity */
2636 next_tick = dc21041_autoconf(dev);
2638 lp->local_state = 1;
2639 de4x5_init_connection(dev);
2642 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2643 lp->media = TP_SUSPECT;
2649 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2653 if (!lp->tx_enable) {
2654 if (lp->timeout < 0) {
2655 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2656 outl(omr & ~OMR_FDX, DE4X5_OMR);
2660 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2662 next_tick = sts & ~TIMER_CB;
2664 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2666 next_tick = dc21041_autoconf(dev);
2668 lp->local_state = 1;
2669 de4x5_init_connection(dev);
2672 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2673 lp->media = AUI_SUSPECT;
2679 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2683 switch (lp->local_state) {
2685 if (lp->timeout < 0) {
2686 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2687 outl(omr & ~OMR_FDX, DE4X5_OMR);
2691 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2693 next_tick = sts & ~TIMER_CB;
2695 lp->local_state++; /* Ensure media connected */
2696 next_tick = dc21041_autoconf(dev);
2701 if (!lp->tx_enable) {
2702 if ((sts = ping_media(dev, 3000)) < 0) {
2703 next_tick = sts & ~TIMER_CB;
2706 lp->local_state = 0;
2709 de4x5_init_connection(dev);
2712 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2713 lp->media = BNC_SUSPECT;
2721 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2725 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2726 outl(omr | OMR_FDX, DE4X5_OMR);
2727 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2728 if (lp->media != lp->c_media) {
2729 de4x5_dbg_media(dev);
2730 lp->c_media = lp->media;
2733 lp->tx_enable = false;
2741 ** Some autonegotiation chips are broken in that they do not return the
2742 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2743 ** register, except at the first power up negotiation.
2746 dc21140m_autoconf(struct net_device *dev)
2748 struct de4x5_private *lp = netdev_priv(dev);
2749 int ana, anlpa, cap, cr, slnk, sr;
2750 int next_tick = DE4X5_AUTOSENSE_MS;
2751 u_long imr, omr, iobase = dev->base_addr;
2755 if (lp->timeout < 0) {
2757 lp->tx_enable = false;
2759 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2761 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2762 next_tick &= ~TIMER_CB;
2765 if (srom_map_media(dev) < 0) {
2769 srom_exec(dev, lp->phy[lp->active].gep);
2770 if (lp->infoblock_media == ANS) {
2771 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2772 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2775 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2777 if (lp->autosense == _100Mb) {
2779 } else if (lp->autosense == _10Mb) {
2781 } else if ((lp->autosense == AUTO) &&
2782 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2783 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2784 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2785 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2787 } else if (lp->autosense == AUTO) {
2788 lp->media = SPD_DET;
2789 } else if (is_spd_100(dev) && is_100_up(dev)) {
2795 lp->local_state = 0;
2796 next_tick = dc21140m_autoconf(dev);
2801 switch (lp->local_state) {
2803 if (lp->timeout < 0) {
2804 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2806 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2808 next_tick = cr & ~TIMER_CB;
2811 lp->local_state = 0;
2812 lp->media = SPD_DET;
2816 next_tick = dc21140m_autoconf(dev);
2821 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000)) < 0) {
2822 next_tick = sr & ~TIMER_CB;
2824 lp->media = SPD_DET;
2825 lp->local_state = 0;
2826 if (sr) { /* Success! */
2827 lp->tmp = MII_SR_ASSC;
2828 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2829 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2830 if (!(anlpa & MII_ANLPA_RF) &&
2831 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2832 if (cap & MII_ANA_100M) {
2833 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
2835 } else if (cap & MII_ANA_10M) {
2836 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
2841 } /* Auto Negotiation failed to finish */
2842 next_tick = dc21140m_autoconf(dev);
2843 } /* Auto Negotiation failed to start */
2848 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2849 if (lp->timeout < 0) {
2850 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2851 (~gep_rd(dev) & GEP_LNP));
2854 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2855 next_tick = slnk & ~TIMER_CB;
2857 if (is_spd_100(dev) && is_100_up(dev)) {
2859 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2864 next_tick = dc21140m_autoconf(dev);
2868 case _100Mb: /* Set 100Mb/s */
2870 if (!lp->tx_enable) {
2872 de4x5_init_connection(dev);
2874 if (!lp->linkOK && (lp->autosense == AUTO)) {
2875 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2878 next_tick = DE4X5_AUTOSENSE_MS;
2886 case _10Mb: /* Set 10Mb/s */
2888 if (!lp->tx_enable) {
2890 de4x5_init_connection(dev);
2892 if (!lp->linkOK && (lp->autosense == AUTO)) {
2893 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2896 next_tick = DE4X5_AUTOSENSE_MS;
2903 if (lp->media != lp->c_media) {
2904 de4x5_dbg_media(dev);
2905 lp->c_media = lp->media;
2908 lp->tx_enable = false;
2916 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2917 ** changing how I figure out the media - but trying to keep it backwards
2918 ** compatible with the de500-xa and de500-aa.
2919 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2920 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2921 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2923 ** When autonegotiation is working, the ANS part searches the SROM for
2924 ** the highest common speed (TP) link that both can run and if that can
2925 ** be full duplex. That infoblock is executed and then the link speed set.
2927 ** Only _10Mb and _100Mb are tested here.
2930 dc2114x_autoconf(struct net_device *dev)
2932 struct de4x5_private *lp = netdev_priv(dev);
2933 u_long iobase = dev->base_addr;
2934 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2935 int next_tick = DE4X5_AUTOSENSE_MS;
2937 switch (lp->media) {
2939 if (lp->timeout < 0) {
2941 lp->tx_enable = false;
2944 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2945 if (lp->params.autosense & ~AUTO) {
2946 srom_map_media(dev); /* Fixed media requested */
2947 if (lp->media != lp->params.autosense) {
2955 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2956 next_tick &= ~TIMER_CB;
2958 if (lp->autosense == _100Mb) {
2960 } else if (lp->autosense == _10Mb) {
2962 } else if (lp->autosense == TP) {
2964 } else if (lp->autosense == BNC) {
2966 } else if (lp->autosense == AUI) {
2969 lp->media = SPD_DET;
2970 if ((lp->infoblock_media == ANS) &&
2971 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2972 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2973 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2974 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2978 lp->local_state = 0;
2979 next_tick = dc2114x_autoconf(dev);
2984 switch (lp->local_state) {
2986 if (lp->timeout < 0) {
2987 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2989 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, false, 500);
2991 next_tick = cr & ~TIMER_CB;
2994 lp->local_state = 0;
2995 lp->media = SPD_DET;
2999 next_tick = dc2114x_autoconf(dev);
3004 sr = test_mii_reg(dev, MII_SR, MII_SR_ASSC, true, 2000);
3006 next_tick = sr & ~TIMER_CB;
3008 lp->media = SPD_DET;
3009 lp->local_state = 0;
3010 if (sr) { /* Success! */
3011 lp->tmp = MII_SR_ASSC;
3012 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3013 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3014 if (!(anlpa & MII_ANLPA_RF) &&
3015 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3016 if (cap & MII_ANA_100M) {
3017 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) != 0;
3019 } else if (cap & MII_ANA_10M) {
3020 lp->fdx = (ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) != 0;
3024 } /* Auto Negotiation failed to finish */
3025 next_tick = dc2114x_autoconf(dev);
3026 } /* Auto Negotiation failed to start */
3032 if (!lp->tx_enable) {
3033 if (lp->timeout < 0) {
3034 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3035 outl(omr & ~OMR_FDX, DE4X5_OMR);
3039 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3041 next_tick = sts & ~TIMER_CB;
3043 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3045 next_tick = dc2114x_autoconf(dev);
3047 lp->local_state = 1;
3048 de4x5_init_connection(dev);
3051 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3052 lp->media = AUI_SUSPECT;
3058 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3062 switch (lp->local_state) {
3064 if (lp->timeout < 0) {
3065 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3066 outl(omr & ~OMR_FDX, DE4X5_OMR);
3070 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3072 next_tick = sts & ~TIMER_CB;
3074 lp->local_state++; /* Ensure media connected */
3075 next_tick = dc2114x_autoconf(dev);
3080 if (!lp->tx_enable) {
3081 if ((sts = ping_media(dev, 3000)) < 0) {
3082 next_tick = sts & ~TIMER_CB;
3085 lp->local_state = 0;
3089 de4x5_init_connection(dev);
3092 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3093 lp->media = BNC_SUSPECT;
3101 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3104 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3105 if (srom_map_media(dev) < 0) {
3110 if (lp->media == _100Mb) {
3111 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3112 lp->media = SPD_DET;
3113 return slnk & ~TIMER_CB;
3116 if (wait_for_link(dev) < 0) {
3117 lp->media = SPD_DET;
3118 return PDET_LINK_WAIT;
3121 if (lp->media == ANS) { /* Do MII parallel detection */
3122 if (is_spd_100(dev)) {
3127 next_tick = dc2114x_autoconf(dev);
3128 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3129 (((lp->media == _10Mb) || (lp->media == TP) ||
3130 (lp->media == BNC) || (lp->media == AUI)) &&
3132 next_tick = dc2114x_autoconf(dev);
3141 if (!lp->tx_enable) {
3143 de4x5_init_connection(dev);
3145 if (!lp->linkOK && (lp->autosense == AUTO)) {
3146 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3149 next_tick = DE4X5_AUTOSENSE_MS;
3157 if (!lp->tx_enable) {
3159 de4x5_init_connection(dev);
3161 if (!lp->linkOK && (lp->autosense == AUTO)) {
3162 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3165 next_tick = DE4X5_AUTOSENSE_MS;
3173 printk("Huh?: media:%02x\n", lp->media);
3182 srom_autoconf(struct net_device *dev)
3184 struct de4x5_private *lp = netdev_priv(dev);
3186 return lp->infoleaf_fn(dev);
3190 ** This mapping keeps the original media codes and FDX flag unchanged.
3191 ** While it isn't strictly necessary, it helps me for the moment...
3192 ** The early return avoids a media state / SROM media space clash.
3195 srom_map_media(struct net_device *dev)
3197 struct de4x5_private *lp = netdev_priv(dev);
3200 if (lp->infoblock_media == lp->media)
3203 switch(lp->infoblock_media) {
3205 if (!lp->params.fdx) return -1;
3208 if (lp->params.fdx && !lp->fdx) return -1;
3209 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3224 case SROM_100BASETF:
3225 if (!lp->params.fdx) return -1;
3228 if (lp->params.fdx && !lp->fdx) return -1;
3232 case SROM_100BASET4:
3236 case SROM_100BASEFF:
3237 if (!lp->params.fdx) return -1;
3240 if (lp->params.fdx && !lp->fdx) return -1;
3246 lp->fdx = lp->params.fdx;
3250 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3251 lp->infoblock_media);
3259 de4x5_init_connection(struct net_device *dev)
3261 struct de4x5_private *lp = netdev_priv(dev);
3262 u_long iobase = dev->base_addr;
3265 if (lp->media != lp->c_media) {
3266 de4x5_dbg_media(dev);
3267 lp->c_media = lp->media; /* Stop scrolling media messages */
3270 spin_lock_irqsave(&lp->lock, flags);
3271 de4x5_rst_desc_ring(dev);
3272 de4x5_setup_intr(dev);
3273 lp->tx_enable = true;
3274 spin_unlock_irqrestore(&lp->lock, flags);
3275 outl(POLL_DEMAND, DE4X5_TPD);
3277 netif_wake_queue(dev);
3281 ** General PHY reset function. Some MII devices don't reset correctly
3282 ** since their MII address pins can float at voltages that are dependent
3283 ** on the signal pin use. Do a double reset to ensure a reset.
3286 de4x5_reset_phy(struct net_device *dev)
3288 struct de4x5_private *lp = netdev_priv(dev);
3289 u_long iobase = dev->base_addr;
3292 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3293 if (lp->timeout < 0) {
3295 if (lp->phy[lp->active].rst) {
3296 srom_exec(dev, lp->phy[lp->active].rst);
3297 srom_exec(dev, lp->phy[lp->active].rst);
3298 } else if (lp->rst) { /* Type 5 infoblock reset */
3299 srom_exec(dev, lp->rst);
3300 srom_exec(dev, lp->rst);
3306 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3310 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, false, 500);
3312 } else if (lp->chipset == DC21140) {
3320 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3322 struct de4x5_private *lp = netdev_priv(dev);
3323 u_long iobase = dev->base_addr;
3326 if (lp->timeout < 0) {
3327 lp->timeout = msec/100;
3328 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3329 reset_init_sia(dev, csr13, csr14, csr15);
3332 /* set up the interrupt mask */
3333 outl(irq_mask, DE4X5_IMR);
3335 /* clear all pending interrupts */
3336 sts = inl(DE4X5_STS);
3337 outl(sts, DE4X5_STS);
3339 /* clear csr12 NRA and SRA bits */
3340 if ((lp->chipset == DC21041) || lp->useSROM) {
3341 csr12 = inl(DE4X5_SISR);
3342 outl(csr12, DE4X5_SISR);
3346 sts = inl(DE4X5_STS) & ~TIMER_CB;
3348 if (!(sts & irqs) && --lp->timeout) {
3349 sts = 100 | TIMER_CB;
3358 test_tp(struct net_device *dev, s32 msec)
3360 struct de4x5_private *lp = netdev_priv(dev);
3361 u_long iobase = dev->base_addr;
3364 if (lp->timeout < 0) {
3365 lp->timeout = msec/100;
3368 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3370 if (sisr && --lp->timeout) {
3371 sisr = 100 | TIMER_CB;
3380 ** Samples the 100Mb Link State Signal. The sample interval is important
3381 ** because too fast a rate can give erroneous results and confuse the
3382 ** speed sense algorithm.
3384 #define SAMPLE_INTERVAL 500 /* ms */
3385 #define SAMPLE_DELAY 2000 /* ms */
3387 test_for_100Mb(struct net_device *dev, int msec)
3389 struct de4x5_private *lp = netdev_priv(dev);
3390 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3392 if (lp->timeout < 0) {
3393 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3394 if (msec > SAMPLE_DELAY) {
3395 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3396 gep = SAMPLE_DELAY | TIMER_CB;
3399 lp->timeout = msec/SAMPLE_INTERVAL;
3403 if (lp->phy[lp->active].id || lp->useSROM) {
3404 gep = is_100_up(dev) | is_spd_100(dev);
3406 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3408 if (!(gep & ret) && --lp->timeout) {
3409 gep = SAMPLE_INTERVAL | TIMER_CB;
3418 wait_for_link(struct net_device *dev)
3420 struct de4x5_private *lp = netdev_priv(dev);
3422 if (lp->timeout < 0) {
3426 if (lp->timeout--) {
3440 test_mii_reg(struct net_device *dev, int reg, int mask, bool pol, long msec)
3442 struct de4x5_private *lp = netdev_priv(dev);
3444 u_long iobase = dev->base_addr;
3446 if (lp->timeout < 0) {
3447 lp->timeout = msec/100;
3450 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3451 test = (reg ^ (pol ? ~0 : 0)) & mask;
3453 if (test && --lp->timeout) {
3454 reg = 100 | TIMER_CB;
3463 is_spd_100(struct net_device *dev)
3465 struct de4x5_private *lp = netdev_priv(dev);
3466 u_long iobase = dev->base_addr;
3470 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3471 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3472 spd &= lp->phy[lp->active].spd.mask;
3473 } else if (!lp->useSROM) { /* de500-xa */
3474 spd = ((~gep_rd(dev)) & GEP_SLNK);
3476 if ((lp->ibn == 2) || !lp->asBitValid)
3477 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3479 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3480 (lp->linkOK & ~lp->asBitValid);
3487 is_100_up(struct net_device *dev)
3489 struct de4x5_private *lp = netdev_priv(dev);
3490 u_long iobase = dev->base_addr;
3493 /* Double read for sticky bits & temporary drops */
3494 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3495 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3496 } else if (!lp->useSROM) { /* de500-xa */
3497 return (~gep_rd(dev)) & GEP_SLNK;
3499 if ((lp->ibn == 2) || !lp->asBitValid)
3500 return (lp->chipset == DC21143) ? (~inl(DE4X5_SISR)&SISR_LS100) : 0;
3502 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3503 (lp->linkOK & ~lp->asBitValid);
3508 is_10_up(struct net_device *dev)
3510 struct de4x5_private *lp = netdev_priv(dev);
3511 u_long iobase = dev->base_addr;
3514 /* Double read for sticky bits & temporary drops */
3515 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3516 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS;
3517 } else if (!lp->useSROM) { /* de500-xa */
3518 return (~gep_rd(dev)) & GEP_LNP;
3520 if ((lp->ibn == 2) || !lp->asBitValid)
3521 return ((lp->chipset & ~0x00ff) == DC2114x) ?
3522 (~inl(DE4X5_SISR)&SISR_LS10):
3525 return (lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3526 (lp->linkOK & ~lp->asBitValid);
3531 is_anc_capable(struct net_device *dev)
3533 struct de4x5_private *lp = netdev_priv(dev);
3534 u_long iobase = dev->base_addr;
3536 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3537 return mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3538 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3539 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3546 ** Send a packet onto the media and watch for send errors that indicate the
3547 ** media is bad or unconnected.
3550 ping_media(struct net_device *dev, int msec)
3552 struct de4x5_private *lp = netdev_priv(dev);
3553 u_long iobase = dev->base_addr;
3556 if (lp->timeout < 0) {
3557 lp->timeout = msec/100;
3559 lp->tmp = lp->tx_new; /* Remember the ring position */
3560 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3561 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
3562 outl(POLL_DEMAND, DE4X5_TPD);
3565 sisr = inl(DE4X5_SISR);
3567 if ((!(sisr & SISR_NCR)) &&
3568 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3570 sisr = 100 | TIMER_CB;
3572 if ((!(sisr & SISR_NCR)) &&
3573 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3586 ** This function does 2 things: on Intels it kmalloc's another buffer to
3587 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3588 ** into which the packet is copied.
3590 static struct sk_buff *
3591 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3593 struct de4x5_private *lp = netdev_priv(dev);
3596 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(CONFIG_SPARC) && !defined(DE4X5_DO_MEMCPY)
3597 struct sk_buff *ret;
3600 p = netdev_alloc_skb(dev, IEEE802_3_SZ + DE4X5_ALIGN + 2);
3601 if (!p) return NULL;
3603 tmp = virt_to_bus(p->data);
3604 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3606 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3608 ret = lp->rx_skb[index];
3609 lp->rx_skb[index] = p;
3611 if ((u_long) ret > 1) {
3618 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3620 p = netdev_alloc_skb(dev, len + 2);
3621 if (!p) return NULL;
3623 skb_reserve(p, 2); /* Align */
3624 if (index < lp->rx_old) { /* Wrapped buffer */
3625 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3626 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3627 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3628 } else { /* Linear buffer */
3629 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3637 de4x5_free_rx_buffs(struct net_device *dev)
3639 struct de4x5_private *lp = netdev_priv(dev);
3642 for (i=0; i<lp->rxRingSize; i++) {
3643 if ((u_long) lp->rx_skb[i] > 1) {
3644 dev_kfree_skb(lp->rx_skb[i]);
3646 lp->rx_ring[i].status = 0;
3647 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3652 de4x5_free_tx_buffs(struct net_device *dev)
3654 struct de4x5_private *lp = netdev_priv(dev);
3657 for (i=0; i<lp->txRingSize; i++) {
3659 de4x5_free_tx_buff(lp, i);
3660 lp->tx_ring[i].status = 0;
3663 /* Unload the locally queued packets */
3664 __skb_queue_purge(&lp->cache.queue);
3668 ** When a user pulls a connection, the DECchip can end up in a
3669 ** 'running - waiting for end of transmission' state. This means that we
3670 ** have to perform a chip soft reset to ensure that we can synchronize
3671 ** the hardware and software and make any media probes using a loopback
3672 ** packet meaningful.
3675 de4x5_save_skbs(struct net_device *dev)
3677 struct de4x5_private *lp = netdev_priv(dev);
3678 u_long iobase = dev->base_addr;
3681 if (!lp->cache.save_cnt) {
3683 de4x5_tx(dev); /* Flush any sent skb's */
3684 de4x5_free_tx_buffs(dev);
3685 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3686 de4x5_sw_reset(dev);
3687 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3688 lp->cache.save_cnt++;
3694 de4x5_rst_desc_ring(struct net_device *dev)
3696 struct de4x5_private *lp = netdev_priv(dev);
3697 u_long iobase = dev->base_addr;
3701 if (lp->cache.save_cnt) {
3703 outl(lp->dma_rings, DE4X5_RRBA);
3704 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3707 lp->rx_new = lp->rx_old = 0;
3708 lp->tx_new = lp->tx_old = 0;
3710 for (i = 0; i < lp->rxRingSize; i++) {
3711 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3714 for (i = 0; i < lp->txRingSize; i++) {
3715 lp->tx_ring[i].status = cpu_to_le32(0);
3719 lp->cache.save_cnt--;
3725 de4x5_cache_state(struct net_device *dev, int flag)
3727 struct de4x5_private *lp = netdev_priv(dev);
3728 u_long iobase = dev->base_addr;
3731 case DE4X5_SAVE_STATE:
3732 lp->cache.csr0 = inl(DE4X5_BMR);
3733 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3734 lp->cache.csr7 = inl(DE4X5_IMR);
3737 case DE4X5_RESTORE_STATE:
3738 outl(lp->cache.csr0, DE4X5_BMR);
3739 outl(lp->cache.csr6, DE4X5_OMR);
3740 outl(lp->cache.csr7, DE4X5_IMR);
3741 if (lp->chipset == DC21140) {
3742 gep_wr(lp->cache.gepc, dev);
3743 gep_wr(lp->cache.gep, dev);
3745 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3753 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3755 struct de4x5_private *lp = netdev_priv(dev);
3757 __skb_queue_tail(&lp->cache.queue, skb);
3761 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3763 struct de4x5_private *lp = netdev_priv(dev);
3765 __skb_queue_head(&lp->cache.queue, skb);
3768 static struct sk_buff *
3769 de4x5_get_cache(struct net_device *dev)
3771 struct de4x5_private *lp = netdev_priv(dev);
3773 return __skb_dequeue(&lp->cache.queue);
3777 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3778 ** is received and the auto-negotiation status is NWAY OK.
3781 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3783 struct de4x5_private *lp = netdev_priv(dev);
3784 u_long iobase = dev->base_addr;
3787 if (lp->timeout < 0) {
3788 lp->timeout = msec/100;
3789 outl(irq_mask, DE4X5_IMR);
3791 /* clear all pending interrupts */
3792 sts = inl(DE4X5_STS);
3793 outl(sts, DE4X5_STS);
3796 ans = inl(DE4X5_SISR) & SISR_ANS;
3797 sts = inl(DE4X5_STS) & ~TIMER_CB;
3799 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3800 sts = 100 | TIMER_CB;
3809 de4x5_setup_intr(struct net_device *dev)
3811 struct de4x5_private *lp = netdev_priv(dev);
3812 u_long iobase = dev->base_addr;
3815 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3818 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3819 outl(sts, DE4X5_STS);
3828 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3830 struct de4x5_private *lp = netdev_priv(dev);
3831 u_long iobase = dev->base_addr;
3836 srom_exec(dev, lp->phy[lp->active].rst);
3837 srom_exec(dev, lp->phy[lp->active].gep);
3838 outl(1, DE4X5_SICR);
3841 csr15 = lp->cache.csr15;
3842 csr14 = lp->cache.csr14;
3843 csr13 = lp->cache.csr13;
3844 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3845 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3848 outl(csr15, DE4X5_SIGR);
3850 outl(csr14, DE4X5_STRR);
3851 outl(csr13, DE4X5_SICR);
3857 ** Create a loopback ethernet packet
3860 create_packet(struct net_device *dev, char *frame, int len)
3865 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3866 *buf++ = dev->dev_addr[i];
3868 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3869 *buf++ = dev->dev_addr[i];
3872 *buf++ = 0; /* Packet length (2 bytes) */
3877 ** Look for a particular board name in the EISA configuration space
3880 EISA_signature(char *name, struct device *device)
3882 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3883 struct eisa_device *edev;
3886 edev = to_eisa_device (device);
3887 i = edev->id.driver_data;
3889 if (i >= 0 && i < siglen) {
3890 strcpy (name, de4x5_signatures[i]);
3894 return status; /* return the device name string */
3898 ** Look for a particular board name in the PCI configuration space
3901 PCI_signature(char *name, struct de4x5_private *lp)
3903 int i, status = 0, siglen = ARRAY_SIZE(de4x5_signatures);
3905 if (lp->chipset == DC21040) {
3906 strcpy(name, "DE434/5");
3908 } else { /* Search for a DEC name in the SROM */
3909 int tmp = *((char *)&lp->srom + 19) * 3;
3910 strncpy(name, (char *)&lp->srom + 26 + tmp, 8);
3913 for (i=0; i<siglen; i++) {
3914 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3919 } else { /* Use chip name to avoid confusion */
3920 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3921 ((lp->chipset == DC21041) ? "DC21041" :
3922 ((lp->chipset == DC21140) ? "DC21140" :
3923 ((lp->chipset == DC21142) ? "DC21142" :
3924 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3927 if (lp->chipset != DC21041) {
3928 lp->useSROM = true; /* card is not recognisably DEC */
3930 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3938 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
3939 ** the DC21040, else read the SROM for the other chips.
3940 ** The SROM may not be present in a multi-MAC card, so first read the
3941 ** MAC address and check for a bad address. If there is a bad one then exit
3942 ** immediately with the prior srom contents intact (the h/w address will
3943 ** be fixed up later).
3946 DevicePresent(struct net_device *dev, u_long aprom_addr)
3949 struct de4x5_private *lp = netdev_priv(dev);
3951 if (lp->chipset == DC21040) {
3952 if (lp->bus == EISA) {
3953 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
3955 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
3957 } else { /* Read new srom */
3959 __le16 *p = (__le16 *)((char *)&lp->srom + SROM_HWADD);
3960 for (i=0; i<(ETH_ALEN>>1); i++) {
3961 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
3962 j += tmp; /* for check for 0:0:0:0:0:0 or ff:ff:ff:ff:ff:ff */
3963 *p = cpu_to_le16(tmp);
3965 if (j == 0 || j == 3 * 0xffff) {
3966 /* could get 0 only from all-0 and 3 * 0xffff only from all-1 */
3970 p = (__le16 *)&lp->srom;
3971 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
3972 tmp = srom_rd(aprom_addr, i);
3973 *p++ = cpu_to_le16(tmp);
3975 de4x5_dbg_srom(&lp->srom);
3980 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
3981 ** pointer correctly (at least on my DE425 EISA card), this routine should do
3982 ** it...from depca.c.
3985 enet_addr_rst(u_long aprom_addr)
3992 char Sig[sizeof(u32) << 1];
3998 dev.llsig.a = ETH_PROM_SIG;
3999 dev.llsig.b = ETH_PROM_SIG;
4000 sigLength = sizeof(u32) << 1;
4002 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4003 data = inb(aprom_addr);
4004 if (dev.Sig[j] == data) { /* track signature */
4006 } else { /* lost signature; begin search again */
4007 if (data == dev.Sig[0]) { /* rare case.... */
4017 ** For the bad status case and no SROM, then add one to the previous
4018 ** address. However, need to add one backwards in case we have 0xff
4019 ** as one or more of the bytes. Only the last 3 bytes should be checked
4020 ** as the first three are invariant - assigned to an organisation.
4023 get_hw_addr(struct net_device *dev)
4025 u_long iobase = dev->base_addr;
4026 int broken, i, k, tmp, status = 0;
4028 struct de4x5_private *lp = netdev_priv(dev);
4030 broken = de4x5_bad_srom(lp);
4032 for (i=0,k=0,j=0;j<3;j++) {
4034 if (k > 0xffff) k-=0xffff;
4036 if (lp->bus == PCI) {
4037 if (lp->chipset == DC21040) {
4038 while ((tmp = inl(DE4X5_APROM)) < 0);
4040 dev->dev_addr[i++] = (u_char) tmp;
4041 while ((tmp = inl(DE4X5_APROM)) < 0);
4042 k += (u_short) (tmp << 8);
4043 dev->dev_addr[i++] = (u_char) tmp;
4044 } else if (!broken) {
4045 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4046 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4047 } else if ((broken == SMC) || (broken == ACCTON)) {
4048 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4049 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4052 k += (u_char) (tmp = inb(EISA_APROM));
4053 dev->dev_addr[i++] = (u_char) tmp;
4054 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4055 dev->dev_addr[i++] = (u_char) tmp;
4058 if (k > 0xffff) k-=0xffff;
4060 if (k == 0xffff) k=0;
4062 if (lp->bus == PCI) {
4063 if (lp->chipset == DC21040) {
4064 while ((tmp = inl(DE4X5_APROM)) < 0);
4065 chksum = (u_char) tmp;
4066 while ((tmp = inl(DE4X5_APROM)) < 0);
4067 chksum |= (u_short) (tmp << 8);
4068 if ((k != chksum) && (dec_only)) status = -1;
4071 chksum = (u_char) inb(EISA_APROM);
4072 chksum |= (u_short) (inb(EISA_APROM) << 8);
4073 if ((k != chksum) && (dec_only)) status = -1;
4076 /* If possible, try to fix a broken card - SMC only so far */
4077 srom_repair(dev, broken);
4079 #ifdef CONFIG_PPC_PMAC
4081 ** If the address starts with 00 a0, we have to bit-reverse
4082 ** each byte of the address.
4084 if ( machine_is(powermac) &&
4085 (dev->dev_addr[0] == 0) &&
4086 (dev->dev_addr[1] == 0xa0) )
4088 for (i = 0; i < ETH_ALEN; ++i)
4090 int x = dev->dev_addr[i];
4091 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4092 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4093 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4096 #endif /* CONFIG_PPC_PMAC */
4098 /* Test for a bad enet address */
4099 status = test_bad_enet(dev, status);
4105 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4106 ** didn't seem to work here...?
4109 de4x5_bad_srom(struct de4x5_private *lp)
4113 for (i = 0; i < ARRAY_SIZE(enet_det); i++) {
4114 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4115 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4118 } else if (i == 1) {
4129 de4x5_strncmp(char *a, char *b, int n)
4133 for (;n && !ret; n--) {
4141 srom_repair(struct net_device *dev, int card)
4143 struct de4x5_private *lp = netdev_priv(dev);
4147 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4148 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4149 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4156 ** Assume that the irq's do not follow the PCI spec - this is seems
4157 ** to be true so far (2 for 2).
4160 test_bad_enet(struct net_device *dev, int status)
4162 struct de4x5_private *lp = netdev_priv(dev);
4165 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4166 if ((tmp == 0) || (tmp == 0x5fa)) {
4167 if ((lp->chipset == last.chipset) &&
4168 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4169 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4170 for (i=ETH_ALEN-1; i>2; --i) {
4171 dev->dev_addr[i] += 1;
4172 if (dev->dev_addr[i] != 0) break;
4174 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4175 if (!an_exception(lp)) {
4176 dev->irq = last.irq;
4181 } else if (!status) {
4182 last.chipset = lp->chipset;
4183 last.bus = lp->bus_num;
4184 last.irq = dev->irq;
4185 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4192 ** List of board exceptions with correctly wired IRQs
4195 an_exception(struct de4x5_private *lp)
4197 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4198 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4209 srom_rd(u_long addr, u_char offset)
4211 sendto_srom(SROM_RD | SROM_SR, addr);
4213 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4214 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4215 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4217 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4221 srom_latch(u_int command, u_long addr)
4223 sendto_srom(command, addr);
4224 sendto_srom(command | DT_CLK, addr);
4225 sendto_srom(command, addr);
4229 srom_command(u_int command, u_long addr)
4231 srom_latch(command, addr);
4232 srom_latch(command, addr);
4233 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4237 srom_address(u_int command, u_long addr, u_char offset)
4242 for (i=0; i<6; i++, a <<= 1) {
4243 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4247 i = (getfrom_srom(addr) >> 3) & 0x01;
4251 srom_data(u_int command, u_long addr)
4257 for (i=0; i<16; i++) {
4258 sendto_srom(command | DT_CLK, addr);
4259 tmp = getfrom_srom(addr);
4260 sendto_srom(command, addr);
4262 word = (word << 1) | ((tmp >> 3) & 0x01);
4265 sendto_srom(command & 0x0000ff00, addr);
4272 srom_busy(u_int command, u_long addr)
4274 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4276 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4280 sendto_srom(command & 0x0000ff00, addr);
4285 sendto_srom(u_int command, u_long addr)
4287 outl(command, addr);
4292 getfrom_srom(u_long addr)
4303 srom_infoleaf_info(struct net_device *dev)
4305 struct de4x5_private *lp = netdev_priv(dev);
4309 /* Find the infoleaf decoder function that matches this chipset */
4310 for (i=0; i<INFOLEAF_SIZE; i++) {
4311 if (lp->chipset == infoleaf_array[i].chipset) break;
4313 if (i == INFOLEAF_SIZE) {
4314 lp->useSROM = false;
4315 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4320 lp->infoleaf_fn = infoleaf_array[i].fn;
4322 /* Find the information offset that this function should use */
4323 count = *((u_char *)&lp->srom + 19);
4324 p = (u_char *)&lp->srom + 26;
4327 for (i=count; i; --i, p+=3) {
4328 if (lp->device == *p) break;
4331 lp->useSROM = false;
4332 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4333 dev->name, lp->device);
4338 lp->infoleaf_offset = get_unaligned_le16(p + 1);
4344 ** This routine loads any type 1 or 3 MII info into the mii device
4345 ** struct and executes any type 5 code to reset PHY devices for this
4347 ** The info for the MII devices will be valid since the index used
4348 ** will follow the discovery process from MII address 1-31 then 0.
4351 srom_init(struct net_device *dev)
4353 struct de4x5_private *lp = netdev_priv(dev);
4354 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4358 if (lp->chipset == DC21140) {
4359 lp->cache.gepc = (*p++ | GEP_CTRL);
4360 gep_wr(lp->cache.gepc, dev);
4366 /* Jump the infoblocks to find types */
4367 for (;count; --count) {
4370 } else if (*(p+1) == 5) {
4371 type5_infoblock(dev, 1, p);
4372 p += ((*p & BLOCK_LEN) + 1);
4373 } else if (*(p+1) == 4) {
4374 p += ((*p & BLOCK_LEN) + 1);
4375 } else if (*(p+1) == 3) {
4376 type3_infoblock(dev, 1, p);
4377 p += ((*p & BLOCK_LEN) + 1);
4378 } else if (*(p+1) == 2) {
4379 p += ((*p & BLOCK_LEN) + 1);
4380 } else if (*(p+1) == 1) {
4381 type1_infoblock(dev, 1, p);
4382 p += ((*p & BLOCK_LEN) + 1);
4384 p += ((*p & BLOCK_LEN) + 1);
4390 ** A generic routine that writes GEP control, data and reset information
4391 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4394 srom_exec(struct net_device *dev, u_char *p)
4396 struct de4x5_private *lp = netdev_priv(dev);
4397 u_long iobase = dev->base_addr;
4398 u_char count = (p ? *p++ : 0);
4399 u_short *w = (u_short *)p;
4401 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4403 if (lp->chipset != DC21140) RESET_SIA;
4406 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4407 *p++ : get_unaligned_le16(w++)), dev);
4408 mdelay(2); /* 2ms per action */
4411 if (lp->chipset != DC21140) {
4412 outl(lp->cache.csr14, DE4X5_STRR);
4413 outl(lp->cache.csr13, DE4X5_SICR);
4418 ** Basically this function is a NOP since it will never be called,
4419 ** unless I implement the DC21041 SROM functions. There's no need
4420 ** since the existing code will be satisfactory for all boards.
4423 dc21041_infoleaf(struct net_device *dev)
4425 return DE4X5_AUTOSENSE_MS;
4429 dc21140_infoleaf(struct net_device *dev)
4431 struct de4x5_private *lp = netdev_priv(dev);
4433 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4434 int next_tick = DE4X5_AUTOSENSE_MS;
4436 /* Read the connection type */
4440 lp->cache.gepc = (*p++ | GEP_CTRL);
4445 /* Recursively figure out the info blocks */
4447 next_tick = dc_infoblock[COMPACT](dev, count, p);
4449 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4452 if (lp->tcount == count) {
4454 if (lp->media != lp->c_media) {
4455 de4x5_dbg_media(dev);
4456 lp->c_media = lp->media;
4460 lp->tx_enable = false;
4463 return next_tick & ~TIMER_CB;
4467 dc21142_infoleaf(struct net_device *dev)
4469 struct de4x5_private *lp = netdev_priv(dev);
4471 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4472 int next_tick = DE4X5_AUTOSENSE_MS;
4474 /* Read the connection type */
4480 /* Recursively figure out the info blocks */
4482 next_tick = dc_infoblock[COMPACT](dev, count, p);
4484 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4487 if (lp->tcount == count) {
4489 if (lp->media != lp->c_media) {
4490 de4x5_dbg_media(dev);
4491 lp->c_media = lp->media;
4495 lp->tx_enable = false;
4498 return next_tick & ~TIMER_CB;
4502 dc21143_infoleaf(struct net_device *dev)
4504 struct de4x5_private *lp = netdev_priv(dev);
4506 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4507 int next_tick = DE4X5_AUTOSENSE_MS;
4509 /* Read the connection type */
4515 /* Recursively figure out the info blocks */
4517 next_tick = dc_infoblock[COMPACT](dev, count, p);
4519 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4521 if (lp->tcount == count) {
4523 if (lp->media != lp->c_media) {
4524 de4x5_dbg_media(dev);
4525 lp->c_media = lp->media;
4529 lp->tx_enable = false;
4532 return next_tick & ~TIMER_CB;
4536 ** The compact infoblock is only designed for DC21140[A] chips, so
4537 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4540 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4542 struct de4x5_private *lp = netdev_priv(dev);
4545 /* Recursively figure out the info blocks */
4546 if (--count > lp->tcount) {
4547 if (*(p+COMPACT_LEN) < 128) {
4548 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4550 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4554 if ((lp->media == INIT) && (lp->timeout < 0)) {
4557 gep_wr(lp->cache.gepc, dev);
4558 lp->infoblock_media = (*p++) & COMPACT_MC;
4559 lp->cache.gep = *p++;
4563 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4564 lp->defMedium = (flags & 0x40) ? -1 : 0;
4565 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4566 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4567 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4570 de4x5_switch_mac_port(dev);
4573 return dc21140m_autoconf(dev);
4577 ** This block describes non MII media for the DC21140[A] only.
4580 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4582 struct de4x5_private *lp = netdev_priv(dev);
4583 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4585 /* Recursively figure out the info blocks */
4586 if (--count > lp->tcount) {
4587 if (*(p+len) < 128) {
4588 return dc_infoblock[COMPACT](dev, count, p+len);
4590 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4594 if ((lp->media == INIT) && (lp->timeout < 0)) {
4597 gep_wr(lp->cache.gepc, dev);
4599 lp->infoblock_media = (*p++) & BLOCK0_MC;
4600 lp->cache.gep = *p++;
4604 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4605 lp->defMedium = (flags & 0x40) ? -1 : 0;
4606 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4607 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4608 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4611 de4x5_switch_mac_port(dev);
4614 return dc21140m_autoconf(dev);
4617 /* These functions are under construction! */
4620 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4622 struct de4x5_private *lp = netdev_priv(dev);
4623 u_char len = (*p & BLOCK_LEN)+1;
4625 /* Recursively figure out the info blocks */
4626 if (--count > lp->tcount) {
4627 if (*(p+len) < 128) {
4628 return dc_infoblock[COMPACT](dev, count, p+len);
4630 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4635 if (lp->state == INITIALISED) {
4638 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4639 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4640 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4641 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4642 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4643 lp->phy[lp->active].ttm = get_unaligned_le16(p);
4645 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4648 lp->infoblock_csr6 = OMR_MII_100;
4650 lp->infoblock_media = ANS;
4652 de4x5_switch_mac_port(dev);
4655 return dc21140m_autoconf(dev);
4659 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4661 struct de4x5_private *lp = netdev_priv(dev);
4662 u_char len = (*p & BLOCK_LEN)+1;
4664 /* Recursively figure out the info blocks */
4665 if (--count > lp->tcount) {
4666 if (*(p+len) < 128) {
4667 return dc_infoblock[COMPACT](dev, count, p+len);
4669 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4673 if ((lp->media == INIT) && (lp->timeout < 0)) {
4677 lp->infoblock_media = (*p) & MEDIA_CODE;
4679 if ((*p++) & EXT_FIELD) {
4680 lp->cache.csr13 = get_unaligned_le16(p); p += 2;
4681 lp->cache.csr14 = get_unaligned_le16(p); p += 2;
4682 lp->cache.csr15 = get_unaligned_le16(p); p += 2;
4684 lp->cache.csr13 = CSR13;
4685 lp->cache.csr14 = CSR14;
4686 lp->cache.csr15 = CSR15;
4688 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4689 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16);
4690 lp->infoblock_csr6 = OMR_SIA;
4693 de4x5_switch_mac_port(dev);
4696 return dc2114x_autoconf(dev);
4700 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4702 struct de4x5_private *lp = netdev_priv(dev);
4703 u_char len = (*p & BLOCK_LEN)+1;
4705 /* Recursively figure out the info blocks */
4706 if (--count > lp->tcount) {
4707 if (*(p+len) < 128) {
4708 return dc_infoblock[COMPACT](dev, count, p+len);
4710 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4715 if (lp->state == INITIALISED) {
4718 if (MOTO_SROM_BUG) lp->active = 0;
4719 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4720 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4721 lp->phy[lp->active].mc = get_unaligned_le16(p); p += 2;
4722 lp->phy[lp->active].ana = get_unaligned_le16(p); p += 2;
4723 lp->phy[lp->active].fdx = get_unaligned_le16(p); p += 2;
4724 lp->phy[lp->active].ttm = get_unaligned_le16(p); p += 2;
4725 lp->phy[lp->active].mci = *p;
4727 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4730 if (MOTO_SROM_BUG) lp->active = 0;
4731 lp->infoblock_csr6 = OMR_MII_100;
4733 lp->infoblock_media = ANS;
4735 de4x5_switch_mac_port(dev);
4738 return dc2114x_autoconf(dev);
4742 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4744 struct de4x5_private *lp = netdev_priv(dev);
4745 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4747 /* Recursively figure out the info blocks */
4748 if (--count > lp->tcount) {
4749 if (*(p+len) < 128) {
4750 return dc_infoblock[COMPACT](dev, count, p+len);
4752 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4756 if ((lp->media == INIT) && (lp->timeout < 0)) {
4760 lp->infoblock_media = (*p++) & MEDIA_CODE;
4761 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4762 lp->cache.csr14 = CSR14;
4763 lp->cache.csr15 = CSR15;
4764 lp->cache.gepc = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4765 lp->cache.gep = ((s32)(get_unaligned_le16(p)) << 16); p += 2;
4769 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4770 lp->defMedium = (flags & 0x40) ? -1 : 0;
4771 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4772 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4773 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4776 de4x5_switch_mac_port(dev);
4779 return dc2114x_autoconf(dev);
4783 ** This block type provides information for resetting external devices
4784 ** (chips) through the General Purpose Register.
4787 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4789 struct de4x5_private *lp = netdev_priv(dev);
4790 u_char len = (*p & BLOCK_LEN)+1;
4792 /* Recursively figure out the info blocks */
4793 if (--count > lp->tcount) {
4794 if (*(p+len) < 128) {
4795 return dc_infoblock[COMPACT](dev, count, p+len);
4797 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4801 /* Must be initializing to run this code */
4802 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4805 srom_exec(dev, lp->rst);
4808 return DE4X5_AUTOSENSE_MS;
4816 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4818 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4819 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4820 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4821 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4822 mii_address(phyreg, ioaddr); /* PHY Register to read */
4823 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4825 return mii_rdata(ioaddr); /* Read data */
4829 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4831 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4832 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4833 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4834 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4835 mii_address(phyreg, ioaddr); /* PHY Register to write */
4836 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4837 data = mii_swap(data, 16); /* Swap data bit ordering */
4838 mii_wdata(data, 16, ioaddr); /* Write data */
4842 mii_rdata(u_long ioaddr)
4847 for (i=0; i<16; i++) {
4849 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4856 mii_wdata(int data, int len, u_long ioaddr)
4860 for (i=0; i<len; i++) {
4861 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4867 mii_address(u_char addr, u_long ioaddr)
4871 addr = mii_swap(addr, 5);
4872 for (i=0; i<5; i++) {
4873 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4879 mii_ta(u_long rw, u_long ioaddr)
4881 if (rw == MII_STWR) {
4882 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4883 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4885 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4890 mii_swap(int data, int len)
4894 for (i=0; i<len; i++) {
4904 sendto_mii(u32 command, int data, u_long ioaddr)
4908 j = (data & 1) << 17;
4909 outl(command | j, ioaddr);
4911 outl(command | MII_MDC | j, ioaddr);
4916 getfrom_mii(u32 command, u_long ioaddr)
4918 outl(command, ioaddr);
4920 outl(command | MII_MDC, ioaddr);
4923 return (inl(ioaddr) >> 19) & 1;
4927 ** Here's 3 ways to calculate the OUI from the ID registers.
4930 mii_get_oui(u_char phyaddr, u_long ioaddr)
4937 int i, r2, r3, ret=0;*/
4940 /* Read r2 and r3 */
4941 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
4942 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
4943 /* SEEQ and Cypress way * /
4944 / * Shuffle r2 and r3 * /
4946 r3 = ((r3>>10)|(r2<<6))&0x0ff;
4947 r2 = ((r2>>2)&0x3fff);
4949 / * Bit reverse r3 * /
4956 / * Bit reverse r2 * /
4957 for (i=0;i<16;i++) {
4963 / * Swap r2 bytes * /
4965 a.breg[0]=a.breg[1];
4968 return (a.reg<<8)|ret; */ /* SEEQ and Cypress way */
4969 /* return (r2<<6)|(u_int)(r3>>10); */ /* NATIONAL and BROADCOM way */
4970 return r2; /* (I did it) My way */
4974 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
4977 mii_get_phy(struct net_device *dev)
4979 struct de4x5_private *lp = netdev_priv(dev);
4980 u_long iobase = dev->base_addr;
4981 int i, j, k, n, limit=ARRAY_SIZE(phy_info);
4987 /* Search the MII address space for possible PHY devices */
4988 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
4989 lp->phy[lp->active].addr = i;
4990 if (i==0) n++; /* Count cycles */
4991 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
4992 id = mii_get_oui(i, DE4X5_MII);
4993 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
4994 for (j=0; j<limit; j++) { /* Search PHY table */
4995 if (id != phy_info[j].id) continue; /* ID match? */
4996 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
4997 if (k < DE4X5_MAX_PHY) {
4998 memcpy((char *)&lp->phy[k],
4999 (char *)&phy_info[j], sizeof(struct phy_table));
5000 lp->phy[k].addr = i;
5004 goto purgatory; /* Stop the search */
5008 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5009 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++);
5010 lp->phy[k].addr = i;
5012 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5013 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5014 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5017 printk("%s: Using generic MII device control. If the board doesn't operate,\nplease mail the following dump to the author:\n", dev->name);
5019 de4x5_debug |= DEBUG_MII;
5020 de4x5_dbg_mii(dev, k);
5027 if (lp->phy[0].id) { /* Reset the PHY devices */
5028 for (k=0; k < DE4X5_MAX_PHY && lp->phy[k].id; k++) { /*For each PHY*/
5029 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5030 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5032 de4x5_dbg_mii(dev, k);
5035 if (!lp->mii_cnt) lp->useMII = false;
5041 build_setup_frame(struct net_device *dev, int mode)
5043 struct de4x5_private *lp = netdev_priv(dev);
5045 char *pa = lp->setup_frame;
5047 /* Initialise the setup frame */
5049 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5052 if (lp->setup_f == HASH_PERF) {
5053 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5054 *(pa + i) = dev->dev_addr[i]; /* Host address */
5055 if (i & 0x01) pa += 2;
5057 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5059 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5060 *(pa + (i&1)) = dev->dev_addr[i];
5061 if (i & 0x01) pa += 4;
5063 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5064 *(pa + (i&1)) = (char) 0xff;
5065 if (i & 0x01) pa += 4;
5069 return pa; /* Points to the next entry */
5073 disable_ast(struct net_device *dev)
5075 struct de4x5_private *lp = netdev_priv(dev);
5076 del_timer_sync(&lp->timer);
5080 de4x5_switch_mac_port(struct net_device *dev)
5082 struct de4x5_private *lp = netdev_priv(dev);
5083 u_long iobase = dev->base_addr;
5088 /* Assert the OMR_PS bit in CSR6 */
5089 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5091 omr |= lp->infoblock_csr6;
5092 if (omr & OMR_PS) omr |= OMR_HBD;
5093 outl(omr, DE4X5_OMR);
5098 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5099 if (lp->chipset == DC21140) {
5100 gep_wr(lp->cache.gepc, dev);
5101 gep_wr(lp->cache.gep, dev);
5102 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5103 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5107 outl(omr, DE4X5_OMR);
5116 gep_wr(s32 data, struct net_device *dev)
5118 struct de4x5_private *lp = netdev_priv(dev);
5119 u_long iobase = dev->base_addr;
5121 if (lp->chipset == DC21140) {
5122 outl(data, DE4X5_GEP);
5123 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5124 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5129 gep_rd(struct net_device *dev)
5131 struct de4x5_private *lp = netdev_priv(dev);
5132 u_long iobase = dev->base_addr;
5134 if (lp->chipset == DC21140) {
5135 return inl(DE4X5_GEP);
5136 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5137 return inl(DE4X5_SIGR) & 0x000fffff;
5144 yawn(struct net_device *dev, int state)
5146 struct de4x5_private *lp = netdev_priv(dev);
5147 u_long iobase = dev->base_addr;
5149 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5151 if(lp->bus == EISA) {
5154 outb(WAKEUP, PCI_CFPM);
5159 outb(SNOOZE, PCI_CFPM);
5163 outl(0, DE4X5_SICR);
5164 outb(SLEEP, PCI_CFPM);
5168 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5171 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5176 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5180 outl(0, DE4X5_SICR);
5181 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5188 de4x5_parse_params(struct net_device *dev)
5190 struct de4x5_private *lp = netdev_priv(dev);
5193 lp->params.fdx = false;
5194 lp->params.autosense = AUTO;
5196 if (args == NULL) return;
5198 if ((p = strstr(args, dev->name))) {
5199 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5203 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = true;
5205 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5206 if (strstr(p, "TP")) {
5207 lp->params.autosense = TP;
5208 } else if (strstr(p, "TP_NW")) {
5209 lp->params.autosense = TP_NW;
5210 } else if (strstr(p, "BNC")) {
5211 lp->params.autosense = BNC;
5212 } else if (strstr(p, "AUI")) {
5213 lp->params.autosense = AUI;
5214 } else if (strstr(p, "BNC_AUI")) {
5215 lp->params.autosense = BNC;
5216 } else if (strstr(p, "10Mb")) {
5217 lp->params.autosense = _10Mb;
5218 } else if (strstr(p, "100Mb")) {
5219 lp->params.autosense = _100Mb;
5220 } else if (strstr(p, "AUTO")) {
5221 lp->params.autosense = AUTO;
5229 de4x5_dbg_open(struct net_device *dev)
5231 struct de4x5_private *lp = netdev_priv(dev);
5234 if (de4x5_debug & DEBUG_OPEN) {
5235 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5236 printk("\tphysical address: %pM\n", dev->dev_addr);
5237 printk("Descriptor head addresses:\n");
5238 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5239 printk("Descriptor addresses:\nRX: ");
5240 for (i=0;i<lp->rxRingSize-1;i++){
5242 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5245 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5247 for (i=0;i<lp->txRingSize-1;i++){
5249 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5252 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5253 printk("Descriptor buffers:\nRX: ");
5254 for (i=0;i<lp->rxRingSize-1;i++){
5256 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5259 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5261 for (i=0;i<lp->txRingSize-1;i++){
5263 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5266 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5267 printk("Ring size:\nRX: %d\nTX: %d\n",
5268 (short)lp->rxRingSize,
5269 (short)lp->txRingSize);
5274 de4x5_dbg_mii(struct net_device *dev, int k)
5276 struct de4x5_private *lp = netdev_priv(dev);
5277 u_long iobase = dev->base_addr;
5279 if (de4x5_debug & DEBUG_MII) {
5280 printk("\nMII device address: %d\n", lp->phy[k].addr);
5281 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5282 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5283 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5284 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5285 if (lp->phy[k].id != BROADCOM_T4) {
5286 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5287 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5289 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5290 if (lp->phy[k].id != BROADCOM_T4) {
5291 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5292 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5294 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5300 de4x5_dbg_media(struct net_device *dev)
5302 struct de4x5_private *lp = netdev_priv(dev);
5304 if (lp->media != lp->c_media) {
5305 if (de4x5_debug & DEBUG_MEDIA) {
5306 printk("%s: media is %s%s\n", dev->name,
5307 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5308 (lp->media == TP ? "TP" :
5309 (lp->media == ANS ? "TP/Nway" :
5310 (lp->media == BNC ? "BNC" :
5311 (lp->media == AUI ? "AUI" :
5312 (lp->media == BNC_AUI ? "BNC/AUI" :
5313 (lp->media == EXT_SIA ? "EXT SIA" :
5314 (lp->media == _100Mb ? "100Mb/s" :
5315 (lp->media == _10Mb ? "10Mb/s" :
5317 ))))))))), (lp->fdx?" full duplex.":"."));
5319 lp->c_media = lp->media;
5324 de4x5_dbg_srom(struct de4x5_srom *p)
5328 if (de4x5_debug & DEBUG_SROM) {
5329 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5330 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5331 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5332 printk("SROM version: %02x\n", (u_char)(p->version));
5333 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5335 printk("Hardware Address: %pM\n", p->ieee_addr);
5336 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5337 for (i=0; i<64; i++) {
5338 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5344 de4x5_dbg_rx(struct sk_buff *skb, int len)
5348 if (de4x5_debug & DEBUG_RX) {
5349 printk("R: %pM <- %pM len/SAP:%02x%02x [%d]\n",
5350 skb->data, &skb->data[6],
5351 (u_char)skb->data[12],
5352 (u_char)skb->data[13],
5354 for (j=0; len>0;j+=16, len-=16) {
5355 printk(" %03x: ",j);
5356 for (i=0; i<16 && i<len; i++) {
5357 printk("%02x ",(u_char)skb->data[i+j]);
5365 ** Perform IOCTL call functions here. Some are privileged operations and the
5366 ** effective uid is checked in those cases. In the normal course of events
5367 ** this function is only used for my testing.
5370 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5372 struct de4x5_private *lp = netdev_priv(dev);
5373 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5374 u_long iobase = dev->base_addr;
5375 int i, j, status = 0;
5385 case DE4X5_GET_HWADDR: /* Get the hardware address */
5386 ioc->len = ETH_ALEN;
5387 for (i=0; i<ETH_ALEN; i++) {
5388 tmp.addr[i] = dev->dev_addr[i];
5390 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5393 case DE4X5_SET_HWADDR: /* Set the hardware address */
5394 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5395 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5396 if (netif_queue_stopped(dev))
5398 netif_stop_queue(dev);
5399 for (i=0; i<ETH_ALEN; i++) {
5400 dev->dev_addr[i] = tmp.addr[i];
5402 build_setup_frame(dev, PHYS_ADDR_ONLY);
5403 /* Set up the descriptor and give ownership to the card */
5404 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5405 SETUP_FRAME_LEN, (struct sk_buff *)1);
5406 lp->tx_new = (lp->tx_new + 1) % lp->txRingSize;
5407 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5408 netif_wake_queue(dev); /* Unlock the TX ring */
5411 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5412 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5413 printk("%s: Boo!\n", dev->name);
5416 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5417 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5418 omr = inl(DE4X5_OMR);
5420 outl(omr, DE4X5_OMR);
5423 case DE4X5_GET_STATS: /* Get the driver statistics */
5425 struct pkt_stats statbuf;
5426 ioc->len = sizeof(statbuf);
5427 spin_lock_irqsave(&lp->lock, flags);
5428 memcpy(&statbuf, &lp->pktStats, ioc->len);
5429 spin_unlock_irqrestore(&lp->lock, flags);
5430 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5434 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5435 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5436 spin_lock_irqsave(&lp->lock, flags);
5437 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5438 spin_unlock_irqrestore(&lp->lock, flags);
5441 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5442 tmp.addr[0] = inl(DE4X5_OMR);
5443 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5446 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5447 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5448 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5449 outl(tmp.addr[0], DE4X5_OMR);
5452 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5454 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5455 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5456 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5457 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5458 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5459 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5460 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5461 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5463 if (copy_to_user(ioc->data, tmp.lval, ioc->len))
5467 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5471 tmp.addr[j++] = dev->irq;
5472 for (i=0; i<ETH_ALEN; i++) {
5473 tmp.addr[j++] = dev->dev_addr[i];
5475 tmp.addr[j++] = lp->rxRingSize;
5476 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5477 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5479 for (i=0;i<lp->rxRingSize-1;i++){
5481 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5484 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5485 for (i=0;i<lp->txRingSize-1;i++){
5487 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5490 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5492 for (i=0;i<lp->rxRingSize-1;i++){
5494 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5497 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5498 for (i=0;i<lp->txRingSize-1;i++){
5500 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5503 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5505 for (i=0;i<lp->rxRingSize;i++){
5506 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5508 for (i=0;i<lp->txRingSize;i++){
5509 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5512 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5513 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5514 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5515 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5516 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5517 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5518 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5519 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5520 tmp.lval[j>>2] = lp->chipset; j+=4;
5521 if (lp->chipset == DC21140) {
5522 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5524 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5525 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5526 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5527 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5529 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5530 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5531 tmp.lval[j>>2] = lp->active; j+=4;
5532 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5533 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5534 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5535 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5536 if (lp->phy[lp->active].id != BROADCOM_T4) {
5537 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5538 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5540 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5541 if (lp->phy[lp->active].id != BROADCOM_T4) {
5542 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5543 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5545 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5549 tmp.addr[j++] = lp->txRingSize;
5550 tmp.addr[j++] = netif_queue_stopped(dev);
5553 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5564 static int __init de4x5_module_init (void)
5569 err = pci_register_driver(&de4x5_pci_driver);
5572 err |= eisa_driver_register (&de4x5_eisa_driver);
5578 static void __exit de4x5_module_exit (void)
5581 pci_unregister_driver (&de4x5_pci_driver);
5584 eisa_driver_unregister (&de4x5_eisa_driver);
5588 module_init (de4x5_module_init);
5589 module_exit (de4x5_module_exit);