2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
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13 * without modification, are permitted provided that the following
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17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
50 CPL_RX_DATA_ACK = 0xD,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
55 CPL_CLOSE_LISTSRV_RPL = 0x20,
56 CPL_L2T_WRITE_RPL = 0x23,
57 CPL_PASS_OPEN_RPL = 0x24,
58 CPL_ACT_OPEN_RPL = 0x25,
59 CPL_PEER_CLOSE = 0x26,
60 CPL_ABORT_REQ_RSS = 0x2B,
61 CPL_ABORT_RPL_RSS = 0x2D,
63 CPL_CLOSE_CON_RPL = 0x32,
66 CPL_RDMA_CQE_READ_RSP = 0x36,
67 CPL_RDMA_CQE_ERR = 0x37,
69 CPL_SET_TCB_RPL = 0x3A,
71 CPL_RX_DDP_COMPLETE = 0x3F,
73 CPL_ACT_ESTABLISH = 0x40,
74 CPL_PASS_ESTABLISH = 0x41,
75 CPL_RX_DATA_DDP = 0x42,
76 CPL_PASS_ACCEPT_REQ = 0x44,
77 CPL_TRACE_PKT_T5 = 0x48,
78 CPL_RX_ISCSI_DDP = 0x49,
80 CPL_RDMA_READ_REQ = 0x60,
82 CPL_PASS_OPEN_REQ6 = 0x81,
83 CPL_ACT_OPEN_REQ6 = 0x83,
85 CPL_RDMA_TERMINATE = 0xA2,
86 CPL_RDMA_WRITE = 0xA4,
87 CPL_SGE_EGR_UPDATE = 0xA5,
90 CPL_ISCSI_DATA = 0xB2,
98 CPL_TX_PKT_LSO = 0xED,
106 CPL_ERR_TCAM_FULL = 3,
107 CPL_ERR_BAD_LENGTH = 15,
108 CPL_ERR_BAD_ROUTE = 18,
109 CPL_ERR_CONN_RESET = 20,
110 CPL_ERR_CONN_EXIST_SYNRECV = 21,
111 CPL_ERR_CONN_EXIST = 22,
112 CPL_ERR_ARP_MISS = 23,
113 CPL_ERR_BAD_SYN = 24,
114 CPL_ERR_CONN_TIMEDOUT = 30,
115 CPL_ERR_XMIT_TIMEDOUT = 31,
116 CPL_ERR_PERSIST_TIMEDOUT = 32,
117 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
118 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
119 CPL_ERR_RTX_NEG_ADVICE = 35,
120 CPL_ERR_PERSIST_NEG_ADVICE = 36,
121 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
122 CPL_ERR_ABORT_FAILED = 42,
123 CPL_ERR_IWARP_FLM = 50,
127 CPL_CONN_POLICY_AUTO = 0,
128 CPL_CONN_POLICY_ASK = 1,
129 CPL_CONN_POLICY_FILTER = 2,
130 CPL_CONN_POLICY_DENY = 3
142 ULP_CRC_HEADER = 1 << 0,
143 ULP_CRC_DATA = 1 << 1
147 CPL_ABORT_SEND_RST = 0,
151 enum { /* TX_PKT_XT checksum types */
170 #define CPL_OPCODE_S 24
171 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
172 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
173 #define TID_G(x) ((x) & 0xFFFFFF)
175 /* tid is assumed to be 24-bits */
176 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
178 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
180 /* extract the TID from a CPL command */
181 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
183 /* partitioning of TID fields that also carry a queue id */
185 #define TID_TID_M 0x3fff
186 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
189 #define TID_QID_M 0x3ff
190 #define TID_QID_V(x) ((x) << TID_QID_S)
191 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
195 #if defined(__LITTLE_ENDIAN_BITFIELD)
214 struct work_request_hdr {
222 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
224 #define WR_HDR struct work_request_hdr wr
226 /* option 0 fields */
228 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
231 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
233 #define RCV_BUFSIZ_S 12
234 #define RCV_BUFSIZ_M 0x3FFU
235 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
237 #define SMAC_SEL_S 28
238 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
241 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
243 #define WND_SCALE_S 50
244 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
246 #define KEEP_ALIVE_S 54
247 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
248 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
251 #define MSS_IDX_M 0xF
252 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
253 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
255 /* option 2 fields */
256 #define RSS_QUEUE_S 0
257 #define RSS_QUEUE_M 0x3FF
258 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
259 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
261 #define RSS_QUEUE_VALID_S 10
262 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
263 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
265 #define RX_FC_DISABLE_S 20
266 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
267 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
269 #define RX_FC_VALID_S 22
270 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
271 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
273 #define RX_CHANNEL_S 26
274 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
276 #define WND_SCALE_EN_S 28
277 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
278 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
280 #define T5_OPT_2_VALID_S 31
281 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
282 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
284 struct cpl_pass_open_req {
295 /* option 0 fields */
297 #define NO_CONG_V(x) ((x) << NO_CONG_S)
298 #define NO_CONG_F NO_CONG_V(1U)
301 #define DELACK_V(x) ((x) << DELACK_S)
302 #define DELACK_F DELACK_V(1U)
306 #define DSCP_V(x) ((x) << DSCP_S)
307 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
309 #define TCAM_BYPASS_S 48
310 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
311 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
314 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
315 #define NAGLE_F NAGLE_V(1ULL)
317 /* option 1 fields */
318 #define SYN_RSS_ENABLE_S 0
319 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
320 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
322 #define SYN_RSS_QUEUE_S 2
323 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
325 #define CONN_POLICY_S 22
326 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
328 struct cpl_pass_open_req6 {
341 struct cpl_pass_open_rpl {
347 struct cpl_pass_accept_rpl {
354 /* option 2 fields */
355 #define RX_COALESCE_VALID_S 11
356 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
357 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
359 #define RX_COALESCE_S 12
360 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
363 #define PACE_V(x) ((x) << PACE_S)
365 #define TX_QUEUE_S 23
366 #define TX_QUEUE_M 0x7
367 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
368 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
370 #define CCTRL_ECN_S 27
371 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
372 #define CCTRL_ECN_F CCTRL_ECN_V(1U)
374 #define TSTAMPS_EN_S 29
375 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
376 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
379 #define SACK_EN_V(x) ((x) << SACK_EN_S)
380 #define SACK_EN_F SACK_EN_V(1U)
382 struct cpl_t5_pass_accept_rpl {
391 struct cpl_act_open_req {
403 #define FILTER_TUPLE_S 24
404 #define FILTER_TUPLE_M 0xFFFFFFFFFF
405 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
406 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
407 struct cpl_t5_act_open_req {
420 struct cpl_act_open_req6 {
434 struct cpl_t5_act_open_req6 {
449 struct cpl_act_open_rpl {
454 /* cpl_act_open_rpl.atid_status fields */
455 #define AOPEN_STATUS_S 0
456 #define AOPEN_STATUS_M 0xFF
457 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
459 #define AOPEN_ATID_S 8
460 #define AOPEN_ATID_M 0xFFFFFF
461 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
463 struct cpl_pass_establish {
473 /* cpl_pass_establish.tos_stid fields */
474 #define PASS_OPEN_TID_S 0
475 #define PASS_OPEN_TID_M 0xFFFFFF
476 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
477 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
479 #define PASS_OPEN_TOS_S 24
480 #define PASS_OPEN_TOS_M 0xFF
481 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
482 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
484 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
485 #define TCPOPT_WSCALE_OK_S 5
486 #define TCPOPT_WSCALE_OK_M 0x1
487 #define TCPOPT_WSCALE_OK_G(x) \
488 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
490 #define TCPOPT_SACK_S 6
491 #define TCPOPT_SACK_M 0x1
492 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
494 #define TCPOPT_TSTAMP_S 7
495 #define TCPOPT_TSTAMP_M 0x1
496 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
498 #define TCPOPT_SND_WSCALE_S 8
499 #define TCPOPT_SND_WSCALE_M 0xF
500 #define TCPOPT_SND_WSCALE_G(x) \
501 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
503 #define TCPOPT_MSS_S 12
504 #define TCPOPT_MSS_M 0xF
505 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
507 struct cpl_act_establish {
524 /* cpl_get_tcb.reply_ctrl fields */
526 #define QUEUENO_V(x) ((x) << QUEUENO_S)
528 #define REPLY_CHAN_S 14
529 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
530 #define REPLY_CHAN_F REPLY_CHAN_V(1U)
532 #define NO_REPLY_S 15
533 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
534 #define NO_REPLY_F NO_REPLY_V(1U)
536 struct cpl_set_tcb_field {
545 /* cpl_set_tcb_field.word_cookie fields */
547 #define TCB_WORD(x) ((x) << TCB_WORD_S)
549 #define TCB_COOKIE_S 5
550 #define TCB_COOKIE_M 0x7
551 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
552 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
554 struct cpl_set_tcb_rpl {
562 struct cpl_close_con_req {
568 struct cpl_close_con_rpl {
576 struct cpl_close_listsvr_req {
583 /* additional cpl_close_listsvr_req.reply_ctrl field */
584 #define LISTSVR_IPV6_S 14
585 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
586 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
588 struct cpl_close_listsvr_rpl {
594 struct cpl_abort_req_rss {
600 struct cpl_abort_req {
609 struct cpl_abort_rpl_rss {
615 struct cpl_abort_rpl {
624 struct cpl_peer_close {
629 struct cpl_tid_release {
635 struct cpl_tx_pkt_core {
637 #define TXPKT_VF(x) ((x) << 0)
638 #define TXPKT_PF(x) ((x) << 8)
639 #define TXPKT_VF_VLD (1 << 11)
640 #define TXPKT_OVLAN_IDX(x) ((x) << 12)
641 #define TXPKT_INTF(x) ((x) << 16)
642 #define TXPKT_INS_OVLAN (1 << 21)
643 #define TXPKT_OPCODE(x) ((x) << 24)
647 #define TXPKT_CSUM_END(x) ((x) << 12)
648 #define TXPKT_CSUM_START(x) ((x) << 20)
649 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20)
650 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30)
651 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34)
652 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40)
653 #define TXPKT_VLAN(x) ((u64)(x) << 44)
654 #define TXPKT_VLAN_VLD (1ULL << 60)
655 #define TXPKT_IPCSUM_DIS (1ULL << 62)
656 #define TXPKT_L4CSUM_DIS (1ULL << 63)
661 struct cpl_tx_pkt_core c;
664 #define cpl_tx_pkt_xt cpl_tx_pkt
666 struct cpl_tx_pkt_lso_core {
668 #define LSO_TCPHDR_LEN(x) ((x) << 0)
669 #define LSO_IPHDR_LEN(x) ((x) << 4)
670 #define LSO_ETHHDR_LEN(x) ((x) << 16)
671 #define LSO_IPV6(x) ((x) << 20)
672 #define LSO_LAST_SLICE (1 << 22)
673 #define LSO_FIRST_SLICE (1 << 23)
674 #define LSO_OPCODE(x) ((x) << 24)
675 #define LSO_T5_XFER_SIZE(x) ((x) << 0)
680 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
683 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
684 #define LSO_TCPHDR_LEN_S 0
685 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
687 #define LSO_IPHDR_LEN_S 4
688 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
690 #define LSO_ETHHDR_LEN_S 16
691 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
693 #define LSO_IPV6_S 20
694 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
695 #define LSO_IPV6_F LSO_IPV6_V(1U)
697 #define LSO_LAST_SLICE_S 22
698 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
699 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
701 #define LSO_FIRST_SLICE_S 23
702 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
703 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
705 #define LSO_OPCODE_S 24
706 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
708 #define LSO_T5_XFER_SIZE_S 0
709 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
711 struct cpl_tx_pkt_lso {
713 struct cpl_tx_pkt_lso_core c;
714 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
717 struct cpl_iscsi_hdr {
727 /* cpl_iscsi_hdr.pdu_len_ddp fields */
728 #define ISCSI_PDU_LEN_S 0
729 #define ISCSI_PDU_LEN_M 0x7FFF
730 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
731 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
733 #define ISCSI_DDP_S 15
734 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
735 #define ISCSI_DDP_F ISCSI_DDP_V(1U)
743 #if defined(__LITTLE_ENDIAN_BITFIELD)
759 struct cpl_rx_data_ack {
765 /* cpl_rx_data_ack.ack_seq fields */
766 #define RX_CREDITS_S 0
767 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
769 #define RX_FORCE_ACK_S 28
770 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
771 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
774 struct rss_header rsshdr;
776 #if defined(__LITTLE_ENDIAN_BITFIELD)
798 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
799 #define RXF_PSH_F RXF_PSH_V(1U)
802 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
803 #define RXF_SYN_F RXF_SYN_V(1U)
806 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
807 #define RXF_UDP_F RXF_UDP_V(1U)
810 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
811 #define RXF_TCP_F RXF_TCP_V(1U)
814 #define RXF_IP_V(x) ((x) << RXF_IP_S)
815 #define RXF_IP_F RXF_IP_V(1U)
818 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
819 #define RXF_IP6_F RXF_IP6_V(1U)
821 #define RXF_SYN_COOKIE_S 26
822 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
823 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
825 #define RXF_FCOE_S 26
826 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
827 #define RXF_FCOE_F RXF_FCOE_V(1U)
830 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
831 #define RXF_LRO_F RXF_LRO_V(1U)
833 /* rx_pkt.l2info fields */
834 #define RX_ETHHDR_LEN_S 0
835 #define RX_ETHHDR_LEN_M 0x1F
836 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
837 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
839 #define RX_T5_ETHHDR_LEN_S 0
840 #define RX_T5_ETHHDR_LEN_M 0x3F
841 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
842 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
844 #define RX_MACIDX_S 8
845 #define RX_MACIDX_M 0x1FF
846 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
847 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
850 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
851 #define RXF_SYN_F RXF_SYN_V(1U)
854 #define RX_CHAN_M 0xF
855 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
856 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
858 /* rx_pkt.hdr_len fields */
859 #define RX_TCPHDR_LEN_S 0
860 #define RX_TCPHDR_LEN_M 0x3F
861 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
862 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
864 #define RX_IPHDR_LEN_S 6
865 #define RX_IPHDR_LEN_M 0x3FF
866 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
867 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
869 /* rx_pkt.err_vec fields */
870 #define RXERR_CSUM_S 13
871 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
872 #define RXERR_CSUM_F RXERR_CSUM_V(1U)
874 struct cpl_trace_pkt {
877 #if defined(__LITTLE_ENDIAN_BITFIELD)
895 struct cpl_t5_trace_pkt {
898 #if defined(__LITTLE_ENDIAN_BITFIELD)
917 struct cpl_l2t_write_req {
926 /* cpl_l2t_write_req.params fields */
927 #define L2T_W_INFO_S 2
928 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
930 #define L2T_W_PORT_S 8
931 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
933 #define L2T_W_NOREPLY_S 15
934 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
935 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
937 struct cpl_l2t_write_rpl {
943 struct cpl_rdma_terminate {
949 struct cpl_sge_egr_update {
955 /* cpl_sge_egr_update.ot fields */
957 #define EGR_QID_M 0x1FFFF
958 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
960 /* cpl_fw*.type values */
965 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1004 struct cpl_fw6_msg {
1012 /* cpl_fw6_msg.type values */
1014 FW6_TYPE_CMD_RPL = 0,
1015 FW6_TYPE_WR_RPL = 1,
1017 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1018 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1021 struct cpl_fw6_msg_ofld_connection_wr_rpl {
1023 __be32 tid; /* or atid in case of active failure */
1030 ULP_TX_MEM_READ = 2,
1031 ULP_TX_MEM_WRITE = 3,
1036 ULP_TX_SC_NOOP = 0x80,
1037 ULP_TX_SC_IMM = 0x81,
1038 ULP_TX_SC_DSGL = 0x82,
1039 ULP_TX_SC_ISGL = 0x83
1042 #define ULPTX_CMD_S 24
1043 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1045 struct ulptx_sge_pair {
1054 struct ulptx_sge_pair sge[0];
1057 #define ULPTX_NSGE_S 0
1058 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1060 #define ULPTX_MORE_S 23
1061 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1062 #define ULPTX_MORE_F ULPTX_MORE_V(1U)
1067 __be32 len16; /* command length */
1068 __be32 dlen; /* data length in 32-byte units */
1072 #define ULP_MEMIO_LOCK_S 31
1073 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1074 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1076 /* additional ulp_mem_io.cmd fields */
1077 #define ULP_MEMIO_ORDER_S 23
1078 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1079 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1081 #define T5_ULP_MEMIO_IMM_S 23
1082 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1083 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1085 #define T5_ULP_MEMIO_ORDER_S 22
1086 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1087 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1089 /* ulp_mem_io.lock_addr fields */
1090 #define ULP_MEMIO_ADDR_S 0
1091 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1093 /* ulp_mem_io.dlen fields */
1094 #define ULP_MEMIO_DATA_LEN_S 0
1095 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1097 #endif /* __T4_MSG_H */