2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 NCHAN = 4, /* # of HW channels */
42 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
43 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
44 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
45 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
46 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
47 TCB_SIZE = 128, /* TCB size */
48 NMTUS = 16, /* size of MTU table */
49 NCCTRL_WIN = 32, /* # of congestion control windows */
50 L2T_SIZE = 4096, /* # of L2T entries */
51 PM_NSTATS = 5, /* # of PM stats */
52 MBOX_LEN = 64, /* mailbox size in bytes */
53 TRACE_LEN = 112, /* length of trace data and mask */
54 FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
55 NWOL_PAT = 8, /* # of WoL patterns */
56 WOL_PAT_LEN = 128, /* length of WoL patterns */
60 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
61 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
62 CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
63 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
64 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
65 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
66 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
67 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
71 SF_PAGE_SIZE = 256, /* serial flash page size */
72 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
75 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
77 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
80 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
81 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
82 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
83 SGE_MAX_IQ_SIZE = 65520,
85 SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
86 SGE_TIMER_UPD_CIDX = 7, /* update cidx only */
88 SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */
90 SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */
91 SGE_INTRDST_IQ = 1, /* destination is an ingress queue */
93 SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */
94 SGE_UPDATEDEL_INTR = 1, /* interrupt */
95 SGE_UPDATEDEL_STPG = 2, /* status page */
96 SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */
98 SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */
99 SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */
100 SGE_HOSTFCMODE_STPG = 2, /* sent to status page */
101 SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */
103 SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
104 SGE_FETCHBURSTMIN_32B = 1,
105 SGE_FETCHBURSTMIN_64B = 2,
106 SGE_FETCHBURSTMIN_128B = 3,
108 SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
109 SGE_FETCHBURSTMAX_128B = 1,
110 SGE_FETCHBURSTMAX_256B = 2,
111 SGE_FETCHBURSTMAX_512B = 3,
113 SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
114 SGE_CIDXFLUSHTHRESH_2 = 1,
115 SGE_CIDXFLUSHTHRESH_4 = 2,
116 SGE_CIDXFLUSHTHRESH_8 = 3,
117 SGE_CIDXFLUSHTHRESH_16 = 4,
118 SGE_CIDXFLUSHTHRESH_32 = 5,
119 SGE_CIDXFLUSHTHRESH_64 = 6,
120 SGE_CIDXFLUSHTHRESH_128 = 7,
122 SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
125 /* PCI-e memory window access */
137 struct sge_qstat { /* data written to SGE queue status entries */
144 * Structure for last 128 bits of response descriptors
147 __be32 hdrbuflen_pidx;
148 __be32 pldbuflen_qid;
155 #define RSPD_NEWBUF 0x80000000U
156 #define RSPD_LEN(x) (((x) >> 0) & 0x7fffffffU)
157 #define RSPD_QID(x) RSPD_LEN(x)
159 #define RSPD_GEN(x) ((x) >> 7)
160 #define RSPD_TYPE(x) (((x) >> 4) & 3)
162 #define V_QINTR_CNT_EN 0x0
163 #define QINTR_CNT_EN 0x1
164 #define QINTR_TIMER_IDX(x) ((x) << 1)
165 #define QINTR_TIMER_IDX_GET(x) (((x) >> 1) & 0x7)
170 #define FLASH_START(start) ((start) * SF_SEC_SIZE)
171 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
175 * Various Expansion-ROM boot images, etc.
177 FLASH_EXP_ROM_START_SEC = 0,
178 FLASH_EXP_ROM_NSECS = 6,
179 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
180 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
183 * iSCSI Boot Firmware Table (iBFT) and other driver-related
186 FLASH_IBFT_START_SEC = 6,
187 FLASH_IBFT_NSECS = 1,
188 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
189 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
192 * Boot configuration data.
194 FLASH_BOOTCFG_START_SEC = 7,
195 FLASH_BOOTCFG_NSECS = 1,
196 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
197 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
200 * Location of firmware image in FLASH.
202 FLASH_FW_START_SEC = 8,
204 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
205 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
208 * iSCSI persistent/crash information.
210 FLASH_ISCSI_CRASH_START_SEC = 29,
211 FLASH_ISCSI_CRASH_NSECS = 1,
212 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
213 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
216 * FCoE persistent/crash information.
218 FLASH_FCOE_CRASH_START_SEC = 30,
219 FLASH_FCOE_CRASH_NSECS = 1,
220 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
221 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
224 * Location of Firmware Configuration File in FLASH. Since the FPGA
225 * "FLASH" is smaller we need to store the Configuration File in a
226 * different location -- which will overlap the end of the firmware
227 * image if firmware ever gets that large ...
229 FLASH_CFG_START_SEC = 31,
231 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
232 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
234 /* We don't support FLASH devices which can't support the full
235 * standard set of sections which we need for normal
238 FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
240 FLASH_FPGA_CFG_START_SEC = 15,
241 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
244 * Sectors 32-63 are reserved for FLASH failover.
249 #undef FLASH_MAX_SIZE
251 #endif /* __T4_HW_H */