2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/skbuff.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/if_vlan.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/jiffies.h>
42 #include <linux/prefetch.h>
43 #include <linux/export.h>
46 #ifdef CONFIG_NET_RX_BUSY_POLL
47 #include <net/busy_poll.h>
48 #endif /* CONFIG_NET_RX_BUSY_POLL */
49 #ifdef CONFIG_CHELSIO_T4_FCOE
50 #include <scsi/fc/fc_fcoe.h>
51 #endif /* CONFIG_CHELSIO_T4_FCOE */
54 #include "t4_values.h"
59 * Rx buffer size. We use largish buffers if possible but settle for single
60 * pages under memory shortage.
63 # define FL_PG_ORDER 0
65 # define FL_PG_ORDER (16 - PAGE_SHIFT)
68 /* RX_PULL_LEN should be <= RX_COPY_THRES */
69 #define RX_COPY_THRES 256
70 #define RX_PULL_LEN 128
73 * Main body length for sk_buffs used for Rx Ethernet packets with fragments.
74 * Should be >= RX_PULL_LEN but possibly bigger to give pskb_may_pull some room.
76 #define RX_PKT_SKB_LEN 512
79 * Max number of Tx descriptors we clean up at a time. Should be modest as
80 * freeing skbs isn't cheap and it happens while holding locks. We just need
81 * to free packets faster than they arrive, we eventually catch up and keep
82 * the amortized cost reasonable. Must be >= 2 * TXQ_STOP_THRES.
84 #define MAX_TX_RECLAIM 16
87 * Max number of Rx buffers we replenish at a time. Again keep this modest,
88 * allocating buffers isn't cheap either.
90 #define MAX_RX_REFILL 16U
93 * Period of the Rx queue check timer. This timer is infrequent as it has
94 * something to do only when the system experiences severe memory shortage.
96 #define RX_QCHECK_PERIOD (HZ / 2)
99 * Period of the Tx queue check timer.
101 #define TX_QCHECK_PERIOD (HZ / 2)
103 /* SGE Hung Ingress DMA Threshold Warning time (in Hz) and Warning Repeat Rate
104 * (in RX_QCHECK_PERIOD multiples). If we find one of the SGE Ingress DMA
105 * State Machines in the same state for this amount of time (in HZ) then we'll
106 * issue a warning about a potential hang. We'll repeat the warning as the
107 * SGE Ingress DMA Channel appears to be hung every N RX_QCHECK_PERIODs till
108 * the situation clears. If the situation clears, we'll note that as well.
110 #define SGE_IDMA_WARN_THRESH (1 * HZ)
111 #define SGE_IDMA_WARN_REPEAT (20 * RX_QCHECK_PERIOD)
114 * Max number of Tx descriptors to be reclaimed by the Tx timer.
116 #define MAX_TIMER_TX_RECLAIM 100
119 * Timer index used when backing off due to memory shortage.
121 #define NOMEM_TMR_IDX (SGE_NTIMERS - 1)
124 * An FL with <= FL_STARVE_THRES buffers is starving and a periodic timer will
125 * attempt to refill it.
127 #define FL_STARVE_THRES 4
130 * Suspend an Ethernet Tx queue with fewer available descriptors than this.
131 * This is the same as calc_tx_descs() for a TSO packet with
132 * nr_frags == MAX_SKB_FRAGS.
134 #define ETHTXQ_STOP_THRES \
135 (1 + DIV_ROUND_UP((3 * MAX_SKB_FRAGS) / 2 + (MAX_SKB_FRAGS & 1), 8))
138 * Suspension threshold for non-Ethernet Tx queues. We require enough room
139 * for a full sized WR.
141 #define TXQ_STOP_THRES (SGE_MAX_WR_LEN / sizeof(struct tx_desc))
144 * Max Tx descriptor space we allow for an Ethernet packet to be inlined
147 #define MAX_IMM_TX_PKT_LEN 128
150 * Max size of a WR sent through a control Tx queue.
152 #define MAX_CTRL_WR_LEN SGE_MAX_WR_LEN
154 struct tx_sw_desc { /* SW state per Tx descriptor */
156 struct ulptx_sgl *sgl;
159 struct rx_sw_desc { /* SW state per Rx descriptor */
165 * Rx buffer sizes for "useskbs" Free List buffers (one ingress packet pe skb
166 * buffer). We currently only support two sizes for 1500- and 9000-byte MTUs.
167 * We could easily support more but there doesn't seem to be much need for
170 #define FL_MTU_SMALL 1500
171 #define FL_MTU_LARGE 9000
173 static inline unsigned int fl_mtu_bufsize(struct adapter *adapter,
176 struct sge *s = &adapter->sge;
178 return ALIGN(s->pktshift + ETH_HLEN + VLAN_HLEN + mtu, s->fl_align);
181 #define FL_MTU_SMALL_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_SMALL)
182 #define FL_MTU_LARGE_BUFSIZE(adapter) fl_mtu_bufsize(adapter, FL_MTU_LARGE)
185 * Bits 0..3 of rx_sw_desc.dma_addr have special meaning. The hardware uses
186 * these to specify the buffer size as an index into the SGE Free List Buffer
187 * Size register array. We also use bit 4, when the buffer has been unmapped
188 * for DMA, but this is of course never sent to the hardware and is only used
189 * to prevent double unmappings. All of the above requires that the Free List
190 * Buffers which we allocate have the bottom 5 bits free (0) -- i.e. are
191 * 32-byte or or a power of 2 greater in alignment. Since the SGE's minimal
192 * Free List Buffer alignment is 32 bytes, this works out for us ...
195 RX_BUF_FLAGS = 0x1f, /* bottom five bits are special */
196 RX_BUF_SIZE = 0x0f, /* bottom three bits are for buf sizes */
197 RX_UNMAPPED_BUF = 0x10, /* buffer is not mapped */
200 * XXX We shouldn't depend on being able to use these indices.
201 * XXX Especially when some other Master PF has initialized the
202 * XXX adapter or we use the Firmware Configuration File. We
203 * XXX should really search through the Host Buffer Size register
204 * XXX array for the appropriately sized buffer indices.
206 RX_SMALL_PG_BUF = 0x0, /* small (PAGE_SIZE) page buffer */
207 RX_LARGE_PG_BUF = 0x1, /* buffer large (FL_PG_ORDER) page buffer */
209 RX_SMALL_MTU_BUF = 0x2, /* small MTU buffer */
210 RX_LARGE_MTU_BUF = 0x3, /* large MTU buffer */
213 static int timer_pkt_quota[] = {1, 1, 2, 3, 4, 5};
214 #define MIN_NAPI_WORK 1
216 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *d)
218 return d->dma_addr & ~(dma_addr_t)RX_BUF_FLAGS;
221 static inline bool is_buf_mapped(const struct rx_sw_desc *d)
223 return !(d->dma_addr & RX_UNMAPPED_BUF);
227 * txq_avail - return the number of available slots in a Tx queue
230 * Returns the number of descriptors in a Tx queue available to write new
233 static inline unsigned int txq_avail(const struct sge_txq *q)
235 return q->size - 1 - q->in_use;
239 * fl_cap - return the capacity of a free-buffer list
242 * Returns the capacity of a free-buffer list. The capacity is less than
243 * the size because one descriptor needs to be left unpopulated, otherwise
244 * HW will think the FL is empty.
246 static inline unsigned int fl_cap(const struct sge_fl *fl)
248 return fl->size - 8; /* 1 descriptor = 8 buffers */
251 static inline bool fl_starving(const struct sge_fl *fl)
253 return fl->avail - fl->pend_cred <= FL_STARVE_THRES;
256 static int map_skb(struct device *dev, const struct sk_buff *skb,
259 const skb_frag_t *fp, *end;
260 const struct skb_shared_info *si;
262 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
263 if (dma_mapping_error(dev, *addr))
266 si = skb_shinfo(skb);
267 end = &si->frags[si->nr_frags];
269 for (fp = si->frags; fp < end; fp++) {
270 *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp),
272 if (dma_mapping_error(dev, *addr))
278 while (fp-- > si->frags)
279 dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE);
281 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
286 #ifdef CONFIG_NEED_DMA_MAP_STATE
287 static void unmap_skb(struct device *dev, const struct sk_buff *skb,
288 const dma_addr_t *addr)
290 const skb_frag_t *fp, *end;
291 const struct skb_shared_info *si;
293 dma_unmap_single(dev, *addr++, skb_headlen(skb), DMA_TO_DEVICE);
295 si = skb_shinfo(skb);
296 end = &si->frags[si->nr_frags];
297 for (fp = si->frags; fp < end; fp++)
298 dma_unmap_page(dev, *addr++, skb_frag_size(fp), DMA_TO_DEVICE);
302 * deferred_unmap_destructor - unmap a packet when it is freed
305 * This is the packet destructor used for Tx packets that need to remain
306 * mapped until they are freed rather than until their Tx descriptors are
309 static void deferred_unmap_destructor(struct sk_buff *skb)
311 unmap_skb(skb->dev->dev.parent, skb, (dma_addr_t *)skb->head);
315 static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
316 const struct ulptx_sgl *sgl, const struct sge_txq *q)
318 const struct ulptx_sge_pair *p;
319 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
321 if (likely(skb_headlen(skb)))
322 dma_unmap_single(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
325 dma_unmap_page(dev, be64_to_cpu(sgl->addr0), ntohl(sgl->len0),
331 * the complexity below is because of the possibility of a wrap-around
332 * in the middle of an SGL
334 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
335 if (likely((u8 *)(p + 1) <= (u8 *)q->stat)) {
336 unmap: dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
337 ntohl(p->len[0]), DMA_TO_DEVICE);
338 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
339 ntohl(p->len[1]), DMA_TO_DEVICE);
341 } else if ((u8 *)p == (u8 *)q->stat) {
342 p = (const struct ulptx_sge_pair *)q->desc;
344 } else if ((u8 *)p + 8 == (u8 *)q->stat) {
345 const __be64 *addr = (const __be64 *)q->desc;
347 dma_unmap_page(dev, be64_to_cpu(addr[0]),
348 ntohl(p->len[0]), DMA_TO_DEVICE);
349 dma_unmap_page(dev, be64_to_cpu(addr[1]),
350 ntohl(p->len[1]), DMA_TO_DEVICE);
351 p = (const struct ulptx_sge_pair *)&addr[2];
353 const __be64 *addr = (const __be64 *)q->desc;
355 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
356 ntohl(p->len[0]), DMA_TO_DEVICE);
357 dma_unmap_page(dev, be64_to_cpu(addr[0]),
358 ntohl(p->len[1]), DMA_TO_DEVICE);
359 p = (const struct ulptx_sge_pair *)&addr[1];
365 if ((u8 *)p == (u8 *)q->stat)
366 p = (const struct ulptx_sge_pair *)q->desc;
367 addr = (u8 *)p + 16 <= (u8 *)q->stat ? p->addr[0] :
368 *(const __be64 *)q->desc;
369 dma_unmap_page(dev, be64_to_cpu(addr), ntohl(p->len[0]),
375 * free_tx_desc - reclaims Tx descriptors and their buffers
376 * @adapter: the adapter
377 * @q: the Tx queue to reclaim descriptors from
378 * @n: the number of descriptors to reclaim
379 * @unmap: whether the buffers should be unmapped for DMA
381 * Reclaims Tx descriptors from an SGE Tx queue and frees the associated
382 * Tx buffers. Called with the Tx queue lock held.
384 static void free_tx_desc(struct adapter *adap, struct sge_txq *q,
385 unsigned int n, bool unmap)
387 struct tx_sw_desc *d;
388 unsigned int cidx = q->cidx;
389 struct device *dev = adap->pdev_dev;
393 if (d->skb) { /* an SGL is present */
395 unmap_sgl(dev, d->skb, d->sgl, q);
396 dev_consume_skb_any(d->skb);
400 if (++cidx == q->size) {
409 * Return the number of reclaimable descriptors in a Tx queue.
411 static inline int reclaimable(const struct sge_txq *q)
413 int hw_cidx = ntohs(q->stat->cidx);
415 return hw_cidx < 0 ? hw_cidx + q->size : hw_cidx;
419 * reclaim_completed_tx - reclaims completed Tx descriptors
421 * @q: the Tx queue to reclaim completed descriptors from
422 * @unmap: whether the buffers should be unmapped for DMA
424 * Reclaims Tx descriptors that the SGE has indicated it has processed,
425 * and frees the associated buffers if possible. Called with the Tx
428 static inline void reclaim_completed_tx(struct adapter *adap, struct sge_txq *q,
431 int avail = reclaimable(q);
435 * Limit the amount of clean up work we do at a time to keep
436 * the Tx lock hold time O(1).
438 if (avail > MAX_TX_RECLAIM)
439 avail = MAX_TX_RECLAIM;
441 free_tx_desc(adap, q, avail, unmap);
446 static inline int get_buf_size(struct adapter *adapter,
447 const struct rx_sw_desc *d)
449 struct sge *s = &adapter->sge;
450 unsigned int rx_buf_size_idx = d->dma_addr & RX_BUF_SIZE;
453 switch (rx_buf_size_idx) {
454 case RX_SMALL_PG_BUF:
455 buf_size = PAGE_SIZE;
458 case RX_LARGE_PG_BUF:
459 buf_size = PAGE_SIZE << s->fl_pg_order;
462 case RX_SMALL_MTU_BUF:
463 buf_size = FL_MTU_SMALL_BUFSIZE(adapter);
466 case RX_LARGE_MTU_BUF:
467 buf_size = FL_MTU_LARGE_BUFSIZE(adapter);
478 * free_rx_bufs - free the Rx buffers on an SGE free list
480 * @q: the SGE free list to free buffers from
481 * @n: how many buffers to free
483 * Release the next @n buffers on an SGE free-buffer Rx queue. The
484 * buffers must be made inaccessible to HW before calling this function.
486 static void free_rx_bufs(struct adapter *adap, struct sge_fl *q, int n)
489 struct rx_sw_desc *d = &q->sdesc[q->cidx];
491 if (is_buf_mapped(d))
492 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
493 get_buf_size(adap, d),
497 if (++q->cidx == q->size)
504 * unmap_rx_buf - unmap the current Rx buffer on an SGE free list
506 * @q: the SGE free list
508 * Unmap the current buffer on an SGE free-buffer Rx queue. The
509 * buffer must be made inaccessible to HW before calling this function.
511 * This is similar to @free_rx_bufs above but does not free the buffer.
512 * Do note that the FL still loses any further access to the buffer.
514 static void unmap_rx_buf(struct adapter *adap, struct sge_fl *q)
516 struct rx_sw_desc *d = &q->sdesc[q->cidx];
518 if (is_buf_mapped(d))
519 dma_unmap_page(adap->pdev_dev, get_buf_addr(d),
520 get_buf_size(adap, d), PCI_DMA_FROMDEVICE);
522 if (++q->cidx == q->size)
527 static inline void ring_fl_db(struct adapter *adap, struct sge_fl *q)
530 if (q->pend_cred >= 8) {
531 if (is_t4(adap->params.chip))
532 val = PIDX_V(q->pend_cred / 8);
534 val = PIDX_T5_V(q->pend_cred / 8) |
539 /* If we don't have access to the new User Doorbell (T5+), use
540 * the old doorbell mechanism; otherwise use the new BAR2
543 if (unlikely(q->bar2_addr == NULL)) {
544 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
545 val | QID_V(q->cntxt_id));
547 writel(val | QID_V(q->bar2_qid),
548 q->bar2_addr + SGE_UDB_KDOORBELL);
550 /* This Write memory Barrier will force the write to
551 * the User Doorbell area to be flushed.
559 static inline void set_rx_sw_desc(struct rx_sw_desc *sd, struct page *pg,
563 sd->dma_addr = mapping; /* includes size low bits */
567 * refill_fl - refill an SGE Rx buffer ring
569 * @q: the ring to refill
570 * @n: the number of new buffers to allocate
571 * @gfp: the gfp flags for the allocations
573 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
574 * allocated with the supplied gfp flags. The caller must assure that
575 * @n does not exceed the queue's capacity. If afterwards the queue is
576 * found critically low mark it as starving in the bitmap of starving FLs.
578 * Returns the number of buffers allocated.
580 static unsigned int refill_fl(struct adapter *adap, struct sge_fl *q, int n,
583 struct sge *s = &adap->sge;
586 unsigned int cred = q->avail;
587 __be64 *d = &q->desc[q->pidx];
588 struct rx_sw_desc *sd = &q->sdesc[q->pidx];
592 if (s->fl_pg_order == 0)
593 goto alloc_small_pages;
596 * Prefer large buffers
599 pg = __dev_alloc_pages(gfp, s->fl_pg_order);
601 q->large_alloc_failed++;
602 break; /* fall back to single pages */
605 mapping = dma_map_page(adap->pdev_dev, pg, 0,
606 PAGE_SIZE << s->fl_pg_order,
608 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
609 __free_pages(pg, s->fl_pg_order);
610 goto out; /* do not try small pages for this error */
612 mapping |= RX_LARGE_PG_BUF;
613 *d++ = cpu_to_be64(mapping);
615 set_rx_sw_desc(sd, pg, mapping);
619 if (++q->pidx == q->size) {
629 pg = __dev_alloc_page(gfp);
635 mapping = dma_map_page(adap->pdev_dev, pg, 0, PAGE_SIZE,
637 if (unlikely(dma_mapping_error(adap->pdev_dev, mapping))) {
641 *d++ = cpu_to_be64(mapping);
643 set_rx_sw_desc(sd, pg, mapping);
647 if (++q->pidx == q->size) {
654 out: cred = q->avail - cred;
655 q->pend_cred += cred;
658 if (unlikely(fl_starving(q))) {
660 set_bit(q->cntxt_id - adap->sge.egr_start,
661 adap->sge.starving_fl);
667 static inline void __refill_fl(struct adapter *adap, struct sge_fl *fl)
669 refill_fl(adap, fl, min(MAX_RX_REFILL, fl_cap(fl) - fl->avail),
674 * alloc_ring - allocate resources for an SGE descriptor ring
675 * @dev: the PCI device's core device
676 * @nelem: the number of descriptors
677 * @elem_size: the size of each descriptor
678 * @sw_size: the size of the SW state associated with each ring element
679 * @phys: the physical address of the allocated ring
680 * @metadata: address of the array holding the SW state for the ring
681 * @stat_size: extra space in HW ring for status information
682 * @node: preferred node for memory allocations
684 * Allocates resources for an SGE descriptor ring, such as Tx queues,
685 * free buffer lists, or response queues. Each SGE ring requires
686 * space for its HW descriptors plus, optionally, space for the SW state
687 * associated with each HW entry (the metadata). The function returns
688 * three values: the virtual address for the HW ring (the return value
689 * of the function), the bus address of the HW ring, and the address
692 static void *alloc_ring(struct device *dev, size_t nelem, size_t elem_size,
693 size_t sw_size, dma_addr_t *phys, void *metadata,
694 size_t stat_size, int node)
696 size_t len = nelem * elem_size + stat_size;
698 void *p = dma_alloc_coherent(dev, len, phys, GFP_KERNEL);
703 s = kzalloc_node(nelem * sw_size, GFP_KERNEL, node);
706 dma_free_coherent(dev, len, p, *phys);
711 *(void **)metadata = s;
717 * sgl_len - calculates the size of an SGL of the given capacity
718 * @n: the number of SGL entries
720 * Calculates the number of flits needed for a scatter/gather list that
721 * can hold the given number of entries.
723 static inline unsigned int sgl_len(unsigned int n)
726 return (3 * n) / 2 + (n & 1) + 2;
730 * flits_to_desc - returns the num of Tx descriptors for the given flits
731 * @n: the number of flits
733 * Returns the number of Tx descriptors needed for the supplied number
736 static inline unsigned int flits_to_desc(unsigned int n)
738 BUG_ON(n > SGE_MAX_WR_LEN / 8);
739 return DIV_ROUND_UP(n, 8);
743 * is_eth_imm - can an Ethernet packet be sent as immediate data?
746 * Returns whether an Ethernet packet is small enough to fit as
747 * immediate data. Return value corresponds to headroom required.
749 static inline int is_eth_imm(const struct sk_buff *skb)
751 int hdrlen = skb_shinfo(skb)->gso_size ?
752 sizeof(struct cpl_tx_pkt_lso_core) : 0;
754 hdrlen += sizeof(struct cpl_tx_pkt);
755 if (skb->len <= MAX_IMM_TX_PKT_LEN - hdrlen)
761 * calc_tx_flits - calculate the number of flits for a packet Tx WR
764 * Returns the number of flits needed for a Tx WR for the given Ethernet
765 * packet, including the needed WR and CPL headers.
767 static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
770 int hdrlen = is_eth_imm(skb);
773 return DIV_ROUND_UP(skb->len + hdrlen, sizeof(__be64));
775 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1) + 4;
776 if (skb_shinfo(skb)->gso_size)
782 * calc_tx_descs - calculate the number of Tx descriptors for a packet
785 * Returns the number of Tx descriptors needed for the given Ethernet
786 * packet, including the needed WR and CPL headers.
788 static inline unsigned int calc_tx_descs(const struct sk_buff *skb)
790 return flits_to_desc(calc_tx_flits(skb));
794 * write_sgl - populate a scatter/gather list for a packet
796 * @q: the Tx queue we are writing into
797 * @sgl: starting location for writing the SGL
798 * @end: points right after the end of the SGL
799 * @start: start offset into skb main-body data to include in the SGL
800 * @addr: the list of bus addresses for the SGL elements
802 * Generates a gather list for the buffers that make up a packet.
803 * The caller must provide adequate space for the SGL that will be written.
804 * The SGL includes all of the packet's page fragments and the data in its
805 * main body except for the first @start bytes. @sgl must be 16-byte
806 * aligned and within a Tx descriptor with available space. @end points
807 * right after the end of the SGL but does not account for any potential
808 * wrap around, i.e., @end > @sgl.
810 static void write_sgl(const struct sk_buff *skb, struct sge_txq *q,
811 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
812 const dma_addr_t *addr)
815 struct ulptx_sge_pair *to;
816 const struct skb_shared_info *si = skb_shinfo(skb);
817 unsigned int nfrags = si->nr_frags;
818 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
820 len = skb_headlen(skb) - start;
822 sgl->len0 = htonl(len);
823 sgl->addr0 = cpu_to_be64(addr[0] + start);
826 sgl->len0 = htonl(skb_frag_size(&si->frags[0]));
827 sgl->addr0 = cpu_to_be64(addr[1]);
830 sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
831 ULPTX_NSGE_V(nfrags));
832 if (likely(--nfrags == 0))
835 * Most of the complexity below deals with the possibility we hit the
836 * end of the queue in the middle of writing the SGL. For this case
837 * only we create the SGL in a temporary buffer and then copy it.
839 to = (u8 *)end > (u8 *)q->stat ? buf : sgl->sge;
841 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
842 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
843 to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i]));
844 to->addr[0] = cpu_to_be64(addr[i]);
845 to->addr[1] = cpu_to_be64(addr[++i]);
848 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
849 to->len[1] = cpu_to_be32(0);
850 to->addr[0] = cpu_to_be64(addr[i + 1]);
852 if (unlikely((u8 *)end > (u8 *)q->stat)) {
853 unsigned int part0 = (u8 *)q->stat - (u8 *)sgl->sge, part1;
856 memcpy(sgl->sge, buf, part0);
857 part1 = (u8 *)end - (u8 *)q->stat;
858 memcpy(q->desc, (u8 *)buf + part0, part1);
859 end = (void *)q->desc + part1;
861 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
865 /* This function copies 64 byte coalesced work request to
866 * memory mapped BAR2 space. For coalesced WR SGE fetches
867 * data from the FIFO instead of from Host.
869 static void cxgb_pio_copy(u64 __iomem *dst, u64 *src)
882 * ring_tx_db - check and potentially ring a Tx queue's doorbell
885 * @n: number of new descriptors to give to HW
887 * Ring the doorbel for a Tx queue.
889 static inline void ring_tx_db(struct adapter *adap, struct sge_txq *q, int n)
891 wmb(); /* write descriptors before telling HW */
893 /* If we don't have access to the new User Doorbell (T5+), use the old
894 * doorbell mechanism; otherwise use the new BAR2 mechanism.
896 if (unlikely(q->bar2_addr == NULL)) {
900 /* For T4 we need to participate in the Doorbell Recovery
903 spin_lock_irqsave(&q->db_lock, flags);
905 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
906 QID_V(q->cntxt_id) | val);
909 q->db_pidx = q->pidx;
910 spin_unlock_irqrestore(&q->db_lock, flags);
912 u32 val = PIDX_T5_V(n);
914 /* T4 and later chips share the same PIDX field offset within
915 * the doorbell, but T5 and later shrank the field in order to
916 * gain a bit for Doorbell Priority. The field was absurdly
917 * large in the first place (14 bits) so we just use the T5
918 * and later limits and warn if a Queue ID is too large.
920 WARN_ON(val & DBPRIO_F);
922 /* If we're only writing a single TX Descriptor and we can use
923 * Inferred QID registers, we can use the Write Combining
924 * Gather Buffer; otherwise we use the simple doorbell.
926 if (n == 1 && q->bar2_qid == 0) {
930 u64 *wr = (u64 *)&q->desc[index];
932 cxgb_pio_copy((u64 __iomem *)
933 (q->bar2_addr + SGE_UDB_WCDOORBELL),
936 writel(val | QID_V(q->bar2_qid),
937 q->bar2_addr + SGE_UDB_KDOORBELL);
940 /* This Write Memory Barrier will force the write to the User
941 * Doorbell area to be flushed. This is needed to prevent
942 * writes on different CPUs for the same queue from hitting
943 * the adapter out of order. This is required when some Work
944 * Requests take the Write Combine Gather Buffer path (user
945 * doorbell area offset [SGE_UDB_WCDOORBELL..+63]) and some
946 * take the traditional path where we simply increment the
947 * PIDX (User Doorbell area SGE_UDB_KDOORBELL) and have the
948 * hardware DMA read the actual Work Request.
955 * inline_tx_skb - inline a packet's data into Tx descriptors
957 * @q: the Tx queue where the packet will be inlined
958 * @pos: starting position in the Tx queue where to inline the packet
960 * Inline a packet's contents directly into Tx descriptors, starting at
961 * the given position within the Tx DMA ring.
962 * Most of the complexity of this operation is dealing with wrap arounds
963 * in the middle of the packet we want to inline.
965 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *q,
969 int left = (void *)q->stat - pos;
971 if (likely(skb->len <= left)) {
972 if (likely(!skb->data_len))
973 skb_copy_from_linear_data(skb, pos, skb->len);
975 skb_copy_bits(skb, 0, pos, skb->len);
978 skb_copy_bits(skb, 0, pos, left);
979 skb_copy_bits(skb, left, q->desc, skb->len - left);
980 pos = (void *)q->desc + (skb->len - left);
983 /* 0-pad to multiple of 16 */
984 p = PTR_ALIGN(pos, 8);
985 if ((uintptr_t)p & 8)
990 * Figure out what HW csum a packet wants and return the appropriate control
993 static u64 hwcsum(const struct sk_buff *skb)
996 const struct iphdr *iph = ip_hdr(skb);
998 if (iph->version == 4) {
999 if (iph->protocol == IPPROTO_TCP)
1000 csum_type = TX_CSUM_TCPIP;
1001 else if (iph->protocol == IPPROTO_UDP)
1002 csum_type = TX_CSUM_UDPIP;
1005 * unknown protocol, disable HW csum
1006 * and hope a bad packet is detected
1008 return TXPKT_L4CSUM_DIS;
1012 * this doesn't work with extension headers
1014 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
1016 if (ip6h->nexthdr == IPPROTO_TCP)
1017 csum_type = TX_CSUM_TCPIP6;
1018 else if (ip6h->nexthdr == IPPROTO_UDP)
1019 csum_type = TX_CSUM_UDPIP6;
1024 if (likely(csum_type >= TX_CSUM_TCPIP))
1025 return TXPKT_CSUM_TYPE(csum_type) |
1026 TXPKT_IPHDR_LEN(skb_network_header_len(skb)) |
1027 TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN);
1029 int start = skb_transport_offset(skb);
1031 return TXPKT_CSUM_TYPE(csum_type) | TXPKT_CSUM_START(start) |
1032 TXPKT_CSUM_LOC(start + skb->csum_offset);
1036 static void eth_txq_stop(struct sge_eth_txq *q)
1038 netif_tx_stop_queue(q->txq);
1042 static inline void txq_advance(struct sge_txq *q, unsigned int n)
1046 if (q->pidx >= q->size)
1050 #ifdef CONFIG_CHELSIO_T4_FCOE
1052 cxgb_fcoe_offload(struct sk_buff *skb, struct adapter *adap,
1053 const struct port_info *pi, u64 *cntrl)
1055 const struct cxgb_fcoe *fcoe = &pi->fcoe;
1057 if (!(fcoe->flags & CXGB_FCOE_ENABLED))
1060 if (skb->protocol != htons(ETH_P_FCOE))
1063 skb_reset_mac_header(skb);
1064 skb->mac_len = sizeof(struct ethhdr);
1066 skb_set_network_header(skb, skb->mac_len);
1067 skb_set_transport_header(skb, skb->mac_len + sizeof(struct fcoe_hdr));
1069 if (!cxgb_fcoe_sof_eof_supported(adap, skb))
1072 /* FC CRC offload */
1073 *cntrl = TXPKT_CSUM_TYPE(TX_CSUM_FCOE) |
1074 TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS |
1075 TXPKT_CSUM_START(CXGB_FCOE_TXPKT_CSUM_START) |
1076 TXPKT_CSUM_END(CXGB_FCOE_TXPKT_CSUM_END) |
1077 TXPKT_CSUM_LOC(CXGB_FCOE_TXPKT_CSUM_END);
1080 #endif /* CONFIG_CHELSIO_T4_FCOE */
1083 * t4_eth_xmit - add a packet to an Ethernet Tx queue
1085 * @dev: the egress net device
1087 * Add a packet to an SGE Ethernet Tx queue. Runs with softirqs disabled.
1089 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1095 unsigned int flits, ndesc;
1096 struct adapter *adap;
1097 struct sge_eth_txq *q;
1098 const struct port_info *pi;
1099 struct fw_eth_tx_pkt_wr *wr;
1100 struct cpl_tx_pkt_core *cpl;
1101 const struct skb_shared_info *ssi;
1102 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1103 bool immediate = false;
1104 #ifdef CONFIG_CHELSIO_T4_FCOE
1106 #endif /* CONFIG_CHELSIO_T4_FCOE */
1109 * The chip min packet length is 10 octets but play safe and reject
1110 * anything shorter than an Ethernet header.
1112 if (unlikely(skb->len < ETH_HLEN)) {
1113 out_free: dev_kfree_skb_any(skb);
1114 return NETDEV_TX_OK;
1117 pi = netdev_priv(dev);
1119 qidx = skb_get_queue_mapping(skb);
1120 q = &adap->sge.ethtxq[qidx + pi->first_qset];
1122 reclaim_completed_tx(adap, &q->q, true);
1123 cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS;
1125 #ifdef CONFIG_CHELSIO_T4_FCOE
1126 err = cxgb_fcoe_offload(skb, adap, pi, &cntrl);
1127 if (unlikely(err == -ENOTSUPP))
1129 #endif /* CONFIG_CHELSIO_T4_FCOE */
1131 flits = calc_tx_flits(skb);
1132 ndesc = flits_to_desc(flits);
1133 credits = txq_avail(&q->q) - ndesc;
1135 if (unlikely(credits < 0)) {
1137 dev_err(adap->pdev_dev,
1138 "%s: Tx ring %u full while queue awake!\n",
1140 return NETDEV_TX_BUSY;
1143 if (is_eth_imm(skb))
1147 unlikely(map_skb(adap->pdev_dev, skb, addr) < 0)) {
1152 wr_mid = FW_WR_LEN16_V(DIV_ROUND_UP(flits, 2));
1153 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1155 wr_mid |= FW_WR_EQUEQ_F | FW_WR_EQUIQ_F;
1158 wr = (void *)&q->q.desc[q->q.pidx];
1159 wr->equiq_to_len16 = htonl(wr_mid);
1160 wr->r3 = cpu_to_be64(0);
1161 end = (u64 *)wr + flits;
1163 len = immediate ? skb->len : 0;
1164 ssi = skb_shinfo(skb);
1165 if (ssi->gso_size) {
1166 struct cpl_tx_pkt_lso *lso = (void *)wr;
1167 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1168 int l3hdr_len = skb_network_header_len(skb);
1169 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1171 len += sizeof(*lso);
1172 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
1173 FW_WR_IMMDLEN_V(len));
1174 lso->c.lso_ctrl = htonl(LSO_OPCODE(CPL_TX_PKT_LSO) |
1175 LSO_FIRST_SLICE | LSO_LAST_SLICE |
1177 LSO_ETHHDR_LEN(eth_xtra_len / 4) |
1178 LSO_IPHDR_LEN(l3hdr_len / 4) |
1179 LSO_TCPHDR_LEN(tcp_hdr(skb)->doff));
1180 lso->c.ipid_ofst = htons(0);
1181 lso->c.mss = htons(ssi->gso_size);
1182 lso->c.seqno_offset = htonl(0);
1183 if (is_t4(adap->params.chip))
1184 lso->c.len = htonl(skb->len);
1186 lso->c.len = htonl(LSO_T5_XFER_SIZE(skb->len));
1187 cpl = (void *)(lso + 1);
1188 cntrl = TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1189 TXPKT_IPHDR_LEN(l3hdr_len) |
1190 TXPKT_ETHHDR_LEN(eth_xtra_len);
1192 q->tx_cso += ssi->gso_segs;
1194 len += sizeof(*cpl);
1195 wr->op_immdlen = htonl(FW_WR_OP_V(FW_ETH_TX_PKT_WR) |
1196 FW_WR_IMMDLEN_V(len));
1197 cpl = (void *)(wr + 1);
1198 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1199 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
1204 if (skb_vlan_tag_present(skb)) {
1206 cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(skb_vlan_tag_get(skb));
1207 #ifdef CONFIG_CHELSIO_T4_FCOE
1208 if (skb->protocol == htons(ETH_P_FCOE))
1209 cntrl |= TXPKT_VLAN(
1210 ((skb->priority & 0x7) << VLAN_PRIO_SHIFT));
1211 #endif /* CONFIG_CHELSIO_T4_FCOE */
1214 cpl->ctrl0 = htonl(TXPKT_OPCODE(CPL_TX_PKT_XT) |
1215 TXPKT_INTF(pi->tx_chan) | TXPKT_PF(adap->fn));
1216 cpl->pack = htons(0);
1217 cpl->len = htons(skb->len);
1218 cpl->ctrl1 = cpu_to_be64(cntrl);
1221 inline_tx_skb(skb, &q->q, cpl + 1);
1222 dev_consume_skb_any(skb);
1226 write_sgl(skb, &q->q, (struct ulptx_sgl *)(cpl + 1), end, 0,
1230 last_desc = q->q.pidx + ndesc - 1;
1231 if (last_desc >= q->q.size)
1232 last_desc -= q->q.size;
1233 q->q.sdesc[last_desc].skb = skb;
1234 q->q.sdesc[last_desc].sgl = (struct ulptx_sgl *)(cpl + 1);
1237 txq_advance(&q->q, ndesc);
1239 ring_tx_db(adap, &q->q, ndesc);
1240 return NETDEV_TX_OK;
1244 * reclaim_completed_tx_imm - reclaim completed control-queue Tx descs
1245 * @q: the SGE control Tx queue
1247 * This is a variant of reclaim_completed_tx() that is used for Tx queues
1248 * that send only immediate data (presently just the control queues) and
1249 * thus do not have any sk_buffs to release.
1251 static inline void reclaim_completed_tx_imm(struct sge_txq *q)
1253 int hw_cidx = ntohs(q->stat->cidx);
1254 int reclaim = hw_cidx - q->cidx;
1259 q->in_use -= reclaim;
1264 * is_imm - check whether a packet can be sent as immediate data
1267 * Returns true if a packet can be sent as a WR with immediate data.
1269 static inline int is_imm(const struct sk_buff *skb)
1271 return skb->len <= MAX_CTRL_WR_LEN;
1275 * ctrlq_check_stop - check if a control queue is full and should stop
1277 * @wr: most recent WR written to the queue
1279 * Check if a control queue has become full and should be stopped.
1280 * We clean up control queue descriptors very lazily, only when we are out.
1281 * If the queue is still full after reclaiming any completed descriptors
1282 * we suspend it and have the last WR wake it up.
1284 static void ctrlq_check_stop(struct sge_ctrl_txq *q, struct fw_wr_hdr *wr)
1286 reclaim_completed_tx_imm(&q->q);
1287 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1288 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
1295 * ctrl_xmit - send a packet through an SGE control Tx queue
1296 * @q: the control queue
1299 * Send a packet through an SGE control Tx queue. Packets sent through
1300 * a control queue must fit entirely as immediate data.
1302 static int ctrl_xmit(struct sge_ctrl_txq *q, struct sk_buff *skb)
1305 struct fw_wr_hdr *wr;
1307 if (unlikely(!is_imm(skb))) {
1310 return NET_XMIT_DROP;
1313 ndesc = DIV_ROUND_UP(skb->len, sizeof(struct tx_desc));
1314 spin_lock(&q->sendq.lock);
1316 if (unlikely(q->full)) {
1317 skb->priority = ndesc; /* save for restart */
1318 __skb_queue_tail(&q->sendq, skb);
1319 spin_unlock(&q->sendq.lock);
1323 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1324 inline_tx_skb(skb, &q->q, wr);
1326 txq_advance(&q->q, ndesc);
1327 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES))
1328 ctrlq_check_stop(q, wr);
1330 ring_tx_db(q->adap, &q->q, ndesc);
1331 spin_unlock(&q->sendq.lock);
1334 return NET_XMIT_SUCCESS;
1338 * restart_ctrlq - restart a suspended control queue
1339 * @data: the control queue to restart
1341 * Resumes transmission on a suspended Tx control queue.
1343 static void restart_ctrlq(unsigned long data)
1345 struct sk_buff *skb;
1346 unsigned int written = 0;
1347 struct sge_ctrl_txq *q = (struct sge_ctrl_txq *)data;
1349 spin_lock(&q->sendq.lock);
1350 reclaim_completed_tx_imm(&q->q);
1351 BUG_ON(txq_avail(&q->q) < TXQ_STOP_THRES); /* q should be empty */
1353 while ((skb = __skb_dequeue(&q->sendq)) != NULL) {
1354 struct fw_wr_hdr *wr;
1355 unsigned int ndesc = skb->priority; /* previously saved */
1358 * Write descriptors and free skbs outside the lock to limit
1359 * wait times. q->full is still set so new skbs will be queued.
1361 spin_unlock(&q->sendq.lock);
1363 wr = (struct fw_wr_hdr *)&q->q.desc[q->q.pidx];
1364 inline_tx_skb(skb, &q->q, wr);
1368 txq_advance(&q->q, ndesc);
1369 if (unlikely(txq_avail(&q->q) < TXQ_STOP_THRES)) {
1370 unsigned long old = q->q.stops;
1372 ctrlq_check_stop(q, wr);
1373 if (q->q.stops != old) { /* suspended anew */
1374 spin_lock(&q->sendq.lock);
1379 ring_tx_db(q->adap, &q->q, written);
1382 spin_lock(&q->sendq.lock);
1385 ringdb: if (written)
1386 ring_tx_db(q->adap, &q->q, written);
1387 spin_unlock(&q->sendq.lock);
1391 * t4_mgmt_tx - send a management message
1392 * @adap: the adapter
1393 * @skb: the packet containing the management message
1395 * Send a management message through control queue 0.
1397 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb)
1402 ret = ctrl_xmit(&adap->sge.ctrlq[0], skb);
1408 * is_ofld_imm - check whether a packet can be sent as immediate data
1411 * Returns true if a packet can be sent as an offload WR with immediate
1412 * data. We currently use the same limit as for Ethernet packets.
1414 static inline int is_ofld_imm(const struct sk_buff *skb)
1416 return skb->len <= MAX_IMM_TX_PKT_LEN;
1420 * calc_tx_flits_ofld - calculate # of flits for an offload packet
1423 * Returns the number of flits needed for the given offload packet.
1424 * These packets are already fully constructed and no additional headers
1427 static inline unsigned int calc_tx_flits_ofld(const struct sk_buff *skb)
1429 unsigned int flits, cnt;
1431 if (is_ofld_imm(skb))
1432 return DIV_ROUND_UP(skb->len, 8);
1434 flits = skb_transport_offset(skb) / 8U; /* headers */
1435 cnt = skb_shinfo(skb)->nr_frags;
1436 if (skb_tail_pointer(skb) != skb_transport_header(skb))
1438 return flits + sgl_len(cnt);
1442 * txq_stop_maperr - stop a Tx queue due to I/O MMU exhaustion
1443 * @adap: the adapter
1444 * @q: the queue to stop
1446 * Mark a Tx queue stopped due to I/O MMU exhaustion and resulting
1447 * inability to map packets. A periodic timer attempts to restart
1450 static void txq_stop_maperr(struct sge_ofld_txq *q)
1454 set_bit(q->q.cntxt_id - q->adap->sge.egr_start,
1455 q->adap->sge.txq_maperr);
1459 * ofldtxq_stop - stop an offload Tx queue that has become full
1460 * @q: the queue to stop
1461 * @skb: the packet causing the queue to become full
1463 * Stops an offload Tx queue that has become full and modifies the packet
1464 * being written to request a wakeup.
1466 static void ofldtxq_stop(struct sge_ofld_txq *q, struct sk_buff *skb)
1468 struct fw_wr_hdr *wr = (struct fw_wr_hdr *)skb->data;
1470 wr->lo |= htonl(FW_WR_EQUEQ_F | FW_WR_EQUIQ_F);
1476 * service_ofldq - restart a suspended offload queue
1477 * @q: the offload queue
1479 * Services an offload Tx queue by moving packets from its packet queue
1480 * to the HW Tx ring. The function starts and ends with the queue locked.
1482 static void service_ofldq(struct sge_ofld_txq *q)
1486 struct sk_buff *skb;
1487 unsigned int written = 0;
1488 unsigned int flits, ndesc;
1490 while ((skb = skb_peek(&q->sendq)) != NULL && !q->full) {
1492 * We drop the lock but leave skb on sendq, thus retaining
1493 * exclusive access to the state of the queue.
1495 spin_unlock(&q->sendq.lock);
1497 reclaim_completed_tx(q->adap, &q->q, false);
1499 flits = skb->priority; /* previously saved */
1500 ndesc = flits_to_desc(flits);
1501 credits = txq_avail(&q->q) - ndesc;
1502 BUG_ON(credits < 0);
1503 if (unlikely(credits < TXQ_STOP_THRES))
1504 ofldtxq_stop(q, skb);
1506 pos = (u64 *)&q->q.desc[q->q.pidx];
1507 if (is_ofld_imm(skb))
1508 inline_tx_skb(skb, &q->q, pos);
1509 else if (map_skb(q->adap->pdev_dev, skb,
1510 (dma_addr_t *)skb->head)) {
1512 spin_lock(&q->sendq.lock);
1515 int last_desc, hdr_len = skb_transport_offset(skb);
1517 memcpy(pos, skb->data, hdr_len);
1518 write_sgl(skb, &q->q, (void *)pos + hdr_len,
1519 pos + flits, hdr_len,
1520 (dma_addr_t *)skb->head);
1521 #ifdef CONFIG_NEED_DMA_MAP_STATE
1522 skb->dev = q->adap->port[0];
1523 skb->destructor = deferred_unmap_destructor;
1525 last_desc = q->q.pidx + ndesc - 1;
1526 if (last_desc >= q->q.size)
1527 last_desc -= q->q.size;
1528 q->q.sdesc[last_desc].skb = skb;
1531 txq_advance(&q->q, ndesc);
1533 if (unlikely(written > 32)) {
1534 ring_tx_db(q->adap, &q->q, written);
1538 spin_lock(&q->sendq.lock);
1539 __skb_unlink(skb, &q->sendq);
1540 if (is_ofld_imm(skb))
1543 if (likely(written))
1544 ring_tx_db(q->adap, &q->q, written);
1548 * ofld_xmit - send a packet through an offload queue
1549 * @q: the Tx offload queue
1552 * Send an offload packet through an SGE offload queue.
1554 static int ofld_xmit(struct sge_ofld_txq *q, struct sk_buff *skb)
1556 skb->priority = calc_tx_flits_ofld(skb); /* save for restart */
1557 spin_lock(&q->sendq.lock);
1558 __skb_queue_tail(&q->sendq, skb);
1559 if (q->sendq.qlen == 1)
1561 spin_unlock(&q->sendq.lock);
1562 return NET_XMIT_SUCCESS;
1566 * restart_ofldq - restart a suspended offload queue
1567 * @data: the offload queue to restart
1569 * Resumes transmission on a suspended Tx offload queue.
1571 static void restart_ofldq(unsigned long data)
1573 struct sge_ofld_txq *q = (struct sge_ofld_txq *)data;
1575 spin_lock(&q->sendq.lock);
1576 q->full = 0; /* the queue actually is completely empty now */
1578 spin_unlock(&q->sendq.lock);
1582 * skb_txq - return the Tx queue an offload packet should use
1585 * Returns the Tx queue an offload packet should use as indicated by bits
1586 * 1-15 in the packet's queue_mapping.
1588 static inline unsigned int skb_txq(const struct sk_buff *skb)
1590 return skb->queue_mapping >> 1;
1594 * is_ctrl_pkt - return whether an offload packet is a control packet
1597 * Returns whether an offload packet should use an OFLD or a CTRL
1598 * Tx queue as indicated by bit 0 in the packet's queue_mapping.
1600 static inline unsigned int is_ctrl_pkt(const struct sk_buff *skb)
1602 return skb->queue_mapping & 1;
1605 static inline int ofld_send(struct adapter *adap, struct sk_buff *skb)
1607 unsigned int idx = skb_txq(skb);
1609 if (unlikely(is_ctrl_pkt(skb))) {
1610 /* Single ctrl queue is a requirement for LE workaround path */
1611 if (adap->tids.nsftids)
1613 return ctrl_xmit(&adap->sge.ctrlq[idx], skb);
1615 return ofld_xmit(&adap->sge.ofldtxq[idx], skb);
1619 * t4_ofld_send - send an offload packet
1620 * @adap: the adapter
1623 * Sends an offload packet. We use the packet queue_mapping to select the
1624 * appropriate Tx queue as follows: bit 0 indicates whether the packet
1625 * should be sent as regular or control, bits 1-15 select the queue.
1627 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb)
1632 ret = ofld_send(adap, skb);
1638 * cxgb4_ofld_send - send an offload packet
1639 * @dev: the net device
1642 * Sends an offload packet. This is an exported version of @t4_ofld_send,
1643 * intended for ULDs.
1645 int cxgb4_ofld_send(struct net_device *dev, struct sk_buff *skb)
1647 return t4_ofld_send(netdev2adap(dev), skb);
1649 EXPORT_SYMBOL(cxgb4_ofld_send);
1651 static inline void copy_frags(struct sk_buff *skb,
1652 const struct pkt_gl *gl, unsigned int offset)
1656 /* usually there's just one frag */
1657 __skb_fill_page_desc(skb, 0, gl->frags[0].page,
1658 gl->frags[0].offset + offset,
1659 gl->frags[0].size - offset);
1660 skb_shinfo(skb)->nr_frags = gl->nfrags;
1661 for (i = 1; i < gl->nfrags; i++)
1662 __skb_fill_page_desc(skb, i, gl->frags[i].page,
1663 gl->frags[i].offset,
1666 /* get a reference to the last page, we don't own it */
1667 get_page(gl->frags[gl->nfrags - 1].page);
1671 * cxgb4_pktgl_to_skb - build an sk_buff from a packet gather list
1672 * @gl: the gather list
1673 * @skb_len: size of sk_buff main body if it carries fragments
1674 * @pull_len: amount of data to move to the sk_buff's main body
1676 * Builds an sk_buff from the given packet gather list. Returns the
1677 * sk_buff or %NULL if sk_buff allocation failed.
1679 struct sk_buff *cxgb4_pktgl_to_skb(const struct pkt_gl *gl,
1680 unsigned int skb_len, unsigned int pull_len)
1682 struct sk_buff *skb;
1685 * Below we rely on RX_COPY_THRES being less than the smallest Rx buffer
1686 * size, which is expected since buffers are at least PAGE_SIZEd.
1687 * In this case packets up to RX_COPY_THRES have only one fragment.
1689 if (gl->tot_len <= RX_COPY_THRES) {
1690 skb = dev_alloc_skb(gl->tot_len);
1693 __skb_put(skb, gl->tot_len);
1694 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
1696 skb = dev_alloc_skb(skb_len);
1699 __skb_put(skb, pull_len);
1700 skb_copy_to_linear_data(skb, gl->va, pull_len);
1702 copy_frags(skb, gl, pull_len);
1703 skb->len = gl->tot_len;
1704 skb->data_len = skb->len - pull_len;
1705 skb->truesize += skb->data_len;
1709 EXPORT_SYMBOL(cxgb4_pktgl_to_skb);
1712 * t4_pktgl_free - free a packet gather list
1713 * @gl: the gather list
1715 * Releases the pages of a packet gather list. We do not own the last
1716 * page on the list and do not free it.
1718 static void t4_pktgl_free(const struct pkt_gl *gl)
1721 const struct page_frag *p;
1723 for (p = gl->frags, n = gl->nfrags - 1; n--; p++)
1728 * Process an MPS trace packet. Give it an unused protocol number so it won't
1729 * be delivered to anyone and send it to the stack for capture.
1731 static noinline int handle_trace_pkt(struct adapter *adap,
1732 const struct pkt_gl *gl)
1734 struct sk_buff *skb;
1736 skb = cxgb4_pktgl_to_skb(gl, RX_PULL_LEN, RX_PULL_LEN);
1737 if (unlikely(!skb)) {
1742 if (is_t4(adap->params.chip))
1743 __skb_pull(skb, sizeof(struct cpl_trace_pkt));
1745 __skb_pull(skb, sizeof(struct cpl_t5_trace_pkt));
1747 skb_reset_mac_header(skb);
1748 skb->protocol = htons(0xffff);
1749 skb->dev = adap->port[0];
1750 netif_receive_skb(skb);
1754 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1755 const struct cpl_rx_pkt *pkt)
1757 struct adapter *adapter = rxq->rspq.adap;
1758 struct sge *s = &adapter->sge;
1760 struct sk_buff *skb;
1762 skb = napi_get_frags(&rxq->rspq.napi);
1763 if (unlikely(!skb)) {
1765 rxq->stats.rx_drops++;
1769 copy_frags(skb, gl, s->pktshift);
1770 skb->len = gl->tot_len - s->pktshift;
1771 skb->data_len = skb->len;
1772 skb->truesize += skb->data_len;
1773 skb->ip_summed = CHECKSUM_UNNECESSARY;
1774 skb_record_rx_queue(skb, rxq->rspq.idx);
1775 skb_mark_napi_id(skb, &rxq->rspq.napi);
1776 if (rxq->rspq.netdev->features & NETIF_F_RXHASH)
1777 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
1780 if (unlikely(pkt->vlan_ex)) {
1781 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
1782 rxq->stats.vlan_ex++;
1784 ret = napi_gro_frags(&rxq->rspq.napi);
1785 if (ret == GRO_HELD)
1786 rxq->stats.lro_pkts++;
1787 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1788 rxq->stats.lro_merged++;
1790 rxq->stats.rx_cso++;
1794 * t4_ethrx_handler - process an ingress ethernet packet
1795 * @q: the response queue that received the packet
1796 * @rsp: the response queue descriptor holding the RX_PKT message
1797 * @si: the gather list of packet fragments
1799 * Process an ingress ethernet packet and deliver it to the stack.
1801 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1802 const struct pkt_gl *si)
1805 struct sk_buff *skb;
1806 const struct cpl_rx_pkt *pkt;
1807 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1808 struct sge *s = &q->adap->sge;
1809 int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
1810 CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
1811 #ifdef CONFIG_CHELSIO_T4_FCOE
1812 struct port_info *pi;
1815 if (unlikely(*(u8 *)rsp == cpl_trace_pkt))
1816 return handle_trace_pkt(q->adap, si);
1818 pkt = (const struct cpl_rx_pkt *)rsp;
1819 csum_ok = pkt->csum_calc && !pkt->err_vec &&
1820 (q->netdev->features & NETIF_F_RXCSUM);
1821 if ((pkt->l2info & htonl(RXF_TCP_F)) &&
1822 !(cxgb_poll_busy_polling(q)) &&
1823 (q->netdev->features & NETIF_F_GRO) && csum_ok && !pkt->ip_frag) {
1824 do_gro(rxq, si, pkt);
1828 skb = cxgb4_pktgl_to_skb(si, RX_PKT_SKB_LEN, RX_PULL_LEN);
1829 if (unlikely(!skb)) {
1831 rxq->stats.rx_drops++;
1835 __skb_pull(skb, s->pktshift); /* remove ethernet header padding */
1836 skb->protocol = eth_type_trans(skb, q->netdev);
1837 skb_record_rx_queue(skb, q->idx);
1838 if (skb->dev->features & NETIF_F_RXHASH)
1839 skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
1844 if (csum_ok && (pkt->l2info & htonl(RXF_UDP_F | RXF_TCP_F))) {
1845 if (!pkt->ip_frag) {
1846 skb->ip_summed = CHECKSUM_UNNECESSARY;
1847 rxq->stats.rx_cso++;
1848 } else if (pkt->l2info & htonl(RXF_IP_F)) {
1849 __sum16 c = (__force __sum16)pkt->csum;
1850 skb->csum = csum_unfold(c);
1851 skb->ip_summed = CHECKSUM_COMPLETE;
1852 rxq->stats.rx_cso++;
1855 skb_checksum_none_assert(skb);
1856 #ifdef CONFIG_CHELSIO_T4_FCOE
1857 #define CPL_RX_PKT_FLAGS (RXF_PSH_F | RXF_SYN_F | RXF_UDP_F | \
1858 RXF_TCP_F | RXF_IP_F | RXF_IP6_F | RXF_LRO_F)
1860 pi = netdev_priv(skb->dev);
1861 if (!(pkt->l2info & cpu_to_be32(CPL_RX_PKT_FLAGS))) {
1862 if ((pkt->l2info & cpu_to_be32(RXF_FCOE_F)) &&
1863 (pi->fcoe.flags & CXGB_FCOE_ENABLED)) {
1864 if (!(pkt->err_vec & cpu_to_be16(RXERR_CSUM_F)))
1865 skb->ip_summed = CHECKSUM_UNNECESSARY;
1869 #undef CPL_RX_PKT_FLAGS
1870 #endif /* CONFIG_CHELSIO_T4_FCOE */
1873 if (unlikely(pkt->vlan_ex)) {
1874 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), ntohs(pkt->vlan));
1875 rxq->stats.vlan_ex++;
1877 skb_mark_napi_id(skb, &q->napi);
1878 netif_receive_skb(skb);
1883 * restore_rx_bufs - put back a packet's Rx buffers
1884 * @si: the packet gather list
1885 * @q: the SGE free list
1886 * @frags: number of FL buffers to restore
1888 * Puts back on an FL the Rx buffers associated with @si. The buffers
1889 * have already been unmapped and are left unmapped, we mark them so to
1890 * prevent further unmapping attempts.
1892 * This function undoes a series of @unmap_rx_buf calls when we find out
1893 * that the current packet can't be processed right away afterall and we
1894 * need to come back to it later. This is a very rare event and there's
1895 * no effort to make this particularly efficient.
1897 static void restore_rx_bufs(const struct pkt_gl *si, struct sge_fl *q,
1900 struct rx_sw_desc *d;
1904 q->cidx = q->size - 1;
1907 d = &q->sdesc[q->cidx];
1908 d->page = si->frags[frags].page;
1909 d->dma_addr |= RX_UNMAPPED_BUF;
1915 * is_new_response - check if a response is newly written
1916 * @r: the response descriptor
1917 * @q: the response queue
1919 * Returns true if a response descriptor contains a yet unprocessed
1922 static inline bool is_new_response(const struct rsp_ctrl *r,
1923 const struct sge_rspq *q)
1925 return RSPD_GEN(r->type_gen) == q->gen;
1929 * rspq_next - advance to the next entry in a response queue
1932 * Updates the state of a response queue to advance it to the next entry.
1934 static inline void rspq_next(struct sge_rspq *q)
1936 q->cur_desc = (void *)q->cur_desc + q->iqe_len;
1937 if (unlikely(++q->cidx == q->size)) {
1940 q->cur_desc = q->desc;
1945 * process_responses - process responses from an SGE response queue
1946 * @q: the ingress queue to process
1947 * @budget: how many responses can be processed in this round
1949 * Process responses from an SGE response queue up to the supplied budget.
1950 * Responses include received packets as well as control messages from FW
1953 * Additionally choose the interrupt holdoff time for the next interrupt
1954 * on this queue. If the system is under memory shortage use a fairly
1955 * long delay to help recovery.
1957 static int process_responses(struct sge_rspq *q, int budget)
1960 int budget_left = budget;
1961 const struct rsp_ctrl *rc;
1962 struct sge_eth_rxq *rxq = container_of(q, struct sge_eth_rxq, rspq);
1963 struct adapter *adapter = q->adap;
1964 struct sge *s = &adapter->sge;
1966 while (likely(budget_left)) {
1967 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
1968 if (!is_new_response(rc, q))
1972 rsp_type = RSPD_TYPE(rc->type_gen);
1973 if (likely(rsp_type == RSP_TYPE_FLBUF)) {
1974 struct page_frag *fp;
1976 const struct rx_sw_desc *rsd;
1977 u32 len = ntohl(rc->pldbuflen_qid), bufsz, frags;
1979 if (len & RSPD_NEWBUF) {
1980 if (likely(q->offset > 0)) {
1981 free_rx_bufs(q->adap, &rxq->fl, 1);
1984 len = RSPD_LEN(len);
1988 /* gather packet fragments */
1989 for (frags = 0, fp = si.frags; ; frags++, fp++) {
1990 rsd = &rxq->fl.sdesc[rxq->fl.cidx];
1991 bufsz = get_buf_size(adapter, rsd);
1992 fp->page = rsd->page;
1993 fp->offset = q->offset;
1994 fp->size = min(bufsz, len);
1998 unmap_rx_buf(q->adap, &rxq->fl);
2002 * Last buffer remains mapped so explicitly make it
2003 * coherent for CPU access.
2005 dma_sync_single_for_cpu(q->adap->pdev_dev,
2007 fp->size, DMA_FROM_DEVICE);
2009 si.va = page_address(si.frags[0].page) +
2013 si.nfrags = frags + 1;
2014 ret = q->handler(q, q->cur_desc, &si);
2015 if (likely(ret == 0))
2016 q->offset += ALIGN(fp->size, s->fl_align);
2018 restore_rx_bufs(&si, &rxq->fl, frags);
2019 } else if (likely(rsp_type == RSP_TYPE_CPL)) {
2020 ret = q->handler(q, q->cur_desc, NULL);
2022 ret = q->handler(q, (const __be64 *)rc, CXGB4_MSG_AN);
2025 if (unlikely(ret)) {
2026 /* couldn't process descriptor, back off for recovery */
2027 q->next_intr_params = QINTR_TIMER_IDX(NOMEM_TMR_IDX);
2035 if (q->offset >= 0 && rxq->fl.size - rxq->fl.avail >= 16)
2036 __refill_fl(q->adap, &rxq->fl);
2037 return budget - budget_left;
2040 #ifdef CONFIG_NET_RX_BUSY_POLL
2041 int cxgb_busy_poll(struct napi_struct *napi)
2043 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi);
2044 unsigned int params, work_done;
2047 if (!cxgb_poll_lock_poll(q))
2048 return LL_FLUSH_BUSY;
2050 work_done = process_responses(q, 4);
2051 params = QINTR_TIMER_IDX(TIMERREG_COUNTER0_X) | QINTR_CNT_EN;
2052 q->next_intr_params = params;
2053 val = CIDXINC_V(work_done) | SEINTARM_V(params);
2055 /* If we don't have access to the new User GTS (T5+), use the old
2056 * doorbell mechanism; otherwise use the new BAR2 mechanism.
2058 if (unlikely(!q->bar2_addr))
2059 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
2060 val | INGRESSQID_V((u32)q->cntxt_id));
2062 writel(val | INGRESSQID_V(q->bar2_qid),
2063 q->bar2_addr + SGE_UDB_GTS);
2067 cxgb_poll_unlock_poll(q);
2070 #endif /* CONFIG_NET_RX_BUSY_POLL */
2073 * napi_rx_handler - the NAPI handler for Rx processing
2074 * @napi: the napi instance
2075 * @budget: how many packets we can process in this round
2077 * Handler for new data events when using NAPI. This does not need any
2078 * locking or protection from interrupts as data interrupts are off at
2079 * this point and other adapter interrupts do not interfere (the latter
2080 * in not a concern at all with MSI-X as non-data interrupts then have
2081 * a separate handler).
2083 static int napi_rx_handler(struct napi_struct *napi, int budget)
2085 unsigned int params;
2086 struct sge_rspq *q = container_of(napi, struct sge_rspq, napi);
2090 if (!cxgb_poll_lock_napi(q))
2093 work_done = process_responses(q, budget);
2094 if (likely(work_done < budget)) {
2097 napi_complete(napi);
2098 timer_index = QINTR_TIMER_IDX_GET(q->next_intr_params);
2100 if (q->adaptive_rx) {
2101 if (work_done > max(timer_pkt_quota[timer_index],
2103 timer_index = (timer_index + 1);
2105 timer_index = timer_index - 1;
2107 timer_index = clamp(timer_index, 0, SGE_TIMERREGS - 1);
2108 q->next_intr_params = QINTR_TIMER_IDX(timer_index) |
2110 params = q->next_intr_params;
2112 params = q->next_intr_params;
2113 q->next_intr_params = q->intr_params;
2116 params = QINTR_TIMER_IDX(7);
2118 val = CIDXINC_V(work_done) | SEINTARM_V(params);
2120 /* If we don't have access to the new User GTS (T5+), use the old
2121 * doorbell mechanism; otherwise use the new BAR2 mechanism.
2123 if (unlikely(q->bar2_addr == NULL)) {
2124 t4_write_reg(q->adap, MYPF_REG(SGE_PF_GTS_A),
2125 val | INGRESSQID_V((u32)q->cntxt_id));
2127 writel(val | INGRESSQID_V(q->bar2_qid),
2128 q->bar2_addr + SGE_UDB_GTS);
2131 cxgb_poll_unlock_napi(q);
2136 * The MSI-X interrupt handler for an SGE response queue.
2138 irqreturn_t t4_sge_intr_msix(int irq, void *cookie)
2140 struct sge_rspq *q = cookie;
2142 napi_schedule(&q->napi);
2147 * Process the indirect interrupt entries in the interrupt queue and kick off
2148 * NAPI for each queue that has generated an entry.
2150 static unsigned int process_intrq(struct adapter *adap)
2152 unsigned int credits;
2153 const struct rsp_ctrl *rc;
2154 struct sge_rspq *q = &adap->sge.intrq;
2157 spin_lock(&adap->sge.intrq_lock);
2158 for (credits = 0; ; credits++) {
2159 rc = (void *)q->cur_desc + (q->iqe_len - sizeof(*rc));
2160 if (!is_new_response(rc, q))
2164 if (RSPD_TYPE(rc->type_gen) == RSP_TYPE_INTR) {
2165 unsigned int qid = ntohl(rc->pldbuflen_qid);
2167 qid -= adap->sge.ingr_start;
2168 napi_schedule(&adap->sge.ingr_map[qid]->napi);
2174 val = CIDXINC_V(credits) | SEINTARM_V(q->intr_params);
2176 /* If we don't have access to the new User GTS (T5+), use the old
2177 * doorbell mechanism; otherwise use the new BAR2 mechanism.
2179 if (unlikely(q->bar2_addr == NULL)) {
2180 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
2181 val | INGRESSQID_V(q->cntxt_id));
2183 writel(val | INGRESSQID_V(q->bar2_qid),
2184 q->bar2_addr + SGE_UDB_GTS);
2187 spin_unlock(&adap->sge.intrq_lock);
2192 * The MSI interrupt handler, which handles data events from SGE response queues
2193 * as well as error and other async events as they all use the same MSI vector.
2195 static irqreturn_t t4_intr_msi(int irq, void *cookie)
2197 struct adapter *adap = cookie;
2199 t4_slow_intr_handler(adap);
2200 process_intrq(adap);
2205 * Interrupt handler for legacy INTx interrupts.
2206 * Handles data events from SGE response queues as well as error and other
2207 * async events as they all use the same interrupt line.
2209 static irqreturn_t t4_intr_intx(int irq, void *cookie)
2211 struct adapter *adap = cookie;
2213 t4_write_reg(adap, MYPF_REG(PCIE_PF_CLI_A), 0);
2214 if (t4_slow_intr_handler(adap) | process_intrq(adap))
2216 return IRQ_NONE; /* probably shared interrupt */
2220 * t4_intr_handler - select the top-level interrupt handler
2221 * @adap: the adapter
2223 * Selects the top-level interrupt handler based on the type of interrupts
2224 * (MSI-X, MSI, or INTx).
2226 irq_handler_t t4_intr_handler(struct adapter *adap)
2228 if (adap->flags & USING_MSIX)
2229 return t4_sge_intr_msix;
2230 if (adap->flags & USING_MSI)
2232 return t4_intr_intx;
2235 static void sge_rx_timer_cb(unsigned long data)
2238 unsigned int i, idma_same_state_cnt[2];
2239 struct adapter *adap = (struct adapter *)data;
2240 struct sge *s = &adap->sge;
2242 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++)
2243 for (m = s->starving_fl[i]; m; m &= m - 1) {
2244 struct sge_eth_rxq *rxq;
2245 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
2246 struct sge_fl *fl = s->egr_map[id];
2248 clear_bit(id, s->starving_fl);
2249 smp_mb__after_atomic();
2251 if (fl_starving(fl)) {
2252 rxq = container_of(fl, struct sge_eth_rxq, fl);
2253 if (napi_reschedule(&rxq->rspq.napi))
2256 set_bit(id, s->starving_fl);
2260 t4_write_reg(adap, SGE_DEBUG_INDEX_A, 13);
2261 idma_same_state_cnt[0] = t4_read_reg(adap, SGE_DEBUG_DATA_HIGH_A);
2262 idma_same_state_cnt[1] = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
2264 for (i = 0; i < 2; i++) {
2265 u32 debug0, debug11;
2267 /* If the Ingress DMA Same State Counter ("timer") is less
2268 * than 1s, then we can reset our synthesized Stall Timer and
2269 * continue. If we have previously emitted warnings about a
2270 * potential stalled Ingress Queue, issue a note indicating
2271 * that the Ingress Queue has resumed forward progress.
2273 if (idma_same_state_cnt[i] < s->idma_1s_thresh) {
2274 if (s->idma_stalled[i] >= SGE_IDMA_WARN_THRESH)
2275 CH_WARN(adap, "SGE idma%d, queue%u,resumed after %d sec\n",
2277 s->idma_stalled[i]/HZ);
2278 s->idma_stalled[i] = 0;
2282 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
2283 * domain. The first time we get here it'll be because we
2284 * passed the 1s Threshold; each additional time it'll be
2285 * because the RX Timer Callback is being fired on its regular
2288 * If the stall is below our Potential Hung Ingress Queue
2289 * Warning Threshold, continue.
2291 if (s->idma_stalled[i] == 0)
2292 s->idma_stalled[i] = HZ;
2294 s->idma_stalled[i] += RX_QCHECK_PERIOD;
2296 if (s->idma_stalled[i] < SGE_IDMA_WARN_THRESH)
2299 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT Hz */
2300 if (((s->idma_stalled[i] - HZ) % SGE_IDMA_WARN_REPEAT) != 0)
2303 /* Read and save the SGE IDMA State and Queue ID information.
2304 * We do this every time in case it changes across time ...
2306 t4_write_reg(adap, SGE_DEBUG_INDEX_A, 0);
2307 debug0 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
2308 s->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
2310 t4_write_reg(adap, SGE_DEBUG_INDEX_A, 11);
2311 debug11 = t4_read_reg(adap, SGE_DEBUG_DATA_LOW_A);
2312 s->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
2314 CH_WARN(adap, "SGE idma%u, queue%u, maybe stuck state%u %dsecs (debug0=%#x, debug11=%#x)\n",
2315 i, s->idma_qid[i], s->idma_state[i],
2316 s->idma_stalled[i]/HZ, debug0, debug11);
2317 t4_sge_decode_idma_state(adap, s->idma_state[i]);
2320 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
2323 static void sge_tx_timer_cb(unsigned long data)
2326 unsigned int i, budget;
2327 struct adapter *adap = (struct adapter *)data;
2328 struct sge *s = &adap->sge;
2330 for (i = 0; i < BITS_TO_LONGS(s->egr_sz); i++)
2331 for (m = s->txq_maperr[i]; m; m &= m - 1) {
2332 unsigned long id = __ffs(m) + i * BITS_PER_LONG;
2333 struct sge_ofld_txq *txq = s->egr_map[id];
2335 clear_bit(id, s->txq_maperr);
2336 tasklet_schedule(&txq->qresume_tsk);
2339 budget = MAX_TIMER_TX_RECLAIM;
2340 i = s->ethtxq_rover;
2342 struct sge_eth_txq *q = &s->ethtxq[i];
2345 time_after_eq(jiffies, q->txq->trans_start + HZ / 100) &&
2346 __netif_tx_trylock(q->txq)) {
2347 int avail = reclaimable(&q->q);
2353 free_tx_desc(adap, &q->q, avail, true);
2354 q->q.in_use -= avail;
2357 __netif_tx_unlock(q->txq);
2360 if (++i >= s->ethqsets)
2362 } while (budget && i != s->ethtxq_rover);
2363 s->ethtxq_rover = i;
2364 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2368 * bar2_address - return the BAR2 address for an SGE Queue's Registers
2369 * @adapter: the adapter
2370 * @qid: the SGE Queue ID
2371 * @qtype: the SGE Queue Type (Egress or Ingress)
2372 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
2374 * Returns the BAR2 address for the SGE Queue Registers associated with
2375 * @qid. If BAR2 SGE Registers aren't available, returns NULL. Also
2376 * returns the BAR2 Queue ID to be used with writes to the BAR2 SGE
2377 * Queue Registers. If the BAR2 Queue ID is 0, then "Inferred Queue ID"
2378 * Registers are supported (e.g. the Write Combining Doorbell Buffer).
2380 static void __iomem *bar2_address(struct adapter *adapter,
2382 enum t4_bar2_qtype qtype,
2383 unsigned int *pbar2_qid)
2388 ret = cxgb4_t4_bar2_sge_qregs(adapter, qid, qtype,
2389 &bar2_qoffset, pbar2_qid);
2393 return adapter->bar2 + bar2_qoffset;
2396 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
2397 struct net_device *dev, int intr_idx,
2398 struct sge_fl *fl, rspq_handler_t hnd)
2402 struct sge *s = &adap->sge;
2403 struct port_info *pi = netdev_priv(dev);
2405 /* Size needs to be multiple of 16, including status entry. */
2406 iq->size = roundup(iq->size, 16);
2408 iq->desc = alloc_ring(adap->pdev_dev, iq->size, iq->iqe_len, 0,
2409 &iq->phys_addr, NULL, 0, NUMA_NO_NODE);
2413 memset(&c, 0, sizeof(c));
2414 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
2415 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2416 FW_IQ_CMD_PFN_V(adap->fn) | FW_IQ_CMD_VFN_V(0));
2417 c.alloc_to_len16 = htonl(FW_IQ_CMD_ALLOC_F | FW_IQ_CMD_IQSTART_F |
2419 c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE_V(FW_IQ_TYPE_FL_INT_CAP) |
2420 FW_IQ_CMD_IQASYNCH_V(fwevtq) | FW_IQ_CMD_VIID_V(pi->viid) |
2421 FW_IQ_CMD_IQANDST_V(intr_idx < 0) | FW_IQ_CMD_IQANUD_V(1) |
2422 FW_IQ_CMD_IQANDSTINDEX_V(intr_idx >= 0 ? intr_idx :
2424 c.iqdroprss_to_iqesize = htons(FW_IQ_CMD_IQPCIECH_V(pi->tx_chan) |
2425 FW_IQ_CMD_IQGTSMODE_F |
2426 FW_IQ_CMD_IQINTCNTTHRESH_V(iq->pktcnt_idx) |
2427 FW_IQ_CMD_IQESIZE_V(ilog2(iq->iqe_len) - 4));
2428 c.iqsize = htons(iq->size);
2429 c.iqaddr = cpu_to_be64(iq->phys_addr);
2432 fl->size = roundup(fl->size, 8);
2433 fl->desc = alloc_ring(adap->pdev_dev, fl->size, sizeof(__be64),
2434 sizeof(struct rx_sw_desc), &fl->addr,
2435 &fl->sdesc, s->stat_len, NUMA_NO_NODE);
2439 flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
2440 c.iqns_to_fl0congen = htonl(FW_IQ_CMD_FL0PACKEN_F |
2441 FW_IQ_CMD_FL0FETCHRO_F |
2442 FW_IQ_CMD_FL0DATARO_F |
2443 FW_IQ_CMD_FL0PADEN_F);
2444 c.fl0dcaen_to_fl0cidxfthresh = htons(FW_IQ_CMD_FL0FBMIN_V(2) |
2445 FW_IQ_CMD_FL0FBMAX_V(3));
2446 c.fl0size = htons(flsz);
2447 c.fl0addr = cpu_to_be64(fl->addr);
2450 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2454 netif_napi_add(dev, &iq->napi, napi_rx_handler, 64);
2455 napi_hash_add(&iq->napi);
2456 iq->cur_desc = iq->desc;
2459 iq->next_intr_params = iq->intr_params;
2460 iq->cntxt_id = ntohs(c.iqid);
2461 iq->abs_id = ntohs(c.physiqid);
2462 iq->bar2_addr = bar2_address(adap,
2464 T4_BAR2_QTYPE_INGRESS,
2466 iq->size--; /* subtract status entry */
2470 /* set offset to -1 to distinguish ingress queues without FL */
2471 iq->offset = fl ? 0 : -1;
2473 adap->sge.ingr_map[iq->cntxt_id - adap->sge.ingr_start] = iq;
2476 fl->cntxt_id = ntohs(c.fl0id);
2477 fl->avail = fl->pend_cred = 0;
2478 fl->pidx = fl->cidx = 0;
2479 fl->alloc_failed = fl->large_alloc_failed = fl->starving = 0;
2480 adap->sge.egr_map[fl->cntxt_id - adap->sge.egr_start] = fl;
2482 /* Note, we must initialize the BAR2 Free List User Doorbell
2483 * information before refilling the Free List!
2485 fl->bar2_addr = bar2_address(adap,
2487 T4_BAR2_QTYPE_EGRESS,
2489 refill_fl(adap, fl, fl_cap(fl), GFP_KERNEL);
2497 dma_free_coherent(adap->pdev_dev, iq->size * iq->iqe_len,
2498 iq->desc, iq->phys_addr);
2501 if (fl && fl->desc) {
2504 dma_free_coherent(adap->pdev_dev, flsz * sizeof(struct tx_desc),
2505 fl->desc, fl->addr);
2511 static void init_txq(struct adapter *adap, struct sge_txq *q, unsigned int id)
2514 q->bar2_addr = bar2_address(adap,
2516 T4_BAR2_QTYPE_EGRESS,
2519 q->cidx = q->pidx = 0;
2520 q->stops = q->restarts = 0;
2521 q->stat = (void *)&q->desc[q->size];
2522 spin_lock_init(&q->db_lock);
2523 adap->sge.egr_map[id - adap->sge.egr_start] = q;
2526 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
2527 struct net_device *dev, struct netdev_queue *netdevq,
2531 struct fw_eq_eth_cmd c;
2532 struct sge *s = &adap->sge;
2533 struct port_info *pi = netdev_priv(dev);
2535 /* Add status entries */
2536 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2538 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2539 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2540 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len,
2541 netdev_queue_numa_node_read(netdevq));
2545 memset(&c, 0, sizeof(c));
2546 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD) | FW_CMD_REQUEST_F |
2547 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2548 FW_EQ_ETH_CMD_PFN_V(adap->fn) |
2549 FW_EQ_ETH_CMD_VFN_V(0));
2550 c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_ALLOC_F |
2551 FW_EQ_ETH_CMD_EQSTART_F | FW_LEN16(c));
2552 c.viid_pkd = htonl(FW_EQ_ETH_CMD_AUTOEQUEQE_F |
2553 FW_EQ_ETH_CMD_VIID_V(pi->viid));
2554 c.fetchszm_to_iqid = htonl(FW_EQ_ETH_CMD_HOSTFCMODE_V(2) |
2555 FW_EQ_ETH_CMD_PCIECHN_V(pi->tx_chan) |
2556 FW_EQ_ETH_CMD_FETCHRO_V(1) |
2557 FW_EQ_ETH_CMD_IQID_V(iqid));
2558 c.dcaen_to_eqsize = htonl(FW_EQ_ETH_CMD_FBMIN_V(2) |
2559 FW_EQ_ETH_CMD_FBMAX_V(3) |
2560 FW_EQ_ETH_CMD_CIDXFTHRESH_V(5) |
2561 FW_EQ_ETH_CMD_EQSIZE_V(nentries));
2562 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2564 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2566 kfree(txq->q.sdesc);
2567 txq->q.sdesc = NULL;
2568 dma_free_coherent(adap->pdev_dev,
2569 nentries * sizeof(struct tx_desc),
2570 txq->q.desc, txq->q.phys_addr);
2575 init_txq(adap, &txq->q, FW_EQ_ETH_CMD_EQID_G(ntohl(c.eqid_pkd)));
2577 txq->tso = txq->tx_cso = txq->vlan_ins = 0;
2578 txq->mapping_err = 0;
2582 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
2583 struct net_device *dev, unsigned int iqid,
2584 unsigned int cmplqid)
2587 struct fw_eq_ctrl_cmd c;
2588 struct sge *s = &adap->sge;
2589 struct port_info *pi = netdev_priv(dev);
2591 /* Add status entries */
2592 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2594 txq->q.desc = alloc_ring(adap->pdev_dev, nentries,
2595 sizeof(struct tx_desc), 0, &txq->q.phys_addr,
2596 NULL, 0, NUMA_NO_NODE);
2600 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST_F |
2601 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2602 FW_EQ_CTRL_CMD_PFN_V(adap->fn) |
2603 FW_EQ_CTRL_CMD_VFN_V(0));
2604 c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_ALLOC_F |
2605 FW_EQ_CTRL_CMD_EQSTART_F | FW_LEN16(c));
2606 c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_CMPLIQID_V(cmplqid));
2607 c.physeqid_pkd = htonl(0);
2608 c.fetchszm_to_iqid = htonl(FW_EQ_CTRL_CMD_HOSTFCMODE_V(2) |
2609 FW_EQ_CTRL_CMD_PCIECHN_V(pi->tx_chan) |
2610 FW_EQ_CTRL_CMD_FETCHRO_F |
2611 FW_EQ_CTRL_CMD_IQID_V(iqid));
2612 c.dcaen_to_eqsize = htonl(FW_EQ_CTRL_CMD_FBMIN_V(2) |
2613 FW_EQ_CTRL_CMD_FBMAX_V(3) |
2614 FW_EQ_CTRL_CMD_CIDXFTHRESH_V(5) |
2615 FW_EQ_CTRL_CMD_EQSIZE_V(nentries));
2616 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2618 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2620 dma_free_coherent(adap->pdev_dev,
2621 nentries * sizeof(struct tx_desc),
2622 txq->q.desc, txq->q.phys_addr);
2627 init_txq(adap, &txq->q, FW_EQ_CTRL_CMD_EQID_G(ntohl(c.cmpliqid_eqid)));
2629 skb_queue_head_init(&txq->sendq);
2630 tasklet_init(&txq->qresume_tsk, restart_ctrlq, (unsigned long)txq);
2635 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
2636 struct net_device *dev, unsigned int iqid)
2639 struct fw_eq_ofld_cmd c;
2640 struct sge *s = &adap->sge;
2641 struct port_info *pi = netdev_priv(dev);
2643 /* Add status entries */
2644 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2646 txq->q.desc = alloc_ring(adap->pdev_dev, txq->q.size,
2647 sizeof(struct tx_desc), sizeof(struct tx_sw_desc),
2648 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len,
2653 memset(&c, 0, sizeof(c));
2654 c.op_to_vfn = htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST_F |
2655 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
2656 FW_EQ_OFLD_CMD_PFN_V(adap->fn) |
2657 FW_EQ_OFLD_CMD_VFN_V(0));
2658 c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_ALLOC_F |
2659 FW_EQ_OFLD_CMD_EQSTART_F | FW_LEN16(c));
2660 c.fetchszm_to_iqid = htonl(FW_EQ_OFLD_CMD_HOSTFCMODE_V(2) |
2661 FW_EQ_OFLD_CMD_PCIECHN_V(pi->tx_chan) |
2662 FW_EQ_OFLD_CMD_FETCHRO_F |
2663 FW_EQ_OFLD_CMD_IQID_V(iqid));
2664 c.dcaen_to_eqsize = htonl(FW_EQ_OFLD_CMD_FBMIN_V(2) |
2665 FW_EQ_OFLD_CMD_FBMAX_V(3) |
2666 FW_EQ_OFLD_CMD_CIDXFTHRESH_V(5) |
2667 FW_EQ_OFLD_CMD_EQSIZE_V(nentries));
2668 c.eqaddr = cpu_to_be64(txq->q.phys_addr);
2670 ret = t4_wr_mbox(adap, adap->fn, &c, sizeof(c), &c);
2672 kfree(txq->q.sdesc);
2673 txq->q.sdesc = NULL;
2674 dma_free_coherent(adap->pdev_dev,
2675 nentries * sizeof(struct tx_desc),
2676 txq->q.desc, txq->q.phys_addr);
2681 init_txq(adap, &txq->q, FW_EQ_OFLD_CMD_EQID_G(ntohl(c.eqid_pkd)));
2683 skb_queue_head_init(&txq->sendq);
2684 tasklet_init(&txq->qresume_tsk, restart_ofldq, (unsigned long)txq);
2686 txq->mapping_err = 0;
2690 static void free_txq(struct adapter *adap, struct sge_txq *q)
2692 struct sge *s = &adap->sge;
2694 dma_free_coherent(adap->pdev_dev,
2695 q->size * sizeof(struct tx_desc) + s->stat_len,
2696 q->desc, q->phys_addr);
2702 static void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq,
2705 struct sge *s = &adap->sge;
2706 unsigned int fl_id = fl ? fl->cntxt_id : 0xffff;
2708 adap->sge.ingr_map[rq->cntxt_id - adap->sge.ingr_start] = NULL;
2709 t4_iq_free(adap, adap->fn, adap->fn, 0, FW_IQ_TYPE_FL_INT_CAP,
2710 rq->cntxt_id, fl_id, 0xffff);
2711 dma_free_coherent(adap->pdev_dev, (rq->size + 1) * rq->iqe_len,
2712 rq->desc, rq->phys_addr);
2713 napi_hash_del(&rq->napi);
2714 netif_napi_del(&rq->napi);
2716 rq->cntxt_id = rq->abs_id = 0;
2720 free_rx_bufs(adap, fl, fl->avail);
2721 dma_free_coherent(adap->pdev_dev, fl->size * 8 + s->stat_len,
2722 fl->desc, fl->addr);
2731 * t4_free_ofld_rxqs - free a block of consecutive Rx queues
2732 * @adap: the adapter
2733 * @n: number of queues
2734 * @q: pointer to first queue
2736 * Release the resources of a consecutive block of offload Rx queues.
2738 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q)
2740 for ( ; n; n--, q++)
2742 free_rspq_fl(adap, &q->rspq,
2743 q->fl.size ? &q->fl : NULL);
2747 * t4_free_sge_resources - free SGE resources
2748 * @adap: the adapter
2750 * Frees resources used by the SGE queue sets.
2752 void t4_free_sge_resources(struct adapter *adap)
2755 struct sge_eth_rxq *eq = adap->sge.ethrxq;
2756 struct sge_eth_txq *etq = adap->sge.ethtxq;
2758 /* clean up Ethernet Tx/Rx queues */
2759 for (i = 0; i < adap->sge.ethqsets; i++, eq++, etq++) {
2761 free_rspq_fl(adap, &eq->rspq,
2762 eq->fl.size ? &eq->fl : NULL);
2764 t4_eth_eq_free(adap, adap->fn, adap->fn, 0,
2766 free_tx_desc(adap, &etq->q, etq->q.in_use, true);
2767 kfree(etq->q.sdesc);
2768 free_txq(adap, &etq->q);
2772 /* clean up RDMA and iSCSI Rx queues */
2773 t4_free_ofld_rxqs(adap, adap->sge.ofldqsets, adap->sge.ofldrxq);
2774 t4_free_ofld_rxqs(adap, adap->sge.rdmaqs, adap->sge.rdmarxq);
2775 t4_free_ofld_rxqs(adap, adap->sge.rdmaciqs, adap->sge.rdmaciq);
2777 /* clean up offload Tx queues */
2778 for (i = 0; i < ARRAY_SIZE(adap->sge.ofldtxq); i++) {
2779 struct sge_ofld_txq *q = &adap->sge.ofldtxq[i];
2782 tasklet_kill(&q->qresume_tsk);
2783 t4_ofld_eq_free(adap, adap->fn, adap->fn, 0,
2785 free_tx_desc(adap, &q->q, q->q.in_use, false);
2787 __skb_queue_purge(&q->sendq);
2788 free_txq(adap, &q->q);
2792 /* clean up control Tx queues */
2793 for (i = 0; i < ARRAY_SIZE(adap->sge.ctrlq); i++) {
2794 struct sge_ctrl_txq *cq = &adap->sge.ctrlq[i];
2797 tasklet_kill(&cq->qresume_tsk);
2798 t4_ctrl_eq_free(adap, adap->fn, adap->fn, 0,
2800 __skb_queue_purge(&cq->sendq);
2801 free_txq(adap, &cq->q);
2805 if (adap->sge.fw_evtq.desc)
2806 free_rspq_fl(adap, &adap->sge.fw_evtq, NULL);
2808 if (adap->sge.intrq.desc)
2809 free_rspq_fl(adap, &adap->sge.intrq, NULL);
2811 /* clear the reverse egress queue map */
2812 memset(adap->sge.egr_map, 0,
2813 adap->sge.egr_sz * sizeof(*adap->sge.egr_map));
2816 void t4_sge_start(struct adapter *adap)
2818 adap->sge.ethtxq_rover = 0;
2819 mod_timer(&adap->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2820 mod_timer(&adap->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2824 * t4_sge_stop - disable SGE operation
2825 * @adap: the adapter
2827 * Stop tasklets and timers associated with the DMA engine. Note that
2828 * this is effective only if measures have been taken to disable any HW
2829 * events that may restart them.
2831 void t4_sge_stop(struct adapter *adap)
2834 struct sge *s = &adap->sge;
2836 if (in_interrupt()) /* actions below require waiting */
2839 if (s->rx_timer.function)
2840 del_timer_sync(&s->rx_timer);
2841 if (s->tx_timer.function)
2842 del_timer_sync(&s->tx_timer);
2844 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++) {
2845 struct sge_ofld_txq *q = &s->ofldtxq[i];
2848 tasklet_kill(&q->qresume_tsk);
2850 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++) {
2851 struct sge_ctrl_txq *cq = &s->ctrlq[i];
2854 tasklet_kill(&cq->qresume_tsk);
2859 * t4_sge_init_soft - grab core SGE values needed by SGE code
2860 * @adap: the adapter
2862 * We need to grab the SGE operating parameters that we need to have
2863 * in order to do our job and make sure we can live with them.
2866 static int t4_sge_init_soft(struct adapter *adap)
2868 struct sge *s = &adap->sge;
2869 u32 fl_small_pg, fl_large_pg, fl_small_mtu, fl_large_mtu;
2870 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
2871 u32 ingress_rx_threshold;
2874 * Verify that CPL messages are going to the Ingress Queue for
2875 * process_responses() and that only packet data is going to the
2878 if ((t4_read_reg(adap, SGE_CONTROL_A) & RXPKTCPLMODE_F) !=
2879 RXPKTCPLMODE_V(RXPKTCPLMODE_SPLIT_X)) {
2880 dev_err(adap->pdev_dev, "bad SGE CPL MODE\n");
2885 * Validate the Host Buffer Register Array indices that we want to
2888 * XXX Note that we should really read through the Host Buffer Size
2889 * XXX register array and find the indices of the Buffer Sizes which
2890 * XXX meet our needs!
2892 #define READ_FL_BUF(x) \
2893 t4_read_reg(adap, SGE_FL_BUFFER_SIZE0_A+(x)*sizeof(u32))
2895 fl_small_pg = READ_FL_BUF(RX_SMALL_PG_BUF);
2896 fl_large_pg = READ_FL_BUF(RX_LARGE_PG_BUF);
2897 fl_small_mtu = READ_FL_BUF(RX_SMALL_MTU_BUF);
2898 fl_large_mtu = READ_FL_BUF(RX_LARGE_MTU_BUF);
2900 /* We only bother using the Large Page logic if the Large Page Buffer
2901 * is larger than our Page Size Buffer.
2903 if (fl_large_pg <= fl_small_pg)
2908 /* The Page Size Buffer must be exactly equal to our Page Size and the
2909 * Large Page Size Buffer should be 0 (per above) or a power of 2.
2911 if (fl_small_pg != PAGE_SIZE ||
2912 (fl_large_pg & (fl_large_pg-1)) != 0) {
2913 dev_err(adap->pdev_dev, "bad SGE FL page buffer sizes [%d, %d]\n",
2914 fl_small_pg, fl_large_pg);
2918 s->fl_pg_order = ilog2(fl_large_pg) - PAGE_SHIFT;
2920 if (fl_small_mtu < FL_MTU_SMALL_BUFSIZE(adap) ||
2921 fl_large_mtu < FL_MTU_LARGE_BUFSIZE(adap)) {
2922 dev_err(adap->pdev_dev, "bad SGE FL MTU sizes [%d, %d]\n",
2923 fl_small_mtu, fl_large_mtu);
2928 * Retrieve our RX interrupt holdoff timer values and counter
2929 * threshold values from the SGE parameters.
2931 timer_value_0_and_1 = t4_read_reg(adap, SGE_TIMER_VALUE_0_AND_1_A);
2932 timer_value_2_and_3 = t4_read_reg(adap, SGE_TIMER_VALUE_2_AND_3_A);
2933 timer_value_4_and_5 = t4_read_reg(adap, SGE_TIMER_VALUE_4_AND_5_A);
2934 s->timer_val[0] = core_ticks_to_us(adap,
2935 TIMERVALUE0_G(timer_value_0_and_1));
2936 s->timer_val[1] = core_ticks_to_us(adap,
2937 TIMERVALUE1_G(timer_value_0_and_1));
2938 s->timer_val[2] = core_ticks_to_us(adap,
2939 TIMERVALUE2_G(timer_value_2_and_3));
2940 s->timer_val[3] = core_ticks_to_us(adap,
2941 TIMERVALUE3_G(timer_value_2_and_3));
2942 s->timer_val[4] = core_ticks_to_us(adap,
2943 TIMERVALUE4_G(timer_value_4_and_5));
2944 s->timer_val[5] = core_ticks_to_us(adap,
2945 TIMERVALUE5_G(timer_value_4_and_5));
2947 ingress_rx_threshold = t4_read_reg(adap, SGE_INGRESS_RX_THRESHOLD_A);
2948 s->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
2949 s->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);
2950 s->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);
2951 s->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);
2957 * t4_sge_init - initialize SGE
2958 * @adap: the adapter
2960 * Perform low-level SGE code initialization needed every time after a
2963 int t4_sge_init(struct adapter *adap)
2965 struct sge *s = &adap->sge;
2966 u32 sge_control, sge_control2, sge_conm_ctrl;
2967 unsigned int ingpadboundary, ingpackboundary;
2968 int ret, egress_threshold;
2971 * Ingress Padding Boundary and Egress Status Page Size are set up by
2972 * t4_fixup_host_params().
2974 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
2975 s->pktshift = PKTSHIFT_G(sge_control);
2976 s->stat_len = (sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64;
2978 /* T4 uses a single control field to specify both the PCIe Padding and
2979 * Packing Boundary. T5 introduced the ability to specify these
2980 * separately. The actual Ingress Packet Data alignment boundary
2981 * within Packed Buffer Mode is the maximum of these two
2984 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) +
2985 INGPADBOUNDARY_SHIFT_X);
2986 if (is_t4(adap->params.chip)) {
2987 s->fl_align = ingpadboundary;
2989 /* T5 has a different interpretation of one of the PCIe Packing
2992 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
2993 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
2994 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
2995 ingpackboundary = 16;
2997 ingpackboundary = 1 << (ingpackboundary +
2998 INGPACKBOUNDARY_SHIFT_X);
3000 s->fl_align = max(ingpadboundary, ingpackboundary);
3003 ret = t4_sge_init_soft(adap);
3008 * A FL with <= fl_starve_thres buffers is starving and a periodic
3009 * timer will attempt to refill it. This needs to be larger than the
3010 * SGE's Egress Congestion Threshold. If it isn't, then we can get
3011 * stuck waiting for new packets while the SGE is waiting for us to
3012 * give it more Free List entries. (Note that the SGE's Egress
3013 * Congestion Threshold is in units of 2 Free List pointers.) For T4,
3014 * there was only a single field to control this. For T5 there's the
3015 * original field which now only applies to Unpacked Mode Free List
3016 * buffers and a new field which only applies to Packed Mode Free List
3019 sge_conm_ctrl = t4_read_reg(adap, SGE_CONM_CTRL_A);
3020 if (is_t4(adap->params.chip))
3021 egress_threshold = EGRTHRESHOLD_G(sge_conm_ctrl);
3023 egress_threshold = EGRTHRESHOLDPACKING_G(sge_conm_ctrl);
3024 s->fl_starve_thres = 2*egress_threshold + 1;
3026 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adap);
3027 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adap);
3028 s->idma_1s_thresh = core_ticks_per_usec(adap) * 1000000; /* 1 s */
3029 s->idma_stalled[0] = 0;
3030 s->idma_stalled[1] = 0;
3031 spin_lock_init(&s->intrq_lock);