2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW4_CFNAME "cxgb4/t4-config.txt"
139 #define FW5_CFNAME "cxgb4/t5-config.txt"
141 MODULE_DESCRIPTION(DRV_DESC);
142 MODULE_AUTHOR("Chelsio Communications");
143 MODULE_LICENSE("Dual BSD/GPL");
144 MODULE_VERSION(DRV_VERSION);
145 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
146 MODULE_FIRMWARE(FW4_FNAME);
147 MODULE_FIRMWARE(FW5_FNAME);
150 * Normally we're willing to become the firmware's Master PF but will be happy
151 * if another PF has already become the Master and initialized the adapter.
152 * Setting "force_init" will cause this driver to forcibly establish itself as
153 * the Master PF and initialize the adapter.
155 static uint force_init;
157 module_param(force_init, uint, 0644);
158 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
161 * Normally if the firmware we connect to has Configuration File support, we
162 * use that and only fall back to the old Driver-based initialization if the
163 * Configuration File fails for some reason. If force_old_init is set, then
164 * we'll always use the old Driver-based initialization sequence.
166 static uint force_old_init;
168 module_param(force_old_init, uint, 0644);
169 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence, deprecated"
172 static int dflt_msg_enable = DFLT_MSG_ENABLE;
174 module_param(dflt_msg_enable, int, 0644);
175 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
178 * The driver uses the best interrupt scheme available on a platform in the
179 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
180 * of these schemes the driver may consider as follows:
182 * msi = 2: choose from among all three options
183 * msi = 1: only consider MSI and INTx interrupts
184 * msi = 0: force INTx interrupts
188 module_param(msi, int, 0644);
189 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
192 * Queue interrupt hold-off timer values. Queues default to the first of these
195 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
197 module_param_array(intr_holdoff, uint, NULL, 0644);
198 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
199 "0..4 in microseconds, deprecated parameter");
201 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
203 module_param_array(intr_cnt, uint, NULL, 0644);
204 MODULE_PARM_DESC(intr_cnt,
205 "thresholds 1..3 for queue interrupt packet counters, "
206 "deprecated parameter");
209 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
210 * offset by 2 bytes in order to have the IP headers line up on 4-byte
211 * boundaries. This is a requirement for many architectures which will throw
212 * a machine check fault if an attempt is made to access one of the 4-byte IP
213 * header fields on a non-4-byte boundary. And it's a major performance issue
214 * even on some architectures which allow it like some implementations of the
215 * x86 ISA. However, some architectures don't mind this and for some very
216 * edge-case performance sensitive applications (like forwarding large volumes
217 * of small packets), setting this DMA offset to 0 will decrease the number of
218 * PCI-E Bus transfers enough to measurably affect performance.
220 static int rx_dma_offset = 2;
224 #ifdef CONFIG_PCI_IOV
225 module_param(vf_acls, bool, 0644);
226 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement, "
227 "deprecated parameter");
229 /* Configure the number of PCI-E Virtual Function which are to be instantiated
230 * on SR-IOV Capable Physical Functions.
232 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
234 module_param_array(num_vf, uint, NULL, 0644);
235 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
238 /* TX Queue select used to determine what algorithm to use for selecting TX
239 * queue. Select between the kernel provided function (select_queue=0) or user
240 * cxgb_select_queue function (select_queue=1)
242 * Default: select_queue=0
244 static int select_queue;
245 module_param(select_queue, int, 0644);
246 MODULE_PARM_DESC(select_queue,
247 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
249 static unsigned int tp_vlan_pri_map = HW_TPL_FR_MT_PR_IV_P_FC;
251 module_param(tp_vlan_pri_map, uint, 0644);
252 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration, "
253 "deprecated parameter");
255 static struct dentry *cxgb4_debugfs_root;
257 static LIST_HEAD(adapter_list);
258 static DEFINE_MUTEX(uld_mutex);
259 /* Adapter list to be accessed from atomic context */
260 static LIST_HEAD(adap_rcu_list);
261 static DEFINE_SPINLOCK(adap_rcu_lock);
262 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
263 static const char *uld_str[] = { "RDMA", "iSCSI" };
265 static void link_report(struct net_device *dev)
267 if (!netif_carrier_ok(dev))
268 netdev_info(dev, "link down\n");
270 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
272 const char *s = "10Mbps";
273 const struct port_info *p = netdev_priv(dev);
275 switch (p->link_cfg.speed) {
290 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
295 #ifdef CONFIG_CHELSIO_T4_DCB
296 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
297 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
299 struct port_info *pi = netdev_priv(dev);
300 struct adapter *adap = pi->adapter;
301 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
304 /* We use a simple mapping of Port TX Queue Index to DCB
305 * Priority when we're enabling DCB.
307 for (i = 0; i < pi->nqsets; i++, txq++) {
311 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
313 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
314 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
315 value = enable ? i : 0xffffffff;
317 /* Since we can be called while atomic (from "interrupt
318 * level") we need to issue the Set Parameters Commannd
319 * without sleeping (timeout < 0).
321 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
325 dev_err(adap->pdev_dev,
326 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
327 enable ? "set" : "unset", pi->port_id, i, -err);
329 txq->dcb_prio = value;
332 #endif /* CONFIG_CHELSIO_T4_DCB */
334 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
336 struct net_device *dev = adapter->port[port_id];
338 /* Skip changes from disabled ports. */
339 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
341 netif_carrier_on(dev);
343 #ifdef CONFIG_CHELSIO_T4_DCB
344 cxgb4_dcb_state_init(dev);
345 dcb_tx_queue_prio_enable(dev, false);
346 #endif /* CONFIG_CHELSIO_T4_DCB */
347 netif_carrier_off(dev);
354 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
356 static const char *mod_str[] = {
357 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
360 const struct net_device *dev = adap->port[port_id];
361 const struct port_info *pi = netdev_priv(dev);
363 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
364 netdev_info(dev, "port module unplugged\n");
365 else if (pi->mod_type < ARRAY_SIZE(mod_str))
366 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
370 * Configure the exact and hash address filters to handle a port's multicast
371 * and secondary unicast MAC addresses.
373 static int set_addr_filters(const struct net_device *dev, bool sleep)
381 const struct netdev_hw_addr *ha;
382 int uc_cnt = netdev_uc_count(dev);
383 int mc_cnt = netdev_mc_count(dev);
384 const struct port_info *pi = netdev_priv(dev);
385 unsigned int mb = pi->adapter->fn;
387 /* first do the secondary unicast addresses */
388 netdev_for_each_uc_addr(ha, dev) {
389 addr[naddr++] = ha->addr;
390 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
391 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
392 naddr, addr, filt_idx, &uhash, sleep);
401 /* next set up the multicast addresses */
402 netdev_for_each_mc_addr(ha, dev) {
403 addr[naddr++] = ha->addr;
404 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
405 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
406 naddr, addr, filt_idx, &mhash, sleep);
415 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
416 uhash | mhash, sleep);
419 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
420 module_param(dbfifo_int_thresh, int, 0644);
421 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
424 * usecs to sleep while draining the dbfifo
426 static int dbfifo_drain_delay = 1000;
427 module_param(dbfifo_drain_delay, int, 0644);
428 MODULE_PARM_DESC(dbfifo_drain_delay,
429 "usecs to sleep while draining the dbfifo");
432 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
433 * If @mtu is -1 it is left unchanged.
435 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
438 struct port_info *pi = netdev_priv(dev);
440 ret = set_addr_filters(dev, sleep_ok);
442 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
443 (dev->flags & IFF_PROMISC) ? 1 : 0,
444 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
450 * link_start - enable a port
451 * @dev: the port to enable
453 * Performs the MAC and PHY actions needed to enable a port.
455 static int link_start(struct net_device *dev)
458 struct port_info *pi = netdev_priv(dev);
459 unsigned int mb = pi->adapter->fn;
462 * We do not set address filters and promiscuity here, the stack does
463 * that step explicitly.
465 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
466 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
468 ret = t4_change_mac(pi->adapter, mb, pi->viid,
469 pi->xact_addr_filt, dev->dev_addr, true,
472 pi->xact_addr_filt = ret;
477 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
481 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
482 true, CXGB4_DCB_ENABLED);
489 int cxgb4_dcb_enabled(const struct net_device *dev)
491 #ifdef CONFIG_CHELSIO_T4_DCB
492 struct port_info *pi = netdev_priv(dev);
494 if (!pi->dcb.enabled)
497 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
498 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
503 EXPORT_SYMBOL(cxgb4_dcb_enabled);
505 #ifdef CONFIG_CHELSIO_T4_DCB
506 /* Handle a Data Center Bridging update message from the firmware. */
507 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
509 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
510 struct net_device *dev = adap->port[port];
511 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
514 cxgb4_dcb_handle_fw_update(adap, pcmd);
515 new_dcb_enabled = cxgb4_dcb_enabled(dev);
517 /* If the DCB has become enabled or disabled on the port then we're
518 * going to need to set up/tear down DCB Priority parameters for the
519 * TX Queues associated with the port.
521 if (new_dcb_enabled != old_dcb_enabled)
522 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
524 #endif /* CONFIG_CHELSIO_T4_DCB */
526 /* Clear a filter and release any of its resources that we own. This also
527 * clears the filter's "pending" status.
529 static void clear_filter(struct adapter *adap, struct filter_entry *f)
531 /* If the new or old filter have loopback rewriteing rules then we'll
532 * need to free any existing Layer Two Table (L2T) entries of the old
533 * filter rule. The firmware will handle freeing up any Source MAC
534 * Table (SMT) entries used for rewriting Source MAC Addresses in
538 cxgb4_l2t_release(f->l2t);
540 /* The zeroing of the filter rule below clears the filter valid,
541 * pending, locked flags, l2t pointer, etc. so it's all we need for
544 memset(f, 0, sizeof(*f));
547 /* Handle a filter write/deletion reply.
549 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
551 unsigned int idx = GET_TID(rpl);
552 unsigned int nidx = idx - adap->tids.ftid_base;
554 struct filter_entry *f;
556 if (idx >= adap->tids.ftid_base && nidx <
557 (adap->tids.nftids + adap->tids.nsftids)) {
559 ret = TCB_COOKIE_G(rpl->cookie);
560 f = &adap->tids.ftid_tab[idx];
562 if (ret == FW_FILTER_WR_FLT_DELETED) {
563 /* Clear the filter when we get confirmation from the
564 * hardware that the filter has been deleted.
566 clear_filter(adap, f);
567 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
568 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
570 clear_filter(adap, f);
571 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
572 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
573 f->pending = 0; /* asynchronous setup completed */
576 /* Something went wrong. Issue a warning about the
577 * problem and clear everything out.
579 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
581 clear_filter(adap, f);
586 /* Response queue handler for the FW event queue.
588 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
589 const struct pkt_gl *gl)
591 u8 opcode = ((const struct rss_header *)rsp)->opcode;
593 rsp++; /* skip RSS header */
595 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
597 if (unlikely(opcode == CPL_FW4_MSG &&
598 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
600 opcode = ((const struct rss_header *)rsp)->opcode;
602 if (opcode != CPL_SGE_EGR_UPDATE) {
603 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
609 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
610 const struct cpl_sge_egr_update *p = (void *)rsp;
611 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
614 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
616 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
617 struct sge_eth_txq *eq;
619 eq = container_of(txq, struct sge_eth_txq, q);
620 netif_tx_wake_queue(eq->txq);
622 struct sge_ofld_txq *oq;
624 oq = container_of(txq, struct sge_ofld_txq, q);
625 tasklet_schedule(&oq->qresume_tsk);
627 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
628 const struct cpl_fw6_msg *p = (void *)rsp;
630 #ifdef CONFIG_CHELSIO_T4_DCB
631 const struct fw_port_cmd *pcmd = (const void *)p->data;
632 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
633 unsigned int action =
634 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
636 if (cmd == FW_PORT_CMD &&
637 action == FW_PORT_ACTION_GET_PORT_INFO) {
638 int port = FW_PORT_CMD_PORTID_G(
639 be32_to_cpu(pcmd->op_to_portid));
640 struct net_device *dev = q->adap->port[port];
641 int state_input = ((pcmd->u.info.dcbxdis_pkd &
642 FW_PORT_CMD_DCBXDIS_F)
643 ? CXGB4_DCB_INPUT_FW_DISABLED
644 : CXGB4_DCB_INPUT_FW_ENABLED);
646 cxgb4_dcb_state_fsm(dev, state_input);
649 if (cmd == FW_PORT_CMD &&
650 action == FW_PORT_ACTION_L2_DCB_CFG)
651 dcb_rpl(q->adap, pcmd);
655 t4_handle_fw_rpl(q->adap, p->data);
656 } else if (opcode == CPL_L2T_WRITE_RPL) {
657 const struct cpl_l2t_write_rpl *p = (void *)rsp;
659 do_l2t_write_rpl(q->adap, p);
660 } else if (opcode == CPL_SET_TCB_RPL) {
661 const struct cpl_set_tcb_rpl *p = (void *)rsp;
663 filter_rpl(q->adap, p);
665 dev_err(q->adap->pdev_dev,
666 "unexpected CPL %#x on FW event queue\n", opcode);
672 * uldrx_handler - response queue handler for ULD queues
673 * @q: the response queue that received the packet
674 * @rsp: the response queue descriptor holding the offload message
675 * @gl: the gather list of packet fragments
677 * Deliver an ingress offload packet to a ULD. All processing is done by
678 * the ULD, we just maintain statistics.
680 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
681 const struct pkt_gl *gl)
683 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
685 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
687 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
688 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
691 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
697 else if (gl == CXGB4_MSG_AN)
704 static void disable_msi(struct adapter *adapter)
706 if (adapter->flags & USING_MSIX) {
707 pci_disable_msix(adapter->pdev);
708 adapter->flags &= ~USING_MSIX;
709 } else if (adapter->flags & USING_MSI) {
710 pci_disable_msi(adapter->pdev);
711 adapter->flags &= ~USING_MSI;
716 * Interrupt handler for non-data events used with MSI-X.
718 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
720 struct adapter *adap = cookie;
721 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
725 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
727 t4_slow_intr_handler(adap);
732 * Name the MSI-X interrupts.
734 static void name_msix_vecs(struct adapter *adap)
736 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
738 /* non-data interrupts */
739 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
742 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
743 adap->port[0]->name);
745 /* Ethernet queues */
746 for_each_port(adap, j) {
747 struct net_device *d = adap->port[j];
748 const struct port_info *pi = netdev_priv(d);
750 for (i = 0; i < pi->nqsets; i++, msi_idx++)
751 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
756 for_each_ofldrxq(&adap->sge, i)
757 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
758 adap->port[0]->name, i);
760 for_each_rdmarxq(&adap->sge, i)
761 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
762 adap->port[0]->name, i);
764 for_each_rdmaciq(&adap->sge, i)
765 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
766 adap->port[0]->name, i);
769 static int request_msix_queue_irqs(struct adapter *adap)
771 struct sge *s = &adap->sge;
772 int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
775 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
776 adap->msix_info[1].desc, &s->fw_evtq);
780 for_each_ethrxq(s, ethqidx) {
781 err = request_irq(adap->msix_info[msi_index].vec,
783 adap->msix_info[msi_index].desc,
784 &s->ethrxq[ethqidx].rspq);
789 for_each_ofldrxq(s, ofldqidx) {
790 err = request_irq(adap->msix_info[msi_index].vec,
792 adap->msix_info[msi_index].desc,
793 &s->ofldrxq[ofldqidx].rspq);
798 for_each_rdmarxq(s, rdmaqidx) {
799 err = request_irq(adap->msix_info[msi_index].vec,
801 adap->msix_info[msi_index].desc,
802 &s->rdmarxq[rdmaqidx].rspq);
807 for_each_rdmaciq(s, rdmaciqqidx) {
808 err = request_irq(adap->msix_info[msi_index].vec,
810 adap->msix_info[msi_index].desc,
811 &s->rdmaciq[rdmaciqqidx].rspq);
819 while (--rdmaciqqidx >= 0)
820 free_irq(adap->msix_info[--msi_index].vec,
821 &s->rdmaciq[rdmaciqqidx].rspq);
822 while (--rdmaqidx >= 0)
823 free_irq(adap->msix_info[--msi_index].vec,
824 &s->rdmarxq[rdmaqidx].rspq);
825 while (--ofldqidx >= 0)
826 free_irq(adap->msix_info[--msi_index].vec,
827 &s->ofldrxq[ofldqidx].rspq);
828 while (--ethqidx >= 0)
829 free_irq(adap->msix_info[--msi_index].vec,
830 &s->ethrxq[ethqidx].rspq);
831 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
835 static void free_msix_queue_irqs(struct adapter *adap)
837 int i, msi_index = 2;
838 struct sge *s = &adap->sge;
840 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
841 for_each_ethrxq(s, i)
842 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
843 for_each_ofldrxq(s, i)
844 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
845 for_each_rdmarxq(s, i)
846 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
847 for_each_rdmaciq(s, i)
848 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
852 * cxgb4_write_rss - write the RSS table for a given port
854 * @queues: array of queue indices for RSS
856 * Sets up the portion of the HW RSS table for the port's VI to distribute
857 * packets to the Rx queues in @queues.
859 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
863 const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
865 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
869 /* map the queue indices to queue ids */
870 for (i = 0; i < pi->rss_size; i++, queues++)
871 rss[i] = q[*queues].rspq.abs_id;
873 err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
874 pi->rss_size, rss, pi->rss_size);
880 * setup_rss - configure RSS
883 * Sets up RSS for each port.
885 static int setup_rss(struct adapter *adap)
889 for_each_port(adap, i) {
890 const struct port_info *pi = adap2pinfo(adap, i);
892 err = cxgb4_write_rss(pi, pi->rss);
900 * Return the channel of the ingress queue with the given qid.
902 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
904 qid -= p->ingr_start;
905 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
909 * Wait until all NAPI handlers are descheduled.
911 static void quiesce_rx(struct adapter *adap)
915 for (i = 0; i < adap->sge.ingr_sz; i++) {
916 struct sge_rspq *q = adap->sge.ingr_map[i];
918 if (q && q->handler) {
919 napi_disable(&q->napi);
921 while (!cxgb_poll_lock_napi(q))
929 /* Disable interrupt and napi handler */
930 static void disable_interrupts(struct adapter *adap)
932 if (adap->flags & FULL_INIT_DONE) {
933 t4_intr_disable(adap);
934 if (adap->flags & USING_MSIX) {
935 free_msix_queue_irqs(adap);
936 free_irq(adap->msix_info[0].vec, adap);
938 free_irq(adap->pdev->irq, adap);
945 * Enable NAPI scheduling and interrupt generation for all Rx queues.
947 static void enable_rx(struct adapter *adap)
951 for (i = 0; i < adap->sge.ingr_sz; i++) {
952 struct sge_rspq *q = adap->sge.ingr_map[i];
957 cxgb_busy_poll_init_lock(q);
958 napi_enable(&q->napi);
960 /* 0-increment GTS to start the timer and enable interrupts */
961 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
962 SEINTARM_V(q->intr_params) |
963 INGRESSQID_V(q->cntxt_id));
967 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
968 unsigned int nq, unsigned int per_chan, int msi_idx,
973 for (i = 0; i < nq; i++, q++) {
976 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
977 adap->port[i / per_chan],
978 msi_idx, q->fl.size ? &q->fl : NULL,
982 memset(&q->stats, 0, sizeof(q->stats));
984 ids[i] = q->rspq.abs_id;
990 * setup_sge_queues - configure SGE Tx/Rx/response queues
993 * Determines how many sets of SGE queues to use and initializes them.
994 * We support multiple queue sets per port if we have MSI-X, otherwise
995 * just one queue set per port.
997 static int setup_sge_queues(struct adapter *adap)
999 int err, msi_idx, i, j;
1000 struct sge *s = &adap->sge;
1002 bitmap_zero(s->starving_fl, s->egr_sz);
1003 bitmap_zero(s->txq_maperr, s->egr_sz);
1005 if (adap->flags & USING_MSIX)
1006 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1008 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1012 msi_idx = -((int)s->intrq.abs_id + 1);
1015 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1016 * don't forget to update the following which need to be
1017 * synchronized to and changes here.
1019 * 1. The calculations of MAX_INGQ in cxgb4.h.
1021 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1022 * to accommodate any new/deleted Ingress Queues
1023 * which need MSI-X Vectors.
1025 * 3. Update sge_qinfo_show() to include information on the
1026 * new/deleted queues.
1028 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1029 msi_idx, NULL, fwevtq_handler);
1031 freeout: t4_free_sge_resources(adap);
1035 for_each_port(adap, i) {
1036 struct net_device *dev = adap->port[i];
1037 struct port_info *pi = netdev_priv(dev);
1038 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1039 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1041 for (j = 0; j < pi->nqsets; j++, q++) {
1044 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1050 memset(&q->stats, 0, sizeof(q->stats));
1052 for (j = 0; j < pi->nqsets; j++, t++) {
1053 err = t4_sge_alloc_eth_txq(adap, t, dev,
1054 netdev_get_tx_queue(dev, j),
1055 s->fw_evtq.cntxt_id);
1061 j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1062 for_each_ofldrxq(s, i) {
1063 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1065 s->fw_evtq.cntxt_id);
1070 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1071 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1078 ALLOC_OFLD_RXQS(s->ofldrxq, s->ofldqsets, j, s->ofld_rxq);
1079 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
1080 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1081 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
1083 #undef ALLOC_OFLD_RXQS
1085 for_each_port(adap, i) {
1087 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1088 * have RDMA queues, and that's the right value.
1090 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1091 s->fw_evtq.cntxt_id,
1092 s->rdmarxq[i].rspq.cntxt_id);
1097 t4_write_reg(adap, is_t4(adap->params.chip) ?
1098 MPS_TRC_RSS_CONTROL_A :
1099 MPS_T5_TRC_RSS_CONTROL_A,
1100 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1101 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1106 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1107 * The allocated memory is cleared.
1109 void *t4_alloc_mem(size_t size)
1111 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1119 * Free memory allocated through alloc_mem().
1121 void t4_free_mem(void *addr)
1123 if (is_vmalloc_addr(addr))
1129 /* Send a Work Request to write the filter at a specified index. We construct
1130 * a Firmware Filter Work Request to have the work done and put the indicated
1131 * filter into "pending" mode which will prevent any further actions against
1132 * it till we get a reply from the firmware on the completion status of the
1135 static int set_filter_wr(struct adapter *adapter, int fidx)
1137 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1138 struct sk_buff *skb;
1139 struct fw_filter_wr *fwr;
1142 /* If the new filter requires loopback Destination MAC and/or VLAN
1143 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1146 if (f->fs.newdmac || f->fs.newvlan) {
1147 /* allocate L2T entry for new filter */
1148 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1151 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1152 f->fs.eport, f->fs.dmac)) {
1153 cxgb4_l2t_release(f->l2t);
1159 ftid = adapter->tids.ftid_base + fidx;
1161 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1162 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1163 memset(fwr, 0, sizeof(*fwr));
1165 /* It would be nice to put most of the following in t4_hw.c but most
1166 * of the work is translating the cxgbtool ch_filter_specification
1167 * into the Work Request and the definition of that structure is
1168 * currently in cxgbtool.h which isn't appropriate to pull into the
1169 * common code. We may eventually try to come up with a more neutral
1170 * filter specification structure but for now it's easiest to simply
1171 * put this fairly direct code in line ...
1173 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1174 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1176 htonl(FW_FILTER_WR_TID_V(ftid) |
1177 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1178 FW_FILTER_WR_NOREPLY_V(0) |
1179 FW_FILTER_WR_IQ_V(f->fs.iq));
1180 fwr->del_filter_to_l2tix =
1181 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1182 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1183 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1184 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1185 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1186 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1187 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1188 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1189 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1190 f->fs.newvlan == VLAN_REWRITE) |
1191 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1192 f->fs.newvlan == VLAN_REWRITE) |
1193 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1194 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1195 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1196 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1197 fwr->ethtype = htons(f->fs.val.ethtype);
1198 fwr->ethtypem = htons(f->fs.mask.ethtype);
1199 fwr->frag_to_ovlan_vldm =
1200 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1201 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1202 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1203 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1204 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1205 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1207 fwr->rx_chan_rx_rpl_iq =
1208 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1209 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1210 fwr->maci_to_matchtypem =
1211 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1212 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1213 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1214 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1215 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1216 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1217 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1218 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1219 fwr->ptcl = f->fs.val.proto;
1220 fwr->ptclm = f->fs.mask.proto;
1221 fwr->ttyp = f->fs.val.tos;
1222 fwr->ttypm = f->fs.mask.tos;
1223 fwr->ivlan = htons(f->fs.val.ivlan);
1224 fwr->ivlanm = htons(f->fs.mask.ivlan);
1225 fwr->ovlan = htons(f->fs.val.ovlan);
1226 fwr->ovlanm = htons(f->fs.mask.ovlan);
1227 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1228 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1229 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1230 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1231 fwr->lp = htons(f->fs.val.lport);
1232 fwr->lpm = htons(f->fs.mask.lport);
1233 fwr->fp = htons(f->fs.val.fport);
1234 fwr->fpm = htons(f->fs.mask.fport);
1236 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1238 /* Mark the filter as "pending" and ship off the Filter Work Request.
1239 * When we get the Work Request Reply we'll clear the pending status.
1242 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1243 t4_ofld_send(adapter, skb);
1247 /* Delete the filter at a specified index.
1249 static int del_filter_wr(struct adapter *adapter, int fidx)
1251 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1252 struct sk_buff *skb;
1253 struct fw_filter_wr *fwr;
1254 unsigned int len, ftid;
1257 ftid = adapter->tids.ftid_base + fidx;
1259 skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1260 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1261 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1263 /* Mark the filter as "pending" and ship off the Filter Work Request.
1264 * When we get the Work Request Reply we'll clear the pending status.
1267 t4_mgmt_tx(adapter, skb);
1271 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1272 void *accel_priv, select_queue_fallback_t fallback)
1276 #ifdef CONFIG_CHELSIO_T4_DCB
1277 /* If a Data Center Bridging has been successfully negotiated on this
1278 * link then we'll use the skb's priority to map it to a TX Queue.
1279 * The skb's priority is determined via the VLAN Tag Priority Code
1282 if (cxgb4_dcb_enabled(dev)) {
1286 err = vlan_get_tag(skb, &vlan_tci);
1287 if (unlikely(err)) {
1288 if (net_ratelimit())
1290 "TX Packet without VLAN Tag on DCB Link\n");
1293 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1294 #ifdef CONFIG_CHELSIO_T4_FCOE
1295 if (skb->protocol == htons(ETH_P_FCOE))
1296 txq = skb->priority & 0x7;
1297 #endif /* CONFIG_CHELSIO_T4_FCOE */
1301 #endif /* CONFIG_CHELSIO_T4_DCB */
1304 txq = (skb_rx_queue_recorded(skb)
1305 ? skb_get_rx_queue(skb)
1306 : smp_processor_id());
1308 while (unlikely(txq >= dev->real_num_tx_queues))
1309 txq -= dev->real_num_tx_queues;
1314 return fallback(dev, skb) % dev->real_num_tx_queues;
1317 static inline int is_offload(const struct adapter *adap)
1319 return adap->params.offload;
1322 static int closest_timer(const struct sge *s, int time)
1324 int i, delta, match = 0, min_delta = INT_MAX;
1326 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1327 delta = time - s->timer_val[i];
1330 if (delta < min_delta) {
1338 static int closest_thres(const struct sge *s, int thres)
1340 int i, delta, match = 0, min_delta = INT_MAX;
1342 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1343 delta = thres - s->counter_val[i];
1346 if (delta < min_delta) {
1355 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1357 * @us: the hold-off time in us, or 0 to disable timer
1358 * @cnt: the hold-off packet count, or 0 to disable counter
1360 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1361 * one of the two needs to be enabled for the queue to generate interrupts.
1363 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1364 unsigned int us, unsigned int cnt)
1366 struct adapter *adap = q->adap;
1368 if ((us | cnt) == 0)
1375 new_idx = closest_thres(&adap->sge, cnt);
1376 if (q->desc && q->pktcnt_idx != new_idx) {
1377 /* the queue has already been created, update it */
1378 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1379 FW_PARAMS_PARAM_X_V(
1380 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1381 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1382 err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
1387 q->pktcnt_idx = new_idx;
1390 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1391 q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
1395 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1397 const struct port_info *pi = netdev_priv(dev);
1398 netdev_features_t changed = dev->features ^ features;
1401 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1404 err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
1406 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1408 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1412 static int setup_debugfs(struct adapter *adap)
1414 if (IS_ERR_OR_NULL(adap->debugfs_root))
1417 #ifdef CONFIG_DEBUG_FS
1418 t4_setup_debugfs(adap);
1424 * upper-layer driver support
1428 * Allocate an active-open TID and set it to the supplied value.
1430 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1434 spin_lock_bh(&t->atid_lock);
1436 union aopen_entry *p = t->afree;
1438 atid = (p - t->atid_tab) + t->atid_base;
1443 spin_unlock_bh(&t->atid_lock);
1446 EXPORT_SYMBOL(cxgb4_alloc_atid);
1449 * Release an active-open TID.
1451 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1453 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1455 spin_lock_bh(&t->atid_lock);
1459 spin_unlock_bh(&t->atid_lock);
1461 EXPORT_SYMBOL(cxgb4_free_atid);
1464 * Allocate a server TID and set it to the supplied value.
1466 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1470 spin_lock_bh(&t->stid_lock);
1471 if (family == PF_INET) {
1472 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1473 if (stid < t->nstids)
1474 __set_bit(stid, t->stid_bmap);
1478 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
1483 t->stid_tab[stid].data = data;
1484 stid += t->stid_base;
1485 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1486 * This is equivalent to 4 TIDs. With CLIP enabled it
1489 if (family == PF_INET)
1492 t->stids_in_use += 4;
1494 spin_unlock_bh(&t->stid_lock);
1497 EXPORT_SYMBOL(cxgb4_alloc_stid);
1499 /* Allocate a server filter TID and set it to the supplied value.
1501 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1505 spin_lock_bh(&t->stid_lock);
1506 if (family == PF_INET) {
1507 stid = find_next_zero_bit(t->stid_bmap,
1508 t->nstids + t->nsftids, t->nstids);
1509 if (stid < (t->nstids + t->nsftids))
1510 __set_bit(stid, t->stid_bmap);
1517 t->stid_tab[stid].data = data;
1519 stid += t->sftid_base;
1522 spin_unlock_bh(&t->stid_lock);
1525 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1527 /* Release a server TID.
1529 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1531 /* Is it a server filter TID? */
1532 if (t->nsftids && (stid >= t->sftid_base)) {
1533 stid -= t->sftid_base;
1536 stid -= t->stid_base;
1539 spin_lock_bh(&t->stid_lock);
1540 if (family == PF_INET)
1541 __clear_bit(stid, t->stid_bmap);
1543 bitmap_release_region(t->stid_bmap, stid, 2);
1544 t->stid_tab[stid].data = NULL;
1545 if (family == PF_INET)
1548 t->stids_in_use -= 4;
1549 spin_unlock_bh(&t->stid_lock);
1551 EXPORT_SYMBOL(cxgb4_free_stid);
1554 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1556 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1559 struct cpl_tid_release *req;
1561 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1562 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1563 INIT_TP_WR(req, tid);
1564 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1568 * Queue a TID release request and if necessary schedule a work queue to
1571 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1574 void **p = &t->tid_tab[tid];
1575 struct adapter *adap = container_of(t, struct adapter, tids);
1577 spin_lock_bh(&adap->tid_release_lock);
1578 *p = adap->tid_release_head;
1579 /* Low 2 bits encode the Tx channel number */
1580 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1581 if (!adap->tid_release_task_busy) {
1582 adap->tid_release_task_busy = true;
1583 queue_work(adap->workq, &adap->tid_release_task);
1585 spin_unlock_bh(&adap->tid_release_lock);
1589 * Process the list of pending TID release requests.
1591 static void process_tid_release_list(struct work_struct *work)
1593 struct sk_buff *skb;
1594 struct adapter *adap;
1596 adap = container_of(work, struct adapter, tid_release_task);
1598 spin_lock_bh(&adap->tid_release_lock);
1599 while (adap->tid_release_head) {
1600 void **p = adap->tid_release_head;
1601 unsigned int chan = (uintptr_t)p & 3;
1602 p = (void *)p - chan;
1604 adap->tid_release_head = *p;
1606 spin_unlock_bh(&adap->tid_release_lock);
1608 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1610 schedule_timeout_uninterruptible(1);
1612 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1613 t4_ofld_send(adap, skb);
1614 spin_lock_bh(&adap->tid_release_lock);
1616 adap->tid_release_task_busy = false;
1617 spin_unlock_bh(&adap->tid_release_lock);
1621 * Release a TID and inform HW. If we are unable to allocate the release
1622 * message we defer to a work queue.
1624 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1627 struct sk_buff *skb;
1628 struct adapter *adap = container_of(t, struct adapter, tids);
1630 old = t->tid_tab[tid];
1631 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1633 t->tid_tab[tid] = NULL;
1634 mk_tid_release(skb, chan, tid);
1635 t4_ofld_send(adap, skb);
1637 cxgb4_queue_tid_release(t, chan, tid);
1639 atomic_dec(&t->tids_in_use);
1641 EXPORT_SYMBOL(cxgb4_remove_tid);
1644 * Allocate and initialize the TID tables. Returns 0 on success.
1646 static int tid_init(struct tid_info *t)
1649 unsigned int stid_bmap_size;
1650 unsigned int natids = t->natids;
1651 struct adapter *adap = container_of(t, struct adapter, tids);
1653 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1654 size = t->ntids * sizeof(*t->tid_tab) +
1655 natids * sizeof(*t->atid_tab) +
1656 t->nstids * sizeof(*t->stid_tab) +
1657 t->nsftids * sizeof(*t->stid_tab) +
1658 stid_bmap_size * sizeof(long) +
1659 t->nftids * sizeof(*t->ftid_tab) +
1660 t->nsftids * sizeof(*t->ftid_tab);
1662 t->tid_tab = t4_alloc_mem(size);
1666 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1667 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1668 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1669 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1670 spin_lock_init(&t->stid_lock);
1671 spin_lock_init(&t->atid_lock);
1673 t->stids_in_use = 0;
1675 t->atids_in_use = 0;
1676 atomic_set(&t->tids_in_use, 0);
1678 /* Setup the free list for atid_tab and clear the stid bitmap. */
1681 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1682 t->afree = t->atid_tab;
1684 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1685 /* Reserve stid 0 for T4/T5 adapters */
1686 if (!t->stid_base &&
1687 (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
1688 __set_bit(0, t->stid_bmap);
1694 * cxgb4_create_server - create an IP server
1696 * @stid: the server TID
1697 * @sip: local IP address to bind server to
1698 * @sport: the server's TCP port
1699 * @queue: queue to direct messages from this server to
1701 * Create an IP server for the given port and address.
1702 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1704 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1705 __be32 sip, __be16 sport, __be16 vlan,
1709 struct sk_buff *skb;
1710 struct adapter *adap;
1711 struct cpl_pass_open_req *req;
1714 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1718 adap = netdev2adap(dev);
1719 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1721 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1722 req->local_port = sport;
1723 req->peer_port = htons(0);
1724 req->local_ip = sip;
1725 req->peer_ip = htonl(0);
1726 chan = rxq_to_chan(&adap->sge, queue);
1727 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1728 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1729 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1730 ret = t4_mgmt_tx(adap, skb);
1731 return net_xmit_eval(ret);
1733 EXPORT_SYMBOL(cxgb4_create_server);
1735 /* cxgb4_create_server6 - create an IPv6 server
1737 * @stid: the server TID
1738 * @sip: local IPv6 address to bind server to
1739 * @sport: the server's TCP port
1740 * @queue: queue to direct messages from this server to
1742 * Create an IPv6 server for the given port and address.
1743 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1745 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1746 const struct in6_addr *sip, __be16 sport,
1750 struct sk_buff *skb;
1751 struct adapter *adap;
1752 struct cpl_pass_open_req6 *req;
1755 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1759 adap = netdev2adap(dev);
1760 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1762 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1763 req->local_port = sport;
1764 req->peer_port = htons(0);
1765 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1766 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1767 req->peer_ip_hi = cpu_to_be64(0);
1768 req->peer_ip_lo = cpu_to_be64(0);
1769 chan = rxq_to_chan(&adap->sge, queue);
1770 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1771 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1772 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1773 ret = t4_mgmt_tx(adap, skb);
1774 return net_xmit_eval(ret);
1776 EXPORT_SYMBOL(cxgb4_create_server6);
1778 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1779 unsigned int queue, bool ipv6)
1781 struct sk_buff *skb;
1782 struct adapter *adap;
1783 struct cpl_close_listsvr_req *req;
1786 adap = netdev2adap(dev);
1788 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1792 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1794 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1795 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1796 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1797 ret = t4_mgmt_tx(adap, skb);
1798 return net_xmit_eval(ret);
1800 EXPORT_SYMBOL(cxgb4_remove_server);
1803 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1804 * @mtus: the HW MTU table
1805 * @mtu: the target MTU
1806 * @idx: index of selected entry in the MTU table
1808 * Returns the index and the value in the HW MTU table that is closest to
1809 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1810 * table, in which case that smallest available value is selected.
1812 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1817 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1823 EXPORT_SYMBOL(cxgb4_best_mtu);
1826 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1827 * @mtus: the HW MTU table
1828 * @header_size: Header Size
1829 * @data_size_max: maximum Data Segment Size
1830 * @data_size_align: desired Data Segment Size Alignment (2^N)
1831 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1833 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1834 * MTU Table based solely on a Maximum MTU parameter, we break that
1835 * parameter up into a Header Size and Maximum Data Segment Size, and
1836 * provide a desired Data Segment Size Alignment. If we find an MTU in
1837 * the Hardware MTU Table which will result in a Data Segment Size with
1838 * the requested alignment _and_ that MTU isn't "too far" from the
1839 * closest MTU, then we'll return that rather than the closest MTU.
1841 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1842 unsigned short header_size,
1843 unsigned short data_size_max,
1844 unsigned short data_size_align,
1845 unsigned int *mtu_idxp)
1847 unsigned short max_mtu = header_size + data_size_max;
1848 unsigned short data_size_align_mask = data_size_align - 1;
1849 int mtu_idx, aligned_mtu_idx;
1851 /* Scan the MTU Table till we find an MTU which is larger than our
1852 * Maximum MTU or we reach the end of the table. Along the way,
1853 * record the last MTU found, if any, which will result in a Data
1854 * Segment Length matching the requested alignment.
1856 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1857 unsigned short data_size = mtus[mtu_idx] - header_size;
1859 /* If this MTU minus the Header Size would result in a
1860 * Data Segment Size of the desired alignment, remember it.
1862 if ((data_size & data_size_align_mask) == 0)
1863 aligned_mtu_idx = mtu_idx;
1865 /* If we're not at the end of the Hardware MTU Table and the
1866 * next element is larger than our Maximum MTU, drop out of
1869 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1873 /* If we fell out of the loop because we ran to the end of the table,
1874 * then we just have to use the last [largest] entry.
1876 if (mtu_idx == NMTUS)
1879 /* If we found an MTU which resulted in the requested Data Segment
1880 * Length alignment and that's "not far" from the largest MTU which is
1881 * less than or equal to the maximum MTU, then use that.
1883 if (aligned_mtu_idx >= 0 &&
1884 mtu_idx - aligned_mtu_idx <= 1)
1885 mtu_idx = aligned_mtu_idx;
1887 /* If the caller has passed in an MTU Index pointer, pass the
1888 * MTU Index back. Return the MTU value.
1891 *mtu_idxp = mtu_idx;
1892 return mtus[mtu_idx];
1894 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1897 * cxgb4_port_chan - get the HW channel of a port
1898 * @dev: the net device for the port
1900 * Return the HW Tx channel of the given port.
1902 unsigned int cxgb4_port_chan(const struct net_device *dev)
1904 return netdev2pinfo(dev)->tx_chan;
1906 EXPORT_SYMBOL(cxgb4_port_chan);
1908 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1910 struct adapter *adap = netdev2adap(dev);
1911 u32 v1, v2, lp_count, hp_count;
1913 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1914 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1915 if (is_t4(adap->params.chip)) {
1916 lp_count = LP_COUNT_G(v1);
1917 hp_count = HP_COUNT_G(v1);
1919 lp_count = LP_COUNT_T5_G(v1);
1920 hp_count = HP_COUNT_T5_G(v2);
1922 return lpfifo ? lp_count : hp_count;
1924 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1927 * cxgb4_port_viid - get the VI id of a port
1928 * @dev: the net device for the port
1930 * Return the VI id of the given port.
1932 unsigned int cxgb4_port_viid(const struct net_device *dev)
1934 return netdev2pinfo(dev)->viid;
1936 EXPORT_SYMBOL(cxgb4_port_viid);
1939 * cxgb4_port_idx - get the index of a port
1940 * @dev: the net device for the port
1942 * Return the index of the given port.
1944 unsigned int cxgb4_port_idx(const struct net_device *dev)
1946 return netdev2pinfo(dev)->port_id;
1948 EXPORT_SYMBOL(cxgb4_port_idx);
1950 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1951 struct tp_tcp_stats *v6)
1953 struct adapter *adap = pci_get_drvdata(pdev);
1955 spin_lock(&adap->stats_lock);
1956 t4_tp_get_tcp_stats(adap, v4, v6);
1957 spin_unlock(&adap->stats_lock);
1959 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1961 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1962 const unsigned int *pgsz_order)
1964 struct adapter *adap = netdev2adap(dev);
1966 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1967 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1968 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1969 HPZ3_V(pgsz_order[3]));
1971 EXPORT_SYMBOL(cxgb4_iscsi_init);
1973 int cxgb4_flush_eq_cache(struct net_device *dev)
1975 struct adapter *adap = netdev2adap(dev);
1978 ret = t4_fwaddrspace_write(adap, adap->mbox,
1979 0xe1000000 + SGE_CTXT_CMD_A, 0x20000000);
1982 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
1984 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
1986 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
1990 spin_lock(&adap->win0_lock);
1991 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
1992 sizeof(indices), (__be32 *)&indices,
1994 spin_unlock(&adap->win0_lock);
1996 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
1997 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2002 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2005 struct adapter *adap = netdev2adap(dev);
2006 u16 hw_pidx, hw_cidx;
2009 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2013 if (pidx != hw_pidx) {
2017 if (pidx >= hw_pidx)
2018 delta = pidx - hw_pidx;
2020 delta = size - hw_pidx + pidx;
2022 if (is_t4(adap->params.chip))
2023 val = PIDX_V(delta);
2025 val = PIDX_T5_V(delta);
2027 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2033 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2035 void cxgb4_disable_db_coalescing(struct net_device *dev)
2037 struct adapter *adap;
2039 adap = netdev2adap(dev);
2040 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F,
2043 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
2045 void cxgb4_enable_db_coalescing(struct net_device *dev)
2047 struct adapter *adap;
2049 adap = netdev2adap(dev);
2050 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, NOCOALESCE_F, 0);
2052 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
2054 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2056 struct adapter *adap;
2057 u32 offset, memtype, memaddr;
2058 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2059 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2062 adap = netdev2adap(dev);
2064 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2066 /* Figure out where the offset lands in the Memory Type/Address scheme.
2067 * This code assumes that the memory is laid out starting at offset 0
2068 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2069 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2070 * MC0, and some have both MC0 and MC1.
2072 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2073 edc0_size = EDRAM0_SIZE_G(size) << 20;
2074 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2075 edc1_size = EDRAM1_SIZE_G(size) << 20;
2076 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2077 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2079 edc0_end = edc0_size;
2080 edc1_end = edc0_end + edc1_size;
2081 mc0_end = edc1_end + mc0_size;
2083 if (offset < edc0_end) {
2086 } else if (offset < edc1_end) {
2088 memaddr = offset - edc0_end;
2090 if (offset < mc0_end) {
2092 memaddr = offset - edc1_end;
2093 } else if (is_t4(adap->params.chip)) {
2094 /* T4 only has a single memory channel */
2097 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2098 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2099 mc1_end = mc0_end + mc1_size;
2100 if (offset < mc1_end) {
2102 memaddr = offset - mc0_end;
2104 /* offset beyond the end of any memory */
2110 spin_lock(&adap->win0_lock);
2111 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2112 spin_unlock(&adap->win0_lock);
2116 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2120 EXPORT_SYMBOL(cxgb4_read_tpte);
2122 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2125 struct adapter *adap;
2127 adap = netdev2adap(dev);
2128 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2129 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2131 return ((u64)hi << 32) | (u64)lo;
2133 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2135 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2137 enum cxgb4_bar2_qtype qtype,
2139 unsigned int *pbar2_qid)
2141 return cxgb4_t4_bar2_sge_qregs(netdev2adap(dev),
2143 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2144 ? T4_BAR2_QTYPE_EGRESS
2145 : T4_BAR2_QTYPE_INGRESS),
2149 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2151 static struct pci_driver cxgb4_driver;
2153 static void check_neigh_update(struct neighbour *neigh)
2155 const struct device *parent;
2156 const struct net_device *netdev = neigh->dev;
2158 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2159 netdev = vlan_dev_real_dev(netdev);
2160 parent = netdev->dev.parent;
2161 if (parent && parent->driver == &cxgb4_driver.driver)
2162 t4_l2t_update(dev_get_drvdata(parent), neigh);
2165 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2169 case NETEVENT_NEIGH_UPDATE:
2170 check_neigh_update(data);
2172 case NETEVENT_REDIRECT:
2179 static bool netevent_registered;
2180 static struct notifier_block cxgb4_netevent_nb = {
2181 .notifier_call = netevent_cb
2184 static void drain_db_fifo(struct adapter *adap, int usecs)
2186 u32 v1, v2, lp_count, hp_count;
2189 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2190 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2191 if (is_t4(adap->params.chip)) {
2192 lp_count = LP_COUNT_G(v1);
2193 hp_count = HP_COUNT_G(v1);
2195 lp_count = LP_COUNT_T5_G(v1);
2196 hp_count = HP_COUNT_T5_G(v2);
2199 if (lp_count == 0 && hp_count == 0)
2201 set_current_state(TASK_UNINTERRUPTIBLE);
2202 schedule_timeout(usecs_to_jiffies(usecs));
2206 static void disable_txq_db(struct sge_txq *q)
2208 unsigned long flags;
2210 spin_lock_irqsave(&q->db_lock, flags);
2212 spin_unlock_irqrestore(&q->db_lock, flags);
2215 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2217 spin_lock_irq(&q->db_lock);
2218 if (q->db_pidx_inc) {
2219 /* Make sure that all writes to the TX descriptors
2220 * are committed before we tell HW about them.
2223 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2224 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2228 spin_unlock_irq(&q->db_lock);
2231 static void disable_dbs(struct adapter *adap)
2235 for_each_ethrxq(&adap->sge, i)
2236 disable_txq_db(&adap->sge.ethtxq[i].q);
2237 for_each_ofldrxq(&adap->sge, i)
2238 disable_txq_db(&adap->sge.ofldtxq[i].q);
2239 for_each_port(adap, i)
2240 disable_txq_db(&adap->sge.ctrlq[i].q);
2243 static void enable_dbs(struct adapter *adap)
2247 for_each_ethrxq(&adap->sge, i)
2248 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2249 for_each_ofldrxq(&adap->sge, i)
2250 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2251 for_each_port(adap, i)
2252 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2255 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2257 if (adap->uld_handle[CXGB4_ULD_RDMA])
2258 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2262 static void process_db_full(struct work_struct *work)
2264 struct adapter *adap;
2266 adap = container_of(work, struct adapter, db_full_task);
2268 drain_db_fifo(adap, dbfifo_drain_delay);
2270 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2271 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2272 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2273 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2276 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2278 u16 hw_pidx, hw_cidx;
2281 spin_lock_irq(&q->db_lock);
2282 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2285 if (q->db_pidx != hw_pidx) {
2289 if (q->db_pidx >= hw_pidx)
2290 delta = q->db_pidx - hw_pidx;
2292 delta = q->size - hw_pidx + q->db_pidx;
2294 if (is_t4(adap->params.chip))
2295 val = PIDX_V(delta);
2297 val = PIDX_T5_V(delta);
2299 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2300 QID_V(q->cntxt_id) | val);
2305 spin_unlock_irq(&q->db_lock);
2307 CH_WARN(adap, "DB drop recovery failed.\n");
2309 static void recover_all_queues(struct adapter *adap)
2313 for_each_ethrxq(&adap->sge, i)
2314 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2315 for_each_ofldrxq(&adap->sge, i)
2316 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2317 for_each_port(adap, i)
2318 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2321 static void process_db_drop(struct work_struct *work)
2323 struct adapter *adap;
2325 adap = container_of(work, struct adapter, db_drop_task);
2327 if (is_t4(adap->params.chip)) {
2328 drain_db_fifo(adap, dbfifo_drain_delay);
2329 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2330 drain_db_fifo(adap, dbfifo_drain_delay);
2331 recover_all_queues(adap);
2332 drain_db_fifo(adap, dbfifo_drain_delay);
2334 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2336 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2337 u16 qid = (dropped_db >> 15) & 0x1ffff;
2338 u16 pidx_inc = dropped_db & 0x1fff;
2340 unsigned int bar2_qid;
2343 ret = cxgb4_t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2344 &bar2_qoffset, &bar2_qid);
2346 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2347 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2349 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2350 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2352 /* Re-enable BAR2 WC */
2353 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2356 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2359 void t4_db_full(struct adapter *adap)
2361 if (is_t4(adap->params.chip)) {
2363 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2364 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2365 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2366 queue_work(adap->workq, &adap->db_full_task);
2370 void t4_db_dropped(struct adapter *adap)
2372 if (is_t4(adap->params.chip)) {
2374 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2376 queue_work(adap->workq, &adap->db_drop_task);
2379 static void uld_attach(struct adapter *adap, unsigned int uld)
2382 struct cxgb4_lld_info lli;
2385 lli.pdev = adap->pdev;
2387 lli.l2t = adap->l2t;
2388 lli.tids = &adap->tids;
2389 lli.ports = adap->port;
2390 lli.vr = &adap->vres;
2391 lli.mtus = adap->params.mtus;
2392 if (uld == CXGB4_ULD_RDMA) {
2393 lli.rxq_ids = adap->sge.rdma_rxq;
2394 lli.ciq_ids = adap->sge.rdma_ciq;
2395 lli.nrxq = adap->sge.rdmaqs;
2396 lli.nciq = adap->sge.rdmaciqs;
2397 } else if (uld == CXGB4_ULD_ISCSI) {
2398 lli.rxq_ids = adap->sge.ofld_rxq;
2399 lli.nrxq = adap->sge.ofldqsets;
2401 lli.ntxq = adap->sge.ofldqsets;
2402 lli.nchan = adap->params.nports;
2403 lli.nports = adap->params.nports;
2404 lli.wr_cred = adap->params.ofldq_wr_cred;
2405 lli.adapter_type = adap->params.chip;
2406 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2407 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2408 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2409 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2410 lli.filt_mode = adap->params.tp.vlan_pri_map;
2411 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2412 for (i = 0; i < NCHAN; i++)
2414 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2415 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2416 lli.fw_vers = adap->params.fw_vers;
2417 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2418 lli.sge_ingpadboundary = adap->sge.fl_align;
2419 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2420 lli.sge_pktshift = adap->sge.pktshift;
2421 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2422 lli.max_ordird_qp = adap->params.max_ordird_qp;
2423 lli.max_ird_adapter = adap->params.max_ird_adapter;
2424 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2426 handle = ulds[uld].add(&lli);
2427 if (IS_ERR(handle)) {
2428 dev_warn(adap->pdev_dev,
2429 "could not attach to the %s driver, error %ld\n",
2430 uld_str[uld], PTR_ERR(handle));
2434 adap->uld_handle[uld] = handle;
2436 if (!netevent_registered) {
2437 register_netevent_notifier(&cxgb4_netevent_nb);
2438 netevent_registered = true;
2441 if (adap->flags & FULL_INIT_DONE)
2442 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2445 static void attach_ulds(struct adapter *adap)
2449 spin_lock(&adap_rcu_lock);
2450 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2451 spin_unlock(&adap_rcu_lock);
2453 mutex_lock(&uld_mutex);
2454 list_add_tail(&adap->list_node, &adapter_list);
2455 for (i = 0; i < CXGB4_ULD_MAX; i++)
2457 uld_attach(adap, i);
2458 mutex_unlock(&uld_mutex);
2461 static void detach_ulds(struct adapter *adap)
2465 mutex_lock(&uld_mutex);
2466 list_del(&adap->list_node);
2467 for (i = 0; i < CXGB4_ULD_MAX; i++)
2468 if (adap->uld_handle[i]) {
2469 ulds[i].state_change(adap->uld_handle[i],
2470 CXGB4_STATE_DETACH);
2471 adap->uld_handle[i] = NULL;
2473 if (netevent_registered && list_empty(&adapter_list)) {
2474 unregister_netevent_notifier(&cxgb4_netevent_nb);
2475 netevent_registered = false;
2477 mutex_unlock(&uld_mutex);
2479 spin_lock(&adap_rcu_lock);
2480 list_del_rcu(&adap->rcu_node);
2481 spin_unlock(&adap_rcu_lock);
2484 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2488 mutex_lock(&uld_mutex);
2489 for (i = 0; i < CXGB4_ULD_MAX; i++)
2490 if (adap->uld_handle[i])
2491 ulds[i].state_change(adap->uld_handle[i], new_state);
2492 mutex_unlock(&uld_mutex);
2496 * cxgb4_register_uld - register an upper-layer driver
2497 * @type: the ULD type
2498 * @p: the ULD methods
2500 * Registers an upper-layer driver with this driver and notifies the ULD
2501 * about any presently available devices that support its type. Returns
2502 * %-EBUSY if a ULD of the same type is already registered.
2504 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2507 struct adapter *adap;
2509 if (type >= CXGB4_ULD_MAX)
2511 mutex_lock(&uld_mutex);
2512 if (ulds[type].add) {
2517 list_for_each_entry(adap, &adapter_list, list_node)
2518 uld_attach(adap, type);
2519 out: mutex_unlock(&uld_mutex);
2522 EXPORT_SYMBOL(cxgb4_register_uld);
2525 * cxgb4_unregister_uld - unregister an upper-layer driver
2526 * @type: the ULD type
2528 * Unregisters an existing upper-layer driver.
2530 int cxgb4_unregister_uld(enum cxgb4_uld type)
2532 struct adapter *adap;
2534 if (type >= CXGB4_ULD_MAX)
2536 mutex_lock(&uld_mutex);
2537 list_for_each_entry(adap, &adapter_list, list_node)
2538 adap->uld_handle[type] = NULL;
2539 ulds[type].add = NULL;
2540 mutex_unlock(&uld_mutex);
2543 EXPORT_SYMBOL(cxgb4_unregister_uld);
2545 #if IS_ENABLED(CONFIG_IPV6)
2546 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2547 unsigned long event, void *data)
2549 struct inet6_ifaddr *ifa = data;
2550 struct net_device *event_dev = ifa->idev->dev;
2551 const struct device *parent = NULL;
2552 #if IS_ENABLED(CONFIG_BONDING)
2553 struct adapter *adap;
2555 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2556 event_dev = vlan_dev_real_dev(event_dev);
2557 #if IS_ENABLED(CONFIG_BONDING)
2558 if (event_dev->flags & IFF_MASTER) {
2559 list_for_each_entry(adap, &adapter_list, list_node) {
2562 cxgb4_clip_get(adap->port[0],
2563 (const u32 *)ifa, 1);
2566 cxgb4_clip_release(adap->port[0],
2567 (const u32 *)ifa, 1);
2578 parent = event_dev->dev.parent;
2580 if (parent && parent->driver == &cxgb4_driver.driver) {
2583 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2586 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2595 static bool inet6addr_registered;
2596 static struct notifier_block cxgb4_inet6addr_notifier = {
2597 .notifier_call = cxgb4_inet6addr_handler
2600 static void update_clip(const struct adapter *adap)
2603 struct net_device *dev;
2608 for (i = 0; i < MAX_NPORTS; i++) {
2609 dev = adap->port[i];
2613 ret = cxgb4_update_root_dev_clip(dev);
2620 #endif /* IS_ENABLED(CONFIG_IPV6) */
2623 * cxgb_up - enable the adapter
2624 * @adap: adapter being enabled
2626 * Called when the first port is enabled, this function performs the
2627 * actions necessary to make an adapter operational, such as completing
2628 * the initialization of HW modules, and enabling interrupts.
2630 * Must be called with the rtnl lock held.
2632 static int cxgb_up(struct adapter *adap)
2636 err = setup_sge_queues(adap);
2639 err = setup_rss(adap);
2643 if (adap->flags & USING_MSIX) {
2644 name_msix_vecs(adap);
2645 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2646 adap->msix_info[0].desc, adap);
2650 err = request_msix_queue_irqs(adap);
2652 free_irq(adap->msix_info[0].vec, adap);
2656 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2657 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2658 adap->port[0]->name, adap);
2664 t4_intr_enable(adap);
2665 adap->flags |= FULL_INIT_DONE;
2666 notify_ulds(adap, CXGB4_STATE_UP);
2667 #if IS_ENABLED(CONFIG_IPV6)
2673 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2675 t4_free_sge_resources(adap);
2679 static void cxgb_down(struct adapter *adapter)
2681 cancel_work_sync(&adapter->tid_release_task);
2682 cancel_work_sync(&adapter->db_full_task);
2683 cancel_work_sync(&adapter->db_drop_task);
2684 adapter->tid_release_task_busy = false;
2685 adapter->tid_release_head = NULL;
2687 t4_sge_stop(adapter);
2688 t4_free_sge_resources(adapter);
2689 adapter->flags &= ~FULL_INIT_DONE;
2693 * net_device operations
2695 static int cxgb_open(struct net_device *dev)
2698 struct port_info *pi = netdev_priv(dev);
2699 struct adapter *adapter = pi->adapter;
2701 netif_carrier_off(dev);
2703 if (!(adapter->flags & FULL_INIT_DONE)) {
2704 err = cxgb_up(adapter);
2709 err = link_start(dev);
2711 netif_tx_start_all_queues(dev);
2715 static int cxgb_close(struct net_device *dev)
2717 struct port_info *pi = netdev_priv(dev);
2718 struct adapter *adapter = pi->adapter;
2720 netif_tx_stop_all_queues(dev);
2721 netif_carrier_off(dev);
2722 return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
2725 /* Return an error number if the indicated filter isn't writable ...
2727 static int writable_filter(struct filter_entry *f)
2737 /* Delete the filter at the specified index (if valid). The checks for all
2738 * the common problems with doing this like the filter being locked, currently
2739 * pending in another operation, etc.
2741 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2743 struct filter_entry *f;
2746 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2749 f = &adapter->tids.ftid_tab[fidx];
2750 ret = writable_filter(f);
2754 return del_filter_wr(adapter, fidx);
2759 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2760 __be32 sip, __be16 sport, __be16 vlan,
2761 unsigned int queue, unsigned char port, unsigned char mask)
2764 struct filter_entry *f;
2765 struct adapter *adap;
2769 adap = netdev2adap(dev);
2771 /* Adjust stid to correct filter index */
2772 stid -= adap->tids.sftid_base;
2773 stid += adap->tids.nftids;
2775 /* Check to make sure the filter requested is writable ...
2777 f = &adap->tids.ftid_tab[stid];
2778 ret = writable_filter(f);
2782 /* Clear out any old resources being used by the filter before
2783 * we start constructing the new filter.
2786 clear_filter(adap, f);
2788 /* Clear out filter specifications */
2789 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2790 f->fs.val.lport = cpu_to_be16(sport);
2791 f->fs.mask.lport = ~0;
2793 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2794 for (i = 0; i < 4; i++) {
2795 f->fs.val.lip[i] = val[i];
2796 f->fs.mask.lip[i] = ~0;
2798 if (adap->params.tp.vlan_pri_map & PORT_F) {
2799 f->fs.val.iport = port;
2800 f->fs.mask.iport = mask;
2804 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2805 f->fs.val.proto = IPPROTO_TCP;
2806 f->fs.mask.proto = ~0;
2811 /* Mark filter as locked */
2815 ret = set_filter_wr(adap, stid);
2817 clear_filter(adap, f);
2823 EXPORT_SYMBOL(cxgb4_create_server_filter);
2825 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2826 unsigned int queue, bool ipv6)
2829 struct filter_entry *f;
2830 struct adapter *adap;
2832 adap = netdev2adap(dev);
2834 /* Adjust stid to correct filter index */
2835 stid -= adap->tids.sftid_base;
2836 stid += adap->tids.nftids;
2838 f = &adap->tids.ftid_tab[stid];
2839 /* Unlock the filter */
2842 ret = delete_filter(adap, stid);
2848 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2850 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2851 struct rtnl_link_stats64 *ns)
2853 struct port_stats stats;
2854 struct port_info *p = netdev_priv(dev);
2855 struct adapter *adapter = p->adapter;
2857 /* Block retrieving statistics during EEH error
2858 * recovery. Otherwise, the recovery might fail
2859 * and the PCI device will be removed permanently
2861 spin_lock(&adapter->stats_lock);
2862 if (!netif_device_present(dev)) {
2863 spin_unlock(&adapter->stats_lock);
2866 t4_get_port_stats(adapter, p->tx_chan, &stats);
2867 spin_unlock(&adapter->stats_lock);
2869 ns->tx_bytes = stats.tx_octets;
2870 ns->tx_packets = stats.tx_frames;
2871 ns->rx_bytes = stats.rx_octets;
2872 ns->rx_packets = stats.rx_frames;
2873 ns->multicast = stats.rx_mcast_frames;
2875 /* detailed rx_errors */
2876 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2878 ns->rx_over_errors = 0;
2879 ns->rx_crc_errors = stats.rx_fcs_err;
2880 ns->rx_frame_errors = stats.rx_symbol_err;
2881 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2882 stats.rx_ovflow2 + stats.rx_ovflow3 +
2883 stats.rx_trunc0 + stats.rx_trunc1 +
2884 stats.rx_trunc2 + stats.rx_trunc3;
2885 ns->rx_missed_errors = 0;
2887 /* detailed tx_errors */
2888 ns->tx_aborted_errors = 0;
2889 ns->tx_carrier_errors = 0;
2890 ns->tx_fifo_errors = 0;
2891 ns->tx_heartbeat_errors = 0;
2892 ns->tx_window_errors = 0;
2894 ns->tx_errors = stats.tx_error_frames;
2895 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2896 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2900 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2903 int ret = 0, prtad, devad;
2904 struct port_info *pi = netdev_priv(dev);
2905 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2909 if (pi->mdio_addr < 0)
2911 data->phy_id = pi->mdio_addr;
2915 if (mdio_phy_id_is_c45(data->phy_id)) {
2916 prtad = mdio_phy_id_prtad(data->phy_id);
2917 devad = mdio_phy_id_devad(data->phy_id);
2918 } else if (data->phy_id < 32) {
2919 prtad = data->phy_id;
2921 data->reg_num &= 0x1f;
2925 mbox = pi->adapter->fn;
2926 if (cmd == SIOCGMIIREG)
2927 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2928 data->reg_num, &data->val_out);
2930 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2931 data->reg_num, data->val_in);
2939 static void cxgb_set_rxmode(struct net_device *dev)
2941 /* unfortunately we can't return errors to the stack */
2942 set_rxmode(dev, -1, false);
2945 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2948 struct port_info *pi = netdev_priv(dev);
2950 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2952 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
2959 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2962 struct sockaddr *addr = p;
2963 struct port_info *pi = netdev_priv(dev);
2965 if (!is_valid_ether_addr(addr->sa_data))
2966 return -EADDRNOTAVAIL;
2968 ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
2969 pi->xact_addr_filt, addr->sa_data, true, true);
2973 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2974 pi->xact_addr_filt = ret;
2978 #ifdef CONFIG_NET_POLL_CONTROLLER
2979 static void cxgb_netpoll(struct net_device *dev)
2981 struct port_info *pi = netdev_priv(dev);
2982 struct adapter *adap = pi->adapter;
2984 if (adap->flags & USING_MSIX) {
2986 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
2988 for (i = pi->nqsets; i; i--, rx++)
2989 t4_sge_intr_msix(0, &rx->rspq);
2991 t4_intr_handler(adap)(0, adap);
2995 static const struct net_device_ops cxgb4_netdev_ops = {
2996 .ndo_open = cxgb_open,
2997 .ndo_stop = cxgb_close,
2998 .ndo_start_xmit = t4_eth_xmit,
2999 .ndo_select_queue = cxgb_select_queue,
3000 .ndo_get_stats64 = cxgb_get_stats,
3001 .ndo_set_rx_mode = cxgb_set_rxmode,
3002 .ndo_set_mac_address = cxgb_set_mac_addr,
3003 .ndo_set_features = cxgb_set_features,
3004 .ndo_validate_addr = eth_validate_addr,
3005 .ndo_do_ioctl = cxgb_ioctl,
3006 .ndo_change_mtu = cxgb_change_mtu,
3007 #ifdef CONFIG_NET_POLL_CONTROLLER
3008 .ndo_poll_controller = cxgb_netpoll,
3010 #ifdef CONFIG_CHELSIO_T4_FCOE
3011 .ndo_fcoe_enable = cxgb_fcoe_enable,
3012 .ndo_fcoe_disable = cxgb_fcoe_disable,
3013 #endif /* CONFIG_CHELSIO_T4_FCOE */
3014 #ifdef CONFIG_NET_RX_BUSY_POLL
3015 .ndo_busy_poll = cxgb_busy_poll,
3020 void t4_fatal_err(struct adapter *adap)
3022 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3023 t4_intr_disable(adap);
3024 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3027 /* Return the specified PCI-E Configuration Space register from our Physical
3028 * Function. We try first via a Firmware LDST Command since we prefer to let
3029 * the firmware own all of these registers, but if that fails we go for it
3030 * directly ourselves.
3032 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
3034 struct fw_ldst_cmd ldst_cmd;
3038 /* Construct and send the Firmware LDST Command to retrieve the
3039 * specified PCI-E Configuration Space register.
3041 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
3042 ldst_cmd.op_to_addrspace =
3043 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
3046 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE));
3047 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
3048 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
3049 ldst_cmd.u.pcie.ctrl_to_fn =
3050 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->fn));
3051 ldst_cmd.u.pcie.r = reg;
3052 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
3055 /* If the LDST Command suucceeded, exctract the returned register
3056 * value. Otherwise read it directly ourself.
3059 val = ntohl(ldst_cmd.u.pcie.data[0]);
3061 t4_hw_pci_read_cfg4(adap, reg, &val);
3066 static void setup_memwin(struct adapter *adap)
3068 u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
3070 if (is_t4(adap->params.chip)) {
3073 /* Truncation intentional: we only read the bottom 32-bits of
3074 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
3075 * mechanism to read BAR0 instead of using
3076 * pci_resource_start() because we could be operating from
3077 * within a Virtual Machine which is trapping our accesses to
3078 * our Configuration Space and we need to set up the PCI-E
3079 * Memory Window decoders with the actual addresses which will
3080 * be coming across the PCI-E link.
3082 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
3083 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
3084 adap->t4_bar0 = bar0;
3086 mem_win0_base = bar0 + MEMWIN0_BASE;
3087 mem_win1_base = bar0 + MEMWIN1_BASE;
3088 mem_win2_base = bar0 + MEMWIN2_BASE;
3089 mem_win2_aperture = MEMWIN2_APERTURE;
3091 /* For T5, only relative offset inside the PCIe BAR is passed */
3092 mem_win0_base = MEMWIN0_BASE;
3093 mem_win1_base = MEMWIN1_BASE;
3094 mem_win2_base = MEMWIN2_BASE_T5;
3095 mem_win2_aperture = MEMWIN2_APERTURE_T5;
3097 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 0),
3098 mem_win0_base | BIR_V(0) |
3099 WINDOW_V(ilog2(MEMWIN0_APERTURE) - 10));
3100 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 1),
3101 mem_win1_base | BIR_V(0) |
3102 WINDOW_V(ilog2(MEMWIN1_APERTURE) - 10));
3103 t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2),
3104 mem_win2_base | BIR_V(0) |
3105 WINDOW_V(ilog2(mem_win2_aperture) - 10));
3106 t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 2));
3109 static void setup_memwin_rdma(struct adapter *adap)
3111 if (adap->vres.ocq.size) {
3115 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3116 start &= PCI_BASE_ADDRESS_MEM_MASK;
3117 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3118 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3120 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3121 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3123 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3124 adap->vres.ocq.start);
3126 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3130 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3135 /* get device capabilities */
3136 memset(c, 0, sizeof(*c));
3137 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3138 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3139 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3140 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
3144 /* select capabilities we'll be using */
3145 if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
3147 c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
3149 c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
3150 } else if (vf_acls) {
3151 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
3154 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3155 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3156 ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
3160 ret = t4_config_glbl_rss(adap, adap->fn,
3161 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3162 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3163 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3167 ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, adap->sge.egr_sz, 64,
3168 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3175 /* tweak some settings */
3176 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3177 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3178 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3179 v = t4_read_reg(adap, TP_PIO_DATA_A);
3180 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3182 /* first 4 Tx modulation queues point to consecutive Tx channels */
3183 adap->params.tp.tx_modq_map = 0xE4;
3184 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3185 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3187 /* associate each Tx modulation queue with consecutive Tx channels */
3189 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3190 &v, 1, TP_TX_SCHED_HDR_A);
3191 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3192 &v, 1, TP_TX_SCHED_FIFO_A);
3193 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3194 &v, 1, TP_TX_SCHED_PCMD_A);
3196 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3197 if (is_offload(adap)) {
3198 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3199 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3200 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3201 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3202 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3203 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3204 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3205 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3206 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3207 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3210 /* get basic stuff going */
3211 return t4_early_init(adap, adap->fn);
3215 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3217 #define MAX_ATIDS 8192U
3220 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3222 * If the firmware we're dealing with has Configuration File support, then
3223 * we use that to perform all configuration
3227 * Tweak configuration based on module parameters, etc. Most of these have
3228 * defaults assigned to them by Firmware Configuration Files (if we're using
3229 * them) but need to be explicitly set if we're using hard-coded
3230 * initialization. But even in the case of using Firmware Configuration
3231 * Files, we'd like to expose the ability to change these via module
3232 * parameters so these are essentially common tweaks/settings for
3233 * Configuration Files and hard-coded initialization ...
3235 static int adap_init0_tweaks(struct adapter *adapter)
3238 * Fix up various Host-Dependent Parameters like Page Size, Cache
3239 * Line Size, etc. The firmware default is for a 4KB Page Size and
3240 * 64B Cache Line Size ...
3242 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3245 * Process module parameters which affect early initialization.
3247 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3248 dev_err(&adapter->pdev->dev,
3249 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3253 t4_set_reg_field(adapter, SGE_CONTROL_A,
3254 PKTSHIFT_V(PKTSHIFT_M),
3255 PKTSHIFT_V(rx_dma_offset));
3258 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3259 * adds the pseudo header itself.
3261 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3262 CSUM_HAS_PSEUDO_HDR_F, 0);
3268 * Attempt to initialize the adapter via a Firmware Configuration File.
3270 static int adap_init0_config(struct adapter *adapter, int reset)
3272 struct fw_caps_config_cmd caps_cmd;
3273 const struct firmware *cf;
3274 unsigned long mtype = 0, maddr = 0;
3275 u32 finiver, finicsum, cfcsum;
3277 int config_issued = 0;
3278 char *fw_config_file, fw_config_file_path[256];
3279 char *config_name = NULL;
3282 * Reset device if necessary.
3285 ret = t4_fw_reset(adapter, adapter->mbox,
3286 PIORSTMODE_F | PIORST_F);
3292 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3293 * then use that. Otherwise, use the configuration file stored
3294 * in the adapter flash ...
3296 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3298 fw_config_file = FW4_CFNAME;
3301 fw_config_file = FW5_CFNAME;
3304 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3305 adapter->pdev->device);
3310 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3312 config_name = "On FLASH";
3313 mtype = FW_MEMTYPE_CF_FLASH;
3314 maddr = t4_flash_cfg_addr(adapter);
3316 u32 params[7], val[7];
3318 sprintf(fw_config_file_path,
3319 "/lib/firmware/%s", fw_config_file);
3320 config_name = fw_config_file_path;
3322 if (cf->size >= FLASH_CFG_MAX_SIZE)
3325 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3326 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3327 ret = t4_query_params(adapter, adapter->mbox,
3328 adapter->fn, 0, 1, params, val);
3331 * For t4_memory_rw() below addresses and
3332 * sizes have to be in terms of multiples of 4
3333 * bytes. So, if the Configuration File isn't
3334 * a multiple of 4 bytes in length we'll have
3335 * to write that out separately since we can't
3336 * guarantee that the bytes following the
3337 * residual byte in the buffer returned by
3338 * request_firmware() are zeroed out ...
3340 size_t resid = cf->size & 0x3;
3341 size_t size = cf->size & ~0x3;
3342 __be32 *data = (__be32 *)cf->data;
3344 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3345 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3347 spin_lock(&adapter->win0_lock);
3348 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3349 size, data, T4_MEMORY_WRITE);
3350 if (ret == 0 && resid != 0) {
3357 last.word = data[size >> 2];
3358 for (i = resid; i < 4; i++)
3360 ret = t4_memory_rw(adapter, 0, mtype,
3365 spin_unlock(&adapter->win0_lock);
3369 release_firmware(cf);
3375 * Issue a Capability Configuration command to the firmware to get it
3376 * to parse the Configuration File. We don't use t4_fw_config_file()
3377 * because we want the ability to modify various features after we've
3378 * processed the configuration file ...
3380 memset(&caps_cmd, 0, sizeof(caps_cmd));
3381 caps_cmd.op_to_write =
3382 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3385 caps_cmd.cfvalid_to_len16 =
3386 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3387 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3388 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3389 FW_LEN16(caps_cmd));
3390 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3393 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3394 * Configuration File in FLASH), our last gasp effort is to use the
3395 * Firmware Configuration File which is embedded in the firmware. A
3396 * very few early versions of the firmware didn't have one embedded
3397 * but we can ignore those.
3399 if (ret == -ENOENT) {
3400 memset(&caps_cmd, 0, sizeof(caps_cmd));
3401 caps_cmd.op_to_write =
3402 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3405 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3406 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3407 sizeof(caps_cmd), &caps_cmd);
3408 config_name = "Firmware Default";
3415 finiver = ntohl(caps_cmd.finiver);
3416 finicsum = ntohl(caps_cmd.finicsum);
3417 cfcsum = ntohl(caps_cmd.cfcsum);
3418 if (finicsum != cfcsum)
3419 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3420 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3424 * And now tell the firmware to use the configuration we just loaded.
3426 caps_cmd.op_to_write =
3427 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3430 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3431 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3437 * Tweak configuration based on system architecture, module
3440 ret = adap_init0_tweaks(adapter);
3445 * And finally tell the firmware to initialize itself using the
3446 * parameters from the Configuration File.
3448 ret = t4_fw_initialize(adapter, adapter->mbox);
3452 /* Emit Firmware Configuration File information and return
3455 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3456 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3457 config_name, finiver, cfcsum);
3461 * Something bad happened. Return the error ... (If the "error"
3462 * is that there's no Configuration File on the adapter we don't
3463 * want to issue a warning since this is fairly common.)
3466 if (config_issued && ret != -ENOENT)
3467 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3472 static struct fw_info fw_info_array[] = {
3475 .fs_name = FW4_CFNAME,
3476 .fw_mod_name = FW4_FNAME,
3478 .chip = FW_HDR_CHIP_T4,
3479 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3480 .intfver_nic = FW_INTFVER(T4, NIC),
3481 .intfver_vnic = FW_INTFVER(T4, VNIC),
3482 .intfver_ri = FW_INTFVER(T4, RI),
3483 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3484 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3488 .fs_name = FW5_CFNAME,
3489 .fw_mod_name = FW5_FNAME,
3491 .chip = FW_HDR_CHIP_T5,
3492 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3493 .intfver_nic = FW_INTFVER(T5, NIC),
3494 .intfver_vnic = FW_INTFVER(T5, VNIC),
3495 .intfver_ri = FW_INTFVER(T5, RI),
3496 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3497 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3502 static struct fw_info *find_fw_info(int chip)
3506 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3507 if (fw_info_array[i].chip == chip)
3508 return &fw_info_array[i];
3514 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3516 static int adap_init0(struct adapter *adap)
3520 enum dev_state state;
3521 u32 params[7], val[7];
3522 struct fw_caps_config_cmd caps_cmd;
3525 /* Grab Firmware Device Log parameters as early as possible so we have
3526 * access to it for debugging, etc.
3528 ret = t4_init_devlog_params(adap);
3532 /* Contact FW, advertising Master capability */
3533 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3535 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3539 if (ret == adap->mbox)
3540 adap->flags |= MASTER_PF;
3543 * If we're the Master PF Driver and the device is uninitialized,
3544 * then let's consider upgrading the firmware ... (We always want
3545 * to check the firmware version number in order to A. get it for
3546 * later reporting and B. to warn if the currently loaded firmware
3547 * is excessively mismatched relative to the driver.)
3549 t4_get_fw_version(adap, &adap->params.fw_vers);
3550 t4_get_tp_version(adap, &adap->params.tp_vers);
3551 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3552 struct fw_info *fw_info;
3553 struct fw_hdr *card_fw;
3554 const struct firmware *fw;
3555 const u8 *fw_data = NULL;
3556 unsigned int fw_size = 0;
3558 /* This is the firmware whose headers the driver was compiled
3561 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3562 if (fw_info == NULL) {
3563 dev_err(adap->pdev_dev,
3564 "unable to get firmware info for chip %d.\n",
3565 CHELSIO_CHIP_VERSION(adap->params.chip));
3569 /* allocate memory to read the header of the firmware on the
3572 card_fw = t4_alloc_mem(sizeof(*card_fw));
3574 /* Get FW from from /lib/firmware/ */
3575 ret = request_firmware(&fw, fw_info->fw_mod_name,
3578 dev_err(adap->pdev_dev,
3579 "unable to load firmware image %s, error %d\n",
3580 fw_info->fw_mod_name, ret);
3586 /* upgrade FW logic */
3587 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3591 release_firmware(fw);
3592 t4_free_mem(card_fw);
3599 * Grab VPD parameters. This should be done after we establish a
3600 * connection to the firmware since some of the VPD parameters
3601 * (notably the Core Clock frequency) are retrieved via requests to
3602 * the firmware. On the other hand, we need these fairly early on
3603 * so we do this right after getting ahold of the firmware.
3605 ret = get_vpd_params(adap, &adap->params.vpd);
3610 * Find out what ports are available to us. Note that we need to do
3611 * this before calling adap_init0_no_config() since it needs nports
3615 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3616 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3617 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
3621 adap->params.nports = hweight32(port_vec);
3622 adap->params.portvec = port_vec;
3624 /* If the firmware is initialized already, emit a simply note to that
3625 * effect. Otherwise, it's time to try initializing the adapter.
3627 if (state == DEV_STATE_INIT) {
3628 dev_info(adap->pdev_dev, "Coming up as %s: "\
3629 "Adapter already initialized\n",
3630 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3632 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3633 "Initializing adapter\n");
3635 /* Find out whether we're dealing with a version of the
3636 * firmware which has configuration file support.
3638 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3639 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3640 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
3643 /* If the firmware doesn't support Configuration Files,
3647 dev_err(adap->pdev_dev, "firmware doesn't support "
3648 "Firmware Configuration Files\n");
3652 /* The firmware provides us with a memory buffer where we can
3653 * load a Configuration File from the host if we want to
3654 * override the Configuration File in flash.
3656 ret = adap_init0_config(adap, reset);
3657 if (ret == -ENOENT) {
3658 dev_err(adap->pdev_dev, "no Configuration File "
3659 "present on adapter.\n");
3663 dev_err(adap->pdev_dev, "could not initialize "
3664 "adapter, error %d\n", -ret);
3669 /* Give the SGE code a chance to pull in anything that it needs ...
3670 * Note that this must be called after we retrieve our VPD parameters
3671 * in order to know how to convert core ticks to seconds, etc.
3673 ret = t4_sge_init(adap);
3677 if (is_bypass_device(adap->pdev->device))
3678 adap->params.bypass = 1;
3681 * Grab some of our basic fundamental operating parameters.
3683 #define FW_PARAM_DEV(param) \
3684 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3685 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3687 #define FW_PARAM_PFVF(param) \
3688 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3689 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3690 FW_PARAMS_PARAM_Y_V(0) | \
3691 FW_PARAMS_PARAM_Z_V(0)
3693 params[0] = FW_PARAM_PFVF(EQ_START);
3694 params[1] = FW_PARAM_PFVF(L2T_START);
3695 params[2] = FW_PARAM_PFVF(L2T_END);
3696 params[3] = FW_PARAM_PFVF(FILTER_START);
3697 params[4] = FW_PARAM_PFVF(FILTER_END);
3698 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3699 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
3702 adap->sge.egr_start = val[0];
3703 adap->l2t_start = val[1];
3704 adap->l2t_end = val[2];
3705 adap->tids.ftid_base = val[3];
3706 adap->tids.nftids = val[4] - val[3] + 1;
3707 adap->sge.ingr_start = val[5];
3709 /* qids (ingress/egress) returned from firmware can be anywhere
3710 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3711 * Hence driver needs to allocate memory for this range to
3712 * store the queue info. Get the highest IQFLINT/EQ index returned
3713 * in FW_EQ_*_CMD.alloc command.
3715 params[0] = FW_PARAM_PFVF(EQ_END);
3716 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3717 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3720 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3721 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3723 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3724 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3725 if (!adap->sge.egr_map) {
3730 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3731 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3732 if (!adap->sge.ingr_map) {
3737 /* Allocate the memory for the vaious egress queue bitmaps
3738 * ie starving_fl and txq_maperr.
3740 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3741 sizeof(long), GFP_KERNEL);
3742 if (!adap->sge.starving_fl) {
3747 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3748 sizeof(long), GFP_KERNEL);
3749 if (!adap->sge.txq_maperr) {
3754 params[0] = FW_PARAM_PFVF(CLIP_START);
3755 params[1] = FW_PARAM_PFVF(CLIP_END);
3756 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3759 adap->clipt_start = val[0];
3760 adap->clipt_end = val[1];
3762 /* query params related to active filter region */
3763 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3764 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3765 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
3766 /* If Active filter size is set we enable establishing
3767 * offload connection through firmware work request
3769 if ((val[0] != val[1]) && (ret >= 0)) {
3770 adap->flags |= FW_OFLD_CONN;
3771 adap->tids.aftid_base = val[0];
3772 adap->tids.aftid_end = val[1];
3775 /* If we're running on newer firmware, let it know that we're
3776 * prepared to deal with encapsulated CPL messages. Older
3777 * firmware won't understand this and we'll just get
3778 * unencapsulated messages ...
3780 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3782 (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
3785 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3786 * capability. Earlier versions of the firmware didn't have the
3787 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3788 * permission to use ULPTX MEMWRITE DSGL.
3790 if (is_t4(adap->params.chip)) {
3791 adap->params.ulptx_memwrite_dsgl = false;
3793 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3794 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
3796 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3800 * Get device capabilities so we can determine what resources we need
3803 memset(&caps_cmd, 0, sizeof(caps_cmd));
3804 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3805 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3806 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3807 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3812 if (caps_cmd.ofldcaps) {
3813 /* query offload-related parameters */
3814 params[0] = FW_PARAM_DEV(NTID);
3815 params[1] = FW_PARAM_PFVF(SERVER_START);
3816 params[2] = FW_PARAM_PFVF(SERVER_END);
3817 params[3] = FW_PARAM_PFVF(TDDP_START);
3818 params[4] = FW_PARAM_PFVF(TDDP_END);
3819 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3820 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3824 adap->tids.ntids = val[0];
3825 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3826 adap->tids.stid_base = val[1];
3827 adap->tids.nstids = val[2] - val[1] + 1;
3829 * Setup server filter region. Divide the available filter
3830 * region into two parts. Regular filters get 1/3rd and server
3831 * filters get 2/3rd part. This is only enabled if workarond
3833 * 1. For regular filters.
3834 * 2. Server filter: This are special filters which are used
3835 * to redirect SYN packets to offload queue.
3837 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3838 adap->tids.sftid_base = adap->tids.ftid_base +
3839 DIV_ROUND_UP(adap->tids.nftids, 3);
3840 adap->tids.nsftids = adap->tids.nftids -
3841 DIV_ROUND_UP(adap->tids.nftids, 3);
3842 adap->tids.nftids = adap->tids.sftid_base -
3843 adap->tids.ftid_base;
3845 adap->vres.ddp.start = val[3];
3846 adap->vres.ddp.size = val[4] - val[3] + 1;
3847 adap->params.ofldq_wr_cred = val[5];
3849 adap->params.offload = 1;
3851 if (caps_cmd.rdmacaps) {
3852 params[0] = FW_PARAM_PFVF(STAG_START);
3853 params[1] = FW_PARAM_PFVF(STAG_END);
3854 params[2] = FW_PARAM_PFVF(RQ_START);
3855 params[3] = FW_PARAM_PFVF(RQ_END);
3856 params[4] = FW_PARAM_PFVF(PBL_START);
3857 params[5] = FW_PARAM_PFVF(PBL_END);
3858 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
3862 adap->vres.stag.start = val[0];
3863 adap->vres.stag.size = val[1] - val[0] + 1;
3864 adap->vres.rq.start = val[2];
3865 adap->vres.rq.size = val[3] - val[2] + 1;
3866 adap->vres.pbl.start = val[4];
3867 adap->vres.pbl.size = val[5] - val[4] + 1;
3869 params[0] = FW_PARAM_PFVF(SQRQ_START);
3870 params[1] = FW_PARAM_PFVF(SQRQ_END);
3871 params[2] = FW_PARAM_PFVF(CQ_START);
3872 params[3] = FW_PARAM_PFVF(CQ_END);
3873 params[4] = FW_PARAM_PFVF(OCQ_START);
3874 params[5] = FW_PARAM_PFVF(OCQ_END);
3875 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params,
3879 adap->vres.qp.start = val[0];
3880 adap->vres.qp.size = val[1] - val[0] + 1;
3881 adap->vres.cq.start = val[2];
3882 adap->vres.cq.size = val[3] - val[2] + 1;
3883 adap->vres.ocq.start = val[4];
3884 adap->vres.ocq.size = val[5] - val[4] + 1;
3886 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
3887 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3888 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params,
3891 adap->params.max_ordird_qp = 8;
3892 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
3895 adap->params.max_ordird_qp = val[0];
3896 adap->params.max_ird_adapter = val[1];
3898 dev_info(adap->pdev_dev,
3899 "max_ordird_qp %d max_ird_adapter %d\n",
3900 adap->params.max_ordird_qp,
3901 adap->params.max_ird_adapter);
3903 if (caps_cmd.iscsicaps) {
3904 params[0] = FW_PARAM_PFVF(ISCSI_START);
3905 params[1] = FW_PARAM_PFVF(ISCSI_END);
3906 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
3910 adap->vres.iscsi.start = val[0];
3911 adap->vres.iscsi.size = val[1] - val[0] + 1;
3913 #undef FW_PARAM_PFVF
3916 /* The MTU/MSS Table is initialized by now, so load their values. If
3917 * we're initializing the adapter, then we'll make any modifications
3918 * we want to the MTU/MSS Table and also initialize the congestion
3921 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
3922 if (state != DEV_STATE_INIT) {
3925 /* The default MTU Table contains values 1492 and 1500.
3926 * However, for TCP, it's better to have two values which are
3927 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
3928 * This allows us to have a TCP Data Payload which is a
3929 * multiple of 8 regardless of what combination of TCP Options
3930 * are in use (always a multiple of 4 bytes) which is
3931 * important for performance reasons. For instance, if no
3932 * options are in use, then we have a 20-byte IP header and a
3933 * 20-byte TCP header. In this case, a 1500-byte MSS would
3934 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
3935 * which is not a multiple of 8. So using an MSS of 1488 in
3936 * this case results in a TCP Data Payload of 1448 bytes which
3937 * is a multiple of 8. On the other hand, if 12-byte TCP Time
3938 * Stamps have been negotiated, then an MTU of 1500 bytes
3939 * results in a TCP Data Payload of 1448 bytes which, as
3940 * above, is a multiple of 8 bytes ...
3942 for (i = 0; i < NMTUS; i++)
3943 if (adap->params.mtus[i] == 1492) {
3944 adap->params.mtus[i] = 1488;
3948 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
3949 adap->params.b_wnd);
3951 t4_init_sge_params(adap);
3952 t4_init_tp_params(adap);
3953 adap->flags |= FW_OK;
3957 * Something bad happened. If a command timed out or failed with EIO
3958 * FW does not operate within its spec or something catastrophic
3959 * happened to HW/FW, stop issuing commands.
3962 kfree(adap->sge.egr_map);
3963 kfree(adap->sge.ingr_map);
3964 kfree(adap->sge.starving_fl);
3965 kfree(adap->sge.txq_maperr);
3966 if (ret != -ETIMEDOUT && ret != -EIO)
3967 t4_fw_bye(adap, adap->mbox);
3973 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
3974 pci_channel_state_t state)
3977 struct adapter *adap = pci_get_drvdata(pdev);
3983 adap->flags &= ~FW_OK;
3984 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
3985 spin_lock(&adap->stats_lock);
3986 for_each_port(adap, i) {
3987 struct net_device *dev = adap->port[i];
3989 netif_device_detach(dev);
3990 netif_carrier_off(dev);
3992 spin_unlock(&adap->stats_lock);
3993 disable_interrupts(adap);
3994 if (adap->flags & FULL_INIT_DONE)
3997 if ((adap->flags & DEV_ENABLED)) {
3998 pci_disable_device(pdev);
3999 adap->flags &= ~DEV_ENABLED;
4001 out: return state == pci_channel_io_perm_failure ?
4002 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4005 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4008 struct fw_caps_config_cmd c;
4009 struct adapter *adap = pci_get_drvdata(pdev);
4012 pci_restore_state(pdev);
4013 pci_save_state(pdev);
4014 return PCI_ERS_RESULT_RECOVERED;
4017 if (!(adap->flags & DEV_ENABLED)) {
4018 if (pci_enable_device(pdev)) {
4019 dev_err(&pdev->dev, "Cannot reenable PCI "
4020 "device after reset\n");
4021 return PCI_ERS_RESULT_DISCONNECT;
4023 adap->flags |= DEV_ENABLED;
4026 pci_set_master(pdev);
4027 pci_restore_state(pdev);
4028 pci_save_state(pdev);
4029 pci_cleanup_aer_uncorrect_error_status(pdev);
4031 if (t4_wait_dev_ready(adap->regs) < 0)
4032 return PCI_ERS_RESULT_DISCONNECT;
4033 if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
4034 return PCI_ERS_RESULT_DISCONNECT;
4035 adap->flags |= FW_OK;
4036 if (adap_init1(adap, &c))
4037 return PCI_ERS_RESULT_DISCONNECT;
4039 for_each_port(adap, i) {
4040 struct port_info *p = adap2pinfo(adap, i);
4042 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
4045 return PCI_ERS_RESULT_DISCONNECT;
4047 p->xact_addr_filt = -1;
4050 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4051 adap->params.b_wnd);
4054 return PCI_ERS_RESULT_DISCONNECT;
4055 return PCI_ERS_RESULT_RECOVERED;
4058 static void eeh_resume(struct pci_dev *pdev)
4061 struct adapter *adap = pci_get_drvdata(pdev);
4067 for_each_port(adap, i) {
4068 struct net_device *dev = adap->port[i];
4070 if (netif_running(dev)) {
4072 cxgb_set_rxmode(dev);
4074 netif_device_attach(dev);
4079 static const struct pci_error_handlers cxgb4_eeh = {
4080 .error_detected = eeh_err_detected,
4081 .slot_reset = eeh_slot_reset,
4082 .resume = eeh_resume,
4085 static inline bool is_x_10g_port(const struct link_config *lc)
4087 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4088 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4091 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4092 unsigned int us, unsigned int cnt,
4093 unsigned int size, unsigned int iqe_size)
4096 cxgb4_set_rspq_intr_params(q, us, cnt);
4097 q->iqe_len = iqe_size;
4102 * Perform default configuration of DMA queues depending on the number and type
4103 * of ports we found and the number of available CPUs. Most settings can be
4104 * modified by the admin prior to actual use.
4106 static void cfg_queues(struct adapter *adap)
4108 struct sge *s = &adap->sge;
4109 int i, n10g = 0, qidx = 0;
4110 #ifndef CONFIG_CHELSIO_T4_DCB
4115 for_each_port(adap, i)
4116 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4117 #ifdef CONFIG_CHELSIO_T4_DCB
4118 /* For Data Center Bridging support we need to be able to support up
4119 * to 8 Traffic Priorities; each of which will be assigned to its
4120 * own TX Queue in order to prevent Head-Of-Line Blocking.
4122 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4123 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4124 MAX_ETH_QSETS, adap->params.nports * 8);
4128 for_each_port(adap, i) {
4129 struct port_info *pi = adap2pinfo(adap, i);
4131 pi->first_qset = qidx;
4135 #else /* !CONFIG_CHELSIO_T4_DCB */
4137 * We default to 1 queue per non-10G port and up to # of cores queues
4141 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4142 if (q10g > netif_get_num_default_rss_queues())
4143 q10g = netif_get_num_default_rss_queues();
4145 for_each_port(adap, i) {
4146 struct port_info *pi = adap2pinfo(adap, i);
4148 pi->first_qset = qidx;
4149 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4152 #endif /* !CONFIG_CHELSIO_T4_DCB */
4155 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4157 if (is_offload(adap)) {
4159 * For offload we use 1 queue/channel if all ports are up to 1G,
4160 * otherwise we divide all available queues amongst the channels
4161 * capped by the number of available cores.
4164 i = min_t(int, ARRAY_SIZE(s->ofldrxq),
4166 s->ofldqsets = roundup(i, adap->params.nports);
4168 s->ofldqsets = adap->params.nports;
4169 /* For RDMA one Rx queue per channel suffices */
4170 s->rdmaqs = adap->params.nports;
4171 /* Try and allow at least 1 CIQ per cpu rounding down
4172 * to the number of ports, with a minimum of 1 per port.
4173 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4174 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4175 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4177 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4178 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4179 adap->params.nports;
4180 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4183 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4184 struct sge_eth_rxq *r = &s->ethrxq[i];
4186 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4190 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4191 s->ethtxq[i].q.size = 1024;
4193 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4194 s->ctrlq[i].q.size = 512;
4196 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4197 s->ofldtxq[i].q.size = 1024;
4199 for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
4200 struct sge_ofld_rxq *r = &s->ofldrxq[i];
4202 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4203 r->rspq.uld = CXGB4_ULD_ISCSI;
4207 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4208 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4210 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4211 r->rspq.uld = CXGB4_ULD_RDMA;
4215 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4216 if (ciq_size > SGE_MAX_IQ_SIZE) {
4217 CH_WARN(adap, "CIQ size too small for available IQs\n");
4218 ciq_size = SGE_MAX_IQ_SIZE;
4221 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4222 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4224 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4225 r->rspq.uld = CXGB4_ULD_RDMA;
4228 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4229 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4233 * Reduce the number of Ethernet queues across all ports to at most n.
4234 * n provides at least one queue per port.
4236 static void reduce_ethqs(struct adapter *adap, int n)
4239 struct port_info *pi;
4241 while (n < adap->sge.ethqsets)
4242 for_each_port(adap, i) {
4243 pi = adap2pinfo(adap, i);
4244 if (pi->nqsets > 1) {
4246 adap->sge.ethqsets--;
4247 if (adap->sge.ethqsets <= n)
4253 for_each_port(adap, i) {
4254 pi = adap2pinfo(adap, i);
4260 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4261 #define EXTRA_VECS 2
4263 static int enable_msix(struct adapter *adap)
4266 int i, want, need, allocated;
4267 struct sge *s = &adap->sge;
4268 unsigned int nchan = adap->params.nports;
4269 struct msix_entry *entries;
4271 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4276 for (i = 0; i < MAX_INGQ + 1; ++i)
4277 entries[i].entry = i;
4279 want = s->max_ethqsets + EXTRA_VECS;
4280 if (is_offload(adap)) {
4281 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
4282 /* need nchan for each possible ULD */
4283 ofld_need = 3 * nchan;
4285 #ifdef CONFIG_CHELSIO_T4_DCB
4286 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4289 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4291 need = adap->params.nports + EXTRA_VECS + ofld_need;
4293 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4294 if (allocated < 0) {
4295 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4296 " not using MSI-X\n");
4301 /* Distribute available vectors to the various queue groups.
4302 * Every group gets its minimum requirement and NIC gets top
4303 * priority for leftovers.
4305 i = allocated - EXTRA_VECS - ofld_need;
4306 if (i < s->max_ethqsets) {
4307 s->max_ethqsets = i;
4308 if (i < s->ethqsets)
4309 reduce_ethqs(adap, i);
4311 if (is_offload(adap)) {
4312 if (allocated < want) {
4314 s->rdmaciqs = nchan;
4317 /* leftovers go to OFLD */
4318 i = allocated - EXTRA_VECS - s->max_ethqsets -
4319 s->rdmaqs - s->rdmaciqs;
4320 s->ofldqsets = (i / nchan) * nchan; /* round down */
4322 for (i = 0; i < allocated; ++i)
4323 adap->msix_info[i].vec = entries[i].vector;
4331 static int init_rss(struct adapter *adap)
4335 for_each_port(adap, i) {
4336 struct port_info *pi = adap2pinfo(adap, i);
4338 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4341 for (j = 0; j < pi->rss_size; j++)
4342 pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
4347 static void print_port_info(const struct net_device *dev)
4351 const char *spd = "";
4352 const struct port_info *pi = netdev_priv(dev);
4353 const struct adapter *adap = pi->adapter;
4355 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4357 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4359 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4362 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4363 bufp += sprintf(bufp, "100/");
4364 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4365 bufp += sprintf(bufp, "1000/");
4366 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4367 bufp += sprintf(bufp, "10G/");
4368 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4369 bufp += sprintf(bufp, "40G/");
4372 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4374 netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
4375 adap->params.vpd.id,
4376 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4377 is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
4378 (adap->flags & USING_MSIX) ? " MSI-X" :
4379 (adap->flags & USING_MSI) ? " MSI" : "");
4380 netdev_info(dev, "S/N: %s, P/N: %s\n",
4381 adap->params.vpd.sn, adap->params.vpd.pn);
4384 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4386 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4390 * Free the following resources:
4391 * - memory used for tables
4394 * - resources FW is holding for us
4396 static void free_some_resources(struct adapter *adapter)
4400 t4_free_mem(adapter->l2t);
4401 t4_free_mem(adapter->tids.tid_tab);
4402 kfree(adapter->sge.egr_map);
4403 kfree(adapter->sge.ingr_map);
4404 kfree(adapter->sge.starving_fl);
4405 kfree(adapter->sge.txq_maperr);
4406 disable_msi(adapter);
4408 for_each_port(adapter, i)
4409 if (adapter->port[i]) {
4410 kfree(adap2pinfo(adapter, i)->rss);
4411 free_netdev(adapter->port[i]);
4413 if (adapter->flags & FW_OK)
4414 t4_fw_bye(adapter, adapter->fn);
4417 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4418 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4419 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4420 #define SEGMENT_SIZE 128
4422 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4424 int func, i, err, s_qpp, qpp, num_seg;
4425 struct port_info *pi;
4426 bool highdma = false;
4427 struct adapter *adapter = NULL;
4430 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4432 err = pci_request_regions(pdev, KBUILD_MODNAME);
4434 /* Just info, some other driver may have claimed the device. */
4435 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4439 err = pci_enable_device(pdev);
4441 dev_err(&pdev->dev, "cannot enable PCI device\n");
4442 goto out_release_regions;
4445 regs = pci_ioremap_bar(pdev, 0);
4447 dev_err(&pdev->dev, "cannot map device registers\n");
4449 goto out_disable_device;
4452 err = t4_wait_dev_ready(regs);
4454 goto out_unmap_bar0;
4456 /* We control everything through one PF */
4457 func = SOURCEPF_G(readl(regs + PL_WHOAMI_A));
4458 if (func != ent->driver_data) {
4460 pci_disable_device(pdev);
4461 pci_save_state(pdev); /* to restore SR-IOV later */
4465 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4467 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4469 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4470 "coherent allocations\n");
4471 goto out_unmap_bar0;
4474 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4476 dev_err(&pdev->dev, "no usable DMA configuration\n");
4477 goto out_unmap_bar0;
4481 pci_enable_pcie_error_reporting(pdev);
4482 enable_pcie_relaxed_ordering(pdev);
4483 pci_set_master(pdev);
4484 pci_save_state(pdev);
4486 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4489 goto out_unmap_bar0;
4492 adapter->workq = create_singlethread_workqueue("cxgb4");
4493 if (!adapter->workq) {
4495 goto out_free_adapter;
4498 /* PCI device has been enabled */
4499 adapter->flags |= DEV_ENABLED;
4501 adapter->regs = regs;
4502 adapter->pdev = pdev;
4503 adapter->pdev_dev = &pdev->dev;
4504 adapter->mbox = func;
4506 adapter->msg_enable = dflt_msg_enable;
4507 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4509 spin_lock_init(&adapter->stats_lock);
4510 spin_lock_init(&adapter->tid_release_lock);
4511 spin_lock_init(&adapter->win0_lock);
4513 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4514 INIT_WORK(&adapter->db_full_task, process_db_full);
4515 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4517 err = t4_prep_adapter(adapter);
4519 goto out_free_adapter;
4522 if (!is_t4(adapter->params.chip)) {
4523 s_qpp = (QUEUESPERPAGEPF0_S +
4524 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4526 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4527 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4528 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4530 /* Each segment size is 128B. Write coalescing is enabled only
4531 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4532 * queue is less no of segments that can be accommodated in
4535 if (qpp > num_seg) {
4537 "Incorrect number of egress queues per page\n");
4539 goto out_free_adapter;
4541 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4542 pci_resource_len(pdev, 2));
4543 if (!adapter->bar2) {
4544 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4546 goto out_free_adapter;
4550 setup_memwin(adapter);
4551 err = adap_init0(adapter);
4552 setup_memwin_rdma(adapter);
4556 for_each_port(adapter, i) {
4557 struct net_device *netdev;
4559 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4566 SET_NETDEV_DEV(netdev, &pdev->dev);
4568 adapter->port[i] = netdev;
4569 pi = netdev_priv(netdev);
4570 pi->adapter = adapter;
4571 pi->xact_addr_filt = -1;
4573 netdev->irq = pdev->irq;
4575 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4576 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4577 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4578 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4580 netdev->hw_features |= NETIF_F_HIGHDMA;
4581 netdev->features |= netdev->hw_features;
4582 netdev->vlan_features = netdev->features & VLAN_FEAT;
4584 netdev->priv_flags |= IFF_UNICAST_FLT;
4586 netdev->netdev_ops = &cxgb4_netdev_ops;
4587 #ifdef CONFIG_CHELSIO_T4_DCB
4588 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4589 cxgb4_dcb_state_init(netdev);
4591 cxgb4_set_ethtool_ops(netdev);
4594 pci_set_drvdata(pdev, adapter);
4596 if (adapter->flags & FW_OK) {
4597 err = t4_port_init(adapter, func, func, 0);
4603 * Configure queues and allocate tables now, they can be needed as
4604 * soon as the first register_netdev completes.
4606 cfg_queues(adapter);
4608 adapter->l2t = t4_init_l2t();
4609 if (!adapter->l2t) {
4610 /* We tolerate a lack of L2T, giving up some functionality */
4611 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4612 adapter->params.offload = 0;
4615 #if IS_ENABLED(CONFIG_IPV6)
4616 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4617 adapter->clipt_end);
4618 if (!adapter->clipt) {
4619 /* We tolerate a lack of clip_table, giving up
4620 * some functionality
4622 dev_warn(&pdev->dev,
4623 "could not allocate Clip table, continuing\n");
4624 adapter->params.offload = 0;
4627 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4628 dev_warn(&pdev->dev, "could not allocate TID table, "
4630 adapter->params.offload = 0;
4633 /* See what interrupts we'll be using */
4634 if (msi > 1 && enable_msix(adapter) == 0)
4635 adapter->flags |= USING_MSIX;
4636 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4637 adapter->flags |= USING_MSI;
4639 err = init_rss(adapter);
4644 * The card is now ready to go. If any errors occur during device
4645 * registration we do not fail the whole card but rather proceed only
4646 * with the ports we manage to register successfully. However we must
4647 * register at least one net device.
4649 for_each_port(adapter, i) {
4650 pi = adap2pinfo(adapter, i);
4651 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4652 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4654 err = register_netdev(adapter->port[i]);
4657 adapter->chan_map[pi->tx_chan] = i;
4658 print_port_info(adapter->port[i]);
4661 dev_err(&pdev->dev, "could not register any net devices\n");
4665 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4669 if (cxgb4_debugfs_root) {
4670 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4671 cxgb4_debugfs_root);
4672 setup_debugfs(adapter);
4675 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4676 pdev->needs_freset = 1;
4678 if (is_offload(adapter))
4679 attach_ulds(adapter);
4682 #ifdef CONFIG_PCI_IOV
4683 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
4684 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4685 dev_info(&pdev->dev,
4686 "instantiated %u virtual functions\n",
4692 free_some_resources(adapter);
4694 if (!is_t4(adapter->params.chip))
4695 iounmap(adapter->bar2);
4698 destroy_workqueue(adapter->workq);
4704 pci_disable_pcie_error_reporting(pdev);
4705 pci_disable_device(pdev);
4706 out_release_regions:
4707 pci_release_regions(pdev);
4711 static void remove_one(struct pci_dev *pdev)
4713 struct adapter *adapter = pci_get_drvdata(pdev);
4715 #ifdef CONFIG_PCI_IOV
4716 pci_disable_sriov(pdev);
4723 /* Tear down per-adapter Work Queue first since it can contain
4724 * references to our adapter data structure.
4726 destroy_workqueue(adapter->workq);
4728 if (is_offload(adapter))
4729 detach_ulds(adapter);
4731 disable_interrupts(adapter);
4733 for_each_port(adapter, i)
4734 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
4735 unregister_netdev(adapter->port[i]);
4737 debugfs_remove_recursive(adapter->debugfs_root);
4739 /* If we allocated filters, free up state associated with any
4742 if (adapter->tids.ftid_tab) {
4743 struct filter_entry *f = &adapter->tids.ftid_tab[0];
4744 for (i = 0; i < (adapter->tids.nftids +
4745 adapter->tids.nsftids); i++, f++)
4747 clear_filter(adapter, f);
4750 if (adapter->flags & FULL_INIT_DONE)
4753 free_some_resources(adapter);
4754 #if IS_ENABLED(CONFIG_IPV6)
4755 t4_cleanup_clip_tbl(adapter);
4757 iounmap(adapter->regs);
4758 if (!is_t4(adapter->params.chip))
4759 iounmap(adapter->bar2);
4760 pci_disable_pcie_error_reporting(pdev);
4761 if ((adapter->flags & DEV_ENABLED)) {
4762 pci_disable_device(pdev);
4763 adapter->flags &= ~DEV_ENABLED;
4765 pci_release_regions(pdev);
4769 pci_release_regions(pdev);
4772 static struct pci_driver cxgb4_driver = {
4773 .name = KBUILD_MODNAME,
4774 .id_table = cxgb4_pci_tbl,
4776 .remove = remove_one,
4777 .shutdown = remove_one,
4778 .err_handler = &cxgb4_eeh,
4781 static int __init cxgb4_init_module(void)
4785 /* Debugfs support is optional, just warn if this fails */
4786 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
4787 if (!cxgb4_debugfs_root)
4788 pr_warn("could not create debugfs entry, continuing\n");
4790 ret = pci_register_driver(&cxgb4_driver);
4792 debugfs_remove(cxgb4_debugfs_root);
4794 #if IS_ENABLED(CONFIG_IPV6)
4795 if (!inet6addr_registered) {
4796 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4797 inet6addr_registered = true;
4804 static void __exit cxgb4_cleanup_module(void)
4806 #if IS_ENABLED(CONFIG_IPV6)
4807 if (inet6addr_registered) {
4808 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
4809 inet6addr_registered = false;
4812 pci_unregister_driver(&cxgb4_driver);
4813 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
4816 module_init(cxgb4_init_module);
4817 module_exit(cxgb4_cleanup_module);