2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/etherdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/log2.h>
16 #include <linux/prefetch.h>
17 #include <linux/irq.h>
21 #include "nicvf_queues.h"
22 #include "thunder_bgx.h"
24 #define DRV_NAME "thunder-nicvf"
25 #define DRV_VERSION "1.0"
27 /* Supported devices */
28 static const struct pci_device_id nicvf_id_table[] = {
29 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
30 PCI_DEVICE_ID_THUNDER_NIC_VF,
31 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
32 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
33 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,
34 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
35 { 0, } /* end of table */
38 MODULE_AUTHOR("Sunil Goutham");
39 MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver");
40 MODULE_LICENSE("GPL v2");
41 MODULE_VERSION(DRV_VERSION);
42 MODULE_DEVICE_TABLE(pci, nicvf_id_table);
44 static int debug = 0x00;
45 module_param(debug, int, 0644);
46 MODULE_PARM_DESC(debug, "Debug message level bitmap");
48 static int cpi_alg = CPI_ALG_NONE;
49 module_param(cpi_alg, int, S_IRUGO);
50 MODULE_PARM_DESC(cpi_alg,
51 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
53 static inline void nicvf_set_rx_frame_cnt(struct nicvf *nic,
57 nic->drv_stats.rx_frames_64++;
58 else if (skb->len <= 127)
59 nic->drv_stats.rx_frames_127++;
60 else if (skb->len <= 255)
61 nic->drv_stats.rx_frames_255++;
62 else if (skb->len <= 511)
63 nic->drv_stats.rx_frames_511++;
64 else if (skb->len <= 1023)
65 nic->drv_stats.rx_frames_1023++;
66 else if (skb->len <= 1518)
67 nic->drv_stats.rx_frames_1518++;
69 nic->drv_stats.rx_frames_jumbo++;
72 /* The Cavium ThunderX network controller can *only* be found in SoCs
73 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
74 * registers on this platform are implicitly strongly ordered with respect
75 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
76 * with no memory barriers in this driver. The readq()/writeq() functions add
77 * explicit ordering operation which in this case are redundant, and only
81 /* Register read/write APIs */
82 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val)
84 writeq_relaxed(val, nic->reg_base + offset);
87 u64 nicvf_reg_read(struct nicvf *nic, u64 offset)
89 return readq_relaxed(nic->reg_base + offset);
92 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
95 void __iomem *addr = nic->reg_base + offset;
97 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));
100 u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx)
102 void __iomem *addr = nic->reg_base + offset;
104 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
107 /* VF -> PF mailbox communication */
109 static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx)
111 u64 *msg = (u64 *)mbx;
113 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]);
114 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]);
117 int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx)
119 int timeout = NIC_MBOX_MSG_TIMEOUT;
122 nic->pf_acked = false;
123 nic->pf_nacked = false;
125 nicvf_write_to_mbx(nic, mbx);
127 /* Wait for previous message to be acked, timeout 2sec */
128 while (!nic->pf_acked) {
136 netdev_err(nic->netdev,
137 "PF didn't ack to mbox msg %d from VF%d\n",
138 (mbx->msg.msg & 0xFF), nic->vf_id);
145 /* Checks if VF is able to comminicate with PF
146 * and also gets the VNIC number this VF is associated to.
148 static int nicvf_check_pf_ready(struct nicvf *nic)
150 int timeout = 5000, sleep = 20;
151 union nic_mbx mbx = {};
153 mbx.msg.msg = NIC_MBOX_MSG_READY;
155 nic->pf_ready_to_rcv_msg = false;
157 nicvf_write_to_mbx(nic, &mbx);
159 while (!nic->pf_ready_to_rcv_msg) {
161 if (nic->pf_ready_to_rcv_msg)
165 netdev_err(nic->netdev,
166 "PF didn't respond to READY msg\n");
173 static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx)
176 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats;
178 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats;
181 static void nicvf_handle_mbx_intr(struct nicvf *nic)
183 union nic_mbx mbx = {};
188 mbx_addr = NIC_VF_PF_MAILBOX_0_1;
189 mbx_data = (u64 *)&mbx;
191 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
192 *mbx_data = nicvf_reg_read(nic, mbx_addr);
194 mbx_addr += sizeof(u64);
197 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg);
198 switch (mbx.msg.msg) {
199 case NIC_MBOX_MSG_READY:
200 nic->pf_ready_to_rcv_msg = true;
201 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F;
202 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F;
203 nic->node = mbx.nic_cfg.node_id;
204 if (!nic->set_mac_pending)
205 ether_addr_copy(nic->netdev->dev_addr,
206 mbx.nic_cfg.mac_addr);
207 nic->link_up = false;
211 case NIC_MBOX_MSG_ACK:
212 nic->pf_acked = true;
214 case NIC_MBOX_MSG_NACK:
215 nic->pf_nacked = true;
217 case NIC_MBOX_MSG_RSS_SIZE:
218 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size;
219 nic->pf_acked = true;
221 case NIC_MBOX_MSG_BGX_STATS:
222 nicvf_read_bgx_stats(nic, &mbx.bgx_stats);
223 nic->pf_acked = true;
224 nic->bgx_stats_acked = true;
226 case NIC_MBOX_MSG_BGX_LINK_CHANGE:
227 nic->pf_acked = true;
228 nic->link_up = mbx.link_status.link_up;
229 nic->duplex = mbx.link_status.duplex;
230 nic->speed = mbx.link_status.speed;
232 netdev_info(nic->netdev, "%s: Link is Up %d Mbps %s\n",
233 nic->netdev->name, nic->speed,
234 nic->duplex == DUPLEX_FULL ?
235 "Full duplex" : "Half duplex");
236 netif_carrier_on(nic->netdev);
237 netif_tx_wake_all_queues(nic->netdev);
239 netdev_info(nic->netdev, "%s: Link is Down\n",
241 netif_carrier_off(nic->netdev);
242 netif_tx_stop_all_queues(nic->netdev);
246 netdev_err(nic->netdev,
247 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg);
250 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0);
253 static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev)
255 union nic_mbx mbx = {};
257 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
258 mbx.mac.vf_id = nic->vf_id;
259 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr);
261 return nicvf_send_msg_to_pf(nic, &mbx);
264 static void nicvf_config_cpi(struct nicvf *nic)
266 union nic_mbx mbx = {};
268 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG;
269 mbx.cpi_cfg.vf_id = nic->vf_id;
270 mbx.cpi_cfg.cpi_alg = nic->cpi_alg;
271 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt;
273 nicvf_send_msg_to_pf(nic, &mbx);
276 static void nicvf_get_rss_size(struct nicvf *nic)
278 union nic_mbx mbx = {};
280 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
281 mbx.rss_size.vf_id = nic->vf_id;
282 nicvf_send_msg_to_pf(nic, &mbx);
285 void nicvf_config_rss(struct nicvf *nic)
287 union nic_mbx mbx = {};
288 struct nicvf_rss_info *rss = &nic->rss_info;
289 int ind_tbl_len = rss->rss_size;
292 mbx.rss_cfg.vf_id = nic->vf_id;
293 mbx.rss_cfg.hash_bits = rss->hash_bits;
294 while (ind_tbl_len) {
295 mbx.rss_cfg.tbl_offset = nextq;
296 mbx.rss_cfg.tbl_len = min(ind_tbl_len,
297 RSS_IND_TBL_LEN_PER_MBX_MSG);
298 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ?
299 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG;
301 for (i = 0; i < mbx.rss_cfg.tbl_len; i++)
302 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++];
304 nicvf_send_msg_to_pf(nic, &mbx);
306 ind_tbl_len -= mbx.rss_cfg.tbl_len;
310 void nicvf_set_rss_key(struct nicvf *nic)
312 struct nicvf_rss_info *rss = &nic->rss_info;
313 u64 key_addr = NIC_VNIC_RSS_KEY_0_4;
316 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
317 nicvf_reg_write(nic, key_addr, rss->key[idx]);
318 key_addr += sizeof(u64);
322 static int nicvf_rss_init(struct nicvf *nic)
324 struct nicvf_rss_info *rss = &nic->rss_info;
327 nicvf_get_rss_size(nic);
329 if ((nic->qs->rq_cnt <= 1) || (cpi_alg != CPI_ALG_NONE)) {
337 /* Using the HW reset value for now */
338 rss->key[0] = 0xFEED0BADFEED0BADULL;
339 rss->key[1] = 0xFEED0BADFEED0BADULL;
340 rss->key[2] = 0xFEED0BADFEED0BADULL;
341 rss->key[3] = 0xFEED0BADFEED0BADULL;
342 rss->key[4] = 0xFEED0BADFEED0BADULL;
344 nicvf_set_rss_key(nic);
346 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA;
347 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg);
349 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size));
351 for (idx = 0; idx < rss->rss_size; idx++)
352 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx,
354 nicvf_config_rss(nic);
358 int nicvf_set_real_num_queues(struct net_device *netdev,
359 int tx_queues, int rx_queues)
363 err = netif_set_real_num_tx_queues(netdev, tx_queues);
366 "Failed to set no of Tx queues: %d\n", tx_queues);
370 err = netif_set_real_num_rx_queues(netdev, rx_queues);
373 "Failed to set no of Rx queues: %d\n", rx_queues);
377 static int nicvf_init_resources(struct nicvf *nic)
380 union nic_mbx mbx = {};
382 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
385 nicvf_qset_config(nic, true);
387 /* Initialize queues and HW for data transfer */
388 err = nicvf_config_data_transfer(nic, true);
390 netdev_err(nic->netdev,
391 "Failed to alloc/config VF's QSet resources\n");
395 /* Send VF config done msg to PF */
396 nicvf_write_to_mbx(nic, &mbx);
401 static void nicvf_snd_pkt_handler(struct net_device *netdev,
402 struct cmp_queue *cq,
403 struct cqe_send_t *cqe_tx, int cqe_type)
405 struct sk_buff *skb = NULL;
406 struct nicvf *nic = netdev_priv(netdev);
407 struct snd_queue *sq;
408 struct sq_hdr_subdesc *hdr;
410 sq = &nic->qs->sq[cqe_tx->sq_idx];
412 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
413 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
416 netdev_dbg(nic->netdev,
417 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n",
418 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx,
419 cqe_tx->sqe_ptr, hdr->subdesc_cnt);
421 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
422 nicvf_check_cqe_tx_errs(nic, cq, cqe_tx);
423 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
424 /* For TSO offloaded packets only one head SKB needs to be freed */
427 dev_consume_skb_any(skb);
431 static void nicvf_rcv_pkt_handler(struct net_device *netdev,
432 struct napi_struct *napi,
433 struct cmp_queue *cq,
434 struct cqe_rx_t *cqe_rx, int cqe_type)
437 struct nicvf *nic = netdev_priv(netdev);
440 /* Check for errors */
441 err = nicvf_check_cqe_rx_errs(nic, cq, cqe_rx);
442 if (err && !cqe_rx->rb_cnt)
445 skb = nicvf_get_rcv_skb(nic, cqe_rx);
447 netdev_dbg(nic->netdev, "Packet not received\n");
451 if (netif_msg_pktdata(nic)) {
452 netdev_info(nic->netdev, "%s: skb 0x%p, len=%d\n", netdev->name,
454 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
455 skb->data, skb->len, true);
458 nicvf_set_rx_frame_cnt(nic, skb);
460 skb_record_rx_queue(skb, cqe_rx->rq_idx);
461 if (netdev->hw_features & NETIF_F_RXCSUM) {
462 /* HW by default verifies TCP/UDP/SCTP checksums */
463 skb->ip_summed = CHECKSUM_UNNECESSARY;
465 skb_checksum_none_assert(skb);
468 skb->protocol = eth_type_trans(skb, netdev);
470 if (napi && (netdev->features & NETIF_F_GRO))
471 napi_gro_receive(napi, skb);
473 netif_receive_skb(skb);
476 static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
477 struct napi_struct *napi, int budget)
479 int processed_cqe, work_done = 0;
480 int cqe_count, cqe_head;
481 struct nicvf *nic = netdev_priv(netdev);
482 struct queue_set *qs = nic->qs;
483 struct cmp_queue *cq = &qs->cq[cq_idx];
484 struct cqe_rx_t *cq_desc;
486 spin_lock_bh(&cq->lock);
489 /* Get no of valid CQ entries to process */
490 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx);
491 cqe_count &= CQ_CQE_COUNT;
495 /* Get head of the valid CQ entries */
496 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
499 netdev_dbg(nic->netdev, "%s cqe_count %d cqe_head %d\n",
500 __func__, cqe_count, cqe_head);
501 while (processed_cqe < cqe_count) {
502 /* Get the CQ descriptor */
503 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
505 cqe_head &= (cq->dmem.q_len - 1);
506 /* Initiate prefetch for next descriptor */
507 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head));
509 if ((work_done >= budget) && napi &&
510 (cq_desc->cqe_type != CQE_TYPE_SEND)) {
514 netdev_dbg(nic->netdev, "cq_desc->cqe_type %d\n",
516 switch (cq_desc->cqe_type) {
518 nicvf_rcv_pkt_handler(netdev, napi, cq,
519 cq_desc, CQE_TYPE_RX);
523 nicvf_snd_pkt_handler(netdev, cq,
524 (void *)cq_desc, CQE_TYPE_SEND);
526 case CQE_TYPE_INVALID:
527 case CQE_TYPE_RX_SPLIT:
528 case CQE_TYPE_RX_TCP:
529 case CQE_TYPE_SEND_PTP:
535 netdev_dbg(nic->netdev, "%s processed_cqe %d work_done %d budget %d\n",
536 __func__, processed_cqe, work_done, budget);
538 /* Ring doorbell to inform H/W to reuse processed CQEs */
539 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
540 cq_idx, processed_cqe);
542 if ((work_done < budget) && napi)
546 spin_unlock_bh(&cq->lock);
550 static int nicvf_poll(struct napi_struct *napi, int budget)
554 struct net_device *netdev = napi->dev;
555 struct nicvf *nic = netdev_priv(netdev);
556 struct nicvf_cq_poll *cq;
557 struct netdev_queue *txq;
559 cq = container_of(napi, struct nicvf_cq_poll, napi);
560 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
562 txq = netdev_get_tx_queue(netdev, cq->cq_idx);
563 if (netif_tx_queue_stopped(txq))
564 netif_tx_wake_queue(txq);
566 if (work_done < budget) {
567 /* Slow packet rate, exit polling */
569 /* Re-enable interrupts */
570 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD,
572 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
573 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD,
574 cq->cq_idx, cq_head);
575 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
580 /* Qset error interrupt handler
582 * As of now only CQ errors are handled
584 static void nicvf_handle_qs_err(unsigned long data)
586 struct nicvf *nic = (struct nicvf *)data;
587 struct queue_set *qs = nic->qs;
591 netif_tx_disable(nic->netdev);
593 /* Check if it is CQ err */
594 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
595 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS,
597 if (!(status & CQ_ERR_MASK))
599 /* Process already queued CQEs and reconfig CQ */
600 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
601 nicvf_sq_disable(nic, qidx);
602 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0);
603 nicvf_cmp_queue_config(nic, qs, qidx, true);
604 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx);
605 nicvf_sq_enable(nic, &qs->sq[qidx], qidx);
607 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
610 netif_tx_start_all_queues(nic->netdev);
611 /* Re-enable Qset error interrupt */
612 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
615 static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq)
617 struct nicvf *nic = (struct nicvf *)nicvf_irq;
620 intr = nicvf_reg_read(nic, NIC_VF_INT);
621 /* Check for spurious interrupt */
622 if (!(intr & NICVF_INTR_MBOX_MASK))
625 nicvf_handle_mbx_intr(nic);
630 static irqreturn_t nicvf_intr_handler(int irq, void *nicvf_irq)
632 u64 qidx, intr, clear_intr = 0;
633 u64 cq_intr, rbdr_intr, qs_err_intr;
634 struct nicvf *nic = (struct nicvf *)nicvf_irq;
635 struct queue_set *qs = nic->qs;
636 struct nicvf_cq_poll *cq_poll = NULL;
638 intr = nicvf_reg_read(nic, NIC_VF_INT);
639 if (netif_msg_intr(nic))
640 netdev_info(nic->netdev, "%s: interrupt status 0x%llx\n",
641 nic->netdev->name, intr);
643 qs_err_intr = intr & NICVF_INTR_QS_ERR_MASK;
645 /* Disable Qset err interrupt and schedule softirq */
646 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
647 tasklet_hi_schedule(&nic->qs_err_task);
648 clear_intr |= qs_err_intr;
651 /* Disable interrupts and start polling */
652 cq_intr = (intr & NICVF_INTR_CQ_MASK) >> NICVF_INTR_CQ_SHIFT;
653 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
654 if (!(cq_intr & (1 << qidx)))
656 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_CQ, qidx))
659 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
660 clear_intr |= ((1 << qidx) << NICVF_INTR_CQ_SHIFT);
662 cq_poll = nic->napi[qidx];
665 napi_schedule(&cq_poll->napi);
668 /* Handle RBDR interrupts */
669 rbdr_intr = (intr & NICVF_INTR_RBDR_MASK) >> NICVF_INTR_RBDR_SHIFT;
671 /* Disable RBDR interrupt and schedule softirq */
672 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
673 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx))
675 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
676 tasklet_hi_schedule(&nic->rbdr_task);
677 clear_intr |= ((1 << qidx) << NICVF_INTR_RBDR_SHIFT);
681 /* Clear interrupts */
682 nicvf_reg_write(nic, NIC_VF_INT, clear_intr);
686 static int nicvf_enable_msix(struct nicvf *nic)
690 nic->num_vec = NIC_VF_MSIX_VECTORS;
692 for (vec = 0; vec < nic->num_vec; vec++)
693 nic->msix_entries[vec].entry = vec;
695 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
697 netdev_err(nic->netdev,
698 "Req for #%d msix vectors failed\n", nic->num_vec);
701 nic->msix_enabled = 1;
705 static void nicvf_disable_msix(struct nicvf *nic)
707 if (nic->msix_enabled) {
708 pci_disable_msix(nic->pdev);
709 nic->msix_enabled = 0;
714 static int nicvf_register_interrupts(struct nicvf *nic)
716 int irq, free, ret = 0;
720 sprintf(nic->irq_name[irq], "NICVF%d CQ%d",
724 sprintf(nic->irq_name[irq], "NICVF%d SQ%d",
725 nic->vf_id, irq - NICVF_INTR_ID_SQ);
727 for_each_rbdr_irq(irq)
728 sprintf(nic->irq_name[irq], "NICVF%d RBDR%d",
729 nic->vf_id, irq - NICVF_INTR_ID_RBDR);
731 /* Register all interrupts except mailbox */
732 for (irq = 0; irq < NICVF_INTR_ID_SQ; irq++) {
733 vector = nic->msix_entries[irq].vector;
734 ret = request_irq(vector, nicvf_intr_handler,
735 0, nic->irq_name[irq], nic);
738 nic->irq_allocated[irq] = true;
741 for (irq = NICVF_INTR_ID_SQ; irq < NICVF_INTR_ID_MISC; irq++) {
742 vector = nic->msix_entries[irq].vector;
743 ret = request_irq(vector, nicvf_intr_handler,
744 0, nic->irq_name[irq], nic);
747 nic->irq_allocated[irq] = true;
750 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR],
751 "NICVF%d Qset error", nic->vf_id);
753 vector = nic->msix_entries[NICVF_INTR_ID_QS_ERR].vector;
754 irq = NICVF_INTR_ID_QS_ERR;
755 ret = request_irq(vector, nicvf_intr_handler,
756 0, nic->irq_name[irq], nic);
758 nic->irq_allocated[irq] = true;
762 netdev_err(nic->netdev, "Request irq failed\n");
763 for (free = 0; free < irq; free++)
764 free_irq(nic->msix_entries[free].vector, nic);
771 static void nicvf_unregister_interrupts(struct nicvf *nic)
775 /* Free registered interrupts */
776 for (irq = 0; irq < nic->num_vec; irq++) {
777 if (nic->irq_allocated[irq])
778 free_irq(nic->msix_entries[irq].vector, nic);
779 nic->irq_allocated[irq] = false;
783 nicvf_disable_msix(nic);
786 /* Initialize MSIX vectors and register MISC interrupt.
787 * Send READY message to PF to check if its alive
789 static int nicvf_register_misc_interrupt(struct nicvf *nic)
792 int irq = NICVF_INTR_ID_MISC;
794 /* Return if mailbox interrupt is already registered */
795 if (nic->msix_enabled)
799 if (!nicvf_enable_msix(nic))
802 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF");
803 /* Register Misc interrupt */
804 ret = request_irq(nic->msix_entries[irq].vector,
805 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic);
809 nic->irq_allocated[irq] = true;
811 /* Enable mailbox interrupt */
812 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0);
814 /* Check if VF is able to communicate with PF */
815 if (!nicvf_check_pf_ready(nic)) {
816 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
817 nicvf_unregister_interrupts(nic);
824 static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
826 struct nicvf *nic = netdev_priv(netdev);
827 int qid = skb_get_queue_mapping(skb);
828 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
830 /* Check for minimum packet length */
831 if (skb->len <= ETH_HLEN) {
836 if (!nicvf_sq_append_skb(nic, skb) && !netif_tx_queue_stopped(txq)) {
837 netif_tx_stop_queue(txq);
838 nic->drv_stats.tx_busy++;
839 if (netif_msg_tx_err(nic))
841 "%s: Transmit ring full, stopping SQ%d\n",
844 return NETDEV_TX_BUSY;
850 int nicvf_stop(struct net_device *netdev)
853 struct nicvf *nic = netdev_priv(netdev);
854 struct queue_set *qs = nic->qs;
855 struct nicvf_cq_poll *cq_poll = NULL;
856 union nic_mbx mbx = {};
858 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN;
859 nicvf_send_msg_to_pf(nic, &mbx);
861 netif_carrier_off(netdev);
862 netif_tx_disable(netdev);
864 /* Disable RBDR & QS error interrupts */
865 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
866 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
867 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
869 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
870 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
872 /* Wait for pending IRQ handlers to finish */
873 for (irq = 0; irq < nic->num_vec; irq++)
874 synchronize_irq(nic->msix_entries[irq].vector);
876 tasklet_kill(&nic->rbdr_task);
877 tasklet_kill(&nic->qs_err_task);
878 if (nic->rb_work_scheduled)
879 cancel_delayed_work_sync(&nic->rbdr_work);
881 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
882 cq_poll = nic->napi[qidx];
885 nic->napi[qidx] = NULL;
886 napi_synchronize(&cq_poll->napi);
887 /* CQ intr is enabled while napi_complete,
890 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
891 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
892 napi_disable(&cq_poll->napi);
893 netif_napi_del(&cq_poll->napi);
898 nicvf_config_data_transfer(nic, false);
900 /* Disable HW Qset */
901 nicvf_qset_config(nic, false);
903 /* disable mailbox interrupt */
904 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
906 nicvf_unregister_interrupts(nic);
911 int nicvf_open(struct net_device *netdev)
914 struct nicvf *nic = netdev_priv(netdev);
915 struct queue_set *qs = nic->qs;
916 struct nicvf_cq_poll *cq_poll = NULL;
918 nic->mtu = netdev->mtu;
920 netif_carrier_off(netdev);
922 err = nicvf_register_misc_interrupt(nic);
926 /* Register NAPI handler for processing CQEs */
927 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
928 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL);
933 cq_poll->cq_idx = qidx;
934 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll,
936 napi_enable(&cq_poll->napi);
937 nic->napi[qidx] = cq_poll;
940 /* Check if we got MAC address from PF or else generate a radom MAC */
941 if (is_zero_ether_addr(netdev->dev_addr)) {
942 eth_hw_addr_random(netdev);
943 nicvf_hw_set_mac_addr(nic, netdev);
946 if (nic->set_mac_pending) {
947 nic->set_mac_pending = false;
948 nicvf_hw_set_mac_addr(nic, netdev);
951 /* Init tasklet for handling Qset err interrupt */
952 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err,
955 /* Init RBDR tasklet which will refill RBDR */
956 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task,
958 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work);
960 /* Configure CPI alorithm */
961 nic->cpi_alg = cpi_alg;
962 nicvf_config_cpi(nic);
964 /* Configure receive side scaling */
967 err = nicvf_register_interrupts(nic);
971 /* Initialize the queues */
972 err = nicvf_init_resources(nic);
976 /* Make sure queue initialization is written */
979 nicvf_reg_write(nic, NIC_VF_INT, -1);
980 /* Enable Qset err interrupt */
981 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
983 /* Enable completion queue interrupt */
984 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
985 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
987 /* Enable RBDR threshold interrupt */
988 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
989 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
991 netif_carrier_on(netdev);
992 netif_tx_start_all_queues(netdev);
996 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
997 nicvf_unregister_interrupts(nic);
999 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
1000 cq_poll = nic->napi[qidx];
1003 napi_disable(&cq_poll->napi);
1004 netif_napi_del(&cq_poll->napi);
1006 nic->napi[qidx] = NULL;
1011 static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
1013 union nic_mbx mbx = {};
1015 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
1016 mbx.frs.max_frs = mtu;
1017 mbx.frs.vf_id = nic->vf_id;
1019 return nicvf_send_msg_to_pf(nic, &mbx);
1022 static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
1024 struct nicvf *nic = netdev_priv(netdev);
1026 if (new_mtu > NIC_HW_MAX_FRS)
1029 if (new_mtu < NIC_HW_MIN_FRS)
1032 if (nicvf_update_hw_max_frs(nic, new_mtu))
1034 netdev->mtu = new_mtu;
1040 static int nicvf_set_mac_address(struct net_device *netdev, void *p)
1042 struct sockaddr *addr = p;
1043 struct nicvf *nic = netdev_priv(netdev);
1045 if (!is_valid_ether_addr(addr->sa_data))
1046 return -EADDRNOTAVAIL;
1048 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1050 if (nic->msix_enabled) {
1051 if (nicvf_hw_set_mac_addr(nic, netdev))
1054 nic->set_mac_pending = true;
1060 void nicvf_update_lmac_stats(struct nicvf *nic)
1063 union nic_mbx mbx = {};
1066 if (!netif_running(nic->netdev))
1069 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
1070 mbx.bgx_stats.vf_id = nic->vf_id;
1072 mbx.bgx_stats.rx = 1;
1073 while (stat < BGX_RX_STATS_COUNT) {
1074 nic->bgx_stats_acked = 0;
1075 mbx.bgx_stats.idx = stat;
1076 nicvf_send_msg_to_pf(nic, &mbx);
1078 while ((!nic->bgx_stats_acked) && (timeout < 10)) {
1088 mbx.bgx_stats.rx = 0;
1089 while (stat < BGX_TX_STATS_COUNT) {
1090 nic->bgx_stats_acked = 0;
1091 mbx.bgx_stats.idx = stat;
1092 nicvf_send_msg_to_pf(nic, &mbx);
1094 while ((!nic->bgx_stats_acked) && (timeout < 10)) {
1102 void nicvf_update_stats(struct nicvf *nic)
1105 struct nicvf_hw_stats *stats = &nic->stats;
1106 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1107 struct queue_set *qs = nic->qs;
1109 #define GET_RX_STATS(reg) \
1110 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
1111 #define GET_TX_STATS(reg) \
1112 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
1114 stats->rx_bytes_ok = GET_RX_STATS(RX_OCTS);
1115 stats->rx_ucast_frames_ok = GET_RX_STATS(RX_UCAST);
1116 stats->rx_bcast_frames_ok = GET_RX_STATS(RX_BCAST);
1117 stats->rx_mcast_frames_ok = GET_RX_STATS(RX_MCAST);
1118 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS);
1119 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR);
1120 stats->rx_drop_red = GET_RX_STATS(RX_RED);
1121 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN);
1122 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST);
1123 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST);
1124 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
1125 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
1127 stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS);
1128 stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST);
1129 stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST);
1130 stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST);
1131 stats->tx_drops = GET_TX_STATS(TX_DROP);
1133 drv_stats->rx_frames_ok = stats->rx_ucast_frames_ok +
1134 stats->rx_bcast_frames_ok +
1135 stats->rx_mcast_frames_ok;
1136 drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok +
1137 stats->tx_bcast_frames_ok +
1138 stats->tx_mcast_frames_ok;
1139 drv_stats->rx_drops = stats->rx_drop_red +
1140 stats->rx_drop_overrun;
1141 drv_stats->tx_drops = stats->tx_drops;
1143 /* Update RQ and SQ stats */
1144 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1145 nicvf_update_rq_stats(nic, qidx);
1146 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1147 nicvf_update_sq_stats(nic, qidx);
1150 static struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev,
1151 struct rtnl_link_stats64 *stats)
1153 struct nicvf *nic = netdev_priv(netdev);
1154 struct nicvf_hw_stats *hw_stats = &nic->stats;
1155 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1157 nicvf_update_stats(nic);
1159 stats->rx_bytes = hw_stats->rx_bytes_ok;
1160 stats->rx_packets = drv_stats->rx_frames_ok;
1161 stats->rx_dropped = drv_stats->rx_drops;
1163 stats->tx_bytes = hw_stats->tx_bytes_ok;
1164 stats->tx_packets = drv_stats->tx_frames_ok;
1165 stats->tx_dropped = drv_stats->tx_drops;
1170 static void nicvf_tx_timeout(struct net_device *dev)
1172 struct nicvf *nic = netdev_priv(dev);
1174 if (netif_msg_tx_err(nic))
1175 netdev_warn(dev, "%s: Transmit timed out, resetting\n",
1178 schedule_work(&nic->reset_task);
1181 static void nicvf_reset_task(struct work_struct *work)
1185 nic = container_of(work, struct nicvf, reset_task);
1187 if (!netif_running(nic->netdev))
1190 nicvf_stop(nic->netdev);
1191 nicvf_open(nic->netdev);
1192 nic->netdev->trans_start = jiffies;
1195 static const struct net_device_ops nicvf_netdev_ops = {
1196 .ndo_open = nicvf_open,
1197 .ndo_stop = nicvf_stop,
1198 .ndo_start_xmit = nicvf_xmit,
1199 .ndo_change_mtu = nicvf_change_mtu,
1200 .ndo_set_mac_address = nicvf_set_mac_address,
1201 .ndo_get_stats64 = nicvf_get_stats64,
1202 .ndo_tx_timeout = nicvf_tx_timeout,
1205 static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1207 struct device *dev = &pdev->dev;
1208 struct net_device *netdev;
1210 struct queue_set *qs;
1213 err = pci_enable_device(pdev);
1215 dev_err(dev, "Failed to enable PCI device\n");
1219 err = pci_request_regions(pdev, DRV_NAME);
1221 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1222 goto err_disable_device;
1225 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1227 dev_err(dev, "Unable to get usable DMA configuration\n");
1228 goto err_release_regions;
1231 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1233 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n");
1234 goto err_release_regions;
1237 netdev = alloc_etherdev_mqs(sizeof(struct nicvf),
1238 MAX_RCV_QUEUES_PER_QS,
1239 MAX_SND_QUEUES_PER_QS);
1242 goto err_release_regions;
1245 pci_set_drvdata(pdev, netdev);
1247 SET_NETDEV_DEV(netdev, &pdev->dev);
1249 nic = netdev_priv(netdev);
1250 nic->netdev = netdev;
1253 /* MAP VF's configuration registers */
1254 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1255 if (!nic->reg_base) {
1256 dev_err(dev, "Cannot map config register space, aborting\n");
1258 goto err_free_netdev;
1261 err = nicvf_set_qset_resources(nic);
1263 goto err_free_netdev;
1267 err = nicvf_set_real_num_queues(netdev, qs->sq_cnt, qs->rq_cnt);
1269 goto err_free_netdev;
1271 /* Check if PF is alive and get MAC address for this VF */
1272 err = nicvf_register_misc_interrupt(nic);
1274 goto err_free_netdev;
1276 netdev->features |= (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
1277 NETIF_F_TSO | NETIF_F_GRO);
1278 netdev->hw_features = netdev->features;
1280 netdev->netdev_ops = &nicvf_netdev_ops;
1282 INIT_WORK(&nic->reset_task, nicvf_reset_task);
1284 err = register_netdev(netdev);
1286 dev_err(dev, "Failed to register netdevice\n");
1287 goto err_unregister_interrupts;
1290 nic->msg_enable = debug;
1292 nicvf_set_ethtool_ops(netdev);
1296 err_unregister_interrupts:
1297 nicvf_unregister_interrupts(nic);
1299 pci_set_drvdata(pdev, NULL);
1300 free_netdev(netdev);
1301 err_release_regions:
1302 pci_release_regions(pdev);
1304 pci_disable_device(pdev);
1308 static void nicvf_remove(struct pci_dev *pdev)
1310 struct net_device *netdev = pci_get_drvdata(pdev);
1311 struct nicvf *nic = netdev_priv(netdev);
1313 unregister_netdev(netdev);
1314 nicvf_unregister_interrupts(nic);
1315 pci_set_drvdata(pdev, NULL);
1316 free_netdev(netdev);
1317 pci_release_regions(pdev);
1318 pci_disable_device(pdev);
1321 static struct pci_driver nicvf_driver = {
1323 .id_table = nicvf_id_table,
1324 .probe = nicvf_probe,
1325 .remove = nicvf_remove,
1328 static int __init nicvf_init_module(void)
1330 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1332 return pci_register_driver(&nicvf_driver);
1335 static void __exit nicvf_cleanup_module(void)
1337 pci_unregister_driver(&nicvf_driver);
1340 module_init(nicvf_init_module);
1341 module_exit(nicvf_cleanup_module);