2 * Cadence MACB/GEM Ethernet Controller driver
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
33 #include <linux/pinctrl/consumer.h>
37 #define MACB_RX_BUFFER_SIZE 128
38 #define RX_BUFFER_MULTIPLE 64 /* bytes */
39 #define RX_RING_SIZE 512 /* must be power of 2 */
40 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
42 #define TX_RING_SIZE 128 /* must be power of 2 */
43 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
45 /* level of occupied TX descriptors under which we wake up TX process */
46 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
48 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
50 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
53 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
56 * Graceful stop timeouts in us. We should allow up to
57 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
59 #define MACB_HALT_TIMEOUT 1230
61 /* Ring buffer accessors */
62 static unsigned int macb_tx_ring_wrap(unsigned int index)
64 return index & (TX_RING_SIZE - 1);
67 static struct macb_dma_desc *macb_tx_desc(struct macb *bp, unsigned int index)
69 return &bp->tx_ring[macb_tx_ring_wrap(index)];
72 static struct macb_tx_skb *macb_tx_skb(struct macb *bp, unsigned int index)
74 return &bp->tx_skb[macb_tx_ring_wrap(index)];
77 static dma_addr_t macb_tx_dma(struct macb *bp, unsigned int index)
81 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
83 return bp->tx_ring_dma + offset;
86 static unsigned int macb_rx_ring_wrap(unsigned int index)
88 return index & (RX_RING_SIZE - 1);
91 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
93 return &bp->rx_ring[macb_rx_ring_wrap(index)];
96 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
98 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
101 void macb_set_hwaddr(struct macb *bp)
106 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
107 macb_or_gem_writel(bp, SA1B, bottom);
108 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
109 macb_or_gem_writel(bp, SA1T, top);
111 /* Clear unused address register sets */
112 macb_or_gem_writel(bp, SA2B, 0);
113 macb_or_gem_writel(bp, SA2T, 0);
114 macb_or_gem_writel(bp, SA3B, 0);
115 macb_or_gem_writel(bp, SA3T, 0);
116 macb_or_gem_writel(bp, SA4B, 0);
117 macb_or_gem_writel(bp, SA4T, 0);
119 EXPORT_SYMBOL_GPL(macb_set_hwaddr);
121 void macb_get_hwaddr(struct macb *bp)
123 struct macb_platform_data *pdata;
129 pdata = dev_get_platdata(&bp->pdev->dev);
131 /* Check all 4 address register for vaild address */
132 for (i = 0; i < 4; i++) {
133 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
134 top = macb_or_gem_readl(bp, SA1T + i * 8);
136 if (pdata && pdata->rev_eth_addr) {
137 addr[5] = bottom & 0xff;
138 addr[4] = (bottom >> 8) & 0xff;
139 addr[3] = (bottom >> 16) & 0xff;
140 addr[2] = (bottom >> 24) & 0xff;
141 addr[1] = top & 0xff;
142 addr[0] = (top & 0xff00) >> 8;
144 addr[0] = bottom & 0xff;
145 addr[1] = (bottom >> 8) & 0xff;
146 addr[2] = (bottom >> 16) & 0xff;
147 addr[3] = (bottom >> 24) & 0xff;
148 addr[4] = top & 0xff;
149 addr[5] = (top >> 8) & 0xff;
152 if (is_valid_ether_addr(addr)) {
153 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
158 netdev_info(bp->dev, "invalid hw address, using random\n");
159 eth_hw_addr_random(bp->dev);
161 EXPORT_SYMBOL_GPL(macb_get_hwaddr);
163 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
165 struct macb *bp = bus->priv;
168 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
169 | MACB_BF(RW, MACB_MAN_READ)
170 | MACB_BF(PHYA, mii_id)
171 | MACB_BF(REGA, regnum)
172 | MACB_BF(CODE, MACB_MAN_CODE)));
174 /* wait for end of transfer */
175 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
178 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
183 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
186 struct macb *bp = bus->priv;
188 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
189 | MACB_BF(RW, MACB_MAN_WRITE)
190 | MACB_BF(PHYA, mii_id)
191 | MACB_BF(REGA, regnum)
192 | MACB_BF(CODE, MACB_MAN_CODE)
193 | MACB_BF(DATA, value)));
195 /* wait for end of transfer */
196 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
203 * macb_set_tx_clk() - Set a clock to a new frequency
204 * @clk Pointer to the clock to change
205 * @rate New frequency in Hz
206 * @dev Pointer to the struct net_device
208 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
210 long ferr, rate, rate_rounded;
226 rate_rounded = clk_round_rate(clk, rate);
227 if (rate_rounded < 0)
230 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
233 ferr = abs(rate_rounded - rate);
234 ferr = DIV_ROUND_UP(ferr, rate / 100000);
236 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
239 if (clk_set_rate(clk, rate_rounded))
240 netdev_err(dev, "adjusting tx_clk failed.\n");
243 static void macb_handle_link_change(struct net_device *dev)
245 struct macb *bp = netdev_priv(dev);
246 struct phy_device *phydev = bp->phy_dev;
249 int status_change = 0;
251 spin_lock_irqsave(&bp->lock, flags);
254 if ((bp->speed != phydev->speed) ||
255 (bp->duplex != phydev->duplex)) {
258 reg = macb_readl(bp, NCFGR);
259 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
261 reg &= ~GEM_BIT(GBE);
265 if (phydev->speed == SPEED_100)
266 reg |= MACB_BIT(SPD);
267 if (phydev->speed == SPEED_1000)
270 macb_or_gem_writel(bp, NCFGR, reg);
272 bp->speed = phydev->speed;
273 bp->duplex = phydev->duplex;
278 if (phydev->link != bp->link) {
283 bp->link = phydev->link;
288 spin_unlock_irqrestore(&bp->lock, flags);
290 if (!IS_ERR(bp->tx_clk))
291 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
295 netif_carrier_on(dev);
296 netdev_info(dev, "link up (%d/%s)\n",
298 phydev->duplex == DUPLEX_FULL ?
301 netif_carrier_off(dev);
302 netdev_info(dev, "link down\n");
307 /* based on au1000_eth. c*/
308 static int macb_mii_probe(struct net_device *dev)
310 struct macb *bp = netdev_priv(dev);
311 struct macb_platform_data *pdata;
312 struct phy_device *phydev;
316 phydev = phy_find_first(bp->mii_bus);
318 netdev_err(dev, "no PHY found\n");
322 pdata = dev_get_platdata(&bp->pdev->dev);
323 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
324 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
326 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
327 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
331 /* attach the mac to the phy */
332 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
335 netdev_err(dev, "Could not attach to PHY\n");
339 /* mask with MAC supported features */
341 phydev->supported &= PHY_GBIT_FEATURES;
343 phydev->supported &= PHY_BASIC_FEATURES;
345 phydev->advertising = phydev->supported;
350 bp->phy_dev = phydev;
355 int macb_mii_init(struct macb *bp)
357 struct macb_platform_data *pdata;
358 struct device_node *np;
361 /* Enable management port */
362 macb_writel(bp, NCR, MACB_BIT(MPE));
364 bp->mii_bus = mdiobus_alloc();
365 if (bp->mii_bus == NULL) {
370 bp->mii_bus->name = "MACB_mii_bus";
371 bp->mii_bus->read = &macb_mdio_read;
372 bp->mii_bus->write = &macb_mdio_write;
373 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
374 bp->pdev->name, bp->pdev->id);
375 bp->mii_bus->priv = bp;
376 bp->mii_bus->parent = &bp->dev->dev;
377 pdata = dev_get_platdata(&bp->pdev->dev);
379 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
380 if (!bp->mii_bus->irq) {
382 goto err_out_free_mdiobus;
385 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
387 np = bp->pdev->dev.of_node;
389 /* try dt phy registration */
390 err = of_mdiobus_register(bp->mii_bus, np);
392 /* fallback to standard phy registration if no phy were
393 found during dt phy registration */
394 if (!err && !phy_find_first(bp->mii_bus)) {
395 for (i = 0; i < PHY_MAX_ADDR; i++) {
396 struct phy_device *phydev;
398 phydev = mdiobus_scan(bp->mii_bus, i);
399 if (IS_ERR(phydev)) {
400 err = PTR_ERR(phydev);
406 goto err_out_unregister_bus;
409 for (i = 0; i < PHY_MAX_ADDR; i++)
410 bp->mii_bus->irq[i] = PHY_POLL;
413 bp->mii_bus->phy_mask = pdata->phy_mask;
415 err = mdiobus_register(bp->mii_bus);
419 goto err_out_free_mdio_irq;
421 err = macb_mii_probe(bp->dev);
423 goto err_out_unregister_bus;
427 err_out_unregister_bus:
428 mdiobus_unregister(bp->mii_bus);
429 err_out_free_mdio_irq:
430 kfree(bp->mii_bus->irq);
431 err_out_free_mdiobus:
432 mdiobus_free(bp->mii_bus);
436 EXPORT_SYMBOL_GPL(macb_mii_init);
438 static void macb_update_stats(struct macb *bp)
440 u32 __iomem *reg = bp->regs + MACB_PFR;
441 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
442 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
444 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
446 for(; p < end; p++, reg++)
447 *p += __raw_readl(reg);
450 static int macb_halt_tx(struct macb *bp)
452 unsigned long halt_time, timeout;
455 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
457 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
460 status = macb_readl(bp, TSR);
461 if (!(status & MACB_BIT(TGO)))
464 usleep_range(10, 250);
465 } while (time_before(halt_time, timeout));
470 static void macb_tx_error_task(struct work_struct *work)
472 struct macb *bp = container_of(work, struct macb, tx_error_task);
473 struct macb_tx_skb *tx_skb;
477 netdev_vdbg(bp->dev, "macb_tx_error_task: t = %u, h = %u\n",
478 bp->tx_tail, bp->tx_head);
480 /* Make sure nobody is trying to queue up new packets */
481 netif_stop_queue(bp->dev);
484 * Stop transmission now
485 * (in case we have just queued new packets)
487 if (macb_halt_tx(bp))
488 /* Just complain for now, reinitializing TX path can be good */
489 netdev_err(bp->dev, "BUG: halt tx timed out\n");
491 /* No need for the lock here as nobody will interrupt us anymore */
494 * Treat frames in TX queue including the ones that caused the error.
495 * Free transmit buffers in upper layer.
497 for (tail = bp->tx_tail; tail != bp->tx_head; tail++) {
498 struct macb_dma_desc *desc;
501 desc = macb_tx_desc(bp, tail);
503 tx_skb = macb_tx_skb(bp, tail);
506 if (ctrl & MACB_BIT(TX_USED)) {
507 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
508 macb_tx_ring_wrap(tail), skb->data);
509 bp->stats.tx_packets++;
510 bp->stats.tx_bytes += skb->len;
513 * "Buffers exhausted mid-frame" errors may only happen
514 * if the driver is buggy, so complain loudly about those.
515 * Statistics are updated by hardware.
517 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
519 "BUG: TX buffers exhausted mid-frame\n");
521 desc->ctrl = ctrl | MACB_BIT(TX_USED);
524 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
530 /* Make descriptor updates visible to hardware */
533 /* Reinitialize the TX desc queue */
534 macb_writel(bp, TBQP, bp->tx_ring_dma);
535 /* Make TX ring reflect state of hardware */
536 bp->tx_head = bp->tx_tail = 0;
538 /* Now we are ready to start transmission again */
539 netif_wake_queue(bp->dev);
541 /* Housework before enabling TX IRQ */
542 macb_writel(bp, TSR, macb_readl(bp, TSR));
543 macb_writel(bp, IER, MACB_TX_INT_FLAGS);
546 static void macb_tx_interrupt(struct macb *bp)
552 status = macb_readl(bp, TSR);
553 macb_writel(bp, TSR, status);
555 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
556 macb_writel(bp, ISR, MACB_BIT(TCOMP));
558 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
559 (unsigned long)status);
562 for (tail = bp->tx_tail; tail != head; tail++) {
563 struct macb_tx_skb *tx_skb;
565 struct macb_dma_desc *desc;
568 desc = macb_tx_desc(bp, tail);
570 /* Make hw descriptor updates visible to CPU */
575 if (!(ctrl & MACB_BIT(TX_USED)))
578 tx_skb = macb_tx_skb(bp, tail);
581 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
582 macb_tx_ring_wrap(tail), skb->data);
583 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping, skb->len,
585 bp->stats.tx_packets++;
586 bp->stats.tx_bytes += skb->len;
588 dev_kfree_skb_irq(skb);
592 if (netif_queue_stopped(bp->dev)
593 && CIRC_CNT(bp->tx_head, bp->tx_tail,
594 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
595 netif_wake_queue(bp->dev);
598 static void gem_rx_refill(struct macb *bp)
602 struct macb_dma_desc *desc;
605 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
608 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
609 desc = &bp->rx_ring[entry];
611 /* Make hw descriptor updates visible to CPU */
616 bp->rx_prepared_head++;
618 if ((addr & MACB_BIT(RX_USED)))
621 if (bp->rx_skbuff[entry] == NULL) {
622 /* allocate sk_buff for this free entry in ring */
623 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
624 if (unlikely(skb == NULL)) {
626 "Unable to allocate sk_buff\n");
630 /* now fill corresponding descriptor entry */
631 paddr = dma_map_single(&bp->pdev->dev, skb->data,
632 bp->rx_buffer_size, DMA_FROM_DEVICE);
633 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
638 bp->rx_skbuff[entry] = skb;
640 if (entry == RX_RING_SIZE - 1)
641 paddr |= MACB_BIT(RX_WRAP);
642 bp->rx_ring[entry].addr = paddr;
643 bp->rx_ring[entry].ctrl = 0;
645 /* properly align Ethernet header */
646 skb_reserve(skb, NET_IP_ALIGN);
650 /* Make descriptor updates visible to hardware */
653 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
654 bp->rx_prepared_head, bp->rx_tail);
657 /* Mark DMA descriptors from begin up to and not including end as unused */
658 static void discard_partial_frame(struct macb *bp, unsigned int begin,
663 for (frag = begin; frag != end; frag++) {
664 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
665 desc->addr &= ~MACB_BIT(RX_USED);
668 /* Make descriptor updates visible to hardware */
672 * When this happens, the hardware stats registers for
673 * whatever caused this is updated, so we don't have to record
678 static int gem_rx(struct macb *bp, int budget)
683 struct macb_dma_desc *desc;
686 while (count < budget) {
689 entry = macb_rx_ring_wrap(bp->rx_tail);
690 desc = &bp->rx_ring[entry];
692 /* Make hw descriptor updates visible to CPU */
698 if (!(addr & MACB_BIT(RX_USED)))
701 desc->addr &= ~MACB_BIT(RX_USED);
705 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
707 "not whole frame pointed by descriptor\n");
708 bp->stats.rx_dropped++;
711 skb = bp->rx_skbuff[entry];
712 if (unlikely(!skb)) {
714 "inconsistent Rx descriptor chain\n");
715 bp->stats.rx_dropped++;
718 /* now everything is ready for receiving packet */
719 bp->rx_skbuff[entry] = NULL;
720 len = MACB_BFEXT(RX_FRMLEN, ctrl);
722 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
725 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
726 dma_unmap_single(&bp->pdev->dev, addr,
727 bp->rx_buffer_size, DMA_FROM_DEVICE);
729 skb->protocol = eth_type_trans(skb, bp->dev);
730 skb_checksum_none_assert(skb);
732 bp->stats.rx_packets++;
733 bp->stats.rx_bytes += skb->len;
735 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
736 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
737 skb->len, skb->csum);
738 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
739 skb->mac_header, 16, true);
740 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
741 skb->data, 32, true);
744 netif_receive_skb(skb);
752 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
753 unsigned int last_frag)
759 struct macb_dma_desc *desc;
761 desc = macb_rx_desc(bp, last_frag);
762 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
764 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
765 macb_rx_ring_wrap(first_frag),
766 macb_rx_ring_wrap(last_frag), len);
769 * The ethernet header starts NET_IP_ALIGN bytes into the
770 * first buffer. Since the header is 14 bytes, this makes the
771 * payload word-aligned.
773 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
774 * the two padding bytes into the skb so that we avoid hitting
775 * the slowpath in memcpy(), and pull them off afterwards.
777 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
779 bp->stats.rx_dropped++;
780 for (frag = first_frag; ; frag++) {
781 desc = macb_rx_desc(bp, frag);
782 desc->addr &= ~MACB_BIT(RX_USED);
783 if (frag == last_frag)
787 /* Make descriptor updates visible to hardware */
795 skb_checksum_none_assert(skb);
798 for (frag = first_frag; ; frag++) {
799 unsigned int frag_len = bp->rx_buffer_size;
801 if (offset + frag_len > len) {
802 BUG_ON(frag != last_frag);
803 frag_len = len - offset;
805 skb_copy_to_linear_data_offset(skb, offset,
806 macb_rx_buffer(bp, frag), frag_len);
807 offset += bp->rx_buffer_size;
808 desc = macb_rx_desc(bp, frag);
809 desc->addr &= ~MACB_BIT(RX_USED);
811 if (frag == last_frag)
815 /* Make descriptor updates visible to hardware */
818 __skb_pull(skb, NET_IP_ALIGN);
819 skb->protocol = eth_type_trans(skb, bp->dev);
821 bp->stats.rx_packets++;
822 bp->stats.rx_bytes += skb->len;
823 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
824 skb->len, skb->csum);
825 netif_receive_skb(skb);
830 static int macb_rx(struct macb *bp, int budget)
836 for (tail = bp->rx_tail; budget > 0; tail++) {
837 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
840 /* Make hw descriptor updates visible to CPU */
846 if (!(addr & MACB_BIT(RX_USED)))
849 if (ctrl & MACB_BIT(RX_SOF)) {
850 if (first_frag != -1)
851 discard_partial_frame(bp, first_frag, tail);
855 if (ctrl & MACB_BIT(RX_EOF)) {
857 BUG_ON(first_frag == -1);
859 dropped = macb_rx_frame(bp, first_frag, tail);
868 if (first_frag != -1)
869 bp->rx_tail = first_frag;
876 static int macb_poll(struct napi_struct *napi, int budget)
878 struct macb *bp = container_of(napi, struct macb, napi);
882 status = macb_readl(bp, RSR);
883 macb_writel(bp, RSR, status);
887 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
888 (unsigned long)status, budget);
890 work_done = bp->macbgem_ops.mog_rx(bp, budget);
891 if (work_done < budget) {
895 * We've done what we can to clean the buffers. Make sure we
896 * get notified when new packets arrive.
898 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
900 /* Packets received while interrupts were disabled */
901 status = macb_readl(bp, RSR);
902 if (unlikely(status))
903 napi_reschedule(napi);
906 /* TODO: Handle errors */
911 static irqreturn_t macb_interrupt(int irq, void *dev_id)
913 struct net_device *dev = dev_id;
914 struct macb *bp = netdev_priv(dev);
917 status = macb_readl(bp, ISR);
919 if (unlikely(!status))
922 spin_lock(&bp->lock);
925 /* close possible race with dev_close */
926 if (unlikely(!netif_running(dev))) {
927 macb_writel(bp, IDR, -1);
931 netdev_vdbg(bp->dev, "isr = 0x%08lx\n", (unsigned long)status);
933 if (status & MACB_RX_INT_FLAGS) {
935 * There's no point taking any more interrupts
936 * until we have processed the buffers. The
937 * scheduling call may fail if the poll routine
938 * is already scheduled, so disable interrupts
941 macb_writel(bp, IDR, MACB_RX_INT_FLAGS);
942 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
943 macb_writel(bp, ISR, MACB_BIT(RCOMP));
945 if (napi_schedule_prep(&bp->napi)) {
946 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
947 __napi_schedule(&bp->napi);
951 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
952 macb_writel(bp, IDR, MACB_TX_INT_FLAGS);
953 schedule_work(&bp->tx_error_task);
955 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
956 macb_writel(bp, ISR, MACB_TX_ERR_FLAGS);
961 if (status & MACB_BIT(TCOMP))
962 macb_tx_interrupt(bp);
965 * Link change detection isn't possible with RMII, so we'll
966 * add that if/when we get our hands on a full-blown MII PHY.
969 if (status & MACB_BIT(ISR_ROVR)) {
970 /* We missed at least one packet */
972 bp->hw_stats.gem.rx_overruns++;
974 bp->hw_stats.macb.rx_overruns++;
976 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
977 macb_writel(bp, ISR, MACB_BIT(ISR_ROVR));
980 if (status & MACB_BIT(HRESP)) {
982 * TODO: Reset the hardware, and maybe move the
983 * netdev_err to a lower-priority context as well
986 netdev_err(dev, "DMA bus error: HRESP not OK\n");
988 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
989 macb_writel(bp, ISR, MACB_BIT(HRESP));
992 status = macb_readl(bp, ISR);
995 spin_unlock(&bp->lock);
1000 #ifdef CONFIG_NET_POLL_CONTROLLER
1002 * Polling receive - used by netconsole and other diagnostic tools
1003 * to allow network i/o with interrupts disabled.
1005 static void macb_poll_controller(struct net_device *dev)
1007 unsigned long flags;
1009 local_irq_save(flags);
1010 macb_interrupt(dev->irq, dev);
1011 local_irq_restore(flags);
1015 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1017 struct macb *bp = netdev_priv(dev);
1019 unsigned int len, entry;
1020 struct macb_dma_desc *desc;
1021 struct macb_tx_skb *tx_skb;
1023 unsigned long flags;
1025 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1026 netdev_vdbg(bp->dev,
1027 "start_xmit: len %u head %p data %p tail %p end %p\n",
1028 skb->len, skb->head, skb->data,
1029 skb_tail_pointer(skb), skb_end_pointer(skb));
1030 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1031 skb->data, 16, true);
1035 spin_lock_irqsave(&bp->lock, flags);
1037 /* This is a hard error, log it. */
1038 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1) {
1039 netif_stop_queue(dev);
1040 spin_unlock_irqrestore(&bp->lock, flags);
1041 netdev_err(bp->dev, "BUG! Tx Ring full when queue awake!\n");
1042 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1043 bp->tx_head, bp->tx_tail);
1044 return NETDEV_TX_BUSY;
1047 entry = macb_tx_ring_wrap(bp->tx_head);
1048 netdev_vdbg(bp->dev, "Allocated ring entry %u\n", entry);
1049 mapping = dma_map_single(&bp->pdev->dev, skb->data,
1050 len, DMA_TO_DEVICE);
1051 if (dma_mapping_error(&bp->pdev->dev, mapping)) {
1052 dev_kfree_skb_any(skb);
1057 tx_skb = &bp->tx_skb[entry];
1059 tx_skb->mapping = mapping;
1060 netdev_vdbg(bp->dev, "Mapped skb data %p to DMA addr %08lx\n",
1061 skb->data, (unsigned long)mapping);
1063 ctrl = MACB_BF(TX_FRMLEN, len);
1064 ctrl |= MACB_BIT(TX_LAST);
1065 if (entry == (TX_RING_SIZE - 1))
1066 ctrl |= MACB_BIT(TX_WRAP);
1068 desc = &bp->tx_ring[entry];
1069 desc->addr = mapping;
1072 /* Make newly initialized descriptor visible to hardware */
1075 skb_tx_timestamp(skb);
1077 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1079 if (CIRC_SPACE(bp->tx_head, bp->tx_tail, TX_RING_SIZE) < 1)
1080 netif_stop_queue(dev);
1083 spin_unlock_irqrestore(&bp->lock, flags);
1085 return NETDEV_TX_OK;
1088 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1090 if (!macb_is_gem(bp)) {
1091 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1093 bp->rx_buffer_size = size;
1095 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1097 "RX buffer must be multiple of %d bytes, expanding\n",
1098 RX_BUFFER_MULTIPLE);
1099 bp->rx_buffer_size =
1100 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1104 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1105 bp->dev->mtu, bp->rx_buffer_size);
1108 static void gem_free_rx_buffers(struct macb *bp)
1110 struct sk_buff *skb;
1111 struct macb_dma_desc *desc;
1118 for (i = 0; i < RX_RING_SIZE; i++) {
1119 skb = bp->rx_skbuff[i];
1124 desc = &bp->rx_ring[i];
1125 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1126 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1128 dev_kfree_skb_any(skb);
1132 kfree(bp->rx_skbuff);
1133 bp->rx_skbuff = NULL;
1136 static void macb_free_rx_buffers(struct macb *bp)
1138 if (bp->rx_buffers) {
1139 dma_free_coherent(&bp->pdev->dev,
1140 RX_RING_SIZE * bp->rx_buffer_size,
1141 bp->rx_buffers, bp->rx_buffers_dma);
1142 bp->rx_buffers = NULL;
1146 static void macb_free_consistent(struct macb *bp)
1152 bp->macbgem_ops.mog_free_rx_buffers(bp);
1154 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1155 bp->rx_ring, bp->rx_ring_dma);
1159 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1160 bp->tx_ring, bp->tx_ring_dma);
1165 static int gem_alloc_rx_buffers(struct macb *bp)
1169 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1170 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1175 "Allocated %d RX struct sk_buff entries at %p\n",
1176 RX_RING_SIZE, bp->rx_skbuff);
1180 static int macb_alloc_rx_buffers(struct macb *bp)
1184 size = RX_RING_SIZE * bp->rx_buffer_size;
1185 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1186 &bp->rx_buffers_dma, GFP_KERNEL);
1187 if (!bp->rx_buffers)
1191 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1192 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1196 static int macb_alloc_consistent(struct macb *bp)
1200 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1201 bp->tx_skb = kmalloc(size, GFP_KERNEL);
1205 size = RX_RING_BYTES;
1206 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1207 &bp->rx_ring_dma, GFP_KERNEL);
1211 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1212 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1214 size = TX_RING_BYTES;
1215 bp->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1216 &bp->tx_ring_dma, GFP_KERNEL);
1220 "Allocated TX ring of %d bytes at %08lx (mapped %p)\n",
1221 size, (unsigned long)bp->tx_ring_dma, bp->tx_ring);
1223 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1229 macb_free_consistent(bp);
1233 static void gem_init_rings(struct macb *bp)
1237 for (i = 0; i < TX_RING_SIZE; i++) {
1238 bp->tx_ring[i].addr = 0;
1239 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1241 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1243 bp->rx_tail = bp->rx_prepared_head = bp->tx_head = bp->tx_tail = 0;
1248 static void macb_init_rings(struct macb *bp)
1253 addr = bp->rx_buffers_dma;
1254 for (i = 0; i < RX_RING_SIZE; i++) {
1255 bp->rx_ring[i].addr = addr;
1256 bp->rx_ring[i].ctrl = 0;
1257 addr += bp->rx_buffer_size;
1259 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1261 for (i = 0; i < TX_RING_SIZE; i++) {
1262 bp->tx_ring[i].addr = 0;
1263 bp->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1265 bp->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1267 bp->rx_tail = bp->tx_head = bp->tx_tail = 0;
1270 static void macb_reset_hw(struct macb *bp)
1273 * Disable RX and TX (XXX: Should we halt the transmission
1276 macb_writel(bp, NCR, 0);
1278 /* Clear the stats registers (XXX: Update stats first?) */
1279 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1281 /* Clear all status flags */
1282 macb_writel(bp, TSR, -1);
1283 macb_writel(bp, RSR, -1);
1285 /* Disable all interrupts */
1286 macb_writel(bp, IDR, -1);
1287 macb_readl(bp, ISR);
1290 static u32 gem_mdc_clk_div(struct macb *bp)
1293 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1295 if (pclk_hz <= 20000000)
1296 config = GEM_BF(CLK, GEM_CLK_DIV8);
1297 else if (pclk_hz <= 40000000)
1298 config = GEM_BF(CLK, GEM_CLK_DIV16);
1299 else if (pclk_hz <= 80000000)
1300 config = GEM_BF(CLK, GEM_CLK_DIV32);
1301 else if (pclk_hz <= 120000000)
1302 config = GEM_BF(CLK, GEM_CLK_DIV48);
1303 else if (pclk_hz <= 160000000)
1304 config = GEM_BF(CLK, GEM_CLK_DIV64);
1306 config = GEM_BF(CLK, GEM_CLK_DIV96);
1311 static u32 macb_mdc_clk_div(struct macb *bp)
1314 unsigned long pclk_hz;
1316 if (macb_is_gem(bp))
1317 return gem_mdc_clk_div(bp);
1319 pclk_hz = clk_get_rate(bp->pclk);
1320 if (pclk_hz <= 20000000)
1321 config = MACB_BF(CLK, MACB_CLK_DIV8);
1322 else if (pclk_hz <= 40000000)
1323 config = MACB_BF(CLK, MACB_CLK_DIV16);
1324 else if (pclk_hz <= 80000000)
1325 config = MACB_BF(CLK, MACB_CLK_DIV32);
1327 config = MACB_BF(CLK, MACB_CLK_DIV64);
1333 * Get the DMA bus width field of the network configuration register that we
1334 * should program. We find the width from decoding the design configuration
1335 * register to find the maximum supported data bus width.
1337 static u32 macb_dbw(struct macb *bp)
1339 if (!macb_is_gem(bp))
1342 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1344 return GEM_BF(DBW, GEM_DBW128);
1346 return GEM_BF(DBW, GEM_DBW64);
1349 return GEM_BF(DBW, GEM_DBW32);
1354 * Configure the receive DMA engine
1355 * - use the correct receive buffer size
1356 * - set the possibility to use INCR16 bursts
1357 * (if not supported by FIFO, it will fallback to default)
1358 * - set both rx/tx packet buffers to full memory size
1359 * These are configurable parameters for GEM.
1361 static void macb_configure_dma(struct macb *bp)
1365 if (macb_is_gem(bp)) {
1366 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1367 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1368 dmacfg |= GEM_BF(FBLDO, 16);
1369 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1370 dmacfg &= ~GEM_BIT(ENDIA);
1371 gem_writel(bp, DMACFG, dmacfg);
1376 * Configure peripheral capacities according to integration options used
1378 static void macb_configure_caps(struct macb *bp)
1380 if (macb_is_gem(bp)) {
1381 if (GEM_BFEXT(IRQCOR, gem_readl(bp, DCFG1)) == 0)
1382 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
1386 static void macb_init_hw(struct macb *bp)
1391 macb_set_hwaddr(bp);
1393 config = macb_mdc_clk_div(bp);
1394 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1395 config |= MACB_BIT(PAE); /* PAuse Enable */
1396 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1397 config |= MACB_BIT(BIG); /* Receive oversized frames */
1398 if (bp->dev->flags & IFF_PROMISC)
1399 config |= MACB_BIT(CAF); /* Copy All Frames */
1400 if (!(bp->dev->flags & IFF_BROADCAST))
1401 config |= MACB_BIT(NBC); /* No BroadCast */
1402 config |= macb_dbw(bp);
1403 macb_writel(bp, NCFGR, config);
1404 bp->speed = SPEED_10;
1405 bp->duplex = DUPLEX_HALF;
1407 macb_configure_dma(bp);
1408 macb_configure_caps(bp);
1410 /* Initialize TX and RX buffers */
1411 macb_writel(bp, RBQP, bp->rx_ring_dma);
1412 macb_writel(bp, TBQP, bp->tx_ring_dma);
1414 /* Enable TX and RX */
1415 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1417 /* Enable interrupts */
1418 macb_writel(bp, IER, (MACB_RX_INT_FLAGS
1420 | MACB_BIT(HRESP)));
1425 * The hash address register is 64 bits long and takes up two
1426 * locations in the memory map. The least significant bits are stored
1427 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1429 * The unicast hash enable and the multicast hash enable bits in the
1430 * network configuration register enable the reception of hash matched
1431 * frames. The destination address is reduced to a 6 bit index into
1432 * the 64 bit hash register using the following hash function. The
1433 * hash function is an exclusive or of every sixth bit of the
1434 * destination address.
1436 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1437 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1438 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1439 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1440 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1441 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1443 * da[0] represents the least significant bit of the first byte
1444 * received, that is, the multicast/unicast indicator, and da[47]
1445 * represents the most significant bit of the last byte received. If
1446 * the hash index, hi[n], points to a bit that is set in the hash
1447 * register then the frame will be matched according to whether the
1448 * frame is multicast or unicast. A multicast match will be signalled
1449 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1450 * index points to a bit set in the hash register. A unicast match
1451 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1452 * and the hash index points to a bit set in the hash register. To
1453 * receive all multicast frames, the hash register should be set with
1454 * all ones and the multicast hash enable bit should be set in the
1455 * network configuration register.
1458 static inline int hash_bit_value(int bitnr, __u8 *addr)
1460 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1466 * Return the hash index value for the specified address.
1468 static int hash_get_index(__u8 *addr)
1473 for (j = 0; j < 6; j++) {
1474 for (i = 0, bitval = 0; i < 8; i++)
1475 bitval ^= hash_bit_value(i*6 + j, addr);
1477 hash_index |= (bitval << j);
1484 * Add multicast addresses to the internal multicast-hash table.
1486 static void macb_sethashtable(struct net_device *dev)
1488 struct netdev_hw_addr *ha;
1489 unsigned long mc_filter[2];
1491 struct macb *bp = netdev_priv(dev);
1493 mc_filter[0] = mc_filter[1] = 0;
1495 netdev_for_each_mc_addr(ha, dev) {
1496 bitnr = hash_get_index(ha->addr);
1497 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1500 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1501 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1505 * Enable/Disable promiscuous and multicast modes.
1507 void macb_set_rx_mode(struct net_device *dev)
1510 struct macb *bp = netdev_priv(dev);
1512 cfg = macb_readl(bp, NCFGR);
1514 if (dev->flags & IFF_PROMISC)
1515 /* Enable promiscuous mode */
1516 cfg |= MACB_BIT(CAF);
1517 else if (dev->flags & (~IFF_PROMISC))
1518 /* Disable promiscuous mode */
1519 cfg &= ~MACB_BIT(CAF);
1521 if (dev->flags & IFF_ALLMULTI) {
1522 /* Enable all multicast mode */
1523 macb_or_gem_writel(bp, HRB, -1);
1524 macb_or_gem_writel(bp, HRT, -1);
1525 cfg |= MACB_BIT(NCFGR_MTI);
1526 } else if (!netdev_mc_empty(dev)) {
1527 /* Enable specific multicasts */
1528 macb_sethashtable(dev);
1529 cfg |= MACB_BIT(NCFGR_MTI);
1530 } else if (dev->flags & (~IFF_ALLMULTI)) {
1531 /* Disable all multicast mode */
1532 macb_or_gem_writel(bp, HRB, 0);
1533 macb_or_gem_writel(bp, HRT, 0);
1534 cfg &= ~MACB_BIT(NCFGR_MTI);
1537 macb_writel(bp, NCFGR, cfg);
1539 EXPORT_SYMBOL_GPL(macb_set_rx_mode);
1541 static int macb_open(struct net_device *dev)
1543 struct macb *bp = netdev_priv(dev);
1544 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1547 netdev_dbg(bp->dev, "open\n");
1549 /* carrier starts down */
1550 netif_carrier_off(dev);
1552 /* if the phy is not yet register, retry later*/
1556 /* RX buffers initialization */
1557 macb_init_rx_buffer_size(bp, bufsz);
1559 err = macb_alloc_consistent(bp);
1561 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1566 napi_enable(&bp->napi);
1568 bp->macbgem_ops.mog_init_rings(bp);
1571 /* schedule a link state check */
1572 phy_start(bp->phy_dev);
1574 netif_start_queue(dev);
1579 static int macb_close(struct net_device *dev)
1581 struct macb *bp = netdev_priv(dev);
1582 unsigned long flags;
1584 netif_stop_queue(dev);
1585 napi_disable(&bp->napi);
1588 phy_stop(bp->phy_dev);
1590 spin_lock_irqsave(&bp->lock, flags);
1592 netif_carrier_off(dev);
1593 spin_unlock_irqrestore(&bp->lock, flags);
1595 macb_free_consistent(bp);
1600 static void gem_update_stats(struct macb *bp)
1602 u32 __iomem *reg = bp->regs + GEM_OTX;
1603 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1604 u32 *end = &bp->hw_stats.gem.rx_udp_checksum_errors + 1;
1606 for (; p < end; p++, reg++)
1607 *p += __raw_readl(reg);
1610 static struct net_device_stats *gem_get_stats(struct macb *bp)
1612 struct gem_stats *hwstat = &bp->hw_stats.gem;
1613 struct net_device_stats *nstat = &bp->stats;
1615 gem_update_stats(bp);
1617 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1618 hwstat->rx_alignment_errors +
1619 hwstat->rx_resource_errors +
1620 hwstat->rx_overruns +
1621 hwstat->rx_oversize_frames +
1622 hwstat->rx_jabbers +
1623 hwstat->rx_undersized_frames +
1624 hwstat->rx_length_field_frame_errors);
1625 nstat->tx_errors = (hwstat->tx_late_collisions +
1626 hwstat->tx_excessive_collisions +
1627 hwstat->tx_underrun +
1628 hwstat->tx_carrier_sense_errors);
1629 nstat->multicast = hwstat->rx_multicast_frames;
1630 nstat->collisions = (hwstat->tx_single_collision_frames +
1631 hwstat->tx_multiple_collision_frames +
1632 hwstat->tx_excessive_collisions);
1633 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1634 hwstat->rx_jabbers +
1635 hwstat->rx_undersized_frames +
1636 hwstat->rx_length_field_frame_errors);
1637 nstat->rx_over_errors = hwstat->rx_resource_errors;
1638 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1639 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1640 nstat->rx_fifo_errors = hwstat->rx_overruns;
1641 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1642 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1643 nstat->tx_fifo_errors = hwstat->tx_underrun;
1648 struct net_device_stats *macb_get_stats(struct net_device *dev)
1650 struct macb *bp = netdev_priv(dev);
1651 struct net_device_stats *nstat = &bp->stats;
1652 struct macb_stats *hwstat = &bp->hw_stats.macb;
1654 if (macb_is_gem(bp))
1655 return gem_get_stats(bp);
1657 /* read stats from hardware */
1658 macb_update_stats(bp);
1660 /* Convert HW stats into netdevice stats */
1661 nstat->rx_errors = (hwstat->rx_fcs_errors +
1662 hwstat->rx_align_errors +
1663 hwstat->rx_resource_errors +
1664 hwstat->rx_overruns +
1665 hwstat->rx_oversize_pkts +
1666 hwstat->rx_jabbers +
1667 hwstat->rx_undersize_pkts +
1668 hwstat->sqe_test_errors +
1669 hwstat->rx_length_mismatch);
1670 nstat->tx_errors = (hwstat->tx_late_cols +
1671 hwstat->tx_excessive_cols +
1672 hwstat->tx_underruns +
1673 hwstat->tx_carrier_errors);
1674 nstat->collisions = (hwstat->tx_single_cols +
1675 hwstat->tx_multiple_cols +
1676 hwstat->tx_excessive_cols);
1677 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1678 hwstat->rx_jabbers +
1679 hwstat->rx_undersize_pkts +
1680 hwstat->rx_length_mismatch);
1681 nstat->rx_over_errors = hwstat->rx_resource_errors +
1682 hwstat->rx_overruns;
1683 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1684 nstat->rx_frame_errors = hwstat->rx_align_errors;
1685 nstat->rx_fifo_errors = hwstat->rx_overruns;
1686 /* XXX: What does "missed" mean? */
1687 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1688 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1689 nstat->tx_fifo_errors = hwstat->tx_underruns;
1690 /* Don't know about heartbeat or window errors... */
1694 EXPORT_SYMBOL_GPL(macb_get_stats);
1696 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1698 struct macb *bp = netdev_priv(dev);
1699 struct phy_device *phydev = bp->phy_dev;
1704 return phy_ethtool_gset(phydev, cmd);
1707 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1709 struct macb *bp = netdev_priv(dev);
1710 struct phy_device *phydev = bp->phy_dev;
1715 return phy_ethtool_sset(phydev, cmd);
1718 static int macb_get_regs_len(struct net_device *netdev)
1720 return MACB_GREGS_NBR * sizeof(u32);
1723 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1726 struct macb *bp = netdev_priv(dev);
1727 unsigned int tail, head;
1730 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
1731 | MACB_GREGS_VERSION;
1733 tail = macb_tx_ring_wrap(bp->tx_tail);
1734 head = macb_tx_ring_wrap(bp->tx_head);
1736 regs_buff[0] = macb_readl(bp, NCR);
1737 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
1738 regs_buff[2] = macb_readl(bp, NSR);
1739 regs_buff[3] = macb_readl(bp, TSR);
1740 regs_buff[4] = macb_readl(bp, RBQP);
1741 regs_buff[5] = macb_readl(bp, TBQP);
1742 regs_buff[6] = macb_readl(bp, RSR);
1743 regs_buff[7] = macb_readl(bp, IMR);
1745 regs_buff[8] = tail;
1746 regs_buff[9] = head;
1747 regs_buff[10] = macb_tx_dma(bp, tail);
1748 regs_buff[11] = macb_tx_dma(bp, head);
1750 if (macb_is_gem(bp)) {
1751 regs_buff[12] = gem_readl(bp, USRIO);
1752 regs_buff[13] = gem_readl(bp, DMACFG);
1756 const struct ethtool_ops macb_ethtool_ops = {
1757 .get_settings = macb_get_settings,
1758 .set_settings = macb_set_settings,
1759 .get_regs_len = macb_get_regs_len,
1760 .get_regs = macb_get_regs,
1761 .get_link = ethtool_op_get_link,
1762 .get_ts_info = ethtool_op_get_ts_info,
1764 EXPORT_SYMBOL_GPL(macb_ethtool_ops);
1766 int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1768 struct macb *bp = netdev_priv(dev);
1769 struct phy_device *phydev = bp->phy_dev;
1771 if (!netif_running(dev))
1777 return phy_mii_ioctl(phydev, rq, cmd);
1779 EXPORT_SYMBOL_GPL(macb_ioctl);
1781 static const struct net_device_ops macb_netdev_ops = {
1782 .ndo_open = macb_open,
1783 .ndo_stop = macb_close,
1784 .ndo_start_xmit = macb_start_xmit,
1785 .ndo_set_rx_mode = macb_set_rx_mode,
1786 .ndo_get_stats = macb_get_stats,
1787 .ndo_do_ioctl = macb_ioctl,
1788 .ndo_validate_addr = eth_validate_addr,
1789 .ndo_change_mtu = eth_change_mtu,
1790 .ndo_set_mac_address = eth_mac_addr,
1791 #ifdef CONFIG_NET_POLL_CONTROLLER
1792 .ndo_poll_controller = macb_poll_controller,
1796 #if defined(CONFIG_OF)
1797 static const struct of_device_id macb_dt_ids[] = {
1798 { .compatible = "cdns,at32ap7000-macb" },
1799 { .compatible = "cdns,at91sam9260-macb" },
1800 { .compatible = "cdns,macb" },
1801 { .compatible = "cdns,pc302-gem" },
1802 { .compatible = "cdns,gem" },
1805 MODULE_DEVICE_TABLE(of, macb_dt_ids);
1808 static int __init macb_probe(struct platform_device *pdev)
1810 struct macb_platform_data *pdata;
1811 struct resource *regs;
1812 struct net_device *dev;
1814 struct phy_device *phydev;
1817 struct pinctrl *pinctrl;
1820 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1822 dev_err(&pdev->dev, "no mmio resource defined\n");
1826 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1827 if (IS_ERR(pinctrl)) {
1828 err = PTR_ERR(pinctrl);
1829 if (err == -EPROBE_DEFER)
1832 dev_warn(&pdev->dev, "No pinctrl provided\n");
1836 dev = alloc_etherdev(sizeof(*bp));
1840 SET_NETDEV_DEV(dev, &pdev->dev);
1842 /* TODO: Actually, we have some interesting features... */
1845 bp = netdev_priv(dev);
1849 spin_lock_init(&bp->lock);
1850 INIT_WORK(&bp->tx_error_task, macb_tx_error_task);
1852 bp->pclk = devm_clk_get(&pdev->dev, "pclk");
1853 if (IS_ERR(bp->pclk)) {
1854 err = PTR_ERR(bp->pclk);
1855 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
1856 goto err_out_free_dev;
1859 bp->hclk = devm_clk_get(&pdev->dev, "hclk");
1860 if (IS_ERR(bp->hclk)) {
1861 err = PTR_ERR(bp->hclk);
1862 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
1863 goto err_out_free_dev;
1866 bp->tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
1868 err = clk_prepare_enable(bp->pclk);
1870 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
1871 goto err_out_free_dev;
1874 err = clk_prepare_enable(bp->hclk);
1876 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
1877 goto err_out_disable_pclk;
1880 if (!IS_ERR(bp->tx_clk)) {
1881 err = clk_prepare_enable(bp->tx_clk);
1883 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n",
1885 goto err_out_disable_hclk;
1889 bp->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
1891 dev_err(&pdev->dev, "failed to map registers, aborting.\n");
1893 goto err_out_disable_clocks;
1896 dev->irq = platform_get_irq(pdev, 0);
1897 err = devm_request_irq(&pdev->dev, dev->irq, macb_interrupt, 0,
1900 dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n",
1902 goto err_out_disable_clocks;
1905 dev->netdev_ops = &macb_netdev_ops;
1906 netif_napi_add(dev, &bp->napi, macb_poll, 64);
1907 dev->ethtool_ops = &macb_ethtool_ops;
1909 dev->base_addr = regs->start;
1911 /* setup appropriated routines according to adapter type */
1912 if (macb_is_gem(bp)) {
1913 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
1914 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
1915 bp->macbgem_ops.mog_init_rings = gem_init_rings;
1916 bp->macbgem_ops.mog_rx = gem_rx;
1918 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
1919 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
1920 bp->macbgem_ops.mog_init_rings = macb_init_rings;
1921 bp->macbgem_ops.mog_rx = macb_rx;
1924 /* Set MII management clock divider */
1925 config = macb_mdc_clk_div(bp);
1926 config |= macb_dbw(bp);
1927 macb_writel(bp, NCFGR, config);
1929 mac = of_get_mac_address(pdev->dev.of_node);
1931 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
1933 macb_get_hwaddr(bp);
1935 err = of_get_phy_mode(pdev->dev.of_node);
1937 pdata = dev_get_platdata(&pdev->dev);
1938 if (pdata && pdata->is_rmii)
1939 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
1941 bp->phy_interface = PHY_INTERFACE_MODE_MII;
1943 bp->phy_interface = err;
1946 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
1947 macb_or_gem_writel(bp, USRIO, GEM_BIT(RGMII));
1948 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
1949 #if defined(CONFIG_ARCH_AT91)
1950 macb_or_gem_writel(bp, USRIO, (MACB_BIT(RMII) |
1953 macb_or_gem_writel(bp, USRIO, 0);
1956 #if defined(CONFIG_ARCH_AT91)
1957 macb_or_gem_writel(bp, USRIO, MACB_BIT(CLKEN));
1959 macb_or_gem_writel(bp, USRIO, MACB_BIT(MII));
1962 err = register_netdev(dev);
1964 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
1965 goto err_out_disable_clocks;
1968 err = macb_mii_init(bp);
1970 goto err_out_unregister_netdev;
1972 platform_set_drvdata(pdev, dev);
1974 netif_carrier_off(dev);
1976 netdev_info(dev, "Cadence %s at 0x%08lx irq %d (%pM)\n",
1977 macb_is_gem(bp) ? "GEM" : "MACB", dev->base_addr,
1978 dev->irq, dev->dev_addr);
1980 phydev = bp->phy_dev;
1981 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1982 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
1986 err_out_unregister_netdev:
1987 unregister_netdev(dev);
1988 err_out_disable_clocks:
1989 if (!IS_ERR(bp->tx_clk))
1990 clk_disable_unprepare(bp->tx_clk);
1991 err_out_disable_hclk:
1992 clk_disable_unprepare(bp->hclk);
1993 err_out_disable_pclk:
1994 clk_disable_unprepare(bp->pclk);
2001 static int __exit macb_remove(struct platform_device *pdev)
2003 struct net_device *dev;
2006 dev = platform_get_drvdata(pdev);
2009 bp = netdev_priv(dev);
2011 phy_disconnect(bp->phy_dev);
2012 mdiobus_unregister(bp->mii_bus);
2013 kfree(bp->mii_bus->irq);
2014 mdiobus_free(bp->mii_bus);
2015 unregister_netdev(dev);
2016 if (!IS_ERR(bp->tx_clk))
2017 clk_disable_unprepare(bp->tx_clk);
2018 clk_disable_unprepare(bp->hclk);
2019 clk_disable_unprepare(bp->pclk);
2027 static int macb_suspend(struct device *dev)
2029 struct platform_device *pdev = to_platform_device(dev);
2030 struct net_device *netdev = platform_get_drvdata(pdev);
2031 struct macb *bp = netdev_priv(netdev);
2033 netif_carrier_off(netdev);
2034 netif_device_detach(netdev);
2036 if (!IS_ERR(bp->tx_clk))
2037 clk_disable_unprepare(bp->tx_clk);
2038 clk_disable_unprepare(bp->hclk);
2039 clk_disable_unprepare(bp->pclk);
2044 static int macb_resume(struct device *dev)
2046 struct platform_device *pdev = to_platform_device(dev);
2047 struct net_device *netdev = platform_get_drvdata(pdev);
2048 struct macb *bp = netdev_priv(netdev);
2050 clk_prepare_enable(bp->pclk);
2051 clk_prepare_enable(bp->hclk);
2052 if (!IS_ERR(bp->tx_clk))
2053 clk_prepare_enable(bp->tx_clk);
2055 netif_device_attach(netdev);
2061 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2063 static struct platform_driver macb_driver = {
2064 .remove = __exit_p(macb_remove),
2067 .owner = THIS_MODULE,
2068 .of_match_table = of_match_ptr(macb_dt_ids),
2073 module_platform_driver_probe(macb_driver, macb_probe);
2075 MODULE_LICENSE("GPL");
2076 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2077 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2078 MODULE_ALIAS("platform:macb");