2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2014 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 137
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "May 11, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static const struct pci_device_id tg3_pci_tbl[] = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static void tg3_mdio_config_5785(struct tg3 *tp)
1407 struct phy_device *phydev;
1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
1413 val = MAC_PHYCFG2_50610_LED_MODES;
1415 case PHY_ID_BCMAC131:
1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1418 case PHY_ID_RTL8211C:
1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1421 case PHY_ID_RTL8201E:
1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1431 val = tr32(MAC_PHYCFG1);
1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1435 tw32(MAC_PHYCFG1, val);
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1448 tw32(MAC_PHYCFG2, val);
1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1482 tw32(MAC_EXT_RGMII_MODE, val);
1485 static void tg3_mdio_start(struct tg3 *tp)
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
1492 tg3_asic_rev(tp) == ASIC_REV_5785)
1493 tg3_mdio_config_5785(tp);
1496 static int tg3_mdio_init(struct tg3 *tp)
1500 struct phy_device *phydev;
1502 if (tg3_flag(tp, 5717_PLUS)) {
1505 tp->phy_addr = tp->pci_fn + 1;
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1520 tp->phy_addr = addr;
1522 tp->phy_addr = TG3_PHY_MII_ADDR;
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
1544 tp->mdio_bus->irq[i] = PHY_POLL;
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1551 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1554 i = mdiobus_register(tp->mdio_bus);
1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1557 mdiobus_free(tp->mdio_bus);
1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1563 if (!phydev || !phydev->drv) {
1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1571 case PHY_ID_BCM57780:
1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1578 PHY_BRCM_RX_REFCLK_UNUSED |
1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1588 case PHY_ID_RTL8211C:
1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
1593 phydev->interface = PHY_INTERFACE_MODE_MII;
1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1599 tg3_flag_set(tp, MDIOBUS_INITED);
1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1602 tg3_mdio_config_5785(tp);
1607 static void tg3_mdio_fini(struct tg3 *tp)
1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
1616 /* tp->lock is held. */
1617 static inline void tg3_generate_fw_event(struct tg3 *tp)
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1625 tp->last_event_jiffies = jiffies;
1628 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1630 /* tp->lock is held. */
1631 static void tg3_wait_for_event_ack(struct tg3 *tp)
1634 unsigned int delay_cnt;
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1641 if (time_remain < 0)
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
1650 for (i = 0; i < delay_cnt; i++) {
1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1653 if (pci_channel_offline(tp->pdev))
1660 /* tp->lock is held. */
1661 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1666 if (!tg3_readphy(tp, MII_BMCR, ®))
1668 if (!tg3_readphy(tp, MII_BMSR, ®))
1669 val |= (reg & 0xffff);
1673 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1675 if (!tg3_readphy(tp, MII_LPA, ®))
1676 val |= (reg & 0xffff);
1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1681 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1683 if (!tg3_readphy(tp, MII_STAT1000, ®))
1684 val |= (reg & 0xffff);
1688 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1695 /* tp->lock is held. */
1696 static void tg3_ump_link_report(struct tg3 *tp)
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1703 tg3_phy_gather_ump_data(tp, data);
1705 tg3_wait_for_event_ack(tp);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1714 tg3_generate_fw_event(tp);
1717 /* tp->lock is held. */
1718 static void tg3_stop_fw(struct tg3 *tp)
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1726 tg3_generate_fw_event(tp);
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1733 /* tp->lock is held. */
1734 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1762 /* tp->lock is held. */
1763 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1783 /* tp->lock is held. */
1784 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1809 static int tg3_poll_fw(struct tg3 *tp)
1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1827 if (pci_channel_offline(tp->pdev))
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1860 netdev_info(tp->dev, "No firmware running\n");
1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1873 static void tg3_link_report(struct tg3 *tp)
1875 if (!netif_carrier_ok(tp->dev)) {
1876 netif_info(tp, link, tp->dev, "Link is down\n");
1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1882 (tp->link_config.active_speed == SPEED_100 ?
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1897 tg3_ump_link_report(tp);
1900 tp->link_up = netif_carrier_ok(tp->dev);
1903 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1917 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1922 miireg = ADVERTISE_1000XPAUSE;
1923 else if (flow_ctrl & FLOW_CTRL_TX)
1924 miireg = ADVERTISE_1000XPSE_ASYM;
1925 else if (flow_ctrl & FLOW_CTRL_RX)
1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1947 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
1963 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1970 if (tg3_flag(tp, USE_PHYLIB))
1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1973 autoneg = tp->link_config.autoneg;
1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1981 flowctrl = tp->link_config.flowctrl;
1983 tp->link_config.active_flowctrl = flowctrl;
1985 if (flowctrl & FLOW_CTRL_RX)
1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1990 if (old_rx_mode != tp->rx_mode)
1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
1993 if (flowctrl & FLOW_CTRL_TX)
1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1998 if (old_tx_mode != tp->tx_mode)
1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
2002 static void tg3_adjust_link(struct net_device *dev)
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2009 spin_lock_bh(&tp->lock);
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2014 oldflowctrl = tp->link_config.active_flowctrl;
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
2022 else if (phydev->speed == SPEED_1000 ||
2023 tg3_asic_rev(tp) != ASIC_REV_5785)
2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2031 lcl_adv = mii_advertise_flowctrl(
2032 tp->link_config.flowctrl);
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2051 if (phydev->speed == SPEED_10)
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 if (phydev->link != tp->old_link ||
2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
2076 tp->old_link = phydev->link;
2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2080 spin_unlock_bh(&tp->lock);
2083 tg3_link_report(tp);
2086 static int tg3_phy_init(struct tg3 *tp)
2088 struct phy_device *phydev;
2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2093 /* Bring the PHY back to a known state. */
2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2098 /* Attach the MAC to the PHY. */
2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
2101 if (IS_ERR(phydev)) {
2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2103 return PTR_ERR(phydev);
2106 /* Mask with MAC supported features. */
2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2111 phydev->supported &= (PHY_GBIT_FEATURES |
2113 SUPPORTED_Asym_Pause);
2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2120 SUPPORTED_Asym_Pause);
2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129 phydev->advertising = phydev->supported;
2134 static void tg3_phy_start(struct tg3 *tp)
2136 struct phy_device *phydev;
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
2153 phy_start_aneg(phydev);
2156 static void tg3_phy_stop(struct tg3 *tp)
2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2164 static void tg3_phy_fini(struct tg3 *tp)
2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2172 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2202 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2222 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2232 tg3_phy_fet_toggle_apd(tp, enable);
2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2253 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2257 if (!tg3_flag(tp, 5705_PLUS) ||
2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2294 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2308 static void tg3_phy_apply_otp(struct tg3 *tp)
2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
2345 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2348 struct ethtool_eee *dest = &tp->eee;
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2364 dest->eee_active = 0;
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2385 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
2413 if (!tp->setlpicnt) {
2414 if (current_link_up &&
2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2425 static void tg3_phy_eee_enable(struct tg3 *tp)
2429 if (tp->link_config.active_speed == SPEED_1000 &&
2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2432 tg3_flag(tp, 57765_CLASS)) &&
2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2444 static int tg3_wait_macro_done(struct tg3 *tp)
2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2452 if ((tmp32 & 0x1000) == 0)
2462 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2472 for (chan = 0; chan < 4; chan++) {
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2484 if (tg3_wait_macro_done(tp)) {
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2492 if (tg3_wait_macro_done(tp)) {
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2498 if (tg3_wait_macro_done(tp)) {
2503 for (i = 0; i < 6; i += 2) {
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2528 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2532 for (chan = 0; chan < 4; chan++) {
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2541 if (tg3_wait_macro_done(tp))
2548 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2557 err = tg3_bmcr_reset(tp);
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
2572 BMCR_FULLDPLX | BMCR_SPEED1000);
2574 /* Set to master mode. */
2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2585 /* Block the PHY control access. */
2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2591 } while (--retries);
2593 err = tg3_phy_reset_chanpat(tp);
2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2616 static void tg3_carrier_off(struct tg3 *tp)
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2622 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2629 /* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2632 static int tg3_phy_reset(struct tg3 *tp)
2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
2647 if (netif_running(tp->dev) && tp->link_up) {
2648 netif_carrier_off(tp->dev);
2649 tg3_link_report(tp);
2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
2655 err = tg3_phy_reset_5703_4_5(tp);
2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2670 err = tg3_bmcr_reset(tp);
2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2692 if (tg3_flag(tp, 5717_PLUS) &&
2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2696 tg3_phy_apply_otp(tp);
2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2699 tg3_phy_toggle_apd(tp, true);
2701 tg3_phy_toggle_apd(tp, false);
2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2740 /* Cannot do read-modify-write on 5401 */
2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2743 /* Set bit 14 with read-modify-write to preserve other bits */
2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2761 /* adjust output voltage */
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2768 tg3_phy_toggle_automdix(tp, true);
2769 tg3_phy_set_wirespeed(tp);
2773 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2783 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2789 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2812 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2814 if (!tg3_flag(tp, IS_NIC))
2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2837 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2841 if (!tg3_flag(tp, IS_NIC) ||
2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2863 if (!tg3_flag(tp, IS_NIC))
2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896 u32 grc_local_ctrl = 0;
2898 /* Workaround to prevent overdrawing Amps. */
2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2938 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2949 msg = tg3_set_function_status(tp, msg);
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2957 tg3_pwrsrc_die_with_vmain(tp);
2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2963 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2965 bool need_vaux = false;
2967 /* The GPIOs do something completely different on 57765. */
2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2980 struct net_device *dev_peer;
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
2984 /* remove_one() may have been run on the peer. */
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2992 tg3_flag(tp_peer, ENABLE_ASF))
2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
3002 tg3_pwrsrc_switch_to_vaux(tp);
3004 tg3_pwrsrc_die_with_vmain(tp);
3007 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3012 if (speed != SPEED_10)
3014 } else if (speed == SPEED_10)
3020 static bool tg3_phy_power_bug(struct tg3 *tp)
3022 switch (tg3_asic_rev(tp)) {
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3045 static bool tg3_phy_led_bug(struct tg3 *tp)
3047 switch (tg3_asic_rev(tp)) {
3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3059 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3099 MII_TG3_FET_SHDW_AUXMODE4,
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3105 } else if (do_low_power) {
3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3116 /* The PHY should not be powered down on some chips because
3119 if (tg3_phy_power_bug(tp))
3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3133 /* tp->lock is held. */
3134 static int tg3_nvram_lock(struct tg3 *tp)
3136 if (tg3_flag(tp, NVRAM)) {
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3151 tp->nvram_lock_cnt++;
3156 /* tp->lock is held. */
3157 static void tg3_nvram_unlock(struct tg3 *tp)
3159 if (tg3_flag(tp, NVRAM)) {
3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3167 /* tp->lock is held. */
3168 static void tg3_enable_nvram_access(struct tg3 *tp)
3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3177 /* tp->lock is held. */
3178 static void tg3_disable_nvram_access(struct tg3 *tp)
3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3187 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3199 tw32(GRC_EEPROM_ADDR,
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3216 tmp = tr32(GRC_EEPROM_DATA);
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3227 #define NVRAM_CMD_TIMEOUT 5000
3229 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3235 usleep_range(10, 40);
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3242 if (i == NVRAM_CMD_TIMEOUT)
3248 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3263 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3278 /* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3284 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3288 if (!tg3_flag(tp, NVRAM))
3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3291 offset = tg3_nvram_phys_addr(tp, offset);
3293 if (offset > NVRAM_ADDR_MSK)
3296 ret = tg3_nvram_lock(tp);
3300 tg3_enable_nvram_access(tp);
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3307 *val = tr32(NVRAM_RDDATA);
3309 tg3_disable_nvram_access(tp);
3311 tg3_nvram_unlock(tp);
3316 /* Ensures NVRAM data is in bytestream format. */
3317 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3320 int res = tg3_nvram_read(tp, offset, &v);
3322 *val = cpu_to_be32(v);
3326 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3332 for (i = 0; i < len; i += 4) {
3338 memcpy(&data, buf + i, 4);
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3362 if (val & EEPROM_ADDR_COMPLETE)
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3375 /* offset and length are dword aligned */
3376 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3391 u32 phy_addr, page_off, size;
3393 phy_addr = offset & ~pagemask;
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3404 page_off = offset & pagemask;
3411 memcpy(tmp + page_off, buf, size);
3413 offset = offset + (pagesize - page_off);
3415 tg3_enable_nvram_access(tp);
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 for (j = 0; j < pagesize; j += 4) {
3444 data = *((__be32 *) (tmp + j));
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3448 tw32(NVRAM_ADDR, phy_addr + j);
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474 /* offset and length are dword aligned */
3475 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3487 page_off = offset % tp->nvram_pagesize;
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3499 nvram_cmd |= NVRAM_CMD_LAST;
3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 /* offset and length are dword aligned */
3530 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3545 ret = tg3_nvram_lock(tp);
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 #define RX_CPU_SCRATCH_BASE 0x30000
3580 #define RX_CPU_SCRATCH_SIZE 0x04000
3581 #define TX_CPU_SCRATCH_BASE 0x34000
3582 #define TX_CPU_SCRATCH_SIZE 0x04000
3584 /* tp->lock is held. */
3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3588 const int iters = 10000;
3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3595 if (pci_channel_offline(tp->pdev))
3599 return (i == iters) ? -EBUSY : 0;
3602 /* tp->lock is held. */
3603 static int tg3_rxcpu_pause(struct tg3 *tp)
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3614 /* tp->lock is held. */
3615 static int tg3_txcpu_pause(struct tg3 *tp)
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3620 /* tp->lock is held. */
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3627 /* tp->lock is held. */
3628 static void tg3_rxcpu_resume(struct tg3 *tp)
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3633 /* tp->lock is held. */
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
3650 * There is only an Rx CPU for the 5750 derivative in the
3653 if (tg3_flag(tp, IS_SSB_CORE))
3656 rc = tg3_txcpu_pause(tp);
3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3671 static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3693 fw_len = tp->fw->size;
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3698 /* tp->lock is held. */
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
3701 const struct tg3_firmware_hdr *fw_hdr)
3704 void (*write_op)(struct tg3 *, u32, u32);
3705 int total_len = tp->fw->size;
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3715 write_op = tg3_write_mem;
3717 write_op = tg3_write_indirect_reg32;
3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3726 tg3_nvram_unlock(tp);
3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3739 total_len -= TG3_FW_HDR_LEN;
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3749 be32_to_cpu(fw_data[i]));
3751 total_len -= be32_to_cpu(fw_hdr->len);
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
3764 /* tp->lock is held. */
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3768 const int iters = 5;
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3782 return (i == iters) ? -EBUSY : 0;
3785 /* tp->lock is held. */
3786 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3788 const struct tg3_firmware_hdr *fw_hdr;
3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3811 /* Now startup only the RX cpu. */
3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
3822 tg3_rxcpu_resume(tp);
3827 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3829 const int iters = 1000;
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3858 /* tp->lock is held. */
3859 static void tg3_load_57766_firmware(struct tg3 *tp)
3861 struct tg3_firmware_hdr *fw_hdr;
3863 if (!tg3_flag(tp, NO_NVRAM))
3866 if (tg3_validate_rxcpu_state(tp))
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3890 if (tg3_rxcpu_pause(tp))
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3896 tg3_rxcpu_resume(tp);
3899 /* tp->lock is held. */
3900 static int tg3_load_tso_firmware(struct tg3 *tp)
3902 const struct tg3_firmware_hdr *fw_hdr;
3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3906 if (!tg3_flag(tp, FW_TSO))
3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3917 cpu_scratch_size = tp->fw_len;
3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
3934 /* Now startup the cpu. */
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
3945 tg3_resume_cpu(tp, cpu_base);
3949 /* tp->lock is held. */
3950 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3952 u32 addr_high, addr_low;
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3968 /* tp->lock is held. */
3969 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3996 static void tg3_enable_register_access(struct tg3 *tp)
3999 * Make sure register accesses (indirect or otherwise) will function
4002 pci_write_config_dword(tp->pdev,
4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4006 static int tg3_power_up(struct tg3 *tp)
4010 tg3_enable_register_access(tp);
4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4023 static int tg3_setup_phy(struct tg3 *, bool);
4025 static int tg3_power_down_prepare(struct tg3 *tp)
4028 bool device_should_wake, do_low_power;
4030 tg3_enable_register_access(tp);
4032 /* Restore the CLKREQ setting. */
4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4042 tg3_flag(tp, WOL_ENABLE);
4044 if (tg3_flag(tp, USE_PHYLIB)) {
4045 do_low_power = false;
4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4048 struct phy_device *phydev;
4049 u32 phyid, advertising;
4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
4060 advertising = ADVERTISED_TP |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4072 advertising |= ADVERTISED_10baseT_Full;
4075 phydev->advertising = advertising;
4077 phy_start_aneg(phydev);
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
4085 do_low_power = true;
4089 do_low_power = true;
4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4095 tg3_setup_phy(tp, false);
4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4114 if (tg3_flag(tp, WOL_CAP))
4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4120 if (device_should_wake) {
4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode = MAC_MODE_PORT_MODE_MII;
4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4158 if (!tg3_flag(tp, 5750_PLUS))
4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4166 if (tg3_flag(tp, ENABLE_APE))
4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
4171 tw32_f(MAC_MODE, mac_mode);
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4194 u32 newbits1, newbits2;
4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4202 } else if (tg3_flag(tp, 5705_PLUS)) {
4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4216 if (!tg3_flag(tp, 5705_PLUS)) {
4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4234 tg3_power_down_phy(tp, do_low_power);
4236 tg3_frob_aux_power(tp, true);
4238 /* Workaround for unstable PLL clock */
4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4242 u32 val = tr32(0x7d00);
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4246 if (!tg3_flag(tp, ENABLE_ASF)) {
4249 err = tg3_nvram_lock(tp);
4250 tg3_halt_cpu(tp, RX_CPU_BASE);
4252 tg3_nvram_unlock(tp);
4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4263 static void tg3_power_down(struct tg3 *tp)
4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4266 pci_set_power_state(tp->pdev, PCI_D3hot);
4269 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4274 *duplex = DUPLEX_HALF;
4277 case MII_TG3_AUX_STAT_10FULL:
4279 *duplex = DUPLEX_FULL;
4282 case MII_TG3_AUX_STAT_100HALF:
4284 *duplex = DUPLEX_HALF;
4287 case MII_TG3_AUX_STAT_100FULL:
4289 *duplex = DUPLEX_FULL;
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
4316 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4321 new_adv = ADVERTISE_CSMA;
4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4323 new_adv |= mii_advertise_flowctrl(flowctrl);
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
4359 if (!tp->eee.eee_enabled) {
4361 tp->eee.advertised = 0;
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4372 switch (tg3_asic_rev(tp)) {
4374 case ASIC_REV_57765:
4375 case ASIC_REV_57766:
4377 /* If we advertised any eee advertisements above... */
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4400 static void tg3_phy_copper_begin(struct tg3 *tp)
4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4427 fc = tp->link_config.flowctrl;
4430 tg3_phy_autoneg_cfg(tp, adv, fc);
4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4445 u32 bmcr, orig_bmcr;
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4459 switch (tp->link_config.speed) {
4465 bmcr |= BMCR_SPEED100;
4469 bmcr |= BMCR_SPEED1000;
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4486 if (!(tmp & BMSR_LSTATUS)) {
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4497 static int tg3_phy_pull_config(struct tg3 *tp)
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4518 tp->link_config.speed = SPEED_10;
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_100;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4539 tp->link_config.duplex = DUPLEX_HALF;
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4587 tp->link_config.advertising |= adv;
4594 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4613 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4615 struct ethtool_eee eee;
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4620 tg3_eee_pull_config(tp, &eee);
4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4628 /* EEE is disabled but we're advertising */
4636 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4638 u32 advmsk, tgtadv, advertising;
4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4652 if ((*lcladv & advmsk) != tgtadv)
4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4673 if (tg3_ctrl != tgtadv)
4680 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4702 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4704 if (curr_link_up != tp->link_up) {
4706 netif_carrier_on(tp->dev);
4708 netif_carrier_off(tp->dev);
4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4713 tg3_link_report(tp);
4720 static void tg3_clear_mac_status(struct tg3 *tp)
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4732 static void tg3_setup_eee(struct tg3 *tp)
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4768 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4770 bool current_link_up;
4772 u32 lcl_adv, rmt_adv;
4777 tg3_clear_mac_status(tp);
4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4787 /* Some third-party PHYs need to be reset on link going
4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4805 !tg3_flag(tp, INIT_COMPLETE))
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4829 err = tg3_init_5401phy_dsp(tp);
4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4843 /* Clear pending interrupts... */
4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4861 current_link_up = false;
4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4865 tp->link_config.rmt_adv = 0;
4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4871 if (!err && !(val & (1 << 10))) {
4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4888 if (bmsr & BMSR_LSTATUS) {
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4908 if (bmcr && bmcr != 0x7fff)
4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4922 if ((bmcr & BMCR_ANENABLE) &&
4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4926 current_link_up = true;
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
4941 tp->link_config.duplex == current_duplex) {
4942 current_link_up = true;
4946 if (current_link_up &&
4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4967 tg3_phy_copper_begin(tp);
4969 if (tg3_flag(tp, ROBOSWITCH)) {
4970 current_link_up = true;
4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4978 tg3_readphy(tp, MII_BMSR, &bmsr);
4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4981 current_link_up = true;
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4985 if (current_link_up) {
4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5012 tw32(MAC_LED_CTRL, led_ctrl);
5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5021 if (current_link_up &&
5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5038 tw32_f(MAC_MODE, tp->mac_mode);
5041 tg3_phy_eee_adjust(tp, current_link_up);
5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5053 tp->link_config.active_speed == SPEED_1000 &&
5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5065 /* Prevent send BD corruption. */
5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5076 tg3_test_and_report_link_chg(tp, current_link_up);
5081 struct tg3_fiber_aneginfo {
5083 #define ANEG_STATE_UNKNOWN 0
5084 #define ANEG_STATE_AN_ENABLE 1
5085 #define ANEG_STATE_RESTART_INIT 2
5086 #define ANEG_STATE_RESTART 3
5087 #define ANEG_STATE_DISABLE_LINK_OK 4
5088 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5089 #define ANEG_STATE_ABILITY_DETECT 6
5090 #define ANEG_STATE_ACK_DETECT_INIT 7
5091 #define ANEG_STATE_ACK_DETECT 8
5092 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5093 #define ANEG_STATE_COMPLETE_ACK 10
5094 #define ANEG_STATE_IDLE_DETECT_INIT 11
5095 #define ANEG_STATE_IDLE_DETECT 12
5096 #define ANEG_STATE_LINK_OK 13
5097 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5101 #define MR_AN_ENABLE 0x00000001
5102 #define MR_RESTART_AN 0x00000002
5103 #define MR_AN_COMPLETE 0x00000004
5104 #define MR_PAGE_RX 0x00000008
5105 #define MR_NP_LOADED 0x00000010
5106 #define MR_TOGGLE_TX 0x00000020
5107 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5110 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5114 #define MR_TOGGLE_RX 0x00002000
5115 #define MR_NP_RX 0x00004000
5117 #define MR_LINK_OK 0x80000000
5119 unsigned long link_time, cur_time;
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5124 char ability_match, idle_match, ack_match;
5126 u32 txconfig, rxconfig;
5127 #define ANEG_CFG_NP 0x00000080
5128 #define ANEG_CFG_ACK 0x00000040
5129 #define ANEG_CFG_RF2 0x00000020
5130 #define ANEG_CFG_RF1 0x00000010
5131 #define ANEG_CFG_PS2 0x00000001
5132 #define ANEG_CFG_PS1 0x00008000
5133 #define ANEG_CFG_HD 0x00004000
5134 #define ANEG_CFG_FD 0x00002000
5135 #define ANEG_CFG_INVAL 0x00001f06
5140 #define ANEG_TIMER_ENAB 2
5141 #define ANEG_FAILED -1
5143 #define ANEG_STATE_SETTLE_TIME 10000
5145 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5149 unsigned long delta;
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5194 ap->rxconfig = rx_cfg_reg;
5197 switch (ap->state) {
5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5214 ap->state = ANEG_STATE_RESTART_INIT;
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
5235 if (delta > ANEG_STATE_SETTLE_TIME)
5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5238 ret = ANEG_TIMER_ENAB;
5241 case ANEG_STATE_DISABLE_LINK_OK:
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5261 case ANEG_STATE_ABILITY_DETECT:
5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5273 ap->state = ANEG_STATE_ACK_DETECT;
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5282 ap->state = ANEG_STATE_AN_ENABLE;
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5319 ap->link_time = ap->cur_time;
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5397 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5442 static void tg3_init_bcm8002(struct tg3 *tp)
5444 u32 mac_status = tr32(MAC_STATUS);
5447 /* Reset when initting first time or we have a link. */
5448 if (tg3_flag(tp, INIT_COMPLETE) &&
5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5475 tg3_writephy(tp, 0x13, 0x0000);
5477 tg3_writephy(tp, 0x11, 0x0a50);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5486 /* Deselect the channel register so we can read the PHYID
5489 tg3_writephy(tp, 0x10, 0x8011);
5492 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5495 bool current_link_up;
5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
5501 expected_sg_dig_ctrl = 0;
5504 current_link_up = false;
5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5522 u32 val = serdes_cfg;
5528 tw32_f(MAC_SERDES_CFG, val);
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
5535 current_link_up = true;
5540 /* Want auto-negotiation. */
5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
5556 current_link_up = true;
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
5570 sg_dig_status = tr32(SG_DIG_STATUS);
5571 mac_status = tr32(MAC_STATUS);
5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5575 u32 local_adv = 0, remote_adv = 0;
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5583 remote_adv |= LPA_1000XPAUSE;
5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5585 remote_adv |= LPA_1000XPAUSE_ASYM;
5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
5591 current_link_up = true;
5592 tp->serdes_counter = 0;
5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
5599 u32 val = serdes_cfg;
5606 tw32_f(MAC_SERDES_CFG, val);
5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
5619 current_link_up = true;
5621 TG3_PHYFLG_PARALLEL_DETECT;
5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5625 goto restart_autoneg;
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5634 return current_link_up;
5637 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5639 bool current_link_up = false;
5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5645 u32 txflags, rxflags;
5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5666 current_link_up = true;
5668 for (i = 0; i < 30; i++) {
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5680 mac_status = tr32(MAC_STATUS);
5681 if (!current_link_up &&
5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
5684 current_link_up = true;
5686 tg3_setup_flow_control(tp, 0, 0);
5688 /* Forcing 1000FD link up. */
5689 current_link_up = true;
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5694 tw32_f(MAC_MODE, tp->mac_mode);
5699 return current_link_up;
5702 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5708 bool current_link_up;
5711 orig_pause_cfg = tp->link_config.active_flowctrl;
5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5715 if (!tg3_flag(tp, HW_AUTONEG) &&
5717 tg3_flag(tp, INIT_COMPLETE)) {
5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5739 tg3_init_bcm8002(tp);
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5745 current_link_up = false;
5746 tp->link_config.rmt_adv = 0;
5747 mac_status = tr32(MAC_STATUS);
5749 if (tg3_flag(tp, HW_AUTONEG))
5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5754 tp->napi[0].hw_status->status =
5755 (SD_STATUS_UPDATED |
5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5770 current_link_up = false;
5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5776 tw32_f(MAC_MODE, tp->mac_mode);
5780 if (current_link_up) {
5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5805 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
5811 bool current_link_up = false;
5812 u32 local_adv, remote_adv, sgsr;
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5827 current_link_up = true;
5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5842 current_duplex = DUPLEX_HALF;
5845 tw32_f(MAC_MODE, tp->mac_mode);
5848 tg3_clear_mac_status(tp);
5850 goto fiber_setup_done;
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5857 tg3_clear_mac_status(tp);
5862 tp->link_config.rmt_adv = 0;
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5870 bmsr &= ~BMSR_LSTATUS;
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5914 new_bmcr |= BMCR_SPEED1000;
5916 /* Force a linkdown */
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5929 tg3_carrier_off(tp);
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5939 bmsr &= ~BMSR_LSTATUS;
5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
5947 current_link_up = true;
5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5951 current_duplex = DUPLEX_HALF;
5956 if (bmcr & BMCR_ANENABLE) {
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5967 current_duplex = DUPLEX_HALF;
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
5972 /* Link is up via parallel detect */
5974 current_link_up = false;
5980 if (current_link_up && current_duplex == DUPLEX_FULL)
5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5987 tw32_f(MAC_MODE, tp->mac_mode);
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5995 tg3_test_and_report_link_chg(tp, current_link_up);
5999 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6001 if (tp->serdes_counter) {
6002 /* Give autoneg time to complete. */
6003 tp->serdes_counter--;
6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6015 /* Select shadow register 0x1f */
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6019 /* Select expansion interrupt status register */
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6037 } else if (tp->link_up &&
6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6042 /* Select expansion interrupt status register */
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6059 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6065 err = tg3_setup_fiber_phy(tp, force_reset);
6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6069 err = tg3_setup_copper_phy(tp, force_reset);
6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6103 if (!tg3_flag(tp, 5705_PLUS)) {
6105 tw32(HOSTCC_STAT_COAL_TICKS,
6106 tp->coal.stats_block_coalesce_usecs);
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6113 val = tr32(PCIE_PWR_MGMT_THRESH);
6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6125 /* tp->lock must be held */
6126 static u64 tg3_refclk_read(struct tg3 *tp)
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6132 /* tp->lock must be held */
6133 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6143 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144 static inline void tg3_full_unlock(struct tg3 *tp);
6145 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6147 struct tg3 *tp = netdev_priv(dev);
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
6151 SOF_TIMESTAMPING_SOFTWARE;
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6162 info->phc_index = -1;
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6173 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6195 tg3_full_lock(tp, 0);
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6204 tg3_full_unlock(tp);
6209 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6220 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
6223 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6225 tg3_full_lock(tp, 0);
6226 ns = tg3_refclk_read(tp);
6227 ns += tp->ptp_adjust;
6228 tg3_full_unlock(tp);
6230 *ts = ns_to_timespec64(ns);
6235 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6236 const struct timespec64 *ts)
6239 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6241 ns = timespec64_to_ns(ts);
6243 tg3_full_lock(tp, 0);
6244 tg3_refclk_write(tp, ns);
6246 tg3_full_unlock(tp);
6251 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6252 struct ptp_clock_request *rq, int on)
6254 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6259 case PTP_CLK_REQ_PEROUT:
6260 if (rq->perout.index != 0)
6263 tg3_full_lock(tp, 0);
6264 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6265 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6270 nsec = rq->perout.start.sec * 1000000000ULL +
6271 rq->perout.start.nsec;
6273 if (rq->perout.period.sec || rq->perout.period.nsec) {
6274 netdev_warn(tp->dev,
6275 "Device supports only a one-shot timesync output, period must be 0\n");
6280 if (nsec & (1ULL << 63)) {
6281 netdev_warn(tp->dev,
6282 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6287 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6288 tw32(TG3_EAV_WATCHDOG0_MSB,
6289 TG3_EAV_WATCHDOG0_EN |
6290 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6292 tw32(TG3_EAV_REF_CLCK_CTL,
6293 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6295 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6296 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6300 tg3_full_unlock(tp);
6310 static const struct ptp_clock_info tg3_ptp_caps = {
6311 .owner = THIS_MODULE,
6312 .name = "tg3 clock",
6313 .max_adj = 250000000,
6319 .adjfreq = tg3_ptp_adjfreq,
6320 .adjtime = tg3_ptp_adjtime,
6321 .gettime64 = tg3_ptp_gettime,
6322 .settime64 = tg3_ptp_settime,
6323 .enable = tg3_ptp_enable,
6326 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6327 struct skb_shared_hwtstamps *timestamp)
6329 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6330 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6334 /* tp->lock must be held */
6335 static void tg3_ptp_init(struct tg3 *tp)
6337 if (!tg3_flag(tp, PTP_CAPABLE))
6340 /* Initialize the hardware clock to the system time. */
6341 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6343 tp->ptp_info = tg3_ptp_caps;
6346 /* tp->lock must be held */
6347 static void tg3_ptp_resume(struct tg3 *tp)
6349 if (!tg3_flag(tp, PTP_CAPABLE))
6352 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6356 static void tg3_ptp_fini(struct tg3 *tp)
6358 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6361 ptp_clock_unregister(tp->ptp_clock);
6362 tp->ptp_clock = NULL;
6366 static inline int tg3_irq_sync(struct tg3 *tp)
6368 return tp->irq_sync;
6371 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6375 dst = (u32 *)((u8 *)dst + off);
6376 for (i = 0; i < len; i += sizeof(u32))
6377 *dst++ = tr32(off + i);
6380 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6382 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6383 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6384 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6385 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6386 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6387 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6388 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6389 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6390 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6391 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6392 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6393 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6395 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6396 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6397 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6398 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6399 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6400 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6402 if (tg3_flag(tp, SUPPORT_MSIX))
6403 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6405 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6406 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6407 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6408 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6409 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6410 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6411 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6414 if (!tg3_flag(tp, 5705_PLUS)) {
6415 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6416 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6417 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6420 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6421 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6422 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6423 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6424 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6426 if (tg3_flag(tp, NVRAM))
6427 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6430 static void tg3_dump_state(struct tg3 *tp)
6435 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6439 if (tg3_flag(tp, PCI_EXPRESS)) {
6440 /* Read up to but not including private PCI registers */
6441 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6442 regs[i / sizeof(u32)] = tr32(i);
6444 tg3_dump_legacy_regs(tp, regs);
6446 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6447 if (!regs[i + 0] && !regs[i + 1] &&
6448 !regs[i + 2] && !regs[i + 3])
6451 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6453 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6458 for (i = 0; i < tp->irq_cnt; i++) {
6459 struct tg3_napi *tnapi = &tp->napi[i];
6461 /* SW status block */
6463 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6465 tnapi->hw_status->status,
6466 tnapi->hw_status->status_tag,
6467 tnapi->hw_status->rx_jumbo_consumer,
6468 tnapi->hw_status->rx_consumer,
6469 tnapi->hw_status->rx_mini_consumer,
6470 tnapi->hw_status->idx[0].rx_producer,
6471 tnapi->hw_status->idx[0].tx_consumer);
6474 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6476 tnapi->last_tag, tnapi->last_irq_tag,
6477 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6479 tnapi->prodring.rx_std_prod_idx,
6480 tnapi->prodring.rx_std_cons_idx,
6481 tnapi->prodring.rx_jmb_prod_idx,
6482 tnapi->prodring.rx_jmb_cons_idx);
6486 /* This is called whenever we suspect that the system chipset is re-
6487 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6488 * is bogus tx completions. We try to recover by setting the
6489 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6492 static void tg3_tx_recover(struct tg3 *tp)
6494 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6495 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6497 netdev_warn(tp->dev,
6498 "The system may be re-ordering memory-mapped I/O "
6499 "cycles to the network device, attempting to recover. "
6500 "Please report the problem to the driver maintainer "
6501 "and include system chipset information.\n");
6503 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6506 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6508 /* Tell compiler to fetch tx indices from memory. */
6510 return tnapi->tx_pending -
6511 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6514 /* Tigon3 never reports partial packet sends. So we do not
6515 * need special logic to handle SKBs that have not had all
6516 * of their frags sent yet, like SunGEM does.
6518 static void tg3_tx(struct tg3_napi *tnapi)
6520 struct tg3 *tp = tnapi->tp;
6521 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6522 u32 sw_idx = tnapi->tx_cons;
6523 struct netdev_queue *txq;
6524 int index = tnapi - tp->napi;
6525 unsigned int pkts_compl = 0, bytes_compl = 0;
6527 if (tg3_flag(tp, ENABLE_TSS))
6530 txq = netdev_get_tx_queue(tp->dev, index);
6532 while (sw_idx != hw_idx) {
6533 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6534 struct sk_buff *skb = ri->skb;
6537 if (unlikely(skb == NULL)) {
6542 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6543 struct skb_shared_hwtstamps timestamp;
6544 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6545 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6547 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6549 skb_tstamp_tx(skb, ×tamp);
6552 pci_unmap_single(tp->pdev,
6553 dma_unmap_addr(ri, mapping),
6559 while (ri->fragmented) {
6560 ri->fragmented = false;
6561 sw_idx = NEXT_TX(sw_idx);
6562 ri = &tnapi->tx_buffers[sw_idx];
6565 sw_idx = NEXT_TX(sw_idx);
6567 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6568 ri = &tnapi->tx_buffers[sw_idx];
6569 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6572 pci_unmap_page(tp->pdev,
6573 dma_unmap_addr(ri, mapping),
6574 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6577 while (ri->fragmented) {
6578 ri->fragmented = false;
6579 sw_idx = NEXT_TX(sw_idx);
6580 ri = &tnapi->tx_buffers[sw_idx];
6583 sw_idx = NEXT_TX(sw_idx);
6587 bytes_compl += skb->len;
6589 dev_kfree_skb_any(skb);
6591 if (unlikely(tx_bug)) {
6597 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6599 tnapi->tx_cons = sw_idx;
6601 /* Need to make the tx_cons update visible to tg3_start_xmit()
6602 * before checking for netif_queue_stopped(). Without the
6603 * memory barrier, there is a small possibility that tg3_start_xmit()
6604 * will miss it and cause the queue to be stopped forever.
6608 if (unlikely(netif_tx_queue_stopped(txq) &&
6609 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6610 __netif_tx_lock(txq, smp_processor_id());
6611 if (netif_tx_queue_stopped(txq) &&
6612 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6613 netif_tx_wake_queue(txq);
6614 __netif_tx_unlock(txq);
6618 static void tg3_frag_free(bool is_frag, void *data)
6621 put_page(virt_to_head_page(data));
6626 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6628 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6629 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6634 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6635 map_sz, PCI_DMA_FROMDEVICE);
6636 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6641 /* Returns size of skb allocated or < 0 on error.
6643 * We only need to fill in the address because the other members
6644 * of the RX descriptor are invariant, see tg3_init_rings.
6646 * Note the purposeful assymetry of cpu vs. chip accesses. For
6647 * posting buffers we only dirty the first cache line of the RX
6648 * descriptor (containing the address). Whereas for the RX status
6649 * buffers the cpu only reads the last cacheline of the RX descriptor
6650 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6652 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6653 u32 opaque_key, u32 dest_idx_unmasked,
6654 unsigned int *frag_size)
6656 struct tg3_rx_buffer_desc *desc;
6657 struct ring_info *map;
6660 int skb_size, data_size, dest_idx;
6662 switch (opaque_key) {
6663 case RXD_OPAQUE_RING_STD:
6664 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6665 desc = &tpr->rx_std[dest_idx];
6666 map = &tpr->rx_std_buffers[dest_idx];
6667 data_size = tp->rx_pkt_map_sz;
6670 case RXD_OPAQUE_RING_JUMBO:
6671 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6672 desc = &tpr->rx_jmb[dest_idx].std;
6673 map = &tpr->rx_jmb_buffers[dest_idx];
6674 data_size = TG3_RX_JMB_MAP_SZ;
6681 /* Do not overwrite any of the map or rp information
6682 * until we are sure we can commit to a new buffer.
6684 * Callers depend upon this behavior and assume that
6685 * we leave everything unchanged if we fail.
6687 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6688 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6689 if (skb_size <= PAGE_SIZE) {
6690 data = netdev_alloc_frag(skb_size);
6691 *frag_size = skb_size;
6693 data = kmalloc(skb_size, GFP_ATOMIC);
6699 mapping = pci_map_single(tp->pdev,
6700 data + TG3_RX_OFFSET(tp),
6702 PCI_DMA_FROMDEVICE);
6703 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6704 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6709 dma_unmap_addr_set(map, mapping, mapping);
6711 desc->addr_hi = ((u64)mapping >> 32);
6712 desc->addr_lo = ((u64)mapping & 0xffffffff);
6717 /* We only need to move over in the address because the other
6718 * members of the RX descriptor are invariant. See notes above
6719 * tg3_alloc_rx_data for full details.
6721 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6722 struct tg3_rx_prodring_set *dpr,
6723 u32 opaque_key, int src_idx,
6724 u32 dest_idx_unmasked)
6726 struct tg3 *tp = tnapi->tp;
6727 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6728 struct ring_info *src_map, *dest_map;
6729 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6732 switch (opaque_key) {
6733 case RXD_OPAQUE_RING_STD:
6734 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6735 dest_desc = &dpr->rx_std[dest_idx];
6736 dest_map = &dpr->rx_std_buffers[dest_idx];
6737 src_desc = &spr->rx_std[src_idx];
6738 src_map = &spr->rx_std_buffers[src_idx];
6741 case RXD_OPAQUE_RING_JUMBO:
6742 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6743 dest_desc = &dpr->rx_jmb[dest_idx].std;
6744 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6745 src_desc = &spr->rx_jmb[src_idx].std;
6746 src_map = &spr->rx_jmb_buffers[src_idx];
6753 dest_map->data = src_map->data;
6754 dma_unmap_addr_set(dest_map, mapping,
6755 dma_unmap_addr(src_map, mapping));
6756 dest_desc->addr_hi = src_desc->addr_hi;
6757 dest_desc->addr_lo = src_desc->addr_lo;
6759 /* Ensure that the update to the skb happens after the physical
6760 * addresses have been transferred to the new BD location.
6764 src_map->data = NULL;
6767 /* The RX ring scheme is composed of multiple rings which post fresh
6768 * buffers to the chip, and one special ring the chip uses to report
6769 * status back to the host.
6771 * The special ring reports the status of received packets to the
6772 * host. The chip does not write into the original descriptor the
6773 * RX buffer was obtained from. The chip simply takes the original
6774 * descriptor as provided by the host, updates the status and length
6775 * field, then writes this into the next status ring entry.
6777 * Each ring the host uses to post buffers to the chip is described
6778 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6779 * it is first placed into the on-chip ram. When the packet's length
6780 * is known, it walks down the TG3_BDINFO entries to select the ring.
6781 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6782 * which is within the range of the new packet's length is chosen.
6784 * The "separate ring for rx status" scheme may sound queer, but it makes
6785 * sense from a cache coherency perspective. If only the host writes
6786 * to the buffer post rings, and only the chip writes to the rx status
6787 * rings, then cache lines never move beyond shared-modified state.
6788 * If both the host and chip were to write into the same ring, cache line
6789 * eviction could occur since both entities want it in an exclusive state.
6791 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6793 struct tg3 *tp = tnapi->tp;
6794 u32 work_mask, rx_std_posted = 0;
6795 u32 std_prod_idx, jmb_prod_idx;
6796 u32 sw_idx = tnapi->rx_rcb_ptr;
6799 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6801 hw_idx = *(tnapi->rx_rcb_prod_idx);
6803 * We need to order the read of hw_idx and the read of
6804 * the opaque cookie.
6809 std_prod_idx = tpr->rx_std_prod_idx;
6810 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6811 while (sw_idx != hw_idx && budget > 0) {
6812 struct ring_info *ri;
6813 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6815 struct sk_buff *skb;
6816 dma_addr_t dma_addr;
6817 u32 opaque_key, desc_idx, *post_ptr;
6821 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6822 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6823 if (opaque_key == RXD_OPAQUE_RING_STD) {
6824 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6825 dma_addr = dma_unmap_addr(ri, mapping);
6827 post_ptr = &std_prod_idx;
6829 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6830 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6831 dma_addr = dma_unmap_addr(ri, mapping);
6833 post_ptr = &jmb_prod_idx;
6835 goto next_pkt_nopost;
6837 work_mask |= opaque_key;
6839 if (desc->err_vlan & RXD_ERR_MASK) {
6841 tg3_recycle_rx(tnapi, tpr, opaque_key,
6842 desc_idx, *post_ptr);
6844 /* Other statistics kept track of by card. */
6849 prefetch(data + TG3_RX_OFFSET(tp));
6850 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6853 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6854 RXD_FLAG_PTPSTAT_PTPV1 ||
6855 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV2) {
6857 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6858 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6861 if (len > TG3_RX_COPY_THRESH(tp)) {
6863 unsigned int frag_size;
6865 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6866 *post_ptr, &frag_size);
6870 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6871 PCI_DMA_FROMDEVICE);
6873 /* Ensure that the update to the data happens
6874 * after the usage of the old DMA mapping.
6880 skb = build_skb(data, frag_size);
6882 tg3_frag_free(frag_size != 0, data);
6883 goto drop_it_no_recycle;
6885 skb_reserve(skb, TG3_RX_OFFSET(tp));
6887 tg3_recycle_rx(tnapi, tpr, opaque_key,
6888 desc_idx, *post_ptr);
6890 skb = netdev_alloc_skb(tp->dev,
6891 len + TG3_RAW_IP_ALIGN);
6893 goto drop_it_no_recycle;
6895 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6896 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6898 data + TG3_RX_OFFSET(tp),
6900 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6905 tg3_hwclock_to_timestamp(tp, tstamp,
6906 skb_hwtstamps(skb));
6908 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6909 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6910 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6911 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6912 skb->ip_summed = CHECKSUM_UNNECESSARY;
6914 skb_checksum_none_assert(skb);
6916 skb->protocol = eth_type_trans(skb, tp->dev);
6918 if (len > (tp->dev->mtu + ETH_HLEN) &&
6919 skb->protocol != htons(ETH_P_8021Q) &&
6920 skb->protocol != htons(ETH_P_8021AD)) {
6921 dev_kfree_skb_any(skb);
6922 goto drop_it_no_recycle;
6925 if (desc->type_flags & RXD_FLAG_VLAN &&
6926 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6927 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6928 desc->err_vlan & RXD_VLAN_MASK);
6930 napi_gro_receive(&tnapi->napi, skb);
6938 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6939 tpr->rx_std_prod_idx = std_prod_idx &
6940 tp->rx_std_ring_mask;
6941 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6942 tpr->rx_std_prod_idx);
6943 work_mask &= ~RXD_OPAQUE_RING_STD;
6948 sw_idx &= tp->rx_ret_ring_mask;
6950 /* Refresh hw_idx to see if there is new work */
6951 if (sw_idx == hw_idx) {
6952 hw_idx = *(tnapi->rx_rcb_prod_idx);
6957 /* ACK the status ring. */
6958 tnapi->rx_rcb_ptr = sw_idx;
6959 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6961 /* Refill RX ring(s). */
6962 if (!tg3_flag(tp, ENABLE_RSS)) {
6963 /* Sync BD data before updating mailbox */
6966 if (work_mask & RXD_OPAQUE_RING_STD) {
6967 tpr->rx_std_prod_idx = std_prod_idx &
6968 tp->rx_std_ring_mask;
6969 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6970 tpr->rx_std_prod_idx);
6972 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6973 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6974 tp->rx_jmb_ring_mask;
6975 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6976 tpr->rx_jmb_prod_idx);
6979 } else if (work_mask) {
6980 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6981 * updated before the producer indices can be updated.
6985 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6986 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6988 if (tnapi != &tp->napi[1]) {
6989 tp->rx_refill = true;
6990 napi_schedule(&tp->napi[1].napi);
6997 static void tg3_poll_link(struct tg3 *tp)
6999 /* handle link change and other phy events */
7000 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7001 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7003 if (sblk->status & SD_STATUS_LINK_CHG) {
7004 sblk->status = SD_STATUS_UPDATED |
7005 (sblk->status & ~SD_STATUS_LINK_CHG);
7006 spin_lock(&tp->lock);
7007 if (tg3_flag(tp, USE_PHYLIB)) {
7009 (MAC_STATUS_SYNC_CHANGED |
7010 MAC_STATUS_CFG_CHANGED |
7011 MAC_STATUS_MI_COMPLETION |
7012 MAC_STATUS_LNKSTATE_CHANGED));
7015 tg3_setup_phy(tp, false);
7016 spin_unlock(&tp->lock);
7021 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7022 struct tg3_rx_prodring_set *dpr,
7023 struct tg3_rx_prodring_set *spr)
7025 u32 si, di, cpycnt, src_prod_idx;
7029 src_prod_idx = spr->rx_std_prod_idx;
7031 /* Make sure updates to the rx_std_buffers[] entries and the
7032 * standard producer index are seen in the correct order.
7036 if (spr->rx_std_cons_idx == src_prod_idx)
7039 if (spr->rx_std_cons_idx < src_prod_idx)
7040 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7042 cpycnt = tp->rx_std_ring_mask + 1 -
7043 spr->rx_std_cons_idx;
7045 cpycnt = min(cpycnt,
7046 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7048 si = spr->rx_std_cons_idx;
7049 di = dpr->rx_std_prod_idx;
7051 for (i = di; i < di + cpycnt; i++) {
7052 if (dpr->rx_std_buffers[i].data) {
7062 /* Ensure that updates to the rx_std_buffers ring and the
7063 * shadowed hardware producer ring from tg3_recycle_skb() are
7064 * ordered correctly WRT the skb check above.
7068 memcpy(&dpr->rx_std_buffers[di],
7069 &spr->rx_std_buffers[si],
7070 cpycnt * sizeof(struct ring_info));
7072 for (i = 0; i < cpycnt; i++, di++, si++) {
7073 struct tg3_rx_buffer_desc *sbd, *dbd;
7074 sbd = &spr->rx_std[si];
7075 dbd = &dpr->rx_std[di];
7076 dbd->addr_hi = sbd->addr_hi;
7077 dbd->addr_lo = sbd->addr_lo;
7080 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7081 tp->rx_std_ring_mask;
7082 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7083 tp->rx_std_ring_mask;
7087 src_prod_idx = spr->rx_jmb_prod_idx;
7089 /* Make sure updates to the rx_jmb_buffers[] entries and
7090 * the jumbo producer index are seen in the correct order.
7094 if (spr->rx_jmb_cons_idx == src_prod_idx)
7097 if (spr->rx_jmb_cons_idx < src_prod_idx)
7098 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7100 cpycnt = tp->rx_jmb_ring_mask + 1 -
7101 spr->rx_jmb_cons_idx;
7103 cpycnt = min(cpycnt,
7104 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7106 si = spr->rx_jmb_cons_idx;
7107 di = dpr->rx_jmb_prod_idx;
7109 for (i = di; i < di + cpycnt; i++) {
7110 if (dpr->rx_jmb_buffers[i].data) {
7120 /* Ensure that updates to the rx_jmb_buffers ring and the
7121 * shadowed hardware producer ring from tg3_recycle_skb() are
7122 * ordered correctly WRT the skb check above.
7126 memcpy(&dpr->rx_jmb_buffers[di],
7127 &spr->rx_jmb_buffers[si],
7128 cpycnt * sizeof(struct ring_info));
7130 for (i = 0; i < cpycnt; i++, di++, si++) {
7131 struct tg3_rx_buffer_desc *sbd, *dbd;
7132 sbd = &spr->rx_jmb[si].std;
7133 dbd = &dpr->rx_jmb[di].std;
7134 dbd->addr_hi = sbd->addr_hi;
7135 dbd->addr_lo = sbd->addr_lo;
7138 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7139 tp->rx_jmb_ring_mask;
7140 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7141 tp->rx_jmb_ring_mask;
7147 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7149 struct tg3 *tp = tnapi->tp;
7151 /* run TX completion thread */
7152 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7154 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7158 if (!tnapi->rx_rcb_prod_idx)
7161 /* run RX thread, within the bounds set by NAPI.
7162 * All RX "locking" is done by ensuring outside
7163 * code synchronizes with tg3->napi.poll()
7165 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7166 work_done += tg3_rx(tnapi, budget - work_done);
7168 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7169 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7171 u32 std_prod_idx = dpr->rx_std_prod_idx;
7172 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7174 tp->rx_refill = false;
7175 for (i = 1; i <= tp->rxq_cnt; i++)
7176 err |= tg3_rx_prodring_xfer(tp, dpr,
7177 &tp->napi[i].prodring);
7181 if (std_prod_idx != dpr->rx_std_prod_idx)
7182 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7183 dpr->rx_std_prod_idx);
7185 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7186 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7187 dpr->rx_jmb_prod_idx);
7192 tw32_f(HOSTCC_MODE, tp->coal_now);
7198 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7200 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7201 schedule_work(&tp->reset_task);
7204 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7206 cancel_work_sync(&tp->reset_task);
7207 tg3_flag_clear(tp, RESET_TASK_PENDING);
7208 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7211 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7213 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7214 struct tg3 *tp = tnapi->tp;
7216 struct tg3_hw_status *sblk = tnapi->hw_status;
7219 work_done = tg3_poll_work(tnapi, work_done, budget);
7221 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7224 if (unlikely(work_done >= budget))
7227 /* tp->last_tag is used in tg3_int_reenable() below
7228 * to tell the hw how much work has been processed,
7229 * so we must read it before checking for more work.
7231 tnapi->last_tag = sblk->status_tag;
7232 tnapi->last_irq_tag = tnapi->last_tag;
7235 /* check for RX/TX work to do */
7236 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7237 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7239 /* This test here is not race free, but will reduce
7240 * the number of interrupts by looping again.
7242 if (tnapi == &tp->napi[1] && tp->rx_refill)
7245 napi_complete_done(napi, work_done);
7246 /* Reenable interrupts. */
7247 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7249 /* This test here is synchronized by napi_schedule()
7250 * and napi_complete() to close the race condition.
7252 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7253 tw32(HOSTCC_MODE, tp->coalesce_mode |
7254 HOSTCC_MODE_ENABLE |
7265 /* work_done is guaranteed to be less than budget. */
7266 napi_complete(napi);
7267 tg3_reset_task_schedule(tp);
7271 static void tg3_process_error(struct tg3 *tp)
7274 bool real_error = false;
7276 if (tg3_flag(tp, ERROR_PROCESSED))
7279 /* Check Flow Attention register */
7280 val = tr32(HOSTCC_FLOW_ATTN);
7281 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7282 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7286 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7287 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7291 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7292 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7301 tg3_flag_set(tp, ERROR_PROCESSED);
7302 tg3_reset_task_schedule(tp);
7305 static int tg3_poll(struct napi_struct *napi, int budget)
7307 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7308 struct tg3 *tp = tnapi->tp;
7310 struct tg3_hw_status *sblk = tnapi->hw_status;
7313 if (sblk->status & SD_STATUS_ERROR)
7314 tg3_process_error(tp);
7318 work_done = tg3_poll_work(tnapi, work_done, budget);
7320 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7323 if (unlikely(work_done >= budget))
7326 if (tg3_flag(tp, TAGGED_STATUS)) {
7327 /* tp->last_tag is used in tg3_int_reenable() below
7328 * to tell the hw how much work has been processed,
7329 * so we must read it before checking for more work.
7331 tnapi->last_tag = sblk->status_tag;
7332 tnapi->last_irq_tag = tnapi->last_tag;
7335 sblk->status &= ~SD_STATUS_UPDATED;
7337 if (likely(!tg3_has_work(tnapi))) {
7338 napi_complete_done(napi, work_done);
7339 tg3_int_reenable(tnapi);
7347 /* work_done is guaranteed to be less than budget. */
7348 napi_complete(napi);
7349 tg3_reset_task_schedule(tp);
7353 static void tg3_napi_disable(struct tg3 *tp)
7357 for (i = tp->irq_cnt - 1; i >= 0; i--)
7358 napi_disable(&tp->napi[i].napi);
7361 static void tg3_napi_enable(struct tg3 *tp)
7365 for (i = 0; i < tp->irq_cnt; i++)
7366 napi_enable(&tp->napi[i].napi);
7369 static void tg3_napi_init(struct tg3 *tp)
7373 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7374 for (i = 1; i < tp->irq_cnt; i++)
7375 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7378 static void tg3_napi_fini(struct tg3 *tp)
7382 for (i = 0; i < tp->irq_cnt; i++)
7383 netif_napi_del(&tp->napi[i].napi);
7386 static inline void tg3_netif_stop(struct tg3 *tp)
7388 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7389 tg3_napi_disable(tp);
7390 netif_carrier_off(tp->dev);
7391 netif_tx_disable(tp->dev);
7394 /* tp->lock must be held */
7395 static inline void tg3_netif_start(struct tg3 *tp)
7399 /* NOTE: unconditional netif_tx_wake_all_queues is only
7400 * appropriate so long as all callers are assured to
7401 * have free tx slots (such as after tg3_init_hw)
7403 netif_tx_wake_all_queues(tp->dev);
7406 netif_carrier_on(tp->dev);
7408 tg3_napi_enable(tp);
7409 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7410 tg3_enable_ints(tp);
7413 static void tg3_irq_quiesce(struct tg3 *tp)
7414 __releases(tp->lock)
7415 __acquires(tp->lock)
7419 BUG_ON(tp->irq_sync);
7424 spin_unlock_bh(&tp->lock);
7426 for (i = 0; i < tp->irq_cnt; i++)
7427 synchronize_irq(tp->napi[i].irq_vec);
7429 spin_lock_bh(&tp->lock);
7432 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7433 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7434 * with as well. Most of the time, this is not necessary except when
7435 * shutting down the device.
7437 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7439 spin_lock_bh(&tp->lock);
7441 tg3_irq_quiesce(tp);
7444 static inline void tg3_full_unlock(struct tg3 *tp)
7446 spin_unlock_bh(&tp->lock);
7449 /* One-shot MSI handler - Chip automatically disables interrupt
7450 * after sending MSI so driver doesn't have to do it.
7452 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7454 struct tg3_napi *tnapi = dev_id;
7455 struct tg3 *tp = tnapi->tp;
7457 prefetch(tnapi->hw_status);
7459 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7461 if (likely(!tg3_irq_sync(tp)))
7462 napi_schedule(&tnapi->napi);
7467 /* MSI ISR - No need to check for interrupt sharing and no need to
7468 * flush status block and interrupt mailbox. PCI ordering rules
7469 * guarantee that MSI will arrive after the status block.
7471 static irqreturn_t tg3_msi(int irq, void *dev_id)
7473 struct tg3_napi *tnapi = dev_id;
7474 struct tg3 *tp = tnapi->tp;
7476 prefetch(tnapi->hw_status);
7478 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7480 * Writing any value to intr-mbox-0 clears PCI INTA# and
7481 * chip-internal interrupt pending events.
7482 * Writing non-zero to intr-mbox-0 additional tells the
7483 * NIC to stop sending us irqs, engaging "in-intr-handler"
7486 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7487 if (likely(!tg3_irq_sync(tp)))
7488 napi_schedule(&tnapi->napi);
7490 return IRQ_RETVAL(1);
7493 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7495 struct tg3_napi *tnapi = dev_id;
7496 struct tg3 *tp = tnapi->tp;
7497 struct tg3_hw_status *sblk = tnapi->hw_status;
7498 unsigned int handled = 1;
7500 /* In INTx mode, it is possible for the interrupt to arrive at
7501 * the CPU before the status block posted prior to the interrupt.
7502 * Reading the PCI State register will confirm whether the
7503 * interrupt is ours and will flush the status block.
7505 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7506 if (tg3_flag(tp, CHIP_RESETTING) ||
7507 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7514 * Writing any value to intr-mbox-0 clears PCI INTA# and
7515 * chip-internal interrupt pending events.
7516 * Writing non-zero to intr-mbox-0 additional tells the
7517 * NIC to stop sending us irqs, engaging "in-intr-handler"
7520 * Flush the mailbox to de-assert the IRQ immediately to prevent
7521 * spurious interrupts. The flush impacts performance but
7522 * excessive spurious interrupts can be worse in some cases.
7524 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7525 if (tg3_irq_sync(tp))
7527 sblk->status &= ~SD_STATUS_UPDATED;
7528 if (likely(tg3_has_work(tnapi))) {
7529 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7530 napi_schedule(&tnapi->napi);
7532 /* No work, shared interrupt perhaps? re-enable
7533 * interrupts, and flush that PCI write
7535 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7539 return IRQ_RETVAL(handled);
7542 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7544 struct tg3_napi *tnapi = dev_id;
7545 struct tg3 *tp = tnapi->tp;
7546 struct tg3_hw_status *sblk = tnapi->hw_status;
7547 unsigned int handled = 1;
7549 /* In INTx mode, it is possible for the interrupt to arrive at
7550 * the CPU before the status block posted prior to the interrupt.
7551 * Reading the PCI State register will confirm whether the
7552 * interrupt is ours and will flush the status block.
7554 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7555 if (tg3_flag(tp, CHIP_RESETTING) ||
7556 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7563 * writing any value to intr-mbox-0 clears PCI INTA# and
7564 * chip-internal interrupt pending events.
7565 * writing non-zero to intr-mbox-0 additional tells the
7566 * NIC to stop sending us irqs, engaging "in-intr-handler"
7569 * Flush the mailbox to de-assert the IRQ immediately to prevent
7570 * spurious interrupts. The flush impacts performance but
7571 * excessive spurious interrupts can be worse in some cases.
7573 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7576 * In a shared interrupt configuration, sometimes other devices'
7577 * interrupts will scream. We record the current status tag here
7578 * so that the above check can report that the screaming interrupts
7579 * are unhandled. Eventually they will be silenced.
7581 tnapi->last_irq_tag = sblk->status_tag;
7583 if (tg3_irq_sync(tp))
7586 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7588 napi_schedule(&tnapi->napi);
7591 return IRQ_RETVAL(handled);
7594 /* ISR for interrupt test */
7595 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7597 struct tg3_napi *tnapi = dev_id;
7598 struct tg3 *tp = tnapi->tp;
7599 struct tg3_hw_status *sblk = tnapi->hw_status;
7601 if ((sblk->status & SD_STATUS_UPDATED) ||
7602 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7603 tg3_disable_ints(tp);
7604 return IRQ_RETVAL(1);
7606 return IRQ_RETVAL(0);
7609 #ifdef CONFIG_NET_POLL_CONTROLLER
7610 static void tg3_poll_controller(struct net_device *dev)
7613 struct tg3 *tp = netdev_priv(dev);
7615 if (tg3_irq_sync(tp))
7618 for (i = 0; i < tp->irq_cnt; i++)
7619 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7623 static void tg3_tx_timeout(struct net_device *dev)
7625 struct tg3 *tp = netdev_priv(dev);
7627 if (netif_msg_tx_err(tp)) {
7628 netdev_err(dev, "transmit timed out, resetting\n");
7632 tg3_reset_task_schedule(tp);
7635 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7636 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7638 u32 base = (u32) mapping & 0xffffffff;
7640 return base + len + 8 < base;
7643 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7644 * of any 4GB boundaries: 4G, 8G, etc
7646 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7649 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7650 u32 base = (u32) mapping & 0xffffffff;
7652 return ((base + len + (mss & 0x3fff)) < base);
7657 /* Test for DMA addresses > 40-bit */
7658 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7661 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7662 if (tg3_flag(tp, 40BIT_DMA_BUG))
7663 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7670 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7671 dma_addr_t mapping, u32 len, u32 flags,
7674 txbd->addr_hi = ((u64) mapping >> 32);
7675 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7676 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7677 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7680 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7681 dma_addr_t map, u32 len, u32 flags,
7684 struct tg3 *tp = tnapi->tp;
7687 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7690 if (tg3_4g_overflow_test(map, len))
7693 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7696 if (tg3_40bit_overflow_test(tp, map, len))
7699 if (tp->dma_limit) {
7700 u32 prvidx = *entry;
7701 u32 tmp_flag = flags & ~TXD_FLAG_END;
7702 while (len > tp->dma_limit && *budget) {
7703 u32 frag_len = tp->dma_limit;
7704 len -= tp->dma_limit;
7706 /* Avoid the 8byte DMA problem */
7708 len += tp->dma_limit / 2;
7709 frag_len = tp->dma_limit / 2;
7712 tnapi->tx_buffers[*entry].fragmented = true;
7714 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7715 frag_len, tmp_flag, mss, vlan);
7718 *entry = NEXT_TX(*entry);
7725 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7726 len, flags, mss, vlan);
7728 *entry = NEXT_TX(*entry);
7731 tnapi->tx_buffers[prvidx].fragmented = false;
7735 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7736 len, flags, mss, vlan);
7737 *entry = NEXT_TX(*entry);
7743 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7746 struct sk_buff *skb;
7747 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7752 pci_unmap_single(tnapi->tp->pdev,
7753 dma_unmap_addr(txb, mapping),
7757 while (txb->fragmented) {
7758 txb->fragmented = false;
7759 entry = NEXT_TX(entry);
7760 txb = &tnapi->tx_buffers[entry];
7763 for (i = 0; i <= last; i++) {
7764 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7766 entry = NEXT_TX(entry);
7767 txb = &tnapi->tx_buffers[entry];
7769 pci_unmap_page(tnapi->tp->pdev,
7770 dma_unmap_addr(txb, mapping),
7771 skb_frag_size(frag), PCI_DMA_TODEVICE);
7773 while (txb->fragmented) {
7774 txb->fragmented = false;
7775 entry = NEXT_TX(entry);
7776 txb = &tnapi->tx_buffers[entry];
7781 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7782 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7783 struct sk_buff **pskb,
7784 u32 *entry, u32 *budget,
7785 u32 base_flags, u32 mss, u32 vlan)
7787 struct tg3 *tp = tnapi->tp;
7788 struct sk_buff *new_skb, *skb = *pskb;
7789 dma_addr_t new_addr = 0;
7792 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7793 new_skb = skb_copy(skb, GFP_ATOMIC);
7795 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7797 new_skb = skb_copy_expand(skb,
7798 skb_headroom(skb) + more_headroom,
7799 skb_tailroom(skb), GFP_ATOMIC);
7805 /* New SKB is guaranteed to be linear. */
7806 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7808 /* Make sure the mapping succeeded */
7809 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7810 dev_kfree_skb_any(new_skb);
7813 u32 save_entry = *entry;
7815 base_flags |= TXD_FLAG_END;
7817 tnapi->tx_buffers[*entry].skb = new_skb;
7818 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7821 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7822 new_skb->len, base_flags,
7824 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7825 dev_kfree_skb_any(new_skb);
7831 dev_kfree_skb_any(skb);
7836 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7838 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7839 * indicated in tg3_tx_frag_set()
7841 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7842 struct netdev_queue *txq, struct sk_buff *skb)
7844 struct sk_buff *segs, *nskb;
7845 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7847 /* Estimate the number of fragments in the worst case */
7848 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7849 netif_tx_stop_queue(txq);
7851 /* netif_tx_stop_queue() must be done before checking
7852 * checking tx index in tg3_tx_avail() below, because in
7853 * tg3_tx(), we update tx index before checking for
7854 * netif_tx_queue_stopped().
7857 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7858 return NETDEV_TX_BUSY;
7860 netif_tx_wake_queue(txq);
7863 segs = skb_gso_segment(skb, tp->dev->features &
7864 ~(NETIF_F_TSO | NETIF_F_TSO6));
7865 if (IS_ERR(segs) || !segs)
7866 goto tg3_tso_bug_end;
7872 tg3_start_xmit(nskb, tp->dev);
7876 dev_kfree_skb_any(skb);
7878 return NETDEV_TX_OK;
7881 /* hard_start_xmit for all devices */
7882 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7884 struct tg3 *tp = netdev_priv(dev);
7885 u32 len, entry, base_flags, mss, vlan = 0;
7887 int i = -1, would_hit_hwbug;
7889 struct tg3_napi *tnapi;
7890 struct netdev_queue *txq;
7892 struct iphdr *iph = NULL;
7893 struct tcphdr *tcph = NULL;
7894 __sum16 tcp_csum = 0, ip_csum = 0;
7895 __be16 ip_tot_len = 0;
7897 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7898 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7899 if (tg3_flag(tp, ENABLE_TSS))
7902 budget = tg3_tx_avail(tnapi);
7904 /* We are running in BH disabled context with netif_tx_lock
7905 * and TX reclaim runs via tp->napi.poll inside of a software
7906 * interrupt. Furthermore, IRQ processing runs lockless so we have
7907 * no IRQ context deadlocks to worry about either. Rejoice!
7909 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7910 if (!netif_tx_queue_stopped(txq)) {
7911 netif_tx_stop_queue(txq);
7913 /* This is a hard error, log it. */
7915 "BUG! Tx Ring full when queue awake!\n");
7917 return NETDEV_TX_BUSY;
7920 entry = tnapi->tx_prod;
7923 mss = skb_shinfo(skb)->gso_size;
7925 u32 tcp_opt_len, hdr_len;
7927 if (skb_cow_head(skb, 0))
7931 tcp_opt_len = tcp_optlen(skb);
7933 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7935 /* HW/FW can not correctly segment packets that have been
7936 * vlan encapsulated.
7938 if (skb->protocol == htons(ETH_P_8021Q) ||
7939 skb->protocol == htons(ETH_P_8021AD))
7940 return tg3_tso_bug(tp, tnapi, txq, skb);
7942 if (!skb_is_gso_v6(skb)) {
7943 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7944 tg3_flag(tp, TSO_BUG))
7945 return tg3_tso_bug(tp, tnapi, txq, skb);
7947 ip_csum = iph->check;
7948 ip_tot_len = iph->tot_len;
7950 iph->tot_len = htons(mss + hdr_len);
7953 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7954 TXD_FLAG_CPU_POST_DMA);
7956 tcph = tcp_hdr(skb);
7957 tcp_csum = tcph->check;
7959 if (tg3_flag(tp, HW_TSO_1) ||
7960 tg3_flag(tp, HW_TSO_2) ||
7961 tg3_flag(tp, HW_TSO_3)) {
7963 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7965 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7969 if (tg3_flag(tp, HW_TSO_3)) {
7970 mss |= (hdr_len & 0xc) << 12;
7972 base_flags |= 0x00000010;
7973 base_flags |= (hdr_len & 0x3e0) << 5;
7974 } else if (tg3_flag(tp, HW_TSO_2))
7975 mss |= hdr_len << 9;
7976 else if (tg3_flag(tp, HW_TSO_1) ||
7977 tg3_asic_rev(tp) == ASIC_REV_5705) {
7978 if (tcp_opt_len || iph->ihl > 5) {
7981 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7982 mss |= (tsflags << 11);
7985 if (tcp_opt_len || iph->ihl > 5) {
7988 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7989 base_flags |= tsflags << 12;
7992 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7993 /* HW/FW can not correctly checksum packets that have been
7994 * vlan encapsulated.
7996 if (skb->protocol == htons(ETH_P_8021Q) ||
7997 skb->protocol == htons(ETH_P_8021AD)) {
7998 if (skb_checksum_help(skb))
8001 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8005 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8006 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8007 base_flags |= TXD_FLAG_JMB_PKT;
8009 if (skb_vlan_tag_present(skb)) {
8010 base_flags |= TXD_FLAG_VLAN;
8011 vlan = skb_vlan_tag_get(skb);
8014 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8015 tg3_flag(tp, TX_TSTAMP_EN)) {
8016 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8017 base_flags |= TXD_FLAG_HWTSTAMP;
8020 len = skb_headlen(skb);
8022 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8023 if (pci_dma_mapping_error(tp->pdev, mapping))
8027 tnapi->tx_buffers[entry].skb = skb;
8028 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8030 would_hit_hwbug = 0;
8032 if (tg3_flag(tp, 5701_DMA_BUG))
8033 would_hit_hwbug = 1;
8035 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8036 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8038 would_hit_hwbug = 1;
8039 } else if (skb_shinfo(skb)->nr_frags > 0) {
8042 if (!tg3_flag(tp, HW_TSO_1) &&
8043 !tg3_flag(tp, HW_TSO_2) &&
8044 !tg3_flag(tp, HW_TSO_3))
8047 /* Now loop through additional data
8048 * fragments, and queue them.
8050 last = skb_shinfo(skb)->nr_frags - 1;
8051 for (i = 0; i <= last; i++) {
8052 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8054 len = skb_frag_size(frag);
8055 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8056 len, DMA_TO_DEVICE);
8058 tnapi->tx_buffers[entry].skb = NULL;
8059 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8061 if (dma_mapping_error(&tp->pdev->dev, mapping))
8065 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8067 ((i == last) ? TXD_FLAG_END : 0),
8069 would_hit_hwbug = 1;
8075 if (would_hit_hwbug) {
8076 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8079 /* If it's a TSO packet, do GSO instead of
8080 * allocating and copying to a large linear SKB
8083 iph->check = ip_csum;
8084 iph->tot_len = ip_tot_len;
8086 tcph->check = tcp_csum;
8087 return tg3_tso_bug(tp, tnapi, txq, skb);
8090 /* If the workaround fails due to memory/mapping
8091 * failure, silently drop this packet.
8093 entry = tnapi->tx_prod;
8094 budget = tg3_tx_avail(tnapi);
8095 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8096 base_flags, mss, vlan))
8100 skb_tx_timestamp(skb);
8101 netdev_tx_sent_queue(txq, skb->len);
8103 /* Sync BD data before updating mailbox */
8106 tnapi->tx_prod = entry;
8107 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8108 netif_tx_stop_queue(txq);
8110 /* netif_tx_stop_queue() must be done before checking
8111 * checking tx index in tg3_tx_avail() below, because in
8112 * tg3_tx(), we update tx index before checking for
8113 * netif_tx_queue_stopped().
8116 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8117 netif_tx_wake_queue(txq);
8120 if (!skb->xmit_more || netif_xmit_stopped(txq)) {
8121 /* Packets are ready, update Tx producer idx on card. */
8122 tw32_tx_mbox(tnapi->prodmbox, entry);
8126 return NETDEV_TX_OK;
8129 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8130 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8132 dev_kfree_skb_any(skb);
8135 return NETDEV_TX_OK;
8138 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8141 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8142 MAC_MODE_PORT_MODE_MASK);
8144 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8146 if (!tg3_flag(tp, 5705_PLUS))
8147 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8149 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8150 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8152 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8154 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8156 if (tg3_flag(tp, 5705_PLUS) ||
8157 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8158 tg3_asic_rev(tp) == ASIC_REV_5700)
8159 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8162 tw32(MAC_MODE, tp->mac_mode);
8166 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8168 u32 val, bmcr, mac_mode, ptest = 0;
8170 tg3_phy_toggle_apd(tp, false);
8171 tg3_phy_toggle_automdix(tp, false);
8173 if (extlpbk && tg3_phy_set_extloopbk(tp))
8176 bmcr = BMCR_FULLDPLX;
8181 bmcr |= BMCR_SPEED100;
8185 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8187 bmcr |= BMCR_SPEED100;
8190 bmcr |= BMCR_SPEED1000;
8195 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8196 tg3_readphy(tp, MII_CTRL1000, &val);
8197 val |= CTL1000_AS_MASTER |
8198 CTL1000_ENABLE_MASTER;
8199 tg3_writephy(tp, MII_CTRL1000, val);
8201 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8202 MII_TG3_FET_PTEST_TRIM_2;
8203 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8206 bmcr |= BMCR_LOOPBACK;
8208 tg3_writephy(tp, MII_BMCR, bmcr);
8210 /* The write needs to be flushed for the FETs */
8211 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8212 tg3_readphy(tp, MII_BMCR, &bmcr);
8216 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8217 tg3_asic_rev(tp) == ASIC_REV_5785) {
8218 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8219 MII_TG3_FET_PTEST_FRC_TX_LINK |
8220 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8222 /* The write needs to be flushed for the AC131 */
8223 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8226 /* Reset to prevent losing 1st rx packet intermittently */
8227 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8228 tg3_flag(tp, 5780_CLASS)) {
8229 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8231 tw32_f(MAC_RX_MODE, tp->rx_mode);
8234 mac_mode = tp->mac_mode &
8235 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8236 if (speed == SPEED_1000)
8237 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8239 mac_mode |= MAC_MODE_PORT_MODE_MII;
8241 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8242 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8244 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8245 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8246 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8247 mac_mode |= MAC_MODE_LINK_POLARITY;
8249 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8250 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8253 tw32(MAC_MODE, mac_mode);
8259 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8261 struct tg3 *tp = netdev_priv(dev);
8263 if (features & NETIF_F_LOOPBACK) {
8264 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8267 spin_lock_bh(&tp->lock);
8268 tg3_mac_loopback(tp, true);
8269 netif_carrier_on(tp->dev);
8270 spin_unlock_bh(&tp->lock);
8271 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8273 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8276 spin_lock_bh(&tp->lock);
8277 tg3_mac_loopback(tp, false);
8278 /* Force link status check */
8279 tg3_setup_phy(tp, true);
8280 spin_unlock_bh(&tp->lock);
8281 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8285 static netdev_features_t tg3_fix_features(struct net_device *dev,
8286 netdev_features_t features)
8288 struct tg3 *tp = netdev_priv(dev);
8290 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8291 features &= ~NETIF_F_ALL_TSO;
8296 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8298 netdev_features_t changed = dev->features ^ features;
8300 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8301 tg3_set_loopback(dev, features);
8306 static void tg3_rx_prodring_free(struct tg3 *tp,
8307 struct tg3_rx_prodring_set *tpr)
8311 if (tpr != &tp->napi[0].prodring) {
8312 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8313 i = (i + 1) & tp->rx_std_ring_mask)
8314 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8317 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8318 for (i = tpr->rx_jmb_cons_idx;
8319 i != tpr->rx_jmb_prod_idx;
8320 i = (i + 1) & tp->rx_jmb_ring_mask) {
8321 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8329 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8330 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8333 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8334 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8335 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8340 /* Initialize rx rings for packet processing.
8342 * The chip has been shut down and the driver detached from
8343 * the networking, so no interrupts or new tx packets will
8344 * end up in the driver. tp->{tx,}lock are held and thus
8347 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8348 struct tg3_rx_prodring_set *tpr)
8350 u32 i, rx_pkt_dma_sz;
8352 tpr->rx_std_cons_idx = 0;
8353 tpr->rx_std_prod_idx = 0;
8354 tpr->rx_jmb_cons_idx = 0;
8355 tpr->rx_jmb_prod_idx = 0;
8357 if (tpr != &tp->napi[0].prodring) {
8358 memset(&tpr->rx_std_buffers[0], 0,
8359 TG3_RX_STD_BUFF_RING_SIZE(tp));
8360 if (tpr->rx_jmb_buffers)
8361 memset(&tpr->rx_jmb_buffers[0], 0,
8362 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8366 /* Zero out all descriptors. */
8367 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8369 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8370 if (tg3_flag(tp, 5780_CLASS) &&
8371 tp->dev->mtu > ETH_DATA_LEN)
8372 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8373 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8375 /* Initialize invariants of the rings, we only set this
8376 * stuff once. This works because the card does not
8377 * write into the rx buffer posting rings.
8379 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8380 struct tg3_rx_buffer_desc *rxd;
8382 rxd = &tpr->rx_std[i];
8383 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8384 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8385 rxd->opaque = (RXD_OPAQUE_RING_STD |
8386 (i << RXD_OPAQUE_INDEX_SHIFT));
8389 /* Now allocate fresh SKBs for each rx ring. */
8390 for (i = 0; i < tp->rx_pending; i++) {
8391 unsigned int frag_size;
8393 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8395 netdev_warn(tp->dev,
8396 "Using a smaller RX standard ring. Only "
8397 "%d out of %d buffers were allocated "
8398 "successfully\n", i, tp->rx_pending);
8406 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8409 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8411 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8414 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8415 struct tg3_rx_buffer_desc *rxd;
8417 rxd = &tpr->rx_jmb[i].std;
8418 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8419 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8421 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8422 (i << RXD_OPAQUE_INDEX_SHIFT));
8425 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8426 unsigned int frag_size;
8428 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8430 netdev_warn(tp->dev,
8431 "Using a smaller RX jumbo ring. Only %d "
8432 "out of %d buffers were allocated "
8433 "successfully\n", i, tp->rx_jumbo_pending);
8436 tp->rx_jumbo_pending = i;
8445 tg3_rx_prodring_free(tp, tpr);
8449 static void tg3_rx_prodring_fini(struct tg3 *tp,
8450 struct tg3_rx_prodring_set *tpr)
8452 kfree(tpr->rx_std_buffers);
8453 tpr->rx_std_buffers = NULL;
8454 kfree(tpr->rx_jmb_buffers);
8455 tpr->rx_jmb_buffers = NULL;
8457 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8458 tpr->rx_std, tpr->rx_std_mapping);
8462 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8463 tpr->rx_jmb, tpr->rx_jmb_mapping);
8468 static int tg3_rx_prodring_init(struct tg3 *tp,
8469 struct tg3_rx_prodring_set *tpr)
8471 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8473 if (!tpr->rx_std_buffers)
8476 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8477 TG3_RX_STD_RING_BYTES(tp),
8478 &tpr->rx_std_mapping,
8483 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8484 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8486 if (!tpr->rx_jmb_buffers)
8489 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8490 TG3_RX_JMB_RING_BYTES(tp),
8491 &tpr->rx_jmb_mapping,
8500 tg3_rx_prodring_fini(tp, tpr);
8504 /* Free up pending packets in all rx/tx rings.
8506 * The chip has been shut down and the driver detached from
8507 * the networking, so no interrupts or new tx packets will
8508 * end up in the driver. tp->{tx,}lock is not held and we are not
8509 * in an interrupt context and thus may sleep.
8511 static void tg3_free_rings(struct tg3 *tp)
8515 for (j = 0; j < tp->irq_cnt; j++) {
8516 struct tg3_napi *tnapi = &tp->napi[j];
8518 tg3_rx_prodring_free(tp, &tnapi->prodring);
8520 if (!tnapi->tx_buffers)
8523 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8524 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8529 tg3_tx_skb_unmap(tnapi, i,
8530 skb_shinfo(skb)->nr_frags - 1);
8532 dev_kfree_skb_any(skb);
8534 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8538 /* Initialize tx/rx rings for packet processing.
8540 * The chip has been shut down and the driver detached from
8541 * the networking, so no interrupts or new tx packets will
8542 * end up in the driver. tp->{tx,}lock are held and thus
8545 static int tg3_init_rings(struct tg3 *tp)
8549 /* Free up all the SKBs. */
8552 for (i = 0; i < tp->irq_cnt; i++) {
8553 struct tg3_napi *tnapi = &tp->napi[i];
8555 tnapi->last_tag = 0;
8556 tnapi->last_irq_tag = 0;
8557 tnapi->hw_status->status = 0;
8558 tnapi->hw_status->status_tag = 0;
8559 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8564 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8566 tnapi->rx_rcb_ptr = 0;
8568 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8570 if (tnapi->prodring.rx_std &&
8571 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8580 static void tg3_mem_tx_release(struct tg3 *tp)
8584 for (i = 0; i < tp->irq_max; i++) {
8585 struct tg3_napi *tnapi = &tp->napi[i];
8587 if (tnapi->tx_ring) {
8588 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8589 tnapi->tx_ring, tnapi->tx_desc_mapping);
8590 tnapi->tx_ring = NULL;
8593 kfree(tnapi->tx_buffers);
8594 tnapi->tx_buffers = NULL;
8598 static int tg3_mem_tx_acquire(struct tg3 *tp)
8601 struct tg3_napi *tnapi = &tp->napi[0];
8603 /* If multivector TSS is enabled, vector 0 does not handle
8604 * tx interrupts. Don't allocate any resources for it.
8606 if (tg3_flag(tp, ENABLE_TSS))
8609 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8610 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8611 TG3_TX_RING_SIZE, GFP_KERNEL);
8612 if (!tnapi->tx_buffers)
8615 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8617 &tnapi->tx_desc_mapping,
8619 if (!tnapi->tx_ring)
8626 tg3_mem_tx_release(tp);
8630 static void tg3_mem_rx_release(struct tg3 *tp)
8634 for (i = 0; i < tp->irq_max; i++) {
8635 struct tg3_napi *tnapi = &tp->napi[i];
8637 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8642 dma_free_coherent(&tp->pdev->dev,
8643 TG3_RX_RCB_RING_BYTES(tp),
8645 tnapi->rx_rcb_mapping);
8646 tnapi->rx_rcb = NULL;
8650 static int tg3_mem_rx_acquire(struct tg3 *tp)
8652 unsigned int i, limit;
8654 limit = tp->rxq_cnt;
8656 /* If RSS is enabled, we need a (dummy) producer ring
8657 * set on vector zero. This is the true hw prodring.
8659 if (tg3_flag(tp, ENABLE_RSS))
8662 for (i = 0; i < limit; i++) {
8663 struct tg3_napi *tnapi = &tp->napi[i];
8665 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8668 /* If multivector RSS is enabled, vector 0
8669 * does not handle rx or tx interrupts.
8670 * Don't allocate any resources for it.
8672 if (!i && tg3_flag(tp, ENABLE_RSS))
8675 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8676 TG3_RX_RCB_RING_BYTES(tp),
8677 &tnapi->rx_rcb_mapping,
8686 tg3_mem_rx_release(tp);
8691 * Must not be invoked with interrupt sources disabled and
8692 * the hardware shutdown down.
8694 static void tg3_free_consistent(struct tg3 *tp)
8698 for (i = 0; i < tp->irq_cnt; i++) {
8699 struct tg3_napi *tnapi = &tp->napi[i];
8701 if (tnapi->hw_status) {
8702 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8704 tnapi->status_mapping);
8705 tnapi->hw_status = NULL;
8709 tg3_mem_rx_release(tp);
8710 tg3_mem_tx_release(tp);
8713 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8714 tp->hw_stats, tp->stats_mapping);
8715 tp->hw_stats = NULL;
8720 * Must not be invoked with interrupt sources disabled and
8721 * the hardware shutdown down. Can sleep.
8723 static int tg3_alloc_consistent(struct tg3 *tp)
8727 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8728 sizeof(struct tg3_hw_stats),
8729 &tp->stats_mapping, GFP_KERNEL);
8733 for (i = 0; i < tp->irq_cnt; i++) {
8734 struct tg3_napi *tnapi = &tp->napi[i];
8735 struct tg3_hw_status *sblk;
8737 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8739 &tnapi->status_mapping,
8741 if (!tnapi->hw_status)
8744 sblk = tnapi->hw_status;
8746 if (tg3_flag(tp, ENABLE_RSS)) {
8747 u16 *prodptr = NULL;
8750 * When RSS is enabled, the status block format changes
8751 * slightly. The "rx_jumbo_consumer", "reserved",
8752 * and "rx_mini_consumer" members get mapped to the
8753 * other three rx return ring producer indexes.
8757 prodptr = &sblk->idx[0].rx_producer;
8760 prodptr = &sblk->rx_jumbo_consumer;
8763 prodptr = &sblk->reserved;
8766 prodptr = &sblk->rx_mini_consumer;
8769 tnapi->rx_rcb_prod_idx = prodptr;
8771 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8775 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8781 tg3_free_consistent(tp);
8785 #define MAX_WAIT_CNT 1000
8787 /* To stop a block, clear the enable bit and poll till it
8788 * clears. tp->lock is held.
8790 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8795 if (tg3_flag(tp, 5705_PLUS)) {
8802 /* We can't enable/disable these bits of the
8803 * 5705/5750, just say success.
8816 for (i = 0; i < MAX_WAIT_CNT; i++) {
8817 if (pci_channel_offline(tp->pdev)) {
8818 dev_err(&tp->pdev->dev,
8819 "tg3_stop_block device offline, "
8820 "ofs=%lx enable_bit=%x\n",
8827 if ((val & enable_bit) == 0)
8831 if (i == MAX_WAIT_CNT && !silent) {
8832 dev_err(&tp->pdev->dev,
8833 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8841 /* tp->lock is held. */
8842 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8846 tg3_disable_ints(tp);
8848 if (pci_channel_offline(tp->pdev)) {
8849 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8850 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8855 tp->rx_mode &= ~RX_MODE_ENABLE;
8856 tw32_f(MAC_RX_MODE, tp->rx_mode);
8859 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8860 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8861 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8862 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8863 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8866 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8867 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8868 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8869 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8870 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8871 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8872 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8874 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8875 tw32_f(MAC_MODE, tp->mac_mode);
8878 tp->tx_mode &= ~TX_MODE_ENABLE;
8879 tw32_f(MAC_TX_MODE, tp->tx_mode);
8881 for (i = 0; i < MAX_WAIT_CNT; i++) {
8883 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8886 if (i >= MAX_WAIT_CNT) {
8887 dev_err(&tp->pdev->dev,
8888 "%s timed out, TX_MODE_ENABLE will not clear "
8889 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8893 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8894 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8895 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8897 tw32(FTQ_RESET, 0xffffffff);
8898 tw32(FTQ_RESET, 0x00000000);
8900 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8901 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8904 for (i = 0; i < tp->irq_cnt; i++) {
8905 struct tg3_napi *tnapi = &tp->napi[i];
8906 if (tnapi->hw_status)
8907 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8913 /* Save PCI command register before chip reset */
8914 static void tg3_save_pci_state(struct tg3 *tp)
8916 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8919 /* Restore PCI state after chip reset */
8920 static void tg3_restore_pci_state(struct tg3 *tp)
8924 /* Re-enable indirect register accesses. */
8925 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8926 tp->misc_host_ctrl);
8928 /* Set MAX PCI retry to zero. */
8929 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8930 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8931 tg3_flag(tp, PCIX_MODE))
8932 val |= PCISTATE_RETRY_SAME_DMA;
8933 /* Allow reads and writes to the APE register and memory space. */
8934 if (tg3_flag(tp, ENABLE_APE))
8935 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8936 PCISTATE_ALLOW_APE_SHMEM_WR |
8937 PCISTATE_ALLOW_APE_PSPACE_WR;
8938 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8940 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8942 if (!tg3_flag(tp, PCI_EXPRESS)) {
8943 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8944 tp->pci_cacheline_sz);
8945 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8949 /* Make sure PCI-X relaxed ordering bit is clear. */
8950 if (tg3_flag(tp, PCIX_MODE)) {
8953 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8955 pcix_cmd &= ~PCI_X_CMD_ERO;
8956 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8960 if (tg3_flag(tp, 5780_CLASS)) {
8962 /* Chip reset on 5780 will reset MSI enable bit,
8963 * so need to restore it.
8965 if (tg3_flag(tp, USING_MSI)) {
8968 pci_read_config_word(tp->pdev,
8969 tp->msi_cap + PCI_MSI_FLAGS,
8971 pci_write_config_word(tp->pdev,
8972 tp->msi_cap + PCI_MSI_FLAGS,
8973 ctrl | PCI_MSI_FLAGS_ENABLE);
8974 val = tr32(MSGINT_MODE);
8975 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8980 static void tg3_override_clk(struct tg3 *tp)
8984 switch (tg3_asic_rev(tp)) {
8986 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8987 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8988 TG3_CPMU_MAC_ORIDE_ENABLE);
8993 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9001 static void tg3_restore_clk(struct tg3 *tp)
9005 switch (tg3_asic_rev(tp)) {
9007 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9008 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9009 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9014 val = tr32(TG3_CPMU_CLCK_ORIDE);
9015 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9023 /* tp->lock is held. */
9024 static int tg3_chip_reset(struct tg3 *tp)
9025 __releases(tp->lock)
9026 __acquires(tp->lock)
9029 void (*write_op)(struct tg3 *, u32, u32);
9032 if (!pci_device_is_present(tp->pdev))
9037 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9039 /* No matching tg3_nvram_unlock() after this because
9040 * chip reset below will undo the nvram lock.
9042 tp->nvram_lock_cnt = 0;
9044 /* GRC_MISC_CFG core clock reset will clear the memory
9045 * enable bit in PCI register 4 and the MSI enable bit
9046 * on some chips, so we save relevant registers here.
9048 tg3_save_pci_state(tp);
9050 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9051 tg3_flag(tp, 5755_PLUS))
9052 tw32(GRC_FASTBOOT_PC, 0);
9055 * We must avoid the readl() that normally takes place.
9056 * It locks machines, causes machine checks, and other
9057 * fun things. So, temporarily disable the 5701
9058 * hardware workaround, while we do the reset.
9060 write_op = tp->write32;
9061 if (write_op == tg3_write_flush_reg32)
9062 tp->write32 = tg3_write32;
9064 /* Prevent the irq handler from reading or writing PCI registers
9065 * during chip reset when the memory enable bit in the PCI command
9066 * register may be cleared. The chip does not generate interrupt
9067 * at this time, but the irq handler may still be called due to irq
9068 * sharing or irqpoll.
9070 tg3_flag_set(tp, CHIP_RESETTING);
9071 for (i = 0; i < tp->irq_cnt; i++) {
9072 struct tg3_napi *tnapi = &tp->napi[i];
9073 if (tnapi->hw_status) {
9074 tnapi->hw_status->status = 0;
9075 tnapi->hw_status->status_tag = 0;
9077 tnapi->last_tag = 0;
9078 tnapi->last_irq_tag = 0;
9082 tg3_full_unlock(tp);
9084 for (i = 0; i < tp->irq_cnt; i++)
9085 synchronize_irq(tp->napi[i].irq_vec);
9087 tg3_full_lock(tp, 0);
9089 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9090 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9091 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9095 val = GRC_MISC_CFG_CORECLK_RESET;
9097 if (tg3_flag(tp, PCI_EXPRESS)) {
9098 /* Force PCIe 1.0a mode */
9099 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9100 !tg3_flag(tp, 57765_PLUS) &&
9101 tr32(TG3_PCIE_PHY_TSTCTL) ==
9102 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9103 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9105 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9106 tw32(GRC_MISC_CFG, (1 << 29));
9111 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9112 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9113 tw32(GRC_VCPU_EXT_CTRL,
9114 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9117 /* Set the clock to the highest frequency to avoid timeouts. With link
9118 * aware mode, the clock speed could be slow and bootcode does not
9119 * complete within the expected time. Override the clock to allow the
9120 * bootcode to finish sooner and then restore it.
9122 tg3_override_clk(tp);
9124 /* Manage gphy power for all CPMU absent PCIe devices. */
9125 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9126 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9128 tw32(GRC_MISC_CFG, val);
9130 /* restore 5701 hardware bug workaround write method */
9131 tp->write32 = write_op;
9133 /* Unfortunately, we have to delay before the PCI read back.
9134 * Some 575X chips even will not respond to a PCI cfg access
9135 * when the reset command is given to the chip.
9137 * How do these hardware designers expect things to work
9138 * properly if the PCI write is posted for a long period
9139 * of time? It is always necessary to have some method by
9140 * which a register read back can occur to push the write
9141 * out which does the reset.
9143 * For most tg3 variants the trick below was working.
9148 /* Flush PCI posted writes. The normal MMIO registers
9149 * are inaccessible at this time so this is the only
9150 * way to make this reliably (actually, this is no longer
9151 * the case, see above). I tried to use indirect
9152 * register read/write but this upset some 5701 variants.
9154 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9158 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9161 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9165 /* Wait for link training to complete. */
9166 for (j = 0; j < 5000; j++)
9169 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9170 pci_write_config_dword(tp->pdev, 0xc4,
9171 cfg_val | (1 << 15));
9174 /* Clear the "no snoop" and "relaxed ordering" bits. */
9175 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9177 * Older PCIe devices only support the 128 byte
9178 * MPS setting. Enforce the restriction.
9180 if (!tg3_flag(tp, CPMU_PRESENT))
9181 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9182 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9184 /* Clear error status */
9185 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9186 PCI_EXP_DEVSTA_CED |
9187 PCI_EXP_DEVSTA_NFED |
9188 PCI_EXP_DEVSTA_FED |
9189 PCI_EXP_DEVSTA_URD);
9192 tg3_restore_pci_state(tp);
9194 tg3_flag_clear(tp, CHIP_RESETTING);
9195 tg3_flag_clear(tp, ERROR_PROCESSED);
9198 if (tg3_flag(tp, 5780_CLASS))
9199 val = tr32(MEMARB_MODE);
9200 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9202 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9204 tw32(0x5000, 0x400);
9207 if (tg3_flag(tp, IS_SSB_CORE)) {
9209 * BCM4785: In order to avoid repercussions from using
9210 * potentially defective internal ROM, stop the Rx RISC CPU,
9211 * which is not required.
9214 tg3_halt_cpu(tp, RX_CPU_BASE);
9217 err = tg3_poll_fw(tp);
9221 tw32(GRC_MODE, tp->grc_mode);
9223 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9226 tw32(0xc4, val | (1 << 15));
9229 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9230 tg3_asic_rev(tp) == ASIC_REV_5705) {
9231 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9232 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9233 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9234 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9237 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9238 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9240 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9241 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9246 tw32_f(MAC_MODE, val);
9249 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9253 if (tg3_flag(tp, PCI_EXPRESS) &&
9254 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9255 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9256 !tg3_flag(tp, 57765_PLUS)) {
9259 tw32(0x7c00, val | (1 << 25));
9262 tg3_restore_clk(tp);
9264 /* Reprobe ASF enable state. */
9265 tg3_flag_clear(tp, ENABLE_ASF);
9266 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9267 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9269 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9270 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9271 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9274 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9275 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9276 tg3_flag_set(tp, ENABLE_ASF);
9277 tp->last_event_jiffies = jiffies;
9278 if (tg3_flag(tp, 5750_PLUS))
9279 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9281 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9282 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9283 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9284 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9285 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9292 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9293 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9294 static void __tg3_set_rx_mode(struct net_device *);
9296 /* tp->lock is held. */
9297 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9303 tg3_write_sig_pre_reset(tp, kind);
9305 tg3_abort_hw(tp, silent);
9306 err = tg3_chip_reset(tp);
9308 __tg3_set_mac_addr(tp, false);
9310 tg3_write_sig_legacy(tp, kind);
9311 tg3_write_sig_post_reset(tp, kind);
9314 /* Save the stats across chip resets... */
9315 tg3_get_nstats(tp, &tp->net_stats_prev);
9316 tg3_get_estats(tp, &tp->estats_prev);
9318 /* And make sure the next sample is new data */
9319 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9325 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9327 struct tg3 *tp = netdev_priv(dev);
9328 struct sockaddr *addr = p;
9330 bool skip_mac_1 = false;
9332 if (!is_valid_ether_addr(addr->sa_data))
9333 return -EADDRNOTAVAIL;
9335 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9337 if (!netif_running(dev))
9340 if (tg3_flag(tp, ENABLE_ASF)) {
9341 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9343 addr0_high = tr32(MAC_ADDR_0_HIGH);
9344 addr0_low = tr32(MAC_ADDR_0_LOW);
9345 addr1_high = tr32(MAC_ADDR_1_HIGH);
9346 addr1_low = tr32(MAC_ADDR_1_LOW);
9348 /* Skip MAC addr 1 if ASF is using it. */
9349 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9350 !(addr1_high == 0 && addr1_low == 0))
9353 spin_lock_bh(&tp->lock);
9354 __tg3_set_mac_addr(tp, skip_mac_1);
9355 __tg3_set_rx_mode(dev);
9356 spin_unlock_bh(&tp->lock);
9361 /* tp->lock is held. */
9362 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9363 dma_addr_t mapping, u32 maxlen_flags,
9367 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9368 ((u64) mapping >> 32));
9370 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9371 ((u64) mapping & 0xffffffff));
9373 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9376 if (!tg3_flag(tp, 5705_PLUS))
9378 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9383 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9387 if (!tg3_flag(tp, ENABLE_TSS)) {
9388 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9389 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9390 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9392 tw32(HOSTCC_TXCOL_TICKS, 0);
9393 tw32(HOSTCC_TXMAX_FRAMES, 0);
9394 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9396 for (; i < tp->txq_cnt; i++) {
9399 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9400 tw32(reg, ec->tx_coalesce_usecs);
9401 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9402 tw32(reg, ec->tx_max_coalesced_frames);
9403 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9404 tw32(reg, ec->tx_max_coalesced_frames_irq);
9408 for (; i < tp->irq_max - 1; i++) {
9409 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9410 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9411 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9415 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9418 u32 limit = tp->rxq_cnt;
9420 if (!tg3_flag(tp, ENABLE_RSS)) {
9421 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9422 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9423 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9426 tw32(HOSTCC_RXCOL_TICKS, 0);
9427 tw32(HOSTCC_RXMAX_FRAMES, 0);
9428 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9431 for (; i < limit; i++) {
9434 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9435 tw32(reg, ec->rx_coalesce_usecs);
9436 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9437 tw32(reg, ec->rx_max_coalesced_frames);
9438 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9439 tw32(reg, ec->rx_max_coalesced_frames_irq);
9442 for (; i < tp->irq_max - 1; i++) {
9443 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9444 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9445 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9449 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9451 tg3_coal_tx_init(tp, ec);
9452 tg3_coal_rx_init(tp, ec);
9454 if (!tg3_flag(tp, 5705_PLUS)) {
9455 u32 val = ec->stats_block_coalesce_usecs;
9457 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9458 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9463 tw32(HOSTCC_STAT_COAL_TICKS, val);
9467 /* tp->lock is held. */
9468 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9472 /* Disable all transmit rings but the first. */
9473 if (!tg3_flag(tp, 5705_PLUS))
9474 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9475 else if (tg3_flag(tp, 5717_PLUS))
9476 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9477 else if (tg3_flag(tp, 57765_CLASS) ||
9478 tg3_asic_rev(tp) == ASIC_REV_5762)
9479 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9481 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9483 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9484 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9485 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9486 BDINFO_FLAGS_DISABLED);
9489 /* tp->lock is held. */
9490 static void tg3_tx_rcbs_init(struct tg3 *tp)
9493 u32 txrcb = NIC_SRAM_SEND_RCB;
9495 if (tg3_flag(tp, ENABLE_TSS))
9498 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9499 struct tg3_napi *tnapi = &tp->napi[i];
9501 if (!tnapi->tx_ring)
9504 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9505 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9506 NIC_SRAM_TX_BUFFER_DESC);
9510 /* tp->lock is held. */
9511 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9515 /* Disable all receive return rings but the first. */
9516 if (tg3_flag(tp, 5717_PLUS))
9517 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9518 else if (!tg3_flag(tp, 5705_PLUS))
9519 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9520 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9521 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9522 tg3_flag(tp, 57765_CLASS))
9523 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9525 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9527 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9528 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9529 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9530 BDINFO_FLAGS_DISABLED);
9533 /* tp->lock is held. */
9534 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9537 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9539 if (tg3_flag(tp, ENABLE_RSS))
9542 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9543 struct tg3_napi *tnapi = &tp->napi[i];
9548 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9549 (tp->rx_ret_ring_mask + 1) <<
9550 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9554 /* tp->lock is held. */
9555 static void tg3_rings_reset(struct tg3 *tp)
9559 struct tg3_napi *tnapi = &tp->napi[0];
9561 tg3_tx_rcbs_disable(tp);
9563 tg3_rx_ret_rcbs_disable(tp);
9565 /* Disable interrupts */
9566 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9567 tp->napi[0].chk_msi_cnt = 0;
9568 tp->napi[0].last_rx_cons = 0;
9569 tp->napi[0].last_tx_cons = 0;
9571 /* Zero mailbox registers. */
9572 if (tg3_flag(tp, SUPPORT_MSIX)) {
9573 for (i = 1; i < tp->irq_max; i++) {
9574 tp->napi[i].tx_prod = 0;
9575 tp->napi[i].tx_cons = 0;
9576 if (tg3_flag(tp, ENABLE_TSS))
9577 tw32_mailbox(tp->napi[i].prodmbox, 0);
9578 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9579 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9580 tp->napi[i].chk_msi_cnt = 0;
9581 tp->napi[i].last_rx_cons = 0;
9582 tp->napi[i].last_tx_cons = 0;
9584 if (!tg3_flag(tp, ENABLE_TSS))
9585 tw32_mailbox(tp->napi[0].prodmbox, 0);
9587 tp->napi[0].tx_prod = 0;
9588 tp->napi[0].tx_cons = 0;
9589 tw32_mailbox(tp->napi[0].prodmbox, 0);
9590 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9593 /* Make sure the NIC-based send BD rings are disabled. */
9594 if (!tg3_flag(tp, 5705_PLUS)) {
9595 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9596 for (i = 0; i < 16; i++)
9597 tw32_tx_mbox(mbox + i * 8, 0);
9600 /* Clear status block in ram. */
9601 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9603 /* Set status block DMA address */
9604 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9605 ((u64) tnapi->status_mapping >> 32));
9606 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9607 ((u64) tnapi->status_mapping & 0xffffffff));
9609 stblk = HOSTCC_STATBLCK_RING1;
9611 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9612 u64 mapping = (u64)tnapi->status_mapping;
9613 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9614 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9617 /* Clear status block in ram. */
9618 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9621 tg3_tx_rcbs_init(tp);
9622 tg3_rx_ret_rcbs_init(tp);
9625 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9627 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9629 if (!tg3_flag(tp, 5750_PLUS) ||
9630 tg3_flag(tp, 5780_CLASS) ||
9631 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9632 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9633 tg3_flag(tp, 57765_PLUS))
9634 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9635 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9636 tg3_asic_rev(tp) == ASIC_REV_5787)
9637 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9639 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9641 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9642 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9644 val = min(nic_rep_thresh, host_rep_thresh);
9645 tw32(RCVBDI_STD_THRESH, val);
9647 if (tg3_flag(tp, 57765_PLUS))
9648 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9650 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9653 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9655 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9657 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9658 tw32(RCVBDI_JUMBO_THRESH, val);
9660 if (tg3_flag(tp, 57765_PLUS))
9661 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9664 static inline u32 calc_crc(unsigned char *buf, int len)
9672 for (j = 0; j < len; j++) {
9675 for (k = 0; k < 8; k++) {
9688 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9690 /* accept or reject all multicast frames */
9691 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9692 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9693 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9694 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9697 static void __tg3_set_rx_mode(struct net_device *dev)
9699 struct tg3 *tp = netdev_priv(dev);
9702 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9703 RX_MODE_KEEP_VLAN_TAG);
9705 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9706 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9709 if (!tg3_flag(tp, ENABLE_ASF))
9710 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9713 if (dev->flags & IFF_PROMISC) {
9714 /* Promiscuous mode. */
9715 rx_mode |= RX_MODE_PROMISC;
9716 } else if (dev->flags & IFF_ALLMULTI) {
9717 /* Accept all multicast. */
9718 tg3_set_multi(tp, 1);
9719 } else if (netdev_mc_empty(dev)) {
9720 /* Reject all multicast. */
9721 tg3_set_multi(tp, 0);
9723 /* Accept one or more multicast(s). */
9724 struct netdev_hw_addr *ha;
9725 u32 mc_filter[4] = { 0, };
9730 netdev_for_each_mc_addr(ha, dev) {
9731 crc = calc_crc(ha->addr, ETH_ALEN);
9733 regidx = (bit & 0x60) >> 5;
9735 mc_filter[regidx] |= (1 << bit);
9738 tw32(MAC_HASH_REG_0, mc_filter[0]);
9739 tw32(MAC_HASH_REG_1, mc_filter[1]);
9740 tw32(MAC_HASH_REG_2, mc_filter[2]);
9741 tw32(MAC_HASH_REG_3, mc_filter[3]);
9744 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9745 rx_mode |= RX_MODE_PROMISC;
9746 } else if (!(dev->flags & IFF_PROMISC)) {
9747 /* Add all entries into to the mac addr filter list */
9749 struct netdev_hw_addr *ha;
9751 netdev_for_each_uc_addr(ha, dev) {
9752 __tg3_set_one_mac_addr(tp, ha->addr,
9753 i + TG3_UCAST_ADDR_IDX(tp));
9758 if (rx_mode != tp->rx_mode) {
9759 tp->rx_mode = rx_mode;
9760 tw32_f(MAC_RX_MODE, rx_mode);
9765 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9769 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9770 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9773 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9777 if (!tg3_flag(tp, SUPPORT_MSIX))
9780 if (tp->rxq_cnt == 1) {
9781 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9785 /* Validate table against current IRQ count */
9786 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9787 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9791 if (i != TG3_RSS_INDIR_TBL_SIZE)
9792 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9795 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9798 u32 reg = MAC_RSS_INDIR_TBL_0;
9800 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9801 u32 val = tp->rss_ind_tbl[i];
9803 for (; i % 8; i++) {
9805 val |= tp->rss_ind_tbl[i];
9812 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9814 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9815 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9817 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9820 /* tp->lock is held. */
9821 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9823 u32 val, rdmac_mode;
9825 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9827 tg3_disable_ints(tp);
9831 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9833 if (tg3_flag(tp, INIT_COMPLETE))
9834 tg3_abort_hw(tp, 1);
9836 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9837 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9838 tg3_phy_pull_config(tp);
9839 tg3_eee_pull_config(tp, NULL);
9840 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9843 /* Enable MAC control of LPI */
9844 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9850 err = tg3_chip_reset(tp);
9854 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9856 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9857 val = tr32(TG3_CPMU_CTRL);
9858 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9859 tw32(TG3_CPMU_CTRL, val);
9861 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9862 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9863 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9864 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9866 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9867 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9868 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9869 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9871 val = tr32(TG3_CPMU_HST_ACC);
9872 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9873 val |= CPMU_HST_ACC_MACCLK_6_25;
9874 tw32(TG3_CPMU_HST_ACC, val);
9877 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9878 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9879 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9880 PCIE_PWR_MGMT_L1_THRESH_4MS;
9881 tw32(PCIE_PWR_MGMT_THRESH, val);
9883 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9884 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9886 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9888 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9889 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9892 if (tg3_flag(tp, L1PLLPD_EN)) {
9893 u32 grc_mode = tr32(GRC_MODE);
9895 /* Access the lower 1K of PL PCIE block registers. */
9896 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9897 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9899 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9900 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9901 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9903 tw32(GRC_MODE, grc_mode);
9906 if (tg3_flag(tp, 57765_CLASS)) {
9907 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9908 u32 grc_mode = tr32(GRC_MODE);
9910 /* Access the lower 1K of PL PCIE block registers. */
9911 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9912 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9914 val = tr32(TG3_PCIE_TLDLPL_PORT +
9915 TG3_PCIE_PL_LO_PHYCTL5);
9916 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9917 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9919 tw32(GRC_MODE, grc_mode);
9922 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9925 /* Fix transmit hangs */
9926 val = tr32(TG3_CPMU_PADRNG_CTL);
9927 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9928 tw32(TG3_CPMU_PADRNG_CTL, val);
9930 grc_mode = tr32(GRC_MODE);
9932 /* Access the lower 1K of DL PCIE block registers. */
9933 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9934 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9936 val = tr32(TG3_PCIE_TLDLPL_PORT +
9937 TG3_PCIE_DL_LO_FTSMAX);
9938 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9939 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9940 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9942 tw32(GRC_MODE, grc_mode);
9945 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9946 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9947 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9948 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9951 /* This works around an issue with Athlon chipsets on
9952 * B3 tigon3 silicon. This bit has no effect on any
9953 * other revision. But do not set this on PCI Express
9954 * chips and don't even touch the clocks if the CPMU is present.
9956 if (!tg3_flag(tp, CPMU_PRESENT)) {
9957 if (!tg3_flag(tp, PCI_EXPRESS))
9958 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9959 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9962 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9963 tg3_flag(tp, PCIX_MODE)) {
9964 val = tr32(TG3PCI_PCISTATE);
9965 val |= PCISTATE_RETRY_SAME_DMA;
9966 tw32(TG3PCI_PCISTATE, val);
9969 if (tg3_flag(tp, ENABLE_APE)) {
9970 /* Allow reads and writes to the
9971 * APE register and memory space.
9973 val = tr32(TG3PCI_PCISTATE);
9974 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9975 PCISTATE_ALLOW_APE_SHMEM_WR |
9976 PCISTATE_ALLOW_APE_PSPACE_WR;
9977 tw32(TG3PCI_PCISTATE, val);
9980 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9981 /* Enable some hw fixes. */
9982 val = tr32(TG3PCI_MSI_DATA);
9983 val |= (1 << 26) | (1 << 28) | (1 << 29);
9984 tw32(TG3PCI_MSI_DATA, val);
9987 /* Descriptor ring init may make accesses to the
9988 * NIC SRAM area to setup the TX descriptors, so we
9989 * can only do this after the hardware has been
9990 * successfully reset.
9992 err = tg3_init_rings(tp);
9996 if (tg3_flag(tp, 57765_PLUS)) {
9997 val = tr32(TG3PCI_DMA_RW_CTRL) &
9998 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9999 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10000 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
10001 if (!tg3_flag(tp, 57765_CLASS) &&
10002 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10003 tg3_asic_rev(tp) != ASIC_REV_5762)
10004 val |= DMA_RWCTRL_TAGGED_STAT_WA;
10005 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10006 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10007 tg3_asic_rev(tp) != ASIC_REV_5761) {
10008 /* This value is determined during the probe time DMA
10009 * engine test, tg3_test_dma.
10011 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10014 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10015 GRC_MODE_4X_NIC_SEND_RINGS |
10016 GRC_MODE_NO_TX_PHDR_CSUM |
10017 GRC_MODE_NO_RX_PHDR_CSUM);
10018 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10020 /* Pseudo-header checksum is done by hardware logic and not
10021 * the offload processers, so make the chip do the pseudo-
10022 * header checksums on receive. For transmit it is more
10023 * convenient to do the pseudo-header checksum in software
10024 * as Linux does that on transmit for us in all cases.
10026 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10028 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10030 tw32(TG3_RX_PTP_CTL,
10031 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10033 if (tg3_flag(tp, PTP_CAPABLE))
10034 val |= GRC_MODE_TIME_SYNC_ENABLE;
10036 tw32(GRC_MODE, tp->grc_mode | val);
10038 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10039 val = tr32(GRC_MISC_CFG);
10041 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10042 tw32(GRC_MISC_CFG, val);
10044 /* Initialize MBUF/DESC pool. */
10045 if (tg3_flag(tp, 5750_PLUS)) {
10047 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10048 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10049 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10050 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10052 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10053 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10054 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10055 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10058 fw_len = tp->fw_len;
10059 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10060 tw32(BUFMGR_MB_POOL_ADDR,
10061 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10062 tw32(BUFMGR_MB_POOL_SIZE,
10063 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10066 if (tp->dev->mtu <= ETH_DATA_LEN) {
10067 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10068 tp->bufmgr_config.mbuf_read_dma_low_water);
10069 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10070 tp->bufmgr_config.mbuf_mac_rx_low_water);
10071 tw32(BUFMGR_MB_HIGH_WATER,
10072 tp->bufmgr_config.mbuf_high_water);
10074 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10075 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10076 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10077 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10078 tw32(BUFMGR_MB_HIGH_WATER,
10079 tp->bufmgr_config.mbuf_high_water_jumbo);
10081 tw32(BUFMGR_DMA_LOW_WATER,
10082 tp->bufmgr_config.dma_low_water);
10083 tw32(BUFMGR_DMA_HIGH_WATER,
10084 tp->bufmgr_config.dma_high_water);
10086 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10087 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10088 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10089 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10090 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10091 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10092 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10093 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10094 tw32(BUFMGR_MODE, val);
10095 for (i = 0; i < 2000; i++) {
10096 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10101 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10105 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10106 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10108 tg3_setup_rxbd_thresholds(tp);
10110 /* Initialize TG3_BDINFO's at:
10111 * RCVDBDI_STD_BD: standard eth size rx ring
10112 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10113 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10116 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10117 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10118 * ring attribute flags
10119 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10121 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10122 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10124 * The size of each ring is fixed in the firmware, but the location is
10127 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10128 ((u64) tpr->rx_std_mapping >> 32));
10129 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10130 ((u64) tpr->rx_std_mapping & 0xffffffff));
10131 if (!tg3_flag(tp, 5717_PLUS))
10132 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10133 NIC_SRAM_RX_BUFFER_DESC);
10135 /* Disable the mini ring */
10136 if (!tg3_flag(tp, 5705_PLUS))
10137 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10138 BDINFO_FLAGS_DISABLED);
10140 /* Program the jumbo buffer descriptor ring control
10141 * blocks on those devices that have them.
10143 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10144 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10146 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10147 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10148 ((u64) tpr->rx_jmb_mapping >> 32));
10149 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10150 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10151 val = TG3_RX_JMB_RING_SIZE(tp) <<
10152 BDINFO_FLAGS_MAXLEN_SHIFT;
10153 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10154 val | BDINFO_FLAGS_USE_EXT_RECV);
10155 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10156 tg3_flag(tp, 57765_CLASS) ||
10157 tg3_asic_rev(tp) == ASIC_REV_5762)
10158 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10159 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10161 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10162 BDINFO_FLAGS_DISABLED);
10165 if (tg3_flag(tp, 57765_PLUS)) {
10166 val = TG3_RX_STD_RING_SIZE(tp);
10167 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10168 val |= (TG3_RX_STD_DMA_SZ << 2);
10170 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10172 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10174 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10176 tpr->rx_std_prod_idx = tp->rx_pending;
10177 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10179 tpr->rx_jmb_prod_idx =
10180 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10181 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10183 tg3_rings_reset(tp);
10185 /* Initialize MAC address and backoff seed. */
10186 __tg3_set_mac_addr(tp, false);
10188 /* MTU + ethernet header + FCS + optional VLAN tag */
10189 tw32(MAC_RX_MTU_SIZE,
10190 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10192 /* The slot time is changed by tg3_setup_phy if we
10193 * run at gigabit with half duplex.
10195 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10196 (6 << TX_LENGTHS_IPG_SHIFT) |
10197 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10199 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10200 tg3_asic_rev(tp) == ASIC_REV_5762)
10201 val |= tr32(MAC_TX_LENGTHS) &
10202 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10203 TX_LENGTHS_CNT_DWN_VAL_MSK);
10205 tw32(MAC_TX_LENGTHS, val);
10207 /* Receive rules. */
10208 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10209 tw32(RCVLPC_CONFIG, 0x0181);
10211 /* Calculate RDMAC_MODE setting early, we need it to determine
10212 * the RCVLPC_STATE_ENABLE mask.
10214 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10215 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10216 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10217 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10218 RDMAC_MODE_LNGREAD_ENAB);
10220 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10221 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10223 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10224 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10225 tg3_asic_rev(tp) == ASIC_REV_57780)
10226 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10227 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10228 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10230 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10231 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10232 if (tg3_flag(tp, TSO_CAPABLE) &&
10233 tg3_asic_rev(tp) == ASIC_REV_5705) {
10234 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10235 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10236 !tg3_flag(tp, IS_5788)) {
10237 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10241 if (tg3_flag(tp, PCI_EXPRESS))
10242 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10244 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10246 if (tp->dev->mtu <= ETH_DATA_LEN) {
10247 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10248 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10252 if (tg3_flag(tp, HW_TSO_1) ||
10253 tg3_flag(tp, HW_TSO_2) ||
10254 tg3_flag(tp, HW_TSO_3))
10255 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10257 if (tg3_flag(tp, 57765_PLUS) ||
10258 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10259 tg3_asic_rev(tp) == ASIC_REV_57780)
10260 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10262 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10263 tg3_asic_rev(tp) == ASIC_REV_5762)
10264 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10266 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10267 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10268 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10269 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10270 tg3_flag(tp, 57765_PLUS)) {
10273 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10274 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10276 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10278 val = tr32(tgtreg);
10279 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10280 tg3_asic_rev(tp) == ASIC_REV_5762) {
10281 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10282 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10283 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10284 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10285 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10286 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10288 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10291 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10292 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10293 tg3_asic_rev(tp) == ASIC_REV_5762) {
10296 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10297 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10299 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10301 val = tr32(tgtreg);
10303 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10304 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10307 /* Receive/send statistics. */
10308 if (tg3_flag(tp, 5750_PLUS)) {
10309 val = tr32(RCVLPC_STATS_ENABLE);
10310 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10311 tw32(RCVLPC_STATS_ENABLE, val);
10312 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10313 tg3_flag(tp, TSO_CAPABLE)) {
10314 val = tr32(RCVLPC_STATS_ENABLE);
10315 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10316 tw32(RCVLPC_STATS_ENABLE, val);
10318 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10320 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10321 tw32(SNDDATAI_STATSENAB, 0xffffff);
10322 tw32(SNDDATAI_STATSCTRL,
10323 (SNDDATAI_SCTRL_ENABLE |
10324 SNDDATAI_SCTRL_FASTUPD));
10326 /* Setup host coalescing engine. */
10327 tw32(HOSTCC_MODE, 0);
10328 for (i = 0; i < 2000; i++) {
10329 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10334 __tg3_set_coalesce(tp, &tp->coal);
10336 if (!tg3_flag(tp, 5705_PLUS)) {
10337 /* Status/statistics block address. See tg3_timer,
10338 * the tg3_periodic_fetch_stats call there, and
10339 * tg3_get_stats to see how this works for 5705/5750 chips.
10341 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10342 ((u64) tp->stats_mapping >> 32));
10343 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10344 ((u64) tp->stats_mapping & 0xffffffff));
10345 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10347 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10349 /* Clear statistics and status block memory areas */
10350 for (i = NIC_SRAM_STATS_BLK;
10351 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10352 i += sizeof(u32)) {
10353 tg3_write_mem(tp, i, 0);
10358 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10360 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10361 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10362 if (!tg3_flag(tp, 5705_PLUS))
10363 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10365 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10366 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10367 /* reset to prevent losing 1st rx packet intermittently */
10368 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10372 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10373 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10374 MAC_MODE_FHDE_ENABLE;
10375 if (tg3_flag(tp, ENABLE_APE))
10376 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10377 if (!tg3_flag(tp, 5705_PLUS) &&
10378 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10379 tg3_asic_rev(tp) != ASIC_REV_5700)
10380 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10381 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10384 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10385 * If TG3_FLAG_IS_NIC is zero, we should read the
10386 * register to preserve the GPIO settings for LOMs. The GPIOs,
10387 * whether used as inputs or outputs, are set by boot code after
10390 if (!tg3_flag(tp, IS_NIC)) {
10393 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10394 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10395 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10397 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10398 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10399 GRC_LCLCTRL_GPIO_OUTPUT3;
10401 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10402 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10404 tp->grc_local_ctrl &= ~gpio_mask;
10405 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10407 /* GPIO1 must be driven high for eeprom write protect */
10408 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10409 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10410 GRC_LCLCTRL_GPIO_OUTPUT1);
10412 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10415 if (tg3_flag(tp, USING_MSIX)) {
10416 val = tr32(MSGINT_MODE);
10417 val |= MSGINT_MODE_ENABLE;
10418 if (tp->irq_cnt > 1)
10419 val |= MSGINT_MODE_MULTIVEC_EN;
10420 if (!tg3_flag(tp, 1SHOT_MSI))
10421 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10422 tw32(MSGINT_MODE, val);
10425 if (!tg3_flag(tp, 5705_PLUS)) {
10426 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10430 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10431 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10432 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10433 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10434 WDMAC_MODE_LNGREAD_ENAB);
10436 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10437 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10438 if (tg3_flag(tp, TSO_CAPABLE) &&
10439 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10440 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10442 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10443 !tg3_flag(tp, IS_5788)) {
10444 val |= WDMAC_MODE_RX_ACCEL;
10448 /* Enable host coalescing bug fix */
10449 if (tg3_flag(tp, 5755_PLUS))
10450 val |= WDMAC_MODE_STATUS_TAG_FIX;
10452 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10453 val |= WDMAC_MODE_BURST_ALL_DATA;
10455 tw32_f(WDMAC_MODE, val);
10458 if (tg3_flag(tp, PCIX_MODE)) {
10461 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10463 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10464 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10465 pcix_cmd |= PCI_X_CMD_READ_2K;
10466 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10467 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10468 pcix_cmd |= PCI_X_CMD_READ_2K;
10470 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10474 tw32_f(RDMAC_MODE, rdmac_mode);
10477 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10478 tg3_asic_rev(tp) == ASIC_REV_5720) {
10479 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10480 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10483 if (i < TG3_NUM_RDMA_CHANNELS) {
10484 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10485 val |= tg3_lso_rd_dma_workaround_bit(tp);
10486 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10487 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10491 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10492 if (!tg3_flag(tp, 5705_PLUS))
10493 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10495 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10496 tw32(SNDDATAC_MODE,
10497 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10499 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10501 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10502 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10503 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10504 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10505 val |= RCVDBDI_MODE_LRG_RING_SZ;
10506 tw32(RCVDBDI_MODE, val);
10507 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10508 if (tg3_flag(tp, HW_TSO_1) ||
10509 tg3_flag(tp, HW_TSO_2) ||
10510 tg3_flag(tp, HW_TSO_3))
10511 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10512 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10513 if (tg3_flag(tp, ENABLE_TSS))
10514 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10515 tw32(SNDBDI_MODE, val);
10516 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10518 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10519 err = tg3_load_5701_a0_firmware_fix(tp);
10524 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10525 /* Ignore any errors for the firmware download. If download
10526 * fails, the device will operate with EEE disabled
10528 tg3_load_57766_firmware(tp);
10531 if (tg3_flag(tp, TSO_CAPABLE)) {
10532 err = tg3_load_tso_firmware(tp);
10537 tp->tx_mode = TX_MODE_ENABLE;
10539 if (tg3_flag(tp, 5755_PLUS) ||
10540 tg3_asic_rev(tp) == ASIC_REV_5906)
10541 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10543 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10544 tg3_asic_rev(tp) == ASIC_REV_5762) {
10545 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10546 tp->tx_mode &= ~val;
10547 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10550 tw32_f(MAC_TX_MODE, tp->tx_mode);
10553 if (tg3_flag(tp, ENABLE_RSS)) {
10556 tg3_rss_write_indir_tbl(tp);
10558 netdev_rss_key_fill(rss_key, 10 * sizeof(u32));
10560 for (i = 0; i < 10 ; i++)
10561 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10564 tp->rx_mode = RX_MODE_ENABLE;
10565 if (tg3_flag(tp, 5755_PLUS))
10566 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10568 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10569 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10571 if (tg3_flag(tp, ENABLE_RSS))
10572 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10573 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10574 RX_MODE_RSS_IPV6_HASH_EN |
10575 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10576 RX_MODE_RSS_IPV4_HASH_EN |
10577 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10579 tw32_f(MAC_RX_MODE, tp->rx_mode);
10582 tw32(MAC_LED_CTRL, tp->led_ctrl);
10584 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10585 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10586 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10589 tw32_f(MAC_RX_MODE, tp->rx_mode);
10592 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10593 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10594 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10595 /* Set drive transmission level to 1.2V */
10596 /* only if the signal pre-emphasis bit is not set */
10597 val = tr32(MAC_SERDES_CFG);
10600 tw32(MAC_SERDES_CFG, val);
10602 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10603 tw32(MAC_SERDES_CFG, 0x616000);
10606 /* Prevent chip from dropping frames when flow control
10609 if (tg3_flag(tp, 57765_CLASS))
10613 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10615 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10616 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10617 /* Use hardware link auto-negotiation */
10618 tg3_flag_set(tp, HW_AUTONEG);
10621 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10622 tg3_asic_rev(tp) == ASIC_REV_5714) {
10625 tmp = tr32(SERDES_RX_CTRL);
10626 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10627 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10628 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10629 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10632 if (!tg3_flag(tp, USE_PHYLIB)) {
10633 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10634 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10636 err = tg3_setup_phy(tp, false);
10640 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10641 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10644 /* Clear CRC stats. */
10645 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10646 tg3_writephy(tp, MII_TG3_TEST1,
10647 tmp | MII_TG3_TEST1_CRC_EN);
10648 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10653 __tg3_set_rx_mode(tp->dev);
10655 /* Initialize receive rules. */
10656 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10657 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10658 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10659 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10661 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10665 if (tg3_flag(tp, ENABLE_ASF))
10669 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10671 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10673 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10675 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10677 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10679 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10681 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10683 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10685 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10687 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10689 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10691 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10693 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10695 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10703 if (tg3_flag(tp, ENABLE_APE))
10704 /* Write our heartbeat update interval to APE. */
10705 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10706 APE_HOST_HEARTBEAT_INT_DISABLE);
10708 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10713 /* Called at device open time to get the chip ready for
10714 * packet processing. Invoked with tp->lock held.
10716 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10718 /* Chip may have been just powered on. If so, the boot code may still
10719 * be running initialization. Wait for it to finish to avoid races in
10720 * accessing the hardware.
10722 tg3_enable_register_access(tp);
10725 tg3_switch_clocks(tp);
10727 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10729 return tg3_reset_hw(tp, reset_phy);
10732 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10736 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10737 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10739 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10742 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10743 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10744 memset(ocir, 0, TG3_OCIR_LEN);
10748 /* sysfs attributes for hwmon */
10749 static ssize_t tg3_show_temp(struct device *dev,
10750 struct device_attribute *devattr, char *buf)
10752 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10753 struct tg3 *tp = dev_get_drvdata(dev);
10756 spin_lock_bh(&tp->lock);
10757 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10758 sizeof(temperature));
10759 spin_unlock_bh(&tp->lock);
10760 return sprintf(buf, "%u\n", temperature);
10764 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10765 TG3_TEMP_SENSOR_OFFSET);
10766 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10767 TG3_TEMP_CAUTION_OFFSET);
10768 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10769 TG3_TEMP_MAX_OFFSET);
10771 static struct attribute *tg3_attrs[] = {
10772 &sensor_dev_attr_temp1_input.dev_attr.attr,
10773 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10774 &sensor_dev_attr_temp1_max.dev_attr.attr,
10777 ATTRIBUTE_GROUPS(tg3);
10779 static void tg3_hwmon_close(struct tg3 *tp)
10781 if (tp->hwmon_dev) {
10782 hwmon_device_unregister(tp->hwmon_dev);
10783 tp->hwmon_dev = NULL;
10787 static void tg3_hwmon_open(struct tg3 *tp)
10791 struct pci_dev *pdev = tp->pdev;
10792 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10794 tg3_sd_scan_scratchpad(tp, ocirs);
10796 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10797 if (!ocirs[i].src_data_length)
10800 size += ocirs[i].src_hdr_length;
10801 size += ocirs[i].src_data_length;
10807 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10809 if (IS_ERR(tp->hwmon_dev)) {
10810 tp->hwmon_dev = NULL;
10811 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10816 #define TG3_STAT_ADD32(PSTAT, REG) \
10817 do { u32 __val = tr32(REG); \
10818 (PSTAT)->low += __val; \
10819 if ((PSTAT)->low < __val) \
10820 (PSTAT)->high += 1; \
10823 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10825 struct tg3_hw_stats *sp = tp->hw_stats;
10830 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10831 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10832 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10833 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10834 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10835 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10836 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10837 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10838 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10839 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10840 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10841 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10842 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10843 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10844 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10845 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10848 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10849 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10850 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10851 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10854 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10855 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10856 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10857 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10858 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10859 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10860 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10861 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10862 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10863 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10864 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10865 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10866 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10867 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10869 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10870 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10871 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10872 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10873 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10874 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10876 u32 val = tr32(HOSTCC_FLOW_ATTN);
10877 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10879 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10880 sp->rx_discards.low += val;
10881 if (sp->rx_discards.low < val)
10882 sp->rx_discards.high += 1;
10884 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10886 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10889 static void tg3_chk_missed_msi(struct tg3 *tp)
10893 for (i = 0; i < tp->irq_cnt; i++) {
10894 struct tg3_napi *tnapi = &tp->napi[i];
10896 if (tg3_has_work(tnapi)) {
10897 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10898 tnapi->last_tx_cons == tnapi->tx_cons) {
10899 if (tnapi->chk_msi_cnt < 1) {
10900 tnapi->chk_msi_cnt++;
10906 tnapi->chk_msi_cnt = 0;
10907 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10908 tnapi->last_tx_cons = tnapi->tx_cons;
10912 static void tg3_timer(unsigned long __opaque)
10914 struct tg3 *tp = (struct tg3 *) __opaque;
10916 spin_lock(&tp->lock);
10918 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10919 spin_unlock(&tp->lock);
10920 goto restart_timer;
10923 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10924 tg3_flag(tp, 57765_CLASS))
10925 tg3_chk_missed_msi(tp);
10927 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10928 /* BCM4785: Flush posted writes from GbE to host memory. */
10932 if (!tg3_flag(tp, TAGGED_STATUS)) {
10933 /* All of this garbage is because when using non-tagged
10934 * IRQ status the mailbox/status_block protocol the chip
10935 * uses with the cpu is race prone.
10937 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10938 tw32(GRC_LOCAL_CTRL,
10939 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10941 tw32(HOSTCC_MODE, tp->coalesce_mode |
10942 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10945 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10946 spin_unlock(&tp->lock);
10947 tg3_reset_task_schedule(tp);
10948 goto restart_timer;
10952 /* This part only runs once per second. */
10953 if (!--tp->timer_counter) {
10954 if (tg3_flag(tp, 5705_PLUS))
10955 tg3_periodic_fetch_stats(tp);
10957 if (tp->setlpicnt && !--tp->setlpicnt)
10958 tg3_phy_eee_enable(tp);
10960 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10964 mac_stat = tr32(MAC_STATUS);
10967 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10968 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10970 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10974 tg3_setup_phy(tp, false);
10975 } else if (tg3_flag(tp, POLL_SERDES)) {
10976 u32 mac_stat = tr32(MAC_STATUS);
10977 int need_setup = 0;
10980 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10983 if (!tp->link_up &&
10984 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10985 MAC_STATUS_SIGNAL_DET))) {
10989 if (!tp->serdes_counter) {
10992 ~MAC_MODE_PORT_MODE_MASK));
10994 tw32_f(MAC_MODE, tp->mac_mode);
10997 tg3_setup_phy(tp, false);
10999 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11000 tg3_flag(tp, 5780_CLASS)) {
11001 tg3_serdes_parallel_detect(tp);
11002 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11003 u32 cpmu = tr32(TG3_CPMU_STATUS);
11004 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
11005 TG3_CPMU_STATUS_LINK_MASK);
11007 if (link_up != tp->link_up)
11008 tg3_setup_phy(tp, false);
11011 tp->timer_counter = tp->timer_multiplier;
11014 /* Heartbeat is only sent once every 2 seconds.
11016 * The heartbeat is to tell the ASF firmware that the host
11017 * driver is still alive. In the event that the OS crashes,
11018 * ASF needs to reset the hardware to free up the FIFO space
11019 * that may be filled with rx packets destined for the host.
11020 * If the FIFO is full, ASF will no longer function properly.
11022 * Unintended resets have been reported on real time kernels
11023 * where the timer doesn't run on time. Netpoll will also have
11026 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11027 * to check the ring condition when the heartbeat is expiring
11028 * before doing the reset. This will prevent most unintended
11031 if (!--tp->asf_counter) {
11032 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11033 tg3_wait_for_event_ack(tp);
11035 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11036 FWCMD_NICDRV_ALIVE3);
11037 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11038 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11039 TG3_FW_UPDATE_TIMEOUT_SEC);
11041 tg3_generate_fw_event(tp);
11043 tp->asf_counter = tp->asf_multiplier;
11046 spin_unlock(&tp->lock);
11049 tp->timer.expires = jiffies + tp->timer_offset;
11050 add_timer(&tp->timer);
11053 static void tg3_timer_init(struct tg3 *tp)
11055 if (tg3_flag(tp, TAGGED_STATUS) &&
11056 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11057 !tg3_flag(tp, 57765_CLASS))
11058 tp->timer_offset = HZ;
11060 tp->timer_offset = HZ / 10;
11062 BUG_ON(tp->timer_offset > HZ);
11064 tp->timer_multiplier = (HZ / tp->timer_offset);
11065 tp->asf_multiplier = (HZ / tp->timer_offset) *
11066 TG3_FW_UPDATE_FREQ_SEC;
11068 init_timer(&tp->timer);
11069 tp->timer.data = (unsigned long) tp;
11070 tp->timer.function = tg3_timer;
11073 static void tg3_timer_start(struct tg3 *tp)
11075 tp->asf_counter = tp->asf_multiplier;
11076 tp->timer_counter = tp->timer_multiplier;
11078 tp->timer.expires = jiffies + tp->timer_offset;
11079 add_timer(&tp->timer);
11082 static void tg3_timer_stop(struct tg3 *tp)
11084 del_timer_sync(&tp->timer);
11087 /* Restart hardware after configuration changes, self-test, etc.
11088 * Invoked with tp->lock held.
11090 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11091 __releases(tp->lock)
11092 __acquires(tp->lock)
11096 err = tg3_init_hw(tp, reset_phy);
11098 netdev_err(tp->dev,
11099 "Failed to re-initialize device, aborting\n");
11100 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11101 tg3_full_unlock(tp);
11102 tg3_timer_stop(tp);
11104 tg3_napi_enable(tp);
11105 dev_close(tp->dev);
11106 tg3_full_lock(tp, 0);
11111 static void tg3_reset_task(struct work_struct *work)
11113 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11117 tg3_full_lock(tp, 0);
11119 if (!netif_running(tp->dev)) {
11120 tg3_flag_clear(tp, RESET_TASK_PENDING);
11121 tg3_full_unlock(tp);
11126 tg3_full_unlock(tp);
11130 tg3_netif_stop(tp);
11132 tg3_full_lock(tp, 1);
11134 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11135 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11136 tp->write32_rx_mbox = tg3_write_flush_reg32;
11137 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11138 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11141 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11142 err = tg3_init_hw(tp, true);
11146 tg3_netif_start(tp);
11149 tg3_full_unlock(tp);
11154 tg3_flag_clear(tp, RESET_TASK_PENDING);
11158 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11161 unsigned long flags;
11163 struct tg3_napi *tnapi = &tp->napi[irq_num];
11165 if (tp->irq_cnt == 1)
11166 name = tp->dev->name;
11168 name = &tnapi->irq_lbl[0];
11169 if (tnapi->tx_buffers && tnapi->rx_rcb)
11170 snprintf(name, IFNAMSIZ,
11171 "%s-txrx-%d", tp->dev->name, irq_num);
11172 else if (tnapi->tx_buffers)
11173 snprintf(name, IFNAMSIZ,
11174 "%s-tx-%d", tp->dev->name, irq_num);
11175 else if (tnapi->rx_rcb)
11176 snprintf(name, IFNAMSIZ,
11177 "%s-rx-%d", tp->dev->name, irq_num);
11179 snprintf(name, IFNAMSIZ,
11180 "%s-%d", tp->dev->name, irq_num);
11181 name[IFNAMSIZ-1] = 0;
11184 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11186 if (tg3_flag(tp, 1SHOT_MSI))
11187 fn = tg3_msi_1shot;
11190 fn = tg3_interrupt;
11191 if (tg3_flag(tp, TAGGED_STATUS))
11192 fn = tg3_interrupt_tagged;
11193 flags = IRQF_SHARED;
11196 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11199 static int tg3_test_interrupt(struct tg3 *tp)
11201 struct tg3_napi *tnapi = &tp->napi[0];
11202 struct net_device *dev = tp->dev;
11203 int err, i, intr_ok = 0;
11206 if (!netif_running(dev))
11209 tg3_disable_ints(tp);
11211 free_irq(tnapi->irq_vec, tnapi);
11214 * Turn off MSI one shot mode. Otherwise this test has no
11215 * observable way to know whether the interrupt was delivered.
11217 if (tg3_flag(tp, 57765_PLUS)) {
11218 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11219 tw32(MSGINT_MODE, val);
11222 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11223 IRQF_SHARED, dev->name, tnapi);
11227 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11228 tg3_enable_ints(tp);
11230 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11233 for (i = 0; i < 5; i++) {
11234 u32 int_mbox, misc_host_ctrl;
11236 int_mbox = tr32_mailbox(tnapi->int_mbox);
11237 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11239 if ((int_mbox != 0) ||
11240 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11245 if (tg3_flag(tp, 57765_PLUS) &&
11246 tnapi->hw_status->status_tag != tnapi->last_tag)
11247 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11252 tg3_disable_ints(tp);
11254 free_irq(tnapi->irq_vec, tnapi);
11256 err = tg3_request_irq(tp, 0);
11262 /* Reenable MSI one shot mode. */
11263 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11264 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11265 tw32(MSGINT_MODE, val);
11273 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11274 * successfully restored
11276 static int tg3_test_msi(struct tg3 *tp)
11281 if (!tg3_flag(tp, USING_MSI))
11284 /* Turn off SERR reporting in case MSI terminates with Master
11287 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11288 pci_write_config_word(tp->pdev, PCI_COMMAND,
11289 pci_cmd & ~PCI_COMMAND_SERR);
11291 err = tg3_test_interrupt(tp);
11293 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11298 /* other failures */
11302 /* MSI test failed, go back to INTx mode */
11303 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11304 "to INTx mode. Please report this failure to the PCI "
11305 "maintainer and include system chipset information\n");
11307 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11309 pci_disable_msi(tp->pdev);
11311 tg3_flag_clear(tp, USING_MSI);
11312 tp->napi[0].irq_vec = tp->pdev->irq;
11314 err = tg3_request_irq(tp, 0);
11318 /* Need to reset the chip because the MSI cycle may have terminated
11319 * with Master Abort.
11321 tg3_full_lock(tp, 1);
11323 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11324 err = tg3_init_hw(tp, true);
11326 tg3_full_unlock(tp);
11329 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11334 static int tg3_request_firmware(struct tg3 *tp)
11336 const struct tg3_firmware_hdr *fw_hdr;
11338 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11339 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11344 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11346 /* Firmware blob starts with version numbers, followed by
11347 * start address and _full_ length including BSS sections
11348 * (which must be longer than the actual data, of course
11351 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11352 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11353 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11354 tp->fw_len, tp->fw_needed);
11355 release_firmware(tp->fw);
11360 /* We no longer need firmware; we have it. */
11361 tp->fw_needed = NULL;
11365 static u32 tg3_irq_count(struct tg3 *tp)
11367 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11370 /* We want as many rx rings enabled as there are cpus.
11371 * In multiqueue MSI-X mode, the first MSI-X vector
11372 * only deals with link interrupts, etc, so we add
11373 * one to the number of vectors we are requesting.
11375 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11381 static bool tg3_enable_msix(struct tg3 *tp)
11384 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11386 tp->txq_cnt = tp->txq_req;
11387 tp->rxq_cnt = tp->rxq_req;
11389 tp->rxq_cnt = netif_get_num_default_rss_queues();
11390 if (tp->rxq_cnt > tp->rxq_max)
11391 tp->rxq_cnt = tp->rxq_max;
11393 /* Disable multiple TX rings by default. Simple round-robin hardware
11394 * scheduling of the TX rings can cause starvation of rings with
11395 * small packets when other rings have TSO or jumbo packets.
11400 tp->irq_cnt = tg3_irq_count(tp);
11402 for (i = 0; i < tp->irq_max; i++) {
11403 msix_ent[i].entry = i;
11404 msix_ent[i].vector = 0;
11407 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11410 } else if (rc < tp->irq_cnt) {
11411 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11414 tp->rxq_cnt = max(rc - 1, 1);
11416 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11419 for (i = 0; i < tp->irq_max; i++)
11420 tp->napi[i].irq_vec = msix_ent[i].vector;
11422 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11423 pci_disable_msix(tp->pdev);
11427 if (tp->irq_cnt == 1)
11430 tg3_flag_set(tp, ENABLE_RSS);
11432 if (tp->txq_cnt > 1)
11433 tg3_flag_set(tp, ENABLE_TSS);
11435 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11440 static void tg3_ints_init(struct tg3 *tp)
11442 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11443 !tg3_flag(tp, TAGGED_STATUS)) {
11444 /* All MSI supporting chips should support tagged
11445 * status. Assert that this is the case.
11447 netdev_warn(tp->dev,
11448 "MSI without TAGGED_STATUS? Not using MSI\n");
11452 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11453 tg3_flag_set(tp, USING_MSIX);
11454 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11455 tg3_flag_set(tp, USING_MSI);
11457 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11458 u32 msi_mode = tr32(MSGINT_MODE);
11459 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11460 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11461 if (!tg3_flag(tp, 1SHOT_MSI))
11462 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11463 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11466 if (!tg3_flag(tp, USING_MSIX)) {
11468 tp->napi[0].irq_vec = tp->pdev->irq;
11471 if (tp->irq_cnt == 1) {
11474 netif_set_real_num_tx_queues(tp->dev, 1);
11475 netif_set_real_num_rx_queues(tp->dev, 1);
11479 static void tg3_ints_fini(struct tg3 *tp)
11481 if (tg3_flag(tp, USING_MSIX))
11482 pci_disable_msix(tp->pdev);
11483 else if (tg3_flag(tp, USING_MSI))
11484 pci_disable_msi(tp->pdev);
11485 tg3_flag_clear(tp, USING_MSI);
11486 tg3_flag_clear(tp, USING_MSIX);
11487 tg3_flag_clear(tp, ENABLE_RSS);
11488 tg3_flag_clear(tp, ENABLE_TSS);
11491 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11494 struct net_device *dev = tp->dev;
11498 * Setup interrupts first so we know how
11499 * many NAPI resources to allocate
11503 tg3_rss_check_indir_tbl(tp);
11505 /* The placement of this call is tied
11506 * to the setup and use of Host TX descriptors.
11508 err = tg3_alloc_consistent(tp);
11510 goto out_ints_fini;
11514 tg3_napi_enable(tp);
11516 for (i = 0; i < tp->irq_cnt; i++) {
11517 struct tg3_napi *tnapi = &tp->napi[i];
11518 err = tg3_request_irq(tp, i);
11520 for (i--; i >= 0; i--) {
11521 tnapi = &tp->napi[i];
11522 free_irq(tnapi->irq_vec, tnapi);
11524 goto out_napi_fini;
11528 tg3_full_lock(tp, 0);
11531 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11533 err = tg3_init_hw(tp, reset_phy);
11535 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11536 tg3_free_rings(tp);
11539 tg3_full_unlock(tp);
11544 if (test_irq && tg3_flag(tp, USING_MSI)) {
11545 err = tg3_test_msi(tp);
11548 tg3_full_lock(tp, 0);
11549 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11550 tg3_free_rings(tp);
11551 tg3_full_unlock(tp);
11553 goto out_napi_fini;
11556 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11557 u32 val = tr32(PCIE_TRANSACTION_CFG);
11559 tw32(PCIE_TRANSACTION_CFG,
11560 val | PCIE_TRANS_CFG_1SHOT_MSI);
11566 tg3_hwmon_open(tp);
11568 tg3_full_lock(tp, 0);
11570 tg3_timer_start(tp);
11571 tg3_flag_set(tp, INIT_COMPLETE);
11572 tg3_enable_ints(tp);
11574 tg3_ptp_resume(tp);
11576 tg3_full_unlock(tp);
11578 netif_tx_start_all_queues(dev);
11581 * Reset loopback feature if it was turned on while the device was down
11582 * make sure that it's installed properly now.
11584 if (dev->features & NETIF_F_LOOPBACK)
11585 tg3_set_loopback(dev, dev->features);
11590 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11591 struct tg3_napi *tnapi = &tp->napi[i];
11592 free_irq(tnapi->irq_vec, tnapi);
11596 tg3_napi_disable(tp);
11598 tg3_free_consistent(tp);
11606 static void tg3_stop(struct tg3 *tp)
11610 tg3_reset_task_cancel(tp);
11611 tg3_netif_stop(tp);
11613 tg3_timer_stop(tp);
11615 tg3_hwmon_close(tp);
11619 tg3_full_lock(tp, 1);
11621 tg3_disable_ints(tp);
11623 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11624 tg3_free_rings(tp);
11625 tg3_flag_clear(tp, INIT_COMPLETE);
11627 tg3_full_unlock(tp);
11629 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11630 struct tg3_napi *tnapi = &tp->napi[i];
11631 free_irq(tnapi->irq_vec, tnapi);
11638 tg3_free_consistent(tp);
11641 static int tg3_open(struct net_device *dev)
11643 struct tg3 *tp = netdev_priv(dev);
11646 if (tp->pcierr_recovery) {
11647 netdev_err(dev, "Failed to open device. PCI error recovery "
11652 if (tp->fw_needed) {
11653 err = tg3_request_firmware(tp);
11654 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11656 netdev_warn(tp->dev, "EEE capability disabled\n");
11657 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11658 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11659 netdev_warn(tp->dev, "EEE capability restored\n");
11660 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11662 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11666 netdev_warn(tp->dev, "TSO capability disabled\n");
11667 tg3_flag_clear(tp, TSO_CAPABLE);
11668 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11669 netdev_notice(tp->dev, "TSO capability restored\n");
11670 tg3_flag_set(tp, TSO_CAPABLE);
11674 tg3_carrier_off(tp);
11676 err = tg3_power_up(tp);
11680 tg3_full_lock(tp, 0);
11682 tg3_disable_ints(tp);
11683 tg3_flag_clear(tp, INIT_COMPLETE);
11685 tg3_full_unlock(tp);
11687 err = tg3_start(tp,
11688 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11691 tg3_frob_aux_power(tp, false);
11692 pci_set_power_state(tp->pdev, PCI_D3hot);
11698 static int tg3_close(struct net_device *dev)
11700 struct tg3 *tp = netdev_priv(dev);
11702 if (tp->pcierr_recovery) {
11703 netdev_err(dev, "Failed to close device. PCI error recovery "
11710 /* Clear stats across close / open calls */
11711 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11712 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11714 if (pci_device_is_present(tp->pdev)) {
11715 tg3_power_down_prepare(tp);
11717 tg3_carrier_off(tp);
11722 static inline u64 get_stat64(tg3_stat64_t *val)
11724 return ((u64)val->high << 32) | ((u64)val->low);
11727 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11729 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11731 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11732 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11733 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11736 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11737 tg3_writephy(tp, MII_TG3_TEST1,
11738 val | MII_TG3_TEST1_CRC_EN);
11739 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11743 tp->phy_crc_errors += val;
11745 return tp->phy_crc_errors;
11748 return get_stat64(&hw_stats->rx_fcs_errors);
11751 #define ESTAT_ADD(member) \
11752 estats->member = old_estats->member + \
11753 get_stat64(&hw_stats->member)
11755 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11757 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11758 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11760 ESTAT_ADD(rx_octets);
11761 ESTAT_ADD(rx_fragments);
11762 ESTAT_ADD(rx_ucast_packets);
11763 ESTAT_ADD(rx_mcast_packets);
11764 ESTAT_ADD(rx_bcast_packets);
11765 ESTAT_ADD(rx_fcs_errors);
11766 ESTAT_ADD(rx_align_errors);
11767 ESTAT_ADD(rx_xon_pause_rcvd);
11768 ESTAT_ADD(rx_xoff_pause_rcvd);
11769 ESTAT_ADD(rx_mac_ctrl_rcvd);
11770 ESTAT_ADD(rx_xoff_entered);
11771 ESTAT_ADD(rx_frame_too_long_errors);
11772 ESTAT_ADD(rx_jabbers);
11773 ESTAT_ADD(rx_undersize_packets);
11774 ESTAT_ADD(rx_in_length_errors);
11775 ESTAT_ADD(rx_out_length_errors);
11776 ESTAT_ADD(rx_64_or_less_octet_packets);
11777 ESTAT_ADD(rx_65_to_127_octet_packets);
11778 ESTAT_ADD(rx_128_to_255_octet_packets);
11779 ESTAT_ADD(rx_256_to_511_octet_packets);
11780 ESTAT_ADD(rx_512_to_1023_octet_packets);
11781 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11782 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11783 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11784 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11785 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11787 ESTAT_ADD(tx_octets);
11788 ESTAT_ADD(tx_collisions);
11789 ESTAT_ADD(tx_xon_sent);
11790 ESTAT_ADD(tx_xoff_sent);
11791 ESTAT_ADD(tx_flow_control);
11792 ESTAT_ADD(tx_mac_errors);
11793 ESTAT_ADD(tx_single_collisions);
11794 ESTAT_ADD(tx_mult_collisions);
11795 ESTAT_ADD(tx_deferred);
11796 ESTAT_ADD(tx_excessive_collisions);
11797 ESTAT_ADD(tx_late_collisions);
11798 ESTAT_ADD(tx_collide_2times);
11799 ESTAT_ADD(tx_collide_3times);
11800 ESTAT_ADD(tx_collide_4times);
11801 ESTAT_ADD(tx_collide_5times);
11802 ESTAT_ADD(tx_collide_6times);
11803 ESTAT_ADD(tx_collide_7times);
11804 ESTAT_ADD(tx_collide_8times);
11805 ESTAT_ADD(tx_collide_9times);
11806 ESTAT_ADD(tx_collide_10times);
11807 ESTAT_ADD(tx_collide_11times);
11808 ESTAT_ADD(tx_collide_12times);
11809 ESTAT_ADD(tx_collide_13times);
11810 ESTAT_ADD(tx_collide_14times);
11811 ESTAT_ADD(tx_collide_15times);
11812 ESTAT_ADD(tx_ucast_packets);
11813 ESTAT_ADD(tx_mcast_packets);
11814 ESTAT_ADD(tx_bcast_packets);
11815 ESTAT_ADD(tx_carrier_sense_errors);
11816 ESTAT_ADD(tx_discards);
11817 ESTAT_ADD(tx_errors);
11819 ESTAT_ADD(dma_writeq_full);
11820 ESTAT_ADD(dma_write_prioq_full);
11821 ESTAT_ADD(rxbds_empty);
11822 ESTAT_ADD(rx_discards);
11823 ESTAT_ADD(rx_errors);
11824 ESTAT_ADD(rx_threshold_hit);
11826 ESTAT_ADD(dma_readq_full);
11827 ESTAT_ADD(dma_read_prioq_full);
11828 ESTAT_ADD(tx_comp_queue_full);
11830 ESTAT_ADD(ring_set_send_prod_index);
11831 ESTAT_ADD(ring_status_update);
11832 ESTAT_ADD(nic_irqs);
11833 ESTAT_ADD(nic_avoided_irqs);
11834 ESTAT_ADD(nic_tx_threshold_hit);
11836 ESTAT_ADD(mbuf_lwm_thresh_hit);
11839 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11841 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11842 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11844 stats->rx_packets = old_stats->rx_packets +
11845 get_stat64(&hw_stats->rx_ucast_packets) +
11846 get_stat64(&hw_stats->rx_mcast_packets) +
11847 get_stat64(&hw_stats->rx_bcast_packets);
11849 stats->tx_packets = old_stats->tx_packets +
11850 get_stat64(&hw_stats->tx_ucast_packets) +
11851 get_stat64(&hw_stats->tx_mcast_packets) +
11852 get_stat64(&hw_stats->tx_bcast_packets);
11854 stats->rx_bytes = old_stats->rx_bytes +
11855 get_stat64(&hw_stats->rx_octets);
11856 stats->tx_bytes = old_stats->tx_bytes +
11857 get_stat64(&hw_stats->tx_octets);
11859 stats->rx_errors = old_stats->rx_errors +
11860 get_stat64(&hw_stats->rx_errors);
11861 stats->tx_errors = old_stats->tx_errors +
11862 get_stat64(&hw_stats->tx_errors) +
11863 get_stat64(&hw_stats->tx_mac_errors) +
11864 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11865 get_stat64(&hw_stats->tx_discards);
11867 stats->multicast = old_stats->multicast +
11868 get_stat64(&hw_stats->rx_mcast_packets);
11869 stats->collisions = old_stats->collisions +
11870 get_stat64(&hw_stats->tx_collisions);
11872 stats->rx_length_errors = old_stats->rx_length_errors +
11873 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11874 get_stat64(&hw_stats->rx_undersize_packets);
11876 stats->rx_frame_errors = old_stats->rx_frame_errors +
11877 get_stat64(&hw_stats->rx_align_errors);
11878 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11879 get_stat64(&hw_stats->tx_discards);
11880 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11881 get_stat64(&hw_stats->tx_carrier_sense_errors);
11883 stats->rx_crc_errors = old_stats->rx_crc_errors +
11884 tg3_calc_crc_errors(tp);
11886 stats->rx_missed_errors = old_stats->rx_missed_errors +
11887 get_stat64(&hw_stats->rx_discards);
11889 stats->rx_dropped = tp->rx_dropped;
11890 stats->tx_dropped = tp->tx_dropped;
11893 static int tg3_get_regs_len(struct net_device *dev)
11895 return TG3_REG_BLK_SIZE;
11898 static void tg3_get_regs(struct net_device *dev,
11899 struct ethtool_regs *regs, void *_p)
11901 struct tg3 *tp = netdev_priv(dev);
11905 memset(_p, 0, TG3_REG_BLK_SIZE);
11907 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11910 tg3_full_lock(tp, 0);
11912 tg3_dump_legacy_regs(tp, (u32 *)_p);
11914 tg3_full_unlock(tp);
11917 static int tg3_get_eeprom_len(struct net_device *dev)
11919 struct tg3 *tp = netdev_priv(dev);
11921 return tp->nvram_size;
11924 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11926 struct tg3 *tp = netdev_priv(dev);
11927 int ret, cpmu_restore = 0;
11929 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
11932 if (tg3_flag(tp, NO_NVRAM))
11935 offset = eeprom->offset;
11939 eeprom->magic = TG3_EEPROM_MAGIC;
11941 /* Override clock, link aware and link idle modes */
11942 if (tg3_flag(tp, CPMU_PRESENT)) {
11943 cpmu_val = tr32(TG3_CPMU_CTRL);
11944 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11945 CPMU_CTRL_LINK_IDLE_MODE)) {
11946 tw32(TG3_CPMU_CTRL, cpmu_val &
11947 ~(CPMU_CTRL_LINK_AWARE_MODE |
11948 CPMU_CTRL_LINK_IDLE_MODE));
11952 tg3_override_clk(tp);
11955 /* adjustments to start on required 4 byte boundary */
11956 b_offset = offset & 3;
11957 b_count = 4 - b_offset;
11958 if (b_count > len) {
11959 /* i.e. offset=1 len=2 */
11962 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11965 memcpy(data, ((char *)&val) + b_offset, b_count);
11968 eeprom->len += b_count;
11971 /* read bytes up to the last 4 byte boundary */
11972 pd = &data[eeprom->len];
11973 for (i = 0; i < (len - (len & 3)); i += 4) {
11974 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11981 memcpy(pd + i, &val, 4);
11982 if (need_resched()) {
11983 if (signal_pending(current)) {
11994 /* read last bytes not ending on 4 byte boundary */
11995 pd = &data[eeprom->len];
11997 b_offset = offset + len - b_count;
11998 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12001 memcpy(pd, &val, b_count);
12002 eeprom->len += b_count;
12007 /* Restore clock, link aware and link idle modes */
12008 tg3_restore_clk(tp);
12010 tw32(TG3_CPMU_CTRL, cpmu_val);
12015 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12017 struct tg3 *tp = netdev_priv(dev);
12019 u32 offset, len, b_offset, odd_len;
12023 if (tg3_flag(tp, NO_NVRAM) ||
12024 eeprom->magic != TG3_EEPROM_MAGIC)
12027 offset = eeprom->offset;
12030 if ((b_offset = (offset & 3))) {
12031 /* adjustments to start on required 4 byte boundary */
12032 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12043 /* adjustments to end on required 4 byte boundary */
12045 len = (len + 3) & ~3;
12046 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12052 if (b_offset || odd_len) {
12053 buf = kmalloc(len, GFP_KERNEL);
12057 memcpy(buf, &start, 4);
12059 memcpy(buf+len-4, &end, 4);
12060 memcpy(buf + b_offset, data, eeprom->len);
12063 ret = tg3_nvram_write_block(tp, offset, len, buf);
12071 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12073 struct tg3 *tp = netdev_priv(dev);
12075 if (tg3_flag(tp, USE_PHYLIB)) {
12076 struct phy_device *phydev;
12077 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12079 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12080 return phy_ethtool_gset(phydev, cmd);
12083 cmd->supported = (SUPPORTED_Autoneg);
12085 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12086 cmd->supported |= (SUPPORTED_1000baseT_Half |
12087 SUPPORTED_1000baseT_Full);
12089 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12090 cmd->supported |= (SUPPORTED_100baseT_Half |
12091 SUPPORTED_100baseT_Full |
12092 SUPPORTED_10baseT_Half |
12093 SUPPORTED_10baseT_Full |
12095 cmd->port = PORT_TP;
12097 cmd->supported |= SUPPORTED_FIBRE;
12098 cmd->port = PORT_FIBRE;
12101 cmd->advertising = tp->link_config.advertising;
12102 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12103 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12104 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12105 cmd->advertising |= ADVERTISED_Pause;
12107 cmd->advertising |= ADVERTISED_Pause |
12108 ADVERTISED_Asym_Pause;
12110 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12111 cmd->advertising |= ADVERTISED_Asym_Pause;
12114 if (netif_running(dev) && tp->link_up) {
12115 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
12116 cmd->duplex = tp->link_config.active_duplex;
12117 cmd->lp_advertising = tp->link_config.rmt_adv;
12118 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12119 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12120 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12122 cmd->eth_tp_mdix = ETH_TP_MDI;
12125 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12126 cmd->duplex = DUPLEX_UNKNOWN;
12127 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
12129 cmd->phy_address = tp->phy_addr;
12130 cmd->transceiver = XCVR_INTERNAL;
12131 cmd->autoneg = tp->link_config.autoneg;
12137 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12139 struct tg3 *tp = netdev_priv(dev);
12140 u32 speed = ethtool_cmd_speed(cmd);
12142 if (tg3_flag(tp, USE_PHYLIB)) {
12143 struct phy_device *phydev;
12144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12146 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12147 return phy_ethtool_sset(phydev, cmd);
12150 if (cmd->autoneg != AUTONEG_ENABLE &&
12151 cmd->autoneg != AUTONEG_DISABLE)
12154 if (cmd->autoneg == AUTONEG_DISABLE &&
12155 cmd->duplex != DUPLEX_FULL &&
12156 cmd->duplex != DUPLEX_HALF)
12159 if (cmd->autoneg == AUTONEG_ENABLE) {
12160 u32 mask = ADVERTISED_Autoneg |
12162 ADVERTISED_Asym_Pause;
12164 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12165 mask |= ADVERTISED_1000baseT_Half |
12166 ADVERTISED_1000baseT_Full;
12168 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12169 mask |= ADVERTISED_100baseT_Half |
12170 ADVERTISED_100baseT_Full |
12171 ADVERTISED_10baseT_Half |
12172 ADVERTISED_10baseT_Full |
12175 mask |= ADVERTISED_FIBRE;
12177 if (cmd->advertising & ~mask)
12180 mask &= (ADVERTISED_1000baseT_Half |
12181 ADVERTISED_1000baseT_Full |
12182 ADVERTISED_100baseT_Half |
12183 ADVERTISED_100baseT_Full |
12184 ADVERTISED_10baseT_Half |
12185 ADVERTISED_10baseT_Full);
12187 cmd->advertising &= mask;
12189 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12190 if (speed != SPEED_1000)
12193 if (cmd->duplex != DUPLEX_FULL)
12196 if (speed != SPEED_100 &&
12202 tg3_full_lock(tp, 0);
12204 tp->link_config.autoneg = cmd->autoneg;
12205 if (cmd->autoneg == AUTONEG_ENABLE) {
12206 tp->link_config.advertising = (cmd->advertising |
12207 ADVERTISED_Autoneg);
12208 tp->link_config.speed = SPEED_UNKNOWN;
12209 tp->link_config.duplex = DUPLEX_UNKNOWN;
12211 tp->link_config.advertising = 0;
12212 tp->link_config.speed = speed;
12213 tp->link_config.duplex = cmd->duplex;
12216 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12218 tg3_warn_mgmt_link_flap(tp);
12220 if (netif_running(dev))
12221 tg3_setup_phy(tp, true);
12223 tg3_full_unlock(tp);
12228 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12230 struct tg3 *tp = netdev_priv(dev);
12232 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12233 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12234 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12235 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12238 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12240 struct tg3 *tp = netdev_priv(dev);
12242 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12243 wol->supported = WAKE_MAGIC;
12245 wol->supported = 0;
12247 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12248 wol->wolopts = WAKE_MAGIC;
12249 memset(&wol->sopass, 0, sizeof(wol->sopass));
12252 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12254 struct tg3 *tp = netdev_priv(dev);
12255 struct device *dp = &tp->pdev->dev;
12257 if (wol->wolopts & ~WAKE_MAGIC)
12259 if ((wol->wolopts & WAKE_MAGIC) &&
12260 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12263 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12265 if (device_may_wakeup(dp))
12266 tg3_flag_set(tp, WOL_ENABLE);
12268 tg3_flag_clear(tp, WOL_ENABLE);
12273 static u32 tg3_get_msglevel(struct net_device *dev)
12275 struct tg3 *tp = netdev_priv(dev);
12276 return tp->msg_enable;
12279 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12281 struct tg3 *tp = netdev_priv(dev);
12282 tp->msg_enable = value;
12285 static int tg3_nway_reset(struct net_device *dev)
12287 struct tg3 *tp = netdev_priv(dev);
12290 if (!netif_running(dev))
12293 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12296 tg3_warn_mgmt_link_flap(tp);
12298 if (tg3_flag(tp, USE_PHYLIB)) {
12299 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12301 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12305 spin_lock_bh(&tp->lock);
12307 tg3_readphy(tp, MII_BMCR, &bmcr);
12308 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12309 ((bmcr & BMCR_ANENABLE) ||
12310 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12311 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12315 spin_unlock_bh(&tp->lock);
12321 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12323 struct tg3 *tp = netdev_priv(dev);
12325 ering->rx_max_pending = tp->rx_std_ring_mask;
12326 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12327 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12329 ering->rx_jumbo_max_pending = 0;
12331 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12333 ering->rx_pending = tp->rx_pending;
12334 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12335 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12337 ering->rx_jumbo_pending = 0;
12339 ering->tx_pending = tp->napi[0].tx_pending;
12342 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12344 struct tg3 *tp = netdev_priv(dev);
12345 int i, irq_sync = 0, err = 0;
12347 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12348 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12349 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12350 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12351 (tg3_flag(tp, TSO_BUG) &&
12352 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12355 if (netif_running(dev)) {
12357 tg3_netif_stop(tp);
12361 tg3_full_lock(tp, irq_sync);
12363 tp->rx_pending = ering->rx_pending;
12365 if (tg3_flag(tp, MAX_RXPEND_64) &&
12366 tp->rx_pending > 63)
12367 tp->rx_pending = 63;
12369 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12370 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12372 for (i = 0; i < tp->irq_max; i++)
12373 tp->napi[i].tx_pending = ering->tx_pending;
12375 if (netif_running(dev)) {
12376 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12377 err = tg3_restart_hw(tp, false);
12379 tg3_netif_start(tp);
12382 tg3_full_unlock(tp);
12384 if (irq_sync && !err)
12390 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12392 struct tg3 *tp = netdev_priv(dev);
12394 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12396 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12397 epause->rx_pause = 1;
12399 epause->rx_pause = 0;
12401 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12402 epause->tx_pause = 1;
12404 epause->tx_pause = 0;
12407 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12409 struct tg3 *tp = netdev_priv(dev);
12412 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12413 tg3_warn_mgmt_link_flap(tp);
12415 if (tg3_flag(tp, USE_PHYLIB)) {
12417 struct phy_device *phydev;
12419 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12421 if (!(phydev->supported & SUPPORTED_Pause) ||
12422 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12423 (epause->rx_pause != epause->tx_pause)))
12426 tp->link_config.flowctrl = 0;
12427 if (epause->rx_pause) {
12428 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12430 if (epause->tx_pause) {
12431 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12432 newadv = ADVERTISED_Pause;
12434 newadv = ADVERTISED_Pause |
12435 ADVERTISED_Asym_Pause;
12436 } else if (epause->tx_pause) {
12437 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12438 newadv = ADVERTISED_Asym_Pause;
12442 if (epause->autoneg)
12443 tg3_flag_set(tp, PAUSE_AUTONEG);
12445 tg3_flag_clear(tp, PAUSE_AUTONEG);
12447 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12448 u32 oldadv = phydev->advertising &
12449 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12450 if (oldadv != newadv) {
12451 phydev->advertising &=
12452 ~(ADVERTISED_Pause |
12453 ADVERTISED_Asym_Pause);
12454 phydev->advertising |= newadv;
12455 if (phydev->autoneg) {
12457 * Always renegotiate the link to
12458 * inform our link partner of our
12459 * flow control settings, even if the
12460 * flow control is forced. Let
12461 * tg3_adjust_link() do the final
12462 * flow control setup.
12464 return phy_start_aneg(phydev);
12468 if (!epause->autoneg)
12469 tg3_setup_flow_control(tp, 0, 0);
12471 tp->link_config.advertising &=
12472 ~(ADVERTISED_Pause |
12473 ADVERTISED_Asym_Pause);
12474 tp->link_config.advertising |= newadv;
12479 if (netif_running(dev)) {
12480 tg3_netif_stop(tp);
12484 tg3_full_lock(tp, irq_sync);
12486 if (epause->autoneg)
12487 tg3_flag_set(tp, PAUSE_AUTONEG);
12489 tg3_flag_clear(tp, PAUSE_AUTONEG);
12490 if (epause->rx_pause)
12491 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12493 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12494 if (epause->tx_pause)
12495 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12497 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12499 if (netif_running(dev)) {
12500 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12501 err = tg3_restart_hw(tp, false);
12503 tg3_netif_start(tp);
12506 tg3_full_unlock(tp);
12509 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12514 static int tg3_get_sset_count(struct net_device *dev, int sset)
12518 return TG3_NUM_TEST;
12520 return TG3_NUM_STATS;
12522 return -EOPNOTSUPP;
12526 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12527 u32 *rules __always_unused)
12529 struct tg3 *tp = netdev_priv(dev);
12531 if (!tg3_flag(tp, SUPPORT_MSIX))
12532 return -EOPNOTSUPP;
12534 switch (info->cmd) {
12535 case ETHTOOL_GRXRINGS:
12536 if (netif_running(tp->dev))
12537 info->data = tp->rxq_cnt;
12539 info->data = num_online_cpus();
12540 if (info->data > TG3_RSS_MAX_NUM_QS)
12541 info->data = TG3_RSS_MAX_NUM_QS;
12544 /* The first interrupt vector only
12545 * handles link interrupts.
12551 return -EOPNOTSUPP;
12555 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12558 struct tg3 *tp = netdev_priv(dev);
12560 if (tg3_flag(tp, SUPPORT_MSIX))
12561 size = TG3_RSS_INDIR_TBL_SIZE;
12566 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)
12568 struct tg3 *tp = netdev_priv(dev);
12572 *hfunc = ETH_RSS_HASH_TOP;
12576 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12577 indir[i] = tp->rss_ind_tbl[i];
12582 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
12585 struct tg3 *tp = netdev_priv(dev);
12588 /* We require at least one supported parameter to be changed and no
12589 * change in any of the unsupported parameters
12592 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
12593 return -EOPNOTSUPP;
12598 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12599 tp->rss_ind_tbl[i] = indir[i];
12601 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12604 /* It is legal to write the indirection
12605 * table while the device is running.
12607 tg3_full_lock(tp, 0);
12608 tg3_rss_write_indir_tbl(tp);
12609 tg3_full_unlock(tp);
12614 static void tg3_get_channels(struct net_device *dev,
12615 struct ethtool_channels *channel)
12617 struct tg3 *tp = netdev_priv(dev);
12618 u32 deflt_qs = netif_get_num_default_rss_queues();
12620 channel->max_rx = tp->rxq_max;
12621 channel->max_tx = tp->txq_max;
12623 if (netif_running(dev)) {
12624 channel->rx_count = tp->rxq_cnt;
12625 channel->tx_count = tp->txq_cnt;
12628 channel->rx_count = tp->rxq_req;
12630 channel->rx_count = min(deflt_qs, tp->rxq_max);
12633 channel->tx_count = tp->txq_req;
12635 channel->tx_count = min(deflt_qs, tp->txq_max);
12639 static int tg3_set_channels(struct net_device *dev,
12640 struct ethtool_channels *channel)
12642 struct tg3 *tp = netdev_priv(dev);
12644 if (!tg3_flag(tp, SUPPORT_MSIX))
12645 return -EOPNOTSUPP;
12647 if (channel->rx_count > tp->rxq_max ||
12648 channel->tx_count > tp->txq_max)
12651 tp->rxq_req = channel->rx_count;
12652 tp->txq_req = channel->tx_count;
12654 if (!netif_running(dev))
12659 tg3_carrier_off(tp);
12661 tg3_start(tp, true, false, false);
12666 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12668 switch (stringset) {
12670 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12673 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12676 WARN_ON(1); /* we need a WARN() */
12681 static int tg3_set_phys_id(struct net_device *dev,
12682 enum ethtool_phys_id_state state)
12684 struct tg3 *tp = netdev_priv(dev);
12686 if (!netif_running(tp->dev))
12690 case ETHTOOL_ID_ACTIVE:
12691 return 1; /* cycle on/off once per second */
12693 case ETHTOOL_ID_ON:
12694 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12695 LED_CTRL_1000MBPS_ON |
12696 LED_CTRL_100MBPS_ON |
12697 LED_CTRL_10MBPS_ON |
12698 LED_CTRL_TRAFFIC_OVERRIDE |
12699 LED_CTRL_TRAFFIC_BLINK |
12700 LED_CTRL_TRAFFIC_LED);
12703 case ETHTOOL_ID_OFF:
12704 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12705 LED_CTRL_TRAFFIC_OVERRIDE);
12708 case ETHTOOL_ID_INACTIVE:
12709 tw32(MAC_LED_CTRL, tp->led_ctrl);
12716 static void tg3_get_ethtool_stats(struct net_device *dev,
12717 struct ethtool_stats *estats, u64 *tmp_stats)
12719 struct tg3 *tp = netdev_priv(dev);
12722 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12724 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12727 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12731 u32 offset = 0, len = 0;
12734 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12737 if (magic == TG3_EEPROM_MAGIC) {
12738 for (offset = TG3_NVM_DIR_START;
12739 offset < TG3_NVM_DIR_END;
12740 offset += TG3_NVM_DIRENT_SIZE) {
12741 if (tg3_nvram_read(tp, offset, &val))
12744 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12745 TG3_NVM_DIRTYPE_EXTVPD)
12749 if (offset != TG3_NVM_DIR_END) {
12750 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12751 if (tg3_nvram_read(tp, offset + 4, &offset))
12754 offset = tg3_nvram_logical_addr(tp, offset);
12758 if (!offset || !len) {
12759 offset = TG3_NVM_VPD_OFF;
12760 len = TG3_NVM_VPD_LEN;
12763 buf = kmalloc(len, GFP_KERNEL);
12767 if (magic == TG3_EEPROM_MAGIC) {
12768 for (i = 0; i < len; i += 4) {
12769 /* The data is in little-endian format in NVRAM.
12770 * Use the big-endian read routines to preserve
12771 * the byte order as it exists in NVRAM.
12773 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12779 unsigned int pos = 0;
12781 ptr = (u8 *)&buf[0];
12782 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12783 cnt = pci_read_vpd(tp->pdev, pos,
12785 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12803 #define NVRAM_TEST_SIZE 0x100
12804 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12805 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12806 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12807 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12808 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12809 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12810 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12811 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12813 static int tg3_test_nvram(struct tg3 *tp)
12815 u32 csum, magic, len;
12817 int i, j, k, err = 0, size;
12819 if (tg3_flag(tp, NO_NVRAM))
12822 if (tg3_nvram_read(tp, 0, &magic) != 0)
12825 if (magic == TG3_EEPROM_MAGIC)
12826 size = NVRAM_TEST_SIZE;
12827 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12828 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12829 TG3_EEPROM_SB_FORMAT_1) {
12830 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12831 case TG3_EEPROM_SB_REVISION_0:
12832 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12834 case TG3_EEPROM_SB_REVISION_2:
12835 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12837 case TG3_EEPROM_SB_REVISION_3:
12838 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12840 case TG3_EEPROM_SB_REVISION_4:
12841 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12843 case TG3_EEPROM_SB_REVISION_5:
12844 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12846 case TG3_EEPROM_SB_REVISION_6:
12847 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12854 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12855 size = NVRAM_SELFBOOT_HW_SIZE;
12859 buf = kmalloc(size, GFP_KERNEL);
12864 for (i = 0, j = 0; i < size; i += 4, j++) {
12865 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12872 /* Selfboot format */
12873 magic = be32_to_cpu(buf[0]);
12874 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12875 TG3_EEPROM_MAGIC_FW) {
12876 u8 *buf8 = (u8 *) buf, csum8 = 0;
12878 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12879 TG3_EEPROM_SB_REVISION_2) {
12880 /* For rev 2, the csum doesn't include the MBA. */
12881 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12883 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12886 for (i = 0; i < size; i++)
12899 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12900 TG3_EEPROM_MAGIC_HW) {
12901 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12902 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12903 u8 *buf8 = (u8 *) buf;
12905 /* Separate the parity bits and the data bytes. */
12906 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12907 if ((i == 0) || (i == 8)) {
12911 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12912 parity[k++] = buf8[i] & msk;
12914 } else if (i == 16) {
12918 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12919 parity[k++] = buf8[i] & msk;
12922 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12923 parity[k++] = buf8[i] & msk;
12926 data[j++] = buf8[i];
12930 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12931 u8 hw8 = hweight8(data[i]);
12933 if ((hw8 & 0x1) && parity[i])
12935 else if (!(hw8 & 0x1) && !parity[i])
12944 /* Bootstrap checksum at offset 0x10 */
12945 csum = calc_crc((unsigned char *) buf, 0x10);
12946 if (csum != le32_to_cpu(buf[0x10/4]))
12949 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12950 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12951 if (csum != le32_to_cpu(buf[0xfc/4]))
12956 buf = tg3_vpd_readblock(tp, &len);
12960 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12962 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12966 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12969 i += PCI_VPD_LRDT_TAG_SIZE;
12970 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12971 PCI_VPD_RO_KEYWORD_CHKSUM);
12975 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12977 for (i = 0; i <= j; i++)
12978 csum8 += ((u8 *)buf)[i];
12992 #define TG3_SERDES_TIMEOUT_SEC 2
12993 #define TG3_COPPER_TIMEOUT_SEC 6
12995 static int tg3_test_link(struct tg3 *tp)
12999 if (!netif_running(tp->dev))
13002 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13003 max = TG3_SERDES_TIMEOUT_SEC;
13005 max = TG3_COPPER_TIMEOUT_SEC;
13007 for (i = 0; i < max; i++) {
13011 if (msleep_interruptible(1000))
13018 /* Only test the commonly used registers */
13019 static int tg3_test_registers(struct tg3 *tp)
13021 int i, is_5705, is_5750;
13022 u32 offset, read_mask, write_mask, val, save_val, read_val;
13026 #define TG3_FL_5705 0x1
13027 #define TG3_FL_NOT_5705 0x2
13028 #define TG3_FL_NOT_5788 0x4
13029 #define TG3_FL_NOT_5750 0x8
13033 /* MAC Control Registers */
13034 { MAC_MODE, TG3_FL_NOT_5705,
13035 0x00000000, 0x00ef6f8c },
13036 { MAC_MODE, TG3_FL_5705,
13037 0x00000000, 0x01ef6b8c },
13038 { MAC_STATUS, TG3_FL_NOT_5705,
13039 0x03800107, 0x00000000 },
13040 { MAC_STATUS, TG3_FL_5705,
13041 0x03800100, 0x00000000 },
13042 { MAC_ADDR_0_HIGH, 0x0000,
13043 0x00000000, 0x0000ffff },
13044 { MAC_ADDR_0_LOW, 0x0000,
13045 0x00000000, 0xffffffff },
13046 { MAC_RX_MTU_SIZE, 0x0000,
13047 0x00000000, 0x0000ffff },
13048 { MAC_TX_MODE, 0x0000,
13049 0x00000000, 0x00000070 },
13050 { MAC_TX_LENGTHS, 0x0000,
13051 0x00000000, 0x00003fff },
13052 { MAC_RX_MODE, TG3_FL_NOT_5705,
13053 0x00000000, 0x000007fc },
13054 { MAC_RX_MODE, TG3_FL_5705,
13055 0x00000000, 0x000007dc },
13056 { MAC_HASH_REG_0, 0x0000,
13057 0x00000000, 0xffffffff },
13058 { MAC_HASH_REG_1, 0x0000,
13059 0x00000000, 0xffffffff },
13060 { MAC_HASH_REG_2, 0x0000,
13061 0x00000000, 0xffffffff },
13062 { MAC_HASH_REG_3, 0x0000,
13063 0x00000000, 0xffffffff },
13065 /* Receive Data and Receive BD Initiator Control Registers. */
13066 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13067 0x00000000, 0xffffffff },
13068 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13069 0x00000000, 0xffffffff },
13070 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13071 0x00000000, 0x00000003 },
13072 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13073 0x00000000, 0xffffffff },
13074 { RCVDBDI_STD_BD+0, 0x0000,
13075 0x00000000, 0xffffffff },
13076 { RCVDBDI_STD_BD+4, 0x0000,
13077 0x00000000, 0xffffffff },
13078 { RCVDBDI_STD_BD+8, 0x0000,
13079 0x00000000, 0xffff0002 },
13080 { RCVDBDI_STD_BD+0xc, 0x0000,
13081 0x00000000, 0xffffffff },
13083 /* Receive BD Initiator Control Registers. */
13084 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13085 0x00000000, 0xffffffff },
13086 { RCVBDI_STD_THRESH, TG3_FL_5705,
13087 0x00000000, 0x000003ff },
13088 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13089 0x00000000, 0xffffffff },
13091 /* Host Coalescing Control Registers. */
13092 { HOSTCC_MODE, TG3_FL_NOT_5705,
13093 0x00000000, 0x00000004 },
13094 { HOSTCC_MODE, TG3_FL_5705,
13095 0x00000000, 0x000000f6 },
13096 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13097 0x00000000, 0xffffffff },
13098 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13099 0x00000000, 0x000003ff },
13100 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13101 0x00000000, 0xffffffff },
13102 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13103 0x00000000, 0x000003ff },
13104 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13105 0x00000000, 0xffffffff },
13106 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13107 0x00000000, 0x000000ff },
13108 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13109 0x00000000, 0xffffffff },
13110 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13111 0x00000000, 0x000000ff },
13112 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13113 0x00000000, 0xffffffff },
13114 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13115 0x00000000, 0xffffffff },
13116 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13117 0x00000000, 0xffffffff },
13118 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13119 0x00000000, 0x000000ff },
13120 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13121 0x00000000, 0xffffffff },
13122 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13123 0x00000000, 0x000000ff },
13124 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13125 0x00000000, 0xffffffff },
13126 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13127 0x00000000, 0xffffffff },
13128 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13129 0x00000000, 0xffffffff },
13130 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13131 0x00000000, 0xffffffff },
13132 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13133 0x00000000, 0xffffffff },
13134 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13135 0xffffffff, 0x00000000 },
13136 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13137 0xffffffff, 0x00000000 },
13139 /* Buffer Manager Control Registers. */
13140 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13141 0x00000000, 0x007fff80 },
13142 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13143 0x00000000, 0x007fffff },
13144 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13145 0x00000000, 0x0000003f },
13146 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13147 0x00000000, 0x000001ff },
13148 { BUFMGR_MB_HIGH_WATER, 0x0000,
13149 0x00000000, 0x000001ff },
13150 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13151 0xffffffff, 0x00000000 },
13152 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13153 0xffffffff, 0x00000000 },
13155 /* Mailbox Registers */
13156 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13157 0x00000000, 0x000001ff },
13158 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13159 0x00000000, 0x000001ff },
13160 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13161 0x00000000, 0x000007ff },
13162 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13163 0x00000000, 0x000001ff },
13165 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13168 is_5705 = is_5750 = 0;
13169 if (tg3_flag(tp, 5705_PLUS)) {
13171 if (tg3_flag(tp, 5750_PLUS))
13175 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13176 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13179 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13182 if (tg3_flag(tp, IS_5788) &&
13183 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13186 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13189 offset = (u32) reg_tbl[i].offset;
13190 read_mask = reg_tbl[i].read_mask;
13191 write_mask = reg_tbl[i].write_mask;
13193 /* Save the original register content */
13194 save_val = tr32(offset);
13196 /* Determine the read-only value. */
13197 read_val = save_val & read_mask;
13199 /* Write zero to the register, then make sure the read-only bits
13200 * are not changed and the read/write bits are all zeros.
13204 val = tr32(offset);
13206 /* Test the read-only and read/write bits. */
13207 if (((val & read_mask) != read_val) || (val & write_mask))
13210 /* Write ones to all the bits defined by RdMask and WrMask, then
13211 * make sure the read-only bits are not changed and the
13212 * read/write bits are all ones.
13214 tw32(offset, read_mask | write_mask);
13216 val = tr32(offset);
13218 /* Test the read-only bits. */
13219 if ((val & read_mask) != read_val)
13222 /* Test the read/write bits. */
13223 if ((val & write_mask) != write_mask)
13226 tw32(offset, save_val);
13232 if (netif_msg_hw(tp))
13233 netdev_err(tp->dev,
13234 "Register test failed at offset %x\n", offset);
13235 tw32(offset, save_val);
13239 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13241 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13245 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13246 for (j = 0; j < len; j += 4) {
13249 tg3_write_mem(tp, offset + j, test_pattern[i]);
13250 tg3_read_mem(tp, offset + j, &val);
13251 if (val != test_pattern[i])
13258 static int tg3_test_memory(struct tg3 *tp)
13260 static struct mem_entry {
13263 } mem_tbl_570x[] = {
13264 { 0x00000000, 0x00b50},
13265 { 0x00002000, 0x1c000},
13266 { 0xffffffff, 0x00000}
13267 }, mem_tbl_5705[] = {
13268 { 0x00000100, 0x0000c},
13269 { 0x00000200, 0x00008},
13270 { 0x00004000, 0x00800},
13271 { 0x00006000, 0x01000},
13272 { 0x00008000, 0x02000},
13273 { 0x00010000, 0x0e000},
13274 { 0xffffffff, 0x00000}
13275 }, mem_tbl_5755[] = {
13276 { 0x00000200, 0x00008},
13277 { 0x00004000, 0x00800},
13278 { 0x00006000, 0x00800},
13279 { 0x00008000, 0x02000},
13280 { 0x00010000, 0x0c000},
13281 { 0xffffffff, 0x00000}
13282 }, mem_tbl_5906[] = {
13283 { 0x00000200, 0x00008},
13284 { 0x00004000, 0x00400},
13285 { 0x00006000, 0x00400},
13286 { 0x00008000, 0x01000},
13287 { 0x00010000, 0x01000},
13288 { 0xffffffff, 0x00000}
13289 }, mem_tbl_5717[] = {
13290 { 0x00000200, 0x00008},
13291 { 0x00010000, 0x0a000},
13292 { 0x00020000, 0x13c00},
13293 { 0xffffffff, 0x00000}
13294 }, mem_tbl_57765[] = {
13295 { 0x00000200, 0x00008},
13296 { 0x00004000, 0x00800},
13297 { 0x00006000, 0x09800},
13298 { 0x00010000, 0x0a000},
13299 { 0xffffffff, 0x00000}
13301 struct mem_entry *mem_tbl;
13305 if (tg3_flag(tp, 5717_PLUS))
13306 mem_tbl = mem_tbl_5717;
13307 else if (tg3_flag(tp, 57765_CLASS) ||
13308 tg3_asic_rev(tp) == ASIC_REV_5762)
13309 mem_tbl = mem_tbl_57765;
13310 else if (tg3_flag(tp, 5755_PLUS))
13311 mem_tbl = mem_tbl_5755;
13312 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13313 mem_tbl = mem_tbl_5906;
13314 else if (tg3_flag(tp, 5705_PLUS))
13315 mem_tbl = mem_tbl_5705;
13317 mem_tbl = mem_tbl_570x;
13319 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13320 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13328 #define TG3_TSO_MSS 500
13330 #define TG3_TSO_IP_HDR_LEN 20
13331 #define TG3_TSO_TCP_HDR_LEN 20
13332 #define TG3_TSO_TCP_OPT_LEN 12
13334 static const u8 tg3_tso_header[] = {
13336 0x45, 0x00, 0x00, 0x00,
13337 0x00, 0x00, 0x40, 0x00,
13338 0x40, 0x06, 0x00, 0x00,
13339 0x0a, 0x00, 0x00, 0x01,
13340 0x0a, 0x00, 0x00, 0x02,
13341 0x0d, 0x00, 0xe0, 0x00,
13342 0x00, 0x00, 0x01, 0x00,
13343 0x00, 0x00, 0x02, 0x00,
13344 0x80, 0x10, 0x10, 0x00,
13345 0x14, 0x09, 0x00, 0x00,
13346 0x01, 0x01, 0x08, 0x0a,
13347 0x11, 0x11, 0x11, 0x11,
13348 0x11, 0x11, 0x11, 0x11,
13351 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13353 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13354 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13356 struct sk_buff *skb;
13357 u8 *tx_data, *rx_data;
13359 int num_pkts, tx_len, rx_len, i, err;
13360 struct tg3_rx_buffer_desc *desc;
13361 struct tg3_napi *tnapi, *rnapi;
13362 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13364 tnapi = &tp->napi[0];
13365 rnapi = &tp->napi[0];
13366 if (tp->irq_cnt > 1) {
13367 if (tg3_flag(tp, ENABLE_RSS))
13368 rnapi = &tp->napi[1];
13369 if (tg3_flag(tp, ENABLE_TSS))
13370 tnapi = &tp->napi[1];
13372 coal_now = tnapi->coal_now | rnapi->coal_now;
13377 skb = netdev_alloc_skb(tp->dev, tx_len);
13381 tx_data = skb_put(skb, tx_len);
13382 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13383 memset(tx_data + ETH_ALEN, 0x0, 8);
13385 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13387 if (tso_loopback) {
13388 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13390 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13391 TG3_TSO_TCP_OPT_LEN;
13393 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13394 sizeof(tg3_tso_header));
13397 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13398 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13400 /* Set the total length field in the IP header */
13401 iph->tot_len = htons((u16)(mss + hdr_len));
13403 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13404 TXD_FLAG_CPU_POST_DMA);
13406 if (tg3_flag(tp, HW_TSO_1) ||
13407 tg3_flag(tp, HW_TSO_2) ||
13408 tg3_flag(tp, HW_TSO_3)) {
13410 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13411 th = (struct tcphdr *)&tx_data[val];
13414 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13416 if (tg3_flag(tp, HW_TSO_3)) {
13417 mss |= (hdr_len & 0xc) << 12;
13418 if (hdr_len & 0x10)
13419 base_flags |= 0x00000010;
13420 base_flags |= (hdr_len & 0x3e0) << 5;
13421 } else if (tg3_flag(tp, HW_TSO_2))
13422 mss |= hdr_len << 9;
13423 else if (tg3_flag(tp, HW_TSO_1) ||
13424 tg3_asic_rev(tp) == ASIC_REV_5705) {
13425 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13427 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13430 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13433 data_off = ETH_HLEN;
13435 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13436 tx_len > VLAN_ETH_FRAME_LEN)
13437 base_flags |= TXD_FLAG_JMB_PKT;
13440 for (i = data_off; i < tx_len; i++)
13441 tx_data[i] = (u8) (i & 0xff);
13443 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13444 if (pci_dma_mapping_error(tp->pdev, map)) {
13445 dev_kfree_skb(skb);
13449 val = tnapi->tx_prod;
13450 tnapi->tx_buffers[val].skb = skb;
13451 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13453 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13458 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13460 budget = tg3_tx_avail(tnapi);
13461 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13462 base_flags | TXD_FLAG_END, mss, 0)) {
13463 tnapi->tx_buffers[val].skb = NULL;
13464 dev_kfree_skb(skb);
13470 /* Sync BD data before updating mailbox */
13473 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13474 tr32_mailbox(tnapi->prodmbox);
13478 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13479 for (i = 0; i < 35; i++) {
13480 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13485 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13486 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13487 if ((tx_idx == tnapi->tx_prod) &&
13488 (rx_idx == (rx_start_idx + num_pkts)))
13492 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13493 dev_kfree_skb(skb);
13495 if (tx_idx != tnapi->tx_prod)
13498 if (rx_idx != rx_start_idx + num_pkts)
13502 while (rx_idx != rx_start_idx) {
13503 desc = &rnapi->rx_rcb[rx_start_idx++];
13504 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13505 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13507 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13508 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13511 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13514 if (!tso_loopback) {
13515 if (rx_len != tx_len)
13518 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13519 if (opaque_key != RXD_OPAQUE_RING_STD)
13522 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13525 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13526 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13527 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13531 if (opaque_key == RXD_OPAQUE_RING_STD) {
13532 rx_data = tpr->rx_std_buffers[desc_idx].data;
13533 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13535 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13536 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13537 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13542 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13543 PCI_DMA_FROMDEVICE);
13545 rx_data += TG3_RX_OFFSET(tp);
13546 for (i = data_off; i < rx_len; i++, val++) {
13547 if (*(rx_data + i) != (u8) (val & 0xff))
13554 /* tg3_free_rings will unmap and free the rx_data */
13559 #define TG3_STD_LOOPBACK_FAILED 1
13560 #define TG3_JMB_LOOPBACK_FAILED 2
13561 #define TG3_TSO_LOOPBACK_FAILED 4
13562 #define TG3_LOOPBACK_FAILED \
13563 (TG3_STD_LOOPBACK_FAILED | \
13564 TG3_JMB_LOOPBACK_FAILED | \
13565 TG3_TSO_LOOPBACK_FAILED)
13567 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13571 u32 jmb_pkt_sz = 9000;
13574 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13576 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13577 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13579 if (!netif_running(tp->dev)) {
13580 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13581 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13583 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13587 err = tg3_reset_hw(tp, true);
13589 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13590 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13592 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13596 if (tg3_flag(tp, ENABLE_RSS)) {
13599 /* Reroute all rx packets to the 1st queue */
13600 for (i = MAC_RSS_INDIR_TBL_0;
13601 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13605 /* HW errata - mac loopback fails in some cases on 5780.
13606 * Normal traffic and PHY loopback are not affected by
13607 * errata. Also, the MAC loopback test is deprecated for
13608 * all newer ASIC revisions.
13610 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13611 !tg3_flag(tp, CPMU_PRESENT)) {
13612 tg3_mac_loopback(tp, true);
13614 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13615 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13617 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13618 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13619 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13621 tg3_mac_loopback(tp, false);
13624 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13625 !tg3_flag(tp, USE_PHYLIB)) {
13628 tg3_phy_lpbk_set(tp, 0, false);
13630 /* Wait for link */
13631 for (i = 0; i < 100; i++) {
13632 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13637 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13638 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13639 if (tg3_flag(tp, TSO_CAPABLE) &&
13640 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13641 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13642 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13643 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13644 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13647 tg3_phy_lpbk_set(tp, 0, true);
13649 /* All link indications report up, but the hardware
13650 * isn't really ready for about 20 msec. Double it
13655 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13656 data[TG3_EXT_LOOPB_TEST] |=
13657 TG3_STD_LOOPBACK_FAILED;
13658 if (tg3_flag(tp, TSO_CAPABLE) &&
13659 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13660 data[TG3_EXT_LOOPB_TEST] |=
13661 TG3_TSO_LOOPBACK_FAILED;
13662 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13663 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13664 data[TG3_EXT_LOOPB_TEST] |=
13665 TG3_JMB_LOOPBACK_FAILED;
13668 /* Re-enable gphy autopowerdown. */
13669 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13670 tg3_phy_toggle_apd(tp, true);
13673 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13674 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13677 tp->phy_flags |= eee_cap;
13682 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13685 struct tg3 *tp = netdev_priv(dev);
13686 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13688 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13689 if (tg3_power_up(tp)) {
13690 etest->flags |= ETH_TEST_FL_FAILED;
13691 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13694 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13697 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13699 if (tg3_test_nvram(tp) != 0) {
13700 etest->flags |= ETH_TEST_FL_FAILED;
13701 data[TG3_NVRAM_TEST] = 1;
13703 if (!doextlpbk && tg3_test_link(tp)) {
13704 etest->flags |= ETH_TEST_FL_FAILED;
13705 data[TG3_LINK_TEST] = 1;
13707 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13708 int err, err2 = 0, irq_sync = 0;
13710 if (netif_running(dev)) {
13712 tg3_netif_stop(tp);
13716 tg3_full_lock(tp, irq_sync);
13717 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13718 err = tg3_nvram_lock(tp);
13719 tg3_halt_cpu(tp, RX_CPU_BASE);
13720 if (!tg3_flag(tp, 5705_PLUS))
13721 tg3_halt_cpu(tp, TX_CPU_BASE);
13723 tg3_nvram_unlock(tp);
13725 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13728 if (tg3_test_registers(tp) != 0) {
13729 etest->flags |= ETH_TEST_FL_FAILED;
13730 data[TG3_REGISTER_TEST] = 1;
13733 if (tg3_test_memory(tp) != 0) {
13734 etest->flags |= ETH_TEST_FL_FAILED;
13735 data[TG3_MEMORY_TEST] = 1;
13739 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13741 if (tg3_test_loopback(tp, data, doextlpbk))
13742 etest->flags |= ETH_TEST_FL_FAILED;
13744 tg3_full_unlock(tp);
13746 if (tg3_test_interrupt(tp) != 0) {
13747 etest->flags |= ETH_TEST_FL_FAILED;
13748 data[TG3_INTERRUPT_TEST] = 1;
13751 tg3_full_lock(tp, 0);
13753 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13754 if (netif_running(dev)) {
13755 tg3_flag_set(tp, INIT_COMPLETE);
13756 err2 = tg3_restart_hw(tp, true);
13758 tg3_netif_start(tp);
13761 tg3_full_unlock(tp);
13763 if (irq_sync && !err2)
13766 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13767 tg3_power_down_prepare(tp);
13771 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13773 struct tg3 *tp = netdev_priv(dev);
13774 struct hwtstamp_config stmpconf;
13776 if (!tg3_flag(tp, PTP_CAPABLE))
13777 return -EOPNOTSUPP;
13779 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13782 if (stmpconf.flags)
13785 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13786 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13789 switch (stmpconf.rx_filter) {
13790 case HWTSTAMP_FILTER_NONE:
13793 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13794 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13795 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13797 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13798 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13799 TG3_RX_PTP_CTL_SYNC_EVNT;
13801 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13802 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13803 TG3_RX_PTP_CTL_DELAY_REQ;
13805 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13806 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13807 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13809 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13810 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13811 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13813 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13814 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13815 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13817 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13818 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13819 TG3_RX_PTP_CTL_SYNC_EVNT;
13821 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13822 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13823 TG3_RX_PTP_CTL_SYNC_EVNT;
13825 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13826 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13827 TG3_RX_PTP_CTL_SYNC_EVNT;
13829 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13830 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13831 TG3_RX_PTP_CTL_DELAY_REQ;
13833 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13834 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13835 TG3_RX_PTP_CTL_DELAY_REQ;
13837 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13838 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13839 TG3_RX_PTP_CTL_DELAY_REQ;
13845 if (netif_running(dev) && tp->rxptpctl)
13846 tw32(TG3_RX_PTP_CTL,
13847 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13849 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13850 tg3_flag_set(tp, TX_TSTAMP_EN);
13852 tg3_flag_clear(tp, TX_TSTAMP_EN);
13854 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13858 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13860 struct tg3 *tp = netdev_priv(dev);
13861 struct hwtstamp_config stmpconf;
13863 if (!tg3_flag(tp, PTP_CAPABLE))
13864 return -EOPNOTSUPP;
13866 stmpconf.flags = 0;
13867 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13868 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13870 switch (tp->rxptpctl) {
13872 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13874 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13875 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13877 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13878 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13880 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13881 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13883 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13884 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13886 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13887 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13889 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13890 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13892 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13893 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13895 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13896 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13898 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13899 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13901 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13902 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13904 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13905 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13907 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13908 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13915 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13919 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13921 struct mii_ioctl_data *data = if_mii(ifr);
13922 struct tg3 *tp = netdev_priv(dev);
13925 if (tg3_flag(tp, USE_PHYLIB)) {
13926 struct phy_device *phydev;
13927 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13929 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13930 return phy_mii_ioctl(phydev, ifr, cmd);
13935 data->phy_id = tp->phy_addr;
13938 case SIOCGMIIREG: {
13941 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13942 break; /* We have no PHY */
13944 if (!netif_running(dev))
13947 spin_lock_bh(&tp->lock);
13948 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13949 data->reg_num & 0x1f, &mii_regval);
13950 spin_unlock_bh(&tp->lock);
13952 data->val_out = mii_regval;
13958 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13959 break; /* We have no PHY */
13961 if (!netif_running(dev))
13964 spin_lock_bh(&tp->lock);
13965 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13966 data->reg_num & 0x1f, data->val_in);
13967 spin_unlock_bh(&tp->lock);
13971 case SIOCSHWTSTAMP:
13972 return tg3_hwtstamp_set(dev, ifr);
13974 case SIOCGHWTSTAMP:
13975 return tg3_hwtstamp_get(dev, ifr);
13981 return -EOPNOTSUPP;
13984 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13986 struct tg3 *tp = netdev_priv(dev);
13988 memcpy(ec, &tp->coal, sizeof(*ec));
13992 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13994 struct tg3 *tp = netdev_priv(dev);
13995 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13996 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13998 if (!tg3_flag(tp, 5705_PLUS)) {
13999 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
14000 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
14001 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
14002 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
14005 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
14006 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
14007 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
14008 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
14009 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
14010 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
14011 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
14012 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
14013 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14014 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14017 /* No rx interrupts will be generated if both are zero */
14018 if ((ec->rx_coalesce_usecs == 0) &&
14019 (ec->rx_max_coalesced_frames == 0))
14022 /* No tx interrupts will be generated if both are zero */
14023 if ((ec->tx_coalesce_usecs == 0) &&
14024 (ec->tx_max_coalesced_frames == 0))
14027 /* Only copy relevant parameters, ignore all others. */
14028 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14029 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14030 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14031 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14032 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14033 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14034 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14035 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14036 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14038 if (netif_running(dev)) {
14039 tg3_full_lock(tp, 0);
14040 __tg3_set_coalesce(tp, &tp->coal);
14041 tg3_full_unlock(tp);
14046 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14048 struct tg3 *tp = netdev_priv(dev);
14050 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14051 netdev_warn(tp->dev, "Board does not support EEE!\n");
14052 return -EOPNOTSUPP;
14055 if (edata->advertised != tp->eee.advertised) {
14056 netdev_warn(tp->dev,
14057 "Direct manipulation of EEE advertisement is not supported\n");
14061 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14062 netdev_warn(tp->dev,
14063 "Maximal Tx Lpi timer supported is %#x(u)\n",
14064 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14070 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14071 tg3_warn_mgmt_link_flap(tp);
14073 if (netif_running(tp->dev)) {
14074 tg3_full_lock(tp, 0);
14077 tg3_full_unlock(tp);
14083 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14085 struct tg3 *tp = netdev_priv(dev);
14087 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14088 netdev_warn(tp->dev,
14089 "Board does not support EEE!\n");
14090 return -EOPNOTSUPP;
14097 static const struct ethtool_ops tg3_ethtool_ops = {
14098 .get_settings = tg3_get_settings,
14099 .set_settings = tg3_set_settings,
14100 .get_drvinfo = tg3_get_drvinfo,
14101 .get_regs_len = tg3_get_regs_len,
14102 .get_regs = tg3_get_regs,
14103 .get_wol = tg3_get_wol,
14104 .set_wol = tg3_set_wol,
14105 .get_msglevel = tg3_get_msglevel,
14106 .set_msglevel = tg3_set_msglevel,
14107 .nway_reset = tg3_nway_reset,
14108 .get_link = ethtool_op_get_link,
14109 .get_eeprom_len = tg3_get_eeprom_len,
14110 .get_eeprom = tg3_get_eeprom,
14111 .set_eeprom = tg3_set_eeprom,
14112 .get_ringparam = tg3_get_ringparam,
14113 .set_ringparam = tg3_set_ringparam,
14114 .get_pauseparam = tg3_get_pauseparam,
14115 .set_pauseparam = tg3_set_pauseparam,
14116 .self_test = tg3_self_test,
14117 .get_strings = tg3_get_strings,
14118 .set_phys_id = tg3_set_phys_id,
14119 .get_ethtool_stats = tg3_get_ethtool_stats,
14120 .get_coalesce = tg3_get_coalesce,
14121 .set_coalesce = tg3_set_coalesce,
14122 .get_sset_count = tg3_get_sset_count,
14123 .get_rxnfc = tg3_get_rxnfc,
14124 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14125 .get_rxfh = tg3_get_rxfh,
14126 .set_rxfh = tg3_set_rxfh,
14127 .get_channels = tg3_get_channels,
14128 .set_channels = tg3_set_channels,
14129 .get_ts_info = tg3_get_ts_info,
14130 .get_eee = tg3_get_eee,
14131 .set_eee = tg3_set_eee,
14134 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14135 struct rtnl_link_stats64 *stats)
14137 struct tg3 *tp = netdev_priv(dev);
14139 spin_lock_bh(&tp->lock);
14140 if (!tp->hw_stats) {
14141 *stats = tp->net_stats_prev;
14142 spin_unlock_bh(&tp->lock);
14146 tg3_get_nstats(tp, stats);
14147 spin_unlock_bh(&tp->lock);
14152 static void tg3_set_rx_mode(struct net_device *dev)
14154 struct tg3 *tp = netdev_priv(dev);
14156 if (!netif_running(dev))
14159 tg3_full_lock(tp, 0);
14160 __tg3_set_rx_mode(dev);
14161 tg3_full_unlock(tp);
14164 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14167 dev->mtu = new_mtu;
14169 if (new_mtu > ETH_DATA_LEN) {
14170 if (tg3_flag(tp, 5780_CLASS)) {
14171 netdev_update_features(dev);
14172 tg3_flag_clear(tp, TSO_CAPABLE);
14174 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14177 if (tg3_flag(tp, 5780_CLASS)) {
14178 tg3_flag_set(tp, TSO_CAPABLE);
14179 netdev_update_features(dev);
14181 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14185 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14187 struct tg3 *tp = netdev_priv(dev);
14189 bool reset_phy = false;
14191 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14194 if (!netif_running(dev)) {
14195 /* We'll just catch it later when the
14198 tg3_set_mtu(dev, tp, new_mtu);
14204 tg3_netif_stop(tp);
14206 tg3_set_mtu(dev, tp, new_mtu);
14208 tg3_full_lock(tp, 1);
14210 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14212 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14213 * breaks all requests to 256 bytes.
14215 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14218 err = tg3_restart_hw(tp, reset_phy);
14221 tg3_netif_start(tp);
14223 tg3_full_unlock(tp);
14231 static const struct net_device_ops tg3_netdev_ops = {
14232 .ndo_open = tg3_open,
14233 .ndo_stop = tg3_close,
14234 .ndo_start_xmit = tg3_start_xmit,
14235 .ndo_get_stats64 = tg3_get_stats64,
14236 .ndo_validate_addr = eth_validate_addr,
14237 .ndo_set_rx_mode = tg3_set_rx_mode,
14238 .ndo_set_mac_address = tg3_set_mac_addr,
14239 .ndo_do_ioctl = tg3_ioctl,
14240 .ndo_tx_timeout = tg3_tx_timeout,
14241 .ndo_change_mtu = tg3_change_mtu,
14242 .ndo_fix_features = tg3_fix_features,
14243 .ndo_set_features = tg3_set_features,
14244 #ifdef CONFIG_NET_POLL_CONTROLLER
14245 .ndo_poll_controller = tg3_poll_controller,
14249 static void tg3_get_eeprom_size(struct tg3 *tp)
14251 u32 cursize, val, magic;
14253 tp->nvram_size = EEPROM_CHIP_SIZE;
14255 if (tg3_nvram_read(tp, 0, &magic) != 0)
14258 if ((magic != TG3_EEPROM_MAGIC) &&
14259 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14260 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14264 * Size the chip by reading offsets at increasing powers of two.
14265 * When we encounter our validation signature, we know the addressing
14266 * has wrapped around, and thus have our chip size.
14270 while (cursize < tp->nvram_size) {
14271 if (tg3_nvram_read(tp, cursize, &val) != 0)
14280 tp->nvram_size = cursize;
14283 static void tg3_get_nvram_size(struct tg3 *tp)
14287 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14290 /* Selfboot format */
14291 if (val != TG3_EEPROM_MAGIC) {
14292 tg3_get_eeprom_size(tp);
14296 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14298 /* This is confusing. We want to operate on the
14299 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14300 * call will read from NVRAM and byteswap the data
14301 * according to the byteswapping settings for all
14302 * other register accesses. This ensures the data we
14303 * want will always reside in the lower 16-bits.
14304 * However, the data in NVRAM is in LE format, which
14305 * means the data from the NVRAM read will always be
14306 * opposite the endianness of the CPU. The 16-bit
14307 * byteswap then brings the data to CPU endianness.
14309 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14313 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14316 static void tg3_get_nvram_info(struct tg3 *tp)
14320 nvcfg1 = tr32(NVRAM_CFG1);
14321 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14322 tg3_flag_set(tp, FLASH);
14324 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14325 tw32(NVRAM_CFG1, nvcfg1);
14328 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14329 tg3_flag(tp, 5780_CLASS)) {
14330 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14331 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14332 tp->nvram_jedecnum = JEDEC_ATMEL;
14333 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14334 tg3_flag_set(tp, NVRAM_BUFFERED);
14336 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14337 tp->nvram_jedecnum = JEDEC_ATMEL;
14338 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14340 case FLASH_VENDOR_ATMEL_EEPROM:
14341 tp->nvram_jedecnum = JEDEC_ATMEL;
14342 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14343 tg3_flag_set(tp, NVRAM_BUFFERED);
14345 case FLASH_VENDOR_ST:
14346 tp->nvram_jedecnum = JEDEC_ST;
14347 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14348 tg3_flag_set(tp, NVRAM_BUFFERED);
14350 case FLASH_VENDOR_SAIFUN:
14351 tp->nvram_jedecnum = JEDEC_SAIFUN;
14352 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14354 case FLASH_VENDOR_SST_SMALL:
14355 case FLASH_VENDOR_SST_LARGE:
14356 tp->nvram_jedecnum = JEDEC_SST;
14357 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14361 tp->nvram_jedecnum = JEDEC_ATMEL;
14362 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14363 tg3_flag_set(tp, NVRAM_BUFFERED);
14367 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14369 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14370 case FLASH_5752PAGE_SIZE_256:
14371 tp->nvram_pagesize = 256;
14373 case FLASH_5752PAGE_SIZE_512:
14374 tp->nvram_pagesize = 512;
14376 case FLASH_5752PAGE_SIZE_1K:
14377 tp->nvram_pagesize = 1024;
14379 case FLASH_5752PAGE_SIZE_2K:
14380 tp->nvram_pagesize = 2048;
14382 case FLASH_5752PAGE_SIZE_4K:
14383 tp->nvram_pagesize = 4096;
14385 case FLASH_5752PAGE_SIZE_264:
14386 tp->nvram_pagesize = 264;
14388 case FLASH_5752PAGE_SIZE_528:
14389 tp->nvram_pagesize = 528;
14394 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14398 nvcfg1 = tr32(NVRAM_CFG1);
14400 /* NVRAM protection for TPM */
14401 if (nvcfg1 & (1 << 27))
14402 tg3_flag_set(tp, PROTECTED_NVRAM);
14404 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14405 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14406 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14407 tp->nvram_jedecnum = JEDEC_ATMEL;
14408 tg3_flag_set(tp, NVRAM_BUFFERED);
14410 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14411 tp->nvram_jedecnum = JEDEC_ATMEL;
14412 tg3_flag_set(tp, NVRAM_BUFFERED);
14413 tg3_flag_set(tp, FLASH);
14415 case FLASH_5752VENDOR_ST_M45PE10:
14416 case FLASH_5752VENDOR_ST_M45PE20:
14417 case FLASH_5752VENDOR_ST_M45PE40:
14418 tp->nvram_jedecnum = JEDEC_ST;
14419 tg3_flag_set(tp, NVRAM_BUFFERED);
14420 tg3_flag_set(tp, FLASH);
14424 if (tg3_flag(tp, FLASH)) {
14425 tg3_nvram_get_pagesize(tp, nvcfg1);
14427 /* For eeprom, set pagesize to maximum eeprom size */
14428 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14430 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14431 tw32(NVRAM_CFG1, nvcfg1);
14435 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14437 u32 nvcfg1, protect = 0;
14439 nvcfg1 = tr32(NVRAM_CFG1);
14441 /* NVRAM protection for TPM */
14442 if (nvcfg1 & (1 << 27)) {
14443 tg3_flag_set(tp, PROTECTED_NVRAM);
14447 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14449 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14450 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14451 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14452 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14453 tp->nvram_jedecnum = JEDEC_ATMEL;
14454 tg3_flag_set(tp, NVRAM_BUFFERED);
14455 tg3_flag_set(tp, FLASH);
14456 tp->nvram_pagesize = 264;
14457 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14458 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14459 tp->nvram_size = (protect ? 0x3e200 :
14460 TG3_NVRAM_SIZE_512KB);
14461 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14462 tp->nvram_size = (protect ? 0x1f200 :
14463 TG3_NVRAM_SIZE_256KB);
14465 tp->nvram_size = (protect ? 0x1f200 :
14466 TG3_NVRAM_SIZE_128KB);
14468 case FLASH_5752VENDOR_ST_M45PE10:
14469 case FLASH_5752VENDOR_ST_M45PE20:
14470 case FLASH_5752VENDOR_ST_M45PE40:
14471 tp->nvram_jedecnum = JEDEC_ST;
14472 tg3_flag_set(tp, NVRAM_BUFFERED);
14473 tg3_flag_set(tp, FLASH);
14474 tp->nvram_pagesize = 256;
14475 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14476 tp->nvram_size = (protect ?
14477 TG3_NVRAM_SIZE_64KB :
14478 TG3_NVRAM_SIZE_128KB);
14479 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14480 tp->nvram_size = (protect ?
14481 TG3_NVRAM_SIZE_64KB :
14482 TG3_NVRAM_SIZE_256KB);
14484 tp->nvram_size = (protect ?
14485 TG3_NVRAM_SIZE_128KB :
14486 TG3_NVRAM_SIZE_512KB);
14491 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14495 nvcfg1 = tr32(NVRAM_CFG1);
14497 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14498 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14499 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14500 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14501 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14502 tp->nvram_jedecnum = JEDEC_ATMEL;
14503 tg3_flag_set(tp, NVRAM_BUFFERED);
14504 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14506 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14507 tw32(NVRAM_CFG1, nvcfg1);
14509 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14510 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14511 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14512 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14513 tp->nvram_jedecnum = JEDEC_ATMEL;
14514 tg3_flag_set(tp, NVRAM_BUFFERED);
14515 tg3_flag_set(tp, FLASH);
14516 tp->nvram_pagesize = 264;
14518 case FLASH_5752VENDOR_ST_M45PE10:
14519 case FLASH_5752VENDOR_ST_M45PE20:
14520 case FLASH_5752VENDOR_ST_M45PE40:
14521 tp->nvram_jedecnum = JEDEC_ST;
14522 tg3_flag_set(tp, NVRAM_BUFFERED);
14523 tg3_flag_set(tp, FLASH);
14524 tp->nvram_pagesize = 256;
14529 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14531 u32 nvcfg1, protect = 0;
14533 nvcfg1 = tr32(NVRAM_CFG1);
14535 /* NVRAM protection for TPM */
14536 if (nvcfg1 & (1 << 27)) {
14537 tg3_flag_set(tp, PROTECTED_NVRAM);
14541 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14543 case FLASH_5761VENDOR_ATMEL_ADB021D:
14544 case FLASH_5761VENDOR_ATMEL_ADB041D:
14545 case FLASH_5761VENDOR_ATMEL_ADB081D:
14546 case FLASH_5761VENDOR_ATMEL_ADB161D:
14547 case FLASH_5761VENDOR_ATMEL_MDB021D:
14548 case FLASH_5761VENDOR_ATMEL_MDB041D:
14549 case FLASH_5761VENDOR_ATMEL_MDB081D:
14550 case FLASH_5761VENDOR_ATMEL_MDB161D:
14551 tp->nvram_jedecnum = JEDEC_ATMEL;
14552 tg3_flag_set(tp, NVRAM_BUFFERED);
14553 tg3_flag_set(tp, FLASH);
14554 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14555 tp->nvram_pagesize = 256;
14557 case FLASH_5761VENDOR_ST_A_M45PE20:
14558 case FLASH_5761VENDOR_ST_A_M45PE40:
14559 case FLASH_5761VENDOR_ST_A_M45PE80:
14560 case FLASH_5761VENDOR_ST_A_M45PE16:
14561 case FLASH_5761VENDOR_ST_M_M45PE20:
14562 case FLASH_5761VENDOR_ST_M_M45PE40:
14563 case FLASH_5761VENDOR_ST_M_M45PE80:
14564 case FLASH_5761VENDOR_ST_M_M45PE16:
14565 tp->nvram_jedecnum = JEDEC_ST;
14566 tg3_flag_set(tp, NVRAM_BUFFERED);
14567 tg3_flag_set(tp, FLASH);
14568 tp->nvram_pagesize = 256;
14573 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14576 case FLASH_5761VENDOR_ATMEL_ADB161D:
14577 case FLASH_5761VENDOR_ATMEL_MDB161D:
14578 case FLASH_5761VENDOR_ST_A_M45PE16:
14579 case FLASH_5761VENDOR_ST_M_M45PE16:
14580 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14582 case FLASH_5761VENDOR_ATMEL_ADB081D:
14583 case FLASH_5761VENDOR_ATMEL_MDB081D:
14584 case FLASH_5761VENDOR_ST_A_M45PE80:
14585 case FLASH_5761VENDOR_ST_M_M45PE80:
14586 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14588 case FLASH_5761VENDOR_ATMEL_ADB041D:
14589 case FLASH_5761VENDOR_ATMEL_MDB041D:
14590 case FLASH_5761VENDOR_ST_A_M45PE40:
14591 case FLASH_5761VENDOR_ST_M_M45PE40:
14592 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14594 case FLASH_5761VENDOR_ATMEL_ADB021D:
14595 case FLASH_5761VENDOR_ATMEL_MDB021D:
14596 case FLASH_5761VENDOR_ST_A_M45PE20:
14597 case FLASH_5761VENDOR_ST_M_M45PE20:
14598 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14604 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14606 tp->nvram_jedecnum = JEDEC_ATMEL;
14607 tg3_flag_set(tp, NVRAM_BUFFERED);
14608 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14611 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14615 nvcfg1 = tr32(NVRAM_CFG1);
14617 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14618 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14619 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14620 tp->nvram_jedecnum = JEDEC_ATMEL;
14621 tg3_flag_set(tp, NVRAM_BUFFERED);
14622 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14624 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14625 tw32(NVRAM_CFG1, nvcfg1);
14627 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14628 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14629 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14630 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14631 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14632 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14633 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14634 tp->nvram_jedecnum = JEDEC_ATMEL;
14635 tg3_flag_set(tp, NVRAM_BUFFERED);
14636 tg3_flag_set(tp, FLASH);
14638 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14639 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14640 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14641 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14642 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14644 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14645 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14646 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14648 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14649 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14650 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14654 case FLASH_5752VENDOR_ST_M45PE10:
14655 case FLASH_5752VENDOR_ST_M45PE20:
14656 case FLASH_5752VENDOR_ST_M45PE40:
14657 tp->nvram_jedecnum = JEDEC_ST;
14658 tg3_flag_set(tp, NVRAM_BUFFERED);
14659 tg3_flag_set(tp, FLASH);
14661 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14662 case FLASH_5752VENDOR_ST_M45PE10:
14663 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14665 case FLASH_5752VENDOR_ST_M45PE20:
14666 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14668 case FLASH_5752VENDOR_ST_M45PE40:
14669 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14674 tg3_flag_set(tp, NO_NVRAM);
14678 tg3_nvram_get_pagesize(tp, nvcfg1);
14679 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14680 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14684 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14688 nvcfg1 = tr32(NVRAM_CFG1);
14690 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14691 case FLASH_5717VENDOR_ATMEL_EEPROM:
14692 case FLASH_5717VENDOR_MICRO_EEPROM:
14693 tp->nvram_jedecnum = JEDEC_ATMEL;
14694 tg3_flag_set(tp, NVRAM_BUFFERED);
14695 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14697 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14698 tw32(NVRAM_CFG1, nvcfg1);
14700 case FLASH_5717VENDOR_ATMEL_MDB011D:
14701 case FLASH_5717VENDOR_ATMEL_ADB011B:
14702 case FLASH_5717VENDOR_ATMEL_ADB011D:
14703 case FLASH_5717VENDOR_ATMEL_MDB021D:
14704 case FLASH_5717VENDOR_ATMEL_ADB021B:
14705 case FLASH_5717VENDOR_ATMEL_ADB021D:
14706 case FLASH_5717VENDOR_ATMEL_45USPT:
14707 tp->nvram_jedecnum = JEDEC_ATMEL;
14708 tg3_flag_set(tp, NVRAM_BUFFERED);
14709 tg3_flag_set(tp, FLASH);
14711 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14712 case FLASH_5717VENDOR_ATMEL_MDB021D:
14713 /* Detect size with tg3_nvram_get_size() */
14715 case FLASH_5717VENDOR_ATMEL_ADB021B:
14716 case FLASH_5717VENDOR_ATMEL_ADB021D:
14717 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14720 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14724 case FLASH_5717VENDOR_ST_M_M25PE10:
14725 case FLASH_5717VENDOR_ST_A_M25PE10:
14726 case FLASH_5717VENDOR_ST_M_M45PE10:
14727 case FLASH_5717VENDOR_ST_A_M45PE10:
14728 case FLASH_5717VENDOR_ST_M_M25PE20:
14729 case FLASH_5717VENDOR_ST_A_M25PE20:
14730 case FLASH_5717VENDOR_ST_M_M45PE20:
14731 case FLASH_5717VENDOR_ST_A_M45PE20:
14732 case FLASH_5717VENDOR_ST_25USPT:
14733 case FLASH_5717VENDOR_ST_45USPT:
14734 tp->nvram_jedecnum = JEDEC_ST;
14735 tg3_flag_set(tp, NVRAM_BUFFERED);
14736 tg3_flag_set(tp, FLASH);
14738 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14739 case FLASH_5717VENDOR_ST_M_M25PE20:
14740 case FLASH_5717VENDOR_ST_M_M45PE20:
14741 /* Detect size with tg3_nvram_get_size() */
14743 case FLASH_5717VENDOR_ST_A_M25PE20:
14744 case FLASH_5717VENDOR_ST_A_M45PE20:
14745 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14748 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14753 tg3_flag_set(tp, NO_NVRAM);
14757 tg3_nvram_get_pagesize(tp, nvcfg1);
14758 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14759 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14762 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14764 u32 nvcfg1, nvmpinstrp;
14766 nvcfg1 = tr32(NVRAM_CFG1);
14767 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14769 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14770 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14771 tg3_flag_set(tp, NO_NVRAM);
14775 switch (nvmpinstrp) {
14776 case FLASH_5762_EEPROM_HD:
14777 nvmpinstrp = FLASH_5720_EEPROM_HD;
14779 case FLASH_5762_EEPROM_LD:
14780 nvmpinstrp = FLASH_5720_EEPROM_LD;
14782 case FLASH_5720VENDOR_M_ST_M45PE20:
14783 /* This pinstrap supports multiple sizes, so force it
14784 * to read the actual size from location 0xf0.
14786 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14791 switch (nvmpinstrp) {
14792 case FLASH_5720_EEPROM_HD:
14793 case FLASH_5720_EEPROM_LD:
14794 tp->nvram_jedecnum = JEDEC_ATMEL;
14795 tg3_flag_set(tp, NVRAM_BUFFERED);
14797 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14798 tw32(NVRAM_CFG1, nvcfg1);
14799 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14800 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14802 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14804 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14805 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14806 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14807 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14808 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14809 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14810 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14811 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14812 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14813 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14814 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14815 case FLASH_5720VENDOR_ATMEL_45USPT:
14816 tp->nvram_jedecnum = JEDEC_ATMEL;
14817 tg3_flag_set(tp, NVRAM_BUFFERED);
14818 tg3_flag_set(tp, FLASH);
14820 switch (nvmpinstrp) {
14821 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14822 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14823 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14824 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14826 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14827 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14828 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14829 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14831 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14832 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14833 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14836 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14837 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14841 case FLASH_5720VENDOR_M_ST_M25PE10:
14842 case FLASH_5720VENDOR_M_ST_M45PE10:
14843 case FLASH_5720VENDOR_A_ST_M25PE10:
14844 case FLASH_5720VENDOR_A_ST_M45PE10:
14845 case FLASH_5720VENDOR_M_ST_M25PE20:
14846 case FLASH_5720VENDOR_M_ST_M45PE20:
14847 case FLASH_5720VENDOR_A_ST_M25PE20:
14848 case FLASH_5720VENDOR_A_ST_M45PE20:
14849 case FLASH_5720VENDOR_M_ST_M25PE40:
14850 case FLASH_5720VENDOR_M_ST_M45PE40:
14851 case FLASH_5720VENDOR_A_ST_M25PE40:
14852 case FLASH_5720VENDOR_A_ST_M45PE40:
14853 case FLASH_5720VENDOR_M_ST_M25PE80:
14854 case FLASH_5720VENDOR_M_ST_M45PE80:
14855 case FLASH_5720VENDOR_A_ST_M25PE80:
14856 case FLASH_5720VENDOR_A_ST_M45PE80:
14857 case FLASH_5720VENDOR_ST_25USPT:
14858 case FLASH_5720VENDOR_ST_45USPT:
14859 tp->nvram_jedecnum = JEDEC_ST;
14860 tg3_flag_set(tp, NVRAM_BUFFERED);
14861 tg3_flag_set(tp, FLASH);
14863 switch (nvmpinstrp) {
14864 case FLASH_5720VENDOR_M_ST_M25PE20:
14865 case FLASH_5720VENDOR_M_ST_M45PE20:
14866 case FLASH_5720VENDOR_A_ST_M25PE20:
14867 case FLASH_5720VENDOR_A_ST_M45PE20:
14868 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14870 case FLASH_5720VENDOR_M_ST_M25PE40:
14871 case FLASH_5720VENDOR_M_ST_M45PE40:
14872 case FLASH_5720VENDOR_A_ST_M25PE40:
14873 case FLASH_5720VENDOR_A_ST_M45PE40:
14874 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14876 case FLASH_5720VENDOR_M_ST_M25PE80:
14877 case FLASH_5720VENDOR_M_ST_M45PE80:
14878 case FLASH_5720VENDOR_A_ST_M25PE80:
14879 case FLASH_5720VENDOR_A_ST_M45PE80:
14880 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14883 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14884 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14889 tg3_flag_set(tp, NO_NVRAM);
14893 tg3_nvram_get_pagesize(tp, nvcfg1);
14894 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14895 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14897 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14900 if (tg3_nvram_read(tp, 0, &val))
14903 if (val != TG3_EEPROM_MAGIC &&
14904 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14905 tg3_flag_set(tp, NO_NVRAM);
14909 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14910 static void tg3_nvram_init(struct tg3 *tp)
14912 if (tg3_flag(tp, IS_SSB_CORE)) {
14913 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14914 tg3_flag_clear(tp, NVRAM);
14915 tg3_flag_clear(tp, NVRAM_BUFFERED);
14916 tg3_flag_set(tp, NO_NVRAM);
14920 tw32_f(GRC_EEPROM_ADDR,
14921 (EEPROM_ADDR_FSM_RESET |
14922 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14923 EEPROM_ADDR_CLKPERD_SHIFT)));
14927 /* Enable seeprom accesses. */
14928 tw32_f(GRC_LOCAL_CTRL,
14929 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14932 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14933 tg3_asic_rev(tp) != ASIC_REV_5701) {
14934 tg3_flag_set(tp, NVRAM);
14936 if (tg3_nvram_lock(tp)) {
14937 netdev_warn(tp->dev,
14938 "Cannot get nvram lock, %s failed\n",
14942 tg3_enable_nvram_access(tp);
14944 tp->nvram_size = 0;
14946 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14947 tg3_get_5752_nvram_info(tp);
14948 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14949 tg3_get_5755_nvram_info(tp);
14950 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14951 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14952 tg3_asic_rev(tp) == ASIC_REV_5785)
14953 tg3_get_5787_nvram_info(tp);
14954 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14955 tg3_get_5761_nvram_info(tp);
14956 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14957 tg3_get_5906_nvram_info(tp);
14958 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14959 tg3_flag(tp, 57765_CLASS))
14960 tg3_get_57780_nvram_info(tp);
14961 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14962 tg3_asic_rev(tp) == ASIC_REV_5719)
14963 tg3_get_5717_nvram_info(tp);
14964 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14965 tg3_asic_rev(tp) == ASIC_REV_5762)
14966 tg3_get_5720_nvram_info(tp);
14968 tg3_get_nvram_info(tp);
14970 if (tp->nvram_size == 0)
14971 tg3_get_nvram_size(tp);
14973 tg3_disable_nvram_access(tp);
14974 tg3_nvram_unlock(tp);
14977 tg3_flag_clear(tp, NVRAM);
14978 tg3_flag_clear(tp, NVRAM_BUFFERED);
14980 tg3_get_eeprom_size(tp);
14984 struct subsys_tbl_ent {
14985 u16 subsys_vendor, subsys_devid;
14989 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14990 /* Broadcom boards. */
14991 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14992 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14993 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14994 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14995 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14996 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14997 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14998 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14999 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15000 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
15001 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15002 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
15003 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15004 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15005 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15006 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
15007 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15008 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
15009 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15010 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
15011 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15012 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
15015 { TG3PCI_SUBVENDOR_ID_3COM,
15016 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15017 { TG3PCI_SUBVENDOR_ID_3COM,
15018 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15019 { TG3PCI_SUBVENDOR_ID_3COM,
15020 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15021 { TG3PCI_SUBVENDOR_ID_3COM,
15022 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15023 { TG3PCI_SUBVENDOR_ID_3COM,
15024 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15027 { TG3PCI_SUBVENDOR_ID_DELL,
15028 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15029 { TG3PCI_SUBVENDOR_ID_DELL,
15030 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15031 { TG3PCI_SUBVENDOR_ID_DELL,
15032 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15033 { TG3PCI_SUBVENDOR_ID_DELL,
15034 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15036 /* Compaq boards. */
15037 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15038 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15039 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15040 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15041 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15042 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15043 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15044 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15045 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15046 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15049 { TG3PCI_SUBVENDOR_ID_IBM,
15050 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15053 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15057 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15058 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15059 tp->pdev->subsystem_vendor) &&
15060 (subsys_id_to_phy_id[i].subsys_devid ==
15061 tp->pdev->subsystem_device))
15062 return &subsys_id_to_phy_id[i];
15067 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15071 tp->phy_id = TG3_PHY_ID_INVALID;
15072 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15074 /* Assume an onboard device and WOL capable by default. */
15075 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15076 tg3_flag_set(tp, WOL_CAP);
15078 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15079 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15080 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15081 tg3_flag_set(tp, IS_NIC);
15083 val = tr32(VCPU_CFGSHDW);
15084 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15085 tg3_flag_set(tp, ASPM_WORKAROUND);
15086 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15087 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15088 tg3_flag_set(tp, WOL_ENABLE);
15089 device_set_wakeup_enable(&tp->pdev->dev, true);
15094 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15095 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15096 u32 nic_cfg, led_cfg;
15097 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15098 u32 nic_phy_id, ver, eeprom_phy_id;
15099 int eeprom_phy_serdes = 0;
15101 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15102 tp->nic_sram_data_cfg = nic_cfg;
15104 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15105 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15106 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15107 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15108 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15109 (ver > 0) && (ver < 0x100))
15110 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15112 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15113 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15115 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15116 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15117 tg3_asic_rev(tp) == ASIC_REV_5720)
15118 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15120 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15121 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15122 eeprom_phy_serdes = 1;
15124 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15125 if (nic_phy_id != 0) {
15126 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15127 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15129 eeprom_phy_id = (id1 >> 16) << 10;
15130 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15131 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15135 tp->phy_id = eeprom_phy_id;
15136 if (eeprom_phy_serdes) {
15137 if (!tg3_flag(tp, 5705_PLUS))
15138 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15140 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15143 if (tg3_flag(tp, 5750_PLUS))
15144 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15145 SHASTA_EXT_LED_MODE_MASK);
15147 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15151 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15152 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15155 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15156 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15159 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15160 tp->led_ctrl = LED_CTRL_MODE_MAC;
15162 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15163 * read on some older 5700/5701 bootcode.
15165 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15166 tg3_asic_rev(tp) == ASIC_REV_5701)
15167 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15171 case SHASTA_EXT_LED_SHARED:
15172 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15173 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15174 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15175 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15176 LED_CTRL_MODE_PHY_2);
15178 if (tg3_flag(tp, 5717_PLUS) ||
15179 tg3_asic_rev(tp) == ASIC_REV_5762)
15180 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15181 LED_CTRL_BLINK_RATE_MASK;
15185 case SHASTA_EXT_LED_MAC:
15186 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15189 case SHASTA_EXT_LED_COMBO:
15190 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15191 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15192 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15193 LED_CTRL_MODE_PHY_2);
15198 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15199 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15200 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15201 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15203 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15204 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15206 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15207 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15208 if ((tp->pdev->subsystem_vendor ==
15209 PCI_VENDOR_ID_ARIMA) &&
15210 (tp->pdev->subsystem_device == 0x205a ||
15211 tp->pdev->subsystem_device == 0x2063))
15212 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15214 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15215 tg3_flag_set(tp, IS_NIC);
15218 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15219 tg3_flag_set(tp, ENABLE_ASF);
15220 if (tg3_flag(tp, 5750_PLUS))
15221 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15224 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15225 tg3_flag(tp, 5750_PLUS))
15226 tg3_flag_set(tp, ENABLE_APE);
15228 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15229 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15230 tg3_flag_clear(tp, WOL_CAP);
15232 if (tg3_flag(tp, WOL_CAP) &&
15233 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15234 tg3_flag_set(tp, WOL_ENABLE);
15235 device_set_wakeup_enable(&tp->pdev->dev, true);
15238 if (cfg2 & (1 << 17))
15239 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15241 /* serdes signal pre-emphasis in register 0x590 set by */
15242 /* bootcode if bit 18 is set */
15243 if (cfg2 & (1 << 18))
15244 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15246 if ((tg3_flag(tp, 57765_PLUS) ||
15247 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15248 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15249 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15250 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15252 if (tg3_flag(tp, PCI_EXPRESS)) {
15255 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15256 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15257 !tg3_flag(tp, 57765_PLUS) &&
15258 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15259 tg3_flag_set(tp, ASPM_WORKAROUND);
15260 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15261 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15262 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15263 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15266 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15267 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15268 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15269 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15270 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15271 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15273 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15274 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15277 if (tg3_flag(tp, WOL_CAP))
15278 device_set_wakeup_enable(&tp->pdev->dev,
15279 tg3_flag(tp, WOL_ENABLE));
15281 device_set_wakeup_capable(&tp->pdev->dev, false);
15284 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15287 u32 val2, off = offset * 8;
15289 err = tg3_nvram_lock(tp);
15293 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15294 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15295 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15296 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15299 for (i = 0; i < 100; i++) {
15300 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15301 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15302 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15308 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15310 tg3_nvram_unlock(tp);
15311 if (val2 & APE_OTP_STATUS_CMD_DONE)
15317 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15322 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15323 tw32(OTP_CTRL, cmd);
15325 /* Wait for up to 1 ms for command to execute. */
15326 for (i = 0; i < 100; i++) {
15327 val = tr32(OTP_STATUS);
15328 if (val & OTP_STATUS_CMD_DONE)
15333 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15336 /* Read the gphy configuration from the OTP region of the chip. The gphy
15337 * configuration is a 32-bit value that straddles the alignment boundary.
15338 * We do two 32-bit reads and then shift and merge the results.
15340 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15342 u32 bhalf_otp, thalf_otp;
15344 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15346 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15349 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15351 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15354 thalf_otp = tr32(OTP_READ_DATA);
15356 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15358 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15361 bhalf_otp = tr32(OTP_READ_DATA);
15363 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15366 static void tg3_phy_init_link_config(struct tg3 *tp)
15368 u32 adv = ADVERTISED_Autoneg;
15370 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15371 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15372 adv |= ADVERTISED_1000baseT_Half;
15373 adv |= ADVERTISED_1000baseT_Full;
15376 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15377 adv |= ADVERTISED_100baseT_Half |
15378 ADVERTISED_100baseT_Full |
15379 ADVERTISED_10baseT_Half |
15380 ADVERTISED_10baseT_Full |
15383 adv |= ADVERTISED_FIBRE;
15385 tp->link_config.advertising = adv;
15386 tp->link_config.speed = SPEED_UNKNOWN;
15387 tp->link_config.duplex = DUPLEX_UNKNOWN;
15388 tp->link_config.autoneg = AUTONEG_ENABLE;
15389 tp->link_config.active_speed = SPEED_UNKNOWN;
15390 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15395 static int tg3_phy_probe(struct tg3 *tp)
15397 u32 hw_phy_id_1, hw_phy_id_2;
15398 u32 hw_phy_id, hw_phy_id_masked;
15401 /* flow control autonegotiation is default behavior */
15402 tg3_flag_set(tp, PAUSE_AUTONEG);
15403 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15405 if (tg3_flag(tp, ENABLE_APE)) {
15406 switch (tp->pci_fn) {
15408 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15411 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15414 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15417 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15422 if (!tg3_flag(tp, ENABLE_ASF) &&
15423 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15424 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15425 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15426 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15428 if (tg3_flag(tp, USE_PHYLIB))
15429 return tg3_phy_init(tp);
15431 /* Reading the PHY ID register can conflict with ASF
15432 * firmware access to the PHY hardware.
15435 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15436 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15438 /* Now read the physical PHY_ID from the chip and verify
15439 * that it is sane. If it doesn't look good, we fall back
15440 * to either the hard-coded table based PHY_ID and failing
15441 * that the value found in the eeprom area.
15443 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15444 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15446 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15447 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15448 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15450 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15453 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15454 tp->phy_id = hw_phy_id;
15455 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15456 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15458 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15460 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15461 /* Do nothing, phy ID already set up in
15462 * tg3_get_eeprom_hw_cfg().
15465 struct subsys_tbl_ent *p;
15467 /* No eeprom signature? Try the hardcoded
15468 * subsys device table.
15470 p = tg3_lookup_by_subsys(tp);
15472 tp->phy_id = p->phy_id;
15473 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15474 /* For now we saw the IDs 0xbc050cd0,
15475 * 0xbc050f80 and 0xbc050c30 on devices
15476 * connected to an BCM4785 and there are
15477 * probably more. Just assume that the phy is
15478 * supported when it is connected to a SSB core
15485 tp->phy_id == TG3_PHY_ID_BCM8002)
15486 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15490 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15491 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15492 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15493 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15494 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15495 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15496 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15497 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15498 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15499 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15501 tp->eee.supported = SUPPORTED_100baseT_Full |
15502 SUPPORTED_1000baseT_Full;
15503 tp->eee.advertised = ADVERTISED_100baseT_Full |
15504 ADVERTISED_1000baseT_Full;
15505 tp->eee.eee_enabled = 1;
15506 tp->eee.tx_lpi_enabled = 1;
15507 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15510 tg3_phy_init_link_config(tp);
15512 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15513 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15514 !tg3_flag(tp, ENABLE_APE) &&
15515 !tg3_flag(tp, ENABLE_ASF)) {
15518 tg3_readphy(tp, MII_BMSR, &bmsr);
15519 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15520 (bmsr & BMSR_LSTATUS))
15521 goto skip_phy_reset;
15523 err = tg3_phy_reset(tp);
15527 tg3_phy_set_wirespeed(tp);
15529 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15530 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15531 tp->link_config.flowctrl);
15533 tg3_writephy(tp, MII_BMCR,
15534 BMCR_ANENABLE | BMCR_ANRESTART);
15539 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15540 err = tg3_init_5401phy_dsp(tp);
15544 err = tg3_init_5401phy_dsp(tp);
15550 static void tg3_read_vpd(struct tg3 *tp)
15553 unsigned int block_end, rosize, len;
15557 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15561 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15563 goto out_not_found;
15565 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15566 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15567 i += PCI_VPD_LRDT_TAG_SIZE;
15569 if (block_end > vpdlen)
15570 goto out_not_found;
15572 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15573 PCI_VPD_RO_KEYWORD_MFR_ID);
15575 len = pci_vpd_info_field_size(&vpd_data[j]);
15577 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15578 if (j + len > block_end || len != 4 ||
15579 memcmp(&vpd_data[j], "1028", 4))
15582 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15583 PCI_VPD_RO_KEYWORD_VENDOR0);
15587 len = pci_vpd_info_field_size(&vpd_data[j]);
15589 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15590 if (j + len > block_end)
15593 if (len >= sizeof(tp->fw_ver))
15594 len = sizeof(tp->fw_ver) - 1;
15595 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15596 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15601 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15602 PCI_VPD_RO_KEYWORD_PARTNO);
15604 goto out_not_found;
15606 len = pci_vpd_info_field_size(&vpd_data[i]);
15608 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15609 if (len > TG3_BPN_SIZE ||
15610 (len + i) > vpdlen)
15611 goto out_not_found;
15613 memcpy(tp->board_part_number, &vpd_data[i], len);
15617 if (tp->board_part_number[0])
15621 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15622 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15623 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15624 strcpy(tp->board_part_number, "BCM5717");
15625 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15626 strcpy(tp->board_part_number, "BCM5718");
15629 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15630 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15631 strcpy(tp->board_part_number, "BCM57780");
15632 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15633 strcpy(tp->board_part_number, "BCM57760");
15634 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15635 strcpy(tp->board_part_number, "BCM57790");
15636 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15637 strcpy(tp->board_part_number, "BCM57788");
15640 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15641 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15642 strcpy(tp->board_part_number, "BCM57761");
15643 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15644 strcpy(tp->board_part_number, "BCM57765");
15645 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15646 strcpy(tp->board_part_number, "BCM57781");
15647 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15648 strcpy(tp->board_part_number, "BCM57785");
15649 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15650 strcpy(tp->board_part_number, "BCM57791");
15651 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15652 strcpy(tp->board_part_number, "BCM57795");
15655 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15656 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15657 strcpy(tp->board_part_number, "BCM57762");
15658 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15659 strcpy(tp->board_part_number, "BCM57766");
15660 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15661 strcpy(tp->board_part_number, "BCM57782");
15662 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15663 strcpy(tp->board_part_number, "BCM57786");
15666 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15667 strcpy(tp->board_part_number, "BCM95906");
15670 strcpy(tp->board_part_number, "none");
15674 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15678 if (tg3_nvram_read(tp, offset, &val) ||
15679 (val & 0xfc000000) != 0x0c000000 ||
15680 tg3_nvram_read(tp, offset + 4, &val) ||
15687 static void tg3_read_bc_ver(struct tg3 *tp)
15689 u32 val, offset, start, ver_offset;
15691 bool newver = false;
15693 if (tg3_nvram_read(tp, 0xc, &offset) ||
15694 tg3_nvram_read(tp, 0x4, &start))
15697 offset = tg3_nvram_logical_addr(tp, offset);
15699 if (tg3_nvram_read(tp, offset, &val))
15702 if ((val & 0xfc000000) == 0x0c000000) {
15703 if (tg3_nvram_read(tp, offset + 4, &val))
15710 dst_off = strlen(tp->fw_ver);
15713 if (TG3_VER_SIZE - dst_off < 16 ||
15714 tg3_nvram_read(tp, offset + 8, &ver_offset))
15717 offset = offset + ver_offset - start;
15718 for (i = 0; i < 16; i += 4) {
15720 if (tg3_nvram_read_be32(tp, offset + i, &v))
15723 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15728 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15731 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15732 TG3_NVM_BCVER_MAJSFT;
15733 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15734 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15735 "v%d.%02d", major, minor);
15739 static void tg3_read_hwsb_ver(struct tg3 *tp)
15741 u32 val, major, minor;
15743 /* Use native endian representation */
15744 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15747 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15748 TG3_NVM_HWSB_CFG1_MAJSFT;
15749 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15750 TG3_NVM_HWSB_CFG1_MINSFT;
15752 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15755 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15757 u32 offset, major, minor, build;
15759 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15761 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15764 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15765 case TG3_EEPROM_SB_REVISION_0:
15766 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15768 case TG3_EEPROM_SB_REVISION_2:
15769 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15771 case TG3_EEPROM_SB_REVISION_3:
15772 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15774 case TG3_EEPROM_SB_REVISION_4:
15775 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15777 case TG3_EEPROM_SB_REVISION_5:
15778 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15780 case TG3_EEPROM_SB_REVISION_6:
15781 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15787 if (tg3_nvram_read(tp, offset, &val))
15790 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15791 TG3_EEPROM_SB_EDH_BLD_SHFT;
15792 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15793 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15794 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15796 if (minor > 99 || build > 26)
15799 offset = strlen(tp->fw_ver);
15800 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15801 " v%d.%02d", major, minor);
15804 offset = strlen(tp->fw_ver);
15805 if (offset < TG3_VER_SIZE - 1)
15806 tp->fw_ver[offset] = 'a' + build - 1;
15810 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15812 u32 val, offset, start;
15815 for (offset = TG3_NVM_DIR_START;
15816 offset < TG3_NVM_DIR_END;
15817 offset += TG3_NVM_DIRENT_SIZE) {
15818 if (tg3_nvram_read(tp, offset, &val))
15821 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15825 if (offset == TG3_NVM_DIR_END)
15828 if (!tg3_flag(tp, 5705_PLUS))
15829 start = 0x08000000;
15830 else if (tg3_nvram_read(tp, offset - 4, &start))
15833 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15834 !tg3_fw_img_is_valid(tp, offset) ||
15835 tg3_nvram_read(tp, offset + 8, &val))
15838 offset += val - start;
15840 vlen = strlen(tp->fw_ver);
15842 tp->fw_ver[vlen++] = ',';
15843 tp->fw_ver[vlen++] = ' ';
15845 for (i = 0; i < 4; i++) {
15847 if (tg3_nvram_read_be32(tp, offset, &v))
15850 offset += sizeof(v);
15852 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15853 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15857 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15862 static void tg3_probe_ncsi(struct tg3 *tp)
15866 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15867 if (apedata != APE_SEG_SIG_MAGIC)
15870 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15871 if (!(apedata & APE_FW_STATUS_READY))
15874 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15875 tg3_flag_set(tp, APE_HAS_NCSI);
15878 static void tg3_read_dash_ver(struct tg3 *tp)
15884 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15886 if (tg3_flag(tp, APE_HAS_NCSI))
15888 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15893 vlen = strlen(tp->fw_ver);
15895 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15897 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15898 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15899 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15900 (apedata & APE_FW_VERSION_BLDMSK));
15903 static void tg3_read_otp_ver(struct tg3 *tp)
15907 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15910 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15911 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15912 TG3_OTP_MAGIC0_VALID(val)) {
15913 u64 val64 = (u64) val << 32 | val2;
15917 for (i = 0; i < 7; i++) {
15918 if ((val64 & 0xff) == 0)
15920 ver = val64 & 0xff;
15923 vlen = strlen(tp->fw_ver);
15924 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15928 static void tg3_read_fw_ver(struct tg3 *tp)
15931 bool vpd_vers = false;
15933 if (tp->fw_ver[0] != 0)
15936 if (tg3_flag(tp, NO_NVRAM)) {
15937 strcat(tp->fw_ver, "sb");
15938 tg3_read_otp_ver(tp);
15942 if (tg3_nvram_read(tp, 0, &val))
15945 if (val == TG3_EEPROM_MAGIC)
15946 tg3_read_bc_ver(tp);
15947 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15948 tg3_read_sb_ver(tp, val);
15949 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15950 tg3_read_hwsb_ver(tp);
15952 if (tg3_flag(tp, ENABLE_ASF)) {
15953 if (tg3_flag(tp, ENABLE_APE)) {
15954 tg3_probe_ncsi(tp);
15956 tg3_read_dash_ver(tp);
15957 } else if (!vpd_vers) {
15958 tg3_read_mgmtfw_ver(tp);
15962 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15965 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15967 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15968 return TG3_RX_RET_MAX_SIZE_5717;
15969 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15970 return TG3_RX_RET_MAX_SIZE_5700;
15972 return TG3_RX_RET_MAX_SIZE_5705;
15975 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
15976 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15977 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15978 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15982 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15984 struct pci_dev *peer;
15985 unsigned int func, devnr = tp->pdev->devfn & ~7;
15987 for (func = 0; func < 8; func++) {
15988 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15989 if (peer && peer != tp->pdev)
15993 /* 5704 can be configured in single-port mode, set peer to
15994 * tp->pdev in that case.
16002 * We don't need to keep the refcount elevated; there's no way
16003 * to remove one half of this device without removing the other
16010 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16012 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16013 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16016 /* All devices that use the alternate
16017 * ASIC REV location have a CPMU.
16019 tg3_flag_set(tp, CPMU_PRESENT);
16021 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16022 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16023 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16024 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16025 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16026 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16027 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16029 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16030 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16031 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16032 reg = TG3PCI_GEN2_PRODID_ASICREV;
16033 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16034 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16035 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16036 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16037 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16040 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16041 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16042 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16043 reg = TG3PCI_GEN15_PRODID_ASICREV;
16045 reg = TG3PCI_PRODID_ASICREV;
16047 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16050 /* Wrong chip ID in 5752 A0. This code can be removed later
16051 * as A0 is not in production.
16053 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16054 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16056 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16057 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16059 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16060 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16061 tg3_asic_rev(tp) == ASIC_REV_5720)
16062 tg3_flag_set(tp, 5717_PLUS);
16064 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16065 tg3_asic_rev(tp) == ASIC_REV_57766)
16066 tg3_flag_set(tp, 57765_CLASS);
16068 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16069 tg3_asic_rev(tp) == ASIC_REV_5762)
16070 tg3_flag_set(tp, 57765_PLUS);
16072 /* Intentionally exclude ASIC_REV_5906 */
16073 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16074 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16075 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16076 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16077 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16078 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16079 tg3_flag(tp, 57765_PLUS))
16080 tg3_flag_set(tp, 5755_PLUS);
16082 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16083 tg3_asic_rev(tp) == ASIC_REV_5714)
16084 tg3_flag_set(tp, 5780_CLASS);
16086 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16087 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16088 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16089 tg3_flag(tp, 5755_PLUS) ||
16090 tg3_flag(tp, 5780_CLASS))
16091 tg3_flag_set(tp, 5750_PLUS);
16093 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16094 tg3_flag(tp, 5750_PLUS))
16095 tg3_flag_set(tp, 5705_PLUS);
16098 static bool tg3_10_100_only_device(struct tg3 *tp,
16099 const struct pci_device_id *ent)
16101 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16103 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16104 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16105 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16108 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16109 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16110 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16120 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16123 u32 pci_state_reg, grc_misc_cfg;
16128 /* Force memory write invalidate off. If we leave it on,
16129 * then on 5700_BX chips we have to enable a workaround.
16130 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16131 * to match the cacheline size. The Broadcom driver have this
16132 * workaround but turns MWI off all the times so never uses
16133 * it. This seems to suggest that the workaround is insufficient.
16135 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16136 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16137 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16139 /* Important! -- Make sure register accesses are byteswapped
16140 * correctly. Also, for those chips that require it, make
16141 * sure that indirect register accesses are enabled before
16142 * the first operation.
16144 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16146 tp->misc_host_ctrl |= (misc_ctrl_reg &
16147 MISC_HOST_CTRL_CHIPREV);
16148 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16149 tp->misc_host_ctrl);
16151 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16153 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16154 * we need to disable memory and use config. cycles
16155 * only to access all registers. The 5702/03 chips
16156 * can mistakenly decode the special cycles from the
16157 * ICH chipsets as memory write cycles, causing corruption
16158 * of register and memory space. Only certain ICH bridges
16159 * will drive special cycles with non-zero data during the
16160 * address phase which can fall within the 5703's address
16161 * range. This is not an ICH bug as the PCI spec allows
16162 * non-zero address during special cycles. However, only
16163 * these ICH bridges are known to drive non-zero addresses
16164 * during special cycles.
16166 * Since special cycles do not cross PCI bridges, we only
16167 * enable this workaround if the 5703 is on the secondary
16168 * bus of these ICH bridges.
16170 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16171 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16172 static struct tg3_dev_id {
16176 } ich_chipsets[] = {
16177 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16179 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16181 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16183 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16187 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16188 struct pci_dev *bridge = NULL;
16190 while (pci_id->vendor != 0) {
16191 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16197 if (pci_id->rev != PCI_ANY_ID) {
16198 if (bridge->revision > pci_id->rev)
16201 if (bridge->subordinate &&
16202 (bridge->subordinate->number ==
16203 tp->pdev->bus->number)) {
16204 tg3_flag_set(tp, ICH_WORKAROUND);
16205 pci_dev_put(bridge);
16211 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16212 static struct tg3_dev_id {
16215 } bridge_chipsets[] = {
16216 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16217 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16220 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16221 struct pci_dev *bridge = NULL;
16223 while (pci_id->vendor != 0) {
16224 bridge = pci_get_device(pci_id->vendor,
16231 if (bridge->subordinate &&
16232 (bridge->subordinate->number <=
16233 tp->pdev->bus->number) &&
16234 (bridge->subordinate->busn_res.end >=
16235 tp->pdev->bus->number)) {
16236 tg3_flag_set(tp, 5701_DMA_BUG);
16237 pci_dev_put(bridge);
16243 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16244 * DMA addresses > 40-bit. This bridge may have other additional
16245 * 57xx devices behind it in some 4-port NIC designs for example.
16246 * Any tg3 device found behind the bridge will also need the 40-bit
16249 if (tg3_flag(tp, 5780_CLASS)) {
16250 tg3_flag_set(tp, 40BIT_DMA_BUG);
16251 tp->msi_cap = tp->pdev->msi_cap;
16253 struct pci_dev *bridge = NULL;
16256 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16257 PCI_DEVICE_ID_SERVERWORKS_EPB,
16259 if (bridge && bridge->subordinate &&
16260 (bridge->subordinate->number <=
16261 tp->pdev->bus->number) &&
16262 (bridge->subordinate->busn_res.end >=
16263 tp->pdev->bus->number)) {
16264 tg3_flag_set(tp, 40BIT_DMA_BUG);
16265 pci_dev_put(bridge);
16271 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16272 tg3_asic_rev(tp) == ASIC_REV_5714)
16273 tp->pdev_peer = tg3_find_peer(tp);
16275 /* Determine TSO capabilities */
16276 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16277 ; /* Do nothing. HW bug. */
16278 else if (tg3_flag(tp, 57765_PLUS))
16279 tg3_flag_set(tp, HW_TSO_3);
16280 else if (tg3_flag(tp, 5755_PLUS) ||
16281 tg3_asic_rev(tp) == ASIC_REV_5906)
16282 tg3_flag_set(tp, HW_TSO_2);
16283 else if (tg3_flag(tp, 5750_PLUS)) {
16284 tg3_flag_set(tp, HW_TSO_1);
16285 tg3_flag_set(tp, TSO_BUG);
16286 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16287 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16288 tg3_flag_clear(tp, TSO_BUG);
16289 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16290 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16291 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16292 tg3_flag_set(tp, FW_TSO);
16293 tg3_flag_set(tp, TSO_BUG);
16294 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16295 tp->fw_needed = FIRMWARE_TG3TSO5;
16297 tp->fw_needed = FIRMWARE_TG3TSO;
16300 /* Selectively allow TSO based on operating conditions */
16301 if (tg3_flag(tp, HW_TSO_1) ||
16302 tg3_flag(tp, HW_TSO_2) ||
16303 tg3_flag(tp, HW_TSO_3) ||
16304 tg3_flag(tp, FW_TSO)) {
16305 /* For firmware TSO, assume ASF is disabled.
16306 * We'll disable TSO later if we discover ASF
16307 * is enabled in tg3_get_eeprom_hw_cfg().
16309 tg3_flag_set(tp, TSO_CAPABLE);
16311 tg3_flag_clear(tp, TSO_CAPABLE);
16312 tg3_flag_clear(tp, TSO_BUG);
16313 tp->fw_needed = NULL;
16316 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16317 tp->fw_needed = FIRMWARE_TG3;
16319 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16320 tp->fw_needed = FIRMWARE_TG357766;
16324 if (tg3_flag(tp, 5750_PLUS)) {
16325 tg3_flag_set(tp, SUPPORT_MSI);
16326 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16327 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16328 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16329 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16330 tp->pdev_peer == tp->pdev))
16331 tg3_flag_clear(tp, SUPPORT_MSI);
16333 if (tg3_flag(tp, 5755_PLUS) ||
16334 tg3_asic_rev(tp) == ASIC_REV_5906) {
16335 tg3_flag_set(tp, 1SHOT_MSI);
16338 if (tg3_flag(tp, 57765_PLUS)) {
16339 tg3_flag_set(tp, SUPPORT_MSIX);
16340 tp->irq_max = TG3_IRQ_MAX_VECS;
16346 if (tp->irq_max > 1) {
16347 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16348 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16350 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16351 tg3_asic_rev(tp) == ASIC_REV_5720)
16352 tp->txq_max = tp->irq_max - 1;
16355 if (tg3_flag(tp, 5755_PLUS) ||
16356 tg3_asic_rev(tp) == ASIC_REV_5906)
16357 tg3_flag_set(tp, SHORT_DMA_BUG);
16359 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16360 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16362 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16363 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16364 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16365 tg3_asic_rev(tp) == ASIC_REV_5762)
16366 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16368 if (tg3_flag(tp, 57765_PLUS) &&
16369 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16370 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16372 if (!tg3_flag(tp, 5705_PLUS) ||
16373 tg3_flag(tp, 5780_CLASS) ||
16374 tg3_flag(tp, USE_JUMBO_BDFLAG))
16375 tg3_flag_set(tp, JUMBO_CAPABLE);
16377 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16380 if (pci_is_pcie(tp->pdev)) {
16383 tg3_flag_set(tp, PCI_EXPRESS);
16385 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16386 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16387 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16388 tg3_flag_clear(tp, HW_TSO_2);
16389 tg3_flag_clear(tp, TSO_CAPABLE);
16391 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16392 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16393 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16394 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16395 tg3_flag_set(tp, CLKREQ_BUG);
16396 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16397 tg3_flag_set(tp, L1PLLPD_EN);
16399 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16400 /* BCM5785 devices are effectively PCIe devices, and should
16401 * follow PCIe codepaths, but do not have a PCIe capabilities
16404 tg3_flag_set(tp, PCI_EXPRESS);
16405 } else if (!tg3_flag(tp, 5705_PLUS) ||
16406 tg3_flag(tp, 5780_CLASS)) {
16407 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16408 if (!tp->pcix_cap) {
16409 dev_err(&tp->pdev->dev,
16410 "Cannot find PCI-X capability, aborting\n");
16414 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16415 tg3_flag_set(tp, PCIX_MODE);
16418 /* If we have an AMD 762 or VIA K8T800 chipset, write
16419 * reordering to the mailbox registers done by the host
16420 * controller can cause major troubles. We read back from
16421 * every mailbox register write to force the writes to be
16422 * posted to the chip in order.
16424 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16425 !tg3_flag(tp, PCI_EXPRESS))
16426 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16428 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16429 &tp->pci_cacheline_sz);
16430 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16431 &tp->pci_lat_timer);
16432 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16433 tp->pci_lat_timer < 64) {
16434 tp->pci_lat_timer = 64;
16435 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16436 tp->pci_lat_timer);
16439 /* Important! -- It is critical that the PCI-X hw workaround
16440 * situation is decided before the first MMIO register access.
16442 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16443 /* 5700 BX chips need to have their TX producer index
16444 * mailboxes written twice to workaround a bug.
16446 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16448 /* If we are in PCI-X mode, enable register write workaround.
16450 * The workaround is to use indirect register accesses
16451 * for all chip writes not to mailbox registers.
16453 if (tg3_flag(tp, PCIX_MODE)) {
16456 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16458 /* The chip can have it's power management PCI config
16459 * space registers clobbered due to this bug.
16460 * So explicitly force the chip into D0 here.
16462 pci_read_config_dword(tp->pdev,
16463 tp->pdev->pm_cap + PCI_PM_CTRL,
16465 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16466 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16467 pci_write_config_dword(tp->pdev,
16468 tp->pdev->pm_cap + PCI_PM_CTRL,
16471 /* Also, force SERR#/PERR# in PCI command. */
16472 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16473 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16474 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16478 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16479 tg3_flag_set(tp, PCI_HIGH_SPEED);
16480 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16481 tg3_flag_set(tp, PCI_32BIT);
16483 /* Chip-specific fixup from Broadcom driver */
16484 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16485 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16486 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16487 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16490 /* Default fast path register access methods */
16491 tp->read32 = tg3_read32;
16492 tp->write32 = tg3_write32;
16493 tp->read32_mbox = tg3_read32;
16494 tp->write32_mbox = tg3_write32;
16495 tp->write32_tx_mbox = tg3_write32;
16496 tp->write32_rx_mbox = tg3_write32;
16498 /* Various workaround register access methods */
16499 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16500 tp->write32 = tg3_write_indirect_reg32;
16501 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16502 (tg3_flag(tp, PCI_EXPRESS) &&
16503 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16505 * Back to back register writes can cause problems on these
16506 * chips, the workaround is to read back all reg writes
16507 * except those to mailbox regs.
16509 * See tg3_write_indirect_reg32().
16511 tp->write32 = tg3_write_flush_reg32;
16514 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16515 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16516 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16517 tp->write32_rx_mbox = tg3_write_flush_reg32;
16520 if (tg3_flag(tp, ICH_WORKAROUND)) {
16521 tp->read32 = tg3_read_indirect_reg32;
16522 tp->write32 = tg3_write_indirect_reg32;
16523 tp->read32_mbox = tg3_read_indirect_mbox;
16524 tp->write32_mbox = tg3_write_indirect_mbox;
16525 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16526 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16531 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16532 pci_cmd &= ~PCI_COMMAND_MEMORY;
16533 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16535 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16536 tp->read32_mbox = tg3_read32_mbox_5906;
16537 tp->write32_mbox = tg3_write32_mbox_5906;
16538 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16539 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16542 if (tp->write32 == tg3_write_indirect_reg32 ||
16543 (tg3_flag(tp, PCIX_MODE) &&
16544 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16545 tg3_asic_rev(tp) == ASIC_REV_5701)))
16546 tg3_flag_set(tp, SRAM_USE_CONFIG);
16548 /* The memory arbiter has to be enabled in order for SRAM accesses
16549 * to succeed. Normally on powerup the tg3 chip firmware will make
16550 * sure it is enabled, but other entities such as system netboot
16551 * code might disable it.
16553 val = tr32(MEMARB_MODE);
16554 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16556 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16557 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16558 tg3_flag(tp, 5780_CLASS)) {
16559 if (tg3_flag(tp, PCIX_MODE)) {
16560 pci_read_config_dword(tp->pdev,
16561 tp->pcix_cap + PCI_X_STATUS,
16563 tp->pci_fn = val & 0x7;
16565 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16566 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16567 tg3_asic_rev(tp) == ASIC_REV_5720) {
16568 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16569 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16570 val = tr32(TG3_CPMU_STATUS);
16572 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16573 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16575 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16576 TG3_CPMU_STATUS_FSHFT_5719;
16579 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16580 tp->write32_tx_mbox = tg3_write_flush_reg32;
16581 tp->write32_rx_mbox = tg3_write_flush_reg32;
16584 /* Get eeprom hw config before calling tg3_set_power_state().
16585 * In particular, the TG3_FLAG_IS_NIC flag must be
16586 * determined before calling tg3_set_power_state() so that
16587 * we know whether or not to switch out of Vaux power.
16588 * When the flag is set, it means that GPIO1 is used for eeprom
16589 * write protect and also implies that it is a LOM where GPIOs
16590 * are not used to switch power.
16592 tg3_get_eeprom_hw_cfg(tp);
16594 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16595 tg3_flag_clear(tp, TSO_CAPABLE);
16596 tg3_flag_clear(tp, TSO_BUG);
16597 tp->fw_needed = NULL;
16600 if (tg3_flag(tp, ENABLE_APE)) {
16601 /* Allow reads and writes to the
16602 * APE register and memory space.
16604 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16605 PCISTATE_ALLOW_APE_SHMEM_WR |
16606 PCISTATE_ALLOW_APE_PSPACE_WR;
16607 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16610 tg3_ape_lock_init(tp);
16613 /* Set up tp->grc_local_ctrl before calling
16614 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16615 * will bring 5700's external PHY out of reset.
16616 * It is also used as eeprom write protect on LOMs.
16618 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16619 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16620 tg3_flag(tp, EEPROM_WRITE_PROT))
16621 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16622 GRC_LCLCTRL_GPIO_OUTPUT1);
16623 /* Unused GPIO3 must be driven as output on 5752 because there
16624 * are no pull-up resistors on unused GPIO pins.
16626 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16627 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16629 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16630 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16631 tg3_flag(tp, 57765_CLASS))
16632 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16634 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16635 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16636 /* Turn off the debug UART. */
16637 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16638 if (tg3_flag(tp, IS_NIC))
16639 /* Keep VMain power. */
16640 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16641 GRC_LCLCTRL_GPIO_OUTPUT0;
16644 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16645 tp->grc_local_ctrl |=
16646 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16648 /* Switch out of Vaux if it is a NIC */
16649 tg3_pwrsrc_switch_to_vmain(tp);
16651 /* Derive initial jumbo mode from MTU assigned in
16652 * ether_setup() via the alloc_etherdev() call
16654 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16655 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16657 /* Determine WakeOnLan speed to use. */
16658 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16659 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16660 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16661 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16662 tg3_flag_clear(tp, WOL_SPEED_100MB);
16664 tg3_flag_set(tp, WOL_SPEED_100MB);
16667 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16668 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16670 /* A few boards don't want Ethernet@WireSpeed phy feature */
16671 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16672 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16673 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16674 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16675 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16676 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16677 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16679 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16680 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16681 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16682 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16683 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16685 if (tg3_flag(tp, 5705_PLUS) &&
16686 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16687 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16688 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16689 !tg3_flag(tp, 57765_PLUS)) {
16690 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16691 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16692 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16693 tg3_asic_rev(tp) == ASIC_REV_5761) {
16694 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16695 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16696 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16697 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16698 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16700 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16703 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16704 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16705 tp->phy_otp = tg3_read_otp_phycfg(tp);
16706 if (tp->phy_otp == 0)
16707 tp->phy_otp = TG3_OTP_DEFAULT;
16710 if (tg3_flag(tp, CPMU_PRESENT))
16711 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16713 tp->mi_mode = MAC_MI_MODE_BASE;
16715 tp->coalesce_mode = 0;
16716 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16717 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16718 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16720 /* Set these bits to enable statistics workaround. */
16721 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16722 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16723 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16724 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16725 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16726 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16729 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16730 tg3_asic_rev(tp) == ASIC_REV_57780)
16731 tg3_flag_set(tp, USE_PHYLIB);
16733 err = tg3_mdio_init(tp);
16737 /* Initialize data/descriptor byte/word swapping. */
16738 val = tr32(GRC_MODE);
16739 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16740 tg3_asic_rev(tp) == ASIC_REV_5762)
16741 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16742 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16743 GRC_MODE_B2HRX_ENABLE |
16744 GRC_MODE_HTX2B_ENABLE |
16745 GRC_MODE_HOST_STACKUP);
16747 val &= GRC_MODE_HOST_STACKUP;
16749 tw32(GRC_MODE, val | tp->grc_mode);
16751 tg3_switch_clocks(tp);
16753 /* Clear this out for sanity. */
16754 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16756 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16757 tw32(TG3PCI_REG_BASE_ADDR, 0);
16759 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16761 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16762 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16763 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16764 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16765 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16766 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16767 void __iomem *sram_base;
16769 /* Write some dummy words into the SRAM status block
16770 * area, see if it reads back correctly. If the return
16771 * value is bad, force enable the PCIX workaround.
16773 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16775 writel(0x00000000, sram_base);
16776 writel(0x00000000, sram_base + 4);
16777 writel(0xffffffff, sram_base + 4);
16778 if (readl(sram_base) != 0x00000000)
16779 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16784 tg3_nvram_init(tp);
16786 /* If the device has an NVRAM, no need to load patch firmware */
16787 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16788 !tg3_flag(tp, NO_NVRAM))
16789 tp->fw_needed = NULL;
16791 grc_misc_cfg = tr32(GRC_MISC_CFG);
16792 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16794 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16795 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16796 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16797 tg3_flag_set(tp, IS_5788);
16799 if (!tg3_flag(tp, IS_5788) &&
16800 tg3_asic_rev(tp) != ASIC_REV_5700)
16801 tg3_flag_set(tp, TAGGED_STATUS);
16802 if (tg3_flag(tp, TAGGED_STATUS)) {
16803 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16804 HOSTCC_MODE_CLRTICK_TXBD);
16806 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16807 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16808 tp->misc_host_ctrl);
16811 /* Preserve the APE MAC_MODE bits */
16812 if (tg3_flag(tp, ENABLE_APE))
16813 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16817 if (tg3_10_100_only_device(tp, ent))
16818 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16820 err = tg3_phy_probe(tp);
16822 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16823 /* ... but do not return immediately ... */
16828 tg3_read_fw_ver(tp);
16830 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16831 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16833 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16834 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16836 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16839 /* 5700 {AX,BX} chips have a broken status block link
16840 * change bit implementation, so we must use the
16841 * status register in those cases.
16843 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16844 tg3_flag_set(tp, USE_LINKCHG_REG);
16846 tg3_flag_clear(tp, USE_LINKCHG_REG);
16848 /* The led_ctrl is set during tg3_phy_probe, here we might
16849 * have to force the link status polling mechanism based
16850 * upon subsystem IDs.
16852 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16853 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16854 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16855 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16856 tg3_flag_set(tp, USE_LINKCHG_REG);
16859 /* For all SERDES we poll the MAC status register. */
16860 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16861 tg3_flag_set(tp, POLL_SERDES);
16863 tg3_flag_clear(tp, POLL_SERDES);
16865 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16866 tg3_flag_set(tp, POLL_CPMU_LINK);
16868 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16869 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16870 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16871 tg3_flag(tp, PCIX_MODE)) {
16872 tp->rx_offset = NET_SKB_PAD;
16873 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16874 tp->rx_copy_thresh = ~(u16)0;
16878 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16879 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16880 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16882 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16884 /* Increment the rx prod index on the rx std ring by at most
16885 * 8 for these chips to workaround hw errata.
16887 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16888 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16889 tg3_asic_rev(tp) == ASIC_REV_5755)
16890 tp->rx_std_max_post = 8;
16892 if (tg3_flag(tp, ASPM_WORKAROUND))
16893 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16894 PCIE_PWR_MGMT_L1_THRESH_MSK;
16899 #ifdef CONFIG_SPARC
16900 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16902 struct net_device *dev = tp->dev;
16903 struct pci_dev *pdev = tp->pdev;
16904 struct device_node *dp = pci_device_to_OF_node(pdev);
16905 const unsigned char *addr;
16908 addr = of_get_property(dp, "local-mac-address", &len);
16909 if (addr && len == ETH_ALEN) {
16910 memcpy(dev->dev_addr, addr, ETH_ALEN);
16916 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16918 struct net_device *dev = tp->dev;
16920 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16925 static int tg3_get_device_address(struct tg3 *tp)
16927 struct net_device *dev = tp->dev;
16928 u32 hi, lo, mac_offset;
16932 #ifdef CONFIG_SPARC
16933 if (!tg3_get_macaddr_sparc(tp))
16937 if (tg3_flag(tp, IS_SSB_CORE)) {
16938 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16939 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16944 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16945 tg3_flag(tp, 5780_CLASS)) {
16946 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16948 if (tg3_nvram_lock(tp))
16949 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16951 tg3_nvram_unlock(tp);
16952 } else if (tg3_flag(tp, 5717_PLUS)) {
16953 if (tp->pci_fn & 1)
16955 if (tp->pci_fn > 1)
16956 mac_offset += 0x18c;
16957 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16960 /* First try to get it from MAC address mailbox. */
16961 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16962 if ((hi >> 16) == 0x484b) {
16963 dev->dev_addr[0] = (hi >> 8) & 0xff;
16964 dev->dev_addr[1] = (hi >> 0) & 0xff;
16966 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16967 dev->dev_addr[2] = (lo >> 24) & 0xff;
16968 dev->dev_addr[3] = (lo >> 16) & 0xff;
16969 dev->dev_addr[4] = (lo >> 8) & 0xff;
16970 dev->dev_addr[5] = (lo >> 0) & 0xff;
16972 /* Some old bootcode may report a 0 MAC address in SRAM */
16973 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16976 /* Next, try NVRAM. */
16977 if (!tg3_flag(tp, NO_NVRAM) &&
16978 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16979 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16980 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16981 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16983 /* Finally just fetch it out of the MAC control regs. */
16985 hi = tr32(MAC_ADDR_0_HIGH);
16986 lo = tr32(MAC_ADDR_0_LOW);
16988 dev->dev_addr[5] = lo & 0xff;
16989 dev->dev_addr[4] = (lo >> 8) & 0xff;
16990 dev->dev_addr[3] = (lo >> 16) & 0xff;
16991 dev->dev_addr[2] = (lo >> 24) & 0xff;
16992 dev->dev_addr[1] = hi & 0xff;
16993 dev->dev_addr[0] = (hi >> 8) & 0xff;
16997 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16998 #ifdef CONFIG_SPARC
16999 if (!tg3_get_default_macaddr_sparc(tp))
17007 #define BOUNDARY_SINGLE_CACHELINE 1
17008 #define BOUNDARY_MULTI_CACHELINE 2
17010 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17012 int cacheline_size;
17016 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17018 cacheline_size = 1024;
17020 cacheline_size = (int) byte * 4;
17022 /* On 5703 and later chips, the boundary bits have no
17025 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17026 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17027 !tg3_flag(tp, PCI_EXPRESS))
17030 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17031 goal = BOUNDARY_MULTI_CACHELINE;
17033 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17034 goal = BOUNDARY_SINGLE_CACHELINE;
17040 if (tg3_flag(tp, 57765_PLUS)) {
17041 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17048 /* PCI controllers on most RISC systems tend to disconnect
17049 * when a device tries to burst across a cache-line boundary.
17050 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17052 * Unfortunately, for PCI-E there are only limited
17053 * write-side controls for this, and thus for reads
17054 * we will still get the disconnects. We'll also waste
17055 * these PCI cycles for both read and write for chips
17056 * other than 5700 and 5701 which do not implement the
17059 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17060 switch (cacheline_size) {
17065 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17066 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17067 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17069 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17070 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17075 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17076 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17080 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17081 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17084 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17085 switch (cacheline_size) {
17089 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17090 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17091 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17097 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17098 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17102 switch (cacheline_size) {
17104 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17105 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17106 DMA_RWCTRL_WRITE_BNDRY_16);
17111 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17112 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17113 DMA_RWCTRL_WRITE_BNDRY_32);
17118 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17119 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17120 DMA_RWCTRL_WRITE_BNDRY_64);
17125 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17126 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17127 DMA_RWCTRL_WRITE_BNDRY_128);
17132 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17133 DMA_RWCTRL_WRITE_BNDRY_256);
17136 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17137 DMA_RWCTRL_WRITE_BNDRY_512);
17141 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17142 DMA_RWCTRL_WRITE_BNDRY_1024);
17151 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17152 int size, bool to_device)
17154 struct tg3_internal_buffer_desc test_desc;
17155 u32 sram_dma_descs;
17158 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17160 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17161 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17162 tw32(RDMAC_STATUS, 0);
17163 tw32(WDMAC_STATUS, 0);
17165 tw32(BUFMGR_MODE, 0);
17166 tw32(FTQ_RESET, 0);
17168 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17169 test_desc.addr_lo = buf_dma & 0xffffffff;
17170 test_desc.nic_mbuf = 0x00002100;
17171 test_desc.len = size;
17174 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17175 * the *second* time the tg3 driver was getting loaded after an
17178 * Broadcom tells me:
17179 * ...the DMA engine is connected to the GRC block and a DMA
17180 * reset may affect the GRC block in some unpredictable way...
17181 * The behavior of resets to individual blocks has not been tested.
17183 * Broadcom noted the GRC reset will also reset all sub-components.
17186 test_desc.cqid_sqid = (13 << 8) | 2;
17188 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17191 test_desc.cqid_sqid = (16 << 8) | 7;
17193 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17196 test_desc.flags = 0x00000005;
17198 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17201 val = *(((u32 *)&test_desc) + i);
17202 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17203 sram_dma_descs + (i * sizeof(u32)));
17204 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17206 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17209 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17211 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17214 for (i = 0; i < 40; i++) {
17218 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17220 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17221 if ((val & 0xffff) == sram_dma_descs) {
17232 #define TEST_BUFFER_SIZE 0x2000
17234 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17235 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17239 static int tg3_test_dma(struct tg3 *tp)
17241 dma_addr_t buf_dma;
17242 u32 *buf, saved_dma_rwctrl;
17245 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17246 &buf_dma, GFP_KERNEL);
17252 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17253 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17255 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17257 if (tg3_flag(tp, 57765_PLUS))
17260 if (tg3_flag(tp, PCI_EXPRESS)) {
17261 /* DMA read watermark not used on PCIE */
17262 tp->dma_rwctrl |= 0x00180000;
17263 } else if (!tg3_flag(tp, PCIX_MODE)) {
17264 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17265 tg3_asic_rev(tp) == ASIC_REV_5750)
17266 tp->dma_rwctrl |= 0x003f0000;
17268 tp->dma_rwctrl |= 0x003f000f;
17270 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17271 tg3_asic_rev(tp) == ASIC_REV_5704) {
17272 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17273 u32 read_water = 0x7;
17275 /* If the 5704 is behind the EPB bridge, we can
17276 * do the less restrictive ONE_DMA workaround for
17277 * better performance.
17279 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17280 tg3_asic_rev(tp) == ASIC_REV_5704)
17281 tp->dma_rwctrl |= 0x8000;
17282 else if (ccval == 0x6 || ccval == 0x7)
17283 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17285 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17287 /* Set bit 23 to enable PCIX hw bug fix */
17289 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17290 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17292 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17293 /* 5780 always in PCIX mode */
17294 tp->dma_rwctrl |= 0x00144000;
17295 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17296 /* 5714 always in PCIX mode */
17297 tp->dma_rwctrl |= 0x00148000;
17299 tp->dma_rwctrl |= 0x001b000f;
17302 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17303 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17305 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17306 tg3_asic_rev(tp) == ASIC_REV_5704)
17307 tp->dma_rwctrl &= 0xfffffff0;
17309 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17310 tg3_asic_rev(tp) == ASIC_REV_5701) {
17311 /* Remove this if it causes problems for some boards. */
17312 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17314 /* On 5700/5701 chips, we need to set this bit.
17315 * Otherwise the chip will issue cacheline transactions
17316 * to streamable DMA memory with not all the byte
17317 * enables turned on. This is an error on several
17318 * RISC PCI controllers, in particular sparc64.
17320 * On 5703/5704 chips, this bit has been reassigned
17321 * a different meaning. In particular, it is used
17322 * on those chips to enable a PCI-X workaround.
17324 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17327 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17330 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17331 tg3_asic_rev(tp) != ASIC_REV_5701)
17334 /* It is best to perform DMA test with maximum write burst size
17335 * to expose the 5700/5701 write DMA bug.
17337 saved_dma_rwctrl = tp->dma_rwctrl;
17338 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17339 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17344 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17347 /* Send the buffer to the chip. */
17348 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17350 dev_err(&tp->pdev->dev,
17351 "%s: Buffer write failed. err = %d\n",
17356 /* Now read it back. */
17357 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17359 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17360 "err = %d\n", __func__, ret);
17365 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17369 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17370 DMA_RWCTRL_WRITE_BNDRY_16) {
17371 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17372 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17373 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17376 dev_err(&tp->pdev->dev,
17377 "%s: Buffer corrupted on read back! "
17378 "(%d != %d)\n", __func__, p[i], i);
17384 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17390 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17391 DMA_RWCTRL_WRITE_BNDRY_16) {
17392 /* DMA test passed without adjusting DMA boundary,
17393 * now look for chipsets that are known to expose the
17394 * DMA bug without failing the test.
17396 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17397 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17398 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17400 /* Safe to use the calculated DMA boundary. */
17401 tp->dma_rwctrl = saved_dma_rwctrl;
17404 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17408 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17413 static void tg3_init_bufmgr_config(struct tg3 *tp)
17415 if (tg3_flag(tp, 57765_PLUS)) {
17416 tp->bufmgr_config.mbuf_read_dma_low_water =
17417 DEFAULT_MB_RDMA_LOW_WATER_5705;
17418 tp->bufmgr_config.mbuf_mac_rx_low_water =
17419 DEFAULT_MB_MACRX_LOW_WATER_57765;
17420 tp->bufmgr_config.mbuf_high_water =
17421 DEFAULT_MB_HIGH_WATER_57765;
17423 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17424 DEFAULT_MB_RDMA_LOW_WATER_5705;
17425 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17426 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17427 tp->bufmgr_config.mbuf_high_water_jumbo =
17428 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17429 } else if (tg3_flag(tp, 5705_PLUS)) {
17430 tp->bufmgr_config.mbuf_read_dma_low_water =
17431 DEFAULT_MB_RDMA_LOW_WATER_5705;
17432 tp->bufmgr_config.mbuf_mac_rx_low_water =
17433 DEFAULT_MB_MACRX_LOW_WATER_5705;
17434 tp->bufmgr_config.mbuf_high_water =
17435 DEFAULT_MB_HIGH_WATER_5705;
17436 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17437 tp->bufmgr_config.mbuf_mac_rx_low_water =
17438 DEFAULT_MB_MACRX_LOW_WATER_5906;
17439 tp->bufmgr_config.mbuf_high_water =
17440 DEFAULT_MB_HIGH_WATER_5906;
17443 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17444 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17445 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17446 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17447 tp->bufmgr_config.mbuf_high_water_jumbo =
17448 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17450 tp->bufmgr_config.mbuf_read_dma_low_water =
17451 DEFAULT_MB_RDMA_LOW_WATER;
17452 tp->bufmgr_config.mbuf_mac_rx_low_water =
17453 DEFAULT_MB_MACRX_LOW_WATER;
17454 tp->bufmgr_config.mbuf_high_water =
17455 DEFAULT_MB_HIGH_WATER;
17457 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17458 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17459 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17460 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17461 tp->bufmgr_config.mbuf_high_water_jumbo =
17462 DEFAULT_MB_HIGH_WATER_JUMBO;
17465 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17466 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17469 static char *tg3_phy_string(struct tg3 *tp)
17471 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17472 case TG3_PHY_ID_BCM5400: return "5400";
17473 case TG3_PHY_ID_BCM5401: return "5401";
17474 case TG3_PHY_ID_BCM5411: return "5411";
17475 case TG3_PHY_ID_BCM5701: return "5701";
17476 case TG3_PHY_ID_BCM5703: return "5703";
17477 case TG3_PHY_ID_BCM5704: return "5704";
17478 case TG3_PHY_ID_BCM5705: return "5705";
17479 case TG3_PHY_ID_BCM5750: return "5750";
17480 case TG3_PHY_ID_BCM5752: return "5752";
17481 case TG3_PHY_ID_BCM5714: return "5714";
17482 case TG3_PHY_ID_BCM5780: return "5780";
17483 case TG3_PHY_ID_BCM5755: return "5755";
17484 case TG3_PHY_ID_BCM5787: return "5787";
17485 case TG3_PHY_ID_BCM5784: return "5784";
17486 case TG3_PHY_ID_BCM5756: return "5722/5756";
17487 case TG3_PHY_ID_BCM5906: return "5906";
17488 case TG3_PHY_ID_BCM5761: return "5761";
17489 case TG3_PHY_ID_BCM5718C: return "5718C";
17490 case TG3_PHY_ID_BCM5718S: return "5718S";
17491 case TG3_PHY_ID_BCM57765: return "57765";
17492 case TG3_PHY_ID_BCM5719C: return "5719C";
17493 case TG3_PHY_ID_BCM5720C: return "5720C";
17494 case TG3_PHY_ID_BCM5762: return "5762C";
17495 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17496 case 0: return "serdes";
17497 default: return "unknown";
17501 static char *tg3_bus_string(struct tg3 *tp, char *str)
17503 if (tg3_flag(tp, PCI_EXPRESS)) {
17504 strcpy(str, "PCI Express");
17506 } else if (tg3_flag(tp, PCIX_MODE)) {
17507 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17509 strcpy(str, "PCIX:");
17511 if ((clock_ctrl == 7) ||
17512 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17513 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17514 strcat(str, "133MHz");
17515 else if (clock_ctrl == 0)
17516 strcat(str, "33MHz");
17517 else if (clock_ctrl == 2)
17518 strcat(str, "50MHz");
17519 else if (clock_ctrl == 4)
17520 strcat(str, "66MHz");
17521 else if (clock_ctrl == 6)
17522 strcat(str, "100MHz");
17524 strcpy(str, "PCI:");
17525 if (tg3_flag(tp, PCI_HIGH_SPEED))
17526 strcat(str, "66MHz");
17528 strcat(str, "33MHz");
17530 if (tg3_flag(tp, PCI_32BIT))
17531 strcat(str, ":32-bit");
17533 strcat(str, ":64-bit");
17537 static void tg3_init_coal(struct tg3 *tp)
17539 struct ethtool_coalesce *ec = &tp->coal;
17541 memset(ec, 0, sizeof(*ec));
17542 ec->cmd = ETHTOOL_GCOALESCE;
17543 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17544 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17545 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17546 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17547 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17548 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17549 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17550 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17551 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17553 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17554 HOSTCC_MODE_CLRTICK_TXBD)) {
17555 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17556 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17557 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17558 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17561 if (tg3_flag(tp, 5705_PLUS)) {
17562 ec->rx_coalesce_usecs_irq = 0;
17563 ec->tx_coalesce_usecs_irq = 0;
17564 ec->stats_block_coalesce_usecs = 0;
17568 static int tg3_init_one(struct pci_dev *pdev,
17569 const struct pci_device_id *ent)
17571 struct net_device *dev;
17574 u32 sndmbx, rcvmbx, intmbx;
17576 u64 dma_mask, persist_dma_mask;
17577 netdev_features_t features = 0;
17579 printk_once(KERN_INFO "%s\n", version);
17581 err = pci_enable_device(pdev);
17583 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17587 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17589 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17590 goto err_out_disable_pdev;
17593 pci_set_master(pdev);
17595 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17598 goto err_out_free_res;
17601 SET_NETDEV_DEV(dev, &pdev->dev);
17603 tp = netdev_priv(dev);
17606 tp->rx_mode = TG3_DEF_RX_MODE;
17607 tp->tx_mode = TG3_DEF_TX_MODE;
17609 tp->pcierr_recovery = false;
17612 tp->msg_enable = tg3_debug;
17614 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17616 if (pdev_is_ssb_gige_core(pdev)) {
17617 tg3_flag_set(tp, IS_SSB_CORE);
17618 if (ssb_gige_must_flush_posted_writes(pdev))
17619 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17620 if (ssb_gige_one_dma_at_once(pdev))
17621 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17622 if (ssb_gige_have_roboswitch(pdev)) {
17623 tg3_flag_set(tp, USE_PHYLIB);
17624 tg3_flag_set(tp, ROBOSWITCH);
17626 if (ssb_gige_is_rgmii(pdev))
17627 tg3_flag_set(tp, RGMII_MODE);
17630 /* The word/byte swap controls here control register access byte
17631 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17634 tp->misc_host_ctrl =
17635 MISC_HOST_CTRL_MASK_PCI_INT |
17636 MISC_HOST_CTRL_WORD_SWAP |
17637 MISC_HOST_CTRL_INDIR_ACCESS |
17638 MISC_HOST_CTRL_PCISTATE_RW;
17640 /* The NONFRM (non-frame) byte/word swap controls take effect
17641 * on descriptor entries, anything which isn't packet data.
17643 * The StrongARM chips on the board (one for tx, one for rx)
17644 * are running in big-endian mode.
17646 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17647 GRC_MODE_WSWAP_NONFRM_DATA);
17648 #ifdef __BIG_ENDIAN
17649 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17651 spin_lock_init(&tp->lock);
17652 spin_lock_init(&tp->indirect_lock);
17653 INIT_WORK(&tp->reset_task, tg3_reset_task);
17655 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17657 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17659 goto err_out_free_dev;
17662 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17663 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17664 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17665 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17666 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17667 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17668 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17669 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17670 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17671 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17673 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17674 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17675 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17676 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17677 tg3_flag_set(tp, ENABLE_APE);
17678 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17679 if (!tp->aperegs) {
17680 dev_err(&pdev->dev,
17681 "Cannot map APE registers, aborting\n");
17683 goto err_out_iounmap;
17687 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17688 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17690 dev->ethtool_ops = &tg3_ethtool_ops;
17691 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17692 dev->netdev_ops = &tg3_netdev_ops;
17693 dev->irq = pdev->irq;
17695 err = tg3_get_invariants(tp, ent);
17697 dev_err(&pdev->dev,
17698 "Problem fetching invariants of chip, aborting\n");
17699 goto err_out_apeunmap;
17702 /* The EPB bridge inside 5714, 5715, and 5780 and any
17703 * device behind the EPB cannot support DMA addresses > 40-bit.
17704 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17705 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17706 * do DMA address check in tg3_start_xmit().
17708 if (tg3_flag(tp, IS_5788))
17709 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17710 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17711 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17712 #ifdef CONFIG_HIGHMEM
17713 dma_mask = DMA_BIT_MASK(64);
17716 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17718 /* Configure DMA attributes. */
17719 if (dma_mask > DMA_BIT_MASK(32)) {
17720 err = pci_set_dma_mask(pdev, dma_mask);
17722 features |= NETIF_F_HIGHDMA;
17723 err = pci_set_consistent_dma_mask(pdev,
17726 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17727 "DMA for consistent allocations\n");
17728 goto err_out_apeunmap;
17732 if (err || dma_mask == DMA_BIT_MASK(32)) {
17733 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17735 dev_err(&pdev->dev,
17736 "No usable DMA configuration, aborting\n");
17737 goto err_out_apeunmap;
17741 tg3_init_bufmgr_config(tp);
17743 /* 5700 B0 chips do not support checksumming correctly due
17744 * to hardware bugs.
17746 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17747 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17749 if (tg3_flag(tp, 5755_PLUS))
17750 features |= NETIF_F_IPV6_CSUM;
17753 /* TSO is on by default on chips that support hardware TSO.
17754 * Firmware TSO on older chips gives lower performance, so it
17755 * is off by default, but can be enabled using ethtool.
17757 if ((tg3_flag(tp, HW_TSO_1) ||
17758 tg3_flag(tp, HW_TSO_2) ||
17759 tg3_flag(tp, HW_TSO_3)) &&
17760 (features & NETIF_F_IP_CSUM))
17761 features |= NETIF_F_TSO;
17762 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17763 if (features & NETIF_F_IPV6_CSUM)
17764 features |= NETIF_F_TSO6;
17765 if (tg3_flag(tp, HW_TSO_3) ||
17766 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17767 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17768 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17769 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17770 tg3_asic_rev(tp) == ASIC_REV_57780)
17771 features |= NETIF_F_TSO_ECN;
17774 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17775 NETIF_F_HW_VLAN_CTAG_RX;
17776 dev->vlan_features |= features;
17779 * Add loopback capability only for a subset of devices that support
17780 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17781 * loopback for the remaining devices.
17783 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17784 !tg3_flag(tp, CPMU_PRESENT))
17785 /* Add the loopback capability */
17786 features |= NETIF_F_LOOPBACK;
17788 dev->hw_features |= features;
17789 dev->priv_flags |= IFF_UNICAST_FLT;
17791 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17792 !tg3_flag(tp, TSO_CAPABLE) &&
17793 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17794 tg3_flag_set(tp, MAX_RXPEND_64);
17795 tp->rx_pending = 63;
17798 err = tg3_get_device_address(tp);
17800 dev_err(&pdev->dev,
17801 "Could not obtain valid ethernet address, aborting\n");
17802 goto err_out_apeunmap;
17805 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17806 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17807 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17808 for (i = 0; i < tp->irq_max; i++) {
17809 struct tg3_napi *tnapi = &tp->napi[i];
17812 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17814 tnapi->int_mbox = intmbx;
17820 tnapi->consmbox = rcvmbx;
17821 tnapi->prodmbox = sndmbx;
17824 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17826 tnapi->coal_now = HOSTCC_MODE_NOW;
17828 if (!tg3_flag(tp, SUPPORT_MSIX))
17832 * If we support MSIX, we'll be using RSS. If we're using
17833 * RSS, the first vector only handles link interrupts and the
17834 * remaining vectors handle rx and tx interrupts. Reuse the
17835 * mailbox values for the next iteration. The values we setup
17836 * above are still useful for the single vectored mode.
17850 * Reset chip in case UNDI or EFI driver did not shutdown
17851 * DMA self test will enable WDMAC and we'll see (spurious)
17852 * pending DMA on the PCI bus at that point.
17854 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17855 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17856 tg3_full_lock(tp, 0);
17857 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17858 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17859 tg3_full_unlock(tp);
17862 err = tg3_test_dma(tp);
17864 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17865 goto err_out_apeunmap;
17870 pci_set_drvdata(pdev, dev);
17872 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17873 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17874 tg3_asic_rev(tp) == ASIC_REV_5762)
17875 tg3_flag_set(tp, PTP_CAPABLE);
17877 tg3_timer_init(tp);
17879 tg3_carrier_off(tp);
17881 err = register_netdev(dev);
17883 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17884 goto err_out_apeunmap;
17887 if (tg3_flag(tp, PTP_CAPABLE)) {
17889 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17891 if (IS_ERR(tp->ptp_clock))
17892 tp->ptp_clock = NULL;
17895 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17896 tp->board_part_number,
17897 tg3_chip_rev_id(tp),
17898 tg3_bus_string(tp, str),
17901 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17902 struct phy_device *phydev;
17903 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17905 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17906 phydev->drv->name, dev_name(&phydev->dev));
17910 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17911 ethtype = "10/100Base-TX";
17912 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17913 ethtype = "1000Base-SX";
17915 ethtype = "10/100/1000Base-T";
17917 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17918 "(WireSpeed[%d], EEE[%d])\n",
17919 tg3_phy_string(tp), ethtype,
17920 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17921 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17924 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17925 (dev->features & NETIF_F_RXCSUM) != 0,
17926 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17927 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17928 tg3_flag(tp, ENABLE_ASF) != 0,
17929 tg3_flag(tp, TSO_CAPABLE) != 0);
17930 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17932 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17933 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17935 pci_save_state(pdev);
17941 iounmap(tp->aperegs);
17942 tp->aperegs = NULL;
17955 pci_release_regions(pdev);
17957 err_out_disable_pdev:
17958 if (pci_is_enabled(pdev))
17959 pci_disable_device(pdev);
17963 static void tg3_remove_one(struct pci_dev *pdev)
17965 struct net_device *dev = pci_get_drvdata(pdev);
17968 struct tg3 *tp = netdev_priv(dev);
17972 release_firmware(tp->fw);
17974 tg3_reset_task_cancel(tp);
17976 if (tg3_flag(tp, USE_PHYLIB)) {
17981 unregister_netdev(dev);
17983 iounmap(tp->aperegs);
17984 tp->aperegs = NULL;
17991 pci_release_regions(pdev);
17992 pci_disable_device(pdev);
17996 #ifdef CONFIG_PM_SLEEP
17997 static int tg3_suspend(struct device *device)
17999 struct pci_dev *pdev = to_pci_dev(device);
18000 struct net_device *dev = pci_get_drvdata(pdev);
18001 struct tg3 *tp = netdev_priv(dev);
18006 if (!netif_running(dev))
18009 tg3_reset_task_cancel(tp);
18011 tg3_netif_stop(tp);
18013 tg3_timer_stop(tp);
18015 tg3_full_lock(tp, 1);
18016 tg3_disable_ints(tp);
18017 tg3_full_unlock(tp);
18019 netif_device_detach(dev);
18021 tg3_full_lock(tp, 0);
18022 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
18023 tg3_flag_clear(tp, INIT_COMPLETE);
18024 tg3_full_unlock(tp);
18026 err = tg3_power_down_prepare(tp);
18030 tg3_full_lock(tp, 0);
18032 tg3_flag_set(tp, INIT_COMPLETE);
18033 err2 = tg3_restart_hw(tp, true);
18037 tg3_timer_start(tp);
18039 netif_device_attach(dev);
18040 tg3_netif_start(tp);
18043 tg3_full_unlock(tp);
18054 static int tg3_resume(struct device *device)
18056 struct pci_dev *pdev = to_pci_dev(device);
18057 struct net_device *dev = pci_get_drvdata(pdev);
18058 struct tg3 *tp = netdev_priv(dev);
18063 if (!netif_running(dev))
18066 netif_device_attach(dev);
18068 tg3_full_lock(tp, 0);
18070 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18072 tg3_flag_set(tp, INIT_COMPLETE);
18073 err = tg3_restart_hw(tp,
18074 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18078 tg3_timer_start(tp);
18080 tg3_netif_start(tp);
18083 tg3_full_unlock(tp);
18092 #endif /* CONFIG_PM_SLEEP */
18094 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18096 static void tg3_shutdown(struct pci_dev *pdev)
18098 struct net_device *dev = pci_get_drvdata(pdev);
18099 struct tg3 *tp = netdev_priv(dev);
18102 netif_device_detach(dev);
18104 if (netif_running(dev))
18107 if (system_state == SYSTEM_POWER_OFF)
18108 tg3_power_down(tp);
18114 * tg3_io_error_detected - called when PCI error is detected
18115 * @pdev: Pointer to PCI device
18116 * @state: The current pci connection state
18118 * This function is called after a PCI bus error affecting
18119 * this device has been detected.
18121 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18122 pci_channel_state_t state)
18124 struct net_device *netdev = pci_get_drvdata(pdev);
18125 struct tg3 *tp = netdev_priv(netdev);
18126 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18128 netdev_info(netdev, "PCI I/O error detected\n");
18132 tp->pcierr_recovery = true;
18134 /* We probably don't have netdev yet */
18135 if (!netdev || !netif_running(netdev))
18140 tg3_netif_stop(tp);
18142 tg3_timer_stop(tp);
18144 /* Want to make sure that the reset task doesn't run */
18145 tg3_reset_task_cancel(tp);
18147 netif_device_detach(netdev);
18149 /* Clean up software state, even if MMIO is blocked */
18150 tg3_full_lock(tp, 0);
18151 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18152 tg3_full_unlock(tp);
18155 if (state == pci_channel_io_perm_failure) {
18157 tg3_napi_enable(tp);
18160 err = PCI_ERS_RESULT_DISCONNECT;
18162 pci_disable_device(pdev);
18171 * tg3_io_slot_reset - called after the pci bus has been reset.
18172 * @pdev: Pointer to PCI device
18174 * Restart the card from scratch, as if from a cold-boot.
18175 * At this point, the card has exprienced a hard reset,
18176 * followed by fixups by BIOS, and has its config space
18177 * set up identically to what it was at cold boot.
18179 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18181 struct net_device *netdev = pci_get_drvdata(pdev);
18182 struct tg3 *tp = netdev_priv(netdev);
18183 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18188 if (pci_enable_device(pdev)) {
18189 dev_err(&pdev->dev,
18190 "Cannot re-enable PCI device after reset.\n");
18194 pci_set_master(pdev);
18195 pci_restore_state(pdev);
18196 pci_save_state(pdev);
18198 if (!netdev || !netif_running(netdev)) {
18199 rc = PCI_ERS_RESULT_RECOVERED;
18203 err = tg3_power_up(tp);
18207 rc = PCI_ERS_RESULT_RECOVERED;
18210 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18211 tg3_napi_enable(tp);
18220 * tg3_io_resume - called when traffic can start flowing again.
18221 * @pdev: Pointer to PCI device
18223 * This callback is called when the error recovery driver tells
18224 * us that its OK to resume normal operation.
18226 static void tg3_io_resume(struct pci_dev *pdev)
18228 struct net_device *netdev = pci_get_drvdata(pdev);
18229 struct tg3 *tp = netdev_priv(netdev);
18234 if (!netif_running(netdev))
18237 tg3_full_lock(tp, 0);
18238 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18239 tg3_flag_set(tp, INIT_COMPLETE);
18240 err = tg3_restart_hw(tp, true);
18242 tg3_full_unlock(tp);
18243 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18247 netif_device_attach(netdev);
18249 tg3_timer_start(tp);
18251 tg3_netif_start(tp);
18253 tg3_full_unlock(tp);
18258 tp->pcierr_recovery = false;
18262 static const struct pci_error_handlers tg3_err_handler = {
18263 .error_detected = tg3_io_error_detected,
18264 .slot_reset = tg3_io_slot_reset,
18265 .resume = tg3_io_resume
18268 static struct pci_driver tg3_driver = {
18269 .name = DRV_MODULE_NAME,
18270 .id_table = tg3_pci_tbl,
18271 .probe = tg3_init_one,
18272 .remove = tg3_remove_one,
18273 .err_handler = &tg3_err_handler,
18274 .driver.pm = &tg3_pm_ops,
18275 .shutdown = tg3_shutdown,
18278 module_pci_driver(tg3_driver);