2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2013 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 134
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "Sep 16, 2013"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
212 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
214 #define FIRMWARE_TG3 "tigon/tg3.bin"
215 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
216 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
219 static char version[] =
220 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
222 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(DRV_MODULE_VERSION);
226 MODULE_FIRMWARE(FIRMWARE_TG3);
227 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
228 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
230 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231 module_param(tg3_debug, int, 0);
232 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
234 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
237 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
257 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
258 TG3_DRV_DATA_FLAG_5705_10_100},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
264 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
265 TG3_DRV_DATA_FLAG_5705_10_100},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
272 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
278 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
287 PCI_VENDOR_ID_LENOVO,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
289 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
312 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
313 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
320 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
330 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
332 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
345 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
346 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
347 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
348 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
349 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
351 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
352 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
356 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
358 static const struct {
359 const char string[ETH_GSTRING_LEN];
360 } ethtool_stats_keys[] = {
363 { "rx_ucast_packets" },
364 { "rx_mcast_packets" },
365 { "rx_bcast_packets" },
367 { "rx_align_errors" },
368 { "rx_xon_pause_rcvd" },
369 { "rx_xoff_pause_rcvd" },
370 { "rx_mac_ctrl_rcvd" },
371 { "rx_xoff_entered" },
372 { "rx_frame_too_long_errors" },
374 { "rx_undersize_packets" },
375 { "rx_in_length_errors" },
376 { "rx_out_length_errors" },
377 { "rx_64_or_less_octet_packets" },
378 { "rx_65_to_127_octet_packets" },
379 { "rx_128_to_255_octet_packets" },
380 { "rx_256_to_511_octet_packets" },
381 { "rx_512_to_1023_octet_packets" },
382 { "rx_1024_to_1522_octet_packets" },
383 { "rx_1523_to_2047_octet_packets" },
384 { "rx_2048_to_4095_octet_packets" },
385 { "rx_4096_to_8191_octet_packets" },
386 { "rx_8192_to_9022_octet_packets" },
393 { "tx_flow_control" },
395 { "tx_single_collisions" },
396 { "tx_mult_collisions" },
398 { "tx_excessive_collisions" },
399 { "tx_late_collisions" },
400 { "tx_collide_2times" },
401 { "tx_collide_3times" },
402 { "tx_collide_4times" },
403 { "tx_collide_5times" },
404 { "tx_collide_6times" },
405 { "tx_collide_7times" },
406 { "tx_collide_8times" },
407 { "tx_collide_9times" },
408 { "tx_collide_10times" },
409 { "tx_collide_11times" },
410 { "tx_collide_12times" },
411 { "tx_collide_13times" },
412 { "tx_collide_14times" },
413 { "tx_collide_15times" },
414 { "tx_ucast_packets" },
415 { "tx_mcast_packets" },
416 { "tx_bcast_packets" },
417 { "tx_carrier_sense_errors" },
421 { "dma_writeq_full" },
422 { "dma_write_prioq_full" },
426 { "rx_threshold_hit" },
428 { "dma_readq_full" },
429 { "dma_read_prioq_full" },
430 { "tx_comp_queue_full" },
432 { "ring_set_send_prod_index" },
433 { "ring_status_update" },
435 { "nic_avoided_irqs" },
436 { "nic_tx_threshold_hit" },
438 { "mbuf_lwm_thresh_hit" },
441 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
442 #define TG3_NVRAM_TEST 0
443 #define TG3_LINK_TEST 1
444 #define TG3_REGISTER_TEST 2
445 #define TG3_MEMORY_TEST 3
446 #define TG3_MAC_LOOPB_TEST 4
447 #define TG3_PHY_LOOPB_TEST 5
448 #define TG3_EXT_LOOPB_TEST 6
449 #define TG3_INTERRUPT_TEST 7
452 static const struct {
453 const char string[ETH_GSTRING_LEN];
454 } ethtool_test_keys[] = {
455 [TG3_NVRAM_TEST] = { "nvram test (online) " },
456 [TG3_LINK_TEST] = { "link test (online) " },
457 [TG3_REGISTER_TEST] = { "register test (offline)" },
458 [TG3_MEMORY_TEST] = { "memory test (offline)" },
459 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
460 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
461 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
462 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
465 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
468 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
470 writel(val, tp->regs + off);
473 static u32 tg3_read32(struct tg3 *tp, u32 off)
475 return readl(tp->regs + off);
478 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
480 writel(val, tp->aperegs + off);
483 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
485 return readl(tp->aperegs + off);
488 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
492 spin_lock_irqsave(&tp->indirect_lock, flags);
493 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
494 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
495 spin_unlock_irqrestore(&tp->indirect_lock, flags);
498 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
500 writel(val, tp->regs + off);
501 readl(tp->regs + off);
504 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
509 spin_lock_irqsave(&tp->indirect_lock, flags);
510 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
511 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
512 spin_unlock_irqrestore(&tp->indirect_lock, flags);
516 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
520 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
521 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
522 TG3_64BIT_REG_LOW, val);
525 if (off == TG3_RX_STD_PROD_IDX_REG) {
526 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
527 TG3_64BIT_REG_LOW, val);
531 spin_lock_irqsave(&tp->indirect_lock, flags);
532 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
533 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
534 spin_unlock_irqrestore(&tp->indirect_lock, flags);
536 /* In indirect mode when disabling interrupts, we also need
537 * to clear the interrupt bit in the GRC local ctrl register.
539 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
541 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
542 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
546 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
551 spin_lock_irqsave(&tp->indirect_lock, flags);
552 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
553 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 /* usec_wait specifies the wait time in usec when writing to certain registers
559 * where it is unsafe to read back the register without some delay.
560 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
561 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
563 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
565 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
566 /* Non-posted methods */
567 tp->write32(tp, off, val);
570 tg3_write32(tp, off, val);
575 /* Wait again after the read for the posted method to guarantee that
576 * the wait time is met.
582 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
584 tp->write32_mbox(tp, off, val);
585 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
586 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
587 !tg3_flag(tp, ICH_WORKAROUND)))
588 tp->read32_mbox(tp, off);
591 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
593 void __iomem *mbox = tp->regs + off;
595 if (tg3_flag(tp, TXD_MBOX_HWBUG))
597 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
598 tg3_flag(tp, FLUSH_POSTED_WRITES))
602 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
604 return readl(tp->regs + off + GRCMBOX_BASE);
607 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
609 writel(val, tp->regs + off + GRCMBOX_BASE);
612 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
613 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
614 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
615 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
616 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
618 #define tw32(reg, val) tp->write32(tp, reg, val)
619 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
620 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
621 #define tr32(reg) tp->read32(tp, reg)
623 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
627 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
628 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
631 spin_lock_irqsave(&tp->indirect_lock, flags);
632 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
633 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
634 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
636 /* Always leave this as zero. */
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
639 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
640 tw32_f(TG3PCI_MEM_WIN_DATA, val);
642 /* Always leave this as zero. */
643 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
645 spin_unlock_irqrestore(&tp->indirect_lock, flags);
648 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
652 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
653 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
658 spin_lock_irqsave(&tp->indirect_lock, flags);
659 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
660 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
661 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
663 /* Always leave this as zero. */
664 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
666 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
667 *val = tr32(TG3PCI_MEM_WIN_DATA);
669 /* Always leave this as zero. */
670 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
672 spin_unlock_irqrestore(&tp->indirect_lock, flags);
675 static void tg3_ape_lock_init(struct tg3 *tp)
680 if (tg3_asic_rev(tp) == ASIC_REV_5761)
681 regbase = TG3_APE_LOCK_GRANT;
683 regbase = TG3_APE_PER_LOCK_GRANT;
685 /* Make sure the driver hasn't any stale locks. */
686 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
688 case TG3_APE_LOCK_PHY0:
689 case TG3_APE_LOCK_PHY1:
690 case TG3_APE_LOCK_PHY2:
691 case TG3_APE_LOCK_PHY3:
692 bit = APE_LOCK_GRANT_DRIVER;
696 bit = APE_LOCK_GRANT_DRIVER;
698 bit = 1 << tp->pci_fn;
700 tg3_ape_write32(tp, regbase + 4 * i, bit);
705 static int tg3_ape_lock(struct tg3 *tp, int locknum)
709 u32 status, req, gnt, bit;
711 if (!tg3_flag(tp, ENABLE_APE))
715 case TG3_APE_LOCK_GPIO:
716 if (tg3_asic_rev(tp) == ASIC_REV_5761)
718 case TG3_APE_LOCK_GRC:
719 case TG3_APE_LOCK_MEM:
721 bit = APE_LOCK_REQ_DRIVER;
723 bit = 1 << tp->pci_fn;
725 case TG3_APE_LOCK_PHY0:
726 case TG3_APE_LOCK_PHY1:
727 case TG3_APE_LOCK_PHY2:
728 case TG3_APE_LOCK_PHY3:
729 bit = APE_LOCK_REQ_DRIVER;
735 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
736 req = TG3_APE_LOCK_REQ;
737 gnt = TG3_APE_LOCK_GRANT;
739 req = TG3_APE_PER_LOCK_REQ;
740 gnt = TG3_APE_PER_LOCK_GRANT;
745 tg3_ape_write32(tp, req + off, bit);
747 /* Wait for up to 1 millisecond to acquire lock. */
748 for (i = 0; i < 100; i++) {
749 status = tg3_ape_read32(tp, gnt + off);
752 if (pci_channel_offline(tp->pdev))
759 /* Revoke the lock request. */
760 tg3_ape_write32(tp, gnt + off, bit);
767 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
771 if (!tg3_flag(tp, ENABLE_APE))
775 case TG3_APE_LOCK_GPIO:
776 if (tg3_asic_rev(tp) == ASIC_REV_5761)
778 case TG3_APE_LOCK_GRC:
779 case TG3_APE_LOCK_MEM:
781 bit = APE_LOCK_GRANT_DRIVER;
783 bit = 1 << tp->pci_fn;
785 case TG3_APE_LOCK_PHY0:
786 case TG3_APE_LOCK_PHY1:
787 case TG3_APE_LOCK_PHY2:
788 case TG3_APE_LOCK_PHY3:
789 bit = APE_LOCK_GRANT_DRIVER;
795 if (tg3_asic_rev(tp) == ASIC_REV_5761)
796 gnt = TG3_APE_LOCK_GRANT;
798 gnt = TG3_APE_PER_LOCK_GRANT;
800 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
803 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
808 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
811 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
812 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
815 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
818 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
821 return timeout_us ? 0 : -EBUSY;
824 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
828 for (i = 0; i < timeout_us / 10; i++) {
829 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
831 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
837 return i == timeout_us / 10;
840 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
844 u32 i, bufoff, msgoff, maxlen, apedata;
846 if (!tg3_flag(tp, APE_HAS_NCSI))
849 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
850 if (apedata != APE_SEG_SIG_MAGIC)
853 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
854 if (!(apedata & APE_FW_STATUS_READY))
857 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
859 msgoff = bufoff + 2 * sizeof(u32);
860 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
865 /* Cap xfer sizes to scratchpad limits. */
866 length = (len > maxlen) ? maxlen : len;
869 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
870 if (!(apedata & APE_FW_STATUS_READY))
873 /* Wait for up to 1 msec for APE to service previous event. */
874 err = tg3_ape_event_lock(tp, 1000);
878 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
879 APE_EVENT_STATUS_SCRTCHPD_READ |
880 APE_EVENT_STATUS_EVENT_PENDING;
881 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
883 tg3_ape_write32(tp, bufoff, base_off);
884 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
886 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
887 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
891 if (tg3_ape_wait_for_event(tp, 30000))
894 for (i = 0; length; i += 4, length -= 4) {
895 u32 val = tg3_ape_read32(tp, msgoff + i);
896 memcpy(data, &val, sizeof(u32));
904 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
909 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
910 if (apedata != APE_SEG_SIG_MAGIC)
913 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
914 if (!(apedata & APE_FW_STATUS_READY))
917 /* Wait for up to 1 millisecond for APE to service previous event. */
918 err = tg3_ape_event_lock(tp, 1000);
922 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
923 event | APE_EVENT_STATUS_EVENT_PENDING);
925 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
926 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
931 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
936 if (!tg3_flag(tp, ENABLE_APE))
940 case RESET_KIND_INIT:
941 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
942 APE_HOST_SEG_SIG_MAGIC);
943 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
944 APE_HOST_SEG_LEN_MAGIC);
945 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
946 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
947 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
948 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
949 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
950 APE_HOST_BEHAV_NO_PHYLOCK);
951 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
952 TG3_APE_HOST_DRVR_STATE_START);
954 event = APE_EVENT_STATUS_STATE_START;
956 case RESET_KIND_SHUTDOWN:
957 /* With the interface we are currently using,
958 * APE does not track driver state. Wiping
959 * out the HOST SEGMENT SIGNATURE forces
960 * the APE to assume OS absent status.
962 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
964 if (device_may_wakeup(&tp->pdev->dev) &&
965 tg3_flag(tp, WOL_ENABLE)) {
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
967 TG3_APE_HOST_WOL_SPEED_AUTO);
968 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
970 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
974 event = APE_EVENT_STATUS_STATE_UNLOAD;
980 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
982 tg3_ape_send_event(tp, event);
985 static void tg3_disable_ints(struct tg3 *tp)
989 tw32(TG3PCI_MISC_HOST_CTRL,
990 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
991 for (i = 0; i < tp->irq_max; i++)
992 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
995 static void tg3_enable_ints(struct tg3 *tp)
1002 tw32(TG3PCI_MISC_HOST_CTRL,
1003 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1005 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1006 for (i = 0; i < tp->irq_cnt; i++) {
1007 struct tg3_napi *tnapi = &tp->napi[i];
1009 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1010 if (tg3_flag(tp, 1SHOT_MSI))
1011 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 tp->coal_now |= tnapi->coal_now;
1016 /* Force an initial interrupt */
1017 if (!tg3_flag(tp, TAGGED_STATUS) &&
1018 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1019 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1021 tw32(HOSTCC_MODE, tp->coal_now);
1023 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1026 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1028 struct tg3 *tp = tnapi->tp;
1029 struct tg3_hw_status *sblk = tnapi->hw_status;
1030 unsigned int work_exists = 0;
1032 /* check for phy events */
1033 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1034 if (sblk->status & SD_STATUS_LINK_CHG)
1038 /* check for TX work to do */
1039 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1042 /* check for RX work to do */
1043 if (tnapi->rx_rcb_prod_idx &&
1044 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1051 * similar to tg3_enable_ints, but it accurately determines whether there
1052 * is new work pending and can return without flushing the PIO write
1053 * which reenables interrupts
1055 static void tg3_int_reenable(struct tg3_napi *tnapi)
1057 struct tg3 *tp = tnapi->tp;
1059 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1062 /* When doing tagged status, this work check is unnecessary.
1063 * The last_tag we write above tells the chip which piece of
1064 * work we've completed.
1066 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1067 tw32(HOSTCC_MODE, tp->coalesce_mode |
1068 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1071 static void tg3_switch_clocks(struct tg3 *tp)
1074 u32 orig_clock_ctrl;
1076 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1079 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1081 orig_clock_ctrl = clock_ctrl;
1082 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1083 CLOCK_CTRL_CLKRUN_OENABLE |
1085 tp->pci_clock_ctrl = clock_ctrl;
1087 if (tg3_flag(tp, 5705_PLUS)) {
1088 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1089 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1090 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1092 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1093 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1095 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1097 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1101 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1104 #define PHY_BUSY_LOOPS 5000
1106 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1113 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1115 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1119 tg3_ape_lock(tp, tp->phy_ape_lock);
1123 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1124 MI_COM_PHY_ADDR_MASK);
1125 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1126 MI_COM_REG_ADDR_MASK);
1127 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1129 tw32_f(MAC_MI_COM, frame_val);
1131 loops = PHY_BUSY_LOOPS;
1132 while (loops != 0) {
1134 frame_val = tr32(MAC_MI_COM);
1136 if ((frame_val & MI_COM_BUSY) == 0) {
1138 frame_val = tr32(MAC_MI_COM);
1146 *val = frame_val & MI_COM_DATA_MASK;
1150 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1151 tw32_f(MAC_MI_MODE, tp->mi_mode);
1155 tg3_ape_unlock(tp, tp->phy_ape_lock);
1160 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1162 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1165 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1172 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1173 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1176 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1178 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1182 tg3_ape_lock(tp, tp->phy_ape_lock);
1184 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1185 MI_COM_PHY_ADDR_MASK);
1186 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1187 MI_COM_REG_ADDR_MASK);
1188 frame_val |= (val & MI_COM_DATA_MASK);
1189 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1191 tw32_f(MAC_MI_COM, frame_val);
1193 loops = PHY_BUSY_LOOPS;
1194 while (loops != 0) {
1196 frame_val = tr32(MAC_MI_COM);
1197 if ((frame_val & MI_COM_BUSY) == 0) {
1199 frame_val = tr32(MAC_MI_COM);
1209 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1210 tw32_f(MAC_MI_MODE, tp->mi_mode);
1214 tg3_ape_unlock(tp, tp->phy_ape_lock);
1219 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1221 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1224 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1228 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1232 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1236 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1237 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1241 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1247 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1251 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1255 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1259 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1260 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1264 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1270 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1274 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1276 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1281 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1287 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1292 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1296 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1297 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1298 MII_TG3_AUXCTL_SHDWSEL_MISC);
1300 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1305 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1307 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1308 set |= MII_TG3_AUXCTL_MISC_WREN;
1310 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1313 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1318 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1324 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1326 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1328 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1329 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1334 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1336 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1337 reg | val | MII_TG3_MISC_SHDW_WREN);
1340 static int tg3_bmcr_reset(struct tg3 *tp)
1345 /* OK, reset it, and poll the BMCR_RESET bit until it
1346 * clears or we time out.
1348 phy_control = BMCR_RESET;
1349 err = tg3_writephy(tp, MII_BMCR, phy_control);
1355 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1359 if ((phy_control & BMCR_RESET) == 0) {
1371 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1373 struct tg3 *tp = bp->priv;
1376 spin_lock_bh(&tp->lock);
1378 if (__tg3_readphy(tp, mii_id, reg, &val))
1381 spin_unlock_bh(&tp->lock);
1386 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1388 struct tg3 *tp = bp->priv;
1391 spin_lock_bh(&tp->lock);
1393 if (__tg3_writephy(tp, mii_id, reg, val))
1396 spin_unlock_bh(&tp->lock);
1401 static int tg3_mdio_reset(struct mii_bus *bp)
1406 static void tg3_mdio_config_5785(struct tg3 *tp)
1409 struct phy_device *phydev;
1411 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1412 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1413 case PHY_ID_BCM50610:
1414 case PHY_ID_BCM50610M:
1415 val = MAC_PHYCFG2_50610_LED_MODES;
1417 case PHY_ID_BCMAC131:
1418 val = MAC_PHYCFG2_AC131_LED_MODES;
1420 case PHY_ID_RTL8211C:
1421 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1423 case PHY_ID_RTL8201E:
1424 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1430 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1431 tw32(MAC_PHYCFG2, val);
1433 val = tr32(MAC_PHYCFG1);
1434 val &= ~(MAC_PHYCFG1_RGMII_INT |
1435 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1436 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1437 tw32(MAC_PHYCFG1, val);
1442 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1443 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1444 MAC_PHYCFG2_FMODE_MASK_MASK |
1445 MAC_PHYCFG2_GMODE_MASK_MASK |
1446 MAC_PHYCFG2_ACT_MASK_MASK |
1447 MAC_PHYCFG2_QUAL_MASK_MASK |
1448 MAC_PHYCFG2_INBAND_ENABLE;
1450 tw32(MAC_PHYCFG2, val);
1452 val = tr32(MAC_PHYCFG1);
1453 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1454 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1455 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1456 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1457 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1458 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1459 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1461 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1462 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1463 tw32(MAC_PHYCFG1, val);
1465 val = tr32(MAC_EXT_RGMII_MODE);
1466 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1467 MAC_RGMII_MODE_RX_QUALITY |
1468 MAC_RGMII_MODE_RX_ACTIVITY |
1469 MAC_RGMII_MODE_RX_ENG_DET |
1470 MAC_RGMII_MODE_TX_ENABLE |
1471 MAC_RGMII_MODE_TX_LOWPWR |
1472 MAC_RGMII_MODE_TX_RESET);
1473 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1474 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1475 val |= MAC_RGMII_MODE_RX_INT_B |
1476 MAC_RGMII_MODE_RX_QUALITY |
1477 MAC_RGMII_MODE_RX_ACTIVITY |
1478 MAC_RGMII_MODE_RX_ENG_DET;
1479 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1480 val |= MAC_RGMII_MODE_TX_ENABLE |
1481 MAC_RGMII_MODE_TX_LOWPWR |
1482 MAC_RGMII_MODE_TX_RESET;
1484 tw32(MAC_EXT_RGMII_MODE, val);
1487 static void tg3_mdio_start(struct tg3 *tp)
1489 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1490 tw32_f(MAC_MI_MODE, tp->mi_mode);
1493 if (tg3_flag(tp, MDIOBUS_INITED) &&
1494 tg3_asic_rev(tp) == ASIC_REV_5785)
1495 tg3_mdio_config_5785(tp);
1498 static int tg3_mdio_init(struct tg3 *tp)
1502 struct phy_device *phydev;
1504 if (tg3_flag(tp, 5717_PLUS)) {
1507 tp->phy_addr = tp->pci_fn + 1;
1509 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1510 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1512 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1513 TG3_CPMU_PHY_STRAP_IS_SERDES;
1516 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1519 addr = ssb_gige_get_phyaddr(tp->pdev);
1522 tp->phy_addr = addr;
1524 tp->phy_addr = TG3_PHY_MII_ADDR;
1528 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1531 tp->mdio_bus = mdiobus_alloc();
1532 if (tp->mdio_bus == NULL)
1535 tp->mdio_bus->name = "tg3 mdio bus";
1536 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1537 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1538 tp->mdio_bus->priv = tp;
1539 tp->mdio_bus->parent = &tp->pdev->dev;
1540 tp->mdio_bus->read = &tg3_mdio_read;
1541 tp->mdio_bus->write = &tg3_mdio_write;
1542 tp->mdio_bus->reset = &tg3_mdio_reset;
1543 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1544 tp->mdio_bus->irq = &tp->mdio_irq[0];
1546 for (i = 0; i < PHY_MAX_ADDR; i++)
1547 tp->mdio_bus->irq[i] = PHY_POLL;
1549 /* The bus registration will look for all the PHYs on the mdio bus.
1550 * Unfortunately, it does not ensure the PHY is powered up before
1551 * accessing the PHY ID registers. A chip reset is the
1552 * quickest way to bring the device back to an operational state..
1554 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1557 i = mdiobus_register(tp->mdio_bus);
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1560 mdiobus_free(tp->mdio_bus);
1564 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1566 if (!phydev || !phydev->drv) {
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1568 mdiobus_unregister(tp->mdio_bus);
1569 mdiobus_free(tp->mdio_bus);
1573 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1574 case PHY_ID_BCM57780:
1575 phydev->interface = PHY_INTERFACE_MODE_GMII;
1576 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1578 case PHY_ID_BCM50610:
1579 case PHY_ID_BCM50610M:
1580 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1581 PHY_BRCM_RX_REFCLK_UNUSED |
1582 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1583 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1584 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1585 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1586 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1587 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1588 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1589 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1591 case PHY_ID_RTL8211C:
1592 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1594 case PHY_ID_RTL8201E:
1595 case PHY_ID_BCMAC131:
1596 phydev->interface = PHY_INTERFACE_MODE_MII;
1597 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1598 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1602 tg3_flag_set(tp, MDIOBUS_INITED);
1604 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1605 tg3_mdio_config_5785(tp);
1610 static void tg3_mdio_fini(struct tg3 *tp)
1612 if (tg3_flag(tp, MDIOBUS_INITED)) {
1613 tg3_flag_clear(tp, MDIOBUS_INITED);
1614 mdiobus_unregister(tp->mdio_bus);
1615 mdiobus_free(tp->mdio_bus);
1619 /* tp->lock is held. */
1620 static inline void tg3_generate_fw_event(struct tg3 *tp)
1624 val = tr32(GRC_RX_CPU_EVENT);
1625 val |= GRC_RX_CPU_DRIVER_EVENT;
1626 tw32_f(GRC_RX_CPU_EVENT, val);
1628 tp->last_event_jiffies = jiffies;
1631 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1633 /* tp->lock is held. */
1634 static void tg3_wait_for_event_ack(struct tg3 *tp)
1637 unsigned int delay_cnt;
1640 /* If enough time has passed, no wait is necessary. */
1641 time_remain = (long)(tp->last_event_jiffies + 1 +
1642 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1644 if (time_remain < 0)
1647 /* Check if we can shorten the wait time. */
1648 delay_cnt = jiffies_to_usecs(time_remain);
1649 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1650 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1651 delay_cnt = (delay_cnt >> 3) + 1;
1653 for (i = 0; i < delay_cnt; i++) {
1654 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1656 if (pci_channel_offline(tp->pdev))
1663 /* tp->lock is held. */
1664 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1669 if (!tg3_readphy(tp, MII_BMCR, ®))
1671 if (!tg3_readphy(tp, MII_BMSR, ®))
1672 val |= (reg & 0xffff);
1676 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1678 if (!tg3_readphy(tp, MII_LPA, ®))
1679 val |= (reg & 0xffff);
1683 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1684 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1686 if (!tg3_readphy(tp, MII_STAT1000, ®))
1687 val |= (reg & 0xffff);
1691 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1698 /* tp->lock is held. */
1699 static void tg3_ump_link_report(struct tg3 *tp)
1703 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1706 tg3_phy_gather_ump_data(tp, data);
1708 tg3_wait_for_event_ack(tp);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1713 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1714 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1715 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1717 tg3_generate_fw_event(tp);
1720 /* tp->lock is held. */
1721 static void tg3_stop_fw(struct tg3 *tp)
1723 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1724 /* Wait for RX cpu to ACK the previous event. */
1725 tg3_wait_for_event_ack(tp);
1727 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1729 tg3_generate_fw_event(tp);
1731 /* Wait for RX cpu to ACK this event. */
1732 tg3_wait_for_event_ack(tp);
1736 /* tp->lock is held. */
1737 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1739 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1740 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1742 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1744 case RESET_KIND_INIT:
1745 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1749 case RESET_KIND_SHUTDOWN:
1750 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1754 case RESET_KIND_SUSPEND:
1755 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1765 /* tp->lock is held. */
1766 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1768 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1770 case RESET_KIND_INIT:
1771 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1772 DRV_STATE_START_DONE);
1775 case RESET_KIND_SHUTDOWN:
1776 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1777 DRV_STATE_UNLOAD_DONE);
1786 /* tp->lock is held. */
1787 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1789 if (tg3_flag(tp, ENABLE_ASF)) {
1791 case RESET_KIND_INIT:
1792 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1796 case RESET_KIND_SHUTDOWN:
1797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1801 case RESET_KIND_SUSPEND:
1802 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1812 static int tg3_poll_fw(struct tg3 *tp)
1817 if (tg3_flag(tp, NO_FWARE_REPORTED))
1820 if (tg3_flag(tp, IS_SSB_CORE)) {
1821 /* We don't use firmware. */
1825 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1826 /* Wait up to 20ms for init done. */
1827 for (i = 0; i < 200; i++) {
1828 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1830 if (pci_channel_offline(tp->pdev))
1838 /* Wait for firmware initialization to complete. */
1839 for (i = 0; i < 100000; i++) {
1840 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1841 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1843 if (pci_channel_offline(tp->pdev)) {
1844 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1845 tg3_flag_set(tp, NO_FWARE_REPORTED);
1846 netdev_info(tp->dev, "No firmware running\n");
1855 /* Chip might not be fitted with firmware. Some Sun onboard
1856 * parts are configured like that. So don't signal the timeout
1857 * of the above loop as an error, but do report the lack of
1858 * running firmware once.
1860 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1861 tg3_flag_set(tp, NO_FWARE_REPORTED);
1863 netdev_info(tp->dev, "No firmware running\n");
1866 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1867 /* The 57765 A0 needs a little more
1868 * time to do some important work.
1876 static void tg3_link_report(struct tg3 *tp)
1878 if (!netif_carrier_ok(tp->dev)) {
1879 netif_info(tp, link, tp->dev, "Link is down\n");
1880 tg3_ump_link_report(tp);
1881 } else if (netif_msg_link(tp)) {
1882 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1883 (tp->link_config.active_speed == SPEED_1000 ?
1885 (tp->link_config.active_speed == SPEED_100 ?
1887 (tp->link_config.active_duplex == DUPLEX_FULL ?
1890 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1891 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1893 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1896 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1897 netdev_info(tp->dev, "EEE is %s\n",
1898 tp->setlpicnt ? "enabled" : "disabled");
1900 tg3_ump_link_report(tp);
1903 tp->link_up = netif_carrier_ok(tp->dev);
1906 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1910 if (adv & ADVERTISE_PAUSE_CAP) {
1911 flowctrl |= FLOW_CTRL_RX;
1912 if (!(adv & ADVERTISE_PAUSE_ASYM))
1913 flowctrl |= FLOW_CTRL_TX;
1914 } else if (adv & ADVERTISE_PAUSE_ASYM)
1915 flowctrl |= FLOW_CTRL_TX;
1920 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1924 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1925 miireg = ADVERTISE_1000XPAUSE;
1926 else if (flow_ctrl & FLOW_CTRL_TX)
1927 miireg = ADVERTISE_1000XPSE_ASYM;
1928 else if (flow_ctrl & FLOW_CTRL_RX)
1929 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1936 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1940 if (adv & ADVERTISE_1000XPAUSE) {
1941 flowctrl |= FLOW_CTRL_RX;
1942 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1943 flowctrl |= FLOW_CTRL_TX;
1944 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1945 flowctrl |= FLOW_CTRL_TX;
1950 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1954 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1955 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1956 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1957 if (lcladv & ADVERTISE_1000XPAUSE)
1959 if (rmtadv & ADVERTISE_1000XPAUSE)
1966 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1970 u32 old_rx_mode = tp->rx_mode;
1971 u32 old_tx_mode = tp->tx_mode;
1973 if (tg3_flag(tp, USE_PHYLIB))
1974 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1976 autoneg = tp->link_config.autoneg;
1978 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1979 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1980 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1982 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1984 flowctrl = tp->link_config.flowctrl;
1986 tp->link_config.active_flowctrl = flowctrl;
1988 if (flowctrl & FLOW_CTRL_RX)
1989 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1991 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1993 if (old_rx_mode != tp->rx_mode)
1994 tw32_f(MAC_RX_MODE, tp->rx_mode);
1996 if (flowctrl & FLOW_CTRL_TX)
1997 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1999 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
2001 if (old_tx_mode != tp->tx_mode)
2002 tw32_f(MAC_TX_MODE, tp->tx_mode);
2005 static void tg3_adjust_link(struct net_device *dev)
2007 u8 oldflowctrl, linkmesg = 0;
2008 u32 mac_mode, lcl_adv, rmt_adv;
2009 struct tg3 *tp = netdev_priv(dev);
2010 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2012 spin_lock_bh(&tp->lock);
2014 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2015 MAC_MODE_HALF_DUPLEX);
2017 oldflowctrl = tp->link_config.active_flowctrl;
2023 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2024 mac_mode |= MAC_MODE_PORT_MODE_MII;
2025 else if (phydev->speed == SPEED_1000 ||
2026 tg3_asic_rev(tp) != ASIC_REV_5785)
2027 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2029 mac_mode |= MAC_MODE_PORT_MODE_MII;
2031 if (phydev->duplex == DUPLEX_HALF)
2032 mac_mode |= MAC_MODE_HALF_DUPLEX;
2034 lcl_adv = mii_advertise_flowctrl(
2035 tp->link_config.flowctrl);
2038 rmt_adv = LPA_PAUSE_CAP;
2039 if (phydev->asym_pause)
2040 rmt_adv |= LPA_PAUSE_ASYM;
2043 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2045 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2047 if (mac_mode != tp->mac_mode) {
2048 tp->mac_mode = mac_mode;
2049 tw32_f(MAC_MODE, tp->mac_mode);
2053 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2054 if (phydev->speed == SPEED_10)
2056 MAC_MI_STAT_10MBPS_MODE |
2057 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2062 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2063 tw32(MAC_TX_LENGTHS,
2064 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2065 (6 << TX_LENGTHS_IPG_SHIFT) |
2066 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2068 tw32(MAC_TX_LENGTHS,
2069 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2070 (6 << TX_LENGTHS_IPG_SHIFT) |
2071 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2073 if (phydev->link != tp->old_link ||
2074 phydev->speed != tp->link_config.active_speed ||
2075 phydev->duplex != tp->link_config.active_duplex ||
2076 oldflowctrl != tp->link_config.active_flowctrl)
2079 tp->old_link = phydev->link;
2080 tp->link_config.active_speed = phydev->speed;
2081 tp->link_config.active_duplex = phydev->duplex;
2083 spin_unlock_bh(&tp->lock);
2086 tg3_link_report(tp);
2089 static int tg3_phy_init(struct tg3 *tp)
2091 struct phy_device *phydev;
2093 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2096 /* Bring the PHY back to a known state. */
2099 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2101 /* Attach the MAC to the PHY. */
2102 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2103 tg3_adjust_link, phydev->interface);
2104 if (IS_ERR(phydev)) {
2105 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2106 return PTR_ERR(phydev);
2109 /* Mask with MAC supported features. */
2110 switch (phydev->interface) {
2111 case PHY_INTERFACE_MODE_GMII:
2112 case PHY_INTERFACE_MODE_RGMII:
2113 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2114 phydev->supported &= (PHY_GBIT_FEATURES |
2116 SUPPORTED_Asym_Pause);
2120 case PHY_INTERFACE_MODE_MII:
2121 phydev->supported &= (PHY_BASIC_FEATURES |
2123 SUPPORTED_Asym_Pause);
2126 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2130 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2132 phydev->advertising = phydev->supported;
2137 static void tg3_phy_start(struct tg3 *tp)
2139 struct phy_device *phydev;
2141 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2144 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2146 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2147 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2148 phydev->speed = tp->link_config.speed;
2149 phydev->duplex = tp->link_config.duplex;
2150 phydev->autoneg = tp->link_config.autoneg;
2151 phydev->advertising = tp->link_config.advertising;
2156 phy_start_aneg(phydev);
2159 static void tg3_phy_stop(struct tg3 *tp)
2161 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2164 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2167 static void tg3_phy_fini(struct tg3 *tp)
2169 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2170 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2171 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2175 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2180 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2183 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2184 /* Cannot do read-modify-write on 5401 */
2185 err = tg3_phy_auxctl_write(tp,
2186 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2187 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2192 err = tg3_phy_auxctl_read(tp,
2193 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2197 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2198 err = tg3_phy_auxctl_write(tp,
2199 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2205 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2209 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2212 tg3_writephy(tp, MII_TG3_FET_TEST,
2213 phytest | MII_TG3_FET_SHADOW_EN);
2214 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2216 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2218 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2219 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2221 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2225 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2229 if (!tg3_flag(tp, 5705_PLUS) ||
2230 (tg3_flag(tp, 5717_PLUS) &&
2231 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2234 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2235 tg3_phy_fet_toggle_apd(tp, enable);
2239 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2240 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2241 MII_TG3_MISC_SHDW_SCR5_SDTL |
2242 MII_TG3_MISC_SHDW_SCR5_C125OE;
2243 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2244 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2246 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2249 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2251 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2253 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2256 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2260 if (!tg3_flag(tp, 5705_PLUS) ||
2261 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2264 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2267 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2268 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2270 tg3_writephy(tp, MII_TG3_FET_TEST,
2271 ephy | MII_TG3_FET_SHADOW_EN);
2272 if (!tg3_readphy(tp, reg, &phy)) {
2274 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2276 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2277 tg3_writephy(tp, reg, phy);
2279 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2284 ret = tg3_phy_auxctl_read(tp,
2285 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2288 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2290 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2291 tg3_phy_auxctl_write(tp,
2292 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2297 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2302 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2305 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2307 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2308 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2311 static void tg3_phy_apply_otp(struct tg3 *tp)
2320 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2323 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2324 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2325 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2327 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2328 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2329 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2331 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2332 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2333 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2335 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2338 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2339 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2341 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2342 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2343 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2345 tg3_phy_toggle_auxctl_smdsp(tp, false);
2348 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2351 struct ethtool_eee *dest = &tp->eee;
2353 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2359 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2362 /* Pull eee_active */
2363 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2364 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2365 dest->eee_active = 1;
2367 dest->eee_active = 0;
2369 /* Pull lp advertised settings */
2370 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2372 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2374 /* Pull advertised and eee_enabled settings */
2375 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2377 dest->eee_enabled = !!val;
2378 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2380 /* Pull tx_lpi_enabled */
2381 val = tr32(TG3_CPMU_EEE_MODE);
2382 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2384 /* Pull lpi timer value */
2385 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2388 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2392 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2397 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2399 tp->link_config.active_duplex == DUPLEX_FULL &&
2400 (tp->link_config.active_speed == SPEED_100 ||
2401 tp->link_config.active_speed == SPEED_1000)) {
2404 if (tp->link_config.active_speed == SPEED_1000)
2405 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2407 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2409 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2411 tg3_eee_pull_config(tp, NULL);
2412 if (tp->eee.eee_active)
2416 if (!tp->setlpicnt) {
2417 if (current_link_up &&
2418 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2419 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2420 tg3_phy_toggle_auxctl_smdsp(tp, false);
2423 val = tr32(TG3_CPMU_EEE_MODE);
2424 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2428 static void tg3_phy_eee_enable(struct tg3 *tp)
2432 if (tp->link_config.active_speed == SPEED_1000 &&
2433 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2434 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2435 tg3_flag(tp, 57765_CLASS)) &&
2436 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2437 val = MII_TG3_DSP_TAP26_ALNOKO |
2438 MII_TG3_DSP_TAP26_RMRXSTO;
2439 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2440 tg3_phy_toggle_auxctl_smdsp(tp, false);
2443 val = tr32(TG3_CPMU_EEE_MODE);
2444 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2447 static int tg3_wait_macro_done(struct tg3 *tp)
2454 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2455 if ((tmp32 & 0x1000) == 0)
2465 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2467 static const u32 test_pat[4][6] = {
2468 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2469 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2470 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2471 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2475 for (chan = 0; chan < 4; chan++) {
2478 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2479 (chan * 0x2000) | 0x0200);
2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2482 for (i = 0; i < 6; i++)
2483 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2486 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2487 if (tg3_wait_macro_done(tp)) {
2492 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2493 (chan * 0x2000) | 0x0200);
2494 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2495 if (tg3_wait_macro_done(tp)) {
2500 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2501 if (tg3_wait_macro_done(tp)) {
2506 for (i = 0; i < 6; i += 2) {
2509 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2510 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2511 tg3_wait_macro_done(tp)) {
2517 if (low != test_pat[chan][i] ||
2518 high != test_pat[chan][i+1]) {
2519 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2520 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2521 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2531 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2535 for (chan = 0; chan < 4; chan++) {
2538 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2539 (chan * 0x2000) | 0x0200);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2541 for (i = 0; i < 6; i++)
2542 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2543 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2544 if (tg3_wait_macro_done(tp))
2551 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2553 u32 reg32, phy9_orig;
2554 int retries, do_phy_reset, err;
2560 err = tg3_bmcr_reset(tp);
2566 /* Disable transmitter and interrupt. */
2567 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2571 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2573 /* Set full-duplex, 1000 mbps. */
2574 tg3_writephy(tp, MII_BMCR,
2575 BMCR_FULLDPLX | BMCR_SPEED1000);
2577 /* Set to master mode. */
2578 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2581 tg3_writephy(tp, MII_CTRL1000,
2582 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2584 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2588 /* Block the PHY control access. */
2589 tg3_phydsp_write(tp, 0x8005, 0x0800);
2591 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2594 } while (--retries);
2596 err = tg3_phy_reset_chanpat(tp);
2600 tg3_phydsp_write(tp, 0x8005, 0x0000);
2602 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2603 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2605 tg3_phy_toggle_auxctl_smdsp(tp, false);
2607 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2609 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2618 static void tg3_carrier_off(struct tg3 *tp)
2620 netif_carrier_off(tp->dev);
2621 tp->link_up = false;
2624 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2626 if (tg3_flag(tp, ENABLE_ASF))
2627 netdev_warn(tp->dev,
2628 "Management side-band traffic will be interrupted during phy settings change\n");
2631 /* This will reset the tigon3 PHY if there is no valid
2632 * link unless the FORCE argument is non-zero.
2634 static int tg3_phy_reset(struct tg3 *tp)
2639 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2640 val = tr32(GRC_MISC_CFG);
2641 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2644 err = tg3_readphy(tp, MII_BMSR, &val);
2645 err |= tg3_readphy(tp, MII_BMSR, &val);
2649 if (netif_running(tp->dev) && tp->link_up) {
2650 netif_carrier_off(tp->dev);
2651 tg3_link_report(tp);
2654 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2655 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2656 tg3_asic_rev(tp) == ASIC_REV_5705) {
2657 err = tg3_phy_reset_5703_4_5(tp);
2664 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2665 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2666 cpmuctrl = tr32(TG3_CPMU_CTRL);
2667 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2669 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2672 err = tg3_bmcr_reset(tp);
2676 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2677 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2678 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2680 tw32(TG3_CPMU_CTRL, cpmuctrl);
2683 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2684 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2685 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2686 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2687 CPMU_LSPD_1000MB_MACCLK_12_5) {
2688 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2690 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2694 if (tg3_flag(tp, 5717_PLUS) &&
2695 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2698 tg3_phy_apply_otp(tp);
2700 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2701 tg3_phy_toggle_apd(tp, true);
2703 tg3_phy_toggle_apd(tp, false);
2706 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2707 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2708 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2709 tg3_phydsp_write(tp, 0x000a, 0x0323);
2710 tg3_phy_toggle_auxctl_smdsp(tp, false);
2713 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2714 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2715 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2718 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2719 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2720 tg3_phydsp_write(tp, 0x000a, 0x310b);
2721 tg3_phydsp_write(tp, 0x201f, 0x9506);
2722 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2723 tg3_phy_toggle_auxctl_smdsp(tp, false);
2725 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2726 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2727 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2728 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2729 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2730 tg3_writephy(tp, MII_TG3_TEST1,
2731 MII_TG3_TEST1_TRIM_EN | 0x4);
2733 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2735 tg3_phy_toggle_auxctl_smdsp(tp, false);
2739 /* Set Extended packet length bit (bit 14) on all chips that */
2740 /* support jumbo frames */
2741 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2742 /* Cannot do read-modify-write on 5401 */
2743 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2744 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2745 /* Set bit 14 with read-modify-write to preserve other bits */
2746 err = tg3_phy_auxctl_read(tp,
2747 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2749 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2750 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2753 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2754 * jumbo frames transmission.
2756 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2757 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2758 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2759 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2762 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2763 /* adjust output voltage */
2764 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2767 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2768 tg3_phydsp_write(tp, 0xffb, 0x4000);
2770 tg3_phy_toggle_automdix(tp, true);
2771 tg3_phy_set_wirespeed(tp);
2775 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2776 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2777 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2778 TG3_GPIO_MSG_NEED_VAUX)
2779 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2780 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2782 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2783 (TG3_GPIO_MSG_DRVR_PRES << 12))
2785 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2786 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2788 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2789 (TG3_GPIO_MSG_NEED_VAUX << 12))
2791 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2795 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2796 tg3_asic_rev(tp) == ASIC_REV_5719)
2797 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2799 status = tr32(TG3_CPMU_DRV_STATUS);
2801 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2802 status &= ~(TG3_GPIO_MSG_MASK << shift);
2803 status |= (newstat << shift);
2805 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2806 tg3_asic_rev(tp) == ASIC_REV_5719)
2807 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2809 tw32(TG3_CPMU_DRV_STATUS, status);
2811 return status >> TG3_APE_GPIO_MSG_SHIFT;
2814 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2816 if (!tg3_flag(tp, IS_NIC))
2819 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2820 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2821 tg3_asic_rev(tp) == ASIC_REV_5720) {
2822 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2825 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2827 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2828 TG3_GRC_LCLCTL_PWRSW_DELAY);
2830 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2832 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2833 TG3_GRC_LCLCTL_PWRSW_DELAY);
2839 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2843 if (!tg3_flag(tp, IS_NIC) ||
2844 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2845 tg3_asic_rev(tp) == ASIC_REV_5701)
2848 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2850 tw32_wait_f(GRC_LOCAL_CTRL,
2851 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2852 TG3_GRC_LCLCTL_PWRSW_DELAY);
2854 tw32_wait_f(GRC_LOCAL_CTRL,
2856 TG3_GRC_LCLCTL_PWRSW_DELAY);
2858 tw32_wait_f(GRC_LOCAL_CTRL,
2859 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2860 TG3_GRC_LCLCTL_PWRSW_DELAY);
2863 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2865 if (!tg3_flag(tp, IS_NIC))
2868 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2869 tg3_asic_rev(tp) == ASIC_REV_5701) {
2870 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2871 (GRC_LCLCTRL_GPIO_OE0 |
2872 GRC_LCLCTRL_GPIO_OE1 |
2873 GRC_LCLCTRL_GPIO_OE2 |
2874 GRC_LCLCTRL_GPIO_OUTPUT0 |
2875 GRC_LCLCTRL_GPIO_OUTPUT1),
2876 TG3_GRC_LCLCTL_PWRSW_DELAY);
2877 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2878 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2879 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2880 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2881 GRC_LCLCTRL_GPIO_OE1 |
2882 GRC_LCLCTRL_GPIO_OE2 |
2883 GRC_LCLCTRL_GPIO_OUTPUT0 |
2884 GRC_LCLCTRL_GPIO_OUTPUT1 |
2886 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2887 TG3_GRC_LCLCTL_PWRSW_DELAY);
2889 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2890 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2891 TG3_GRC_LCLCTL_PWRSW_DELAY);
2893 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2894 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2895 TG3_GRC_LCLCTL_PWRSW_DELAY);
2898 u32 grc_local_ctrl = 0;
2900 /* Workaround to prevent overdrawing Amps. */
2901 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2902 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2903 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2905 TG3_GRC_LCLCTL_PWRSW_DELAY);
2908 /* On 5753 and variants, GPIO2 cannot be used. */
2909 no_gpio2 = tp->nic_sram_data_cfg &
2910 NIC_SRAM_DATA_CFG_NO_GPIO2;
2912 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2913 GRC_LCLCTRL_GPIO_OE1 |
2914 GRC_LCLCTRL_GPIO_OE2 |
2915 GRC_LCLCTRL_GPIO_OUTPUT1 |
2916 GRC_LCLCTRL_GPIO_OUTPUT2;
2918 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2919 GRC_LCLCTRL_GPIO_OUTPUT2);
2921 tw32_wait_f(GRC_LOCAL_CTRL,
2922 tp->grc_local_ctrl | grc_local_ctrl,
2923 TG3_GRC_LCLCTL_PWRSW_DELAY);
2925 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2927 tw32_wait_f(GRC_LOCAL_CTRL,
2928 tp->grc_local_ctrl | grc_local_ctrl,
2929 TG3_GRC_LCLCTL_PWRSW_DELAY);
2932 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2933 tw32_wait_f(GRC_LOCAL_CTRL,
2934 tp->grc_local_ctrl | grc_local_ctrl,
2935 TG3_GRC_LCLCTL_PWRSW_DELAY);
2940 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2944 /* Serialize power state transitions */
2945 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2948 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2949 msg = TG3_GPIO_MSG_NEED_VAUX;
2951 msg = tg3_set_function_status(tp, msg);
2953 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2956 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2957 tg3_pwrsrc_switch_to_vaux(tp);
2959 tg3_pwrsrc_die_with_vmain(tp);
2962 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2965 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2967 bool need_vaux = false;
2969 /* The GPIOs do something completely different on 57765. */
2970 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2973 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2974 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2975 tg3_asic_rev(tp) == ASIC_REV_5720) {
2976 tg3_frob_aux_power_5717(tp, include_wol ?
2977 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2981 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2982 struct net_device *dev_peer;
2984 dev_peer = pci_get_drvdata(tp->pdev_peer);
2986 /* remove_one() may have been run on the peer. */
2988 struct tg3 *tp_peer = netdev_priv(dev_peer);
2990 if (tg3_flag(tp_peer, INIT_COMPLETE))
2993 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2994 tg3_flag(tp_peer, ENABLE_ASF))
2999 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
3000 tg3_flag(tp, ENABLE_ASF))
3004 tg3_pwrsrc_switch_to_vaux(tp);
3006 tg3_pwrsrc_die_with_vmain(tp);
3009 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3011 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3013 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3014 if (speed != SPEED_10)
3016 } else if (speed == SPEED_10)
3022 static bool tg3_phy_power_bug(struct tg3 *tp)
3024 switch (tg3_asic_rev(tp)) {
3029 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3038 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3047 static bool tg3_phy_led_bug(struct tg3 *tp)
3049 switch (tg3_asic_rev(tp)) {
3052 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3061 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3065 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3068 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3069 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3070 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3071 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3074 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3075 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3076 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3081 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3083 val = tr32(GRC_MISC_CFG);
3084 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3087 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3089 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3092 tg3_writephy(tp, MII_ADVERTISE, 0);
3093 tg3_writephy(tp, MII_BMCR,
3094 BMCR_ANENABLE | BMCR_ANRESTART);
3096 tg3_writephy(tp, MII_TG3_FET_TEST,
3097 phytest | MII_TG3_FET_SHADOW_EN);
3098 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3099 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3101 MII_TG3_FET_SHDW_AUXMODE4,
3104 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3107 } else if (do_low_power) {
3108 if (!tg3_phy_led_bug(tp))
3109 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3110 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3112 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3113 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3114 MII_TG3_AUXCTL_PCTL_VREG_11V;
3115 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3118 /* The PHY should not be powered down on some chips because
3121 if (tg3_phy_power_bug(tp))
3124 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3125 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3126 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3127 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3128 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3129 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3132 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3135 /* tp->lock is held. */
3136 static int tg3_nvram_lock(struct tg3 *tp)
3138 if (tg3_flag(tp, NVRAM)) {
3141 if (tp->nvram_lock_cnt == 0) {
3142 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3143 for (i = 0; i < 8000; i++) {
3144 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3149 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3153 tp->nvram_lock_cnt++;
3158 /* tp->lock is held. */
3159 static void tg3_nvram_unlock(struct tg3 *tp)
3161 if (tg3_flag(tp, NVRAM)) {
3162 if (tp->nvram_lock_cnt > 0)
3163 tp->nvram_lock_cnt--;
3164 if (tp->nvram_lock_cnt == 0)
3165 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3169 /* tp->lock is held. */
3170 static void tg3_enable_nvram_access(struct tg3 *tp)
3172 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3173 u32 nvaccess = tr32(NVRAM_ACCESS);
3175 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3179 /* tp->lock is held. */
3180 static void tg3_disable_nvram_access(struct tg3 *tp)
3182 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3183 u32 nvaccess = tr32(NVRAM_ACCESS);
3185 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3189 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3190 u32 offset, u32 *val)
3195 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3198 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3199 EEPROM_ADDR_DEVID_MASK |
3201 tw32(GRC_EEPROM_ADDR,
3203 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3204 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3205 EEPROM_ADDR_ADDR_MASK) |
3206 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3208 for (i = 0; i < 1000; i++) {
3209 tmp = tr32(GRC_EEPROM_ADDR);
3211 if (tmp & EEPROM_ADDR_COMPLETE)
3215 if (!(tmp & EEPROM_ADDR_COMPLETE))
3218 tmp = tr32(GRC_EEPROM_DATA);
3221 * The data will always be opposite the native endian
3222 * format. Perform a blind byteswap to compensate.
3229 #define NVRAM_CMD_TIMEOUT 10000
3231 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3235 tw32(NVRAM_CMD, nvram_cmd);
3236 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3238 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3244 if (i == NVRAM_CMD_TIMEOUT)
3250 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3252 if (tg3_flag(tp, NVRAM) &&
3253 tg3_flag(tp, NVRAM_BUFFERED) &&
3254 tg3_flag(tp, FLASH) &&
3255 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3256 (tp->nvram_jedecnum == JEDEC_ATMEL))
3258 addr = ((addr / tp->nvram_pagesize) <<
3259 ATMEL_AT45DB0X1B_PAGE_POS) +
3260 (addr % tp->nvram_pagesize);
3265 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3267 if (tg3_flag(tp, NVRAM) &&
3268 tg3_flag(tp, NVRAM_BUFFERED) &&
3269 tg3_flag(tp, FLASH) &&
3270 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3271 (tp->nvram_jedecnum == JEDEC_ATMEL))
3273 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3274 tp->nvram_pagesize) +
3275 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3280 /* NOTE: Data read in from NVRAM is byteswapped according to
3281 * the byteswapping settings for all other register accesses.
3282 * tg3 devices are BE devices, so on a BE machine, the data
3283 * returned will be exactly as it is seen in NVRAM. On a LE
3284 * machine, the 32-bit value will be byteswapped.
3286 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3290 if (!tg3_flag(tp, NVRAM))
3291 return tg3_nvram_read_using_eeprom(tp, offset, val);
3293 offset = tg3_nvram_phys_addr(tp, offset);
3295 if (offset > NVRAM_ADDR_MSK)
3298 ret = tg3_nvram_lock(tp);
3302 tg3_enable_nvram_access(tp);
3304 tw32(NVRAM_ADDR, offset);
3305 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3306 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3309 *val = tr32(NVRAM_RDDATA);
3311 tg3_disable_nvram_access(tp);
3313 tg3_nvram_unlock(tp);
3318 /* Ensures NVRAM data is in bytestream format. */
3319 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3322 int res = tg3_nvram_read(tp, offset, &v);
3324 *val = cpu_to_be32(v);
3328 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3329 u32 offset, u32 len, u8 *buf)
3334 for (i = 0; i < len; i += 4) {
3340 memcpy(&data, buf + i, 4);
3343 * The SEEPROM interface expects the data to always be opposite
3344 * the native endian format. We accomplish this by reversing
3345 * all the operations that would have been performed on the
3346 * data from a call to tg3_nvram_read_be32().
3348 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3350 val = tr32(GRC_EEPROM_ADDR);
3351 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3353 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3355 tw32(GRC_EEPROM_ADDR, val |
3356 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3357 (addr & EEPROM_ADDR_ADDR_MASK) |
3361 for (j = 0; j < 1000; j++) {
3362 val = tr32(GRC_EEPROM_ADDR);
3364 if (val & EEPROM_ADDR_COMPLETE)
3368 if (!(val & EEPROM_ADDR_COMPLETE)) {
3377 /* offset and length are dword aligned */
3378 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3382 u32 pagesize = tp->nvram_pagesize;
3383 u32 pagemask = pagesize - 1;
3387 tmp = kmalloc(pagesize, GFP_KERNEL);
3393 u32 phy_addr, page_off, size;
3395 phy_addr = offset & ~pagemask;
3397 for (j = 0; j < pagesize; j += 4) {
3398 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3399 (__be32 *) (tmp + j));
3406 page_off = offset & pagemask;
3413 memcpy(tmp + page_off, buf, size);
3415 offset = offset + (pagesize - page_off);
3417 tg3_enable_nvram_access(tp);
3420 * Before we can erase the flash page, we need
3421 * to issue a special "write enable" command.
3423 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3425 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3428 /* Erase the target page */
3429 tw32(NVRAM_ADDR, phy_addr);
3431 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3432 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3434 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3437 /* Issue another write enable to start the write. */
3438 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3440 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3443 for (j = 0; j < pagesize; j += 4) {
3446 data = *((__be32 *) (tmp + j));
3448 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3450 tw32(NVRAM_ADDR, phy_addr + j);
3452 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3456 nvram_cmd |= NVRAM_CMD_FIRST;
3457 else if (j == (pagesize - 4))
3458 nvram_cmd |= NVRAM_CMD_LAST;
3460 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3468 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3469 tg3_nvram_exec_cmd(tp, nvram_cmd);
3476 /* offset and length are dword aligned */
3477 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3482 for (i = 0; i < len; i += 4, offset += 4) {
3483 u32 page_off, phy_addr, nvram_cmd;
3486 memcpy(&data, buf + i, 4);
3487 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3489 page_off = offset % tp->nvram_pagesize;
3491 phy_addr = tg3_nvram_phys_addr(tp, offset);
3493 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3495 if (page_off == 0 || i == 0)
3496 nvram_cmd |= NVRAM_CMD_FIRST;
3497 if (page_off == (tp->nvram_pagesize - 4))
3498 nvram_cmd |= NVRAM_CMD_LAST;
3501 nvram_cmd |= NVRAM_CMD_LAST;
3503 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3504 !tg3_flag(tp, FLASH) ||
3505 !tg3_flag(tp, 57765_PLUS))
3506 tw32(NVRAM_ADDR, phy_addr);
3508 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3509 !tg3_flag(tp, 5755_PLUS) &&
3510 (tp->nvram_jedecnum == JEDEC_ST) &&
3511 (nvram_cmd & NVRAM_CMD_FIRST)) {
3514 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3515 ret = tg3_nvram_exec_cmd(tp, cmd);
3519 if (!tg3_flag(tp, FLASH)) {
3520 /* We always do complete word writes to eeprom. */
3521 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3524 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3531 /* offset and length are dword aligned */
3532 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3536 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3537 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3538 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3542 if (!tg3_flag(tp, NVRAM)) {
3543 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3547 ret = tg3_nvram_lock(tp);
3551 tg3_enable_nvram_access(tp);
3552 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3553 tw32(NVRAM_WRITE1, 0x406);
3555 grc_mode = tr32(GRC_MODE);
3556 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3558 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3559 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3562 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3566 grc_mode = tr32(GRC_MODE);
3567 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3569 tg3_disable_nvram_access(tp);
3570 tg3_nvram_unlock(tp);
3573 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3574 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3581 #define RX_CPU_SCRATCH_BASE 0x30000
3582 #define RX_CPU_SCRATCH_SIZE 0x04000
3583 #define TX_CPU_SCRATCH_BASE 0x34000
3584 #define TX_CPU_SCRATCH_SIZE 0x04000
3586 /* tp->lock is held. */
3587 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3590 const int iters = 10000;
3592 for (i = 0; i < iters; i++) {
3593 tw32(cpu_base + CPU_STATE, 0xffffffff);
3594 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3595 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3597 if (pci_channel_offline(tp->pdev))
3601 return (i == iters) ? -EBUSY : 0;
3604 /* tp->lock is held. */
3605 static int tg3_rxcpu_pause(struct tg3 *tp)
3607 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3609 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3610 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3616 /* tp->lock is held. */
3617 static int tg3_txcpu_pause(struct tg3 *tp)
3619 return tg3_pause_cpu(tp, TX_CPU_BASE);
3622 /* tp->lock is held. */
3623 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3625 tw32(cpu_base + CPU_STATE, 0xffffffff);
3626 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3629 /* tp->lock is held. */
3630 static void tg3_rxcpu_resume(struct tg3 *tp)
3632 tg3_resume_cpu(tp, RX_CPU_BASE);
3635 /* tp->lock is held. */
3636 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3640 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3642 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3643 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3645 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3648 if (cpu_base == RX_CPU_BASE) {
3649 rc = tg3_rxcpu_pause(tp);
3652 * There is only an Rx CPU for the 5750 derivative in the
3655 if (tg3_flag(tp, IS_SSB_CORE))
3658 rc = tg3_txcpu_pause(tp);
3662 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3663 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3667 /* Clear firmware's nvram arbitration. */
3668 if (tg3_flag(tp, NVRAM))
3669 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3673 static int tg3_fw_data_len(struct tg3 *tp,
3674 const struct tg3_firmware_hdr *fw_hdr)
3678 /* Non fragmented firmware have one firmware header followed by a
3679 * contiguous chunk of data to be written. The length field in that
3680 * header is not the length of data to be written but the complete
3681 * length of the bss. The data length is determined based on
3682 * tp->fw->size minus headers.
3684 * Fragmented firmware have a main header followed by multiple
3685 * fragments. Each fragment is identical to non fragmented firmware
3686 * with a firmware header followed by a contiguous chunk of data. In
3687 * the main header, the length field is unused and set to 0xffffffff.
3688 * In each fragment header the length is the entire size of that
3689 * fragment i.e. fragment data + header length. Data length is
3690 * therefore length field in the header minus TG3_FW_HDR_LEN.
3692 if (tp->fw_len == 0xffffffff)
3693 fw_len = be32_to_cpu(fw_hdr->len);
3695 fw_len = tp->fw->size;
3697 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3700 /* tp->lock is held. */
3701 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3702 u32 cpu_scratch_base, int cpu_scratch_size,
3703 const struct tg3_firmware_hdr *fw_hdr)
3706 void (*write_op)(struct tg3 *, u32, u32);
3707 int total_len = tp->fw->size;
3709 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3711 "%s: Trying to load TX cpu firmware which is 5705\n",
3716 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3717 write_op = tg3_write_mem;
3719 write_op = tg3_write_indirect_reg32;
3721 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3722 /* It is possible that bootcode is still loading at this point.
3723 * Get the nvram lock first before halting the cpu.
3725 int lock_err = tg3_nvram_lock(tp);
3726 err = tg3_halt_cpu(tp, cpu_base);
3728 tg3_nvram_unlock(tp);
3732 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3733 write_op(tp, cpu_scratch_base + i, 0);
3734 tw32(cpu_base + CPU_STATE, 0xffffffff);
3735 tw32(cpu_base + CPU_MODE,
3736 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3738 /* Subtract additional main header for fragmented firmware and
3739 * advance to the first fragment
3741 total_len -= TG3_FW_HDR_LEN;
3746 u32 *fw_data = (u32 *)(fw_hdr + 1);
3747 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3748 write_op(tp, cpu_scratch_base +
3749 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3751 be32_to_cpu(fw_data[i]));
3753 total_len -= be32_to_cpu(fw_hdr->len);
3755 /* Advance to next fragment */
3756 fw_hdr = (struct tg3_firmware_hdr *)
3757 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3758 } while (total_len > 0);
3766 /* tp->lock is held. */
3767 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3770 const int iters = 5;
3772 tw32(cpu_base + CPU_STATE, 0xffffffff);
3773 tw32_f(cpu_base + CPU_PC, pc);
3775 for (i = 0; i < iters; i++) {
3776 if (tr32(cpu_base + CPU_PC) == pc)
3778 tw32(cpu_base + CPU_STATE, 0xffffffff);
3779 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3780 tw32_f(cpu_base + CPU_PC, pc);
3784 return (i == iters) ? -EBUSY : 0;
3787 /* tp->lock is held. */
3788 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3790 const struct tg3_firmware_hdr *fw_hdr;
3793 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3795 /* Firmware blob starts with version numbers, followed by
3796 start address and length. We are setting complete length.
3797 length = end_address_of_bss - start_address_of_text.
3798 Remainder is the blob to be loaded contiguously
3799 from start address. */
3801 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3802 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3807 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3808 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3813 /* Now startup only the RX cpu. */
3814 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3815 be32_to_cpu(fw_hdr->base_addr));
3817 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3818 "should be %08x\n", __func__,
3819 tr32(RX_CPU_BASE + CPU_PC),
3820 be32_to_cpu(fw_hdr->base_addr));
3824 tg3_rxcpu_resume(tp);
3829 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3831 const int iters = 1000;
3835 /* Wait for boot code to complete initialization and enter service
3836 * loop. It is then safe to download service patches
3838 for (i = 0; i < iters; i++) {
3839 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3846 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3850 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3852 netdev_warn(tp->dev,
3853 "Other patches exist. Not downloading EEE patch\n");
3860 /* tp->lock is held. */
3861 static void tg3_load_57766_firmware(struct tg3 *tp)
3863 struct tg3_firmware_hdr *fw_hdr;
3865 if (!tg3_flag(tp, NO_NVRAM))
3868 if (tg3_validate_rxcpu_state(tp))
3874 /* This firmware blob has a different format than older firmware
3875 * releases as given below. The main difference is we have fragmented
3876 * data to be written to non-contiguous locations.
3878 * In the beginning we have a firmware header identical to other
3879 * firmware which consists of version, base addr and length. The length
3880 * here is unused and set to 0xffffffff.
3882 * This is followed by a series of firmware fragments which are
3883 * individually identical to previous firmware. i.e. they have the
3884 * firmware header and followed by data for that fragment. The version
3885 * field of the individual fragment header is unused.
3888 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3889 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3892 if (tg3_rxcpu_pause(tp))
3895 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3896 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3898 tg3_rxcpu_resume(tp);
3901 /* tp->lock is held. */
3902 static int tg3_load_tso_firmware(struct tg3 *tp)
3904 const struct tg3_firmware_hdr *fw_hdr;
3905 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3908 if (!tg3_flag(tp, FW_TSO))
3911 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3913 /* Firmware blob starts with version numbers, followed by
3914 start address and length. We are setting complete length.
3915 length = end_address_of_bss - start_address_of_text.
3916 Remainder is the blob to be loaded contiguously
3917 from start address. */
3919 cpu_scratch_size = tp->fw_len;
3921 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3922 cpu_base = RX_CPU_BASE;
3923 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3925 cpu_base = TX_CPU_BASE;
3926 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3927 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3930 err = tg3_load_firmware_cpu(tp, cpu_base,
3931 cpu_scratch_base, cpu_scratch_size,
3936 /* Now startup the cpu. */
3937 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3938 be32_to_cpu(fw_hdr->base_addr));
3941 "%s fails to set CPU PC, is %08x should be %08x\n",
3942 __func__, tr32(cpu_base + CPU_PC),
3943 be32_to_cpu(fw_hdr->base_addr));
3947 tg3_resume_cpu(tp, cpu_base);
3952 /* tp->lock is held. */
3953 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3955 u32 addr_high, addr_low;
3958 addr_high = ((tp->dev->dev_addr[0] << 8) |
3959 tp->dev->dev_addr[1]);
3960 addr_low = ((tp->dev->dev_addr[2] << 24) |
3961 (tp->dev->dev_addr[3] << 16) |
3962 (tp->dev->dev_addr[4] << 8) |
3963 (tp->dev->dev_addr[5] << 0));
3964 for (i = 0; i < 4; i++) {
3965 if (i == 1 && skip_mac_1)
3967 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3968 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3971 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3972 tg3_asic_rev(tp) == ASIC_REV_5704) {
3973 for (i = 0; i < 12; i++) {
3974 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3975 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3979 addr_high = (tp->dev->dev_addr[0] +
3980 tp->dev->dev_addr[1] +
3981 tp->dev->dev_addr[2] +
3982 tp->dev->dev_addr[3] +
3983 tp->dev->dev_addr[4] +
3984 tp->dev->dev_addr[5]) &
3985 TX_BACKOFF_SEED_MASK;
3986 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3989 static void tg3_enable_register_access(struct tg3 *tp)
3992 * Make sure register accesses (indirect or otherwise) will function
3995 pci_write_config_dword(tp->pdev,
3996 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
3999 static int tg3_power_up(struct tg3 *tp)
4003 tg3_enable_register_access(tp);
4005 err = pci_set_power_state(tp->pdev, PCI_D0);
4007 /* Switch out of Vaux if it is a NIC */
4008 tg3_pwrsrc_switch_to_vmain(tp);
4010 netdev_err(tp->dev, "Transition to D0 failed\n");
4016 static int tg3_setup_phy(struct tg3 *, bool);
4018 static int tg3_power_down_prepare(struct tg3 *tp)
4021 bool device_should_wake, do_low_power;
4023 tg3_enable_register_access(tp);
4025 /* Restore the CLKREQ setting. */
4026 if (tg3_flag(tp, CLKREQ_BUG))
4027 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4028 PCI_EXP_LNKCTL_CLKREQ_EN);
4030 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4031 tw32(TG3PCI_MISC_HOST_CTRL,
4032 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4034 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4035 tg3_flag(tp, WOL_ENABLE);
4037 if (tg3_flag(tp, USE_PHYLIB)) {
4038 do_low_power = false;
4039 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4040 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4041 struct phy_device *phydev;
4042 u32 phyid, advertising;
4044 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4046 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4048 tp->link_config.speed = phydev->speed;
4049 tp->link_config.duplex = phydev->duplex;
4050 tp->link_config.autoneg = phydev->autoneg;
4051 tp->link_config.advertising = phydev->advertising;
4053 advertising = ADVERTISED_TP |
4055 ADVERTISED_Autoneg |
4056 ADVERTISED_10baseT_Half;
4058 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4059 if (tg3_flag(tp, WOL_SPEED_100MB))
4061 ADVERTISED_100baseT_Half |
4062 ADVERTISED_100baseT_Full |
4063 ADVERTISED_10baseT_Full;
4065 advertising |= ADVERTISED_10baseT_Full;
4068 phydev->advertising = advertising;
4070 phy_start_aneg(phydev);
4072 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4073 if (phyid != PHY_ID_BCMAC131) {
4074 phyid &= PHY_BCM_OUI_MASK;
4075 if (phyid == PHY_BCM_OUI_1 ||
4076 phyid == PHY_BCM_OUI_2 ||
4077 phyid == PHY_BCM_OUI_3)
4078 do_low_power = true;
4082 do_low_power = true;
4084 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4085 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4087 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4088 tg3_setup_phy(tp, false);
4091 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4094 val = tr32(GRC_VCPU_EXT_CTRL);
4095 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4096 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4100 for (i = 0; i < 200; i++) {
4101 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4102 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4107 if (tg3_flag(tp, WOL_CAP))
4108 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4109 WOL_DRV_STATE_SHUTDOWN |
4113 if (device_should_wake) {
4116 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4118 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4119 tg3_phy_auxctl_write(tp,
4120 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4121 MII_TG3_AUXCTL_PCTL_WOL_EN |
4122 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4123 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4127 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4128 mac_mode = MAC_MODE_PORT_MODE_GMII;
4129 else if (tp->phy_flags &
4130 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4131 if (tp->link_config.active_speed == SPEED_1000)
4132 mac_mode = MAC_MODE_PORT_MODE_GMII;
4134 mac_mode = MAC_MODE_PORT_MODE_MII;
4136 mac_mode = MAC_MODE_PORT_MODE_MII;
4138 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4139 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4140 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4141 SPEED_100 : SPEED_10;
4142 if (tg3_5700_link_polarity(tp, speed))
4143 mac_mode |= MAC_MODE_LINK_POLARITY;
4145 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4148 mac_mode = MAC_MODE_PORT_MODE_TBI;
4151 if (!tg3_flag(tp, 5750_PLUS))
4152 tw32(MAC_LED_CTRL, tp->led_ctrl);
4154 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4155 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4156 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4157 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4159 if (tg3_flag(tp, ENABLE_APE))
4160 mac_mode |= MAC_MODE_APE_TX_EN |
4161 MAC_MODE_APE_RX_EN |
4162 MAC_MODE_TDE_ENABLE;
4164 tw32_f(MAC_MODE, mac_mode);
4167 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4171 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4172 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4173 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4176 base_val = tp->pci_clock_ctrl;
4177 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4178 CLOCK_CTRL_TXCLK_DISABLE);
4180 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4181 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4182 } else if (tg3_flag(tp, 5780_CLASS) ||
4183 tg3_flag(tp, CPMU_PRESENT) ||
4184 tg3_asic_rev(tp) == ASIC_REV_5906) {
4186 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4187 u32 newbits1, newbits2;
4189 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4190 tg3_asic_rev(tp) == ASIC_REV_5701) {
4191 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4192 CLOCK_CTRL_TXCLK_DISABLE |
4194 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4195 } else if (tg3_flag(tp, 5705_PLUS)) {
4196 newbits1 = CLOCK_CTRL_625_CORE;
4197 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4199 newbits1 = CLOCK_CTRL_ALTCLK;
4200 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4203 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4206 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4209 if (!tg3_flag(tp, 5705_PLUS)) {
4212 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4213 tg3_asic_rev(tp) == ASIC_REV_5701) {
4214 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4215 CLOCK_CTRL_TXCLK_DISABLE |
4216 CLOCK_CTRL_44MHZ_CORE);
4218 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4221 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4222 tp->pci_clock_ctrl | newbits3, 40);
4226 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4227 tg3_power_down_phy(tp, do_low_power);
4229 tg3_frob_aux_power(tp, true);
4231 /* Workaround for unstable PLL clock */
4232 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4233 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4234 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4235 u32 val = tr32(0x7d00);
4237 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4239 if (!tg3_flag(tp, ENABLE_ASF)) {
4242 err = tg3_nvram_lock(tp);
4243 tg3_halt_cpu(tp, RX_CPU_BASE);
4245 tg3_nvram_unlock(tp);
4249 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4251 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4256 static void tg3_power_down(struct tg3 *tp)
4258 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4259 pci_set_power_state(tp->pdev, PCI_D3hot);
4262 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4264 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4265 case MII_TG3_AUX_STAT_10HALF:
4267 *duplex = DUPLEX_HALF;
4270 case MII_TG3_AUX_STAT_10FULL:
4272 *duplex = DUPLEX_FULL;
4275 case MII_TG3_AUX_STAT_100HALF:
4277 *duplex = DUPLEX_HALF;
4280 case MII_TG3_AUX_STAT_100FULL:
4282 *duplex = DUPLEX_FULL;
4285 case MII_TG3_AUX_STAT_1000HALF:
4286 *speed = SPEED_1000;
4287 *duplex = DUPLEX_HALF;
4290 case MII_TG3_AUX_STAT_1000FULL:
4291 *speed = SPEED_1000;
4292 *duplex = DUPLEX_FULL;
4296 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4297 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4299 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4303 *speed = SPEED_UNKNOWN;
4304 *duplex = DUPLEX_UNKNOWN;
4309 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4314 new_adv = ADVERTISE_CSMA;
4315 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4316 new_adv |= mii_advertise_flowctrl(flowctrl);
4318 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4322 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4323 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4325 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4326 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4327 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4329 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4334 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4337 tw32(TG3_CPMU_EEE_MODE,
4338 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4340 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4345 /* Advertise 100-BaseTX EEE ability */
4346 if (advertise & ADVERTISED_100baseT_Full)
4347 val |= MDIO_AN_EEE_ADV_100TX;
4348 /* Advertise 1000-BaseT EEE ability */
4349 if (advertise & ADVERTISED_1000baseT_Full)
4350 val |= MDIO_AN_EEE_ADV_1000T;
4352 if (!tp->eee.eee_enabled) {
4354 tp->eee.advertised = 0;
4356 tp->eee.advertised = advertise &
4357 (ADVERTISED_100baseT_Full |
4358 ADVERTISED_1000baseT_Full);
4361 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4365 switch (tg3_asic_rev(tp)) {
4367 case ASIC_REV_57765:
4368 case ASIC_REV_57766:
4370 /* If we advertised any eee advertisements above... */
4372 val = MII_TG3_DSP_TAP26_ALNOKO |
4373 MII_TG3_DSP_TAP26_RMRXSTO |
4374 MII_TG3_DSP_TAP26_OPCSINPT;
4375 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4379 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4380 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4381 MII_TG3_DSP_CH34TP2_HIBW01);
4384 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4393 static void tg3_phy_copper_begin(struct tg3 *tp)
4395 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4396 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4399 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4400 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4401 adv = ADVERTISED_10baseT_Half |
4402 ADVERTISED_10baseT_Full;
4403 if (tg3_flag(tp, WOL_SPEED_100MB))
4404 adv |= ADVERTISED_100baseT_Half |
4405 ADVERTISED_100baseT_Full;
4406 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK)
4407 adv |= ADVERTISED_1000baseT_Half |
4408 ADVERTISED_1000baseT_Full;
4410 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4412 adv = tp->link_config.advertising;
4413 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4414 adv &= ~(ADVERTISED_1000baseT_Half |
4415 ADVERTISED_1000baseT_Full);
4417 fc = tp->link_config.flowctrl;
4420 tg3_phy_autoneg_cfg(tp, adv, fc);
4422 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4423 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4424 /* Normally during power down we want to autonegotiate
4425 * the lowest possible speed for WOL. However, to avoid
4426 * link flap, we leave it untouched.
4431 tg3_writephy(tp, MII_BMCR,
4432 BMCR_ANENABLE | BMCR_ANRESTART);
4435 u32 bmcr, orig_bmcr;
4437 tp->link_config.active_speed = tp->link_config.speed;
4438 tp->link_config.active_duplex = tp->link_config.duplex;
4440 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4441 /* With autoneg disabled, 5715 only links up when the
4442 * advertisement register has the configured speed
4445 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4449 switch (tp->link_config.speed) {
4455 bmcr |= BMCR_SPEED100;
4459 bmcr |= BMCR_SPEED1000;
4463 if (tp->link_config.duplex == DUPLEX_FULL)
4464 bmcr |= BMCR_FULLDPLX;
4466 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4467 (bmcr != orig_bmcr)) {
4468 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4469 for (i = 0; i < 1500; i++) {
4473 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4474 tg3_readphy(tp, MII_BMSR, &tmp))
4476 if (!(tmp & BMSR_LSTATUS)) {
4481 tg3_writephy(tp, MII_BMCR, bmcr);
4487 static int tg3_phy_pull_config(struct tg3 *tp)
4492 err = tg3_readphy(tp, MII_BMCR, &val);
4496 if (!(val & BMCR_ANENABLE)) {
4497 tp->link_config.autoneg = AUTONEG_DISABLE;
4498 tp->link_config.advertising = 0;
4499 tg3_flag_clear(tp, PAUSE_AUTONEG);
4503 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4505 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4508 tp->link_config.speed = SPEED_10;
4511 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4514 tp->link_config.speed = SPEED_100;
4516 case BMCR_SPEED1000:
4517 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4518 tp->link_config.speed = SPEED_1000;
4526 if (val & BMCR_FULLDPLX)
4527 tp->link_config.duplex = DUPLEX_FULL;
4529 tp->link_config.duplex = DUPLEX_HALF;
4531 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4537 tp->link_config.autoneg = AUTONEG_ENABLE;
4538 tp->link_config.advertising = ADVERTISED_Autoneg;
4539 tg3_flag_set(tp, PAUSE_AUTONEG);
4541 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4544 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4548 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4549 tp->link_config.advertising |= adv | ADVERTISED_TP;
4551 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4553 tp->link_config.advertising |= ADVERTISED_FIBRE;
4556 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4559 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4560 err = tg3_readphy(tp, MII_CTRL1000, &val);
4564 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4566 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4570 adv = tg3_decode_flowctrl_1000X(val);
4571 tp->link_config.flowctrl = adv;
4573 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4574 adv = mii_adv_to_ethtool_adv_x(val);
4577 tp->link_config.advertising |= adv;
4584 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4588 /* Turn off tap power management. */
4589 /* Set Extended packet length bit */
4590 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4592 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4593 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4594 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4595 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4596 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4603 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4605 struct ethtool_eee eee;
4607 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4610 tg3_eee_pull_config(tp, &eee);
4612 if (tp->eee.eee_enabled) {
4613 if (tp->eee.advertised != eee.advertised ||
4614 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4615 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4618 /* EEE is disabled but we're advertising */
4626 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4628 u32 advmsk, tgtadv, advertising;
4630 advertising = tp->link_config.advertising;
4631 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4633 advmsk = ADVERTISE_ALL;
4634 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4635 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4636 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4639 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4642 if ((*lcladv & advmsk) != tgtadv)
4645 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4648 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4650 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4654 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4655 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4656 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4657 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4658 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4660 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4663 if (tg3_ctrl != tgtadv)
4670 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4674 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4677 if (tg3_readphy(tp, MII_STAT1000, &val))
4680 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4683 if (tg3_readphy(tp, MII_LPA, rmtadv))
4686 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4687 tp->link_config.rmt_adv = lpeth;
4692 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4694 if (curr_link_up != tp->link_up) {
4696 netif_carrier_on(tp->dev);
4698 netif_carrier_off(tp->dev);
4699 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4700 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4703 tg3_link_report(tp);
4710 static void tg3_clear_mac_status(struct tg3 *tp)
4715 MAC_STATUS_SYNC_CHANGED |
4716 MAC_STATUS_CFG_CHANGED |
4717 MAC_STATUS_MI_COMPLETION |
4718 MAC_STATUS_LNKSTATE_CHANGED);
4722 static void tg3_setup_eee(struct tg3 *tp)
4726 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4727 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4728 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4729 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4731 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4733 tw32_f(TG3_CPMU_EEE_CTRL,
4734 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4736 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4737 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4738 TG3_CPMU_EEEMD_LPI_IN_RX |
4739 TG3_CPMU_EEEMD_EEE_ENABLE;
4741 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4742 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4744 if (tg3_flag(tp, ENABLE_APE))
4745 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4747 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4749 tw32_f(TG3_CPMU_EEE_DBTMR1,
4750 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4751 (tp->eee.tx_lpi_timer & 0xffff));
4753 tw32_f(TG3_CPMU_EEE_DBTMR2,
4754 TG3_CPMU_DBTMR2_APE_TX_2047US |
4755 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4758 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4760 bool current_link_up;
4762 u32 lcl_adv, rmt_adv;
4767 tg3_clear_mac_status(tp);
4769 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4771 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4775 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4777 /* Some third-party PHYs need to be reset on link going
4780 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4781 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4782 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4784 tg3_readphy(tp, MII_BMSR, &bmsr);
4785 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4786 !(bmsr & BMSR_LSTATUS))
4792 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4793 tg3_readphy(tp, MII_BMSR, &bmsr);
4794 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4795 !tg3_flag(tp, INIT_COMPLETE))
4798 if (!(bmsr & BMSR_LSTATUS)) {
4799 err = tg3_init_5401phy_dsp(tp);
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 for (i = 0; i < 1000; i++) {
4806 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4807 (bmsr & BMSR_LSTATUS)) {
4813 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4814 TG3_PHY_REV_BCM5401_B0 &&
4815 !(bmsr & BMSR_LSTATUS) &&
4816 tp->link_config.active_speed == SPEED_1000) {
4817 err = tg3_phy_reset(tp);
4819 err = tg3_init_5401phy_dsp(tp);
4824 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4825 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4826 /* 5701 {A0,B0} CRC bug workaround */
4827 tg3_writephy(tp, 0x15, 0x0a75);
4828 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4829 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4830 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4833 /* Clear pending interrupts... */
4834 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4835 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4837 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4838 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4839 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4840 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4842 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4843 tg3_asic_rev(tp) == ASIC_REV_5701) {
4844 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4845 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4846 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4848 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4851 current_link_up = false;
4852 current_speed = SPEED_UNKNOWN;
4853 current_duplex = DUPLEX_UNKNOWN;
4854 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4855 tp->link_config.rmt_adv = 0;
4857 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4858 err = tg3_phy_auxctl_read(tp,
4859 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4861 if (!err && !(val & (1 << 10))) {
4862 tg3_phy_auxctl_write(tp,
4863 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4870 for (i = 0; i < 100; i++) {
4871 tg3_readphy(tp, MII_BMSR, &bmsr);
4872 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4873 (bmsr & BMSR_LSTATUS))
4878 if (bmsr & BMSR_LSTATUS) {
4881 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4882 for (i = 0; i < 2000; i++) {
4884 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4889 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4894 for (i = 0; i < 200; i++) {
4895 tg3_readphy(tp, MII_BMCR, &bmcr);
4896 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4898 if (bmcr && bmcr != 0x7fff)
4906 tp->link_config.active_speed = current_speed;
4907 tp->link_config.active_duplex = current_duplex;
4909 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4910 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4912 if ((bmcr & BMCR_ANENABLE) &&
4914 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4915 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4916 current_link_up = true;
4918 /* EEE settings changes take effect only after a phy
4919 * reset. If we have skipped a reset due to Link Flap
4920 * Avoidance being enabled, do it now.
4922 if (!eee_config_ok &&
4923 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4929 if (!(bmcr & BMCR_ANENABLE) &&
4930 tp->link_config.speed == current_speed &&
4931 tp->link_config.duplex == current_duplex) {
4932 current_link_up = true;
4936 if (current_link_up &&
4937 tp->link_config.active_duplex == DUPLEX_FULL) {
4940 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4941 reg = MII_TG3_FET_GEN_STAT;
4942 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4944 reg = MII_TG3_EXT_STAT;
4945 bit = MII_TG3_EXT_STAT_MDIX;
4948 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4949 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4951 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4956 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4957 tg3_phy_copper_begin(tp);
4959 if (tg3_flag(tp, ROBOSWITCH)) {
4960 current_link_up = true;
4961 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4962 current_speed = SPEED_1000;
4963 current_duplex = DUPLEX_FULL;
4964 tp->link_config.active_speed = current_speed;
4965 tp->link_config.active_duplex = current_duplex;
4968 tg3_readphy(tp, MII_BMSR, &bmsr);
4969 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4970 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4971 current_link_up = true;
4974 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4975 if (current_link_up) {
4976 if (tp->link_config.active_speed == SPEED_100 ||
4977 tp->link_config.active_speed == SPEED_10)
4978 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4980 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4981 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4982 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4984 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4986 /* In order for the 5750 core in BCM4785 chip to work properly
4987 * in RGMII mode, the Led Control Register must be set up.
4989 if (tg3_flag(tp, RGMII_MODE)) {
4990 u32 led_ctrl = tr32(MAC_LED_CTRL);
4991 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
4993 if (tp->link_config.active_speed == SPEED_10)
4994 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
4995 else if (tp->link_config.active_speed == SPEED_100)
4996 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
4997 LED_CTRL_100MBPS_ON);
4998 else if (tp->link_config.active_speed == SPEED_1000)
4999 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5000 LED_CTRL_1000MBPS_ON);
5002 tw32(MAC_LED_CTRL, led_ctrl);
5006 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5007 if (tp->link_config.active_duplex == DUPLEX_HALF)
5008 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5010 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5011 if (current_link_up &&
5012 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5013 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5015 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5018 /* ??? Without this setting Netgear GA302T PHY does not
5019 * ??? send/receive packets...
5021 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5022 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5023 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5024 tw32_f(MAC_MI_MODE, tp->mi_mode);
5028 tw32_f(MAC_MODE, tp->mac_mode);
5031 tg3_phy_eee_adjust(tp, current_link_up);
5033 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5034 /* Polled via timer. */
5035 tw32_f(MAC_EVENT, 0);
5037 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5041 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5043 tp->link_config.active_speed == SPEED_1000 &&
5044 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5047 (MAC_STATUS_SYNC_CHANGED |
5048 MAC_STATUS_CFG_CHANGED));
5051 NIC_SRAM_FIRMWARE_MBOX,
5052 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5055 /* Prevent send BD corruption. */
5056 if (tg3_flag(tp, CLKREQ_BUG)) {
5057 if (tp->link_config.active_speed == SPEED_100 ||
5058 tp->link_config.active_speed == SPEED_10)
5059 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5060 PCI_EXP_LNKCTL_CLKREQ_EN);
5062 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5063 PCI_EXP_LNKCTL_CLKREQ_EN);
5066 tg3_test_and_report_link_chg(tp, current_link_up);
5071 struct tg3_fiber_aneginfo {
5073 #define ANEG_STATE_UNKNOWN 0
5074 #define ANEG_STATE_AN_ENABLE 1
5075 #define ANEG_STATE_RESTART_INIT 2
5076 #define ANEG_STATE_RESTART 3
5077 #define ANEG_STATE_DISABLE_LINK_OK 4
5078 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5079 #define ANEG_STATE_ABILITY_DETECT 6
5080 #define ANEG_STATE_ACK_DETECT_INIT 7
5081 #define ANEG_STATE_ACK_DETECT 8
5082 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5083 #define ANEG_STATE_COMPLETE_ACK 10
5084 #define ANEG_STATE_IDLE_DETECT_INIT 11
5085 #define ANEG_STATE_IDLE_DETECT 12
5086 #define ANEG_STATE_LINK_OK 13
5087 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5088 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5091 #define MR_AN_ENABLE 0x00000001
5092 #define MR_RESTART_AN 0x00000002
5093 #define MR_AN_COMPLETE 0x00000004
5094 #define MR_PAGE_RX 0x00000008
5095 #define MR_NP_LOADED 0x00000010
5096 #define MR_TOGGLE_TX 0x00000020
5097 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5098 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5099 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5100 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5101 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5102 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5103 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5104 #define MR_TOGGLE_RX 0x00002000
5105 #define MR_NP_RX 0x00004000
5107 #define MR_LINK_OK 0x80000000
5109 unsigned long link_time, cur_time;
5111 u32 ability_match_cfg;
5112 int ability_match_count;
5114 char ability_match, idle_match, ack_match;
5116 u32 txconfig, rxconfig;
5117 #define ANEG_CFG_NP 0x00000080
5118 #define ANEG_CFG_ACK 0x00000040
5119 #define ANEG_CFG_RF2 0x00000020
5120 #define ANEG_CFG_RF1 0x00000010
5121 #define ANEG_CFG_PS2 0x00000001
5122 #define ANEG_CFG_PS1 0x00008000
5123 #define ANEG_CFG_HD 0x00004000
5124 #define ANEG_CFG_FD 0x00002000
5125 #define ANEG_CFG_INVAL 0x00001f06
5130 #define ANEG_TIMER_ENAB 2
5131 #define ANEG_FAILED -1
5133 #define ANEG_STATE_SETTLE_TIME 10000
5135 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5136 struct tg3_fiber_aneginfo *ap)
5139 unsigned long delta;
5143 if (ap->state == ANEG_STATE_UNKNOWN) {
5147 ap->ability_match_cfg = 0;
5148 ap->ability_match_count = 0;
5149 ap->ability_match = 0;
5155 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5156 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5158 if (rx_cfg_reg != ap->ability_match_cfg) {
5159 ap->ability_match_cfg = rx_cfg_reg;
5160 ap->ability_match = 0;
5161 ap->ability_match_count = 0;
5163 if (++ap->ability_match_count > 1) {
5164 ap->ability_match = 1;
5165 ap->ability_match_cfg = rx_cfg_reg;
5168 if (rx_cfg_reg & ANEG_CFG_ACK)
5176 ap->ability_match_cfg = 0;
5177 ap->ability_match_count = 0;
5178 ap->ability_match = 0;
5184 ap->rxconfig = rx_cfg_reg;
5187 switch (ap->state) {
5188 case ANEG_STATE_UNKNOWN:
5189 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5190 ap->state = ANEG_STATE_AN_ENABLE;
5193 case ANEG_STATE_AN_ENABLE:
5194 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5195 if (ap->flags & MR_AN_ENABLE) {
5198 ap->ability_match_cfg = 0;
5199 ap->ability_match_count = 0;
5200 ap->ability_match = 0;
5204 ap->state = ANEG_STATE_RESTART_INIT;
5206 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5210 case ANEG_STATE_RESTART_INIT:
5211 ap->link_time = ap->cur_time;
5212 ap->flags &= ~(MR_NP_LOADED);
5214 tw32(MAC_TX_AUTO_NEG, 0);
5215 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5216 tw32_f(MAC_MODE, tp->mac_mode);
5219 ret = ANEG_TIMER_ENAB;
5220 ap->state = ANEG_STATE_RESTART;
5223 case ANEG_STATE_RESTART:
5224 delta = ap->cur_time - ap->link_time;
5225 if (delta > ANEG_STATE_SETTLE_TIME)
5226 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5228 ret = ANEG_TIMER_ENAB;
5231 case ANEG_STATE_DISABLE_LINK_OK:
5235 case ANEG_STATE_ABILITY_DETECT_INIT:
5236 ap->flags &= ~(MR_TOGGLE_TX);
5237 ap->txconfig = ANEG_CFG_FD;
5238 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5239 if (flowctrl & ADVERTISE_1000XPAUSE)
5240 ap->txconfig |= ANEG_CFG_PS1;
5241 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5242 ap->txconfig |= ANEG_CFG_PS2;
5243 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5244 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5245 tw32_f(MAC_MODE, tp->mac_mode);
5248 ap->state = ANEG_STATE_ABILITY_DETECT;
5251 case ANEG_STATE_ABILITY_DETECT:
5252 if (ap->ability_match != 0 && ap->rxconfig != 0)
5253 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5256 case ANEG_STATE_ACK_DETECT_INIT:
5257 ap->txconfig |= ANEG_CFG_ACK;
5258 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5259 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5260 tw32_f(MAC_MODE, tp->mac_mode);
5263 ap->state = ANEG_STATE_ACK_DETECT;
5266 case ANEG_STATE_ACK_DETECT:
5267 if (ap->ack_match != 0) {
5268 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5269 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5270 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5272 ap->state = ANEG_STATE_AN_ENABLE;
5274 } else if (ap->ability_match != 0 &&
5275 ap->rxconfig == 0) {
5276 ap->state = ANEG_STATE_AN_ENABLE;
5280 case ANEG_STATE_COMPLETE_ACK_INIT:
5281 if (ap->rxconfig & ANEG_CFG_INVAL) {
5285 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5286 MR_LP_ADV_HALF_DUPLEX |
5287 MR_LP_ADV_SYM_PAUSE |
5288 MR_LP_ADV_ASYM_PAUSE |
5289 MR_LP_ADV_REMOTE_FAULT1 |
5290 MR_LP_ADV_REMOTE_FAULT2 |
5291 MR_LP_ADV_NEXT_PAGE |
5294 if (ap->rxconfig & ANEG_CFG_FD)
5295 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5296 if (ap->rxconfig & ANEG_CFG_HD)
5297 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5298 if (ap->rxconfig & ANEG_CFG_PS1)
5299 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5300 if (ap->rxconfig & ANEG_CFG_PS2)
5301 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5302 if (ap->rxconfig & ANEG_CFG_RF1)
5303 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5304 if (ap->rxconfig & ANEG_CFG_RF2)
5305 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5306 if (ap->rxconfig & ANEG_CFG_NP)
5307 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5309 ap->link_time = ap->cur_time;
5311 ap->flags ^= (MR_TOGGLE_TX);
5312 if (ap->rxconfig & 0x0008)
5313 ap->flags |= MR_TOGGLE_RX;
5314 if (ap->rxconfig & ANEG_CFG_NP)
5315 ap->flags |= MR_NP_RX;
5316 ap->flags |= MR_PAGE_RX;
5318 ap->state = ANEG_STATE_COMPLETE_ACK;
5319 ret = ANEG_TIMER_ENAB;
5322 case ANEG_STATE_COMPLETE_ACK:
5323 if (ap->ability_match != 0 &&
5324 ap->rxconfig == 0) {
5325 ap->state = ANEG_STATE_AN_ENABLE;
5328 delta = ap->cur_time - ap->link_time;
5329 if (delta > ANEG_STATE_SETTLE_TIME) {
5330 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5331 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5333 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5334 !(ap->flags & MR_NP_RX)) {
5335 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 case ANEG_STATE_IDLE_DETECT_INIT:
5344 ap->link_time = ap->cur_time;
5345 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5346 tw32_f(MAC_MODE, tp->mac_mode);
5349 ap->state = ANEG_STATE_IDLE_DETECT;
5350 ret = ANEG_TIMER_ENAB;
5353 case ANEG_STATE_IDLE_DETECT:
5354 if (ap->ability_match != 0 &&
5355 ap->rxconfig == 0) {
5356 ap->state = ANEG_STATE_AN_ENABLE;
5359 delta = ap->cur_time - ap->link_time;
5360 if (delta > ANEG_STATE_SETTLE_TIME) {
5361 /* XXX another gem from the Broadcom driver :( */
5362 ap->state = ANEG_STATE_LINK_OK;
5366 case ANEG_STATE_LINK_OK:
5367 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5371 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5372 /* ??? unimplemented */
5375 case ANEG_STATE_NEXT_PAGE_WAIT:
5376 /* ??? unimplemented */
5387 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5390 struct tg3_fiber_aneginfo aninfo;
5391 int status = ANEG_FAILED;
5395 tw32_f(MAC_TX_AUTO_NEG, 0);
5397 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5398 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5401 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5404 memset(&aninfo, 0, sizeof(aninfo));
5405 aninfo.flags |= MR_AN_ENABLE;
5406 aninfo.state = ANEG_STATE_UNKNOWN;
5407 aninfo.cur_time = 0;
5409 while (++tick < 195000) {
5410 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5411 if (status == ANEG_DONE || status == ANEG_FAILED)
5417 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5418 tw32_f(MAC_MODE, tp->mac_mode);
5421 *txflags = aninfo.txconfig;
5422 *rxflags = aninfo.flags;
5424 if (status == ANEG_DONE &&
5425 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5426 MR_LP_ADV_FULL_DUPLEX)))
5432 static void tg3_init_bcm8002(struct tg3 *tp)
5434 u32 mac_status = tr32(MAC_STATUS);
5437 /* Reset when initting first time or we have a link. */
5438 if (tg3_flag(tp, INIT_COMPLETE) &&
5439 !(mac_status & MAC_STATUS_PCS_SYNCED))
5442 /* Set PLL lock range. */
5443 tg3_writephy(tp, 0x16, 0x8007);
5446 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5448 /* Wait for reset to complete. */
5449 /* XXX schedule_timeout() ... */
5450 for (i = 0; i < 500; i++)
5453 /* Config mode; select PMA/Ch 1 regs. */
5454 tg3_writephy(tp, 0x10, 0x8411);
5456 /* Enable auto-lock and comdet, select txclk for tx. */
5457 tg3_writephy(tp, 0x11, 0x0a10);
5459 tg3_writephy(tp, 0x18, 0x00a0);
5460 tg3_writephy(tp, 0x16, 0x41ff);
5462 /* Assert and deassert POR. */
5463 tg3_writephy(tp, 0x13, 0x0400);
5465 tg3_writephy(tp, 0x13, 0x0000);
5467 tg3_writephy(tp, 0x11, 0x0a50);
5469 tg3_writephy(tp, 0x11, 0x0a10);
5471 /* Wait for signal to stabilize */
5472 /* XXX schedule_timeout() ... */
5473 for (i = 0; i < 15000; i++)
5476 /* Deselect the channel register so we can read the PHYID
5479 tg3_writephy(tp, 0x10, 0x8011);
5482 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5485 bool current_link_up;
5486 u32 sg_dig_ctrl, sg_dig_status;
5487 u32 serdes_cfg, expected_sg_dig_ctrl;
5488 int workaround, port_a;
5491 expected_sg_dig_ctrl = 0;
5494 current_link_up = false;
5496 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5497 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5499 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5502 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5503 /* preserve bits 20-23 for voltage regulator */
5504 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5507 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5509 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5510 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5512 u32 val = serdes_cfg;
5518 tw32_f(MAC_SERDES_CFG, val);
5521 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5523 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5524 tg3_setup_flow_control(tp, 0, 0);
5525 current_link_up = true;
5530 /* Want auto-negotiation. */
5531 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5533 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5534 if (flowctrl & ADVERTISE_1000XPAUSE)
5535 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5536 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5537 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5539 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5540 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5541 tp->serdes_counter &&
5542 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5543 MAC_STATUS_RCVD_CFG)) ==
5544 MAC_STATUS_PCS_SYNCED)) {
5545 tp->serdes_counter--;
5546 current_link_up = true;
5551 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5552 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5554 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5556 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5557 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5558 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5559 MAC_STATUS_SIGNAL_DET)) {
5560 sg_dig_status = tr32(SG_DIG_STATUS);
5561 mac_status = tr32(MAC_STATUS);
5563 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5564 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5565 u32 local_adv = 0, remote_adv = 0;
5567 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5568 local_adv |= ADVERTISE_1000XPAUSE;
5569 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5570 local_adv |= ADVERTISE_1000XPSE_ASYM;
5572 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5573 remote_adv |= LPA_1000XPAUSE;
5574 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5575 remote_adv |= LPA_1000XPAUSE_ASYM;
5577 tp->link_config.rmt_adv =
5578 mii_adv_to_ethtool_adv_x(remote_adv);
5580 tg3_setup_flow_control(tp, local_adv, remote_adv);
5581 current_link_up = true;
5582 tp->serdes_counter = 0;
5583 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5584 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5585 if (tp->serdes_counter)
5586 tp->serdes_counter--;
5589 u32 val = serdes_cfg;
5596 tw32_f(MAC_SERDES_CFG, val);
5599 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5602 /* Link parallel detection - link is up */
5603 /* only if we have PCS_SYNC and not */
5604 /* receiving config code words */
5605 mac_status = tr32(MAC_STATUS);
5606 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5607 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5608 tg3_setup_flow_control(tp, 0, 0);
5609 current_link_up = true;
5611 TG3_PHYFLG_PARALLEL_DETECT;
5612 tp->serdes_counter =
5613 SERDES_PARALLEL_DET_TIMEOUT;
5615 goto restart_autoneg;
5619 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5620 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5624 return current_link_up;
5627 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5629 bool current_link_up = false;
5631 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5634 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5635 u32 txflags, rxflags;
5638 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5639 u32 local_adv = 0, remote_adv = 0;
5641 if (txflags & ANEG_CFG_PS1)
5642 local_adv |= ADVERTISE_1000XPAUSE;
5643 if (txflags & ANEG_CFG_PS2)
5644 local_adv |= ADVERTISE_1000XPSE_ASYM;
5646 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5647 remote_adv |= LPA_1000XPAUSE;
5648 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5649 remote_adv |= LPA_1000XPAUSE_ASYM;
5651 tp->link_config.rmt_adv =
5652 mii_adv_to_ethtool_adv_x(remote_adv);
5654 tg3_setup_flow_control(tp, local_adv, remote_adv);
5656 current_link_up = true;
5658 for (i = 0; i < 30; i++) {
5661 (MAC_STATUS_SYNC_CHANGED |
5662 MAC_STATUS_CFG_CHANGED));
5664 if ((tr32(MAC_STATUS) &
5665 (MAC_STATUS_SYNC_CHANGED |
5666 MAC_STATUS_CFG_CHANGED)) == 0)
5670 mac_status = tr32(MAC_STATUS);
5671 if (!current_link_up &&
5672 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5673 !(mac_status & MAC_STATUS_RCVD_CFG))
5674 current_link_up = true;
5676 tg3_setup_flow_control(tp, 0, 0);
5678 /* Forcing 1000FD link up. */
5679 current_link_up = true;
5681 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5684 tw32_f(MAC_MODE, tp->mac_mode);
5689 return current_link_up;
5692 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5695 u16 orig_active_speed;
5696 u8 orig_active_duplex;
5698 bool current_link_up;
5701 orig_pause_cfg = tp->link_config.active_flowctrl;
5702 orig_active_speed = tp->link_config.active_speed;
5703 orig_active_duplex = tp->link_config.active_duplex;
5705 if (!tg3_flag(tp, HW_AUTONEG) &&
5707 tg3_flag(tp, INIT_COMPLETE)) {
5708 mac_status = tr32(MAC_STATUS);
5709 mac_status &= (MAC_STATUS_PCS_SYNCED |
5710 MAC_STATUS_SIGNAL_DET |
5711 MAC_STATUS_CFG_CHANGED |
5712 MAC_STATUS_RCVD_CFG);
5713 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5714 MAC_STATUS_SIGNAL_DET)) {
5715 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5716 MAC_STATUS_CFG_CHANGED));
5721 tw32_f(MAC_TX_AUTO_NEG, 0);
5723 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5724 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5725 tw32_f(MAC_MODE, tp->mac_mode);
5728 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5729 tg3_init_bcm8002(tp);
5731 /* Enable link change event even when serdes polling. */
5732 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5735 current_link_up = false;
5736 tp->link_config.rmt_adv = 0;
5737 mac_status = tr32(MAC_STATUS);
5739 if (tg3_flag(tp, HW_AUTONEG))
5740 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5742 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5744 tp->napi[0].hw_status->status =
5745 (SD_STATUS_UPDATED |
5746 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5748 for (i = 0; i < 100; i++) {
5749 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5750 MAC_STATUS_CFG_CHANGED));
5752 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5753 MAC_STATUS_CFG_CHANGED |
5754 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5758 mac_status = tr32(MAC_STATUS);
5759 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5760 current_link_up = false;
5761 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5762 tp->serdes_counter == 0) {
5763 tw32_f(MAC_MODE, (tp->mac_mode |
5764 MAC_MODE_SEND_CONFIGS));
5766 tw32_f(MAC_MODE, tp->mac_mode);
5770 if (current_link_up) {
5771 tp->link_config.active_speed = SPEED_1000;
5772 tp->link_config.active_duplex = DUPLEX_FULL;
5773 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5774 LED_CTRL_LNKLED_OVERRIDE |
5775 LED_CTRL_1000MBPS_ON));
5777 tp->link_config.active_speed = SPEED_UNKNOWN;
5778 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5779 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5780 LED_CTRL_LNKLED_OVERRIDE |
5781 LED_CTRL_TRAFFIC_OVERRIDE));
5784 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5785 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5786 if (orig_pause_cfg != now_pause_cfg ||
5787 orig_active_speed != tp->link_config.active_speed ||
5788 orig_active_duplex != tp->link_config.active_duplex)
5789 tg3_link_report(tp);
5795 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5799 u16 current_speed = SPEED_UNKNOWN;
5800 u8 current_duplex = DUPLEX_UNKNOWN;
5801 bool current_link_up = false;
5802 u32 local_adv, remote_adv, sgsr;
5804 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5805 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5806 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5807 (sgsr & SERDES_TG3_SGMII_MODE)) {
5812 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5814 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5815 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5817 current_link_up = true;
5818 if (sgsr & SERDES_TG3_SPEED_1000) {
5819 current_speed = SPEED_1000;
5820 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5821 } else if (sgsr & SERDES_TG3_SPEED_100) {
5822 current_speed = SPEED_100;
5823 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5825 current_speed = SPEED_10;
5826 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5829 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5830 current_duplex = DUPLEX_FULL;
5832 current_duplex = DUPLEX_HALF;
5835 tw32_f(MAC_MODE, tp->mac_mode);
5838 tg3_clear_mac_status(tp);
5840 goto fiber_setup_done;
5843 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5844 tw32_f(MAC_MODE, tp->mac_mode);
5847 tg3_clear_mac_status(tp);
5852 tp->link_config.rmt_adv = 0;
5854 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5855 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5856 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5857 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5858 bmsr |= BMSR_LSTATUS;
5860 bmsr &= ~BMSR_LSTATUS;
5863 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5865 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5866 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5867 /* do nothing, just check for link up at the end */
5868 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5871 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5872 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5873 ADVERTISE_1000XPAUSE |
5874 ADVERTISE_1000XPSE_ASYM |
5877 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5878 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5880 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5881 tg3_writephy(tp, MII_ADVERTISE, newadv);
5882 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5883 tg3_writephy(tp, MII_BMCR, bmcr);
5885 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5886 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5887 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5894 bmcr &= ~BMCR_SPEED1000;
5895 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5897 if (tp->link_config.duplex == DUPLEX_FULL)
5898 new_bmcr |= BMCR_FULLDPLX;
5900 if (new_bmcr != bmcr) {
5901 /* BMCR_SPEED1000 is a reserved bit that needs
5902 * to be set on write.
5904 new_bmcr |= BMCR_SPEED1000;
5906 /* Force a linkdown */
5910 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5911 adv &= ~(ADVERTISE_1000XFULL |
5912 ADVERTISE_1000XHALF |
5914 tg3_writephy(tp, MII_ADVERTISE, adv);
5915 tg3_writephy(tp, MII_BMCR, bmcr |
5919 tg3_carrier_off(tp);
5921 tg3_writephy(tp, MII_BMCR, new_bmcr);
5923 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5924 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5925 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5926 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5927 bmsr |= BMSR_LSTATUS;
5929 bmsr &= ~BMSR_LSTATUS;
5931 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5935 if (bmsr & BMSR_LSTATUS) {
5936 current_speed = SPEED_1000;
5937 current_link_up = true;
5938 if (bmcr & BMCR_FULLDPLX)
5939 current_duplex = DUPLEX_FULL;
5941 current_duplex = DUPLEX_HALF;
5946 if (bmcr & BMCR_ANENABLE) {
5949 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5950 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5951 common = local_adv & remote_adv;
5952 if (common & (ADVERTISE_1000XHALF |
5953 ADVERTISE_1000XFULL)) {
5954 if (common & ADVERTISE_1000XFULL)
5955 current_duplex = DUPLEX_FULL;
5957 current_duplex = DUPLEX_HALF;
5959 tp->link_config.rmt_adv =
5960 mii_adv_to_ethtool_adv_x(remote_adv);
5961 } else if (!tg3_flag(tp, 5780_CLASS)) {
5962 /* Link is up via parallel detect */
5964 current_link_up = false;
5970 if (current_link_up && current_duplex == DUPLEX_FULL)
5971 tg3_setup_flow_control(tp, local_adv, remote_adv);
5973 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5974 if (tp->link_config.active_duplex == DUPLEX_HALF)
5975 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5977 tw32_f(MAC_MODE, tp->mac_mode);
5980 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5982 tp->link_config.active_speed = current_speed;
5983 tp->link_config.active_duplex = current_duplex;
5985 tg3_test_and_report_link_chg(tp, current_link_up);
5989 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5991 if (tp->serdes_counter) {
5992 /* Give autoneg time to complete. */
5993 tp->serdes_counter--;
5998 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6001 tg3_readphy(tp, MII_BMCR, &bmcr);
6002 if (bmcr & BMCR_ANENABLE) {
6005 /* Select shadow register 0x1f */
6006 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6007 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6009 /* Select expansion interrupt status register */
6010 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6011 MII_TG3_DSP_EXP1_INT_STAT);
6012 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6013 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6015 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6016 /* We have signal detect and not receiving
6017 * config code words, link is up by parallel
6021 bmcr &= ~BMCR_ANENABLE;
6022 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6023 tg3_writephy(tp, MII_BMCR, bmcr);
6024 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6027 } else if (tp->link_up &&
6028 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6029 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6032 /* Select expansion interrupt status register */
6033 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6034 MII_TG3_DSP_EXP1_INT_STAT);
6035 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6039 /* Config code words received, turn on autoneg. */
6040 tg3_readphy(tp, MII_BMCR, &bmcr);
6041 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6043 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6049 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6054 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6055 err = tg3_setup_fiber_phy(tp, force_reset);
6056 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6057 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6059 err = tg3_setup_copper_phy(tp, force_reset);
6061 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6064 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6065 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6067 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6072 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6073 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6074 tw32(GRC_MISC_CFG, val);
6077 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6078 (6 << TX_LENGTHS_IPG_SHIFT);
6079 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6080 tg3_asic_rev(tp) == ASIC_REV_5762)
6081 val |= tr32(MAC_TX_LENGTHS) &
6082 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6083 TX_LENGTHS_CNT_DWN_VAL_MSK);
6085 if (tp->link_config.active_speed == SPEED_1000 &&
6086 tp->link_config.active_duplex == DUPLEX_HALF)
6087 tw32(MAC_TX_LENGTHS, val |
6088 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6090 tw32(MAC_TX_LENGTHS, val |
6091 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6093 if (!tg3_flag(tp, 5705_PLUS)) {
6095 tw32(HOSTCC_STAT_COAL_TICKS,
6096 tp->coal.stats_block_coalesce_usecs);
6098 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6102 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6103 val = tr32(PCIE_PWR_MGMT_THRESH);
6105 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6108 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6109 tw32(PCIE_PWR_MGMT_THRESH, val);
6115 /* tp->lock must be held */
6116 static u64 tg3_refclk_read(struct tg3 *tp)
6118 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6119 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6122 /* tp->lock must be held */
6123 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6125 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6127 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6128 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6129 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6130 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6133 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6134 static inline void tg3_full_unlock(struct tg3 *tp);
6135 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6137 struct tg3 *tp = netdev_priv(dev);
6139 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6140 SOF_TIMESTAMPING_RX_SOFTWARE |
6141 SOF_TIMESTAMPING_SOFTWARE;
6143 if (tg3_flag(tp, PTP_CAPABLE)) {
6144 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6145 SOF_TIMESTAMPING_RX_HARDWARE |
6146 SOF_TIMESTAMPING_RAW_HARDWARE;
6150 info->phc_index = ptp_clock_index(tp->ptp_clock);
6152 info->phc_index = -1;
6154 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6156 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6157 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6158 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6159 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6163 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6165 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6166 bool neg_adj = false;
6174 /* Frequency adjustment is performed using hardware with a 24 bit
6175 * accumulator and a programmable correction value. On each clk, the
6176 * correction value gets added to the accumulator and when it
6177 * overflows, the time counter is incremented/decremented.
6179 * So conversion from ppb to correction value is
6180 * ppb * (1 << 24) / 1000000000
6182 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6183 TG3_EAV_REF_CLK_CORRECT_MASK;
6185 tg3_full_lock(tp, 0);
6188 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6189 TG3_EAV_REF_CLK_CORRECT_EN |
6190 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6192 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6194 tg3_full_unlock(tp);
6199 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6201 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6203 tg3_full_lock(tp, 0);
6204 tp->ptp_adjust += delta;
6205 tg3_full_unlock(tp);
6210 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6214 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6216 tg3_full_lock(tp, 0);
6217 ns = tg3_refclk_read(tp);
6218 ns += tp->ptp_adjust;
6219 tg3_full_unlock(tp);
6221 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6222 ts->tv_nsec = remainder;
6227 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6228 const struct timespec *ts)
6231 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6233 ns = timespec_to_ns(ts);
6235 tg3_full_lock(tp, 0);
6236 tg3_refclk_write(tp, ns);
6238 tg3_full_unlock(tp);
6243 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6244 struct ptp_clock_request *rq, int on)
6246 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6251 case PTP_CLK_REQ_PEROUT:
6252 if (rq->perout.index != 0)
6255 tg3_full_lock(tp, 0);
6256 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6257 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6262 nsec = rq->perout.start.sec * 1000000000ULL +
6263 rq->perout.start.nsec;
6265 if (rq->perout.period.sec || rq->perout.period.nsec) {
6266 netdev_warn(tp->dev,
6267 "Device supports only a one-shot timesync output, period must be 0\n");
6272 if (nsec & (1ULL << 63)) {
6273 netdev_warn(tp->dev,
6274 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6279 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6280 tw32(TG3_EAV_WATCHDOG0_MSB,
6281 TG3_EAV_WATCHDOG0_EN |
6282 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6284 tw32(TG3_EAV_REF_CLCK_CTL,
6285 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6287 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6288 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6292 tg3_full_unlock(tp);
6302 static const struct ptp_clock_info tg3_ptp_caps = {
6303 .owner = THIS_MODULE,
6304 .name = "tg3 clock",
6305 .max_adj = 250000000,
6310 .adjfreq = tg3_ptp_adjfreq,
6311 .adjtime = tg3_ptp_adjtime,
6312 .gettime = tg3_ptp_gettime,
6313 .settime = tg3_ptp_settime,
6314 .enable = tg3_ptp_enable,
6317 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6318 struct skb_shared_hwtstamps *timestamp)
6320 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6321 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6325 /* tp->lock must be held */
6326 static void tg3_ptp_init(struct tg3 *tp)
6328 if (!tg3_flag(tp, PTP_CAPABLE))
6331 /* Initialize the hardware clock to the system time. */
6332 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6334 tp->ptp_info = tg3_ptp_caps;
6337 /* tp->lock must be held */
6338 static void tg3_ptp_resume(struct tg3 *tp)
6340 if (!tg3_flag(tp, PTP_CAPABLE))
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6347 static void tg3_ptp_fini(struct tg3 *tp)
6349 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6352 ptp_clock_unregister(tp->ptp_clock);
6353 tp->ptp_clock = NULL;
6357 static inline int tg3_irq_sync(struct tg3 *tp)
6359 return tp->irq_sync;
6362 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6366 dst = (u32 *)((u8 *)dst + off);
6367 for (i = 0; i < len; i += sizeof(u32))
6368 *dst++ = tr32(off + i);
6371 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6373 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6374 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6375 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6376 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6377 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6378 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6379 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6380 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6381 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6382 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6383 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6384 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6385 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6386 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6387 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6388 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6389 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6390 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6391 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6393 if (tg3_flag(tp, SUPPORT_MSIX))
6394 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6396 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6397 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6398 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6399 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6400 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6401 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6402 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6403 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6405 if (!tg3_flag(tp, 5705_PLUS)) {
6406 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6407 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6408 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6411 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6412 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6413 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6414 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6415 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6417 if (tg3_flag(tp, NVRAM))
6418 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6421 static void tg3_dump_state(struct tg3 *tp)
6426 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6430 if (tg3_flag(tp, PCI_EXPRESS)) {
6431 /* Read up to but not including private PCI registers */
6432 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6433 regs[i / sizeof(u32)] = tr32(i);
6435 tg3_dump_legacy_regs(tp, regs);
6437 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6438 if (!regs[i + 0] && !regs[i + 1] &&
6439 !regs[i + 2] && !regs[i + 3])
6442 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6444 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6449 for (i = 0; i < tp->irq_cnt; i++) {
6450 struct tg3_napi *tnapi = &tp->napi[i];
6452 /* SW status block */
6454 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6456 tnapi->hw_status->status,
6457 tnapi->hw_status->status_tag,
6458 tnapi->hw_status->rx_jumbo_consumer,
6459 tnapi->hw_status->rx_consumer,
6460 tnapi->hw_status->rx_mini_consumer,
6461 tnapi->hw_status->idx[0].rx_producer,
6462 tnapi->hw_status->idx[0].tx_consumer);
6465 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6467 tnapi->last_tag, tnapi->last_irq_tag,
6468 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6470 tnapi->prodring.rx_std_prod_idx,
6471 tnapi->prodring.rx_std_cons_idx,
6472 tnapi->prodring.rx_jmb_prod_idx,
6473 tnapi->prodring.rx_jmb_cons_idx);
6477 /* This is called whenever we suspect that the system chipset is re-
6478 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6479 * is bogus tx completions. We try to recover by setting the
6480 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6483 static void tg3_tx_recover(struct tg3 *tp)
6485 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6486 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6488 netdev_warn(tp->dev,
6489 "The system may be re-ordering memory-mapped I/O "
6490 "cycles to the network device, attempting to recover. "
6491 "Please report the problem to the driver maintainer "
6492 "and include system chipset information.\n");
6494 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6497 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6499 /* Tell compiler to fetch tx indices from memory. */
6501 return tnapi->tx_pending -
6502 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6505 /* Tigon3 never reports partial packet sends. So we do not
6506 * need special logic to handle SKBs that have not had all
6507 * of their frags sent yet, like SunGEM does.
6509 static void tg3_tx(struct tg3_napi *tnapi)
6511 struct tg3 *tp = tnapi->tp;
6512 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6513 u32 sw_idx = tnapi->tx_cons;
6514 struct netdev_queue *txq;
6515 int index = tnapi - tp->napi;
6516 unsigned int pkts_compl = 0, bytes_compl = 0;
6518 if (tg3_flag(tp, ENABLE_TSS))
6521 txq = netdev_get_tx_queue(tp->dev, index);
6523 while (sw_idx != hw_idx) {
6524 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6525 struct sk_buff *skb = ri->skb;
6528 if (unlikely(skb == NULL)) {
6533 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6534 struct skb_shared_hwtstamps timestamp;
6535 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6536 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6538 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6540 skb_tstamp_tx(skb, ×tamp);
6543 pci_unmap_single(tp->pdev,
6544 dma_unmap_addr(ri, mapping),
6550 while (ri->fragmented) {
6551 ri->fragmented = false;
6552 sw_idx = NEXT_TX(sw_idx);
6553 ri = &tnapi->tx_buffers[sw_idx];
6556 sw_idx = NEXT_TX(sw_idx);
6558 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6559 ri = &tnapi->tx_buffers[sw_idx];
6560 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6563 pci_unmap_page(tp->pdev,
6564 dma_unmap_addr(ri, mapping),
6565 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6568 while (ri->fragmented) {
6569 ri->fragmented = false;
6570 sw_idx = NEXT_TX(sw_idx);
6571 ri = &tnapi->tx_buffers[sw_idx];
6574 sw_idx = NEXT_TX(sw_idx);
6578 bytes_compl += skb->len;
6582 if (unlikely(tx_bug)) {
6588 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6590 tnapi->tx_cons = sw_idx;
6592 /* Need to make the tx_cons update visible to tg3_start_xmit()
6593 * before checking for netif_queue_stopped(). Without the
6594 * memory barrier, there is a small possibility that tg3_start_xmit()
6595 * will miss it and cause the queue to be stopped forever.
6599 if (unlikely(netif_tx_queue_stopped(txq) &&
6600 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6601 __netif_tx_lock(txq, smp_processor_id());
6602 if (netif_tx_queue_stopped(txq) &&
6603 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6604 netif_tx_wake_queue(txq);
6605 __netif_tx_unlock(txq);
6609 static void tg3_frag_free(bool is_frag, void *data)
6612 put_page(virt_to_head_page(data));
6617 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6619 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6620 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6625 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6626 map_sz, PCI_DMA_FROMDEVICE);
6627 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6632 /* Returns size of skb allocated or < 0 on error.
6634 * We only need to fill in the address because the other members
6635 * of the RX descriptor are invariant, see tg3_init_rings.
6637 * Note the purposeful assymetry of cpu vs. chip accesses. For
6638 * posting buffers we only dirty the first cache line of the RX
6639 * descriptor (containing the address). Whereas for the RX status
6640 * buffers the cpu only reads the last cacheline of the RX descriptor
6641 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6643 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6644 u32 opaque_key, u32 dest_idx_unmasked,
6645 unsigned int *frag_size)
6647 struct tg3_rx_buffer_desc *desc;
6648 struct ring_info *map;
6651 int skb_size, data_size, dest_idx;
6653 switch (opaque_key) {
6654 case RXD_OPAQUE_RING_STD:
6655 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6656 desc = &tpr->rx_std[dest_idx];
6657 map = &tpr->rx_std_buffers[dest_idx];
6658 data_size = tp->rx_pkt_map_sz;
6661 case RXD_OPAQUE_RING_JUMBO:
6662 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6663 desc = &tpr->rx_jmb[dest_idx].std;
6664 map = &tpr->rx_jmb_buffers[dest_idx];
6665 data_size = TG3_RX_JMB_MAP_SZ;
6672 /* Do not overwrite any of the map or rp information
6673 * until we are sure we can commit to a new buffer.
6675 * Callers depend upon this behavior and assume that
6676 * we leave everything unchanged if we fail.
6678 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6679 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6680 if (skb_size <= PAGE_SIZE) {
6681 data = netdev_alloc_frag(skb_size);
6682 *frag_size = skb_size;
6684 data = kmalloc(skb_size, GFP_ATOMIC);
6690 mapping = pci_map_single(tp->pdev,
6691 data + TG3_RX_OFFSET(tp),
6693 PCI_DMA_FROMDEVICE);
6694 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6695 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6700 dma_unmap_addr_set(map, mapping, mapping);
6702 desc->addr_hi = ((u64)mapping >> 32);
6703 desc->addr_lo = ((u64)mapping & 0xffffffff);
6708 /* We only need to move over in the address because the other
6709 * members of the RX descriptor are invariant. See notes above
6710 * tg3_alloc_rx_data for full details.
6712 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6713 struct tg3_rx_prodring_set *dpr,
6714 u32 opaque_key, int src_idx,
6715 u32 dest_idx_unmasked)
6717 struct tg3 *tp = tnapi->tp;
6718 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6719 struct ring_info *src_map, *dest_map;
6720 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6723 switch (opaque_key) {
6724 case RXD_OPAQUE_RING_STD:
6725 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6726 dest_desc = &dpr->rx_std[dest_idx];
6727 dest_map = &dpr->rx_std_buffers[dest_idx];
6728 src_desc = &spr->rx_std[src_idx];
6729 src_map = &spr->rx_std_buffers[src_idx];
6732 case RXD_OPAQUE_RING_JUMBO:
6733 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6734 dest_desc = &dpr->rx_jmb[dest_idx].std;
6735 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6736 src_desc = &spr->rx_jmb[src_idx].std;
6737 src_map = &spr->rx_jmb_buffers[src_idx];
6744 dest_map->data = src_map->data;
6745 dma_unmap_addr_set(dest_map, mapping,
6746 dma_unmap_addr(src_map, mapping));
6747 dest_desc->addr_hi = src_desc->addr_hi;
6748 dest_desc->addr_lo = src_desc->addr_lo;
6750 /* Ensure that the update to the skb happens after the physical
6751 * addresses have been transferred to the new BD location.
6755 src_map->data = NULL;
6758 /* The RX ring scheme is composed of multiple rings which post fresh
6759 * buffers to the chip, and one special ring the chip uses to report
6760 * status back to the host.
6762 * The special ring reports the status of received packets to the
6763 * host. The chip does not write into the original descriptor the
6764 * RX buffer was obtained from. The chip simply takes the original
6765 * descriptor as provided by the host, updates the status and length
6766 * field, then writes this into the next status ring entry.
6768 * Each ring the host uses to post buffers to the chip is described
6769 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6770 * it is first placed into the on-chip ram. When the packet's length
6771 * is known, it walks down the TG3_BDINFO entries to select the ring.
6772 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6773 * which is within the range of the new packet's length is chosen.
6775 * The "separate ring for rx status" scheme may sound queer, but it makes
6776 * sense from a cache coherency perspective. If only the host writes
6777 * to the buffer post rings, and only the chip writes to the rx status
6778 * rings, then cache lines never move beyond shared-modified state.
6779 * If both the host and chip were to write into the same ring, cache line
6780 * eviction could occur since both entities want it in an exclusive state.
6782 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6784 struct tg3 *tp = tnapi->tp;
6785 u32 work_mask, rx_std_posted = 0;
6786 u32 std_prod_idx, jmb_prod_idx;
6787 u32 sw_idx = tnapi->rx_rcb_ptr;
6790 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6792 hw_idx = *(tnapi->rx_rcb_prod_idx);
6794 * We need to order the read of hw_idx and the read of
6795 * the opaque cookie.
6800 std_prod_idx = tpr->rx_std_prod_idx;
6801 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6802 while (sw_idx != hw_idx && budget > 0) {
6803 struct ring_info *ri;
6804 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6806 struct sk_buff *skb;
6807 dma_addr_t dma_addr;
6808 u32 opaque_key, desc_idx, *post_ptr;
6812 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6813 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6814 if (opaque_key == RXD_OPAQUE_RING_STD) {
6815 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6816 dma_addr = dma_unmap_addr(ri, mapping);
6818 post_ptr = &std_prod_idx;
6820 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6821 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6822 dma_addr = dma_unmap_addr(ri, mapping);
6824 post_ptr = &jmb_prod_idx;
6826 goto next_pkt_nopost;
6828 work_mask |= opaque_key;
6830 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
6831 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
6833 tg3_recycle_rx(tnapi, tpr, opaque_key,
6834 desc_idx, *post_ptr);
6836 /* Other statistics kept track of by card. */
6841 prefetch(data + TG3_RX_OFFSET(tp));
6842 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6845 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6846 RXD_FLAG_PTPSTAT_PTPV1 ||
6847 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6848 RXD_FLAG_PTPSTAT_PTPV2) {
6849 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6850 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6853 if (len > TG3_RX_COPY_THRESH(tp)) {
6855 unsigned int frag_size;
6857 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6858 *post_ptr, &frag_size);
6862 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6863 PCI_DMA_FROMDEVICE);
6865 /* Ensure that the update to the data happens
6866 * after the usage of the old DMA mapping.
6872 skb = build_skb(data, frag_size);
6874 tg3_frag_free(frag_size != 0, data);
6875 goto drop_it_no_recycle;
6877 skb_reserve(skb, TG3_RX_OFFSET(tp));
6879 tg3_recycle_rx(tnapi, tpr, opaque_key,
6880 desc_idx, *post_ptr);
6882 skb = netdev_alloc_skb(tp->dev,
6883 len + TG3_RAW_IP_ALIGN);
6885 goto drop_it_no_recycle;
6887 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6888 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6890 data + TG3_RX_OFFSET(tp),
6892 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6897 tg3_hwclock_to_timestamp(tp, tstamp,
6898 skb_hwtstamps(skb));
6900 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6901 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6902 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6903 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6904 skb->ip_summed = CHECKSUM_UNNECESSARY;
6906 skb_checksum_none_assert(skb);
6908 skb->protocol = eth_type_trans(skb, tp->dev);
6910 if (len > (tp->dev->mtu + ETH_HLEN) &&
6911 skb->protocol != htons(ETH_P_8021Q)) {
6913 goto drop_it_no_recycle;
6916 if (desc->type_flags & RXD_FLAG_VLAN &&
6917 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6918 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6919 desc->err_vlan & RXD_VLAN_MASK);
6921 napi_gro_receive(&tnapi->napi, skb);
6929 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6930 tpr->rx_std_prod_idx = std_prod_idx &
6931 tp->rx_std_ring_mask;
6932 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6933 tpr->rx_std_prod_idx);
6934 work_mask &= ~RXD_OPAQUE_RING_STD;
6939 sw_idx &= tp->rx_ret_ring_mask;
6941 /* Refresh hw_idx to see if there is new work */
6942 if (sw_idx == hw_idx) {
6943 hw_idx = *(tnapi->rx_rcb_prod_idx);
6948 /* ACK the status ring. */
6949 tnapi->rx_rcb_ptr = sw_idx;
6950 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6952 /* Refill RX ring(s). */
6953 if (!tg3_flag(tp, ENABLE_RSS)) {
6954 /* Sync BD data before updating mailbox */
6957 if (work_mask & RXD_OPAQUE_RING_STD) {
6958 tpr->rx_std_prod_idx = std_prod_idx &
6959 tp->rx_std_ring_mask;
6960 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6961 tpr->rx_std_prod_idx);
6963 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6964 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6965 tp->rx_jmb_ring_mask;
6966 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6967 tpr->rx_jmb_prod_idx);
6970 } else if (work_mask) {
6971 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6972 * updated before the producer indices can be updated.
6976 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6977 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6979 if (tnapi != &tp->napi[1]) {
6980 tp->rx_refill = true;
6981 napi_schedule(&tp->napi[1].napi);
6988 static void tg3_poll_link(struct tg3 *tp)
6990 /* handle link change and other phy events */
6991 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
6992 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
6994 if (sblk->status & SD_STATUS_LINK_CHG) {
6995 sblk->status = SD_STATUS_UPDATED |
6996 (sblk->status & ~SD_STATUS_LINK_CHG);
6997 spin_lock(&tp->lock);
6998 if (tg3_flag(tp, USE_PHYLIB)) {
7000 (MAC_STATUS_SYNC_CHANGED |
7001 MAC_STATUS_CFG_CHANGED |
7002 MAC_STATUS_MI_COMPLETION |
7003 MAC_STATUS_LNKSTATE_CHANGED));
7006 tg3_setup_phy(tp, false);
7007 spin_unlock(&tp->lock);
7012 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7013 struct tg3_rx_prodring_set *dpr,
7014 struct tg3_rx_prodring_set *spr)
7016 u32 si, di, cpycnt, src_prod_idx;
7020 src_prod_idx = spr->rx_std_prod_idx;
7022 /* Make sure updates to the rx_std_buffers[] entries and the
7023 * standard producer index are seen in the correct order.
7027 if (spr->rx_std_cons_idx == src_prod_idx)
7030 if (spr->rx_std_cons_idx < src_prod_idx)
7031 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7033 cpycnt = tp->rx_std_ring_mask + 1 -
7034 spr->rx_std_cons_idx;
7036 cpycnt = min(cpycnt,
7037 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7039 si = spr->rx_std_cons_idx;
7040 di = dpr->rx_std_prod_idx;
7042 for (i = di; i < di + cpycnt; i++) {
7043 if (dpr->rx_std_buffers[i].data) {
7053 /* Ensure that updates to the rx_std_buffers ring and the
7054 * shadowed hardware producer ring from tg3_recycle_skb() are
7055 * ordered correctly WRT the skb check above.
7059 memcpy(&dpr->rx_std_buffers[di],
7060 &spr->rx_std_buffers[si],
7061 cpycnt * sizeof(struct ring_info));
7063 for (i = 0; i < cpycnt; i++, di++, si++) {
7064 struct tg3_rx_buffer_desc *sbd, *dbd;
7065 sbd = &spr->rx_std[si];
7066 dbd = &dpr->rx_std[di];
7067 dbd->addr_hi = sbd->addr_hi;
7068 dbd->addr_lo = sbd->addr_lo;
7071 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7072 tp->rx_std_ring_mask;
7073 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7074 tp->rx_std_ring_mask;
7078 src_prod_idx = spr->rx_jmb_prod_idx;
7080 /* Make sure updates to the rx_jmb_buffers[] entries and
7081 * the jumbo producer index are seen in the correct order.
7085 if (spr->rx_jmb_cons_idx == src_prod_idx)
7088 if (spr->rx_jmb_cons_idx < src_prod_idx)
7089 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7091 cpycnt = tp->rx_jmb_ring_mask + 1 -
7092 spr->rx_jmb_cons_idx;
7094 cpycnt = min(cpycnt,
7095 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7097 si = spr->rx_jmb_cons_idx;
7098 di = dpr->rx_jmb_prod_idx;
7100 for (i = di; i < di + cpycnt; i++) {
7101 if (dpr->rx_jmb_buffers[i].data) {
7111 /* Ensure that updates to the rx_jmb_buffers ring and the
7112 * shadowed hardware producer ring from tg3_recycle_skb() are
7113 * ordered correctly WRT the skb check above.
7117 memcpy(&dpr->rx_jmb_buffers[di],
7118 &spr->rx_jmb_buffers[si],
7119 cpycnt * sizeof(struct ring_info));
7121 for (i = 0; i < cpycnt; i++, di++, si++) {
7122 struct tg3_rx_buffer_desc *sbd, *dbd;
7123 sbd = &spr->rx_jmb[si].std;
7124 dbd = &dpr->rx_jmb[di].std;
7125 dbd->addr_hi = sbd->addr_hi;
7126 dbd->addr_lo = sbd->addr_lo;
7129 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7130 tp->rx_jmb_ring_mask;
7131 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7132 tp->rx_jmb_ring_mask;
7138 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7140 struct tg3 *tp = tnapi->tp;
7142 /* run TX completion thread */
7143 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7145 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7149 if (!tnapi->rx_rcb_prod_idx)
7152 /* run RX thread, within the bounds set by NAPI.
7153 * All RX "locking" is done by ensuring outside
7154 * code synchronizes with tg3->napi.poll()
7156 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7157 work_done += tg3_rx(tnapi, budget - work_done);
7159 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7160 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7162 u32 std_prod_idx = dpr->rx_std_prod_idx;
7163 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7165 tp->rx_refill = false;
7166 for (i = 1; i <= tp->rxq_cnt; i++)
7167 err |= tg3_rx_prodring_xfer(tp, dpr,
7168 &tp->napi[i].prodring);
7172 if (std_prod_idx != dpr->rx_std_prod_idx)
7173 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7174 dpr->rx_std_prod_idx);
7176 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7177 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7178 dpr->rx_jmb_prod_idx);
7183 tw32_f(HOSTCC_MODE, tp->coal_now);
7189 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7191 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7192 schedule_work(&tp->reset_task);
7195 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7197 cancel_work_sync(&tp->reset_task);
7198 tg3_flag_clear(tp, RESET_TASK_PENDING);
7199 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7202 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7204 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7205 struct tg3 *tp = tnapi->tp;
7207 struct tg3_hw_status *sblk = tnapi->hw_status;
7210 work_done = tg3_poll_work(tnapi, work_done, budget);
7212 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7215 if (unlikely(work_done >= budget))
7218 /* tp->last_tag is used in tg3_int_reenable() below
7219 * to tell the hw how much work has been processed,
7220 * so we must read it before checking for more work.
7222 tnapi->last_tag = sblk->status_tag;
7223 tnapi->last_irq_tag = tnapi->last_tag;
7226 /* check for RX/TX work to do */
7227 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7228 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7230 /* This test here is not race free, but will reduce
7231 * the number of interrupts by looping again.
7233 if (tnapi == &tp->napi[1] && tp->rx_refill)
7236 napi_complete(napi);
7237 /* Reenable interrupts. */
7238 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7240 /* This test here is synchronized by napi_schedule()
7241 * and napi_complete() to close the race condition.
7243 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7244 tw32(HOSTCC_MODE, tp->coalesce_mode |
7245 HOSTCC_MODE_ENABLE |
7256 /* work_done is guaranteed to be less than budget. */
7257 napi_complete(napi);
7258 tg3_reset_task_schedule(tp);
7262 static void tg3_process_error(struct tg3 *tp)
7265 bool real_error = false;
7267 if (tg3_flag(tp, ERROR_PROCESSED))
7270 /* Check Flow Attention register */
7271 val = tr32(HOSTCC_FLOW_ATTN);
7272 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7273 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7277 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7278 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7282 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7283 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7292 tg3_flag_set(tp, ERROR_PROCESSED);
7293 tg3_reset_task_schedule(tp);
7296 static int tg3_poll(struct napi_struct *napi, int budget)
7298 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7299 struct tg3 *tp = tnapi->tp;
7301 struct tg3_hw_status *sblk = tnapi->hw_status;
7304 if (sblk->status & SD_STATUS_ERROR)
7305 tg3_process_error(tp);
7309 work_done = tg3_poll_work(tnapi, work_done, budget);
7311 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7314 if (unlikely(work_done >= budget))
7317 if (tg3_flag(tp, TAGGED_STATUS)) {
7318 /* tp->last_tag is used in tg3_int_reenable() below
7319 * to tell the hw how much work has been processed,
7320 * so we must read it before checking for more work.
7322 tnapi->last_tag = sblk->status_tag;
7323 tnapi->last_irq_tag = tnapi->last_tag;
7326 sblk->status &= ~SD_STATUS_UPDATED;
7328 if (likely(!tg3_has_work(tnapi))) {
7329 napi_complete(napi);
7330 tg3_int_reenable(tnapi);
7338 /* work_done is guaranteed to be less than budget. */
7339 napi_complete(napi);
7340 tg3_reset_task_schedule(tp);
7344 static void tg3_napi_disable(struct tg3 *tp)
7348 for (i = tp->irq_cnt - 1; i >= 0; i--)
7349 napi_disable(&tp->napi[i].napi);
7352 static void tg3_napi_enable(struct tg3 *tp)
7356 for (i = 0; i < tp->irq_cnt; i++)
7357 napi_enable(&tp->napi[i].napi);
7360 static void tg3_napi_init(struct tg3 *tp)
7364 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7365 for (i = 1; i < tp->irq_cnt; i++)
7366 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7369 static void tg3_napi_fini(struct tg3 *tp)
7373 for (i = 0; i < tp->irq_cnt; i++)
7374 netif_napi_del(&tp->napi[i].napi);
7377 static inline void tg3_netif_stop(struct tg3 *tp)
7379 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7380 tg3_napi_disable(tp);
7381 netif_carrier_off(tp->dev);
7382 netif_tx_disable(tp->dev);
7385 /* tp->lock must be held */
7386 static inline void tg3_netif_start(struct tg3 *tp)
7390 /* NOTE: unconditional netif_tx_wake_all_queues is only
7391 * appropriate so long as all callers are assured to
7392 * have free tx slots (such as after tg3_init_hw)
7394 netif_tx_wake_all_queues(tp->dev);
7397 netif_carrier_on(tp->dev);
7399 tg3_napi_enable(tp);
7400 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7401 tg3_enable_ints(tp);
7404 static void tg3_irq_quiesce(struct tg3 *tp)
7408 BUG_ON(tp->irq_sync);
7413 for (i = 0; i < tp->irq_cnt; i++)
7414 synchronize_irq(tp->napi[i].irq_vec);
7417 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7418 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7419 * with as well. Most of the time, this is not necessary except when
7420 * shutting down the device.
7422 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7424 spin_lock_bh(&tp->lock);
7426 tg3_irq_quiesce(tp);
7429 static inline void tg3_full_unlock(struct tg3 *tp)
7431 spin_unlock_bh(&tp->lock);
7434 /* One-shot MSI handler - Chip automatically disables interrupt
7435 * after sending MSI so driver doesn't have to do it.
7437 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7439 struct tg3_napi *tnapi = dev_id;
7440 struct tg3 *tp = tnapi->tp;
7442 prefetch(tnapi->hw_status);
7444 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7446 if (likely(!tg3_irq_sync(tp)))
7447 napi_schedule(&tnapi->napi);
7452 /* MSI ISR - No need to check for interrupt sharing and no need to
7453 * flush status block and interrupt mailbox. PCI ordering rules
7454 * guarantee that MSI will arrive after the status block.
7456 static irqreturn_t tg3_msi(int irq, void *dev_id)
7458 struct tg3_napi *tnapi = dev_id;
7459 struct tg3 *tp = tnapi->tp;
7461 prefetch(tnapi->hw_status);
7463 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7465 * Writing any value to intr-mbox-0 clears PCI INTA# and
7466 * chip-internal interrupt pending events.
7467 * Writing non-zero to intr-mbox-0 additional tells the
7468 * NIC to stop sending us irqs, engaging "in-intr-handler"
7471 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7472 if (likely(!tg3_irq_sync(tp)))
7473 napi_schedule(&tnapi->napi);
7475 return IRQ_RETVAL(1);
7478 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7480 struct tg3_napi *tnapi = dev_id;
7481 struct tg3 *tp = tnapi->tp;
7482 struct tg3_hw_status *sblk = tnapi->hw_status;
7483 unsigned int handled = 1;
7485 /* In INTx mode, it is possible for the interrupt to arrive at
7486 * the CPU before the status block posted prior to the interrupt.
7487 * Reading the PCI State register will confirm whether the
7488 * interrupt is ours and will flush the status block.
7490 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7491 if (tg3_flag(tp, CHIP_RESETTING) ||
7492 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7499 * Writing any value to intr-mbox-0 clears PCI INTA# and
7500 * chip-internal interrupt pending events.
7501 * Writing non-zero to intr-mbox-0 additional tells the
7502 * NIC to stop sending us irqs, engaging "in-intr-handler"
7505 * Flush the mailbox to de-assert the IRQ immediately to prevent
7506 * spurious interrupts. The flush impacts performance but
7507 * excessive spurious interrupts can be worse in some cases.
7509 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7510 if (tg3_irq_sync(tp))
7512 sblk->status &= ~SD_STATUS_UPDATED;
7513 if (likely(tg3_has_work(tnapi))) {
7514 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7515 napi_schedule(&tnapi->napi);
7517 /* No work, shared interrupt perhaps? re-enable
7518 * interrupts, and flush that PCI write
7520 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7524 return IRQ_RETVAL(handled);
7527 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7529 struct tg3_napi *tnapi = dev_id;
7530 struct tg3 *tp = tnapi->tp;
7531 struct tg3_hw_status *sblk = tnapi->hw_status;
7532 unsigned int handled = 1;
7534 /* In INTx mode, it is possible for the interrupt to arrive at
7535 * the CPU before the status block posted prior to the interrupt.
7536 * Reading the PCI State register will confirm whether the
7537 * interrupt is ours and will flush the status block.
7539 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7540 if (tg3_flag(tp, CHIP_RESETTING) ||
7541 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7548 * writing any value to intr-mbox-0 clears PCI INTA# and
7549 * chip-internal interrupt pending events.
7550 * writing non-zero to intr-mbox-0 additional tells the
7551 * NIC to stop sending us irqs, engaging "in-intr-handler"
7554 * Flush the mailbox to de-assert the IRQ immediately to prevent
7555 * spurious interrupts. The flush impacts performance but
7556 * excessive spurious interrupts can be worse in some cases.
7558 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7561 * In a shared interrupt configuration, sometimes other devices'
7562 * interrupts will scream. We record the current status tag here
7563 * so that the above check can report that the screaming interrupts
7564 * are unhandled. Eventually they will be silenced.
7566 tnapi->last_irq_tag = sblk->status_tag;
7568 if (tg3_irq_sync(tp))
7571 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7573 napi_schedule(&tnapi->napi);
7576 return IRQ_RETVAL(handled);
7579 /* ISR for interrupt test */
7580 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7582 struct tg3_napi *tnapi = dev_id;
7583 struct tg3 *tp = tnapi->tp;
7584 struct tg3_hw_status *sblk = tnapi->hw_status;
7586 if ((sblk->status & SD_STATUS_UPDATED) ||
7587 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7588 tg3_disable_ints(tp);
7589 return IRQ_RETVAL(1);
7591 return IRQ_RETVAL(0);
7594 #ifdef CONFIG_NET_POLL_CONTROLLER
7595 static void tg3_poll_controller(struct net_device *dev)
7598 struct tg3 *tp = netdev_priv(dev);
7600 if (tg3_irq_sync(tp))
7603 for (i = 0; i < tp->irq_cnt; i++)
7604 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7608 static void tg3_tx_timeout(struct net_device *dev)
7610 struct tg3 *tp = netdev_priv(dev);
7612 if (netif_msg_tx_err(tp)) {
7613 netdev_err(dev, "transmit timed out, resetting\n");
7617 tg3_reset_task_schedule(tp);
7620 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7621 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7623 u32 base = (u32) mapping & 0xffffffff;
7625 return (base > 0xffffdcc0) && (base + len + 8 < base);
7628 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7629 * of any 4GB boundaries: 4G, 8G, etc
7631 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7634 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7635 u32 base = (u32) mapping & 0xffffffff;
7637 return ((base + len + (mss & 0x3fff)) < base);
7642 /* Test for DMA addresses > 40-bit */
7643 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7646 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7647 if (tg3_flag(tp, 40BIT_DMA_BUG))
7648 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7655 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7656 dma_addr_t mapping, u32 len, u32 flags,
7659 txbd->addr_hi = ((u64) mapping >> 32);
7660 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7661 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7662 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7665 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7666 dma_addr_t map, u32 len, u32 flags,
7669 struct tg3 *tp = tnapi->tp;
7672 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7675 if (tg3_4g_overflow_test(map, len))
7678 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7681 if (tg3_40bit_overflow_test(tp, map, len))
7684 if (tp->dma_limit) {
7685 u32 prvidx = *entry;
7686 u32 tmp_flag = flags & ~TXD_FLAG_END;
7687 while (len > tp->dma_limit && *budget) {
7688 u32 frag_len = tp->dma_limit;
7689 len -= tp->dma_limit;
7691 /* Avoid the 8byte DMA problem */
7693 len += tp->dma_limit / 2;
7694 frag_len = tp->dma_limit / 2;
7697 tnapi->tx_buffers[*entry].fragmented = true;
7699 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7700 frag_len, tmp_flag, mss, vlan);
7703 *entry = NEXT_TX(*entry);
7710 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7711 len, flags, mss, vlan);
7713 *entry = NEXT_TX(*entry);
7716 tnapi->tx_buffers[prvidx].fragmented = false;
7720 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7721 len, flags, mss, vlan);
7722 *entry = NEXT_TX(*entry);
7728 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7731 struct sk_buff *skb;
7732 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7737 pci_unmap_single(tnapi->tp->pdev,
7738 dma_unmap_addr(txb, mapping),
7742 while (txb->fragmented) {
7743 txb->fragmented = false;
7744 entry = NEXT_TX(entry);
7745 txb = &tnapi->tx_buffers[entry];
7748 for (i = 0; i <= last; i++) {
7749 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7751 entry = NEXT_TX(entry);
7752 txb = &tnapi->tx_buffers[entry];
7754 pci_unmap_page(tnapi->tp->pdev,
7755 dma_unmap_addr(txb, mapping),
7756 skb_frag_size(frag), PCI_DMA_TODEVICE);
7758 while (txb->fragmented) {
7759 txb->fragmented = false;
7760 entry = NEXT_TX(entry);
7761 txb = &tnapi->tx_buffers[entry];
7766 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7767 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7768 struct sk_buff **pskb,
7769 u32 *entry, u32 *budget,
7770 u32 base_flags, u32 mss, u32 vlan)
7772 struct tg3 *tp = tnapi->tp;
7773 struct sk_buff *new_skb, *skb = *pskb;
7774 dma_addr_t new_addr = 0;
7777 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7778 new_skb = skb_copy(skb, GFP_ATOMIC);
7780 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7782 new_skb = skb_copy_expand(skb,
7783 skb_headroom(skb) + more_headroom,
7784 skb_tailroom(skb), GFP_ATOMIC);
7790 /* New SKB is guaranteed to be linear. */
7791 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7793 /* Make sure the mapping succeeded */
7794 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7795 dev_kfree_skb(new_skb);
7798 u32 save_entry = *entry;
7800 base_flags |= TXD_FLAG_END;
7802 tnapi->tx_buffers[*entry].skb = new_skb;
7803 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7806 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7807 new_skb->len, base_flags,
7809 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7810 dev_kfree_skb(new_skb);
7821 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7823 /* Use GSO to workaround a rare TSO bug that may be triggered when the
7824 * TSO header is greater than 80 bytes.
7826 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
7828 struct sk_buff *segs, *nskb;
7829 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7831 /* Estimate the number of fragments in the worst case */
7832 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
7833 netif_stop_queue(tp->dev);
7835 /* netif_tx_stop_queue() must be done before checking
7836 * checking tx index in tg3_tx_avail() below, because in
7837 * tg3_tx(), we update tx index before checking for
7838 * netif_tx_queue_stopped().
7841 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
7842 return NETDEV_TX_BUSY;
7844 netif_wake_queue(tp->dev);
7847 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
7849 goto tg3_tso_bug_end;
7855 tg3_start_xmit(nskb, tp->dev);
7861 return NETDEV_TX_OK;
7864 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
7865 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
7867 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7869 struct tg3 *tp = netdev_priv(dev);
7870 u32 len, entry, base_flags, mss, vlan = 0;
7872 int i = -1, would_hit_hwbug;
7874 struct tg3_napi *tnapi;
7875 struct netdev_queue *txq;
7878 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7879 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7880 if (tg3_flag(tp, ENABLE_TSS))
7883 budget = tg3_tx_avail(tnapi);
7885 /* We are running in BH disabled context with netif_tx_lock
7886 * and TX reclaim runs via tp->napi.poll inside of a software
7887 * interrupt. Furthermore, IRQ processing runs lockless so we have
7888 * no IRQ context deadlocks to worry about either. Rejoice!
7890 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7891 if (!netif_tx_queue_stopped(txq)) {
7892 netif_tx_stop_queue(txq);
7894 /* This is a hard error, log it. */
7896 "BUG! Tx Ring full when queue awake!\n");
7898 return NETDEV_TX_BUSY;
7901 entry = tnapi->tx_prod;
7903 if (skb->ip_summed == CHECKSUM_PARTIAL)
7904 base_flags |= TXD_FLAG_TCPUDP_CSUM;
7906 mss = skb_shinfo(skb)->gso_size;
7909 u32 tcp_opt_len, hdr_len;
7911 if (skb_header_cloned(skb) &&
7912 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7916 tcp_opt_len = tcp_optlen(skb);
7918 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7920 if (!skb_is_gso_v6(skb)) {
7922 iph->tot_len = htons(mss + hdr_len);
7925 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7926 tg3_flag(tp, TSO_BUG))
7927 return tg3_tso_bug(tp, skb);
7929 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7930 TXD_FLAG_CPU_POST_DMA);
7932 if (tg3_flag(tp, HW_TSO_1) ||
7933 tg3_flag(tp, HW_TSO_2) ||
7934 tg3_flag(tp, HW_TSO_3)) {
7935 tcp_hdr(skb)->check = 0;
7936 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7938 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7943 if (tg3_flag(tp, HW_TSO_3)) {
7944 mss |= (hdr_len & 0xc) << 12;
7946 base_flags |= 0x00000010;
7947 base_flags |= (hdr_len & 0x3e0) << 5;
7948 } else if (tg3_flag(tp, HW_TSO_2))
7949 mss |= hdr_len << 9;
7950 else if (tg3_flag(tp, HW_TSO_1) ||
7951 tg3_asic_rev(tp) == ASIC_REV_5705) {
7952 if (tcp_opt_len || iph->ihl > 5) {
7955 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7956 mss |= (tsflags << 11);
7959 if (tcp_opt_len || iph->ihl > 5) {
7962 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7963 base_flags |= tsflags << 12;
7968 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
7969 !mss && skb->len > VLAN_ETH_FRAME_LEN)
7970 base_flags |= TXD_FLAG_JMB_PKT;
7972 if (vlan_tx_tag_present(skb)) {
7973 base_flags |= TXD_FLAG_VLAN;
7974 vlan = vlan_tx_tag_get(skb);
7977 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
7978 tg3_flag(tp, TX_TSTAMP_EN)) {
7979 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7980 base_flags |= TXD_FLAG_HWTSTAMP;
7983 len = skb_headlen(skb);
7985 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
7986 if (pci_dma_mapping_error(tp->pdev, mapping))
7990 tnapi->tx_buffers[entry].skb = skb;
7991 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
7993 would_hit_hwbug = 0;
7995 if (tg3_flag(tp, 5701_DMA_BUG))
7996 would_hit_hwbug = 1;
7998 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
7999 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8001 would_hit_hwbug = 1;
8002 } else if (skb_shinfo(skb)->nr_frags > 0) {
8005 if (!tg3_flag(tp, HW_TSO_1) &&
8006 !tg3_flag(tp, HW_TSO_2) &&
8007 !tg3_flag(tp, HW_TSO_3))
8010 /* Now loop through additional data
8011 * fragments, and queue them.
8013 last = skb_shinfo(skb)->nr_frags - 1;
8014 for (i = 0; i <= last; i++) {
8015 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8017 len = skb_frag_size(frag);
8018 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8019 len, DMA_TO_DEVICE);
8021 tnapi->tx_buffers[entry].skb = NULL;
8022 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8024 if (dma_mapping_error(&tp->pdev->dev, mapping))
8028 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8030 ((i == last) ? TXD_FLAG_END : 0),
8032 would_hit_hwbug = 1;
8038 if (would_hit_hwbug) {
8039 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8041 /* If the workaround fails due to memory/mapping
8042 * failure, silently drop this packet.
8044 entry = tnapi->tx_prod;
8045 budget = tg3_tx_avail(tnapi);
8046 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8047 base_flags, mss, vlan))
8051 skb_tx_timestamp(skb);
8052 netdev_tx_sent_queue(txq, skb->len);
8054 /* Sync BD data before updating mailbox */
8057 /* Packets are ready, update Tx producer idx local and on card. */
8058 tw32_tx_mbox(tnapi->prodmbox, entry);
8060 tnapi->tx_prod = entry;
8061 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8062 netif_tx_stop_queue(txq);
8064 /* netif_tx_stop_queue() must be done before checking
8065 * checking tx index in tg3_tx_avail() below, because in
8066 * tg3_tx(), we update tx index before checking for
8067 * netif_tx_queue_stopped().
8070 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8071 netif_tx_wake_queue(txq);
8075 return NETDEV_TX_OK;
8078 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8079 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8084 return NETDEV_TX_OK;
8087 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8090 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8091 MAC_MODE_PORT_MODE_MASK);
8093 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8095 if (!tg3_flag(tp, 5705_PLUS))
8096 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8098 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8099 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8101 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8103 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8105 if (tg3_flag(tp, 5705_PLUS) ||
8106 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8107 tg3_asic_rev(tp) == ASIC_REV_5700)
8108 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8111 tw32(MAC_MODE, tp->mac_mode);
8115 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8117 u32 val, bmcr, mac_mode, ptest = 0;
8119 tg3_phy_toggle_apd(tp, false);
8120 tg3_phy_toggle_automdix(tp, false);
8122 if (extlpbk && tg3_phy_set_extloopbk(tp))
8125 bmcr = BMCR_FULLDPLX;
8130 bmcr |= BMCR_SPEED100;
8134 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8136 bmcr |= BMCR_SPEED100;
8139 bmcr |= BMCR_SPEED1000;
8144 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8145 tg3_readphy(tp, MII_CTRL1000, &val);
8146 val |= CTL1000_AS_MASTER |
8147 CTL1000_ENABLE_MASTER;
8148 tg3_writephy(tp, MII_CTRL1000, val);
8150 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8151 MII_TG3_FET_PTEST_TRIM_2;
8152 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8155 bmcr |= BMCR_LOOPBACK;
8157 tg3_writephy(tp, MII_BMCR, bmcr);
8159 /* The write needs to be flushed for the FETs */
8160 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8161 tg3_readphy(tp, MII_BMCR, &bmcr);
8165 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8166 tg3_asic_rev(tp) == ASIC_REV_5785) {
8167 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8168 MII_TG3_FET_PTEST_FRC_TX_LINK |
8169 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8171 /* The write needs to be flushed for the AC131 */
8172 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8175 /* Reset to prevent losing 1st rx packet intermittently */
8176 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8177 tg3_flag(tp, 5780_CLASS)) {
8178 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8180 tw32_f(MAC_RX_MODE, tp->rx_mode);
8183 mac_mode = tp->mac_mode &
8184 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8185 if (speed == SPEED_1000)
8186 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8188 mac_mode |= MAC_MODE_PORT_MODE_MII;
8190 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8191 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8193 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8194 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8195 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8196 mac_mode |= MAC_MODE_LINK_POLARITY;
8198 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8199 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8202 tw32(MAC_MODE, mac_mode);
8208 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8210 struct tg3 *tp = netdev_priv(dev);
8212 if (features & NETIF_F_LOOPBACK) {
8213 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8216 spin_lock_bh(&tp->lock);
8217 tg3_mac_loopback(tp, true);
8218 netif_carrier_on(tp->dev);
8219 spin_unlock_bh(&tp->lock);
8220 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8222 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8225 spin_lock_bh(&tp->lock);
8226 tg3_mac_loopback(tp, false);
8227 /* Force link status check */
8228 tg3_setup_phy(tp, true);
8229 spin_unlock_bh(&tp->lock);
8230 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8234 static netdev_features_t tg3_fix_features(struct net_device *dev,
8235 netdev_features_t features)
8237 struct tg3 *tp = netdev_priv(dev);
8239 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8240 features &= ~NETIF_F_ALL_TSO;
8245 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8247 netdev_features_t changed = dev->features ^ features;
8249 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8250 tg3_set_loopback(dev, features);
8255 static void tg3_rx_prodring_free(struct tg3 *tp,
8256 struct tg3_rx_prodring_set *tpr)
8260 if (tpr != &tp->napi[0].prodring) {
8261 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8262 i = (i + 1) & tp->rx_std_ring_mask)
8263 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8266 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8267 for (i = tpr->rx_jmb_cons_idx;
8268 i != tpr->rx_jmb_prod_idx;
8269 i = (i + 1) & tp->rx_jmb_ring_mask) {
8270 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8278 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8279 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8282 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8283 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8284 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8289 /* Initialize rx rings for packet processing.
8291 * The chip has been shut down and the driver detached from
8292 * the networking, so no interrupts or new tx packets will
8293 * end up in the driver. tp->{tx,}lock are held and thus
8296 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8297 struct tg3_rx_prodring_set *tpr)
8299 u32 i, rx_pkt_dma_sz;
8301 tpr->rx_std_cons_idx = 0;
8302 tpr->rx_std_prod_idx = 0;
8303 tpr->rx_jmb_cons_idx = 0;
8304 tpr->rx_jmb_prod_idx = 0;
8306 if (tpr != &tp->napi[0].prodring) {
8307 memset(&tpr->rx_std_buffers[0], 0,
8308 TG3_RX_STD_BUFF_RING_SIZE(tp));
8309 if (tpr->rx_jmb_buffers)
8310 memset(&tpr->rx_jmb_buffers[0], 0,
8311 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8315 /* Zero out all descriptors. */
8316 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8318 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8319 if (tg3_flag(tp, 5780_CLASS) &&
8320 tp->dev->mtu > ETH_DATA_LEN)
8321 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8322 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8324 /* Initialize invariants of the rings, we only set this
8325 * stuff once. This works because the card does not
8326 * write into the rx buffer posting rings.
8328 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8329 struct tg3_rx_buffer_desc *rxd;
8331 rxd = &tpr->rx_std[i];
8332 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8333 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8334 rxd->opaque = (RXD_OPAQUE_RING_STD |
8335 (i << RXD_OPAQUE_INDEX_SHIFT));
8338 /* Now allocate fresh SKBs for each rx ring. */
8339 for (i = 0; i < tp->rx_pending; i++) {
8340 unsigned int frag_size;
8342 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8344 netdev_warn(tp->dev,
8345 "Using a smaller RX standard ring. Only "
8346 "%d out of %d buffers were allocated "
8347 "successfully\n", i, tp->rx_pending);
8355 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8358 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8360 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8363 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8364 struct tg3_rx_buffer_desc *rxd;
8366 rxd = &tpr->rx_jmb[i].std;
8367 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8368 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8370 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8371 (i << RXD_OPAQUE_INDEX_SHIFT));
8374 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8375 unsigned int frag_size;
8377 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8379 netdev_warn(tp->dev,
8380 "Using a smaller RX jumbo ring. Only %d "
8381 "out of %d buffers were allocated "
8382 "successfully\n", i, tp->rx_jumbo_pending);
8385 tp->rx_jumbo_pending = i;
8394 tg3_rx_prodring_free(tp, tpr);
8398 static void tg3_rx_prodring_fini(struct tg3 *tp,
8399 struct tg3_rx_prodring_set *tpr)
8401 kfree(tpr->rx_std_buffers);
8402 tpr->rx_std_buffers = NULL;
8403 kfree(tpr->rx_jmb_buffers);
8404 tpr->rx_jmb_buffers = NULL;
8406 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8407 tpr->rx_std, tpr->rx_std_mapping);
8411 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8412 tpr->rx_jmb, tpr->rx_jmb_mapping);
8417 static int tg3_rx_prodring_init(struct tg3 *tp,
8418 struct tg3_rx_prodring_set *tpr)
8420 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8422 if (!tpr->rx_std_buffers)
8425 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8426 TG3_RX_STD_RING_BYTES(tp),
8427 &tpr->rx_std_mapping,
8432 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8433 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8435 if (!tpr->rx_jmb_buffers)
8438 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8439 TG3_RX_JMB_RING_BYTES(tp),
8440 &tpr->rx_jmb_mapping,
8449 tg3_rx_prodring_fini(tp, tpr);
8453 /* Free up pending packets in all rx/tx rings.
8455 * The chip has been shut down and the driver detached from
8456 * the networking, so no interrupts or new tx packets will
8457 * end up in the driver. tp->{tx,}lock is not held and we are not
8458 * in an interrupt context and thus may sleep.
8460 static void tg3_free_rings(struct tg3 *tp)
8464 for (j = 0; j < tp->irq_cnt; j++) {
8465 struct tg3_napi *tnapi = &tp->napi[j];
8467 tg3_rx_prodring_free(tp, &tnapi->prodring);
8469 if (!tnapi->tx_buffers)
8472 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8473 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8478 tg3_tx_skb_unmap(tnapi, i,
8479 skb_shinfo(skb)->nr_frags - 1);
8481 dev_kfree_skb_any(skb);
8483 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8487 /* Initialize tx/rx rings for packet processing.
8489 * The chip has been shut down and the driver detached from
8490 * the networking, so no interrupts or new tx packets will
8491 * end up in the driver. tp->{tx,}lock are held and thus
8494 static int tg3_init_rings(struct tg3 *tp)
8498 /* Free up all the SKBs. */
8501 for (i = 0; i < tp->irq_cnt; i++) {
8502 struct tg3_napi *tnapi = &tp->napi[i];
8504 tnapi->last_tag = 0;
8505 tnapi->last_irq_tag = 0;
8506 tnapi->hw_status->status = 0;
8507 tnapi->hw_status->status_tag = 0;
8508 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8513 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8515 tnapi->rx_rcb_ptr = 0;
8517 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8519 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8528 static void tg3_mem_tx_release(struct tg3 *tp)
8532 for (i = 0; i < tp->irq_max; i++) {
8533 struct tg3_napi *tnapi = &tp->napi[i];
8535 if (tnapi->tx_ring) {
8536 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8537 tnapi->tx_ring, tnapi->tx_desc_mapping);
8538 tnapi->tx_ring = NULL;
8541 kfree(tnapi->tx_buffers);
8542 tnapi->tx_buffers = NULL;
8546 static int tg3_mem_tx_acquire(struct tg3 *tp)
8549 struct tg3_napi *tnapi = &tp->napi[0];
8551 /* If multivector TSS is enabled, vector 0 does not handle
8552 * tx interrupts. Don't allocate any resources for it.
8554 if (tg3_flag(tp, ENABLE_TSS))
8557 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8558 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8559 TG3_TX_RING_SIZE, GFP_KERNEL);
8560 if (!tnapi->tx_buffers)
8563 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8565 &tnapi->tx_desc_mapping,
8567 if (!tnapi->tx_ring)
8574 tg3_mem_tx_release(tp);
8578 static void tg3_mem_rx_release(struct tg3 *tp)
8582 for (i = 0; i < tp->irq_max; i++) {
8583 struct tg3_napi *tnapi = &tp->napi[i];
8585 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8590 dma_free_coherent(&tp->pdev->dev,
8591 TG3_RX_RCB_RING_BYTES(tp),
8593 tnapi->rx_rcb_mapping);
8594 tnapi->rx_rcb = NULL;
8598 static int tg3_mem_rx_acquire(struct tg3 *tp)
8600 unsigned int i, limit;
8602 limit = tp->rxq_cnt;
8604 /* If RSS is enabled, we need a (dummy) producer ring
8605 * set on vector zero. This is the true hw prodring.
8607 if (tg3_flag(tp, ENABLE_RSS))
8610 for (i = 0; i < limit; i++) {
8611 struct tg3_napi *tnapi = &tp->napi[i];
8613 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8616 /* If multivector RSS is enabled, vector 0
8617 * does not handle rx or tx interrupts.
8618 * Don't allocate any resources for it.
8620 if (!i && tg3_flag(tp, ENABLE_RSS))
8623 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8624 TG3_RX_RCB_RING_BYTES(tp),
8625 &tnapi->rx_rcb_mapping,
8634 tg3_mem_rx_release(tp);
8639 * Must not be invoked with interrupt sources disabled and
8640 * the hardware shutdown down.
8642 static void tg3_free_consistent(struct tg3 *tp)
8646 for (i = 0; i < tp->irq_cnt; i++) {
8647 struct tg3_napi *tnapi = &tp->napi[i];
8649 if (tnapi->hw_status) {
8650 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8652 tnapi->status_mapping);
8653 tnapi->hw_status = NULL;
8657 tg3_mem_rx_release(tp);
8658 tg3_mem_tx_release(tp);
8661 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8662 tp->hw_stats, tp->stats_mapping);
8663 tp->hw_stats = NULL;
8668 * Must not be invoked with interrupt sources disabled and
8669 * the hardware shutdown down. Can sleep.
8671 static int tg3_alloc_consistent(struct tg3 *tp)
8675 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8676 sizeof(struct tg3_hw_stats),
8677 &tp->stats_mapping, GFP_KERNEL);
8681 for (i = 0; i < tp->irq_cnt; i++) {
8682 struct tg3_napi *tnapi = &tp->napi[i];
8683 struct tg3_hw_status *sblk;
8685 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8687 &tnapi->status_mapping,
8689 if (!tnapi->hw_status)
8692 sblk = tnapi->hw_status;
8694 if (tg3_flag(tp, ENABLE_RSS)) {
8695 u16 *prodptr = NULL;
8698 * When RSS is enabled, the status block format changes
8699 * slightly. The "rx_jumbo_consumer", "reserved",
8700 * and "rx_mini_consumer" members get mapped to the
8701 * other three rx return ring producer indexes.
8705 prodptr = &sblk->idx[0].rx_producer;
8708 prodptr = &sblk->rx_jumbo_consumer;
8711 prodptr = &sblk->reserved;
8714 prodptr = &sblk->rx_mini_consumer;
8717 tnapi->rx_rcb_prod_idx = prodptr;
8719 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8723 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8729 tg3_free_consistent(tp);
8733 #define MAX_WAIT_CNT 1000
8735 /* To stop a block, clear the enable bit and poll till it
8736 * clears. tp->lock is held.
8738 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8743 if (tg3_flag(tp, 5705_PLUS)) {
8750 /* We can't enable/disable these bits of the
8751 * 5705/5750, just say success.
8764 for (i = 0; i < MAX_WAIT_CNT; i++) {
8765 if (pci_channel_offline(tp->pdev)) {
8766 dev_err(&tp->pdev->dev,
8767 "tg3_stop_block device offline, "
8768 "ofs=%lx enable_bit=%x\n",
8775 if ((val & enable_bit) == 0)
8779 if (i == MAX_WAIT_CNT && !silent) {
8780 dev_err(&tp->pdev->dev,
8781 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8789 /* tp->lock is held. */
8790 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8794 tg3_disable_ints(tp);
8796 if (pci_channel_offline(tp->pdev)) {
8797 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8798 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8803 tp->rx_mode &= ~RX_MODE_ENABLE;
8804 tw32_f(MAC_RX_MODE, tp->rx_mode);
8807 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8808 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8809 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8810 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8811 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8812 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8814 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8815 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8816 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8817 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8818 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8819 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8820 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8822 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8823 tw32_f(MAC_MODE, tp->mac_mode);
8826 tp->tx_mode &= ~TX_MODE_ENABLE;
8827 tw32_f(MAC_TX_MODE, tp->tx_mode);
8829 for (i = 0; i < MAX_WAIT_CNT; i++) {
8831 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8834 if (i >= MAX_WAIT_CNT) {
8835 dev_err(&tp->pdev->dev,
8836 "%s timed out, TX_MODE_ENABLE will not clear "
8837 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8841 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8842 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8843 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8845 tw32(FTQ_RESET, 0xffffffff);
8846 tw32(FTQ_RESET, 0x00000000);
8848 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8849 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8852 for (i = 0; i < tp->irq_cnt; i++) {
8853 struct tg3_napi *tnapi = &tp->napi[i];
8854 if (tnapi->hw_status)
8855 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8861 /* Save PCI command register before chip reset */
8862 static void tg3_save_pci_state(struct tg3 *tp)
8864 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8867 /* Restore PCI state after chip reset */
8868 static void tg3_restore_pci_state(struct tg3 *tp)
8872 /* Re-enable indirect register accesses. */
8873 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8874 tp->misc_host_ctrl);
8876 /* Set MAX PCI retry to zero. */
8877 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8878 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8879 tg3_flag(tp, PCIX_MODE))
8880 val |= PCISTATE_RETRY_SAME_DMA;
8881 /* Allow reads and writes to the APE register and memory space. */
8882 if (tg3_flag(tp, ENABLE_APE))
8883 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8884 PCISTATE_ALLOW_APE_SHMEM_WR |
8885 PCISTATE_ALLOW_APE_PSPACE_WR;
8886 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8888 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8890 if (!tg3_flag(tp, PCI_EXPRESS)) {
8891 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8892 tp->pci_cacheline_sz);
8893 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8897 /* Make sure PCI-X relaxed ordering bit is clear. */
8898 if (tg3_flag(tp, PCIX_MODE)) {
8901 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8903 pcix_cmd &= ~PCI_X_CMD_ERO;
8904 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8908 if (tg3_flag(tp, 5780_CLASS)) {
8910 /* Chip reset on 5780 will reset MSI enable bit,
8911 * so need to restore it.
8913 if (tg3_flag(tp, USING_MSI)) {
8916 pci_read_config_word(tp->pdev,
8917 tp->msi_cap + PCI_MSI_FLAGS,
8919 pci_write_config_word(tp->pdev,
8920 tp->msi_cap + PCI_MSI_FLAGS,
8921 ctrl | PCI_MSI_FLAGS_ENABLE);
8922 val = tr32(MSGINT_MODE);
8923 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8928 /* tp->lock is held. */
8929 static int tg3_chip_reset(struct tg3 *tp)
8932 void (*write_op)(struct tg3 *, u32, u32);
8935 if (!pci_device_is_present(tp->pdev))
8940 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
8942 /* No matching tg3_nvram_unlock() after this because
8943 * chip reset below will undo the nvram lock.
8945 tp->nvram_lock_cnt = 0;
8947 /* GRC_MISC_CFG core clock reset will clear the memory
8948 * enable bit in PCI register 4 and the MSI enable bit
8949 * on some chips, so we save relevant registers here.
8951 tg3_save_pci_state(tp);
8953 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
8954 tg3_flag(tp, 5755_PLUS))
8955 tw32(GRC_FASTBOOT_PC, 0);
8958 * We must avoid the readl() that normally takes place.
8959 * It locks machines, causes machine checks, and other
8960 * fun things. So, temporarily disable the 5701
8961 * hardware workaround, while we do the reset.
8963 write_op = tp->write32;
8964 if (write_op == tg3_write_flush_reg32)
8965 tp->write32 = tg3_write32;
8967 /* Prevent the irq handler from reading or writing PCI registers
8968 * during chip reset when the memory enable bit in the PCI command
8969 * register may be cleared. The chip does not generate interrupt
8970 * at this time, but the irq handler may still be called due to irq
8971 * sharing or irqpoll.
8973 tg3_flag_set(tp, CHIP_RESETTING);
8974 for (i = 0; i < tp->irq_cnt; i++) {
8975 struct tg3_napi *tnapi = &tp->napi[i];
8976 if (tnapi->hw_status) {
8977 tnapi->hw_status->status = 0;
8978 tnapi->hw_status->status_tag = 0;
8980 tnapi->last_tag = 0;
8981 tnapi->last_irq_tag = 0;
8985 for (i = 0; i < tp->irq_cnt; i++)
8986 synchronize_irq(tp->napi[i].irq_vec);
8988 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
8989 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
8990 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
8994 val = GRC_MISC_CFG_CORECLK_RESET;
8996 if (tg3_flag(tp, PCI_EXPRESS)) {
8997 /* Force PCIe 1.0a mode */
8998 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
8999 !tg3_flag(tp, 57765_PLUS) &&
9000 tr32(TG3_PCIE_PHY_TSTCTL) ==
9001 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9002 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9004 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9005 tw32(GRC_MISC_CFG, (1 << 29));
9010 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9011 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9012 tw32(GRC_VCPU_EXT_CTRL,
9013 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9016 /* Manage gphy power for all CPMU absent PCIe devices. */
9017 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9018 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9020 tw32(GRC_MISC_CFG, val);
9022 /* restore 5701 hardware bug workaround write method */
9023 tp->write32 = write_op;
9025 /* Unfortunately, we have to delay before the PCI read back.
9026 * Some 575X chips even will not respond to a PCI cfg access
9027 * when the reset command is given to the chip.
9029 * How do these hardware designers expect things to work
9030 * properly if the PCI write is posted for a long period
9031 * of time? It is always necessary to have some method by
9032 * which a register read back can occur to push the write
9033 * out which does the reset.
9035 * For most tg3 variants the trick below was working.
9040 /* Flush PCI posted writes. The normal MMIO registers
9041 * are inaccessible at this time so this is the only
9042 * way to make this reliably (actually, this is no longer
9043 * the case, see above). I tried to use indirect
9044 * register read/write but this upset some 5701 variants.
9046 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9050 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9053 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9057 /* Wait for link training to complete. */
9058 for (j = 0; j < 5000; j++)
9061 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9062 pci_write_config_dword(tp->pdev, 0xc4,
9063 cfg_val | (1 << 15));
9066 /* Clear the "no snoop" and "relaxed ordering" bits. */
9067 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9069 * Older PCIe devices only support the 128 byte
9070 * MPS setting. Enforce the restriction.
9072 if (!tg3_flag(tp, CPMU_PRESENT))
9073 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9074 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9076 /* Clear error status */
9077 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9078 PCI_EXP_DEVSTA_CED |
9079 PCI_EXP_DEVSTA_NFED |
9080 PCI_EXP_DEVSTA_FED |
9081 PCI_EXP_DEVSTA_URD);
9084 tg3_restore_pci_state(tp);
9086 tg3_flag_clear(tp, CHIP_RESETTING);
9087 tg3_flag_clear(tp, ERROR_PROCESSED);
9090 if (tg3_flag(tp, 5780_CLASS))
9091 val = tr32(MEMARB_MODE);
9092 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9094 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9096 tw32(0x5000, 0x400);
9099 if (tg3_flag(tp, IS_SSB_CORE)) {
9101 * BCM4785: In order to avoid repercussions from using
9102 * potentially defective internal ROM, stop the Rx RISC CPU,
9103 * which is not required.
9106 tg3_halt_cpu(tp, RX_CPU_BASE);
9109 err = tg3_poll_fw(tp);
9113 tw32(GRC_MODE, tp->grc_mode);
9115 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9118 tw32(0xc4, val | (1 << 15));
9121 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9122 tg3_asic_rev(tp) == ASIC_REV_5705) {
9123 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9124 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9125 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9126 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9129 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9130 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9132 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9133 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9138 tw32_f(MAC_MODE, val);
9141 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9145 if (tg3_flag(tp, PCI_EXPRESS) &&
9146 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9147 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9148 !tg3_flag(tp, 57765_PLUS)) {
9151 tw32(0x7c00, val | (1 << 25));
9154 if (tg3_asic_rev(tp) == ASIC_REV_5720) {
9155 val = tr32(TG3_CPMU_CLCK_ORIDE);
9156 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9159 /* Reprobe ASF enable state. */
9160 tg3_flag_clear(tp, ENABLE_ASF);
9161 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9162 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9164 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9165 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9166 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9169 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9170 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9171 tg3_flag_set(tp, ENABLE_ASF);
9172 tp->last_event_jiffies = jiffies;
9173 if (tg3_flag(tp, 5750_PLUS))
9174 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9176 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9177 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9178 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9179 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9180 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9187 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9188 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9190 /* tp->lock is held. */
9191 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9197 tg3_write_sig_pre_reset(tp, kind);
9199 tg3_abort_hw(tp, silent);
9200 err = tg3_chip_reset(tp);
9202 __tg3_set_mac_addr(tp, false);
9204 tg3_write_sig_legacy(tp, kind);
9205 tg3_write_sig_post_reset(tp, kind);
9208 /* Save the stats across chip resets... */
9209 tg3_get_nstats(tp, &tp->net_stats_prev);
9210 tg3_get_estats(tp, &tp->estats_prev);
9212 /* And make sure the next sample is new data */
9213 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9219 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9221 struct tg3 *tp = netdev_priv(dev);
9222 struct sockaddr *addr = p;
9224 bool skip_mac_1 = false;
9226 if (!is_valid_ether_addr(addr->sa_data))
9227 return -EADDRNOTAVAIL;
9229 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9231 if (!netif_running(dev))
9234 if (tg3_flag(tp, ENABLE_ASF)) {
9235 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9237 addr0_high = tr32(MAC_ADDR_0_HIGH);
9238 addr0_low = tr32(MAC_ADDR_0_LOW);
9239 addr1_high = tr32(MAC_ADDR_1_HIGH);
9240 addr1_low = tr32(MAC_ADDR_1_LOW);
9242 /* Skip MAC addr 1 if ASF is using it. */
9243 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9244 !(addr1_high == 0 && addr1_low == 0))
9247 spin_lock_bh(&tp->lock);
9248 __tg3_set_mac_addr(tp, skip_mac_1);
9249 spin_unlock_bh(&tp->lock);
9254 /* tp->lock is held. */
9255 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9256 dma_addr_t mapping, u32 maxlen_flags,
9260 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9261 ((u64) mapping >> 32));
9263 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9264 ((u64) mapping & 0xffffffff));
9266 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9269 if (!tg3_flag(tp, 5705_PLUS))
9271 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9276 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9280 if (!tg3_flag(tp, ENABLE_TSS)) {
9281 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9282 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9283 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9285 tw32(HOSTCC_TXCOL_TICKS, 0);
9286 tw32(HOSTCC_TXMAX_FRAMES, 0);
9287 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9289 for (; i < tp->txq_cnt; i++) {
9292 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9293 tw32(reg, ec->tx_coalesce_usecs);
9294 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9295 tw32(reg, ec->tx_max_coalesced_frames);
9296 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9297 tw32(reg, ec->tx_max_coalesced_frames_irq);
9301 for (; i < tp->irq_max - 1; i++) {
9302 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9303 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9304 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9308 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9311 u32 limit = tp->rxq_cnt;
9313 if (!tg3_flag(tp, ENABLE_RSS)) {
9314 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9315 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9316 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9319 tw32(HOSTCC_RXCOL_TICKS, 0);
9320 tw32(HOSTCC_RXMAX_FRAMES, 0);
9321 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9324 for (; i < limit; i++) {
9327 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9328 tw32(reg, ec->rx_coalesce_usecs);
9329 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9330 tw32(reg, ec->rx_max_coalesced_frames);
9331 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9332 tw32(reg, ec->rx_max_coalesced_frames_irq);
9335 for (; i < tp->irq_max - 1; i++) {
9336 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9337 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9338 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9342 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9344 tg3_coal_tx_init(tp, ec);
9345 tg3_coal_rx_init(tp, ec);
9347 if (!tg3_flag(tp, 5705_PLUS)) {
9348 u32 val = ec->stats_block_coalesce_usecs;
9350 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9351 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9356 tw32(HOSTCC_STAT_COAL_TICKS, val);
9360 /* tp->lock is held. */
9361 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9365 /* Disable all transmit rings but the first. */
9366 if (!tg3_flag(tp, 5705_PLUS))
9367 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9368 else if (tg3_flag(tp, 5717_PLUS))
9369 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9370 else if (tg3_flag(tp, 57765_CLASS) ||
9371 tg3_asic_rev(tp) == ASIC_REV_5762)
9372 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9374 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9376 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9377 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9378 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9379 BDINFO_FLAGS_DISABLED);
9382 /* tp->lock is held. */
9383 static void tg3_tx_rcbs_init(struct tg3 *tp)
9386 u32 txrcb = NIC_SRAM_SEND_RCB;
9388 if (tg3_flag(tp, ENABLE_TSS))
9391 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9392 struct tg3_napi *tnapi = &tp->napi[i];
9394 if (!tnapi->tx_ring)
9397 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9398 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9399 NIC_SRAM_TX_BUFFER_DESC);
9403 /* tp->lock is held. */
9404 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9408 /* Disable all receive return rings but the first. */
9409 if (tg3_flag(tp, 5717_PLUS))
9410 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9411 else if (!tg3_flag(tp, 5705_PLUS))
9412 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9413 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9414 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9415 tg3_flag(tp, 57765_CLASS))
9416 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9418 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9420 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9421 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9422 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9423 BDINFO_FLAGS_DISABLED);
9426 /* tp->lock is held. */
9427 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9430 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9432 if (tg3_flag(tp, ENABLE_RSS))
9435 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9436 struct tg3_napi *tnapi = &tp->napi[i];
9441 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9442 (tp->rx_ret_ring_mask + 1) <<
9443 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9447 /* tp->lock is held. */
9448 static void tg3_rings_reset(struct tg3 *tp)
9452 struct tg3_napi *tnapi = &tp->napi[0];
9454 tg3_tx_rcbs_disable(tp);
9456 tg3_rx_ret_rcbs_disable(tp);
9458 /* Disable interrupts */
9459 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9460 tp->napi[0].chk_msi_cnt = 0;
9461 tp->napi[0].last_rx_cons = 0;
9462 tp->napi[0].last_tx_cons = 0;
9464 /* Zero mailbox registers. */
9465 if (tg3_flag(tp, SUPPORT_MSIX)) {
9466 for (i = 1; i < tp->irq_max; i++) {
9467 tp->napi[i].tx_prod = 0;
9468 tp->napi[i].tx_cons = 0;
9469 if (tg3_flag(tp, ENABLE_TSS))
9470 tw32_mailbox(tp->napi[i].prodmbox, 0);
9471 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9472 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9473 tp->napi[i].chk_msi_cnt = 0;
9474 tp->napi[i].last_rx_cons = 0;
9475 tp->napi[i].last_tx_cons = 0;
9477 if (!tg3_flag(tp, ENABLE_TSS))
9478 tw32_mailbox(tp->napi[0].prodmbox, 0);
9480 tp->napi[0].tx_prod = 0;
9481 tp->napi[0].tx_cons = 0;
9482 tw32_mailbox(tp->napi[0].prodmbox, 0);
9483 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9486 /* Make sure the NIC-based send BD rings are disabled. */
9487 if (!tg3_flag(tp, 5705_PLUS)) {
9488 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9489 for (i = 0; i < 16; i++)
9490 tw32_tx_mbox(mbox + i * 8, 0);
9493 /* Clear status block in ram. */
9494 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9496 /* Set status block DMA address */
9497 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9498 ((u64) tnapi->status_mapping >> 32));
9499 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9500 ((u64) tnapi->status_mapping & 0xffffffff));
9502 stblk = HOSTCC_STATBLCK_RING1;
9504 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9505 u64 mapping = (u64)tnapi->status_mapping;
9506 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9507 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9510 /* Clear status block in ram. */
9511 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9514 tg3_tx_rcbs_init(tp);
9515 tg3_rx_ret_rcbs_init(tp);
9518 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9520 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9522 if (!tg3_flag(tp, 5750_PLUS) ||
9523 tg3_flag(tp, 5780_CLASS) ||
9524 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9525 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9526 tg3_flag(tp, 57765_PLUS))
9527 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9528 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9529 tg3_asic_rev(tp) == ASIC_REV_5787)
9530 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9532 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9534 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9535 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9537 val = min(nic_rep_thresh, host_rep_thresh);
9538 tw32(RCVBDI_STD_THRESH, val);
9540 if (tg3_flag(tp, 57765_PLUS))
9541 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9543 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9546 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9548 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9550 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9551 tw32(RCVBDI_JUMBO_THRESH, val);
9553 if (tg3_flag(tp, 57765_PLUS))
9554 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9557 static inline u32 calc_crc(unsigned char *buf, int len)
9565 for (j = 0; j < len; j++) {
9568 for (k = 0; k < 8; k++) {
9581 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9583 /* accept or reject all multicast frames */
9584 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9585 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9586 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9587 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9590 static void __tg3_set_rx_mode(struct net_device *dev)
9592 struct tg3 *tp = netdev_priv(dev);
9595 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9596 RX_MODE_KEEP_VLAN_TAG);
9598 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9599 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9602 if (!tg3_flag(tp, ENABLE_ASF))
9603 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9606 if (dev->flags & IFF_PROMISC) {
9607 /* Promiscuous mode. */
9608 rx_mode |= RX_MODE_PROMISC;
9609 } else if (dev->flags & IFF_ALLMULTI) {
9610 /* Accept all multicast. */
9611 tg3_set_multi(tp, 1);
9612 } else if (netdev_mc_empty(dev)) {
9613 /* Reject all multicast. */
9614 tg3_set_multi(tp, 0);
9616 /* Accept one or more multicast(s). */
9617 struct netdev_hw_addr *ha;
9618 u32 mc_filter[4] = { 0, };
9623 netdev_for_each_mc_addr(ha, dev) {
9624 crc = calc_crc(ha->addr, ETH_ALEN);
9626 regidx = (bit & 0x60) >> 5;
9628 mc_filter[regidx] |= (1 << bit);
9631 tw32(MAC_HASH_REG_0, mc_filter[0]);
9632 tw32(MAC_HASH_REG_1, mc_filter[1]);
9633 tw32(MAC_HASH_REG_2, mc_filter[2]);
9634 tw32(MAC_HASH_REG_3, mc_filter[3]);
9637 if (rx_mode != tp->rx_mode) {
9638 tp->rx_mode = rx_mode;
9639 tw32_f(MAC_RX_MODE, rx_mode);
9644 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9648 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9649 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9652 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9656 if (!tg3_flag(tp, SUPPORT_MSIX))
9659 if (tp->rxq_cnt == 1) {
9660 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9664 /* Validate table against current IRQ count */
9665 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9666 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9670 if (i != TG3_RSS_INDIR_TBL_SIZE)
9671 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9674 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9677 u32 reg = MAC_RSS_INDIR_TBL_0;
9679 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9680 u32 val = tp->rss_ind_tbl[i];
9682 for (; i % 8; i++) {
9684 val |= tp->rss_ind_tbl[i];
9691 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9693 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9694 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9696 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9699 /* tp->lock is held. */
9700 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9702 u32 val, rdmac_mode;
9704 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9706 tg3_disable_ints(tp);
9710 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9712 if (tg3_flag(tp, INIT_COMPLETE))
9713 tg3_abort_hw(tp, 1);
9715 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9716 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9717 tg3_phy_pull_config(tp);
9718 tg3_eee_pull_config(tp, NULL);
9719 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9722 /* Enable MAC control of LPI */
9723 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9729 err = tg3_chip_reset(tp);
9733 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9735 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9736 val = tr32(TG3_CPMU_CTRL);
9737 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9738 tw32(TG3_CPMU_CTRL, val);
9740 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9741 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9742 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9743 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9745 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9746 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9747 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9748 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9750 val = tr32(TG3_CPMU_HST_ACC);
9751 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9752 val |= CPMU_HST_ACC_MACCLK_6_25;
9753 tw32(TG3_CPMU_HST_ACC, val);
9756 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9757 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9758 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9759 PCIE_PWR_MGMT_L1_THRESH_4MS;
9760 tw32(PCIE_PWR_MGMT_THRESH, val);
9762 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9763 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9765 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9767 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9768 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9771 if (tg3_flag(tp, L1PLLPD_EN)) {
9772 u32 grc_mode = tr32(GRC_MODE);
9774 /* Access the lower 1K of PL PCIE block registers. */
9775 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9776 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9778 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9779 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9780 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9782 tw32(GRC_MODE, grc_mode);
9785 if (tg3_flag(tp, 57765_CLASS)) {
9786 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9787 u32 grc_mode = tr32(GRC_MODE);
9789 /* Access the lower 1K of PL PCIE block registers. */
9790 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9791 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9793 val = tr32(TG3_PCIE_TLDLPL_PORT +
9794 TG3_PCIE_PL_LO_PHYCTL5);
9795 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9796 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9798 tw32(GRC_MODE, grc_mode);
9801 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9804 /* Fix transmit hangs */
9805 val = tr32(TG3_CPMU_PADRNG_CTL);
9806 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9807 tw32(TG3_CPMU_PADRNG_CTL, val);
9809 grc_mode = tr32(GRC_MODE);
9811 /* Access the lower 1K of DL PCIE block registers. */
9812 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9813 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9815 val = tr32(TG3_PCIE_TLDLPL_PORT +
9816 TG3_PCIE_DL_LO_FTSMAX);
9817 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9818 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9819 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9821 tw32(GRC_MODE, grc_mode);
9824 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9825 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9826 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9827 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9830 /* This works around an issue with Athlon chipsets on
9831 * B3 tigon3 silicon. This bit has no effect on any
9832 * other revision. But do not set this on PCI Express
9833 * chips and don't even touch the clocks if the CPMU is present.
9835 if (!tg3_flag(tp, CPMU_PRESENT)) {
9836 if (!tg3_flag(tp, PCI_EXPRESS))
9837 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9838 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9841 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9842 tg3_flag(tp, PCIX_MODE)) {
9843 val = tr32(TG3PCI_PCISTATE);
9844 val |= PCISTATE_RETRY_SAME_DMA;
9845 tw32(TG3PCI_PCISTATE, val);
9848 if (tg3_flag(tp, ENABLE_APE)) {
9849 /* Allow reads and writes to the
9850 * APE register and memory space.
9852 val = tr32(TG3PCI_PCISTATE);
9853 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9854 PCISTATE_ALLOW_APE_SHMEM_WR |
9855 PCISTATE_ALLOW_APE_PSPACE_WR;
9856 tw32(TG3PCI_PCISTATE, val);
9859 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9860 /* Enable some hw fixes. */
9861 val = tr32(TG3PCI_MSI_DATA);
9862 val |= (1 << 26) | (1 << 28) | (1 << 29);
9863 tw32(TG3PCI_MSI_DATA, val);
9866 /* Descriptor ring init may make accesses to the
9867 * NIC SRAM area to setup the TX descriptors, so we
9868 * can only do this after the hardware has been
9869 * successfully reset.
9871 err = tg3_init_rings(tp);
9875 if (tg3_flag(tp, 57765_PLUS)) {
9876 val = tr32(TG3PCI_DMA_RW_CTRL) &
9877 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9878 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9879 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9880 if (!tg3_flag(tp, 57765_CLASS) &&
9881 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9882 tg3_asic_rev(tp) != ASIC_REV_5762)
9883 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9884 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9885 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9886 tg3_asic_rev(tp) != ASIC_REV_5761) {
9887 /* This value is determined during the probe time DMA
9888 * engine test, tg3_test_dma.
9890 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
9893 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
9894 GRC_MODE_4X_NIC_SEND_RINGS |
9895 GRC_MODE_NO_TX_PHDR_CSUM |
9896 GRC_MODE_NO_RX_PHDR_CSUM);
9897 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
9899 /* Pseudo-header checksum is done by hardware logic and not
9900 * the offload processers, so make the chip do the pseudo-
9901 * header checksums on receive. For transmit it is more
9902 * convenient to do the pseudo-header checksum in software
9903 * as Linux does that on transmit for us in all cases.
9905 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
9907 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
9909 tw32(TG3_RX_PTP_CTL,
9910 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
9912 if (tg3_flag(tp, PTP_CAPABLE))
9913 val |= GRC_MODE_TIME_SYNC_ENABLE;
9915 tw32(GRC_MODE, tp->grc_mode | val);
9917 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9918 val = tr32(GRC_MISC_CFG);
9920 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
9921 tw32(GRC_MISC_CFG, val);
9923 /* Initialize MBUF/DESC pool. */
9924 if (tg3_flag(tp, 5750_PLUS)) {
9926 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
9927 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
9928 if (tg3_asic_rev(tp) == ASIC_REV_5704)
9929 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
9931 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
9932 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
9933 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
9934 } else if (tg3_flag(tp, TSO_CAPABLE)) {
9937 fw_len = tp->fw_len;
9938 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
9939 tw32(BUFMGR_MB_POOL_ADDR,
9940 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
9941 tw32(BUFMGR_MB_POOL_SIZE,
9942 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
9945 if (tp->dev->mtu <= ETH_DATA_LEN) {
9946 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9947 tp->bufmgr_config.mbuf_read_dma_low_water);
9948 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9949 tp->bufmgr_config.mbuf_mac_rx_low_water);
9950 tw32(BUFMGR_MB_HIGH_WATER,
9951 tp->bufmgr_config.mbuf_high_water);
9953 tw32(BUFMGR_MB_RDMA_LOW_WATER,
9954 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
9955 tw32(BUFMGR_MB_MACRX_LOW_WATER,
9956 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
9957 tw32(BUFMGR_MB_HIGH_WATER,
9958 tp->bufmgr_config.mbuf_high_water_jumbo);
9960 tw32(BUFMGR_DMA_LOW_WATER,
9961 tp->bufmgr_config.dma_low_water);
9962 tw32(BUFMGR_DMA_HIGH_WATER,
9963 tp->bufmgr_config.dma_high_water);
9965 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
9966 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9967 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
9968 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
9969 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
9970 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
9971 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
9972 tw32(BUFMGR_MODE, val);
9973 for (i = 0; i < 2000; i++) {
9974 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
9979 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
9983 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
9984 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
9986 tg3_setup_rxbd_thresholds(tp);
9988 /* Initialize TG3_BDINFO's at:
9989 * RCVDBDI_STD_BD: standard eth size rx ring
9990 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9991 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9994 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9995 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9996 * ring attribute flags
9997 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9999 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10000 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10002 * The size of each ring is fixed in the firmware, but the location is
10005 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10006 ((u64) tpr->rx_std_mapping >> 32));
10007 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10008 ((u64) tpr->rx_std_mapping & 0xffffffff));
10009 if (!tg3_flag(tp, 5717_PLUS))
10010 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10011 NIC_SRAM_RX_BUFFER_DESC);
10013 /* Disable the mini ring */
10014 if (!tg3_flag(tp, 5705_PLUS))
10015 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10016 BDINFO_FLAGS_DISABLED);
10018 /* Program the jumbo buffer descriptor ring control
10019 * blocks on those devices that have them.
10021 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10022 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10024 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10025 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10026 ((u64) tpr->rx_jmb_mapping >> 32));
10027 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10028 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10029 val = TG3_RX_JMB_RING_SIZE(tp) <<
10030 BDINFO_FLAGS_MAXLEN_SHIFT;
10031 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10032 val | BDINFO_FLAGS_USE_EXT_RECV);
10033 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10034 tg3_flag(tp, 57765_CLASS) ||
10035 tg3_asic_rev(tp) == ASIC_REV_5762)
10036 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10037 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10039 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10040 BDINFO_FLAGS_DISABLED);
10043 if (tg3_flag(tp, 57765_PLUS)) {
10044 val = TG3_RX_STD_RING_SIZE(tp);
10045 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10046 val |= (TG3_RX_STD_DMA_SZ << 2);
10048 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10050 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10052 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10054 tpr->rx_std_prod_idx = tp->rx_pending;
10055 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10057 tpr->rx_jmb_prod_idx =
10058 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10059 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10061 tg3_rings_reset(tp);
10063 /* Initialize MAC address and backoff seed. */
10064 __tg3_set_mac_addr(tp, false);
10066 /* MTU + ethernet header + FCS + optional VLAN tag */
10067 tw32(MAC_RX_MTU_SIZE,
10068 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10070 /* The slot time is changed by tg3_setup_phy if we
10071 * run at gigabit with half duplex.
10073 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10074 (6 << TX_LENGTHS_IPG_SHIFT) |
10075 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10077 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10078 tg3_asic_rev(tp) == ASIC_REV_5762)
10079 val |= tr32(MAC_TX_LENGTHS) &
10080 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10081 TX_LENGTHS_CNT_DWN_VAL_MSK);
10083 tw32(MAC_TX_LENGTHS, val);
10085 /* Receive rules. */
10086 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10087 tw32(RCVLPC_CONFIG, 0x0181);
10089 /* Calculate RDMAC_MODE setting early, we need it to determine
10090 * the RCVLPC_STATE_ENABLE mask.
10092 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10093 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10094 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10095 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10096 RDMAC_MODE_LNGREAD_ENAB);
10098 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10099 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10101 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10102 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10103 tg3_asic_rev(tp) == ASIC_REV_57780)
10104 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10105 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10106 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10108 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10109 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10110 if (tg3_flag(tp, TSO_CAPABLE) &&
10111 tg3_asic_rev(tp) == ASIC_REV_5705) {
10112 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10113 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10114 !tg3_flag(tp, IS_5788)) {
10115 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10119 if (tg3_flag(tp, PCI_EXPRESS))
10120 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10122 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10124 if (tp->dev->mtu <= ETH_DATA_LEN) {
10125 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10126 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10130 if (tg3_flag(tp, HW_TSO_1) ||
10131 tg3_flag(tp, HW_TSO_2) ||
10132 tg3_flag(tp, HW_TSO_3))
10133 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10135 if (tg3_flag(tp, 57765_PLUS) ||
10136 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10137 tg3_asic_rev(tp) == ASIC_REV_57780)
10138 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10140 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10141 tg3_asic_rev(tp) == ASIC_REV_5762)
10142 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10144 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10145 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10146 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10147 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10148 tg3_flag(tp, 57765_PLUS)) {
10151 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10152 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10154 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10156 val = tr32(tgtreg);
10157 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10158 tg3_asic_rev(tp) == ASIC_REV_5762) {
10159 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10160 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10161 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10162 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10163 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10164 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10166 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10169 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10170 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10171 tg3_asic_rev(tp) == ASIC_REV_5762) {
10174 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10175 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10177 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10179 val = tr32(tgtreg);
10181 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10182 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10185 /* Receive/send statistics. */
10186 if (tg3_flag(tp, 5750_PLUS)) {
10187 val = tr32(RCVLPC_STATS_ENABLE);
10188 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10189 tw32(RCVLPC_STATS_ENABLE, val);
10190 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10191 tg3_flag(tp, TSO_CAPABLE)) {
10192 val = tr32(RCVLPC_STATS_ENABLE);
10193 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10194 tw32(RCVLPC_STATS_ENABLE, val);
10196 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10198 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10199 tw32(SNDDATAI_STATSENAB, 0xffffff);
10200 tw32(SNDDATAI_STATSCTRL,
10201 (SNDDATAI_SCTRL_ENABLE |
10202 SNDDATAI_SCTRL_FASTUPD));
10204 /* Setup host coalescing engine. */
10205 tw32(HOSTCC_MODE, 0);
10206 for (i = 0; i < 2000; i++) {
10207 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10212 __tg3_set_coalesce(tp, &tp->coal);
10214 if (!tg3_flag(tp, 5705_PLUS)) {
10215 /* Status/statistics block address. See tg3_timer,
10216 * the tg3_periodic_fetch_stats call there, and
10217 * tg3_get_stats to see how this works for 5705/5750 chips.
10219 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10220 ((u64) tp->stats_mapping >> 32));
10221 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10222 ((u64) tp->stats_mapping & 0xffffffff));
10223 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10225 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10227 /* Clear statistics and status block memory areas */
10228 for (i = NIC_SRAM_STATS_BLK;
10229 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10230 i += sizeof(u32)) {
10231 tg3_write_mem(tp, i, 0);
10236 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10238 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10239 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10240 if (!tg3_flag(tp, 5705_PLUS))
10241 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10243 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10244 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10245 /* reset to prevent losing 1st rx packet intermittently */
10246 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10250 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10251 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10252 MAC_MODE_FHDE_ENABLE;
10253 if (tg3_flag(tp, ENABLE_APE))
10254 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10255 if (!tg3_flag(tp, 5705_PLUS) &&
10256 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10257 tg3_asic_rev(tp) != ASIC_REV_5700)
10258 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10259 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10262 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10263 * If TG3_FLAG_IS_NIC is zero, we should read the
10264 * register to preserve the GPIO settings for LOMs. The GPIOs,
10265 * whether used as inputs or outputs, are set by boot code after
10268 if (!tg3_flag(tp, IS_NIC)) {
10271 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10272 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10273 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10275 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10276 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10277 GRC_LCLCTRL_GPIO_OUTPUT3;
10279 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10280 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10282 tp->grc_local_ctrl &= ~gpio_mask;
10283 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10285 /* GPIO1 must be driven high for eeprom write protect */
10286 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10287 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10288 GRC_LCLCTRL_GPIO_OUTPUT1);
10290 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10293 if (tg3_flag(tp, USING_MSIX)) {
10294 val = tr32(MSGINT_MODE);
10295 val |= MSGINT_MODE_ENABLE;
10296 if (tp->irq_cnt > 1)
10297 val |= MSGINT_MODE_MULTIVEC_EN;
10298 if (!tg3_flag(tp, 1SHOT_MSI))
10299 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10300 tw32(MSGINT_MODE, val);
10303 if (!tg3_flag(tp, 5705_PLUS)) {
10304 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10308 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10309 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10310 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10311 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10312 WDMAC_MODE_LNGREAD_ENAB);
10314 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10315 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10316 if (tg3_flag(tp, TSO_CAPABLE) &&
10317 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10318 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10320 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10321 !tg3_flag(tp, IS_5788)) {
10322 val |= WDMAC_MODE_RX_ACCEL;
10326 /* Enable host coalescing bug fix */
10327 if (tg3_flag(tp, 5755_PLUS))
10328 val |= WDMAC_MODE_STATUS_TAG_FIX;
10330 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10331 val |= WDMAC_MODE_BURST_ALL_DATA;
10333 tw32_f(WDMAC_MODE, val);
10336 if (tg3_flag(tp, PCIX_MODE)) {
10339 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10341 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10342 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10343 pcix_cmd |= PCI_X_CMD_READ_2K;
10344 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10345 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10346 pcix_cmd |= PCI_X_CMD_READ_2K;
10348 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10352 tw32_f(RDMAC_MODE, rdmac_mode);
10355 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10356 tg3_asic_rev(tp) == ASIC_REV_5720) {
10357 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10358 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10361 if (i < TG3_NUM_RDMA_CHANNELS) {
10362 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10363 val |= tg3_lso_rd_dma_workaround_bit(tp);
10364 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10365 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10369 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10370 if (!tg3_flag(tp, 5705_PLUS))
10371 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10373 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10374 tw32(SNDDATAC_MODE,
10375 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10377 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10379 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10380 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10381 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10382 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10383 val |= RCVDBDI_MODE_LRG_RING_SZ;
10384 tw32(RCVDBDI_MODE, val);
10385 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10386 if (tg3_flag(tp, HW_TSO_1) ||
10387 tg3_flag(tp, HW_TSO_2) ||
10388 tg3_flag(tp, HW_TSO_3))
10389 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10390 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10391 if (tg3_flag(tp, ENABLE_TSS))
10392 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10393 tw32(SNDBDI_MODE, val);
10394 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10396 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10397 err = tg3_load_5701_a0_firmware_fix(tp);
10402 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10403 /* Ignore any errors for the firmware download. If download
10404 * fails, the device will operate with EEE disabled
10406 tg3_load_57766_firmware(tp);
10409 if (tg3_flag(tp, TSO_CAPABLE)) {
10410 err = tg3_load_tso_firmware(tp);
10415 tp->tx_mode = TX_MODE_ENABLE;
10417 if (tg3_flag(tp, 5755_PLUS) ||
10418 tg3_asic_rev(tp) == ASIC_REV_5906)
10419 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10421 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10422 tg3_asic_rev(tp) == ASIC_REV_5762) {
10423 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10424 tp->tx_mode &= ~val;
10425 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10428 tw32_f(MAC_TX_MODE, tp->tx_mode);
10431 if (tg3_flag(tp, ENABLE_RSS)) {
10432 tg3_rss_write_indir_tbl(tp);
10434 /* Setup the "secret" hash key. */
10435 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10436 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10437 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10438 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10439 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10440 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10441 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10442 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10443 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10444 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10447 tp->rx_mode = RX_MODE_ENABLE;
10448 if (tg3_flag(tp, 5755_PLUS))
10449 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10451 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10452 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10454 if (tg3_flag(tp, ENABLE_RSS))
10455 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10456 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10457 RX_MODE_RSS_IPV6_HASH_EN |
10458 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10459 RX_MODE_RSS_IPV4_HASH_EN |
10460 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10462 tw32_f(MAC_RX_MODE, tp->rx_mode);
10465 tw32(MAC_LED_CTRL, tp->led_ctrl);
10467 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10468 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10469 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10472 tw32_f(MAC_RX_MODE, tp->rx_mode);
10475 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10476 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10477 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10478 /* Set drive transmission level to 1.2V */
10479 /* only if the signal pre-emphasis bit is not set */
10480 val = tr32(MAC_SERDES_CFG);
10483 tw32(MAC_SERDES_CFG, val);
10485 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10486 tw32(MAC_SERDES_CFG, 0x616000);
10489 /* Prevent chip from dropping frames when flow control
10492 if (tg3_flag(tp, 57765_CLASS))
10496 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10498 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10499 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10500 /* Use hardware link auto-negotiation */
10501 tg3_flag_set(tp, HW_AUTONEG);
10504 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10505 tg3_asic_rev(tp) == ASIC_REV_5714) {
10508 tmp = tr32(SERDES_RX_CTRL);
10509 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10510 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10511 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10515 if (!tg3_flag(tp, USE_PHYLIB)) {
10516 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10517 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10519 err = tg3_setup_phy(tp, false);
10523 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10524 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10527 /* Clear CRC stats. */
10528 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10529 tg3_writephy(tp, MII_TG3_TEST1,
10530 tmp | MII_TG3_TEST1_CRC_EN);
10531 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10536 __tg3_set_rx_mode(tp->dev);
10538 /* Initialize receive rules. */
10539 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10540 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10541 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10542 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10544 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10548 if (tg3_flag(tp, ENABLE_ASF))
10552 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10554 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10556 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10558 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10560 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10562 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10564 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10566 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10568 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10570 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10572 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10574 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10576 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10578 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10586 if (tg3_flag(tp, ENABLE_APE))
10587 /* Write our heartbeat update interval to APE. */
10588 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10589 APE_HOST_HEARTBEAT_INT_DISABLE);
10591 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10596 /* Called at device open time to get the chip ready for
10597 * packet processing. Invoked with tp->lock held.
10599 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10601 /* Chip may have been just powered on. If so, the boot code may still
10602 * be running initialization. Wait for it to finish to avoid races in
10603 * accessing the hardware.
10605 tg3_enable_register_access(tp);
10608 tg3_switch_clocks(tp);
10610 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10612 return tg3_reset_hw(tp, reset_phy);
10615 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10619 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10620 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10622 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10625 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10626 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10627 memset(ocir, 0, TG3_OCIR_LEN);
10631 /* sysfs attributes for hwmon */
10632 static ssize_t tg3_show_temp(struct device *dev,
10633 struct device_attribute *devattr, char *buf)
10635 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10636 struct tg3 *tp = dev_get_drvdata(dev);
10639 spin_lock_bh(&tp->lock);
10640 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10641 sizeof(temperature));
10642 spin_unlock_bh(&tp->lock);
10643 return sprintf(buf, "%u\n", temperature);
10647 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10648 TG3_TEMP_SENSOR_OFFSET);
10649 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10650 TG3_TEMP_CAUTION_OFFSET);
10651 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10652 TG3_TEMP_MAX_OFFSET);
10654 static struct attribute *tg3_attrs[] = {
10655 &sensor_dev_attr_temp1_input.dev_attr.attr,
10656 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10657 &sensor_dev_attr_temp1_max.dev_attr.attr,
10660 ATTRIBUTE_GROUPS(tg3);
10662 static void tg3_hwmon_close(struct tg3 *tp)
10664 if (tp->hwmon_dev) {
10665 hwmon_device_unregister(tp->hwmon_dev);
10666 tp->hwmon_dev = NULL;
10670 static void tg3_hwmon_open(struct tg3 *tp)
10674 struct pci_dev *pdev = tp->pdev;
10675 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10677 tg3_sd_scan_scratchpad(tp, ocirs);
10679 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10680 if (!ocirs[i].src_data_length)
10683 size += ocirs[i].src_hdr_length;
10684 size += ocirs[i].src_data_length;
10690 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10692 if (IS_ERR(tp->hwmon_dev)) {
10693 tp->hwmon_dev = NULL;
10694 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10699 #define TG3_STAT_ADD32(PSTAT, REG) \
10700 do { u32 __val = tr32(REG); \
10701 (PSTAT)->low += __val; \
10702 if ((PSTAT)->low < __val) \
10703 (PSTAT)->high += 1; \
10706 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10708 struct tg3_hw_stats *sp = tp->hw_stats;
10713 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10714 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10715 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10716 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10717 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10718 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10719 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10720 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10721 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10722 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10723 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10724 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10725 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10726 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10727 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10728 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10731 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10732 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10733 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10734 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10737 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10738 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10739 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10740 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10741 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10742 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10743 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10744 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10745 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10746 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10747 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10748 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10749 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10750 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10752 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10753 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10754 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10755 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10756 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10758 u32 val = tr32(HOSTCC_FLOW_ATTN);
10759 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10761 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10762 sp->rx_discards.low += val;
10763 if (sp->rx_discards.low < val)
10764 sp->rx_discards.high += 1;
10766 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10768 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10771 static void tg3_chk_missed_msi(struct tg3 *tp)
10775 for (i = 0; i < tp->irq_cnt; i++) {
10776 struct tg3_napi *tnapi = &tp->napi[i];
10778 if (tg3_has_work(tnapi)) {
10779 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10780 tnapi->last_tx_cons == tnapi->tx_cons) {
10781 if (tnapi->chk_msi_cnt < 1) {
10782 tnapi->chk_msi_cnt++;
10788 tnapi->chk_msi_cnt = 0;
10789 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10790 tnapi->last_tx_cons = tnapi->tx_cons;
10794 static void tg3_timer(unsigned long __opaque)
10796 struct tg3 *tp = (struct tg3 *) __opaque;
10798 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10799 goto restart_timer;
10801 spin_lock(&tp->lock);
10803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10804 tg3_flag(tp, 57765_CLASS))
10805 tg3_chk_missed_msi(tp);
10807 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10808 /* BCM4785: Flush posted writes from GbE to host memory. */
10812 if (!tg3_flag(tp, TAGGED_STATUS)) {
10813 /* All of this garbage is because when using non-tagged
10814 * IRQ status the mailbox/status_block protocol the chip
10815 * uses with the cpu is race prone.
10817 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10818 tw32(GRC_LOCAL_CTRL,
10819 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10821 tw32(HOSTCC_MODE, tp->coalesce_mode |
10822 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10825 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10826 spin_unlock(&tp->lock);
10827 tg3_reset_task_schedule(tp);
10828 goto restart_timer;
10832 /* This part only runs once per second. */
10833 if (!--tp->timer_counter) {
10834 if (tg3_flag(tp, 5705_PLUS))
10835 tg3_periodic_fetch_stats(tp);
10837 if (tp->setlpicnt && !--tp->setlpicnt)
10838 tg3_phy_eee_enable(tp);
10840 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10844 mac_stat = tr32(MAC_STATUS);
10847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10848 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10850 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10854 tg3_setup_phy(tp, false);
10855 } else if (tg3_flag(tp, POLL_SERDES)) {
10856 u32 mac_stat = tr32(MAC_STATUS);
10857 int need_setup = 0;
10860 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10863 if (!tp->link_up &&
10864 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10865 MAC_STATUS_SIGNAL_DET))) {
10869 if (!tp->serdes_counter) {
10872 ~MAC_MODE_PORT_MODE_MASK));
10874 tw32_f(MAC_MODE, tp->mac_mode);
10877 tg3_setup_phy(tp, false);
10879 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10880 tg3_flag(tp, 5780_CLASS)) {
10881 tg3_serdes_parallel_detect(tp);
10884 tp->timer_counter = tp->timer_multiplier;
10887 /* Heartbeat is only sent once every 2 seconds.
10889 * The heartbeat is to tell the ASF firmware that the host
10890 * driver is still alive. In the event that the OS crashes,
10891 * ASF needs to reset the hardware to free up the FIFO space
10892 * that may be filled with rx packets destined for the host.
10893 * If the FIFO is full, ASF will no longer function properly.
10895 * Unintended resets have been reported on real time kernels
10896 * where the timer doesn't run on time. Netpoll will also have
10899 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10900 * to check the ring condition when the heartbeat is expiring
10901 * before doing the reset. This will prevent most unintended
10904 if (!--tp->asf_counter) {
10905 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
10906 tg3_wait_for_event_ack(tp);
10908 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
10909 FWCMD_NICDRV_ALIVE3);
10910 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
10911 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
10912 TG3_FW_UPDATE_TIMEOUT_SEC);
10914 tg3_generate_fw_event(tp);
10916 tp->asf_counter = tp->asf_multiplier;
10919 spin_unlock(&tp->lock);
10922 tp->timer.expires = jiffies + tp->timer_offset;
10923 add_timer(&tp->timer);
10926 static void tg3_timer_init(struct tg3 *tp)
10928 if (tg3_flag(tp, TAGGED_STATUS) &&
10929 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10930 !tg3_flag(tp, 57765_CLASS))
10931 tp->timer_offset = HZ;
10933 tp->timer_offset = HZ / 10;
10935 BUG_ON(tp->timer_offset > HZ);
10937 tp->timer_multiplier = (HZ / tp->timer_offset);
10938 tp->asf_multiplier = (HZ / tp->timer_offset) *
10939 TG3_FW_UPDATE_FREQ_SEC;
10941 init_timer(&tp->timer);
10942 tp->timer.data = (unsigned long) tp;
10943 tp->timer.function = tg3_timer;
10946 static void tg3_timer_start(struct tg3 *tp)
10948 tp->asf_counter = tp->asf_multiplier;
10949 tp->timer_counter = tp->timer_multiplier;
10951 tp->timer.expires = jiffies + tp->timer_offset;
10952 add_timer(&tp->timer);
10955 static void tg3_timer_stop(struct tg3 *tp)
10957 del_timer_sync(&tp->timer);
10960 /* Restart hardware after configuration changes, self-test, etc.
10961 * Invoked with tp->lock held.
10963 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
10964 __releases(tp->lock)
10965 __acquires(tp->lock)
10969 err = tg3_init_hw(tp, reset_phy);
10971 netdev_err(tp->dev,
10972 "Failed to re-initialize device, aborting\n");
10973 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10974 tg3_full_unlock(tp);
10975 tg3_timer_stop(tp);
10977 tg3_napi_enable(tp);
10978 dev_close(tp->dev);
10979 tg3_full_lock(tp, 0);
10984 static void tg3_reset_task(struct work_struct *work)
10986 struct tg3 *tp = container_of(work, struct tg3, reset_task);
10989 tg3_full_lock(tp, 0);
10991 if (!netif_running(tp->dev)) {
10992 tg3_flag_clear(tp, RESET_TASK_PENDING);
10993 tg3_full_unlock(tp);
10997 tg3_full_unlock(tp);
11001 tg3_netif_stop(tp);
11003 tg3_full_lock(tp, 1);
11005 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11006 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11007 tp->write32_rx_mbox = tg3_write_flush_reg32;
11008 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11009 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11012 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11013 err = tg3_init_hw(tp, true);
11017 tg3_netif_start(tp);
11020 tg3_full_unlock(tp);
11025 tg3_flag_clear(tp, RESET_TASK_PENDING);
11028 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11031 unsigned long flags;
11033 struct tg3_napi *tnapi = &tp->napi[irq_num];
11035 if (tp->irq_cnt == 1)
11036 name = tp->dev->name;
11038 name = &tnapi->irq_lbl[0];
11039 if (tnapi->tx_buffers && tnapi->rx_rcb)
11040 snprintf(name, IFNAMSIZ,
11041 "%s-txrx-%d", tp->dev->name, irq_num);
11042 else if (tnapi->tx_buffers)
11043 snprintf(name, IFNAMSIZ,
11044 "%s-tx-%d", tp->dev->name, irq_num);
11045 else if (tnapi->rx_rcb)
11046 snprintf(name, IFNAMSIZ,
11047 "%s-rx-%d", tp->dev->name, irq_num);
11049 snprintf(name, IFNAMSIZ,
11050 "%s-%d", tp->dev->name, irq_num);
11051 name[IFNAMSIZ-1] = 0;
11054 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11056 if (tg3_flag(tp, 1SHOT_MSI))
11057 fn = tg3_msi_1shot;
11060 fn = tg3_interrupt;
11061 if (tg3_flag(tp, TAGGED_STATUS))
11062 fn = tg3_interrupt_tagged;
11063 flags = IRQF_SHARED;
11066 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11069 static int tg3_test_interrupt(struct tg3 *tp)
11071 struct tg3_napi *tnapi = &tp->napi[0];
11072 struct net_device *dev = tp->dev;
11073 int err, i, intr_ok = 0;
11076 if (!netif_running(dev))
11079 tg3_disable_ints(tp);
11081 free_irq(tnapi->irq_vec, tnapi);
11084 * Turn off MSI one shot mode. Otherwise this test has no
11085 * observable way to know whether the interrupt was delivered.
11087 if (tg3_flag(tp, 57765_PLUS)) {
11088 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11089 tw32(MSGINT_MODE, val);
11092 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11093 IRQF_SHARED, dev->name, tnapi);
11097 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11098 tg3_enable_ints(tp);
11100 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11103 for (i = 0; i < 5; i++) {
11104 u32 int_mbox, misc_host_ctrl;
11106 int_mbox = tr32_mailbox(tnapi->int_mbox);
11107 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11109 if ((int_mbox != 0) ||
11110 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11115 if (tg3_flag(tp, 57765_PLUS) &&
11116 tnapi->hw_status->status_tag != tnapi->last_tag)
11117 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11122 tg3_disable_ints(tp);
11124 free_irq(tnapi->irq_vec, tnapi);
11126 err = tg3_request_irq(tp, 0);
11132 /* Reenable MSI one shot mode. */
11133 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11134 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11135 tw32(MSGINT_MODE, val);
11143 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11144 * successfully restored
11146 static int tg3_test_msi(struct tg3 *tp)
11151 if (!tg3_flag(tp, USING_MSI))
11154 /* Turn off SERR reporting in case MSI terminates with Master
11157 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11158 pci_write_config_word(tp->pdev, PCI_COMMAND,
11159 pci_cmd & ~PCI_COMMAND_SERR);
11161 err = tg3_test_interrupt(tp);
11163 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11168 /* other failures */
11172 /* MSI test failed, go back to INTx mode */
11173 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11174 "to INTx mode. Please report this failure to the PCI "
11175 "maintainer and include system chipset information\n");
11177 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11179 pci_disable_msi(tp->pdev);
11181 tg3_flag_clear(tp, USING_MSI);
11182 tp->napi[0].irq_vec = tp->pdev->irq;
11184 err = tg3_request_irq(tp, 0);
11188 /* Need to reset the chip because the MSI cycle may have terminated
11189 * with Master Abort.
11191 tg3_full_lock(tp, 1);
11193 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11194 err = tg3_init_hw(tp, true);
11196 tg3_full_unlock(tp);
11199 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11204 static int tg3_request_firmware(struct tg3 *tp)
11206 const struct tg3_firmware_hdr *fw_hdr;
11208 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11209 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11214 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11216 /* Firmware blob starts with version numbers, followed by
11217 * start address and _full_ length including BSS sections
11218 * (which must be longer than the actual data, of course
11221 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11222 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11223 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11224 tp->fw_len, tp->fw_needed);
11225 release_firmware(tp->fw);
11230 /* We no longer need firmware; we have it. */
11231 tp->fw_needed = NULL;
11235 static u32 tg3_irq_count(struct tg3 *tp)
11237 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11240 /* We want as many rx rings enabled as there are cpus.
11241 * In multiqueue MSI-X mode, the first MSI-X vector
11242 * only deals with link interrupts, etc, so we add
11243 * one to the number of vectors we are requesting.
11245 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11251 static bool tg3_enable_msix(struct tg3 *tp)
11254 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11256 tp->txq_cnt = tp->txq_req;
11257 tp->rxq_cnt = tp->rxq_req;
11259 tp->rxq_cnt = netif_get_num_default_rss_queues();
11260 if (tp->rxq_cnt > tp->rxq_max)
11261 tp->rxq_cnt = tp->rxq_max;
11263 /* Disable multiple TX rings by default. Simple round-robin hardware
11264 * scheduling of the TX rings can cause starvation of rings with
11265 * small packets when other rings have TSO or jumbo packets.
11270 tp->irq_cnt = tg3_irq_count(tp);
11272 for (i = 0; i < tp->irq_max; i++) {
11273 msix_ent[i].entry = i;
11274 msix_ent[i].vector = 0;
11277 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
11280 } else if (rc != 0) {
11281 if (pci_enable_msix(tp->pdev, msix_ent, rc))
11283 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11286 tp->rxq_cnt = max(rc - 1, 1);
11288 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11291 for (i = 0; i < tp->irq_max; i++)
11292 tp->napi[i].irq_vec = msix_ent[i].vector;
11294 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11295 pci_disable_msix(tp->pdev);
11299 if (tp->irq_cnt == 1)
11302 tg3_flag_set(tp, ENABLE_RSS);
11304 if (tp->txq_cnt > 1)
11305 tg3_flag_set(tp, ENABLE_TSS);
11307 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11312 static void tg3_ints_init(struct tg3 *tp)
11314 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11315 !tg3_flag(tp, TAGGED_STATUS)) {
11316 /* All MSI supporting chips should support tagged
11317 * status. Assert that this is the case.
11319 netdev_warn(tp->dev,
11320 "MSI without TAGGED_STATUS? Not using MSI\n");
11324 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11325 tg3_flag_set(tp, USING_MSIX);
11326 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11327 tg3_flag_set(tp, USING_MSI);
11329 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11330 u32 msi_mode = tr32(MSGINT_MODE);
11331 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11332 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11333 if (!tg3_flag(tp, 1SHOT_MSI))
11334 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11335 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11338 if (!tg3_flag(tp, USING_MSIX)) {
11340 tp->napi[0].irq_vec = tp->pdev->irq;
11343 if (tp->irq_cnt == 1) {
11346 netif_set_real_num_tx_queues(tp->dev, 1);
11347 netif_set_real_num_rx_queues(tp->dev, 1);
11351 static void tg3_ints_fini(struct tg3 *tp)
11353 if (tg3_flag(tp, USING_MSIX))
11354 pci_disable_msix(tp->pdev);
11355 else if (tg3_flag(tp, USING_MSI))
11356 pci_disable_msi(tp->pdev);
11357 tg3_flag_clear(tp, USING_MSI);
11358 tg3_flag_clear(tp, USING_MSIX);
11359 tg3_flag_clear(tp, ENABLE_RSS);
11360 tg3_flag_clear(tp, ENABLE_TSS);
11363 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11366 struct net_device *dev = tp->dev;
11370 * Setup interrupts first so we know how
11371 * many NAPI resources to allocate
11375 tg3_rss_check_indir_tbl(tp);
11377 /* The placement of this call is tied
11378 * to the setup and use of Host TX descriptors.
11380 err = tg3_alloc_consistent(tp);
11382 goto out_ints_fini;
11386 tg3_napi_enable(tp);
11388 for (i = 0; i < tp->irq_cnt; i++) {
11389 struct tg3_napi *tnapi = &tp->napi[i];
11390 err = tg3_request_irq(tp, i);
11392 for (i--; i >= 0; i--) {
11393 tnapi = &tp->napi[i];
11394 free_irq(tnapi->irq_vec, tnapi);
11396 goto out_napi_fini;
11400 tg3_full_lock(tp, 0);
11403 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11405 err = tg3_init_hw(tp, reset_phy);
11407 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11408 tg3_free_rings(tp);
11411 tg3_full_unlock(tp);
11416 if (test_irq && tg3_flag(tp, USING_MSI)) {
11417 err = tg3_test_msi(tp);
11420 tg3_full_lock(tp, 0);
11421 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11422 tg3_free_rings(tp);
11423 tg3_full_unlock(tp);
11425 goto out_napi_fini;
11428 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11429 u32 val = tr32(PCIE_TRANSACTION_CFG);
11431 tw32(PCIE_TRANSACTION_CFG,
11432 val | PCIE_TRANS_CFG_1SHOT_MSI);
11438 tg3_hwmon_open(tp);
11440 tg3_full_lock(tp, 0);
11442 tg3_timer_start(tp);
11443 tg3_flag_set(tp, INIT_COMPLETE);
11444 tg3_enable_ints(tp);
11449 tg3_ptp_resume(tp);
11452 tg3_full_unlock(tp);
11454 netif_tx_start_all_queues(dev);
11457 * Reset loopback feature if it was turned on while the device was down
11458 * make sure that it's installed properly now.
11460 if (dev->features & NETIF_F_LOOPBACK)
11461 tg3_set_loopback(dev, dev->features);
11466 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11467 struct tg3_napi *tnapi = &tp->napi[i];
11468 free_irq(tnapi->irq_vec, tnapi);
11472 tg3_napi_disable(tp);
11474 tg3_free_consistent(tp);
11482 static void tg3_stop(struct tg3 *tp)
11486 tg3_reset_task_cancel(tp);
11487 tg3_netif_stop(tp);
11489 tg3_timer_stop(tp);
11491 tg3_hwmon_close(tp);
11495 tg3_full_lock(tp, 1);
11497 tg3_disable_ints(tp);
11499 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11500 tg3_free_rings(tp);
11501 tg3_flag_clear(tp, INIT_COMPLETE);
11503 tg3_full_unlock(tp);
11505 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11506 struct tg3_napi *tnapi = &tp->napi[i];
11507 free_irq(tnapi->irq_vec, tnapi);
11514 tg3_free_consistent(tp);
11517 static int tg3_open(struct net_device *dev)
11519 struct tg3 *tp = netdev_priv(dev);
11522 if (tp->fw_needed) {
11523 err = tg3_request_firmware(tp);
11524 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11526 netdev_warn(tp->dev, "EEE capability disabled\n");
11527 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11528 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11529 netdev_warn(tp->dev, "EEE capability restored\n");
11530 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11532 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11536 netdev_warn(tp->dev, "TSO capability disabled\n");
11537 tg3_flag_clear(tp, TSO_CAPABLE);
11538 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11539 netdev_notice(tp->dev, "TSO capability restored\n");
11540 tg3_flag_set(tp, TSO_CAPABLE);
11544 tg3_carrier_off(tp);
11546 err = tg3_power_up(tp);
11550 tg3_full_lock(tp, 0);
11552 tg3_disable_ints(tp);
11553 tg3_flag_clear(tp, INIT_COMPLETE);
11555 tg3_full_unlock(tp);
11557 err = tg3_start(tp,
11558 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11561 tg3_frob_aux_power(tp, false);
11562 pci_set_power_state(tp->pdev, PCI_D3hot);
11565 if (tg3_flag(tp, PTP_CAPABLE)) {
11566 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11568 if (IS_ERR(tp->ptp_clock))
11569 tp->ptp_clock = NULL;
11575 static int tg3_close(struct net_device *dev)
11577 struct tg3 *tp = netdev_priv(dev);
11583 /* Clear stats across close / open calls */
11584 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11585 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11587 if (pci_device_is_present(tp->pdev)) {
11588 tg3_power_down_prepare(tp);
11590 tg3_carrier_off(tp);
11595 static inline u64 get_stat64(tg3_stat64_t *val)
11597 return ((u64)val->high << 32) | ((u64)val->low);
11600 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11602 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11604 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11605 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11606 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11609 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11610 tg3_writephy(tp, MII_TG3_TEST1,
11611 val | MII_TG3_TEST1_CRC_EN);
11612 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11616 tp->phy_crc_errors += val;
11618 return tp->phy_crc_errors;
11621 return get_stat64(&hw_stats->rx_fcs_errors);
11624 #define ESTAT_ADD(member) \
11625 estats->member = old_estats->member + \
11626 get_stat64(&hw_stats->member)
11628 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11630 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11631 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11633 ESTAT_ADD(rx_octets);
11634 ESTAT_ADD(rx_fragments);
11635 ESTAT_ADD(rx_ucast_packets);
11636 ESTAT_ADD(rx_mcast_packets);
11637 ESTAT_ADD(rx_bcast_packets);
11638 ESTAT_ADD(rx_fcs_errors);
11639 ESTAT_ADD(rx_align_errors);
11640 ESTAT_ADD(rx_xon_pause_rcvd);
11641 ESTAT_ADD(rx_xoff_pause_rcvd);
11642 ESTAT_ADD(rx_mac_ctrl_rcvd);
11643 ESTAT_ADD(rx_xoff_entered);
11644 ESTAT_ADD(rx_frame_too_long_errors);
11645 ESTAT_ADD(rx_jabbers);
11646 ESTAT_ADD(rx_undersize_packets);
11647 ESTAT_ADD(rx_in_length_errors);
11648 ESTAT_ADD(rx_out_length_errors);
11649 ESTAT_ADD(rx_64_or_less_octet_packets);
11650 ESTAT_ADD(rx_65_to_127_octet_packets);
11651 ESTAT_ADD(rx_128_to_255_octet_packets);
11652 ESTAT_ADD(rx_256_to_511_octet_packets);
11653 ESTAT_ADD(rx_512_to_1023_octet_packets);
11654 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11655 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11656 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11657 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11658 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11660 ESTAT_ADD(tx_octets);
11661 ESTAT_ADD(tx_collisions);
11662 ESTAT_ADD(tx_xon_sent);
11663 ESTAT_ADD(tx_xoff_sent);
11664 ESTAT_ADD(tx_flow_control);
11665 ESTAT_ADD(tx_mac_errors);
11666 ESTAT_ADD(tx_single_collisions);
11667 ESTAT_ADD(tx_mult_collisions);
11668 ESTAT_ADD(tx_deferred);
11669 ESTAT_ADD(tx_excessive_collisions);
11670 ESTAT_ADD(tx_late_collisions);
11671 ESTAT_ADD(tx_collide_2times);
11672 ESTAT_ADD(tx_collide_3times);
11673 ESTAT_ADD(tx_collide_4times);
11674 ESTAT_ADD(tx_collide_5times);
11675 ESTAT_ADD(tx_collide_6times);
11676 ESTAT_ADD(tx_collide_7times);
11677 ESTAT_ADD(tx_collide_8times);
11678 ESTAT_ADD(tx_collide_9times);
11679 ESTAT_ADD(tx_collide_10times);
11680 ESTAT_ADD(tx_collide_11times);
11681 ESTAT_ADD(tx_collide_12times);
11682 ESTAT_ADD(tx_collide_13times);
11683 ESTAT_ADD(tx_collide_14times);
11684 ESTAT_ADD(tx_collide_15times);
11685 ESTAT_ADD(tx_ucast_packets);
11686 ESTAT_ADD(tx_mcast_packets);
11687 ESTAT_ADD(tx_bcast_packets);
11688 ESTAT_ADD(tx_carrier_sense_errors);
11689 ESTAT_ADD(tx_discards);
11690 ESTAT_ADD(tx_errors);
11692 ESTAT_ADD(dma_writeq_full);
11693 ESTAT_ADD(dma_write_prioq_full);
11694 ESTAT_ADD(rxbds_empty);
11695 ESTAT_ADD(rx_discards);
11696 ESTAT_ADD(rx_errors);
11697 ESTAT_ADD(rx_threshold_hit);
11699 ESTAT_ADD(dma_readq_full);
11700 ESTAT_ADD(dma_read_prioq_full);
11701 ESTAT_ADD(tx_comp_queue_full);
11703 ESTAT_ADD(ring_set_send_prod_index);
11704 ESTAT_ADD(ring_status_update);
11705 ESTAT_ADD(nic_irqs);
11706 ESTAT_ADD(nic_avoided_irqs);
11707 ESTAT_ADD(nic_tx_threshold_hit);
11709 ESTAT_ADD(mbuf_lwm_thresh_hit);
11712 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11714 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11715 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11717 stats->rx_packets = old_stats->rx_packets +
11718 get_stat64(&hw_stats->rx_ucast_packets) +
11719 get_stat64(&hw_stats->rx_mcast_packets) +
11720 get_stat64(&hw_stats->rx_bcast_packets);
11722 stats->tx_packets = old_stats->tx_packets +
11723 get_stat64(&hw_stats->tx_ucast_packets) +
11724 get_stat64(&hw_stats->tx_mcast_packets) +
11725 get_stat64(&hw_stats->tx_bcast_packets);
11727 stats->rx_bytes = old_stats->rx_bytes +
11728 get_stat64(&hw_stats->rx_octets);
11729 stats->tx_bytes = old_stats->tx_bytes +
11730 get_stat64(&hw_stats->tx_octets);
11732 stats->rx_errors = old_stats->rx_errors +
11733 get_stat64(&hw_stats->rx_errors);
11734 stats->tx_errors = old_stats->tx_errors +
11735 get_stat64(&hw_stats->tx_errors) +
11736 get_stat64(&hw_stats->tx_mac_errors) +
11737 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11738 get_stat64(&hw_stats->tx_discards);
11740 stats->multicast = old_stats->multicast +
11741 get_stat64(&hw_stats->rx_mcast_packets);
11742 stats->collisions = old_stats->collisions +
11743 get_stat64(&hw_stats->tx_collisions);
11745 stats->rx_length_errors = old_stats->rx_length_errors +
11746 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11747 get_stat64(&hw_stats->rx_undersize_packets);
11749 stats->rx_over_errors = old_stats->rx_over_errors +
11750 get_stat64(&hw_stats->rxbds_empty);
11751 stats->rx_frame_errors = old_stats->rx_frame_errors +
11752 get_stat64(&hw_stats->rx_align_errors);
11753 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11754 get_stat64(&hw_stats->tx_discards);
11755 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11756 get_stat64(&hw_stats->tx_carrier_sense_errors);
11758 stats->rx_crc_errors = old_stats->rx_crc_errors +
11759 tg3_calc_crc_errors(tp);
11761 stats->rx_missed_errors = old_stats->rx_missed_errors +
11762 get_stat64(&hw_stats->rx_discards);
11764 stats->rx_dropped = tp->rx_dropped;
11765 stats->tx_dropped = tp->tx_dropped;
11768 static int tg3_get_regs_len(struct net_device *dev)
11770 return TG3_REG_BLK_SIZE;
11773 static void tg3_get_regs(struct net_device *dev,
11774 struct ethtool_regs *regs, void *_p)
11776 struct tg3 *tp = netdev_priv(dev);
11780 memset(_p, 0, TG3_REG_BLK_SIZE);
11782 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11785 tg3_full_lock(tp, 0);
11787 tg3_dump_legacy_regs(tp, (u32 *)_p);
11789 tg3_full_unlock(tp);
11792 static int tg3_get_eeprom_len(struct net_device *dev)
11794 struct tg3 *tp = netdev_priv(dev);
11796 return tp->nvram_size;
11799 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11801 struct tg3 *tp = netdev_priv(dev);
11804 u32 i, offset, len, b_offset, b_count;
11807 if (tg3_flag(tp, NO_NVRAM))
11810 offset = eeprom->offset;
11814 eeprom->magic = TG3_EEPROM_MAGIC;
11817 /* adjustments to start on required 4 byte boundary */
11818 b_offset = offset & 3;
11819 b_count = 4 - b_offset;
11820 if (b_count > len) {
11821 /* i.e. offset=1 len=2 */
11824 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11827 memcpy(data, ((char *)&val) + b_offset, b_count);
11830 eeprom->len += b_count;
11833 /* read bytes up to the last 4 byte boundary */
11834 pd = &data[eeprom->len];
11835 for (i = 0; i < (len - (len & 3)); i += 4) {
11836 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11841 memcpy(pd + i, &val, 4);
11846 /* read last bytes not ending on 4 byte boundary */
11847 pd = &data[eeprom->len];
11849 b_offset = offset + len - b_count;
11850 ret = tg3_nvram_read_be32(tp, b_offset, &val);
11853 memcpy(pd, &val, b_count);
11854 eeprom->len += b_count;
11859 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11861 struct tg3 *tp = netdev_priv(dev);
11863 u32 offset, len, b_offset, odd_len;
11867 if (tg3_flag(tp, NO_NVRAM) ||
11868 eeprom->magic != TG3_EEPROM_MAGIC)
11871 offset = eeprom->offset;
11874 if ((b_offset = (offset & 3))) {
11875 /* adjustments to start on required 4 byte boundary */
11876 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
11887 /* adjustments to end on required 4 byte boundary */
11889 len = (len + 3) & ~3;
11890 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
11896 if (b_offset || odd_len) {
11897 buf = kmalloc(len, GFP_KERNEL);
11901 memcpy(buf, &start, 4);
11903 memcpy(buf+len-4, &end, 4);
11904 memcpy(buf + b_offset, data, eeprom->len);
11907 ret = tg3_nvram_write_block(tp, offset, len, buf);
11915 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11917 struct tg3 *tp = netdev_priv(dev);
11919 if (tg3_flag(tp, USE_PHYLIB)) {
11920 struct phy_device *phydev;
11921 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11923 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
11924 return phy_ethtool_gset(phydev, cmd);
11927 cmd->supported = (SUPPORTED_Autoneg);
11929 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
11930 cmd->supported |= (SUPPORTED_1000baseT_Half |
11931 SUPPORTED_1000baseT_Full);
11933 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11934 cmd->supported |= (SUPPORTED_100baseT_Half |
11935 SUPPORTED_100baseT_Full |
11936 SUPPORTED_10baseT_Half |
11937 SUPPORTED_10baseT_Full |
11939 cmd->port = PORT_TP;
11941 cmd->supported |= SUPPORTED_FIBRE;
11942 cmd->port = PORT_FIBRE;
11945 cmd->advertising = tp->link_config.advertising;
11946 if (tg3_flag(tp, PAUSE_AUTONEG)) {
11947 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
11948 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11949 cmd->advertising |= ADVERTISED_Pause;
11951 cmd->advertising |= ADVERTISED_Pause |
11952 ADVERTISED_Asym_Pause;
11954 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
11955 cmd->advertising |= ADVERTISED_Asym_Pause;
11958 if (netif_running(dev) && tp->link_up) {
11959 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
11960 cmd->duplex = tp->link_config.active_duplex;
11961 cmd->lp_advertising = tp->link_config.rmt_adv;
11962 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
11963 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
11964 cmd->eth_tp_mdix = ETH_TP_MDI_X;
11966 cmd->eth_tp_mdix = ETH_TP_MDI;
11969 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
11970 cmd->duplex = DUPLEX_UNKNOWN;
11971 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
11973 cmd->phy_address = tp->phy_addr;
11974 cmd->transceiver = XCVR_INTERNAL;
11975 cmd->autoneg = tp->link_config.autoneg;
11981 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
11983 struct tg3 *tp = netdev_priv(dev);
11984 u32 speed = ethtool_cmd_speed(cmd);
11986 if (tg3_flag(tp, USE_PHYLIB)) {
11987 struct phy_device *phydev;
11988 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11990 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
11991 return phy_ethtool_sset(phydev, cmd);
11994 if (cmd->autoneg != AUTONEG_ENABLE &&
11995 cmd->autoneg != AUTONEG_DISABLE)
11998 if (cmd->autoneg == AUTONEG_DISABLE &&
11999 cmd->duplex != DUPLEX_FULL &&
12000 cmd->duplex != DUPLEX_HALF)
12003 if (cmd->autoneg == AUTONEG_ENABLE) {
12004 u32 mask = ADVERTISED_Autoneg |
12006 ADVERTISED_Asym_Pause;
12008 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12009 mask |= ADVERTISED_1000baseT_Half |
12010 ADVERTISED_1000baseT_Full;
12012 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12013 mask |= ADVERTISED_100baseT_Half |
12014 ADVERTISED_100baseT_Full |
12015 ADVERTISED_10baseT_Half |
12016 ADVERTISED_10baseT_Full |
12019 mask |= ADVERTISED_FIBRE;
12021 if (cmd->advertising & ~mask)
12024 mask &= (ADVERTISED_1000baseT_Half |
12025 ADVERTISED_1000baseT_Full |
12026 ADVERTISED_100baseT_Half |
12027 ADVERTISED_100baseT_Full |
12028 ADVERTISED_10baseT_Half |
12029 ADVERTISED_10baseT_Full);
12031 cmd->advertising &= mask;
12033 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12034 if (speed != SPEED_1000)
12037 if (cmd->duplex != DUPLEX_FULL)
12040 if (speed != SPEED_100 &&
12046 tg3_full_lock(tp, 0);
12048 tp->link_config.autoneg = cmd->autoneg;
12049 if (cmd->autoneg == AUTONEG_ENABLE) {
12050 tp->link_config.advertising = (cmd->advertising |
12051 ADVERTISED_Autoneg);
12052 tp->link_config.speed = SPEED_UNKNOWN;
12053 tp->link_config.duplex = DUPLEX_UNKNOWN;
12055 tp->link_config.advertising = 0;
12056 tp->link_config.speed = speed;
12057 tp->link_config.duplex = cmd->duplex;
12060 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12062 tg3_warn_mgmt_link_flap(tp);
12064 if (netif_running(dev))
12065 tg3_setup_phy(tp, true);
12067 tg3_full_unlock(tp);
12072 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12074 struct tg3 *tp = netdev_priv(dev);
12076 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12077 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12078 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12079 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12082 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12084 struct tg3 *tp = netdev_priv(dev);
12086 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12087 wol->supported = WAKE_MAGIC;
12089 wol->supported = 0;
12091 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12092 wol->wolopts = WAKE_MAGIC;
12093 memset(&wol->sopass, 0, sizeof(wol->sopass));
12096 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12098 struct tg3 *tp = netdev_priv(dev);
12099 struct device *dp = &tp->pdev->dev;
12101 if (wol->wolopts & ~WAKE_MAGIC)
12103 if ((wol->wolopts & WAKE_MAGIC) &&
12104 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12107 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12109 if (device_may_wakeup(dp))
12110 tg3_flag_set(tp, WOL_ENABLE);
12112 tg3_flag_clear(tp, WOL_ENABLE);
12117 static u32 tg3_get_msglevel(struct net_device *dev)
12119 struct tg3 *tp = netdev_priv(dev);
12120 return tp->msg_enable;
12123 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12125 struct tg3 *tp = netdev_priv(dev);
12126 tp->msg_enable = value;
12129 static int tg3_nway_reset(struct net_device *dev)
12131 struct tg3 *tp = netdev_priv(dev);
12134 if (!netif_running(dev))
12137 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12140 tg3_warn_mgmt_link_flap(tp);
12142 if (tg3_flag(tp, USE_PHYLIB)) {
12143 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12145 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12149 spin_lock_bh(&tp->lock);
12151 tg3_readphy(tp, MII_BMCR, &bmcr);
12152 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12153 ((bmcr & BMCR_ANENABLE) ||
12154 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12155 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12159 spin_unlock_bh(&tp->lock);
12165 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12167 struct tg3 *tp = netdev_priv(dev);
12169 ering->rx_max_pending = tp->rx_std_ring_mask;
12170 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12171 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12173 ering->rx_jumbo_max_pending = 0;
12175 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12177 ering->rx_pending = tp->rx_pending;
12178 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12179 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12181 ering->rx_jumbo_pending = 0;
12183 ering->tx_pending = tp->napi[0].tx_pending;
12186 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12188 struct tg3 *tp = netdev_priv(dev);
12189 int i, irq_sync = 0, err = 0;
12191 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12192 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12193 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12194 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12195 (tg3_flag(tp, TSO_BUG) &&
12196 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12199 if (netif_running(dev)) {
12201 tg3_netif_stop(tp);
12205 tg3_full_lock(tp, irq_sync);
12207 tp->rx_pending = ering->rx_pending;
12209 if (tg3_flag(tp, MAX_RXPEND_64) &&
12210 tp->rx_pending > 63)
12211 tp->rx_pending = 63;
12212 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12214 for (i = 0; i < tp->irq_max; i++)
12215 tp->napi[i].tx_pending = ering->tx_pending;
12217 if (netif_running(dev)) {
12218 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12219 err = tg3_restart_hw(tp, false);
12221 tg3_netif_start(tp);
12224 tg3_full_unlock(tp);
12226 if (irq_sync && !err)
12232 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12234 struct tg3 *tp = netdev_priv(dev);
12236 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12238 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12239 epause->rx_pause = 1;
12241 epause->rx_pause = 0;
12243 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12244 epause->tx_pause = 1;
12246 epause->tx_pause = 0;
12249 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12251 struct tg3 *tp = netdev_priv(dev);
12254 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12255 tg3_warn_mgmt_link_flap(tp);
12257 if (tg3_flag(tp, USE_PHYLIB)) {
12259 struct phy_device *phydev;
12261 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12263 if (!(phydev->supported & SUPPORTED_Pause) ||
12264 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12265 (epause->rx_pause != epause->tx_pause)))
12268 tp->link_config.flowctrl = 0;
12269 if (epause->rx_pause) {
12270 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12272 if (epause->tx_pause) {
12273 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12274 newadv = ADVERTISED_Pause;
12276 newadv = ADVERTISED_Pause |
12277 ADVERTISED_Asym_Pause;
12278 } else if (epause->tx_pause) {
12279 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12280 newadv = ADVERTISED_Asym_Pause;
12284 if (epause->autoneg)
12285 tg3_flag_set(tp, PAUSE_AUTONEG);
12287 tg3_flag_clear(tp, PAUSE_AUTONEG);
12289 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12290 u32 oldadv = phydev->advertising &
12291 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12292 if (oldadv != newadv) {
12293 phydev->advertising &=
12294 ~(ADVERTISED_Pause |
12295 ADVERTISED_Asym_Pause);
12296 phydev->advertising |= newadv;
12297 if (phydev->autoneg) {
12299 * Always renegotiate the link to
12300 * inform our link partner of our
12301 * flow control settings, even if the
12302 * flow control is forced. Let
12303 * tg3_adjust_link() do the final
12304 * flow control setup.
12306 return phy_start_aneg(phydev);
12310 if (!epause->autoneg)
12311 tg3_setup_flow_control(tp, 0, 0);
12313 tp->link_config.advertising &=
12314 ~(ADVERTISED_Pause |
12315 ADVERTISED_Asym_Pause);
12316 tp->link_config.advertising |= newadv;
12321 if (netif_running(dev)) {
12322 tg3_netif_stop(tp);
12326 tg3_full_lock(tp, irq_sync);
12328 if (epause->autoneg)
12329 tg3_flag_set(tp, PAUSE_AUTONEG);
12331 tg3_flag_clear(tp, PAUSE_AUTONEG);
12332 if (epause->rx_pause)
12333 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12335 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12336 if (epause->tx_pause)
12337 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12339 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12341 if (netif_running(dev)) {
12342 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12343 err = tg3_restart_hw(tp, false);
12345 tg3_netif_start(tp);
12348 tg3_full_unlock(tp);
12351 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12356 static int tg3_get_sset_count(struct net_device *dev, int sset)
12360 return TG3_NUM_TEST;
12362 return TG3_NUM_STATS;
12364 return -EOPNOTSUPP;
12368 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12369 u32 *rules __always_unused)
12371 struct tg3 *tp = netdev_priv(dev);
12373 if (!tg3_flag(tp, SUPPORT_MSIX))
12374 return -EOPNOTSUPP;
12376 switch (info->cmd) {
12377 case ETHTOOL_GRXRINGS:
12378 if (netif_running(tp->dev))
12379 info->data = tp->rxq_cnt;
12381 info->data = num_online_cpus();
12382 if (info->data > TG3_RSS_MAX_NUM_QS)
12383 info->data = TG3_RSS_MAX_NUM_QS;
12386 /* The first interrupt vector only
12387 * handles link interrupts.
12393 return -EOPNOTSUPP;
12397 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12400 struct tg3 *tp = netdev_priv(dev);
12402 if (tg3_flag(tp, SUPPORT_MSIX))
12403 size = TG3_RSS_INDIR_TBL_SIZE;
12408 static int tg3_get_rxfh_indir(struct net_device *dev, u32 *indir)
12410 struct tg3 *tp = netdev_priv(dev);
12413 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12414 indir[i] = tp->rss_ind_tbl[i];
12419 static int tg3_set_rxfh_indir(struct net_device *dev, const u32 *indir)
12421 struct tg3 *tp = netdev_priv(dev);
12424 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12425 tp->rss_ind_tbl[i] = indir[i];
12427 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12430 /* It is legal to write the indirection
12431 * table while the device is running.
12433 tg3_full_lock(tp, 0);
12434 tg3_rss_write_indir_tbl(tp);
12435 tg3_full_unlock(tp);
12440 static void tg3_get_channels(struct net_device *dev,
12441 struct ethtool_channels *channel)
12443 struct tg3 *tp = netdev_priv(dev);
12444 u32 deflt_qs = netif_get_num_default_rss_queues();
12446 channel->max_rx = tp->rxq_max;
12447 channel->max_tx = tp->txq_max;
12449 if (netif_running(dev)) {
12450 channel->rx_count = tp->rxq_cnt;
12451 channel->tx_count = tp->txq_cnt;
12454 channel->rx_count = tp->rxq_req;
12456 channel->rx_count = min(deflt_qs, tp->rxq_max);
12459 channel->tx_count = tp->txq_req;
12461 channel->tx_count = min(deflt_qs, tp->txq_max);
12465 static int tg3_set_channels(struct net_device *dev,
12466 struct ethtool_channels *channel)
12468 struct tg3 *tp = netdev_priv(dev);
12470 if (!tg3_flag(tp, SUPPORT_MSIX))
12471 return -EOPNOTSUPP;
12473 if (channel->rx_count > tp->rxq_max ||
12474 channel->tx_count > tp->txq_max)
12477 tp->rxq_req = channel->rx_count;
12478 tp->txq_req = channel->tx_count;
12480 if (!netif_running(dev))
12485 tg3_carrier_off(tp);
12487 tg3_start(tp, true, false, false);
12492 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12494 switch (stringset) {
12496 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12499 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12502 WARN_ON(1); /* we need a WARN() */
12507 static int tg3_set_phys_id(struct net_device *dev,
12508 enum ethtool_phys_id_state state)
12510 struct tg3 *tp = netdev_priv(dev);
12512 if (!netif_running(tp->dev))
12516 case ETHTOOL_ID_ACTIVE:
12517 return 1; /* cycle on/off once per second */
12519 case ETHTOOL_ID_ON:
12520 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12521 LED_CTRL_1000MBPS_ON |
12522 LED_CTRL_100MBPS_ON |
12523 LED_CTRL_10MBPS_ON |
12524 LED_CTRL_TRAFFIC_OVERRIDE |
12525 LED_CTRL_TRAFFIC_BLINK |
12526 LED_CTRL_TRAFFIC_LED);
12529 case ETHTOOL_ID_OFF:
12530 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12531 LED_CTRL_TRAFFIC_OVERRIDE);
12534 case ETHTOOL_ID_INACTIVE:
12535 tw32(MAC_LED_CTRL, tp->led_ctrl);
12542 static void tg3_get_ethtool_stats(struct net_device *dev,
12543 struct ethtool_stats *estats, u64 *tmp_stats)
12545 struct tg3 *tp = netdev_priv(dev);
12548 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12550 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12553 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12557 u32 offset = 0, len = 0;
12560 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12563 if (magic == TG3_EEPROM_MAGIC) {
12564 for (offset = TG3_NVM_DIR_START;
12565 offset < TG3_NVM_DIR_END;
12566 offset += TG3_NVM_DIRENT_SIZE) {
12567 if (tg3_nvram_read(tp, offset, &val))
12570 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12571 TG3_NVM_DIRTYPE_EXTVPD)
12575 if (offset != TG3_NVM_DIR_END) {
12576 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12577 if (tg3_nvram_read(tp, offset + 4, &offset))
12580 offset = tg3_nvram_logical_addr(tp, offset);
12584 if (!offset || !len) {
12585 offset = TG3_NVM_VPD_OFF;
12586 len = TG3_NVM_VPD_LEN;
12589 buf = kmalloc(len, GFP_KERNEL);
12593 if (magic == TG3_EEPROM_MAGIC) {
12594 for (i = 0; i < len; i += 4) {
12595 /* The data is in little-endian format in NVRAM.
12596 * Use the big-endian read routines to preserve
12597 * the byte order as it exists in NVRAM.
12599 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12605 unsigned int pos = 0;
12607 ptr = (u8 *)&buf[0];
12608 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12609 cnt = pci_read_vpd(tp->pdev, pos,
12611 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12629 #define NVRAM_TEST_SIZE 0x100
12630 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12631 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12632 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12633 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12634 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12635 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12636 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12637 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12639 static int tg3_test_nvram(struct tg3 *tp)
12641 u32 csum, magic, len;
12643 int i, j, k, err = 0, size;
12645 if (tg3_flag(tp, NO_NVRAM))
12648 if (tg3_nvram_read(tp, 0, &magic) != 0)
12651 if (magic == TG3_EEPROM_MAGIC)
12652 size = NVRAM_TEST_SIZE;
12653 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12654 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12655 TG3_EEPROM_SB_FORMAT_1) {
12656 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12657 case TG3_EEPROM_SB_REVISION_0:
12658 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12660 case TG3_EEPROM_SB_REVISION_2:
12661 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12663 case TG3_EEPROM_SB_REVISION_3:
12664 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12666 case TG3_EEPROM_SB_REVISION_4:
12667 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12669 case TG3_EEPROM_SB_REVISION_5:
12670 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12672 case TG3_EEPROM_SB_REVISION_6:
12673 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12680 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12681 size = NVRAM_SELFBOOT_HW_SIZE;
12685 buf = kmalloc(size, GFP_KERNEL);
12690 for (i = 0, j = 0; i < size; i += 4, j++) {
12691 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12698 /* Selfboot format */
12699 magic = be32_to_cpu(buf[0]);
12700 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12701 TG3_EEPROM_MAGIC_FW) {
12702 u8 *buf8 = (u8 *) buf, csum8 = 0;
12704 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12705 TG3_EEPROM_SB_REVISION_2) {
12706 /* For rev 2, the csum doesn't include the MBA. */
12707 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12709 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12712 for (i = 0; i < size; i++)
12725 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12726 TG3_EEPROM_MAGIC_HW) {
12727 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12728 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12729 u8 *buf8 = (u8 *) buf;
12731 /* Separate the parity bits and the data bytes. */
12732 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12733 if ((i == 0) || (i == 8)) {
12737 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12738 parity[k++] = buf8[i] & msk;
12740 } else if (i == 16) {
12744 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12745 parity[k++] = buf8[i] & msk;
12748 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12749 parity[k++] = buf8[i] & msk;
12752 data[j++] = buf8[i];
12756 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12757 u8 hw8 = hweight8(data[i]);
12759 if ((hw8 & 0x1) && parity[i])
12761 else if (!(hw8 & 0x1) && !parity[i])
12770 /* Bootstrap checksum at offset 0x10 */
12771 csum = calc_crc((unsigned char *) buf, 0x10);
12772 if (csum != le32_to_cpu(buf[0x10/4]))
12775 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12776 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12777 if (csum != le32_to_cpu(buf[0xfc/4]))
12782 buf = tg3_vpd_readblock(tp, &len);
12786 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12788 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12792 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12795 i += PCI_VPD_LRDT_TAG_SIZE;
12796 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12797 PCI_VPD_RO_KEYWORD_CHKSUM);
12801 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12803 for (i = 0; i <= j; i++)
12804 csum8 += ((u8 *)buf)[i];
12818 #define TG3_SERDES_TIMEOUT_SEC 2
12819 #define TG3_COPPER_TIMEOUT_SEC 6
12821 static int tg3_test_link(struct tg3 *tp)
12825 if (!netif_running(tp->dev))
12828 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12829 max = TG3_SERDES_TIMEOUT_SEC;
12831 max = TG3_COPPER_TIMEOUT_SEC;
12833 for (i = 0; i < max; i++) {
12837 if (msleep_interruptible(1000))
12844 /* Only test the commonly used registers */
12845 static int tg3_test_registers(struct tg3 *tp)
12847 int i, is_5705, is_5750;
12848 u32 offset, read_mask, write_mask, val, save_val, read_val;
12852 #define TG3_FL_5705 0x1
12853 #define TG3_FL_NOT_5705 0x2
12854 #define TG3_FL_NOT_5788 0x4
12855 #define TG3_FL_NOT_5750 0x8
12859 /* MAC Control Registers */
12860 { MAC_MODE, TG3_FL_NOT_5705,
12861 0x00000000, 0x00ef6f8c },
12862 { MAC_MODE, TG3_FL_5705,
12863 0x00000000, 0x01ef6b8c },
12864 { MAC_STATUS, TG3_FL_NOT_5705,
12865 0x03800107, 0x00000000 },
12866 { MAC_STATUS, TG3_FL_5705,
12867 0x03800100, 0x00000000 },
12868 { MAC_ADDR_0_HIGH, 0x0000,
12869 0x00000000, 0x0000ffff },
12870 { MAC_ADDR_0_LOW, 0x0000,
12871 0x00000000, 0xffffffff },
12872 { MAC_RX_MTU_SIZE, 0x0000,
12873 0x00000000, 0x0000ffff },
12874 { MAC_TX_MODE, 0x0000,
12875 0x00000000, 0x00000070 },
12876 { MAC_TX_LENGTHS, 0x0000,
12877 0x00000000, 0x00003fff },
12878 { MAC_RX_MODE, TG3_FL_NOT_5705,
12879 0x00000000, 0x000007fc },
12880 { MAC_RX_MODE, TG3_FL_5705,
12881 0x00000000, 0x000007dc },
12882 { MAC_HASH_REG_0, 0x0000,
12883 0x00000000, 0xffffffff },
12884 { MAC_HASH_REG_1, 0x0000,
12885 0x00000000, 0xffffffff },
12886 { MAC_HASH_REG_2, 0x0000,
12887 0x00000000, 0xffffffff },
12888 { MAC_HASH_REG_3, 0x0000,
12889 0x00000000, 0xffffffff },
12891 /* Receive Data and Receive BD Initiator Control Registers. */
12892 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
12893 0x00000000, 0xffffffff },
12894 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
12895 0x00000000, 0xffffffff },
12896 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
12897 0x00000000, 0x00000003 },
12898 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
12899 0x00000000, 0xffffffff },
12900 { RCVDBDI_STD_BD+0, 0x0000,
12901 0x00000000, 0xffffffff },
12902 { RCVDBDI_STD_BD+4, 0x0000,
12903 0x00000000, 0xffffffff },
12904 { RCVDBDI_STD_BD+8, 0x0000,
12905 0x00000000, 0xffff0002 },
12906 { RCVDBDI_STD_BD+0xc, 0x0000,
12907 0x00000000, 0xffffffff },
12909 /* Receive BD Initiator Control Registers. */
12910 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
12911 0x00000000, 0xffffffff },
12912 { RCVBDI_STD_THRESH, TG3_FL_5705,
12913 0x00000000, 0x000003ff },
12914 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
12915 0x00000000, 0xffffffff },
12917 /* Host Coalescing Control Registers. */
12918 { HOSTCC_MODE, TG3_FL_NOT_5705,
12919 0x00000000, 0x00000004 },
12920 { HOSTCC_MODE, TG3_FL_5705,
12921 0x00000000, 0x000000f6 },
12922 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
12923 0x00000000, 0xffffffff },
12924 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
12925 0x00000000, 0x000003ff },
12926 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
12927 0x00000000, 0xffffffff },
12928 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
12929 0x00000000, 0x000003ff },
12930 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
12931 0x00000000, 0xffffffff },
12932 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12933 0x00000000, 0x000000ff },
12934 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
12935 0x00000000, 0xffffffff },
12936 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
12937 0x00000000, 0x000000ff },
12938 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
12939 0x00000000, 0xffffffff },
12940 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
12941 0x00000000, 0xffffffff },
12942 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12943 0x00000000, 0xffffffff },
12944 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12945 0x00000000, 0x000000ff },
12946 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
12947 0x00000000, 0xffffffff },
12948 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
12949 0x00000000, 0x000000ff },
12950 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
12951 0x00000000, 0xffffffff },
12952 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
12953 0x00000000, 0xffffffff },
12954 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
12955 0x00000000, 0xffffffff },
12956 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
12957 0x00000000, 0xffffffff },
12958 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
12959 0x00000000, 0xffffffff },
12960 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
12961 0xffffffff, 0x00000000 },
12962 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
12963 0xffffffff, 0x00000000 },
12965 /* Buffer Manager Control Registers. */
12966 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
12967 0x00000000, 0x007fff80 },
12968 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
12969 0x00000000, 0x007fffff },
12970 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
12971 0x00000000, 0x0000003f },
12972 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
12973 0x00000000, 0x000001ff },
12974 { BUFMGR_MB_HIGH_WATER, 0x0000,
12975 0x00000000, 0x000001ff },
12976 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
12977 0xffffffff, 0x00000000 },
12978 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
12979 0xffffffff, 0x00000000 },
12981 /* Mailbox Registers */
12982 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
12983 0x00000000, 0x000001ff },
12984 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
12985 0x00000000, 0x000001ff },
12986 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
12987 0x00000000, 0x000007ff },
12988 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
12989 0x00000000, 0x000001ff },
12991 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12994 is_5705 = is_5750 = 0;
12995 if (tg3_flag(tp, 5705_PLUS)) {
12997 if (tg3_flag(tp, 5750_PLUS))
13001 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13002 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13005 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13008 if (tg3_flag(tp, IS_5788) &&
13009 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13012 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13015 offset = (u32) reg_tbl[i].offset;
13016 read_mask = reg_tbl[i].read_mask;
13017 write_mask = reg_tbl[i].write_mask;
13019 /* Save the original register content */
13020 save_val = tr32(offset);
13022 /* Determine the read-only value. */
13023 read_val = save_val & read_mask;
13025 /* Write zero to the register, then make sure the read-only bits
13026 * are not changed and the read/write bits are all zeros.
13030 val = tr32(offset);
13032 /* Test the read-only and read/write bits. */
13033 if (((val & read_mask) != read_val) || (val & write_mask))
13036 /* Write ones to all the bits defined by RdMask and WrMask, then
13037 * make sure the read-only bits are not changed and the
13038 * read/write bits are all ones.
13040 tw32(offset, read_mask | write_mask);
13042 val = tr32(offset);
13044 /* Test the read-only bits. */
13045 if ((val & read_mask) != read_val)
13048 /* Test the read/write bits. */
13049 if ((val & write_mask) != write_mask)
13052 tw32(offset, save_val);
13058 if (netif_msg_hw(tp))
13059 netdev_err(tp->dev,
13060 "Register test failed at offset %x\n", offset);
13061 tw32(offset, save_val);
13065 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13067 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13071 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13072 for (j = 0; j < len; j += 4) {
13075 tg3_write_mem(tp, offset + j, test_pattern[i]);
13076 tg3_read_mem(tp, offset + j, &val);
13077 if (val != test_pattern[i])
13084 static int tg3_test_memory(struct tg3 *tp)
13086 static struct mem_entry {
13089 } mem_tbl_570x[] = {
13090 { 0x00000000, 0x00b50},
13091 { 0x00002000, 0x1c000},
13092 { 0xffffffff, 0x00000}
13093 }, mem_tbl_5705[] = {
13094 { 0x00000100, 0x0000c},
13095 { 0x00000200, 0x00008},
13096 { 0x00004000, 0x00800},
13097 { 0x00006000, 0x01000},
13098 { 0x00008000, 0x02000},
13099 { 0x00010000, 0x0e000},
13100 { 0xffffffff, 0x00000}
13101 }, mem_tbl_5755[] = {
13102 { 0x00000200, 0x00008},
13103 { 0x00004000, 0x00800},
13104 { 0x00006000, 0x00800},
13105 { 0x00008000, 0x02000},
13106 { 0x00010000, 0x0c000},
13107 { 0xffffffff, 0x00000}
13108 }, mem_tbl_5906[] = {
13109 { 0x00000200, 0x00008},
13110 { 0x00004000, 0x00400},
13111 { 0x00006000, 0x00400},
13112 { 0x00008000, 0x01000},
13113 { 0x00010000, 0x01000},
13114 { 0xffffffff, 0x00000}
13115 }, mem_tbl_5717[] = {
13116 { 0x00000200, 0x00008},
13117 { 0x00010000, 0x0a000},
13118 { 0x00020000, 0x13c00},
13119 { 0xffffffff, 0x00000}
13120 }, mem_tbl_57765[] = {
13121 { 0x00000200, 0x00008},
13122 { 0x00004000, 0x00800},
13123 { 0x00006000, 0x09800},
13124 { 0x00010000, 0x0a000},
13125 { 0xffffffff, 0x00000}
13127 struct mem_entry *mem_tbl;
13131 if (tg3_flag(tp, 5717_PLUS))
13132 mem_tbl = mem_tbl_5717;
13133 else if (tg3_flag(tp, 57765_CLASS) ||
13134 tg3_asic_rev(tp) == ASIC_REV_5762)
13135 mem_tbl = mem_tbl_57765;
13136 else if (tg3_flag(tp, 5755_PLUS))
13137 mem_tbl = mem_tbl_5755;
13138 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13139 mem_tbl = mem_tbl_5906;
13140 else if (tg3_flag(tp, 5705_PLUS))
13141 mem_tbl = mem_tbl_5705;
13143 mem_tbl = mem_tbl_570x;
13145 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13146 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13154 #define TG3_TSO_MSS 500
13156 #define TG3_TSO_IP_HDR_LEN 20
13157 #define TG3_TSO_TCP_HDR_LEN 20
13158 #define TG3_TSO_TCP_OPT_LEN 12
13160 static const u8 tg3_tso_header[] = {
13162 0x45, 0x00, 0x00, 0x00,
13163 0x00, 0x00, 0x40, 0x00,
13164 0x40, 0x06, 0x00, 0x00,
13165 0x0a, 0x00, 0x00, 0x01,
13166 0x0a, 0x00, 0x00, 0x02,
13167 0x0d, 0x00, 0xe0, 0x00,
13168 0x00, 0x00, 0x01, 0x00,
13169 0x00, 0x00, 0x02, 0x00,
13170 0x80, 0x10, 0x10, 0x00,
13171 0x14, 0x09, 0x00, 0x00,
13172 0x01, 0x01, 0x08, 0x0a,
13173 0x11, 0x11, 0x11, 0x11,
13174 0x11, 0x11, 0x11, 0x11,
13177 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13179 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13180 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13182 struct sk_buff *skb;
13183 u8 *tx_data, *rx_data;
13185 int num_pkts, tx_len, rx_len, i, err;
13186 struct tg3_rx_buffer_desc *desc;
13187 struct tg3_napi *tnapi, *rnapi;
13188 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13190 tnapi = &tp->napi[0];
13191 rnapi = &tp->napi[0];
13192 if (tp->irq_cnt > 1) {
13193 if (tg3_flag(tp, ENABLE_RSS))
13194 rnapi = &tp->napi[1];
13195 if (tg3_flag(tp, ENABLE_TSS))
13196 tnapi = &tp->napi[1];
13198 coal_now = tnapi->coal_now | rnapi->coal_now;
13203 skb = netdev_alloc_skb(tp->dev, tx_len);
13207 tx_data = skb_put(skb, tx_len);
13208 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13209 memset(tx_data + ETH_ALEN, 0x0, 8);
13211 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13213 if (tso_loopback) {
13214 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13216 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13217 TG3_TSO_TCP_OPT_LEN;
13219 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13220 sizeof(tg3_tso_header));
13223 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13224 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13226 /* Set the total length field in the IP header */
13227 iph->tot_len = htons((u16)(mss + hdr_len));
13229 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13230 TXD_FLAG_CPU_POST_DMA);
13232 if (tg3_flag(tp, HW_TSO_1) ||
13233 tg3_flag(tp, HW_TSO_2) ||
13234 tg3_flag(tp, HW_TSO_3)) {
13236 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13237 th = (struct tcphdr *)&tx_data[val];
13240 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13242 if (tg3_flag(tp, HW_TSO_3)) {
13243 mss |= (hdr_len & 0xc) << 12;
13244 if (hdr_len & 0x10)
13245 base_flags |= 0x00000010;
13246 base_flags |= (hdr_len & 0x3e0) << 5;
13247 } else if (tg3_flag(tp, HW_TSO_2))
13248 mss |= hdr_len << 9;
13249 else if (tg3_flag(tp, HW_TSO_1) ||
13250 tg3_asic_rev(tp) == ASIC_REV_5705) {
13251 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13253 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13256 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13259 data_off = ETH_HLEN;
13261 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13262 tx_len > VLAN_ETH_FRAME_LEN)
13263 base_flags |= TXD_FLAG_JMB_PKT;
13266 for (i = data_off; i < tx_len; i++)
13267 tx_data[i] = (u8) (i & 0xff);
13269 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13270 if (pci_dma_mapping_error(tp->pdev, map)) {
13271 dev_kfree_skb(skb);
13275 val = tnapi->tx_prod;
13276 tnapi->tx_buffers[val].skb = skb;
13277 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13279 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13284 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13286 budget = tg3_tx_avail(tnapi);
13287 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13288 base_flags | TXD_FLAG_END, mss, 0)) {
13289 tnapi->tx_buffers[val].skb = NULL;
13290 dev_kfree_skb(skb);
13296 /* Sync BD data before updating mailbox */
13299 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13300 tr32_mailbox(tnapi->prodmbox);
13304 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13305 for (i = 0; i < 35; i++) {
13306 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13311 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13312 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13313 if ((tx_idx == tnapi->tx_prod) &&
13314 (rx_idx == (rx_start_idx + num_pkts)))
13318 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13319 dev_kfree_skb(skb);
13321 if (tx_idx != tnapi->tx_prod)
13324 if (rx_idx != rx_start_idx + num_pkts)
13328 while (rx_idx != rx_start_idx) {
13329 desc = &rnapi->rx_rcb[rx_start_idx++];
13330 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13331 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13333 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13334 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13337 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13340 if (!tso_loopback) {
13341 if (rx_len != tx_len)
13344 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13345 if (opaque_key != RXD_OPAQUE_RING_STD)
13348 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13351 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13352 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13353 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13357 if (opaque_key == RXD_OPAQUE_RING_STD) {
13358 rx_data = tpr->rx_std_buffers[desc_idx].data;
13359 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13361 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13362 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13363 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13368 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13369 PCI_DMA_FROMDEVICE);
13371 rx_data += TG3_RX_OFFSET(tp);
13372 for (i = data_off; i < rx_len; i++, val++) {
13373 if (*(rx_data + i) != (u8) (val & 0xff))
13380 /* tg3_free_rings will unmap and free the rx_data */
13385 #define TG3_STD_LOOPBACK_FAILED 1
13386 #define TG3_JMB_LOOPBACK_FAILED 2
13387 #define TG3_TSO_LOOPBACK_FAILED 4
13388 #define TG3_LOOPBACK_FAILED \
13389 (TG3_STD_LOOPBACK_FAILED | \
13390 TG3_JMB_LOOPBACK_FAILED | \
13391 TG3_TSO_LOOPBACK_FAILED)
13393 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13397 u32 jmb_pkt_sz = 9000;
13400 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13402 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13403 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13405 if (!netif_running(tp->dev)) {
13406 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13407 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13409 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13413 err = tg3_reset_hw(tp, true);
13415 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13416 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13418 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13422 if (tg3_flag(tp, ENABLE_RSS)) {
13425 /* Reroute all rx packets to the 1st queue */
13426 for (i = MAC_RSS_INDIR_TBL_0;
13427 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13431 /* HW errata - mac loopback fails in some cases on 5780.
13432 * Normal traffic and PHY loopback are not affected by
13433 * errata. Also, the MAC loopback test is deprecated for
13434 * all newer ASIC revisions.
13436 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13437 !tg3_flag(tp, CPMU_PRESENT)) {
13438 tg3_mac_loopback(tp, true);
13440 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13441 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13443 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13444 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13445 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13447 tg3_mac_loopback(tp, false);
13450 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13451 !tg3_flag(tp, USE_PHYLIB)) {
13454 tg3_phy_lpbk_set(tp, 0, false);
13456 /* Wait for link */
13457 for (i = 0; i < 100; i++) {
13458 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13463 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13464 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13465 if (tg3_flag(tp, TSO_CAPABLE) &&
13466 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13467 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13468 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13469 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13470 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13473 tg3_phy_lpbk_set(tp, 0, true);
13475 /* All link indications report up, but the hardware
13476 * isn't really ready for about 20 msec. Double it
13481 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13482 data[TG3_EXT_LOOPB_TEST] |=
13483 TG3_STD_LOOPBACK_FAILED;
13484 if (tg3_flag(tp, TSO_CAPABLE) &&
13485 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13486 data[TG3_EXT_LOOPB_TEST] |=
13487 TG3_TSO_LOOPBACK_FAILED;
13488 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13489 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13490 data[TG3_EXT_LOOPB_TEST] |=
13491 TG3_JMB_LOOPBACK_FAILED;
13494 /* Re-enable gphy autopowerdown. */
13495 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13496 tg3_phy_toggle_apd(tp, true);
13499 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13500 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13503 tp->phy_flags |= eee_cap;
13508 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13511 struct tg3 *tp = netdev_priv(dev);
13512 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13514 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13515 if (tg3_power_up(tp)) {
13516 etest->flags |= ETH_TEST_FL_FAILED;
13517 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13520 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13523 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13525 if (tg3_test_nvram(tp) != 0) {
13526 etest->flags |= ETH_TEST_FL_FAILED;
13527 data[TG3_NVRAM_TEST] = 1;
13529 if (!doextlpbk && tg3_test_link(tp)) {
13530 etest->flags |= ETH_TEST_FL_FAILED;
13531 data[TG3_LINK_TEST] = 1;
13533 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13534 int err, err2 = 0, irq_sync = 0;
13536 if (netif_running(dev)) {
13538 tg3_netif_stop(tp);
13542 tg3_full_lock(tp, irq_sync);
13543 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13544 err = tg3_nvram_lock(tp);
13545 tg3_halt_cpu(tp, RX_CPU_BASE);
13546 if (!tg3_flag(tp, 5705_PLUS))
13547 tg3_halt_cpu(tp, TX_CPU_BASE);
13549 tg3_nvram_unlock(tp);
13551 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13554 if (tg3_test_registers(tp) != 0) {
13555 etest->flags |= ETH_TEST_FL_FAILED;
13556 data[TG3_REGISTER_TEST] = 1;
13559 if (tg3_test_memory(tp) != 0) {
13560 etest->flags |= ETH_TEST_FL_FAILED;
13561 data[TG3_MEMORY_TEST] = 1;
13565 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13567 if (tg3_test_loopback(tp, data, doextlpbk))
13568 etest->flags |= ETH_TEST_FL_FAILED;
13570 tg3_full_unlock(tp);
13572 if (tg3_test_interrupt(tp) != 0) {
13573 etest->flags |= ETH_TEST_FL_FAILED;
13574 data[TG3_INTERRUPT_TEST] = 1;
13577 tg3_full_lock(tp, 0);
13579 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13580 if (netif_running(dev)) {
13581 tg3_flag_set(tp, INIT_COMPLETE);
13582 err2 = tg3_restart_hw(tp, true);
13584 tg3_netif_start(tp);
13587 tg3_full_unlock(tp);
13589 if (irq_sync && !err2)
13592 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13593 tg3_power_down_prepare(tp);
13597 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13599 struct tg3 *tp = netdev_priv(dev);
13600 struct hwtstamp_config stmpconf;
13602 if (!tg3_flag(tp, PTP_CAPABLE))
13603 return -EOPNOTSUPP;
13605 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13608 if (stmpconf.flags)
13611 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13612 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13615 switch (stmpconf.rx_filter) {
13616 case HWTSTAMP_FILTER_NONE:
13619 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13620 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13621 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13623 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13624 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13625 TG3_RX_PTP_CTL_SYNC_EVNT;
13627 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13628 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13629 TG3_RX_PTP_CTL_DELAY_REQ;
13631 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13632 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13633 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13635 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13636 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13637 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13639 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13640 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13641 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13643 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13644 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13645 TG3_RX_PTP_CTL_SYNC_EVNT;
13647 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13648 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13649 TG3_RX_PTP_CTL_SYNC_EVNT;
13651 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13652 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13653 TG3_RX_PTP_CTL_SYNC_EVNT;
13655 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13656 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13657 TG3_RX_PTP_CTL_DELAY_REQ;
13659 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13660 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13661 TG3_RX_PTP_CTL_DELAY_REQ;
13663 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13664 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13665 TG3_RX_PTP_CTL_DELAY_REQ;
13671 if (netif_running(dev) && tp->rxptpctl)
13672 tw32(TG3_RX_PTP_CTL,
13673 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13675 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13676 tg3_flag_set(tp, TX_TSTAMP_EN);
13678 tg3_flag_clear(tp, TX_TSTAMP_EN);
13680 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13684 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13686 struct tg3 *tp = netdev_priv(dev);
13687 struct hwtstamp_config stmpconf;
13689 if (!tg3_flag(tp, PTP_CAPABLE))
13690 return -EOPNOTSUPP;
13692 stmpconf.flags = 0;
13693 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13694 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13696 switch (tp->rxptpctl) {
13698 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13700 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13701 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13703 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13704 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13706 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13707 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13709 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13710 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13712 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13713 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13715 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13716 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13718 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13719 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13721 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13722 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13724 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13725 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13727 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13728 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13730 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13731 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13733 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13734 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13741 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13745 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13747 struct mii_ioctl_data *data = if_mii(ifr);
13748 struct tg3 *tp = netdev_priv(dev);
13751 if (tg3_flag(tp, USE_PHYLIB)) {
13752 struct phy_device *phydev;
13753 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13755 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13756 return phy_mii_ioctl(phydev, ifr, cmd);
13761 data->phy_id = tp->phy_addr;
13764 case SIOCGMIIREG: {
13767 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13768 break; /* We have no PHY */
13770 if (!netif_running(dev))
13773 spin_lock_bh(&tp->lock);
13774 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13775 data->reg_num & 0x1f, &mii_regval);
13776 spin_unlock_bh(&tp->lock);
13778 data->val_out = mii_regval;
13784 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13785 break; /* We have no PHY */
13787 if (!netif_running(dev))
13790 spin_lock_bh(&tp->lock);
13791 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13792 data->reg_num & 0x1f, data->val_in);
13793 spin_unlock_bh(&tp->lock);
13797 case SIOCSHWTSTAMP:
13798 return tg3_hwtstamp_set(dev, ifr);
13800 case SIOCGHWTSTAMP:
13801 return tg3_hwtstamp_get(dev, ifr);
13807 return -EOPNOTSUPP;
13810 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13812 struct tg3 *tp = netdev_priv(dev);
13814 memcpy(ec, &tp->coal, sizeof(*ec));
13818 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13820 struct tg3 *tp = netdev_priv(dev);
13821 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13822 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13824 if (!tg3_flag(tp, 5705_PLUS)) {
13825 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13826 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13827 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13828 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13831 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13832 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13833 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13834 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13835 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13836 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13837 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13838 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13839 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13840 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
13843 /* No rx interrupts will be generated if both are zero */
13844 if ((ec->rx_coalesce_usecs == 0) &&
13845 (ec->rx_max_coalesced_frames == 0))
13848 /* No tx interrupts will be generated if both are zero */
13849 if ((ec->tx_coalesce_usecs == 0) &&
13850 (ec->tx_max_coalesced_frames == 0))
13853 /* Only copy relevant parameters, ignore all others. */
13854 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
13855 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
13856 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
13857 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
13858 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
13859 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
13860 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
13861 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
13862 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
13864 if (netif_running(dev)) {
13865 tg3_full_lock(tp, 0);
13866 __tg3_set_coalesce(tp, &tp->coal);
13867 tg3_full_unlock(tp);
13872 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
13874 struct tg3 *tp = netdev_priv(dev);
13876 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13877 netdev_warn(tp->dev, "Board does not support EEE!\n");
13878 return -EOPNOTSUPP;
13881 if (edata->advertised != tp->eee.advertised) {
13882 netdev_warn(tp->dev,
13883 "Direct manipulation of EEE advertisement is not supported\n");
13887 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
13888 netdev_warn(tp->dev,
13889 "Maximal Tx Lpi timer supported is %#x(u)\n",
13890 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
13896 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
13897 tg3_warn_mgmt_link_flap(tp);
13899 if (netif_running(tp->dev)) {
13900 tg3_full_lock(tp, 0);
13903 tg3_full_unlock(tp);
13909 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
13911 struct tg3 *tp = netdev_priv(dev);
13913 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
13914 netdev_warn(tp->dev,
13915 "Board does not support EEE!\n");
13916 return -EOPNOTSUPP;
13923 static const struct ethtool_ops tg3_ethtool_ops = {
13924 .get_settings = tg3_get_settings,
13925 .set_settings = tg3_set_settings,
13926 .get_drvinfo = tg3_get_drvinfo,
13927 .get_regs_len = tg3_get_regs_len,
13928 .get_regs = tg3_get_regs,
13929 .get_wol = tg3_get_wol,
13930 .set_wol = tg3_set_wol,
13931 .get_msglevel = tg3_get_msglevel,
13932 .set_msglevel = tg3_set_msglevel,
13933 .nway_reset = tg3_nway_reset,
13934 .get_link = ethtool_op_get_link,
13935 .get_eeprom_len = tg3_get_eeprom_len,
13936 .get_eeprom = tg3_get_eeprom,
13937 .set_eeprom = tg3_set_eeprom,
13938 .get_ringparam = tg3_get_ringparam,
13939 .set_ringparam = tg3_set_ringparam,
13940 .get_pauseparam = tg3_get_pauseparam,
13941 .set_pauseparam = tg3_set_pauseparam,
13942 .self_test = tg3_self_test,
13943 .get_strings = tg3_get_strings,
13944 .set_phys_id = tg3_set_phys_id,
13945 .get_ethtool_stats = tg3_get_ethtool_stats,
13946 .get_coalesce = tg3_get_coalesce,
13947 .set_coalesce = tg3_set_coalesce,
13948 .get_sset_count = tg3_get_sset_count,
13949 .get_rxnfc = tg3_get_rxnfc,
13950 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
13951 .get_rxfh_indir = tg3_get_rxfh_indir,
13952 .set_rxfh_indir = tg3_set_rxfh_indir,
13953 .get_channels = tg3_get_channels,
13954 .set_channels = tg3_set_channels,
13955 .get_ts_info = tg3_get_ts_info,
13956 .get_eee = tg3_get_eee,
13957 .set_eee = tg3_set_eee,
13960 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
13961 struct rtnl_link_stats64 *stats)
13963 struct tg3 *tp = netdev_priv(dev);
13965 spin_lock_bh(&tp->lock);
13966 if (!tp->hw_stats) {
13967 spin_unlock_bh(&tp->lock);
13968 return &tp->net_stats_prev;
13971 tg3_get_nstats(tp, stats);
13972 spin_unlock_bh(&tp->lock);
13977 static void tg3_set_rx_mode(struct net_device *dev)
13979 struct tg3 *tp = netdev_priv(dev);
13981 if (!netif_running(dev))
13984 tg3_full_lock(tp, 0);
13985 __tg3_set_rx_mode(dev);
13986 tg3_full_unlock(tp);
13989 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
13992 dev->mtu = new_mtu;
13994 if (new_mtu > ETH_DATA_LEN) {
13995 if (tg3_flag(tp, 5780_CLASS)) {
13996 netdev_update_features(dev);
13997 tg3_flag_clear(tp, TSO_CAPABLE);
13999 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14002 if (tg3_flag(tp, 5780_CLASS)) {
14003 tg3_flag_set(tp, TSO_CAPABLE);
14004 netdev_update_features(dev);
14006 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14010 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14012 struct tg3 *tp = netdev_priv(dev);
14014 bool reset_phy = false;
14016 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14019 if (!netif_running(dev)) {
14020 /* We'll just catch it later when the
14023 tg3_set_mtu(dev, tp, new_mtu);
14029 tg3_netif_stop(tp);
14031 tg3_full_lock(tp, 1);
14033 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14035 tg3_set_mtu(dev, tp, new_mtu);
14037 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14038 * breaks all requests to 256 bytes.
14040 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14043 err = tg3_restart_hw(tp, reset_phy);
14046 tg3_netif_start(tp);
14048 tg3_full_unlock(tp);
14056 static const struct net_device_ops tg3_netdev_ops = {
14057 .ndo_open = tg3_open,
14058 .ndo_stop = tg3_close,
14059 .ndo_start_xmit = tg3_start_xmit,
14060 .ndo_get_stats64 = tg3_get_stats64,
14061 .ndo_validate_addr = eth_validate_addr,
14062 .ndo_set_rx_mode = tg3_set_rx_mode,
14063 .ndo_set_mac_address = tg3_set_mac_addr,
14064 .ndo_do_ioctl = tg3_ioctl,
14065 .ndo_tx_timeout = tg3_tx_timeout,
14066 .ndo_change_mtu = tg3_change_mtu,
14067 .ndo_fix_features = tg3_fix_features,
14068 .ndo_set_features = tg3_set_features,
14069 #ifdef CONFIG_NET_POLL_CONTROLLER
14070 .ndo_poll_controller = tg3_poll_controller,
14074 static void tg3_get_eeprom_size(struct tg3 *tp)
14076 u32 cursize, val, magic;
14078 tp->nvram_size = EEPROM_CHIP_SIZE;
14080 if (tg3_nvram_read(tp, 0, &magic) != 0)
14083 if ((magic != TG3_EEPROM_MAGIC) &&
14084 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14085 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14089 * Size the chip by reading offsets at increasing powers of two.
14090 * When we encounter our validation signature, we know the addressing
14091 * has wrapped around, and thus have our chip size.
14095 while (cursize < tp->nvram_size) {
14096 if (tg3_nvram_read(tp, cursize, &val) != 0)
14105 tp->nvram_size = cursize;
14108 static void tg3_get_nvram_size(struct tg3 *tp)
14112 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14115 /* Selfboot format */
14116 if (val != TG3_EEPROM_MAGIC) {
14117 tg3_get_eeprom_size(tp);
14121 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14123 /* This is confusing. We want to operate on the
14124 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14125 * call will read from NVRAM and byteswap the data
14126 * according to the byteswapping settings for all
14127 * other register accesses. This ensures the data we
14128 * want will always reside in the lower 16-bits.
14129 * However, the data in NVRAM is in LE format, which
14130 * means the data from the NVRAM read will always be
14131 * opposite the endianness of the CPU. The 16-bit
14132 * byteswap then brings the data to CPU endianness.
14134 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14138 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14141 static void tg3_get_nvram_info(struct tg3 *tp)
14145 nvcfg1 = tr32(NVRAM_CFG1);
14146 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14147 tg3_flag_set(tp, FLASH);
14149 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14150 tw32(NVRAM_CFG1, nvcfg1);
14153 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14154 tg3_flag(tp, 5780_CLASS)) {
14155 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14156 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14157 tp->nvram_jedecnum = JEDEC_ATMEL;
14158 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14159 tg3_flag_set(tp, NVRAM_BUFFERED);
14161 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14162 tp->nvram_jedecnum = JEDEC_ATMEL;
14163 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14165 case FLASH_VENDOR_ATMEL_EEPROM:
14166 tp->nvram_jedecnum = JEDEC_ATMEL;
14167 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14168 tg3_flag_set(tp, NVRAM_BUFFERED);
14170 case FLASH_VENDOR_ST:
14171 tp->nvram_jedecnum = JEDEC_ST;
14172 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14173 tg3_flag_set(tp, NVRAM_BUFFERED);
14175 case FLASH_VENDOR_SAIFUN:
14176 tp->nvram_jedecnum = JEDEC_SAIFUN;
14177 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14179 case FLASH_VENDOR_SST_SMALL:
14180 case FLASH_VENDOR_SST_LARGE:
14181 tp->nvram_jedecnum = JEDEC_SST;
14182 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14186 tp->nvram_jedecnum = JEDEC_ATMEL;
14187 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14188 tg3_flag_set(tp, NVRAM_BUFFERED);
14192 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14194 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14195 case FLASH_5752PAGE_SIZE_256:
14196 tp->nvram_pagesize = 256;
14198 case FLASH_5752PAGE_SIZE_512:
14199 tp->nvram_pagesize = 512;
14201 case FLASH_5752PAGE_SIZE_1K:
14202 tp->nvram_pagesize = 1024;
14204 case FLASH_5752PAGE_SIZE_2K:
14205 tp->nvram_pagesize = 2048;
14207 case FLASH_5752PAGE_SIZE_4K:
14208 tp->nvram_pagesize = 4096;
14210 case FLASH_5752PAGE_SIZE_264:
14211 tp->nvram_pagesize = 264;
14213 case FLASH_5752PAGE_SIZE_528:
14214 tp->nvram_pagesize = 528;
14219 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14223 nvcfg1 = tr32(NVRAM_CFG1);
14225 /* NVRAM protection for TPM */
14226 if (nvcfg1 & (1 << 27))
14227 tg3_flag_set(tp, PROTECTED_NVRAM);
14229 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14230 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14231 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14232 tp->nvram_jedecnum = JEDEC_ATMEL;
14233 tg3_flag_set(tp, NVRAM_BUFFERED);
14235 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14236 tp->nvram_jedecnum = JEDEC_ATMEL;
14237 tg3_flag_set(tp, NVRAM_BUFFERED);
14238 tg3_flag_set(tp, FLASH);
14240 case FLASH_5752VENDOR_ST_M45PE10:
14241 case FLASH_5752VENDOR_ST_M45PE20:
14242 case FLASH_5752VENDOR_ST_M45PE40:
14243 tp->nvram_jedecnum = JEDEC_ST;
14244 tg3_flag_set(tp, NVRAM_BUFFERED);
14245 tg3_flag_set(tp, FLASH);
14249 if (tg3_flag(tp, FLASH)) {
14250 tg3_nvram_get_pagesize(tp, nvcfg1);
14252 /* For eeprom, set pagesize to maximum eeprom size */
14253 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14255 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14256 tw32(NVRAM_CFG1, nvcfg1);
14260 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14262 u32 nvcfg1, protect = 0;
14264 nvcfg1 = tr32(NVRAM_CFG1);
14266 /* NVRAM protection for TPM */
14267 if (nvcfg1 & (1 << 27)) {
14268 tg3_flag_set(tp, PROTECTED_NVRAM);
14272 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14274 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14275 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14276 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14277 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14278 tp->nvram_jedecnum = JEDEC_ATMEL;
14279 tg3_flag_set(tp, NVRAM_BUFFERED);
14280 tg3_flag_set(tp, FLASH);
14281 tp->nvram_pagesize = 264;
14282 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14283 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14284 tp->nvram_size = (protect ? 0x3e200 :
14285 TG3_NVRAM_SIZE_512KB);
14286 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14287 tp->nvram_size = (protect ? 0x1f200 :
14288 TG3_NVRAM_SIZE_256KB);
14290 tp->nvram_size = (protect ? 0x1f200 :
14291 TG3_NVRAM_SIZE_128KB);
14293 case FLASH_5752VENDOR_ST_M45PE10:
14294 case FLASH_5752VENDOR_ST_M45PE20:
14295 case FLASH_5752VENDOR_ST_M45PE40:
14296 tp->nvram_jedecnum = JEDEC_ST;
14297 tg3_flag_set(tp, NVRAM_BUFFERED);
14298 tg3_flag_set(tp, FLASH);
14299 tp->nvram_pagesize = 256;
14300 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14301 tp->nvram_size = (protect ?
14302 TG3_NVRAM_SIZE_64KB :
14303 TG3_NVRAM_SIZE_128KB);
14304 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14305 tp->nvram_size = (protect ?
14306 TG3_NVRAM_SIZE_64KB :
14307 TG3_NVRAM_SIZE_256KB);
14309 tp->nvram_size = (protect ?
14310 TG3_NVRAM_SIZE_128KB :
14311 TG3_NVRAM_SIZE_512KB);
14316 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14320 nvcfg1 = tr32(NVRAM_CFG1);
14322 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14323 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14324 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14325 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14326 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14327 tp->nvram_jedecnum = JEDEC_ATMEL;
14328 tg3_flag_set(tp, NVRAM_BUFFERED);
14329 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14331 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14332 tw32(NVRAM_CFG1, nvcfg1);
14334 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14335 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14336 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14337 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14338 tp->nvram_jedecnum = JEDEC_ATMEL;
14339 tg3_flag_set(tp, NVRAM_BUFFERED);
14340 tg3_flag_set(tp, FLASH);
14341 tp->nvram_pagesize = 264;
14343 case FLASH_5752VENDOR_ST_M45PE10:
14344 case FLASH_5752VENDOR_ST_M45PE20:
14345 case FLASH_5752VENDOR_ST_M45PE40:
14346 tp->nvram_jedecnum = JEDEC_ST;
14347 tg3_flag_set(tp, NVRAM_BUFFERED);
14348 tg3_flag_set(tp, FLASH);
14349 tp->nvram_pagesize = 256;
14354 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14356 u32 nvcfg1, protect = 0;
14358 nvcfg1 = tr32(NVRAM_CFG1);
14360 /* NVRAM protection for TPM */
14361 if (nvcfg1 & (1 << 27)) {
14362 tg3_flag_set(tp, PROTECTED_NVRAM);
14366 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14368 case FLASH_5761VENDOR_ATMEL_ADB021D:
14369 case FLASH_5761VENDOR_ATMEL_ADB041D:
14370 case FLASH_5761VENDOR_ATMEL_ADB081D:
14371 case FLASH_5761VENDOR_ATMEL_ADB161D:
14372 case FLASH_5761VENDOR_ATMEL_MDB021D:
14373 case FLASH_5761VENDOR_ATMEL_MDB041D:
14374 case FLASH_5761VENDOR_ATMEL_MDB081D:
14375 case FLASH_5761VENDOR_ATMEL_MDB161D:
14376 tp->nvram_jedecnum = JEDEC_ATMEL;
14377 tg3_flag_set(tp, NVRAM_BUFFERED);
14378 tg3_flag_set(tp, FLASH);
14379 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14380 tp->nvram_pagesize = 256;
14382 case FLASH_5761VENDOR_ST_A_M45PE20:
14383 case FLASH_5761VENDOR_ST_A_M45PE40:
14384 case FLASH_5761VENDOR_ST_A_M45PE80:
14385 case FLASH_5761VENDOR_ST_A_M45PE16:
14386 case FLASH_5761VENDOR_ST_M_M45PE20:
14387 case FLASH_5761VENDOR_ST_M_M45PE40:
14388 case FLASH_5761VENDOR_ST_M_M45PE80:
14389 case FLASH_5761VENDOR_ST_M_M45PE16:
14390 tp->nvram_jedecnum = JEDEC_ST;
14391 tg3_flag_set(tp, NVRAM_BUFFERED);
14392 tg3_flag_set(tp, FLASH);
14393 tp->nvram_pagesize = 256;
14398 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14401 case FLASH_5761VENDOR_ATMEL_ADB161D:
14402 case FLASH_5761VENDOR_ATMEL_MDB161D:
14403 case FLASH_5761VENDOR_ST_A_M45PE16:
14404 case FLASH_5761VENDOR_ST_M_M45PE16:
14405 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14407 case FLASH_5761VENDOR_ATMEL_ADB081D:
14408 case FLASH_5761VENDOR_ATMEL_MDB081D:
14409 case FLASH_5761VENDOR_ST_A_M45PE80:
14410 case FLASH_5761VENDOR_ST_M_M45PE80:
14411 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14413 case FLASH_5761VENDOR_ATMEL_ADB041D:
14414 case FLASH_5761VENDOR_ATMEL_MDB041D:
14415 case FLASH_5761VENDOR_ST_A_M45PE40:
14416 case FLASH_5761VENDOR_ST_M_M45PE40:
14417 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14419 case FLASH_5761VENDOR_ATMEL_ADB021D:
14420 case FLASH_5761VENDOR_ATMEL_MDB021D:
14421 case FLASH_5761VENDOR_ST_A_M45PE20:
14422 case FLASH_5761VENDOR_ST_M_M45PE20:
14423 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14429 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14431 tp->nvram_jedecnum = JEDEC_ATMEL;
14432 tg3_flag_set(tp, NVRAM_BUFFERED);
14433 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14436 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14440 nvcfg1 = tr32(NVRAM_CFG1);
14442 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14443 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14444 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14445 tp->nvram_jedecnum = JEDEC_ATMEL;
14446 tg3_flag_set(tp, NVRAM_BUFFERED);
14447 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14449 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14450 tw32(NVRAM_CFG1, nvcfg1);
14452 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14453 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14454 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14455 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14456 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14457 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14458 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14459 tp->nvram_jedecnum = JEDEC_ATMEL;
14460 tg3_flag_set(tp, NVRAM_BUFFERED);
14461 tg3_flag_set(tp, FLASH);
14463 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14464 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14465 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14466 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14467 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14469 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14470 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14471 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14473 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14474 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14475 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14479 case FLASH_5752VENDOR_ST_M45PE10:
14480 case FLASH_5752VENDOR_ST_M45PE20:
14481 case FLASH_5752VENDOR_ST_M45PE40:
14482 tp->nvram_jedecnum = JEDEC_ST;
14483 tg3_flag_set(tp, NVRAM_BUFFERED);
14484 tg3_flag_set(tp, FLASH);
14486 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14487 case FLASH_5752VENDOR_ST_M45PE10:
14488 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14490 case FLASH_5752VENDOR_ST_M45PE20:
14491 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14493 case FLASH_5752VENDOR_ST_M45PE40:
14494 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14499 tg3_flag_set(tp, NO_NVRAM);
14503 tg3_nvram_get_pagesize(tp, nvcfg1);
14504 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14505 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14509 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14513 nvcfg1 = tr32(NVRAM_CFG1);
14515 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14516 case FLASH_5717VENDOR_ATMEL_EEPROM:
14517 case FLASH_5717VENDOR_MICRO_EEPROM:
14518 tp->nvram_jedecnum = JEDEC_ATMEL;
14519 tg3_flag_set(tp, NVRAM_BUFFERED);
14520 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14522 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14523 tw32(NVRAM_CFG1, nvcfg1);
14525 case FLASH_5717VENDOR_ATMEL_MDB011D:
14526 case FLASH_5717VENDOR_ATMEL_ADB011B:
14527 case FLASH_5717VENDOR_ATMEL_ADB011D:
14528 case FLASH_5717VENDOR_ATMEL_MDB021D:
14529 case FLASH_5717VENDOR_ATMEL_ADB021B:
14530 case FLASH_5717VENDOR_ATMEL_ADB021D:
14531 case FLASH_5717VENDOR_ATMEL_45USPT:
14532 tp->nvram_jedecnum = JEDEC_ATMEL;
14533 tg3_flag_set(tp, NVRAM_BUFFERED);
14534 tg3_flag_set(tp, FLASH);
14536 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14537 case FLASH_5717VENDOR_ATMEL_MDB021D:
14538 /* Detect size with tg3_nvram_get_size() */
14540 case FLASH_5717VENDOR_ATMEL_ADB021B:
14541 case FLASH_5717VENDOR_ATMEL_ADB021D:
14542 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14545 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14549 case FLASH_5717VENDOR_ST_M_M25PE10:
14550 case FLASH_5717VENDOR_ST_A_M25PE10:
14551 case FLASH_5717VENDOR_ST_M_M45PE10:
14552 case FLASH_5717VENDOR_ST_A_M45PE10:
14553 case FLASH_5717VENDOR_ST_M_M25PE20:
14554 case FLASH_5717VENDOR_ST_A_M25PE20:
14555 case FLASH_5717VENDOR_ST_M_M45PE20:
14556 case FLASH_5717VENDOR_ST_A_M45PE20:
14557 case FLASH_5717VENDOR_ST_25USPT:
14558 case FLASH_5717VENDOR_ST_45USPT:
14559 tp->nvram_jedecnum = JEDEC_ST;
14560 tg3_flag_set(tp, NVRAM_BUFFERED);
14561 tg3_flag_set(tp, FLASH);
14563 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14564 case FLASH_5717VENDOR_ST_M_M25PE20:
14565 case FLASH_5717VENDOR_ST_M_M45PE20:
14566 /* Detect size with tg3_nvram_get_size() */
14568 case FLASH_5717VENDOR_ST_A_M25PE20:
14569 case FLASH_5717VENDOR_ST_A_M45PE20:
14570 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14573 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14578 tg3_flag_set(tp, NO_NVRAM);
14582 tg3_nvram_get_pagesize(tp, nvcfg1);
14583 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14584 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14587 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14589 u32 nvcfg1, nvmpinstrp;
14591 nvcfg1 = tr32(NVRAM_CFG1);
14592 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14594 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14595 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14596 tg3_flag_set(tp, NO_NVRAM);
14600 switch (nvmpinstrp) {
14601 case FLASH_5762_EEPROM_HD:
14602 nvmpinstrp = FLASH_5720_EEPROM_HD;
14604 case FLASH_5762_EEPROM_LD:
14605 nvmpinstrp = FLASH_5720_EEPROM_LD;
14607 case FLASH_5720VENDOR_M_ST_M45PE20:
14608 /* This pinstrap supports multiple sizes, so force it
14609 * to read the actual size from location 0xf0.
14611 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14616 switch (nvmpinstrp) {
14617 case FLASH_5720_EEPROM_HD:
14618 case FLASH_5720_EEPROM_LD:
14619 tp->nvram_jedecnum = JEDEC_ATMEL;
14620 tg3_flag_set(tp, NVRAM_BUFFERED);
14622 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14623 tw32(NVRAM_CFG1, nvcfg1);
14624 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14625 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14627 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14629 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14630 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14631 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14632 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14633 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14634 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14635 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14636 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14637 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14638 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14639 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14640 case FLASH_5720VENDOR_ATMEL_45USPT:
14641 tp->nvram_jedecnum = JEDEC_ATMEL;
14642 tg3_flag_set(tp, NVRAM_BUFFERED);
14643 tg3_flag_set(tp, FLASH);
14645 switch (nvmpinstrp) {
14646 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14647 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14648 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14649 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14651 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14652 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14653 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14654 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14656 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14657 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14658 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14661 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14662 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14666 case FLASH_5720VENDOR_M_ST_M25PE10:
14667 case FLASH_5720VENDOR_M_ST_M45PE10:
14668 case FLASH_5720VENDOR_A_ST_M25PE10:
14669 case FLASH_5720VENDOR_A_ST_M45PE10:
14670 case FLASH_5720VENDOR_M_ST_M25PE20:
14671 case FLASH_5720VENDOR_M_ST_M45PE20:
14672 case FLASH_5720VENDOR_A_ST_M25PE20:
14673 case FLASH_5720VENDOR_A_ST_M45PE20:
14674 case FLASH_5720VENDOR_M_ST_M25PE40:
14675 case FLASH_5720VENDOR_M_ST_M45PE40:
14676 case FLASH_5720VENDOR_A_ST_M25PE40:
14677 case FLASH_5720VENDOR_A_ST_M45PE40:
14678 case FLASH_5720VENDOR_M_ST_M25PE80:
14679 case FLASH_5720VENDOR_M_ST_M45PE80:
14680 case FLASH_5720VENDOR_A_ST_M25PE80:
14681 case FLASH_5720VENDOR_A_ST_M45PE80:
14682 case FLASH_5720VENDOR_ST_25USPT:
14683 case FLASH_5720VENDOR_ST_45USPT:
14684 tp->nvram_jedecnum = JEDEC_ST;
14685 tg3_flag_set(tp, NVRAM_BUFFERED);
14686 tg3_flag_set(tp, FLASH);
14688 switch (nvmpinstrp) {
14689 case FLASH_5720VENDOR_M_ST_M25PE20:
14690 case FLASH_5720VENDOR_M_ST_M45PE20:
14691 case FLASH_5720VENDOR_A_ST_M25PE20:
14692 case FLASH_5720VENDOR_A_ST_M45PE20:
14693 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14695 case FLASH_5720VENDOR_M_ST_M25PE40:
14696 case FLASH_5720VENDOR_M_ST_M45PE40:
14697 case FLASH_5720VENDOR_A_ST_M25PE40:
14698 case FLASH_5720VENDOR_A_ST_M45PE40:
14699 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14701 case FLASH_5720VENDOR_M_ST_M25PE80:
14702 case FLASH_5720VENDOR_M_ST_M45PE80:
14703 case FLASH_5720VENDOR_A_ST_M25PE80:
14704 case FLASH_5720VENDOR_A_ST_M45PE80:
14705 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14708 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14709 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14714 tg3_flag_set(tp, NO_NVRAM);
14718 tg3_nvram_get_pagesize(tp, nvcfg1);
14719 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14720 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14722 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14725 if (tg3_nvram_read(tp, 0, &val))
14728 if (val != TG3_EEPROM_MAGIC &&
14729 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14730 tg3_flag_set(tp, NO_NVRAM);
14734 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14735 static void tg3_nvram_init(struct tg3 *tp)
14737 if (tg3_flag(tp, IS_SSB_CORE)) {
14738 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14739 tg3_flag_clear(tp, NVRAM);
14740 tg3_flag_clear(tp, NVRAM_BUFFERED);
14741 tg3_flag_set(tp, NO_NVRAM);
14745 tw32_f(GRC_EEPROM_ADDR,
14746 (EEPROM_ADDR_FSM_RESET |
14747 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14748 EEPROM_ADDR_CLKPERD_SHIFT)));
14752 /* Enable seeprom accesses. */
14753 tw32_f(GRC_LOCAL_CTRL,
14754 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14757 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14758 tg3_asic_rev(tp) != ASIC_REV_5701) {
14759 tg3_flag_set(tp, NVRAM);
14761 if (tg3_nvram_lock(tp)) {
14762 netdev_warn(tp->dev,
14763 "Cannot get nvram lock, %s failed\n",
14767 tg3_enable_nvram_access(tp);
14769 tp->nvram_size = 0;
14771 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14772 tg3_get_5752_nvram_info(tp);
14773 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14774 tg3_get_5755_nvram_info(tp);
14775 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14776 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14777 tg3_asic_rev(tp) == ASIC_REV_5785)
14778 tg3_get_5787_nvram_info(tp);
14779 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14780 tg3_get_5761_nvram_info(tp);
14781 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14782 tg3_get_5906_nvram_info(tp);
14783 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14784 tg3_flag(tp, 57765_CLASS))
14785 tg3_get_57780_nvram_info(tp);
14786 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14787 tg3_asic_rev(tp) == ASIC_REV_5719)
14788 tg3_get_5717_nvram_info(tp);
14789 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14790 tg3_asic_rev(tp) == ASIC_REV_5762)
14791 tg3_get_5720_nvram_info(tp);
14793 tg3_get_nvram_info(tp);
14795 if (tp->nvram_size == 0)
14796 tg3_get_nvram_size(tp);
14798 tg3_disable_nvram_access(tp);
14799 tg3_nvram_unlock(tp);
14802 tg3_flag_clear(tp, NVRAM);
14803 tg3_flag_clear(tp, NVRAM_BUFFERED);
14805 tg3_get_eeprom_size(tp);
14809 struct subsys_tbl_ent {
14810 u16 subsys_vendor, subsys_devid;
14814 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14815 /* Broadcom boards. */
14816 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14817 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14818 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14819 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14820 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14821 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14822 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14823 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14824 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14825 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14826 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14827 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14828 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14829 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14830 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14831 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14832 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14833 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14834 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14835 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14836 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14837 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
14840 { TG3PCI_SUBVENDOR_ID_3COM,
14841 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
14842 { TG3PCI_SUBVENDOR_ID_3COM,
14843 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
14844 { TG3PCI_SUBVENDOR_ID_3COM,
14845 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
14846 { TG3PCI_SUBVENDOR_ID_3COM,
14847 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
14848 { TG3PCI_SUBVENDOR_ID_3COM,
14849 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
14852 { TG3PCI_SUBVENDOR_ID_DELL,
14853 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
14854 { TG3PCI_SUBVENDOR_ID_DELL,
14855 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
14856 { TG3PCI_SUBVENDOR_ID_DELL,
14857 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
14858 { TG3PCI_SUBVENDOR_ID_DELL,
14859 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
14861 /* Compaq boards. */
14862 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14863 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
14864 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14865 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
14866 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14867 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
14868 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14869 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
14870 { TG3PCI_SUBVENDOR_ID_COMPAQ,
14871 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
14874 { TG3PCI_SUBVENDOR_ID_IBM,
14875 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
14878 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
14882 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
14883 if ((subsys_id_to_phy_id[i].subsys_vendor ==
14884 tp->pdev->subsystem_vendor) &&
14885 (subsys_id_to_phy_id[i].subsys_devid ==
14886 tp->pdev->subsystem_device))
14887 return &subsys_id_to_phy_id[i];
14892 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
14896 tp->phy_id = TG3_PHY_ID_INVALID;
14897 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14899 /* Assume an onboard device and WOL capable by default. */
14900 tg3_flag_set(tp, EEPROM_WRITE_PROT);
14901 tg3_flag_set(tp, WOL_CAP);
14903 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
14904 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
14905 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
14906 tg3_flag_set(tp, IS_NIC);
14908 val = tr32(VCPU_CFGSHDW);
14909 if (val & VCPU_CFGSHDW_ASPM_DBNC)
14910 tg3_flag_set(tp, ASPM_WORKAROUND);
14911 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
14912 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
14913 tg3_flag_set(tp, WOL_ENABLE);
14914 device_set_wakeup_enable(&tp->pdev->dev, true);
14919 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
14920 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
14921 u32 nic_cfg, led_cfg;
14922 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
14923 int eeprom_phy_serdes = 0;
14925 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
14926 tp->nic_sram_data_cfg = nic_cfg;
14928 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
14929 ver >>= NIC_SRAM_DATA_VER_SHIFT;
14930 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14931 tg3_asic_rev(tp) != ASIC_REV_5701 &&
14932 tg3_asic_rev(tp) != ASIC_REV_5703 &&
14933 (ver > 0) && (ver < 0x100))
14934 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
14936 if (tg3_asic_rev(tp) == ASIC_REV_5785)
14937 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
14939 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
14940 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
14941 eeprom_phy_serdes = 1;
14943 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
14944 if (nic_phy_id != 0) {
14945 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
14946 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
14948 eeprom_phy_id = (id1 >> 16) << 10;
14949 eeprom_phy_id |= (id2 & 0xfc00) << 16;
14950 eeprom_phy_id |= (id2 & 0x03ff) << 0;
14954 tp->phy_id = eeprom_phy_id;
14955 if (eeprom_phy_serdes) {
14956 if (!tg3_flag(tp, 5705_PLUS))
14957 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
14959 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
14962 if (tg3_flag(tp, 5750_PLUS))
14963 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
14964 SHASTA_EXT_LED_MODE_MASK);
14966 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
14970 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
14971 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14974 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
14975 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
14978 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
14979 tp->led_ctrl = LED_CTRL_MODE_MAC;
14981 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14982 * read on some older 5700/5701 bootcode.
14984 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
14985 tg3_asic_rev(tp) == ASIC_REV_5701)
14986 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
14990 case SHASTA_EXT_LED_SHARED:
14991 tp->led_ctrl = LED_CTRL_MODE_SHARED;
14992 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
14993 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
14994 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
14995 LED_CTRL_MODE_PHY_2);
14997 if (tg3_flag(tp, 5717_PLUS) ||
14998 tg3_asic_rev(tp) == ASIC_REV_5762)
14999 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15000 LED_CTRL_BLINK_RATE_MASK;
15004 case SHASTA_EXT_LED_MAC:
15005 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15008 case SHASTA_EXT_LED_COMBO:
15009 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15010 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15011 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15012 LED_CTRL_MODE_PHY_2);
15017 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15018 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15019 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15020 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15022 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15023 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15025 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15026 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15027 if ((tp->pdev->subsystem_vendor ==
15028 PCI_VENDOR_ID_ARIMA) &&
15029 (tp->pdev->subsystem_device == 0x205a ||
15030 tp->pdev->subsystem_device == 0x2063))
15031 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15033 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15034 tg3_flag_set(tp, IS_NIC);
15037 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15038 tg3_flag_set(tp, ENABLE_ASF);
15039 if (tg3_flag(tp, 5750_PLUS))
15040 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15043 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15044 tg3_flag(tp, 5750_PLUS))
15045 tg3_flag_set(tp, ENABLE_APE);
15047 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15048 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15049 tg3_flag_clear(tp, WOL_CAP);
15051 if (tg3_flag(tp, WOL_CAP) &&
15052 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15053 tg3_flag_set(tp, WOL_ENABLE);
15054 device_set_wakeup_enable(&tp->pdev->dev, true);
15057 if (cfg2 & (1 << 17))
15058 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15060 /* serdes signal pre-emphasis in register 0x590 set by */
15061 /* bootcode if bit 18 is set */
15062 if (cfg2 & (1 << 18))
15063 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15065 if ((tg3_flag(tp, 57765_PLUS) ||
15066 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15067 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15068 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15069 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15071 if (tg3_flag(tp, PCI_EXPRESS)) {
15074 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15075 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15076 !tg3_flag(tp, 57765_PLUS) &&
15077 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15078 tg3_flag_set(tp, ASPM_WORKAROUND);
15079 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15080 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15081 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15082 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15085 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15086 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15087 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15088 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15089 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15090 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15093 if (tg3_flag(tp, WOL_CAP))
15094 device_set_wakeup_enable(&tp->pdev->dev,
15095 tg3_flag(tp, WOL_ENABLE));
15097 device_set_wakeup_capable(&tp->pdev->dev, false);
15100 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15103 u32 val2, off = offset * 8;
15105 err = tg3_nvram_lock(tp);
15109 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15110 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15111 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15112 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15115 for (i = 0; i < 100; i++) {
15116 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15117 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15118 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15124 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15126 tg3_nvram_unlock(tp);
15127 if (val2 & APE_OTP_STATUS_CMD_DONE)
15133 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15138 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15139 tw32(OTP_CTRL, cmd);
15141 /* Wait for up to 1 ms for command to execute. */
15142 for (i = 0; i < 100; i++) {
15143 val = tr32(OTP_STATUS);
15144 if (val & OTP_STATUS_CMD_DONE)
15149 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15152 /* Read the gphy configuration from the OTP region of the chip. The gphy
15153 * configuration is a 32-bit value that straddles the alignment boundary.
15154 * We do two 32-bit reads and then shift and merge the results.
15156 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15158 u32 bhalf_otp, thalf_otp;
15160 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15162 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15165 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15167 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15170 thalf_otp = tr32(OTP_READ_DATA);
15172 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15174 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15177 bhalf_otp = tr32(OTP_READ_DATA);
15179 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15182 static void tg3_phy_init_link_config(struct tg3 *tp)
15184 u32 adv = ADVERTISED_Autoneg;
15186 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15187 adv |= ADVERTISED_1000baseT_Half |
15188 ADVERTISED_1000baseT_Full;
15190 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15191 adv |= ADVERTISED_100baseT_Half |
15192 ADVERTISED_100baseT_Full |
15193 ADVERTISED_10baseT_Half |
15194 ADVERTISED_10baseT_Full |
15197 adv |= ADVERTISED_FIBRE;
15199 tp->link_config.advertising = adv;
15200 tp->link_config.speed = SPEED_UNKNOWN;
15201 tp->link_config.duplex = DUPLEX_UNKNOWN;
15202 tp->link_config.autoneg = AUTONEG_ENABLE;
15203 tp->link_config.active_speed = SPEED_UNKNOWN;
15204 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15209 static int tg3_phy_probe(struct tg3 *tp)
15211 u32 hw_phy_id_1, hw_phy_id_2;
15212 u32 hw_phy_id, hw_phy_id_masked;
15215 /* flow control autonegotiation is default behavior */
15216 tg3_flag_set(tp, PAUSE_AUTONEG);
15217 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15219 if (tg3_flag(tp, ENABLE_APE)) {
15220 switch (tp->pci_fn) {
15222 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15225 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15228 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15231 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15236 if (!tg3_flag(tp, ENABLE_ASF) &&
15237 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15238 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15239 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15240 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15242 if (tg3_flag(tp, USE_PHYLIB))
15243 return tg3_phy_init(tp);
15245 /* Reading the PHY ID register can conflict with ASF
15246 * firmware access to the PHY hardware.
15249 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15250 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15252 /* Now read the physical PHY_ID from the chip and verify
15253 * that it is sane. If it doesn't look good, we fall back
15254 * to either the hard-coded table based PHY_ID and failing
15255 * that the value found in the eeprom area.
15257 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15258 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15260 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15261 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15262 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15264 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15267 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15268 tp->phy_id = hw_phy_id;
15269 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15270 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15272 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15274 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15275 /* Do nothing, phy ID already set up in
15276 * tg3_get_eeprom_hw_cfg().
15279 struct subsys_tbl_ent *p;
15281 /* No eeprom signature? Try the hardcoded
15282 * subsys device table.
15284 p = tg3_lookup_by_subsys(tp);
15286 tp->phy_id = p->phy_id;
15287 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15288 /* For now we saw the IDs 0xbc050cd0,
15289 * 0xbc050f80 and 0xbc050c30 on devices
15290 * connected to an BCM4785 and there are
15291 * probably more. Just assume that the phy is
15292 * supported when it is connected to a SSB core
15299 tp->phy_id == TG3_PHY_ID_BCM8002)
15300 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15304 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15305 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15306 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15307 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15308 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15309 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15310 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15311 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15312 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15313 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15315 tp->eee.supported = SUPPORTED_100baseT_Full |
15316 SUPPORTED_1000baseT_Full;
15317 tp->eee.advertised = ADVERTISED_100baseT_Full |
15318 ADVERTISED_1000baseT_Full;
15319 tp->eee.eee_enabled = 1;
15320 tp->eee.tx_lpi_enabled = 1;
15321 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15324 tg3_phy_init_link_config(tp);
15326 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15327 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15328 !tg3_flag(tp, ENABLE_APE) &&
15329 !tg3_flag(tp, ENABLE_ASF)) {
15332 tg3_readphy(tp, MII_BMSR, &bmsr);
15333 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15334 (bmsr & BMSR_LSTATUS))
15335 goto skip_phy_reset;
15337 err = tg3_phy_reset(tp);
15341 tg3_phy_set_wirespeed(tp);
15343 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15344 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15345 tp->link_config.flowctrl);
15347 tg3_writephy(tp, MII_BMCR,
15348 BMCR_ANENABLE | BMCR_ANRESTART);
15353 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15354 err = tg3_init_5401phy_dsp(tp);
15358 err = tg3_init_5401phy_dsp(tp);
15364 static void tg3_read_vpd(struct tg3 *tp)
15367 unsigned int block_end, rosize, len;
15371 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15375 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15377 goto out_not_found;
15379 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15380 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15381 i += PCI_VPD_LRDT_TAG_SIZE;
15383 if (block_end > vpdlen)
15384 goto out_not_found;
15386 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15387 PCI_VPD_RO_KEYWORD_MFR_ID);
15389 len = pci_vpd_info_field_size(&vpd_data[j]);
15391 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15392 if (j + len > block_end || len != 4 ||
15393 memcmp(&vpd_data[j], "1028", 4))
15396 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15397 PCI_VPD_RO_KEYWORD_VENDOR0);
15401 len = pci_vpd_info_field_size(&vpd_data[j]);
15403 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15404 if (j + len > block_end)
15407 if (len >= sizeof(tp->fw_ver))
15408 len = sizeof(tp->fw_ver) - 1;
15409 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15410 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15415 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15416 PCI_VPD_RO_KEYWORD_PARTNO);
15418 goto out_not_found;
15420 len = pci_vpd_info_field_size(&vpd_data[i]);
15422 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15423 if (len > TG3_BPN_SIZE ||
15424 (len + i) > vpdlen)
15425 goto out_not_found;
15427 memcpy(tp->board_part_number, &vpd_data[i], len);
15431 if (tp->board_part_number[0])
15435 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15436 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15437 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15438 strcpy(tp->board_part_number, "BCM5717");
15439 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15440 strcpy(tp->board_part_number, "BCM5718");
15443 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15444 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15445 strcpy(tp->board_part_number, "BCM57780");
15446 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15447 strcpy(tp->board_part_number, "BCM57760");
15448 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15449 strcpy(tp->board_part_number, "BCM57790");
15450 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15451 strcpy(tp->board_part_number, "BCM57788");
15454 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15455 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15456 strcpy(tp->board_part_number, "BCM57761");
15457 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15458 strcpy(tp->board_part_number, "BCM57765");
15459 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15460 strcpy(tp->board_part_number, "BCM57781");
15461 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15462 strcpy(tp->board_part_number, "BCM57785");
15463 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15464 strcpy(tp->board_part_number, "BCM57791");
15465 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15466 strcpy(tp->board_part_number, "BCM57795");
15469 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15470 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15471 strcpy(tp->board_part_number, "BCM57762");
15472 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15473 strcpy(tp->board_part_number, "BCM57766");
15474 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15475 strcpy(tp->board_part_number, "BCM57782");
15476 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15477 strcpy(tp->board_part_number, "BCM57786");
15480 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15481 strcpy(tp->board_part_number, "BCM95906");
15484 strcpy(tp->board_part_number, "none");
15488 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15492 if (tg3_nvram_read(tp, offset, &val) ||
15493 (val & 0xfc000000) != 0x0c000000 ||
15494 tg3_nvram_read(tp, offset + 4, &val) ||
15501 static void tg3_read_bc_ver(struct tg3 *tp)
15503 u32 val, offset, start, ver_offset;
15505 bool newver = false;
15507 if (tg3_nvram_read(tp, 0xc, &offset) ||
15508 tg3_nvram_read(tp, 0x4, &start))
15511 offset = tg3_nvram_logical_addr(tp, offset);
15513 if (tg3_nvram_read(tp, offset, &val))
15516 if ((val & 0xfc000000) == 0x0c000000) {
15517 if (tg3_nvram_read(tp, offset + 4, &val))
15524 dst_off = strlen(tp->fw_ver);
15527 if (TG3_VER_SIZE - dst_off < 16 ||
15528 tg3_nvram_read(tp, offset + 8, &ver_offset))
15531 offset = offset + ver_offset - start;
15532 for (i = 0; i < 16; i += 4) {
15534 if (tg3_nvram_read_be32(tp, offset + i, &v))
15537 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15542 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15545 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15546 TG3_NVM_BCVER_MAJSFT;
15547 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15548 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15549 "v%d.%02d", major, minor);
15553 static void tg3_read_hwsb_ver(struct tg3 *tp)
15555 u32 val, major, minor;
15557 /* Use native endian representation */
15558 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15561 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15562 TG3_NVM_HWSB_CFG1_MAJSFT;
15563 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15564 TG3_NVM_HWSB_CFG1_MINSFT;
15566 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15569 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15571 u32 offset, major, minor, build;
15573 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15575 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15578 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15579 case TG3_EEPROM_SB_REVISION_0:
15580 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15582 case TG3_EEPROM_SB_REVISION_2:
15583 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15585 case TG3_EEPROM_SB_REVISION_3:
15586 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15588 case TG3_EEPROM_SB_REVISION_4:
15589 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15591 case TG3_EEPROM_SB_REVISION_5:
15592 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15594 case TG3_EEPROM_SB_REVISION_6:
15595 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15601 if (tg3_nvram_read(tp, offset, &val))
15604 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15605 TG3_EEPROM_SB_EDH_BLD_SHFT;
15606 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15607 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15608 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15610 if (minor > 99 || build > 26)
15613 offset = strlen(tp->fw_ver);
15614 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15615 " v%d.%02d", major, minor);
15618 offset = strlen(tp->fw_ver);
15619 if (offset < TG3_VER_SIZE - 1)
15620 tp->fw_ver[offset] = 'a' + build - 1;
15624 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15626 u32 val, offset, start;
15629 for (offset = TG3_NVM_DIR_START;
15630 offset < TG3_NVM_DIR_END;
15631 offset += TG3_NVM_DIRENT_SIZE) {
15632 if (tg3_nvram_read(tp, offset, &val))
15635 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15639 if (offset == TG3_NVM_DIR_END)
15642 if (!tg3_flag(tp, 5705_PLUS))
15643 start = 0x08000000;
15644 else if (tg3_nvram_read(tp, offset - 4, &start))
15647 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15648 !tg3_fw_img_is_valid(tp, offset) ||
15649 tg3_nvram_read(tp, offset + 8, &val))
15652 offset += val - start;
15654 vlen = strlen(tp->fw_ver);
15656 tp->fw_ver[vlen++] = ',';
15657 tp->fw_ver[vlen++] = ' ';
15659 for (i = 0; i < 4; i++) {
15661 if (tg3_nvram_read_be32(tp, offset, &v))
15664 offset += sizeof(v);
15666 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15667 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15671 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15676 static void tg3_probe_ncsi(struct tg3 *tp)
15680 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15681 if (apedata != APE_SEG_SIG_MAGIC)
15684 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15685 if (!(apedata & APE_FW_STATUS_READY))
15688 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15689 tg3_flag_set(tp, APE_HAS_NCSI);
15692 static void tg3_read_dash_ver(struct tg3 *tp)
15698 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15700 if (tg3_flag(tp, APE_HAS_NCSI))
15702 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15707 vlen = strlen(tp->fw_ver);
15709 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15711 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15712 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15713 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15714 (apedata & APE_FW_VERSION_BLDMSK));
15717 static void tg3_read_otp_ver(struct tg3 *tp)
15721 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15724 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15725 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15726 TG3_OTP_MAGIC0_VALID(val)) {
15727 u64 val64 = (u64) val << 32 | val2;
15731 for (i = 0; i < 7; i++) {
15732 if ((val64 & 0xff) == 0)
15734 ver = val64 & 0xff;
15737 vlen = strlen(tp->fw_ver);
15738 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15742 static void tg3_read_fw_ver(struct tg3 *tp)
15745 bool vpd_vers = false;
15747 if (tp->fw_ver[0] != 0)
15750 if (tg3_flag(tp, NO_NVRAM)) {
15751 strcat(tp->fw_ver, "sb");
15752 tg3_read_otp_ver(tp);
15756 if (tg3_nvram_read(tp, 0, &val))
15759 if (val == TG3_EEPROM_MAGIC)
15760 tg3_read_bc_ver(tp);
15761 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15762 tg3_read_sb_ver(tp, val);
15763 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15764 tg3_read_hwsb_ver(tp);
15766 if (tg3_flag(tp, ENABLE_ASF)) {
15767 if (tg3_flag(tp, ENABLE_APE)) {
15768 tg3_probe_ncsi(tp);
15770 tg3_read_dash_ver(tp);
15771 } else if (!vpd_vers) {
15772 tg3_read_mgmtfw_ver(tp);
15776 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15779 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15781 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15782 return TG3_RX_RET_MAX_SIZE_5717;
15783 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15784 return TG3_RX_RET_MAX_SIZE_5700;
15786 return TG3_RX_RET_MAX_SIZE_5705;
15789 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets) = {
15790 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15791 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15792 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15796 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15798 struct pci_dev *peer;
15799 unsigned int func, devnr = tp->pdev->devfn & ~7;
15801 for (func = 0; func < 8; func++) {
15802 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15803 if (peer && peer != tp->pdev)
15807 /* 5704 can be configured in single-port mode, set peer to
15808 * tp->pdev in that case.
15816 * We don't need to keep the refcount elevated; there's no way
15817 * to remove one half of this device without removing the other
15824 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15826 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15827 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
15830 /* All devices that use the alternate
15831 * ASIC REV location have a CPMU.
15833 tg3_flag_set(tp, CPMU_PRESENT);
15835 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15836 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
15837 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
15838 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
15839 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
15840 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
15841 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
15842 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
15843 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
15844 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
15845 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
15846 reg = TG3PCI_GEN2_PRODID_ASICREV;
15847 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
15848 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
15849 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
15850 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
15851 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
15852 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
15853 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
15854 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
15855 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
15856 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15857 reg = TG3PCI_GEN15_PRODID_ASICREV;
15859 reg = TG3PCI_PRODID_ASICREV;
15861 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
15864 /* Wrong chip ID in 5752 A0. This code can be removed later
15865 * as A0 is not in production.
15867 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
15868 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
15870 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
15871 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
15873 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15874 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15875 tg3_asic_rev(tp) == ASIC_REV_5720)
15876 tg3_flag_set(tp, 5717_PLUS);
15878 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
15879 tg3_asic_rev(tp) == ASIC_REV_57766)
15880 tg3_flag_set(tp, 57765_CLASS);
15882 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
15883 tg3_asic_rev(tp) == ASIC_REV_5762)
15884 tg3_flag_set(tp, 57765_PLUS);
15886 /* Intentionally exclude ASIC_REV_5906 */
15887 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
15888 tg3_asic_rev(tp) == ASIC_REV_5787 ||
15889 tg3_asic_rev(tp) == ASIC_REV_5784 ||
15890 tg3_asic_rev(tp) == ASIC_REV_5761 ||
15891 tg3_asic_rev(tp) == ASIC_REV_5785 ||
15892 tg3_asic_rev(tp) == ASIC_REV_57780 ||
15893 tg3_flag(tp, 57765_PLUS))
15894 tg3_flag_set(tp, 5755_PLUS);
15896 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
15897 tg3_asic_rev(tp) == ASIC_REV_5714)
15898 tg3_flag_set(tp, 5780_CLASS);
15900 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
15901 tg3_asic_rev(tp) == ASIC_REV_5752 ||
15902 tg3_asic_rev(tp) == ASIC_REV_5906 ||
15903 tg3_flag(tp, 5755_PLUS) ||
15904 tg3_flag(tp, 5780_CLASS))
15905 tg3_flag_set(tp, 5750_PLUS);
15907 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
15908 tg3_flag(tp, 5750_PLUS))
15909 tg3_flag_set(tp, 5705_PLUS);
15912 static bool tg3_10_100_only_device(struct tg3 *tp,
15913 const struct pci_device_id *ent)
15915 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
15917 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
15918 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
15919 (tp->phy_flags & TG3_PHYFLG_IS_FET))
15922 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
15923 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
15924 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
15934 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
15937 u32 pci_state_reg, grc_misc_cfg;
15942 /* Force memory write invalidate off. If we leave it on,
15943 * then on 5700_BX chips we have to enable a workaround.
15944 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15945 * to match the cacheline size. The Broadcom driver have this
15946 * workaround but turns MWI off all the times so never uses
15947 * it. This seems to suggest that the workaround is insufficient.
15949 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
15950 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
15951 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
15953 /* Important! -- Make sure register accesses are byteswapped
15954 * correctly. Also, for those chips that require it, make
15955 * sure that indirect register accesses are enabled before
15956 * the first operation.
15958 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15960 tp->misc_host_ctrl |= (misc_ctrl_reg &
15961 MISC_HOST_CTRL_CHIPREV);
15962 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
15963 tp->misc_host_ctrl);
15965 tg3_detect_asic_rev(tp, misc_ctrl_reg);
15967 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15968 * we need to disable memory and use config. cycles
15969 * only to access all registers. The 5702/03 chips
15970 * can mistakenly decode the special cycles from the
15971 * ICH chipsets as memory write cycles, causing corruption
15972 * of register and memory space. Only certain ICH bridges
15973 * will drive special cycles with non-zero data during the
15974 * address phase which can fall within the 5703's address
15975 * range. This is not an ICH bug as the PCI spec allows
15976 * non-zero address during special cycles. However, only
15977 * these ICH bridges are known to drive non-zero addresses
15978 * during special cycles.
15980 * Since special cycles do not cross PCI bridges, we only
15981 * enable this workaround if the 5703 is on the secondary
15982 * bus of these ICH bridges.
15984 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
15985 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
15986 static struct tg3_dev_id {
15990 } ich_chipsets[] = {
15991 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
15993 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
15995 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
15997 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16001 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16002 struct pci_dev *bridge = NULL;
16004 while (pci_id->vendor != 0) {
16005 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16011 if (pci_id->rev != PCI_ANY_ID) {
16012 if (bridge->revision > pci_id->rev)
16015 if (bridge->subordinate &&
16016 (bridge->subordinate->number ==
16017 tp->pdev->bus->number)) {
16018 tg3_flag_set(tp, ICH_WORKAROUND);
16019 pci_dev_put(bridge);
16025 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16026 static struct tg3_dev_id {
16029 } bridge_chipsets[] = {
16030 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16031 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16034 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16035 struct pci_dev *bridge = NULL;
16037 while (pci_id->vendor != 0) {
16038 bridge = pci_get_device(pci_id->vendor,
16045 if (bridge->subordinate &&
16046 (bridge->subordinate->number <=
16047 tp->pdev->bus->number) &&
16048 (bridge->subordinate->busn_res.end >=
16049 tp->pdev->bus->number)) {
16050 tg3_flag_set(tp, 5701_DMA_BUG);
16051 pci_dev_put(bridge);
16057 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16058 * DMA addresses > 40-bit. This bridge may have other additional
16059 * 57xx devices behind it in some 4-port NIC designs for example.
16060 * Any tg3 device found behind the bridge will also need the 40-bit
16063 if (tg3_flag(tp, 5780_CLASS)) {
16064 tg3_flag_set(tp, 40BIT_DMA_BUG);
16065 tp->msi_cap = tp->pdev->msi_cap;
16067 struct pci_dev *bridge = NULL;
16070 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16071 PCI_DEVICE_ID_SERVERWORKS_EPB,
16073 if (bridge && bridge->subordinate &&
16074 (bridge->subordinate->number <=
16075 tp->pdev->bus->number) &&
16076 (bridge->subordinate->busn_res.end >=
16077 tp->pdev->bus->number)) {
16078 tg3_flag_set(tp, 40BIT_DMA_BUG);
16079 pci_dev_put(bridge);
16085 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16086 tg3_asic_rev(tp) == ASIC_REV_5714)
16087 tp->pdev_peer = tg3_find_peer(tp);
16089 /* Determine TSO capabilities */
16090 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16091 ; /* Do nothing. HW bug. */
16092 else if (tg3_flag(tp, 57765_PLUS))
16093 tg3_flag_set(tp, HW_TSO_3);
16094 else if (tg3_flag(tp, 5755_PLUS) ||
16095 tg3_asic_rev(tp) == ASIC_REV_5906)
16096 tg3_flag_set(tp, HW_TSO_2);
16097 else if (tg3_flag(tp, 5750_PLUS)) {
16098 tg3_flag_set(tp, HW_TSO_1);
16099 tg3_flag_set(tp, TSO_BUG);
16100 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16101 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16102 tg3_flag_clear(tp, TSO_BUG);
16103 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16104 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16105 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16106 tg3_flag_set(tp, FW_TSO);
16107 tg3_flag_set(tp, TSO_BUG);
16108 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16109 tp->fw_needed = FIRMWARE_TG3TSO5;
16111 tp->fw_needed = FIRMWARE_TG3TSO;
16114 /* Selectively allow TSO based on operating conditions */
16115 if (tg3_flag(tp, HW_TSO_1) ||
16116 tg3_flag(tp, HW_TSO_2) ||
16117 tg3_flag(tp, HW_TSO_3) ||
16118 tg3_flag(tp, FW_TSO)) {
16119 /* For firmware TSO, assume ASF is disabled.
16120 * We'll disable TSO later if we discover ASF
16121 * is enabled in tg3_get_eeprom_hw_cfg().
16123 tg3_flag_set(tp, TSO_CAPABLE);
16125 tg3_flag_clear(tp, TSO_CAPABLE);
16126 tg3_flag_clear(tp, TSO_BUG);
16127 tp->fw_needed = NULL;
16130 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16131 tp->fw_needed = FIRMWARE_TG3;
16133 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16134 tp->fw_needed = FIRMWARE_TG357766;
16138 if (tg3_flag(tp, 5750_PLUS)) {
16139 tg3_flag_set(tp, SUPPORT_MSI);
16140 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16141 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16142 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16143 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16144 tp->pdev_peer == tp->pdev))
16145 tg3_flag_clear(tp, SUPPORT_MSI);
16147 if (tg3_flag(tp, 5755_PLUS) ||
16148 tg3_asic_rev(tp) == ASIC_REV_5906) {
16149 tg3_flag_set(tp, 1SHOT_MSI);
16152 if (tg3_flag(tp, 57765_PLUS)) {
16153 tg3_flag_set(tp, SUPPORT_MSIX);
16154 tp->irq_max = TG3_IRQ_MAX_VECS;
16160 if (tp->irq_max > 1) {
16161 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16162 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16164 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16165 tg3_asic_rev(tp) == ASIC_REV_5720)
16166 tp->txq_max = tp->irq_max - 1;
16169 if (tg3_flag(tp, 5755_PLUS) ||
16170 tg3_asic_rev(tp) == ASIC_REV_5906)
16171 tg3_flag_set(tp, SHORT_DMA_BUG);
16173 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16174 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16176 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16177 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16178 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16179 tg3_asic_rev(tp) == ASIC_REV_5762)
16180 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16182 if (tg3_flag(tp, 57765_PLUS) &&
16183 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16184 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16186 if (!tg3_flag(tp, 5705_PLUS) ||
16187 tg3_flag(tp, 5780_CLASS) ||
16188 tg3_flag(tp, USE_JUMBO_BDFLAG))
16189 tg3_flag_set(tp, JUMBO_CAPABLE);
16191 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16194 if (pci_is_pcie(tp->pdev)) {
16197 tg3_flag_set(tp, PCI_EXPRESS);
16199 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16200 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16201 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16202 tg3_flag_clear(tp, HW_TSO_2);
16203 tg3_flag_clear(tp, TSO_CAPABLE);
16205 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16206 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16207 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16208 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16209 tg3_flag_set(tp, CLKREQ_BUG);
16210 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16211 tg3_flag_set(tp, L1PLLPD_EN);
16213 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16214 /* BCM5785 devices are effectively PCIe devices, and should
16215 * follow PCIe codepaths, but do not have a PCIe capabilities
16218 tg3_flag_set(tp, PCI_EXPRESS);
16219 } else if (!tg3_flag(tp, 5705_PLUS) ||
16220 tg3_flag(tp, 5780_CLASS)) {
16221 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16222 if (!tp->pcix_cap) {
16223 dev_err(&tp->pdev->dev,
16224 "Cannot find PCI-X capability, aborting\n");
16228 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16229 tg3_flag_set(tp, PCIX_MODE);
16232 /* If we have an AMD 762 or VIA K8T800 chipset, write
16233 * reordering to the mailbox registers done by the host
16234 * controller can cause major troubles. We read back from
16235 * every mailbox register write to force the writes to be
16236 * posted to the chip in order.
16238 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16239 !tg3_flag(tp, PCI_EXPRESS))
16240 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16242 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16243 &tp->pci_cacheline_sz);
16244 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16245 &tp->pci_lat_timer);
16246 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16247 tp->pci_lat_timer < 64) {
16248 tp->pci_lat_timer = 64;
16249 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16250 tp->pci_lat_timer);
16253 /* Important! -- It is critical that the PCI-X hw workaround
16254 * situation is decided before the first MMIO register access.
16256 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16257 /* 5700 BX chips need to have their TX producer index
16258 * mailboxes written twice to workaround a bug.
16260 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16262 /* If we are in PCI-X mode, enable register write workaround.
16264 * The workaround is to use indirect register accesses
16265 * for all chip writes not to mailbox registers.
16267 if (tg3_flag(tp, PCIX_MODE)) {
16270 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16272 /* The chip can have it's power management PCI config
16273 * space registers clobbered due to this bug.
16274 * So explicitly force the chip into D0 here.
16276 pci_read_config_dword(tp->pdev,
16277 tp->pdev->pm_cap + PCI_PM_CTRL,
16279 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16280 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16281 pci_write_config_dword(tp->pdev,
16282 tp->pdev->pm_cap + PCI_PM_CTRL,
16285 /* Also, force SERR#/PERR# in PCI command. */
16286 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16287 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16288 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16292 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16293 tg3_flag_set(tp, PCI_HIGH_SPEED);
16294 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16295 tg3_flag_set(tp, PCI_32BIT);
16297 /* Chip-specific fixup from Broadcom driver */
16298 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16299 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16300 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16301 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16304 /* Default fast path register access methods */
16305 tp->read32 = tg3_read32;
16306 tp->write32 = tg3_write32;
16307 tp->read32_mbox = tg3_read32;
16308 tp->write32_mbox = tg3_write32;
16309 tp->write32_tx_mbox = tg3_write32;
16310 tp->write32_rx_mbox = tg3_write32;
16312 /* Various workaround register access methods */
16313 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16314 tp->write32 = tg3_write_indirect_reg32;
16315 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16316 (tg3_flag(tp, PCI_EXPRESS) &&
16317 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16319 * Back to back register writes can cause problems on these
16320 * chips, the workaround is to read back all reg writes
16321 * except those to mailbox regs.
16323 * See tg3_write_indirect_reg32().
16325 tp->write32 = tg3_write_flush_reg32;
16328 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16329 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16330 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16331 tp->write32_rx_mbox = tg3_write_flush_reg32;
16334 if (tg3_flag(tp, ICH_WORKAROUND)) {
16335 tp->read32 = tg3_read_indirect_reg32;
16336 tp->write32 = tg3_write_indirect_reg32;
16337 tp->read32_mbox = tg3_read_indirect_mbox;
16338 tp->write32_mbox = tg3_write_indirect_mbox;
16339 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16340 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16345 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16346 pci_cmd &= ~PCI_COMMAND_MEMORY;
16347 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16349 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16350 tp->read32_mbox = tg3_read32_mbox_5906;
16351 tp->write32_mbox = tg3_write32_mbox_5906;
16352 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16353 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16356 if (tp->write32 == tg3_write_indirect_reg32 ||
16357 (tg3_flag(tp, PCIX_MODE) &&
16358 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16359 tg3_asic_rev(tp) == ASIC_REV_5701)))
16360 tg3_flag_set(tp, SRAM_USE_CONFIG);
16362 /* The memory arbiter has to be enabled in order for SRAM accesses
16363 * to succeed. Normally on powerup the tg3 chip firmware will make
16364 * sure it is enabled, but other entities such as system netboot
16365 * code might disable it.
16367 val = tr32(MEMARB_MODE);
16368 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16370 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16371 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16372 tg3_flag(tp, 5780_CLASS)) {
16373 if (tg3_flag(tp, PCIX_MODE)) {
16374 pci_read_config_dword(tp->pdev,
16375 tp->pcix_cap + PCI_X_STATUS,
16377 tp->pci_fn = val & 0x7;
16379 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16380 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16381 tg3_asic_rev(tp) == ASIC_REV_5720) {
16382 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16383 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16384 val = tr32(TG3_CPMU_STATUS);
16386 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16387 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16389 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16390 TG3_CPMU_STATUS_FSHFT_5719;
16393 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16394 tp->write32_tx_mbox = tg3_write_flush_reg32;
16395 tp->write32_rx_mbox = tg3_write_flush_reg32;
16398 /* Get eeprom hw config before calling tg3_set_power_state().
16399 * In particular, the TG3_FLAG_IS_NIC flag must be
16400 * determined before calling tg3_set_power_state() so that
16401 * we know whether or not to switch out of Vaux power.
16402 * When the flag is set, it means that GPIO1 is used for eeprom
16403 * write protect and also implies that it is a LOM where GPIOs
16404 * are not used to switch power.
16406 tg3_get_eeprom_hw_cfg(tp);
16408 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16409 tg3_flag_clear(tp, TSO_CAPABLE);
16410 tg3_flag_clear(tp, TSO_BUG);
16411 tp->fw_needed = NULL;
16414 if (tg3_flag(tp, ENABLE_APE)) {
16415 /* Allow reads and writes to the
16416 * APE register and memory space.
16418 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16419 PCISTATE_ALLOW_APE_SHMEM_WR |
16420 PCISTATE_ALLOW_APE_PSPACE_WR;
16421 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16424 tg3_ape_lock_init(tp);
16427 /* Set up tp->grc_local_ctrl before calling
16428 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16429 * will bring 5700's external PHY out of reset.
16430 * It is also used as eeprom write protect on LOMs.
16432 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16433 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16434 tg3_flag(tp, EEPROM_WRITE_PROT))
16435 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16436 GRC_LCLCTRL_GPIO_OUTPUT1);
16437 /* Unused GPIO3 must be driven as output on 5752 because there
16438 * are no pull-up resistors on unused GPIO pins.
16440 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16441 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16443 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16444 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16445 tg3_flag(tp, 57765_CLASS))
16446 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16448 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16449 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16450 /* Turn off the debug UART. */
16451 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16452 if (tg3_flag(tp, IS_NIC))
16453 /* Keep VMain power. */
16454 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16455 GRC_LCLCTRL_GPIO_OUTPUT0;
16458 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16459 tp->grc_local_ctrl |=
16460 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16462 /* Switch out of Vaux if it is a NIC */
16463 tg3_pwrsrc_switch_to_vmain(tp);
16465 /* Derive initial jumbo mode from MTU assigned in
16466 * ether_setup() via the alloc_etherdev() call
16468 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16469 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16471 /* Determine WakeOnLan speed to use. */
16472 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16473 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16474 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16475 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16476 tg3_flag_clear(tp, WOL_SPEED_100MB);
16478 tg3_flag_set(tp, WOL_SPEED_100MB);
16481 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16482 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16484 /* A few boards don't want Ethernet@WireSpeed phy feature */
16485 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16486 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16487 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16488 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16489 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16490 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16491 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16493 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16494 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16495 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16496 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16497 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16499 if (tg3_flag(tp, 5705_PLUS) &&
16500 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16501 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16502 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16503 !tg3_flag(tp, 57765_PLUS)) {
16504 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16505 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16506 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16507 tg3_asic_rev(tp) == ASIC_REV_5761) {
16508 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16509 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16510 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16511 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16512 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16514 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16517 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16518 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16519 tp->phy_otp = tg3_read_otp_phycfg(tp);
16520 if (tp->phy_otp == 0)
16521 tp->phy_otp = TG3_OTP_DEFAULT;
16524 if (tg3_flag(tp, CPMU_PRESENT))
16525 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16527 tp->mi_mode = MAC_MI_MODE_BASE;
16529 tp->coalesce_mode = 0;
16530 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16531 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16532 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16534 /* Set these bits to enable statistics workaround. */
16535 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16536 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16537 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16538 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16539 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16542 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16543 tg3_asic_rev(tp) == ASIC_REV_57780)
16544 tg3_flag_set(tp, USE_PHYLIB);
16546 err = tg3_mdio_init(tp);
16550 /* Initialize data/descriptor byte/word swapping. */
16551 val = tr32(GRC_MODE);
16552 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16553 tg3_asic_rev(tp) == ASIC_REV_5762)
16554 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16555 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16556 GRC_MODE_B2HRX_ENABLE |
16557 GRC_MODE_HTX2B_ENABLE |
16558 GRC_MODE_HOST_STACKUP);
16560 val &= GRC_MODE_HOST_STACKUP;
16562 tw32(GRC_MODE, val | tp->grc_mode);
16564 tg3_switch_clocks(tp);
16566 /* Clear this out for sanity. */
16567 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16569 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16571 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16572 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16573 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16574 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16575 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16576 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16577 void __iomem *sram_base;
16579 /* Write some dummy words into the SRAM status block
16580 * area, see if it reads back correctly. If the return
16581 * value is bad, force enable the PCIX workaround.
16583 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16585 writel(0x00000000, sram_base);
16586 writel(0x00000000, sram_base + 4);
16587 writel(0xffffffff, sram_base + 4);
16588 if (readl(sram_base) != 0x00000000)
16589 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16594 tg3_nvram_init(tp);
16596 /* If the device has an NVRAM, no need to load patch firmware */
16597 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16598 !tg3_flag(tp, NO_NVRAM))
16599 tp->fw_needed = NULL;
16601 grc_misc_cfg = tr32(GRC_MISC_CFG);
16602 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16604 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16605 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16606 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16607 tg3_flag_set(tp, IS_5788);
16609 if (!tg3_flag(tp, IS_5788) &&
16610 tg3_asic_rev(tp) != ASIC_REV_5700)
16611 tg3_flag_set(tp, TAGGED_STATUS);
16612 if (tg3_flag(tp, TAGGED_STATUS)) {
16613 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16614 HOSTCC_MODE_CLRTICK_TXBD);
16616 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16617 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16618 tp->misc_host_ctrl);
16621 /* Preserve the APE MAC_MODE bits */
16622 if (tg3_flag(tp, ENABLE_APE))
16623 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16627 if (tg3_10_100_only_device(tp, ent))
16628 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16630 err = tg3_phy_probe(tp);
16632 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16633 /* ... but do not return immediately ... */
16638 tg3_read_fw_ver(tp);
16640 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16641 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16643 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16644 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16646 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16649 /* 5700 {AX,BX} chips have a broken status block link
16650 * change bit implementation, so we must use the
16651 * status register in those cases.
16653 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16654 tg3_flag_set(tp, USE_LINKCHG_REG);
16656 tg3_flag_clear(tp, USE_LINKCHG_REG);
16658 /* The led_ctrl is set during tg3_phy_probe, here we might
16659 * have to force the link status polling mechanism based
16660 * upon subsystem IDs.
16662 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16663 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16664 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16665 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16666 tg3_flag_set(tp, USE_LINKCHG_REG);
16669 /* For all SERDES we poll the MAC status register. */
16670 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16671 tg3_flag_set(tp, POLL_SERDES);
16673 tg3_flag_clear(tp, POLL_SERDES);
16675 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16676 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16677 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16678 tg3_flag(tp, PCIX_MODE)) {
16679 tp->rx_offset = NET_SKB_PAD;
16680 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16681 tp->rx_copy_thresh = ~(u16)0;
16685 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16686 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16687 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16689 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16691 /* Increment the rx prod index on the rx std ring by at most
16692 * 8 for these chips to workaround hw errata.
16694 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16695 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16696 tg3_asic_rev(tp) == ASIC_REV_5755)
16697 tp->rx_std_max_post = 8;
16699 if (tg3_flag(tp, ASPM_WORKAROUND))
16700 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16701 PCIE_PWR_MGMT_L1_THRESH_MSK;
16706 #ifdef CONFIG_SPARC
16707 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16709 struct net_device *dev = tp->dev;
16710 struct pci_dev *pdev = tp->pdev;
16711 struct device_node *dp = pci_device_to_OF_node(pdev);
16712 const unsigned char *addr;
16715 addr = of_get_property(dp, "local-mac-address", &len);
16716 if (addr && len == ETH_ALEN) {
16717 memcpy(dev->dev_addr, addr, ETH_ALEN);
16723 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16725 struct net_device *dev = tp->dev;
16727 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16732 static int tg3_get_device_address(struct tg3 *tp)
16734 struct net_device *dev = tp->dev;
16735 u32 hi, lo, mac_offset;
16739 #ifdef CONFIG_SPARC
16740 if (!tg3_get_macaddr_sparc(tp))
16744 if (tg3_flag(tp, IS_SSB_CORE)) {
16745 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16746 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16751 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16752 tg3_flag(tp, 5780_CLASS)) {
16753 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16755 if (tg3_nvram_lock(tp))
16756 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16758 tg3_nvram_unlock(tp);
16759 } else if (tg3_flag(tp, 5717_PLUS)) {
16760 if (tp->pci_fn & 1)
16762 if (tp->pci_fn > 1)
16763 mac_offset += 0x18c;
16764 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16767 /* First try to get it from MAC address mailbox. */
16768 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16769 if ((hi >> 16) == 0x484b) {
16770 dev->dev_addr[0] = (hi >> 8) & 0xff;
16771 dev->dev_addr[1] = (hi >> 0) & 0xff;
16773 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16774 dev->dev_addr[2] = (lo >> 24) & 0xff;
16775 dev->dev_addr[3] = (lo >> 16) & 0xff;
16776 dev->dev_addr[4] = (lo >> 8) & 0xff;
16777 dev->dev_addr[5] = (lo >> 0) & 0xff;
16779 /* Some old bootcode may report a 0 MAC address in SRAM */
16780 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16783 /* Next, try NVRAM. */
16784 if (!tg3_flag(tp, NO_NVRAM) &&
16785 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16786 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16787 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16788 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16790 /* Finally just fetch it out of the MAC control regs. */
16792 hi = tr32(MAC_ADDR_0_HIGH);
16793 lo = tr32(MAC_ADDR_0_LOW);
16795 dev->dev_addr[5] = lo & 0xff;
16796 dev->dev_addr[4] = (lo >> 8) & 0xff;
16797 dev->dev_addr[3] = (lo >> 16) & 0xff;
16798 dev->dev_addr[2] = (lo >> 24) & 0xff;
16799 dev->dev_addr[1] = hi & 0xff;
16800 dev->dev_addr[0] = (hi >> 8) & 0xff;
16804 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16805 #ifdef CONFIG_SPARC
16806 if (!tg3_get_default_macaddr_sparc(tp))
16814 #define BOUNDARY_SINGLE_CACHELINE 1
16815 #define BOUNDARY_MULTI_CACHELINE 2
16817 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16819 int cacheline_size;
16823 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
16825 cacheline_size = 1024;
16827 cacheline_size = (int) byte * 4;
16829 /* On 5703 and later chips, the boundary bits have no
16832 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16833 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16834 !tg3_flag(tp, PCI_EXPRESS))
16837 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16838 goal = BOUNDARY_MULTI_CACHELINE;
16840 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16841 goal = BOUNDARY_SINGLE_CACHELINE;
16847 if (tg3_flag(tp, 57765_PLUS)) {
16848 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
16855 /* PCI controllers on most RISC systems tend to disconnect
16856 * when a device tries to burst across a cache-line boundary.
16857 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16859 * Unfortunately, for PCI-E there are only limited
16860 * write-side controls for this, and thus for reads
16861 * we will still get the disconnects. We'll also waste
16862 * these PCI cycles for both read and write for chips
16863 * other than 5700 and 5701 which do not implement the
16866 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
16867 switch (cacheline_size) {
16872 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16873 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
16874 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
16876 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16877 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16882 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
16883 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
16887 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
16888 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
16891 } else if (tg3_flag(tp, PCI_EXPRESS)) {
16892 switch (cacheline_size) {
16896 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16897 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16898 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
16904 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
16905 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
16909 switch (cacheline_size) {
16911 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16912 val |= (DMA_RWCTRL_READ_BNDRY_16 |
16913 DMA_RWCTRL_WRITE_BNDRY_16);
16918 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16919 val |= (DMA_RWCTRL_READ_BNDRY_32 |
16920 DMA_RWCTRL_WRITE_BNDRY_32);
16925 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16926 val |= (DMA_RWCTRL_READ_BNDRY_64 |
16927 DMA_RWCTRL_WRITE_BNDRY_64);
16932 if (goal == BOUNDARY_SINGLE_CACHELINE) {
16933 val |= (DMA_RWCTRL_READ_BNDRY_128 |
16934 DMA_RWCTRL_WRITE_BNDRY_128);
16939 val |= (DMA_RWCTRL_READ_BNDRY_256 |
16940 DMA_RWCTRL_WRITE_BNDRY_256);
16943 val |= (DMA_RWCTRL_READ_BNDRY_512 |
16944 DMA_RWCTRL_WRITE_BNDRY_512);
16948 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
16949 DMA_RWCTRL_WRITE_BNDRY_1024);
16958 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
16959 int size, bool to_device)
16961 struct tg3_internal_buffer_desc test_desc;
16962 u32 sram_dma_descs;
16965 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
16967 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
16968 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
16969 tw32(RDMAC_STATUS, 0);
16970 tw32(WDMAC_STATUS, 0);
16972 tw32(BUFMGR_MODE, 0);
16973 tw32(FTQ_RESET, 0);
16975 test_desc.addr_hi = ((u64) buf_dma) >> 32;
16976 test_desc.addr_lo = buf_dma & 0xffffffff;
16977 test_desc.nic_mbuf = 0x00002100;
16978 test_desc.len = size;
16981 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16982 * the *second* time the tg3 driver was getting loaded after an
16985 * Broadcom tells me:
16986 * ...the DMA engine is connected to the GRC block and a DMA
16987 * reset may affect the GRC block in some unpredictable way...
16988 * The behavior of resets to individual blocks has not been tested.
16990 * Broadcom noted the GRC reset will also reset all sub-components.
16993 test_desc.cqid_sqid = (13 << 8) | 2;
16995 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
16998 test_desc.cqid_sqid = (16 << 8) | 7;
17000 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17003 test_desc.flags = 0x00000005;
17005 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17008 val = *(((u32 *)&test_desc) + i);
17009 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17010 sram_dma_descs + (i * sizeof(u32)));
17011 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17013 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17016 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17018 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17021 for (i = 0; i < 40; i++) {
17025 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17027 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17028 if ((val & 0xffff) == sram_dma_descs) {
17039 #define TEST_BUFFER_SIZE 0x2000
17041 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets) = {
17042 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17046 static int tg3_test_dma(struct tg3 *tp)
17048 dma_addr_t buf_dma;
17049 u32 *buf, saved_dma_rwctrl;
17052 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17053 &buf_dma, GFP_KERNEL);
17059 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17060 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17062 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17064 if (tg3_flag(tp, 57765_PLUS))
17067 if (tg3_flag(tp, PCI_EXPRESS)) {
17068 /* DMA read watermark not used on PCIE */
17069 tp->dma_rwctrl |= 0x00180000;
17070 } else if (!tg3_flag(tp, PCIX_MODE)) {
17071 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17072 tg3_asic_rev(tp) == ASIC_REV_5750)
17073 tp->dma_rwctrl |= 0x003f0000;
17075 tp->dma_rwctrl |= 0x003f000f;
17077 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17078 tg3_asic_rev(tp) == ASIC_REV_5704) {
17079 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17080 u32 read_water = 0x7;
17082 /* If the 5704 is behind the EPB bridge, we can
17083 * do the less restrictive ONE_DMA workaround for
17084 * better performance.
17086 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17087 tg3_asic_rev(tp) == ASIC_REV_5704)
17088 tp->dma_rwctrl |= 0x8000;
17089 else if (ccval == 0x6 || ccval == 0x7)
17090 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17092 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17094 /* Set bit 23 to enable PCIX hw bug fix */
17096 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17097 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17099 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17100 /* 5780 always in PCIX mode */
17101 tp->dma_rwctrl |= 0x00144000;
17102 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17103 /* 5714 always in PCIX mode */
17104 tp->dma_rwctrl |= 0x00148000;
17106 tp->dma_rwctrl |= 0x001b000f;
17109 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17110 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17112 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17113 tg3_asic_rev(tp) == ASIC_REV_5704)
17114 tp->dma_rwctrl &= 0xfffffff0;
17116 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17117 tg3_asic_rev(tp) == ASIC_REV_5701) {
17118 /* Remove this if it causes problems for some boards. */
17119 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17121 /* On 5700/5701 chips, we need to set this bit.
17122 * Otherwise the chip will issue cacheline transactions
17123 * to streamable DMA memory with not all the byte
17124 * enables turned on. This is an error on several
17125 * RISC PCI controllers, in particular sparc64.
17127 * On 5703/5704 chips, this bit has been reassigned
17128 * a different meaning. In particular, it is used
17129 * on those chips to enable a PCI-X workaround.
17131 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17134 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17137 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17138 tg3_asic_rev(tp) != ASIC_REV_5701)
17141 /* It is best to perform DMA test with maximum write burst size
17142 * to expose the 5700/5701 write DMA bug.
17144 saved_dma_rwctrl = tp->dma_rwctrl;
17145 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17146 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17151 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17154 /* Send the buffer to the chip. */
17155 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17157 dev_err(&tp->pdev->dev,
17158 "%s: Buffer write failed. err = %d\n",
17163 /* Now read it back. */
17164 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17166 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17167 "err = %d\n", __func__, ret);
17172 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17176 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17177 DMA_RWCTRL_WRITE_BNDRY_16) {
17178 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17179 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17180 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17183 dev_err(&tp->pdev->dev,
17184 "%s: Buffer corrupted on read back! "
17185 "(%d != %d)\n", __func__, p[i], i);
17191 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17197 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17198 DMA_RWCTRL_WRITE_BNDRY_16) {
17199 /* DMA test passed without adjusting DMA boundary,
17200 * now look for chipsets that are known to expose the
17201 * DMA bug without failing the test.
17203 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17204 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17205 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17207 /* Safe to use the calculated DMA boundary. */
17208 tp->dma_rwctrl = saved_dma_rwctrl;
17211 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17215 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17220 static void tg3_init_bufmgr_config(struct tg3 *tp)
17222 if (tg3_flag(tp, 57765_PLUS)) {
17223 tp->bufmgr_config.mbuf_read_dma_low_water =
17224 DEFAULT_MB_RDMA_LOW_WATER_5705;
17225 tp->bufmgr_config.mbuf_mac_rx_low_water =
17226 DEFAULT_MB_MACRX_LOW_WATER_57765;
17227 tp->bufmgr_config.mbuf_high_water =
17228 DEFAULT_MB_HIGH_WATER_57765;
17230 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17231 DEFAULT_MB_RDMA_LOW_WATER_5705;
17232 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17233 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17234 tp->bufmgr_config.mbuf_high_water_jumbo =
17235 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17236 } else if (tg3_flag(tp, 5705_PLUS)) {
17237 tp->bufmgr_config.mbuf_read_dma_low_water =
17238 DEFAULT_MB_RDMA_LOW_WATER_5705;
17239 tp->bufmgr_config.mbuf_mac_rx_low_water =
17240 DEFAULT_MB_MACRX_LOW_WATER_5705;
17241 tp->bufmgr_config.mbuf_high_water =
17242 DEFAULT_MB_HIGH_WATER_5705;
17243 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17244 tp->bufmgr_config.mbuf_mac_rx_low_water =
17245 DEFAULT_MB_MACRX_LOW_WATER_5906;
17246 tp->bufmgr_config.mbuf_high_water =
17247 DEFAULT_MB_HIGH_WATER_5906;
17250 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17251 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17252 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17253 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17254 tp->bufmgr_config.mbuf_high_water_jumbo =
17255 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17257 tp->bufmgr_config.mbuf_read_dma_low_water =
17258 DEFAULT_MB_RDMA_LOW_WATER;
17259 tp->bufmgr_config.mbuf_mac_rx_low_water =
17260 DEFAULT_MB_MACRX_LOW_WATER;
17261 tp->bufmgr_config.mbuf_high_water =
17262 DEFAULT_MB_HIGH_WATER;
17264 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17265 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17266 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17267 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17268 tp->bufmgr_config.mbuf_high_water_jumbo =
17269 DEFAULT_MB_HIGH_WATER_JUMBO;
17272 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17273 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17276 static char *tg3_phy_string(struct tg3 *tp)
17278 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17279 case TG3_PHY_ID_BCM5400: return "5400";
17280 case TG3_PHY_ID_BCM5401: return "5401";
17281 case TG3_PHY_ID_BCM5411: return "5411";
17282 case TG3_PHY_ID_BCM5701: return "5701";
17283 case TG3_PHY_ID_BCM5703: return "5703";
17284 case TG3_PHY_ID_BCM5704: return "5704";
17285 case TG3_PHY_ID_BCM5705: return "5705";
17286 case TG3_PHY_ID_BCM5750: return "5750";
17287 case TG3_PHY_ID_BCM5752: return "5752";
17288 case TG3_PHY_ID_BCM5714: return "5714";
17289 case TG3_PHY_ID_BCM5780: return "5780";
17290 case TG3_PHY_ID_BCM5755: return "5755";
17291 case TG3_PHY_ID_BCM5787: return "5787";
17292 case TG3_PHY_ID_BCM5784: return "5784";
17293 case TG3_PHY_ID_BCM5756: return "5722/5756";
17294 case TG3_PHY_ID_BCM5906: return "5906";
17295 case TG3_PHY_ID_BCM5761: return "5761";
17296 case TG3_PHY_ID_BCM5718C: return "5718C";
17297 case TG3_PHY_ID_BCM5718S: return "5718S";
17298 case TG3_PHY_ID_BCM57765: return "57765";
17299 case TG3_PHY_ID_BCM5719C: return "5719C";
17300 case TG3_PHY_ID_BCM5720C: return "5720C";
17301 case TG3_PHY_ID_BCM5762: return "5762C";
17302 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17303 case 0: return "serdes";
17304 default: return "unknown";
17308 static char *tg3_bus_string(struct tg3 *tp, char *str)
17310 if (tg3_flag(tp, PCI_EXPRESS)) {
17311 strcpy(str, "PCI Express");
17313 } else if (tg3_flag(tp, PCIX_MODE)) {
17314 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17316 strcpy(str, "PCIX:");
17318 if ((clock_ctrl == 7) ||
17319 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17320 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17321 strcat(str, "133MHz");
17322 else if (clock_ctrl == 0)
17323 strcat(str, "33MHz");
17324 else if (clock_ctrl == 2)
17325 strcat(str, "50MHz");
17326 else if (clock_ctrl == 4)
17327 strcat(str, "66MHz");
17328 else if (clock_ctrl == 6)
17329 strcat(str, "100MHz");
17331 strcpy(str, "PCI:");
17332 if (tg3_flag(tp, PCI_HIGH_SPEED))
17333 strcat(str, "66MHz");
17335 strcat(str, "33MHz");
17337 if (tg3_flag(tp, PCI_32BIT))
17338 strcat(str, ":32-bit");
17340 strcat(str, ":64-bit");
17344 static void tg3_init_coal(struct tg3 *tp)
17346 struct ethtool_coalesce *ec = &tp->coal;
17348 memset(ec, 0, sizeof(*ec));
17349 ec->cmd = ETHTOOL_GCOALESCE;
17350 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17351 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17352 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17353 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17354 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17355 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17356 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17357 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17358 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17360 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17361 HOSTCC_MODE_CLRTICK_TXBD)) {
17362 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17363 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17364 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17365 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17368 if (tg3_flag(tp, 5705_PLUS)) {
17369 ec->rx_coalesce_usecs_irq = 0;
17370 ec->tx_coalesce_usecs_irq = 0;
17371 ec->stats_block_coalesce_usecs = 0;
17375 static int tg3_init_one(struct pci_dev *pdev,
17376 const struct pci_device_id *ent)
17378 struct net_device *dev;
17381 u32 sndmbx, rcvmbx, intmbx;
17383 u64 dma_mask, persist_dma_mask;
17384 netdev_features_t features = 0;
17386 printk_once(KERN_INFO "%s\n", version);
17388 err = pci_enable_device(pdev);
17390 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17394 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17396 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17397 goto err_out_disable_pdev;
17400 pci_set_master(pdev);
17402 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17405 goto err_out_free_res;
17408 SET_NETDEV_DEV(dev, &pdev->dev);
17410 tp = netdev_priv(dev);
17413 tp->rx_mode = TG3_DEF_RX_MODE;
17414 tp->tx_mode = TG3_DEF_TX_MODE;
17418 tp->msg_enable = tg3_debug;
17420 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17422 if (pdev_is_ssb_gige_core(pdev)) {
17423 tg3_flag_set(tp, IS_SSB_CORE);
17424 if (ssb_gige_must_flush_posted_writes(pdev))
17425 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17426 if (ssb_gige_one_dma_at_once(pdev))
17427 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17428 if (ssb_gige_have_roboswitch(pdev)) {
17429 tg3_flag_set(tp, USE_PHYLIB);
17430 tg3_flag_set(tp, ROBOSWITCH);
17432 if (ssb_gige_is_rgmii(pdev))
17433 tg3_flag_set(tp, RGMII_MODE);
17436 /* The word/byte swap controls here control register access byte
17437 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17440 tp->misc_host_ctrl =
17441 MISC_HOST_CTRL_MASK_PCI_INT |
17442 MISC_HOST_CTRL_WORD_SWAP |
17443 MISC_HOST_CTRL_INDIR_ACCESS |
17444 MISC_HOST_CTRL_PCISTATE_RW;
17446 /* The NONFRM (non-frame) byte/word swap controls take effect
17447 * on descriptor entries, anything which isn't packet data.
17449 * The StrongARM chips on the board (one for tx, one for rx)
17450 * are running in big-endian mode.
17452 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17453 GRC_MODE_WSWAP_NONFRM_DATA);
17454 #ifdef __BIG_ENDIAN
17455 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17457 spin_lock_init(&tp->lock);
17458 spin_lock_init(&tp->indirect_lock);
17459 INIT_WORK(&tp->reset_task, tg3_reset_task);
17461 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17463 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17465 goto err_out_free_dev;
17468 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17469 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17470 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17471 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17472 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17473 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17474 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17475 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17476 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17477 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17478 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17479 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17480 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17481 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17482 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17483 tg3_flag_set(tp, ENABLE_APE);
17484 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17485 if (!tp->aperegs) {
17486 dev_err(&pdev->dev,
17487 "Cannot map APE registers, aborting\n");
17489 goto err_out_iounmap;
17493 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17494 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17496 dev->ethtool_ops = &tg3_ethtool_ops;
17497 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17498 dev->netdev_ops = &tg3_netdev_ops;
17499 dev->irq = pdev->irq;
17501 err = tg3_get_invariants(tp, ent);
17503 dev_err(&pdev->dev,
17504 "Problem fetching invariants of chip, aborting\n");
17505 goto err_out_apeunmap;
17508 /* The EPB bridge inside 5714, 5715, and 5780 and any
17509 * device behind the EPB cannot support DMA addresses > 40-bit.
17510 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17511 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17512 * do DMA address check in tg3_start_xmit().
17514 if (tg3_flag(tp, IS_5788))
17515 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17516 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17517 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17518 #ifdef CONFIG_HIGHMEM
17519 dma_mask = DMA_BIT_MASK(64);
17522 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17524 /* Configure DMA attributes. */
17525 if (dma_mask > DMA_BIT_MASK(32)) {
17526 err = pci_set_dma_mask(pdev, dma_mask);
17528 features |= NETIF_F_HIGHDMA;
17529 err = pci_set_consistent_dma_mask(pdev,
17532 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17533 "DMA for consistent allocations\n");
17534 goto err_out_apeunmap;
17538 if (err || dma_mask == DMA_BIT_MASK(32)) {
17539 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17541 dev_err(&pdev->dev,
17542 "No usable DMA configuration, aborting\n");
17543 goto err_out_apeunmap;
17547 tg3_init_bufmgr_config(tp);
17549 features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
17551 /* 5700 B0 chips do not support checksumming correctly due
17552 * to hardware bugs.
17554 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17555 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17557 if (tg3_flag(tp, 5755_PLUS))
17558 features |= NETIF_F_IPV6_CSUM;
17561 /* TSO is on by default on chips that support hardware TSO.
17562 * Firmware TSO on older chips gives lower performance, so it
17563 * is off by default, but can be enabled using ethtool.
17565 if ((tg3_flag(tp, HW_TSO_1) ||
17566 tg3_flag(tp, HW_TSO_2) ||
17567 tg3_flag(tp, HW_TSO_3)) &&
17568 (features & NETIF_F_IP_CSUM))
17569 features |= NETIF_F_TSO;
17570 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17571 if (features & NETIF_F_IPV6_CSUM)
17572 features |= NETIF_F_TSO6;
17573 if (tg3_flag(tp, HW_TSO_3) ||
17574 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17575 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17576 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17577 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17578 tg3_asic_rev(tp) == ASIC_REV_57780)
17579 features |= NETIF_F_TSO_ECN;
17582 dev->features |= features;
17583 dev->vlan_features |= features;
17586 * Add loopback capability only for a subset of devices that support
17587 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17588 * loopback for the remaining devices.
17590 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17591 !tg3_flag(tp, CPMU_PRESENT))
17592 /* Add the loopback capability */
17593 features |= NETIF_F_LOOPBACK;
17595 dev->hw_features |= features;
17597 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17598 !tg3_flag(tp, TSO_CAPABLE) &&
17599 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17600 tg3_flag_set(tp, MAX_RXPEND_64);
17601 tp->rx_pending = 63;
17604 err = tg3_get_device_address(tp);
17606 dev_err(&pdev->dev,
17607 "Could not obtain valid ethernet address, aborting\n");
17608 goto err_out_apeunmap;
17612 * Reset chip in case UNDI or EFI driver did not shutdown
17613 * DMA self test will enable WDMAC and we'll see (spurious)
17614 * pending DMA on the PCI bus at that point.
17616 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17617 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17618 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17619 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17622 err = tg3_test_dma(tp);
17624 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17625 goto err_out_apeunmap;
17628 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17629 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17630 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17631 for (i = 0; i < tp->irq_max; i++) {
17632 struct tg3_napi *tnapi = &tp->napi[i];
17635 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17637 tnapi->int_mbox = intmbx;
17643 tnapi->consmbox = rcvmbx;
17644 tnapi->prodmbox = sndmbx;
17647 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17649 tnapi->coal_now = HOSTCC_MODE_NOW;
17651 if (!tg3_flag(tp, SUPPORT_MSIX))
17655 * If we support MSIX, we'll be using RSS. If we're using
17656 * RSS, the first vector only handles link interrupts and the
17657 * remaining vectors handle rx and tx interrupts. Reuse the
17658 * mailbox values for the next iteration. The values we setup
17659 * above are still useful for the single vectored mode.
17674 pci_set_drvdata(pdev, dev);
17676 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17677 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17678 tg3_asic_rev(tp) == ASIC_REV_5762)
17679 tg3_flag_set(tp, PTP_CAPABLE);
17681 tg3_timer_init(tp);
17683 tg3_carrier_off(tp);
17685 err = register_netdev(dev);
17687 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17688 goto err_out_apeunmap;
17691 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17692 tp->board_part_number,
17693 tg3_chip_rev_id(tp),
17694 tg3_bus_string(tp, str),
17697 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17698 struct phy_device *phydev;
17699 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17701 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17702 phydev->drv->name, dev_name(&phydev->dev));
17706 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17707 ethtype = "10/100Base-TX";
17708 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17709 ethtype = "1000Base-SX";
17711 ethtype = "10/100/1000Base-T";
17713 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17714 "(WireSpeed[%d], EEE[%d])\n",
17715 tg3_phy_string(tp), ethtype,
17716 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17717 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17720 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17721 (dev->features & NETIF_F_RXCSUM) != 0,
17722 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17723 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17724 tg3_flag(tp, ENABLE_ASF) != 0,
17725 tg3_flag(tp, TSO_CAPABLE) != 0);
17726 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17728 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17729 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17731 pci_save_state(pdev);
17737 iounmap(tp->aperegs);
17738 tp->aperegs = NULL;
17751 pci_release_regions(pdev);
17753 err_out_disable_pdev:
17754 if (pci_is_enabled(pdev))
17755 pci_disable_device(pdev);
17759 static void tg3_remove_one(struct pci_dev *pdev)
17761 struct net_device *dev = pci_get_drvdata(pdev);
17764 struct tg3 *tp = netdev_priv(dev);
17766 release_firmware(tp->fw);
17768 tg3_reset_task_cancel(tp);
17770 if (tg3_flag(tp, USE_PHYLIB)) {
17775 unregister_netdev(dev);
17777 iounmap(tp->aperegs);
17778 tp->aperegs = NULL;
17785 pci_release_regions(pdev);
17786 pci_disable_device(pdev);
17790 #ifdef CONFIG_PM_SLEEP
17791 static int tg3_suspend(struct device *device)
17793 struct pci_dev *pdev = to_pci_dev(device);
17794 struct net_device *dev = pci_get_drvdata(pdev);
17795 struct tg3 *tp = netdev_priv(dev);
17800 if (!netif_running(dev))
17803 tg3_reset_task_cancel(tp);
17805 tg3_netif_stop(tp);
17807 tg3_timer_stop(tp);
17809 tg3_full_lock(tp, 1);
17810 tg3_disable_ints(tp);
17811 tg3_full_unlock(tp);
17813 netif_device_detach(dev);
17815 tg3_full_lock(tp, 0);
17816 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17817 tg3_flag_clear(tp, INIT_COMPLETE);
17818 tg3_full_unlock(tp);
17820 err = tg3_power_down_prepare(tp);
17824 tg3_full_lock(tp, 0);
17826 tg3_flag_set(tp, INIT_COMPLETE);
17827 err2 = tg3_restart_hw(tp, true);
17831 tg3_timer_start(tp);
17833 netif_device_attach(dev);
17834 tg3_netif_start(tp);
17837 tg3_full_unlock(tp);
17848 static int tg3_resume(struct device *device)
17850 struct pci_dev *pdev = to_pci_dev(device);
17851 struct net_device *dev = pci_get_drvdata(pdev);
17852 struct tg3 *tp = netdev_priv(dev);
17857 if (!netif_running(dev))
17860 netif_device_attach(dev);
17862 tg3_full_lock(tp, 0);
17864 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
17866 tg3_flag_set(tp, INIT_COMPLETE);
17867 err = tg3_restart_hw(tp,
17868 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
17872 tg3_timer_start(tp);
17874 tg3_netif_start(tp);
17877 tg3_full_unlock(tp);
17886 #endif /* CONFIG_PM_SLEEP */
17888 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
17890 static void tg3_shutdown(struct pci_dev *pdev)
17892 struct net_device *dev = pci_get_drvdata(pdev);
17893 struct tg3 *tp = netdev_priv(dev);
17896 netif_device_detach(dev);
17898 if (netif_running(dev))
17901 if (system_state == SYSTEM_POWER_OFF)
17902 tg3_power_down(tp);
17908 * tg3_io_error_detected - called when PCI error is detected
17909 * @pdev: Pointer to PCI device
17910 * @state: The current pci connection state
17912 * This function is called after a PCI bus error affecting
17913 * this device has been detected.
17915 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
17916 pci_channel_state_t state)
17918 struct net_device *netdev = pci_get_drvdata(pdev);
17919 struct tg3 *tp = netdev_priv(netdev);
17920 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
17922 netdev_info(netdev, "PCI I/O error detected\n");
17926 /* We probably don't have netdev yet */
17927 if (!netdev || !netif_running(netdev))
17932 tg3_netif_stop(tp);
17934 tg3_timer_stop(tp);
17936 /* Want to make sure that the reset task doesn't run */
17937 tg3_reset_task_cancel(tp);
17939 netif_device_detach(netdev);
17941 /* Clean up software state, even if MMIO is blocked */
17942 tg3_full_lock(tp, 0);
17943 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
17944 tg3_full_unlock(tp);
17947 if (state == pci_channel_io_perm_failure) {
17949 tg3_napi_enable(tp);
17952 err = PCI_ERS_RESULT_DISCONNECT;
17954 pci_disable_device(pdev);
17963 * tg3_io_slot_reset - called after the pci bus has been reset.
17964 * @pdev: Pointer to PCI device
17966 * Restart the card from scratch, as if from a cold-boot.
17967 * At this point, the card has exprienced a hard reset,
17968 * followed by fixups by BIOS, and has its config space
17969 * set up identically to what it was at cold boot.
17971 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
17973 struct net_device *netdev = pci_get_drvdata(pdev);
17974 struct tg3 *tp = netdev_priv(netdev);
17975 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
17980 if (pci_enable_device(pdev)) {
17981 dev_err(&pdev->dev,
17982 "Cannot re-enable PCI device after reset.\n");
17986 pci_set_master(pdev);
17987 pci_restore_state(pdev);
17988 pci_save_state(pdev);
17990 if (!netdev || !netif_running(netdev)) {
17991 rc = PCI_ERS_RESULT_RECOVERED;
17995 err = tg3_power_up(tp);
17999 rc = PCI_ERS_RESULT_RECOVERED;
18002 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18003 tg3_napi_enable(tp);
18012 * tg3_io_resume - called when traffic can start flowing again.
18013 * @pdev: Pointer to PCI device
18015 * This callback is called when the error recovery driver tells
18016 * us that its OK to resume normal operation.
18018 static void tg3_io_resume(struct pci_dev *pdev)
18020 struct net_device *netdev = pci_get_drvdata(pdev);
18021 struct tg3 *tp = netdev_priv(netdev);
18026 if (!netif_running(netdev))
18029 tg3_full_lock(tp, 0);
18030 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18031 tg3_flag_set(tp, INIT_COMPLETE);
18032 err = tg3_restart_hw(tp, true);
18034 tg3_full_unlock(tp);
18035 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18039 netif_device_attach(netdev);
18041 tg3_timer_start(tp);
18043 tg3_netif_start(tp);
18045 tg3_full_unlock(tp);
18053 static const struct pci_error_handlers tg3_err_handler = {
18054 .error_detected = tg3_io_error_detected,
18055 .slot_reset = tg3_io_slot_reset,
18056 .resume = tg3_io_resume
18059 static struct pci_driver tg3_driver = {
18060 .name = DRV_MODULE_NAME,
18061 .id_table = tg3_pci_tbl,
18062 .probe = tg3_init_one,
18063 .remove = tg3_remove_one,
18064 .err_handler = &tg3_err_handler,
18065 .driver.pm = &tg3_pm_ops,
18066 .shutdown = tg3_shutdown,
18069 module_pci_driver(tg3_driver);