drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014 Broadcom Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26
  27 #include "bcmgenet.h"
  28
  29 /* read a value from the MII */
  30 static int bcmgenet_mii_read(struct mii_bus *bus, int phy_id, int location)
  31 {
  32         int ret;
  33         struct net_device *dev = bus->priv;
  34         struct bcmgenet_priv *priv = netdev_priv(dev);
  35         u32 reg;
  36
  37         bcmgenet_umac_writel(priv, (MDIO_RD | (phy_id << MDIO_PMD_SHIFT) |
  38                              (location << MDIO_REG_SHIFT)), UMAC_MDIO_CMD);
  39         /* Start MDIO transaction*/
  40         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  41         reg |= MDIO_START_BUSY;
  42         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  43         wait_event_timeout(priv->wq,
  44                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
  45                            & MDIO_START_BUSY),
  46                            HZ / 100);
  47         ret = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  48
  49         if (ret & MDIO_READ_FAIL)
  50                 return -EIO;
  51
  52         return ret & 0xffff;
  53 }
  54
  55 /* write a value to the MII */
  56 static int bcmgenet_mii_write(struct mii_bus *bus, int phy_id,
  57                               int location, u16 val)
  58 {
  59         struct net_device *dev = bus->priv;
  60         struct bcmgenet_priv *priv = netdev_priv(dev);
  61         u32 reg;
  62
  63         bcmgenet_umac_writel(priv, (MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
  64                              (location << MDIO_REG_SHIFT) | (0xffff & val)),
  65                              UMAC_MDIO_CMD);
  66         reg = bcmgenet_umac_readl(priv, UMAC_MDIO_CMD);
  67         reg |= MDIO_START_BUSY;
  68         bcmgenet_umac_writel(priv, reg, UMAC_MDIO_CMD);
  69         wait_event_timeout(priv->wq,
  70                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD) &
  71                            MDIO_START_BUSY),
  72                            HZ / 100);
  73
  74         return 0;
  75 }
  76
  77 /* setup netdev link state when PHY link status change and
  78  * update UMAC and RGMII block when link up
  79  */
  80 static void bcmgenet_mii_setup(struct net_device *dev)
  81 {
  82         struct bcmgenet_priv *priv = netdev_priv(dev);
  83         struct phy_device *phydev = priv->phydev;
  84         u32 reg, cmd_bits = 0;
  85         unsigned int status_changed = 0;
  86
  87         if (priv->old_link != phydev->link) {
  88                 status_changed = 1;
  89                 priv->old_link = phydev->link;
  90         }
  91
  92         if (phydev->link) {
  93                 /* program UMAC and RGMII block based on established link
  94                  * speed, pause, and duplex.
  95                  * the speed set in umac->cmd tell RGMII block which clock
  96                  * 25MHz(100Mbps)/125MHz(1Gbps) to use for transmit.
  97                  * receive clock is provided by PHY.
  98                  */
  99                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 100                 reg &= ~OOB_DISABLE;
 101                 reg |= RGMII_LINK;
 102                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 103
 104                 /* speed */
 105                 if (phydev->speed == SPEED_1000)
 106                         cmd_bits = UMAC_SPEED_1000;
 107                 else if (phydev->speed == SPEED_100)
 108                         cmd_bits = UMAC_SPEED_100;
 109                 else
 110                         cmd_bits = UMAC_SPEED_10;
 111                 cmd_bits <<= CMD_SPEED_SHIFT;
 112
 113                 if (priv->old_duplex != phydev->duplex) {
 114                         status_changed = 1;
 115                         priv->old_duplex = phydev->duplex;
 116                 }
 117
 118                 /* duplex */
 119                 if (phydev->duplex != DUPLEX_FULL)
 120                         cmd_bits |= CMD_HD_EN;
 121
 122                 if (priv->old_pause != phydev->pause) {
 123                         status_changed = 1;
 124                         priv->old_pause = phydev->pause;
 125                 }
 126
 127                 /* pause capability */
 128                 if (!phydev->pause)
 129                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
 130         }
 131
 132         if (status_changed) {
 133                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
 134                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
 135                                CMD_HD_EN |
 136                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 137                 reg |= cmd_bits;
 138                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 139
 140                 phy_print_status(phydev);
 141         }
 142 }
 143
 144 void bcmgenet_mii_reset(struct net_device *dev)
 145 {
 146         struct bcmgenet_priv *priv = netdev_priv(dev);
 147
 148         if (priv->phydev) {
 149                 phy_init_hw(priv->phydev);
 150                 phy_start_aneg(priv->phydev);
 151         }
 152 }
 153
 154 static void bcmgenet_ephy_power_up(struct net_device *dev)
 155 {
 156         struct bcmgenet_priv *priv = netdev_priv(dev);
 157         u32 reg = 0;
 158
 159         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 160         if (!GENET_IS_V4(priv))
 161                 return;
 162
 163         reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 164         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 165         reg |= EXT_GPHY_RESET;
 166         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 167         mdelay(2);
 168
 169         reg &= ~EXT_GPHY_RESET;
 170         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 171         udelay(20);
 172 }
 173
 174 static void bcmgenet_internal_phy_setup(struct net_device *dev)
 175 {
 176         struct bcmgenet_priv *priv = netdev_priv(dev);
 177         u32 reg;
 178
 179         /* Power up EPHY */
 180         bcmgenet_ephy_power_up(dev);
 181         /* enable APD */
 182         reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 183         reg |= EXT_PWR_DN_EN_LD;
 184         bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 185         bcmgenet_mii_reset(dev);
 186 }
 187
 188 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 189 {
 190         u32 reg;
 191
 192         /* Speed settings are set in bcmgenet_mii_setup() */
 193         reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 194         reg |= LED_ACT_SOURCE_MAC;
 195         bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 196 }
 197
 198 int bcmgenet_mii_config(struct net_device *dev)
 199 {
 200         struct bcmgenet_priv *priv = netdev_priv(dev);
 201         struct phy_device *phydev = priv->phydev;
 202         struct device *kdev = &priv->pdev->dev;
 203         const char *phy_name = NULL;
 204         u32 id_mode_dis = 0;
 205         u32 port_ctrl;
 206         u32 reg;
 207
 208         priv->ext_phy = !phy_is_internal(priv->phydev) &&
 209                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 210
 211         if (phy_is_internal(priv->phydev))
 212                 priv->phy_interface = PHY_INTERFACE_MODE_NA;
 213
 214         switch (priv->phy_interface) {
 215         case PHY_INTERFACE_MODE_NA:
 216         case PHY_INTERFACE_MODE_MOCA:
 217                 /* Irrespective of the actually configured PHY speed (100 or
 218                  * 1000) GENETv4 only has an internal GPHY so we will just end
 219                  * up masking the Gigabit features from what we support, not
 220                  * switching to the EPHY
 221                  */
 222                 if (GENET_IS_V4(priv))
 223                         port_ctrl = PORT_MODE_INT_GPHY;
 224                 else
 225                         port_ctrl = PORT_MODE_INT_EPHY;
 226
 227                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 228
 229                 if (phy_is_internal(priv->phydev)) {
 230                         phy_name = "internal PHY";
 231                         bcmgenet_internal_phy_setup(dev);
 232                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 233                         phy_name = "MoCA";
 234                         bcmgenet_moca_phy_setup(priv);
 235                 }
 236                 break;
 237
 238         case PHY_INTERFACE_MODE_MII:
 239                 phy_name = "external MII";
 240                 phydev->supported &= PHY_BASIC_FEATURES;
 241                 bcmgenet_sys_writel(priv,
 242                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 243                 break;
 244
 245         case PHY_INTERFACE_MODE_REVMII:
 246                 phy_name = "external RvMII";
 247                 /* of_mdiobus_register took care of reading the 'max-speed'
 248                  * PHY property for us, effectively limiting the PHY supported
 249                  * capabilities, use that knowledge to also configure the
 250                  * Reverse MII interface correctly.
 251                  */
 252                 if ((priv->phydev->supported & PHY_BASIC_FEATURES) ==
 253                                 PHY_BASIC_FEATURES)
 254                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 255                 else
 256                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 257                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 258                 break;
 259
 260         case PHY_INTERFACE_MODE_RGMII:
 261                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 262                  *              (requires PCB or receiver-side delay)
 263                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 264                  *
 265                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 266                  */
 267                 id_mode_dis = BIT(16);
 268                 /* fall through */
 269         case PHY_INTERFACE_MODE_RGMII_TXID:
 270                 if (id_mode_dis)
 271                         phy_name = "external RGMII (no delay)";
 272                 else
 273                         phy_name = "external RGMII (TX delay)";
 274                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 275                 reg |= RGMII_MODE_EN | id_mode_dis;
 276                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 277                 bcmgenet_sys_writel(priv,
 278                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 279                 break;
 280         default:
 281                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 282                 return -EINVAL;
 283         }
 284
 285         dev_info(kdev, "configuring instance for %s\n", phy_name);
 286
 287         return 0;
 288 }
 289
 290 static int bcmgenet_mii_probe(struct net_device *dev)
 291 {
 292         struct bcmgenet_priv *priv = netdev_priv(dev);
 293         struct device_node *dn = priv->pdev->dev.of_node;
 294         struct phy_device *phydev;
 295         unsigned int phy_flags;
 296         int ret;
 297
 298         if (priv->phydev) {
 299                 pr_info("PHY already attached\n");
 300                 return 0;
 301         }
 302
 303         /* In the case of a fixed PHY, the DT node associated
 304          * to the PHY is the Ethernet MAC DT node.
 305          */
 306         if (of_phy_is_fixed_link(dn)) {
 307                 ret = of_phy_register_fixed_link(dn);
 308                 if (ret)
 309                         return ret;
 310
 311                 priv->phy_dn = dn;
 312         }
 313
 314         phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup, 0,
 315                                 priv->phy_interface);
 316         if (!phydev) {
 317                 pr_err("could not attach to PHY\n");
 318                 return -ENODEV;
 319         }
 320
 321         priv->old_link = -1;
 322         priv->old_duplex = -1;
 323         priv->old_pause = -1;
 324         priv->phydev = phydev;
 325
 326         /* Configure port multiplexer based on what the probed PHY device since
 327          * reading the 'max-speed' property determines the maximum supported
 328          * PHY speed which is needed for bcmgenet_mii_config() to configure
 329          * things appropriately.
 330          */
 331         ret = bcmgenet_mii_config(dev);
 332         if (ret) {
 333                 phy_disconnect(priv->phydev);
 334                 return ret;
 335         }
 336
 337         phy_flags = PHY_BRCM_100MBPS_WAR;
 338
 339         /* workarounds are only needed for 100Mpbs PHYs, and
 340          * never on GENET V1 hardware
 341          */
 342         if ((phydev->supported & PHY_GBIT_FEATURES) || GENET_IS_V1(priv))
 343                 phy_flags = 0;
 344
 345         phydev->dev_flags |= phy_flags;
 346         phydev->advertising = phydev->supported;
 347
 348         /* The internal PHY has its link interrupts routed to the
 349          * Ethernet MAC ISRs
 350          */
 351         if (phy_is_internal(priv->phydev))
 352                 priv->mii_bus->irq[phydev->addr] = PHY_IGNORE_INTERRUPT;
 353         else
 354                 priv->mii_bus->irq[phydev->addr] = PHY_POLL;
 355
 356         pr_info("attached PHY at address %d [%s]\n",
 357                 phydev->addr, phydev->drv->name);
 358
 359         return 0;
 360 }
 361
 362 static int bcmgenet_mii_alloc(struct bcmgenet_priv *priv)
 363 {
 364         struct mii_bus *bus;
 365
 366         if (priv->mii_bus)
 367                 return 0;
 368
 369         priv->mii_bus = mdiobus_alloc();
 370         if (!priv->mii_bus) {
 371                 pr_err("failed to allocate\n");
 372                 return -ENOMEM;
 373         }
 374
 375         bus = priv->mii_bus;
 376         bus->priv = priv->dev;
 377         bus->name = "bcmgenet MII bus";
 378         bus->parent = &priv->pdev->dev;
 379         bus->read = bcmgenet_mii_read;
 380         bus->write = bcmgenet_mii_write;
 381         snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d",
 382                  priv->pdev->name, priv->pdev->id);
 383
 384         bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
 385         if (!bus->irq) {
 386                 mdiobus_free(priv->mii_bus);
 387                 return -ENOMEM;
 388         }
 389
 390         return 0;
 391 }
 392
 393 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 394 {
 395         struct device_node *dn = priv->pdev->dev.of_node;
 396         struct device *kdev = &priv->pdev->dev;
 397         struct device_node *mdio_dn;
 398         char *compat;
 399         int ret;
 400
 401         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 402         if (!compat)
 403                 return -ENOMEM;
 404
 405         mdio_dn = of_find_compatible_node(dn, NULL, compat);
 406         kfree(compat);
 407         if (!mdio_dn) {
 408                 dev_err(kdev, "unable to find MDIO bus node\n");
 409                 return -ENODEV;
 410         }
 411
 412         ret = of_mdiobus_register(priv->mii_bus, mdio_dn);
 413         if (ret) {
 414                 dev_err(kdev, "failed to register MDIO bus\n");
 415                 return ret;
 416         }
 417
 418         /* Fetch the PHY phandle */
 419         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 420
 421         /* Get the link mode */
 422         priv->phy_interface = of_get_phy_mode(dn);
 423
 424         return 0;
 425 }
 426
 427 int bcmgenet_mii_init(struct net_device *dev)
 428 {
 429         struct bcmgenet_priv *priv = netdev_priv(dev);
 430         int ret;
 431
 432         ret = bcmgenet_mii_alloc(priv);
 433         if (ret)
 434                 return ret;
 435
 436         ret = bcmgenet_mii_of_init(priv);
 437         if (ret)
 438                 goto out_free;
 439
 440         ret = bcmgenet_mii_probe(dev);
 441         if (ret)
 442                 goto out;
 443
 444         return 0;
 445
 446 out:
 447         mdiobus_unregister(priv->mii_bus);
 448 out_free:
 449         kfree(priv->mii_bus->irq);
 450         mdiobus_free(priv->mii_bus);
 451         return ret;
 452 }
 453
 454 void bcmgenet_mii_exit(struct net_device *dev)
 455 {
 456         struct bcmgenet_priv *priv = netdev_priv(dev);
 457
 458         mdiobus_unregister(priv->mii_bus);
 459         kfree(priv->mii_bus->irq);
 460         mdiobus_free(priv->mii_bus);
 461 }