drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  *
   3  * Unless you and Broadcom execute a separate written software license
   4  * agreement governing use of this software, this software is licensed to you
   5  * under the terms of the GNU General Public License version 2, available
   6  * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
   7  *
   8  * Notwithstanding the above, under no circumstances may you combine this
   9  * software in any way with any other Broadcom software provided under a
  10  * license other than the GPL, without Broadcom's express prior written
  11  * consent.
  12  *
  13  * Written by Yaniv Rosner
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/pci.h>
  22 #include <linux/netdevice.h>
  23 #include <linux/delay.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mutex.h>
  26
  27 #include "bnx2x.h"
  28 #include "bnx2x_cmn.h"
  29
  30 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  31                                              struct link_params *params,
  32                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  33                                              u8 *o_buf, u8);
  34 /********************************************************/
  35 #define ETH_HLEN                        14
  36 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  37 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  38 #define ETH_MIN_PACKET_SIZE             60
  39 #define ETH_MAX_PACKET_SIZE             1500
  40 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  41 #define MDIO_ACCESS_TIMEOUT             1000
  42 #define WC_LANE_MAX                     4
  43 #define I2C_SWITCH_WIDTH                2
  44 #define I2C_BSC0                        0
  45 #define I2C_BSC1                        1
  46 #define I2C_WA_RETRY_CNT                3
  47 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  48 #define MCPR_IMC_COMMAND_READ_OP        1
  49 #define MCPR_IMC_COMMAND_WRITE_OP       2
  50
  51 /* LED Blink rate that will achieve ~15.9Hz */
  52 #define LED_BLINK_RATE_VAL_E3           354
  53 #define LED_BLINK_RATE_VAL_E1X_E2       480
  54 /***********************************************************/
  55 /*                      Shortcut definitions               */
  56 /***********************************************************/
  57
  58 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  59
  60 #define NIG_STATUS_EMAC0_MI_INT \
  61                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  62 #define NIG_STATUS_XGXS0_LINK10G \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  64 #define NIG_STATUS_XGXS0_LINK_STATUS \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  66 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  68 #define NIG_STATUS_SERDES0_LINK_STATUS \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  70 #define NIG_MASK_MI_INT \
  71                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  72 #define NIG_MASK_XGXS0_LINK10G \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  74 #define NIG_MASK_XGXS0_LINK_STATUS \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  76 #define NIG_MASK_SERDES0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  78
  79 #define MDIO_AN_CL73_OR_37_COMPLETE \
  80                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  81                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  82
  83 #define XGXS_RESET_BITS \
  84         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  85          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  86          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  89
  90 #define SERDES_RESET_BITS \
  91         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  92          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  93          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  95
  96 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  97 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
  98 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
  99 #define AUTONEG_PARALLEL \
 100                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 101 #define AUTONEG_SGMII_FIBER_AUTODET \
 102                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 103 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 104
 105 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 106                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 107 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 109 #define GP_STATUS_SPEED_MASK \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 111 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 112 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 113 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 114 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 115 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 116 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 117 #define GP_STATUS_10G_HIG \
 118                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 119 #define GP_STATUS_10G_CX4 \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 121 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 122 #define GP_STATUS_10G_KX4 \
 123                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 124 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 125 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 126 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 127 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 128 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 129 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 130 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 131 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 132 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 133 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 134 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 135 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 136 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 137 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 138 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 139 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 140 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 141 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 142 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 143 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 144
 145 #define LINK_UPDATE_MASK \
 146                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 147                          LINK_STATUS_LINK_UP | \
 148                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 149                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 150                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 151                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 152                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 153                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 154                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 155
 156 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 157         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 158         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 159         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 160
 161
 162 #define SFP_EEPROM_COMP_CODE_ADDR               0x3
 163         #define SFP_EEPROM_COMP_CODE_SR_MASK    (1<<4)
 164         #define SFP_EEPROM_COMP_CODE_LR_MASK    (1<<5)
 165         #define SFP_EEPROM_COMP_CODE_LRM_MASK   (1<<6)
 166
 167 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 168         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 169         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 170
 171 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 172         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 173 #define SFP_EEPROM_OPTIONS_SIZE                 2
 174
 175 #define EDC_MODE_LINEAR                         0x0022
 176 #define EDC_MODE_LIMITING                               0x0044
 177 #define EDC_MODE_PASSIVE_DAC                    0x0055
 178 #define EDC_MODE_ACTIVE_DAC                     0x0066
 179
 180 /* ETS defines*/
 181 #define DCBX_INVALID_COS                                        (0xFF)
 182
 183 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 184 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 185 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 186 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 187 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 188
 189 #define MAX_PACKET_SIZE                                 (9700)
 190 #define MAX_KR_LINK_RETRY                               4
 191
 192 /**********************************************************/
 193 /*                     INTERFACE                          */
 194 /**********************************************************/
 195
 196 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 197         bnx2x_cl45_write(_bp, _phy, \
 198                 (_phy)->def_md_devad, \
 199                 (_bank + (_addr & 0xf)), \
 200                 _val)
 201
 202 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 203         bnx2x_cl45_read(_bp, _phy, \
 204                 (_phy)->def_md_devad, \
 205                 (_bank + (_addr & 0xf)), \
 206                 _val)
 207
 208 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 209 {
 210         u32 val = REG_RD(bp, reg);
 211
 212         val |= bits;
 213         REG_WR(bp, reg, val);
 214         return val;
 215 }
 216
 217 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 218 {
 219         u32 val = REG_RD(bp, reg);
 220
 221         val &= ~bits;
 222         REG_WR(bp, reg, val);
 223         return val;
 224 }
 225
 226 /*
 227  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 228  *                   or link flap can be avoided.
 229  *
 230  * @params:     link parameters
 231  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 232  *         condition code.
 233  */
 234 static int bnx2x_check_lfa(struct link_params *params)
 235 {
 236         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 237         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 238         u32 saved_val, req_val, eee_status;
 239         struct bnx2x *bp = params->bp;
 240
 241         additional_config =
 242                 REG_RD(bp, params->lfa_base +
 243                            offsetof(struct shmem_lfa, additional_config));
 244
 245         /* NOTE: must be first condition checked -
 246         * to verify DCC bit is cleared in any case!
 247         */
 248         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 249                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 250                 REG_WR(bp, params->lfa_base +
 251                            offsetof(struct shmem_lfa, additional_config),
 252                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 253                 return LFA_DCC_LFA_DISABLED;
 254         }
 255
 256         /* Verify that link is up */
 257         link_status = REG_RD(bp, params->shmem_base +
 258                              offsetof(struct shmem_region,
 259                                       port_mb[params->port].link_status));
 260         if (!(link_status & LINK_STATUS_LINK_UP))
 261                 return LFA_LINK_DOWN;
 262
 263         /* if loaded after BOOT from SAN, don't flap the link in any case and
 264          * rely on link set by preboot driver
 265          */
 266         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 267                 return 0;
 268
 269         /* Verify that loopback mode is not set */
 270         if (params->loopback_mode)
 271                 return LFA_LOOPBACK_ENABLED;
 272
 273         /* Verify that MFW supports LFA */
 274         if (!params->lfa_base)
 275                 return LFA_MFW_IS_TOO_OLD;
 276
 277         if (params->num_phys == 3) {
 278                 cfg_size = 2;
 279                 lfa_mask = 0xffffffff;
 280         } else {
 281                 cfg_size = 1;
 282                 lfa_mask = 0xffff;
 283         }
 284
 285         /* Compare Duplex */
 286         saved_val = REG_RD(bp, params->lfa_base +
 287                            offsetof(struct shmem_lfa, req_duplex));
 288         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 289         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 290                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 291                                (saved_val & lfa_mask), (req_val & lfa_mask));
 292                 return LFA_DUPLEX_MISMATCH;
 293         }
 294         /* Compare Flow Control */
 295         saved_val = REG_RD(bp, params->lfa_base +
 296                            offsetof(struct shmem_lfa, req_flow_ctrl));
 297         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 298         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 299                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 300                                (saved_val & lfa_mask), (req_val & lfa_mask));
 301                 return LFA_FLOW_CTRL_MISMATCH;
 302         }
 303         /* Compare Link Speed */
 304         saved_val = REG_RD(bp, params->lfa_base +
 305                            offsetof(struct shmem_lfa, req_line_speed));
 306         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 307         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 308                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 309                                (saved_val & lfa_mask), (req_val & lfa_mask));
 310                 return LFA_LINK_SPEED_MISMATCH;
 311         }
 312
 313         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 314                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 315                                             offsetof(struct shmem_lfa,
 316                                                      speed_cap_mask[cfg_idx]));
 317
 318                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 319                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 320                                        cur_speed_cap_mask,
 321                                        params->speed_cap_mask[cfg_idx]);
 322                         return LFA_SPEED_CAP_MISMATCH;
 323                 }
 324         }
 325
 326         cur_req_fc_auto_adv =
 327                 REG_RD(bp, params->lfa_base +
 328                        offsetof(struct shmem_lfa, additional_config)) &
 329                 REQ_FC_AUTO_ADV_MASK;
 330
 331         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 332                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 333                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 334                 return LFA_FLOW_CTRL_MISMATCH;
 335         }
 336
 337         eee_status = REG_RD(bp, params->shmem2_base +
 338                             offsetof(struct shmem2_region,
 339                                      eee_status[params->port]));
 340
 341         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 342              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 343             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 344              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 345                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 346                                eee_status);
 347                 return LFA_EEE_MISMATCH;
 348         }
 349
 350         /* LFA conditions are met */
 351         return 0;
 352 }
 353 /******************************************************************/
 354 /*                      EPIO/GPIO section                         */
 355 /******************************************************************/
 356 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 357 {
 358         u32 epio_mask, gp_oenable;
 359         *en = 0;
 360         /* Sanity check */
 361         if (epio_pin > 31) {
 362                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 363                 return;
 364         }
 365
 366         epio_mask = 1 << epio_pin;
 367         /* Set this EPIO to output */
 368         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 369         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 370
 371         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 372 }
 373 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 374 {
 375         u32 epio_mask, gp_output, gp_oenable;
 376
 377         /* Sanity check */
 378         if (epio_pin > 31) {
 379                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 380                 return;
 381         }
 382         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 383         epio_mask = 1 << epio_pin;
 384         /* Set this EPIO to output */
 385         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 386         if (en)
 387                 gp_output |= epio_mask;
 388         else
 389                 gp_output &= ~epio_mask;
 390
 391         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 392
 393         /* Set the value for this EPIO */
 394         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 395         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 396 }
 397
 398 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 399 {
 400         if (pin_cfg == PIN_CFG_NA)
 401                 return;
 402         if (pin_cfg >= PIN_CFG_EPIO0) {
 403                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 404         } else {
 405                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 406                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 407                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 408         }
 409 }
 410
 411 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 412 {
 413         if (pin_cfg == PIN_CFG_NA)
 414                 return -EINVAL;
 415         if (pin_cfg >= PIN_CFG_EPIO0) {
 416                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 417         } else {
 418                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 419                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 420                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 421         }
 422         return 0;
 423
 424 }
 425 /******************************************************************/
 426 /*                              ETS section                       */
 427 /******************************************************************/
 428 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 429 {
 430         /* ETS disabled configuration*/
 431         struct bnx2x *bp = params->bp;
 432
 433         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 434
 435         /* mapping between entry  priority to client number (0,1,2 -debug and
 436          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 437          * 3bits client num.
 438          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 439          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 440          */
 441
 442         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 443         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 444          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 445          * COS0 entry, 4 - COS1 entry.
 446          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 447          * bit4   bit3    bit2   bit1     bit0
 448          * MCP and debug are strict
 449          */
 450
 451         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 452         /* defines which entries (clients) are subjected to WFQ arbitration */
 453         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 454         /* For strict priority entries defines the number of consecutive
 455          * slots for the highest priority.
 456          */
 457         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 458         /* mapping between the CREDIT_WEIGHT registers and actual client
 459          * numbers
 460          */
 461         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 462         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 463         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 464
 465         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 466         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 467         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 468         /* ETS mode disable */
 469         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 470         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 471          * weight for COS0/COS1.
 472          */
 473         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 474         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 475         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 476         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 477         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 478         /* Defines the number of consecutive slots for the strict priority */
 479         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 480 }
 481 /******************************************************************************
 482 * Description:
 483 *       Getting min_w_val will be set according to line speed .
 484 *.
 485 ******************************************************************************/
 486 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 487 {
 488         u32 min_w_val = 0;
 489         /* Calculate min_w_val.*/
 490         if (vars->link_up) {
 491                 if (vars->line_speed == SPEED_20000)
 492                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 493                 else
 494                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 495         } else
 496                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 497         /* If the link isn't up (static configuration for example ) The
 498          * link will be according to 20GBPS.
 499          */
 500         return min_w_val;
 501 }
 502 /******************************************************************************
 503 * Description:
 504 *       Getting credit upper bound form min_w_val.
 505 *.
 506 ******************************************************************************/
 507 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 508 {
 509         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 510                                                 MAX_PACKET_SIZE);
 511         return credit_upper_bound;
 512 }
 513 /******************************************************************************
 514 * Description:
 515 *       Set credit upper bound for NIG.
 516 *.
 517 ******************************************************************************/
 518 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 519         const struct link_params *params,
 520         const u32 min_w_val)
 521 {
 522         struct bnx2x *bp = params->bp;
 523         const u8 port = params->port;
 524         const u32 credit_upper_bound =
 525             bnx2x_ets_get_credit_upper_bound(min_w_val);
 526
 527         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 528                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 529         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 530                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 531         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 532                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 533         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 534                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 535         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 536                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 537         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 538                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 539
 540         if (!port) {
 541                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 542                         credit_upper_bound);
 543                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 544                         credit_upper_bound);
 545                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 546                         credit_upper_bound);
 547         }
 548 }
 549 /******************************************************************************
 550 * Description:
 551 *       Will return the NIG ETS registers to init values.Except
 552 *       credit_upper_bound.
 553 *       That isn't used in this configuration (No WFQ is enabled) and will be
 554 *       configured acording to spec
 555 *.
 556 ******************************************************************************/
 557 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 558                                         const struct link_vars *vars)
 559 {
 560         struct bnx2x *bp = params->bp;
 561         const u8 port = params->port;
 562         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 563         /* Mapping between entry  priority to client number (0,1,2 -debug and
 564          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 565          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 566          * reset value or init tool
 567          */
 568         if (port) {
 569                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 570                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 571         } else {
 572                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 573                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 574         }
 575         /* For strict priority entries defines the number of consecutive
 576          * slots for the highest priority.
 577          */
 578         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 579                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 580         /* Mapping between the CREDIT_WEIGHT registers and actual client
 581          * numbers
 582          */
 583         if (port) {
 584                 /*Port 1 has 6 COS*/
 585                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 586                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 587         } else {
 588                 /*Port 0 has 9 COS*/
 589                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 590                        0x43210876);
 591                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 592         }
 593
 594         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 595          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 596          * COS0 entry, 4 - COS1 entry.
 597          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 598          * bit4   bit3    bit2   bit1     bit0
 599          * MCP and debug are strict
 600          */
 601         if (port)
 602                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 603         else
 604                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 605         /* defines which entries (clients) are subjected to WFQ arbitration */
 606         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 607                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 608
 609         /* Please notice the register address are note continuous and a
 610          * for here is note appropriate.In 2 port mode port0 only COS0-5
 611          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 612          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 613          * are never used for WFQ
 614          */
 615         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 616                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 617         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 618                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 619         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 620                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 621         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 622                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 623         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 624                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 625         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 626                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 627         if (!port) {
 628                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 629                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 630                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 631         }
 632
 633         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 634 }
 635 /******************************************************************************
 636 * Description:
 637 *       Set credit upper bound for PBF.
 638 *.
 639 ******************************************************************************/
 640 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 641         const struct link_params *params,
 642         const u32 min_w_val)
 643 {
 644         struct bnx2x *bp = params->bp;
 645         const u32 credit_upper_bound =
 646             bnx2x_ets_get_credit_upper_bound(min_w_val);
 647         const u8 port = params->port;
 648         u32 base_upper_bound = 0;
 649         u8 max_cos = 0;
 650         u8 i = 0;
 651         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 652          * port mode port1 has COS0-2 that can be used for WFQ.
 653          */
 654         if (!port) {
 655                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 656                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 657         } else {
 658                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 659                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 660         }
 661
 662         for (i = 0; i < max_cos; i++)
 663                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 664 }
 665
 666 /******************************************************************************
 667 * Description:
 668 *       Will return the PBF ETS registers to init values.Except
 669 *       credit_upper_bound.
 670 *       That isn't used in this configuration (No WFQ is enabled) and will be
 671 *       configured acording to spec
 672 *.
 673 ******************************************************************************/
 674 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 675 {
 676         struct bnx2x *bp = params->bp;
 677         const u8 port = params->port;
 678         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 679         u8 i = 0;
 680         u32 base_weight = 0;
 681         u8 max_cos = 0;
 682
 683         /* Mapping between entry  priority to client number 0 - COS0
 684          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 685          * TODO_ETS - Should be done by reset value or init tool
 686          */
 687         if (port)
 688                 /*  0x688 (|011|0 10|00 1|000) */
 689                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 690         else
 691                 /*  (10 1|100 |011|0 10|00 1|000) */
 692                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 693
 694         /* TODO_ETS - Should be done by reset value or init tool */
 695         if (port)
 696                 /* 0x688 (|011|0 10|00 1|000)*/
 697                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 698         else
 699         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 700         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 701
 702         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 703                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 704
 705
 706         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 707                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 708
 709         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 710                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 711         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 712          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 713          */
 714         if (!port) {
 715                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 716                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 717         } else {
 718                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 719                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 720         }
 721
 722         for (i = 0; i < max_cos; i++)
 723                 REG_WR(bp, base_weight + (0x4 * i), 0);
 724
 725         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 726 }
 727 /******************************************************************************
 728 * Description:
 729 *       E3B0 disable will return basicly the values to init values.
 730 *.
 731 ******************************************************************************/
 732 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 733                                    const struct link_vars *vars)
 734 {
 735         struct bnx2x *bp = params->bp;
 736
 737         if (!CHIP_IS_E3B0(bp)) {
 738                 DP(NETIF_MSG_LINK,
 739                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 740                 return -EINVAL;
 741         }
 742
 743         bnx2x_ets_e3b0_nig_disabled(params, vars);
 744
 745         bnx2x_ets_e3b0_pbf_disabled(params);
 746
 747         return 0;
 748 }
 749
 750 /******************************************************************************
 751 * Description:
 752 *       Disable will return basicly the values to init values.
 753 *
 754 ******************************************************************************/
 755 int bnx2x_ets_disabled(struct link_params *params,
 756                       struct link_vars *vars)
 757 {
 758         struct bnx2x *bp = params->bp;
 759         int bnx2x_status = 0;
 760
 761         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 762                 bnx2x_ets_e2e3a0_disabled(params);
 763         else if (CHIP_IS_E3B0(bp))
 764                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 765         else {
 766                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 767                 return -EINVAL;
 768         }
 769
 770         return bnx2x_status;
 771 }
 772
 773 /******************************************************************************
 774 * Description
 775 *       Set the COS mappimg to SP and BW until this point all the COS are not
 776 *       set as SP or BW.
 777 ******************************************************************************/
 778 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 779                                   const struct bnx2x_ets_params *ets_params,
 780                                   const u8 cos_sp_bitmap,
 781                                   const u8 cos_bw_bitmap)
 782 {
 783         struct bnx2x *bp = params->bp;
 784         const u8 port = params->port;
 785         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 786         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 787         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 788         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 789
 790         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 791                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 792
 793         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 794                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 795
 796         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 797                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 798                nig_cli_subject2wfq_bitmap);
 799
 800         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 801                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 802                pbf_cli_subject2wfq_bitmap);
 803
 804         return 0;
 805 }
 806
 807 /******************************************************************************
 808 * Description:
 809 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 810 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 811 ******************************************************************************/
 812 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 813                                      const u8 cos_entry,
 814                                      const u32 min_w_val_nig,
 815                                      const u32 min_w_val_pbf,
 816                                      const u16 total_bw,
 817                                      const u8 bw,
 818                                      const u8 port)
 819 {
 820         u32 nig_reg_adress_crd_weight = 0;
 821         u32 pbf_reg_adress_crd_weight = 0;
 822         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 823         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 824         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 825
 826         switch (cos_entry) {
 827         case 0:
 828             nig_reg_adress_crd_weight =
 829                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 830                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 831              pbf_reg_adress_crd_weight = (port) ?
 832                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 833              break;
 834         case 1:
 835              nig_reg_adress_crd_weight = (port) ?
 836                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 837                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 838              pbf_reg_adress_crd_weight = (port) ?
 839                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 840              break;
 841         case 2:
 842              nig_reg_adress_crd_weight = (port) ?
 843                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 844                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 845
 846                  pbf_reg_adress_crd_weight = (port) ?
 847                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 848              break;
 849         case 3:
 850             if (port)
 851                         return -EINVAL;
 852              nig_reg_adress_crd_weight =
 853                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 854              pbf_reg_adress_crd_weight =
 855                  PBF_REG_COS3_WEIGHT_P0;
 856              break;
 857         case 4:
 858             if (port)
 859                 return -EINVAL;
 860              nig_reg_adress_crd_weight =
 861                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 862              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 863              break;
 864         case 5:
 865             if (port)
 866                 return -EINVAL;
 867              nig_reg_adress_crd_weight =
 868                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 869              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 870              break;
 871         }
 872
 873         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 874
 875         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 876
 877         return 0;
 878 }
 879 /******************************************************************************
 880 * Description:
 881 *       Calculate the total BW.A value of 0 isn't legal.
 882 *
 883 ******************************************************************************/
 884 static int bnx2x_ets_e3b0_get_total_bw(
 885         const struct link_params *params,
 886         struct bnx2x_ets_params *ets_params,
 887         u16 *total_bw)
 888 {
 889         struct bnx2x *bp = params->bp;
 890         u8 cos_idx = 0;
 891         u8 is_bw_cos_exist = 0;
 892
 893         *total_bw = 0 ;
 894         /* Calculate total BW requested */
 895         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 896                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 897                         is_bw_cos_exist = 1;
 898                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 899                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 900                                                    "was set to 0\n");
 901                                 /* This is to prevent a state when ramrods
 902                                  * can't be sent
 903                                  */
 904                                 ets_params->cos[cos_idx].params.bw_params.bw
 905                                          = 1;
 906                         }
 907                         *total_bw +=
 908                                 ets_params->cos[cos_idx].params.bw_params.bw;
 909                 }
 910         }
 911
 912         /* Check total BW is valid */
 913         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 914                 if (*total_bw == 0) {
 915                         DP(NETIF_MSG_LINK,
 916                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 917                         return -EINVAL;
 918                 }
 919                 DP(NETIF_MSG_LINK,
 920                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 921                 /* We can handle a case whre the BW isn't 100 this can happen
 922                  * if the TC are joined.
 923                  */
 924         }
 925         return 0;
 926 }
 927
 928 /******************************************************************************
 929 * Description:
 930 *       Invalidate all the sp_pri_to_cos.
 931 *
 932 ******************************************************************************/
 933 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 934 {
 935         u8 pri = 0;
 936         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 937                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 938 }
 939 /******************************************************************************
 940 * Description:
 941 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 942 *       according to sp_pri_to_cos.
 943 *
 944 ******************************************************************************/
 945 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 946                                             u8 *sp_pri_to_cos, const u8 pri,
 947                                             const u8 cos_entry)
 948 {
 949         struct bnx2x *bp = params->bp;
 950         const u8 port = params->port;
 951         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 952                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 953
 954         if (pri >= max_num_of_cos) {
 955                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 956                    "parameter Illegal strict priority\n");
 957             return -EINVAL;
 958         }
 959
 960         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 961                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 962                                    "parameter There can't be two COS's with "
 963                                    "the same strict pri\n");
 964                 return -EINVAL;
 965         }
 966
 967         sp_pri_to_cos[pri] = cos_entry;
 968         return 0;
 969
 970 }
 971
 972 /******************************************************************************
 973 * Description:
 974 *       Returns the correct value according to COS and priority in
 975 *       the sp_pri_cli register.
 976 *
 977 ******************************************************************************/
 978 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 979                                          const u8 pri_set,
 980                                          const u8 pri_offset,
 981                                          const u8 entry_size)
 982 {
 983         u64 pri_cli_nig = 0;
 984         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
 985                                                     (pri_set + pri_offset));
 986
 987         return pri_cli_nig;
 988 }
 989 /******************************************************************************
 990 * Description:
 991 *       Returns the correct value according to COS and priority in the
 992 *       sp_pri_cli register for NIG.
 993 *
 994 ******************************************************************************/
 995 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
 996 {
 997         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
 998         const u8 nig_cos_offset = 3;
 999         const u8 nig_pri_offset = 3;
1000
1001         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1002                 nig_pri_offset, 4);
1003
1004 }
1005 /******************************************************************************
1006 * Description:
1007 *       Returns the correct value according to COS and priority in the
1008 *       sp_pri_cli register for PBF.
1009 *
1010 ******************************************************************************/
1011 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1012 {
1013         const u8 pbf_cos_offset = 0;
1014         const u8 pbf_pri_offset = 0;
1015
1016         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1017                 pbf_pri_offset, 3);
1018
1019 }
1020
1021 /******************************************************************************
1022 * Description:
1023 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1024 *       according to sp_pri_to_cos.(which COS has higher priority)
1025 *
1026 ******************************************************************************/
1027 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1028                                              u8 *sp_pri_to_cos)
1029 {
1030         struct bnx2x *bp = params->bp;
1031         u8 i = 0;
1032         const u8 port = params->port;
1033         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1034         u64 pri_cli_nig = 0x210;
1035         u32 pri_cli_pbf = 0x0;
1036         u8 pri_set = 0;
1037         u8 pri_bitmask = 0;
1038         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1039                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1040
1041         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1042
1043         /* Set all the strict priority first */
1044         for (i = 0; i < max_num_of_cos; i++) {
1045                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1046                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1047                                 DP(NETIF_MSG_LINK,
1048                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1049                                            "invalid cos entry\n");
1050                                 return -EINVAL;
1051                         }
1052
1053                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1054                             sp_pri_to_cos[i], pri_set);
1055
1056                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1057                             sp_pri_to_cos[i], pri_set);
1058                         pri_bitmask = 1 << sp_pri_to_cos[i];
1059                         /* COS is used remove it from bitmap.*/
1060                         if (!(pri_bitmask & cos_bit_to_set)) {
1061                                 DP(NETIF_MSG_LINK,
1062                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1063                                         "invalid There can't be two COS's with"
1064                                         " the same strict pri\n");
1065                                 return -EINVAL;
1066                         }
1067                         cos_bit_to_set &= ~pri_bitmask;
1068                         pri_set++;
1069                 }
1070         }
1071
1072         /* Set all the Non strict priority i= COS*/
1073         for (i = 0; i < max_num_of_cos; i++) {
1074                 pri_bitmask = 1 << i;
1075                 /* Check if COS was already used for SP */
1076                 if (pri_bitmask & cos_bit_to_set) {
1077                         /* COS wasn't used for SP */
1078                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1079                             i, pri_set);
1080
1081                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1082                             i, pri_set);
1083                         /* COS is used remove it from bitmap.*/
1084                         cos_bit_to_set &= ~pri_bitmask;
1085                         pri_set++;
1086                 }
1087         }
1088
1089         if (pri_set != max_num_of_cos) {
1090                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1091                                    "entries were set\n");
1092                 return -EINVAL;
1093         }
1094
1095         if (port) {
1096                 /* Only 6 usable clients*/
1097                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1098                        (u32)pri_cli_nig);
1099
1100                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1101         } else {
1102                 /* Only 9 usable clients*/
1103                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1104                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1105
1106                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1107                        pri_cli_nig_lsb);
1108                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1109                        pri_cli_nig_msb);
1110
1111                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1112         }
1113         return 0;
1114 }
1115
1116 /******************************************************************************
1117 * Description:
1118 *       Configure the COS to ETS according to BW and SP settings.
1119 ******************************************************************************/
1120 int bnx2x_ets_e3b0_config(const struct link_params *params,
1121                          const struct link_vars *vars,
1122                          struct bnx2x_ets_params *ets_params)
1123 {
1124         struct bnx2x *bp = params->bp;
1125         int bnx2x_status = 0;
1126         const u8 port = params->port;
1127         u16 total_bw = 0;
1128         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1129         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1130         u8 cos_bw_bitmap = 0;
1131         u8 cos_sp_bitmap = 0;
1132         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1133         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1134                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1135         u8 cos_entry = 0;
1136
1137         if (!CHIP_IS_E3B0(bp)) {
1138                 DP(NETIF_MSG_LINK,
1139                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1140                 return -EINVAL;
1141         }
1142
1143         if ((ets_params->num_of_cos > max_num_of_cos)) {
1144                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1145                                    "isn't supported\n");
1146                 return -EINVAL;
1147         }
1148
1149         /* Prepare sp strict priority parameters*/
1150         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1151
1152         /* Prepare BW parameters*/
1153         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1154                                                    &total_bw);
1155         if (bnx2x_status) {
1156                 DP(NETIF_MSG_LINK,
1157                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1158                 return -EINVAL;
1159         }
1160
1161         /* Upper bound is set according to current link speed (min_w_val
1162          * should be the same for upper bound and COS credit val).
1163          */
1164         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1165         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1166
1167
1168         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1169                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1170                         cos_bw_bitmap |= (1 << cos_entry);
1171                         /* The function also sets the BW in HW(not the mappin
1172                          * yet)
1173                          */
1174                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1175                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1176                                 total_bw,
1177                                 ets_params->cos[cos_entry].params.bw_params.bw,
1178                                  port);
1179                 } else if (bnx2x_cos_state_strict ==
1180                         ets_params->cos[cos_entry].state){
1181                         cos_sp_bitmap |= (1 << cos_entry);
1182
1183                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1184                                 params,
1185                                 sp_pri_to_cos,
1186                                 ets_params->cos[cos_entry].params.sp_params.pri,
1187                                 cos_entry);
1188
1189                 } else {
1190                         DP(NETIF_MSG_LINK,
1191                            "bnx2x_ets_e3b0_config cos state not valid\n");
1192                         return -EINVAL;
1193                 }
1194                 if (bnx2x_status) {
1195                         DP(NETIF_MSG_LINK,
1196                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1197                         return bnx2x_status;
1198                 }
1199         }
1200
1201         /* Set SP register (which COS has higher priority) */
1202         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1203                                                          sp_pri_to_cos);
1204
1205         if (bnx2x_status) {
1206                 DP(NETIF_MSG_LINK,
1207                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1208                 return bnx2x_status;
1209         }
1210
1211         /* Set client mapping of BW and strict */
1212         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1213                                               cos_sp_bitmap,
1214                                               cos_bw_bitmap);
1215
1216         if (bnx2x_status) {
1217                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1218                 return bnx2x_status;
1219         }
1220         return 0;
1221 }
1222 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1223 {
1224         /* ETS disabled configuration */
1225         struct bnx2x *bp = params->bp;
1226         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1227         /* Defines which entries (clients) are subjected to WFQ arbitration
1228          * COS0 0x8
1229          * COS1 0x10
1230          */
1231         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1232         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1233          * client numbers (WEIGHT_0 does not actually have to represent
1234          * client 0)
1235          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1236          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1237          */
1238         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1239
1240         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1241                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1242         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1243                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1244
1245         /* ETS mode enabled*/
1246         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1247
1248         /* Defines the number of consecutive slots for the strict priority */
1249         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1250         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1251          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1252          * entry, 4 - COS1 entry.
1253          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1254          * bit4   bit3    bit2     bit1    bit0
1255          * MCP and debug are strict
1256          */
1257         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1258
1259         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1260         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1261                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1262         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1263                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1264 }
1265
1266 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1267                         const u32 cos1_bw)
1268 {
1269         /* ETS disabled configuration*/
1270         struct bnx2x *bp = params->bp;
1271         const u32 total_bw = cos0_bw + cos1_bw;
1272         u32 cos0_credit_weight = 0;
1273         u32 cos1_credit_weight = 0;
1274
1275         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1276
1277         if ((!total_bw) ||
1278             (!cos0_bw) ||
1279             (!cos1_bw)) {
1280                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1281                 return;
1282         }
1283
1284         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1285                 total_bw;
1286         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1287                 total_bw;
1288
1289         bnx2x_ets_bw_limit_common(params);
1290
1291         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1292         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1293
1294         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1295         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1296 }
1297
1298 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1299 {
1300         /* ETS disabled configuration*/
1301         struct bnx2x *bp = params->bp;
1302         u32 val = 0;
1303
1304         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1305         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1306          * as strict.  Bits 0,1,2 - debug and management entries,
1307          * 3 - COS0 entry, 4 - COS1 entry.
1308          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1309          *  bit4   bit3   bit2      bit1     bit0
1310          * MCP and debug are strict
1311          */
1312         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1313         /* For strict priority entries defines the number of consecutive slots
1314          * for the highest priority.
1315          */
1316         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1317         /* ETS mode disable */
1318         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1319         /* Defines the number of consecutive slots for the strict priority */
1320         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1321
1322         /* Defines the number of consecutive slots for the strict priority */
1323         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1324
1325         /* Mapping between entry  priority to client number (0,1,2 -debug and
1326          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1327          * 3bits client num.
1328          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1329          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1330          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1331          */
1332         val = (!strict_cos) ? 0x2318 : 0x22E0;
1333         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1334
1335         return 0;
1336 }
1337
1338 /******************************************************************/
1339 /*                      PFC section                               */
1340 /******************************************************************/
1341 static void bnx2x_update_pfc_xmac(struct link_params *params,
1342                                   struct link_vars *vars,
1343                                   u8 is_lb)
1344 {
1345         struct bnx2x *bp = params->bp;
1346         u32 xmac_base;
1347         u32 pause_val, pfc0_val, pfc1_val;
1348
1349         /* XMAC base adrr */
1350         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1351
1352         /* Initialize pause and pfc registers */
1353         pause_val = 0x18000;
1354         pfc0_val = 0xFFFF8000;
1355         pfc1_val = 0x2;
1356
1357         /* No PFC support */
1358         if (!(params->feature_config_flags &
1359               FEATURE_CONFIG_PFC_ENABLED)) {
1360
1361                 /* RX flow control - Process pause frame in receive direction
1362                  */
1363                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1364                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1365
1366                 /* TX flow control - Send pause packet when buffer is full */
1367                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1368                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1369         } else {/* PFC support */
1370                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1371                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1372                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1373                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1374                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1375                 /* Write pause and PFC registers */
1376                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1377                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1378                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1379                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1380
1381         }
1382
1383         /* Write pause and PFC registers */
1384         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1385         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1386         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1387
1388
1389         /* Set MAC address for source TX Pause/PFC frames */
1390         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1391                ((params->mac_addr[2] << 24) |
1392                 (params->mac_addr[3] << 16) |
1393                 (params->mac_addr[4] << 8) |
1394                 (params->mac_addr[5])));
1395         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1396                ((params->mac_addr[0] << 8) |
1397                 (params->mac_addr[1])));
1398
1399         udelay(30);
1400 }
1401
1402
1403 static void bnx2x_emac_get_pfc_stat(struct link_params *params,
1404                                     u32 pfc_frames_sent[2],
1405                                     u32 pfc_frames_received[2])
1406 {
1407         /* Read pfc statistic */
1408         struct bnx2x *bp = params->bp;
1409         u32 emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1410         u32 val_xon = 0;
1411         u32 val_xoff = 0;
1412
1413         DP(NETIF_MSG_LINK, "pfc statistic read from EMAC\n");
1414
1415         /* PFC received frames */
1416         val_xoff = REG_RD(bp, emac_base +
1417                                 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
1418         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
1419         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
1420         val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
1421
1422         pfc_frames_received[0] = val_xon + val_xoff;
1423
1424         /* PFC received sent */
1425         val_xoff = REG_RD(bp, emac_base +
1426                                 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
1427         val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
1428         val_xon = REG_RD(bp, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
1429         val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
1430
1431         pfc_frames_sent[0] = val_xon + val_xoff;
1432 }
1433
1434 /* Read pfc statistic*/
1435 void bnx2x_pfc_statistic(struct link_params *params, struct link_vars *vars,
1436                          u32 pfc_frames_sent[2],
1437                          u32 pfc_frames_received[2])
1438 {
1439         /* Read pfc statistic */
1440         struct bnx2x *bp = params->bp;
1441
1442         DP(NETIF_MSG_LINK, "pfc statistic\n");
1443
1444         if (!vars->link_up)
1445                 return;
1446
1447         if (vars->mac_type == MAC_TYPE_EMAC) {
1448                 DP(NETIF_MSG_LINK, "About to read PFC stats from EMAC\n");
1449                 bnx2x_emac_get_pfc_stat(params, pfc_frames_sent,
1450                                         pfc_frames_received);
1451         }
1452 }
1453 /******************************************************************/
1454 /*                      MAC/PBF section                           */
1455 /******************************************************************/
1456 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1457                                u32 emac_base)
1458 {
1459         u32 new_mode, cur_mode;
1460         u32 clc_cnt;
1461         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1462          * (a value of 49==0x31) and make sure that the AUTO poll is off
1463          */
1464         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1465
1466         if (USES_WARPCORE(bp))
1467                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1468         else
1469                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1470
1471         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1472             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1473                 return;
1474
1475         new_mode = cur_mode &
1476                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1477         new_mode |= clc_cnt;
1478         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1479
1480         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1481            cur_mode, new_mode);
1482         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1483         udelay(40);
1484 }
1485
1486 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1487                                         struct link_params *params)
1488 {
1489         u8 phy_index;
1490         /* Set mdio clock per phy */
1491         for (phy_index = INT_PHY; phy_index < params->num_phys;
1492               phy_index++)
1493                 bnx2x_set_mdio_clk(bp, params->chip_id,
1494                                    params->phy[phy_index].mdio_ctrl);
1495 }
1496
1497 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1498 {
1499         u32 port4mode_ovwr_val;
1500         /* Check 4-port override enabled */
1501         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1502         if (port4mode_ovwr_val & (1<<0)) {
1503                 /* Return 4-port mode override value */
1504                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1505         }
1506         /* Return 4-port mode from input pin */
1507         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1508 }
1509
1510 static void bnx2x_emac_init(struct link_params *params,
1511                             struct link_vars *vars)
1512 {
1513         /* reset and unreset the emac core */
1514         struct bnx2x *bp = params->bp;
1515         u8 port = params->port;
1516         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1517         u32 val;
1518         u16 timeout;
1519
1520         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1521                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1522         udelay(5);
1523         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1524                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1525
1526         /* init emac - use read-modify-write */
1527         /* self clear reset */
1528         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1529         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1530
1531         timeout = 200;
1532         do {
1533                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1534                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1535                 if (!timeout) {
1536                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1537                         return;
1538                 }
1539                 timeout--;
1540         } while (val & EMAC_MODE_RESET);
1541
1542         bnx2x_set_mdio_emac_per_phy(bp, params);
1543         /* Set mac address */
1544         val = ((params->mac_addr[0] << 8) |
1545                 params->mac_addr[1]);
1546         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1547
1548         val = ((params->mac_addr[2] << 24) |
1549                (params->mac_addr[3] << 16) |
1550                (params->mac_addr[4] << 8) |
1551                 params->mac_addr[5]);
1552         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1553 }
1554
1555 static void bnx2x_set_xumac_nig(struct link_params *params,
1556                                 u16 tx_pause_en,
1557                                 u8 enable)
1558 {
1559         struct bnx2x *bp = params->bp;
1560
1561         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1562                enable);
1563         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1564                enable);
1565         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1566                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1567 }
1568
1569 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1570 {
1571         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1572         u32 val;
1573         struct bnx2x *bp = params->bp;
1574         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1575                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1576                 return;
1577         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1578         if (en)
1579                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1580                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1581         else
1582                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1583                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1584         /* Disable RX and TX */
1585         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1586 }
1587
1588 static void bnx2x_umac_enable(struct link_params *params,
1589                             struct link_vars *vars, u8 lb)
1590 {
1591         u32 val;
1592         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1593         struct bnx2x *bp = params->bp;
1594         /* Reset UMAC */
1595         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1596                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1597         usleep_range(1000, 2000);
1598
1599         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1600                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1601
1602         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1603
1604         /* This register opens the gate for the UMAC despite its name */
1605         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1606
1607         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1608                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1609                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1610                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1611         switch (vars->line_speed) {
1612         case SPEED_10:
1613                 val |= (0<<2);
1614                 break;
1615         case SPEED_100:
1616                 val |= (1<<2);
1617                 break;
1618         case SPEED_1000:
1619                 val |= (2<<2);
1620                 break;
1621         case SPEED_2500:
1622                 val |= (3<<2);
1623                 break;
1624         default:
1625                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1626                                vars->line_speed);
1627                 break;
1628         }
1629         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1630                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1631
1632         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1633                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1634
1635         if (vars->duplex == DUPLEX_HALF)
1636                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1637
1638         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1639         udelay(50);
1640
1641         /* Configure UMAC for EEE */
1642         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1643                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1644                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1645                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1646                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1647         } else {
1648                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1649         }
1650
1651         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1652         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1653                ((params->mac_addr[2] << 24) |
1654                 (params->mac_addr[3] << 16) |
1655                 (params->mac_addr[4] << 8) |
1656                 (params->mac_addr[5])));
1657         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1658                ((params->mac_addr[0] << 8) |
1659                 (params->mac_addr[1])));
1660
1661         /* Enable RX and TX */
1662         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1663         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1664                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1665         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1666         udelay(50);
1667
1668         /* Remove SW Reset */
1669         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1670
1671         /* Check loopback mode */
1672         if (lb)
1673                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1674         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1675
1676         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1677          * length used by the MAC receive logic to check frames.
1678          */
1679         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1680         bnx2x_set_xumac_nig(params,
1681                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1682         vars->mac_type = MAC_TYPE_UMAC;
1683
1684 }
1685
1686 /* Define the XMAC mode */
1687 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1688 {
1689         struct bnx2x *bp = params->bp;
1690         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1691
1692         /* In 4-port mode, need to set the mode only once, so if XMAC is
1693          * already out of reset, it means the mode has already been set,
1694          * and it must not* reset the XMAC again, since it controls both
1695          * ports of the path
1696          */
1697
1698         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1699              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1700              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1701             is_port4mode &&
1702             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1703              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1704                 DP(NETIF_MSG_LINK,
1705                    "XMAC already out of reset in 4-port mode\n");
1706                 return;
1707         }
1708
1709         /* Hard reset */
1710         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1711                MISC_REGISTERS_RESET_REG_2_XMAC);
1712         usleep_range(1000, 2000);
1713
1714         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1715                MISC_REGISTERS_RESET_REG_2_XMAC);
1716         if (is_port4mode) {
1717                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1718
1719                 /* Set the number of ports on the system side to up to 2 */
1720                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1721
1722                 /* Set the number of ports on the Warp Core to 10G */
1723                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1724         } else {
1725                 /* Set the number of ports on the system side to 1 */
1726                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1727                 if (max_speed == SPEED_10000) {
1728                         DP(NETIF_MSG_LINK,
1729                            "Init XMAC to 10G x 1 port per path\n");
1730                         /* Set the number of ports on the Warp Core to 10G */
1731                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1732                 } else {
1733                         DP(NETIF_MSG_LINK,
1734                            "Init XMAC to 20G x 2 ports per path\n");
1735                         /* Set the number of ports on the Warp Core to 20G */
1736                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1737                 }
1738         }
1739         /* Soft reset */
1740         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1741                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1742         usleep_range(1000, 2000);
1743
1744         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1745                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1746
1747 }
1748
1749 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1750 {
1751         u8 port = params->port;
1752         struct bnx2x *bp = params->bp;
1753         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1754         u32 val;
1755
1756         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1757             MISC_REGISTERS_RESET_REG_2_XMAC) {
1758                 /* Send an indication to change the state in the NIG back to XON
1759                  * Clearing this bit enables the next set of this bit to get
1760                  * rising edge
1761                  */
1762                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1763                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1764                        (pfc_ctrl & ~(1<<1)));
1765                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1766                        (pfc_ctrl | (1<<1)));
1767                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1768                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1769                 if (en)
1770                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1771                 else
1772                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1773                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1774         }
1775 }
1776
1777 static int bnx2x_xmac_enable(struct link_params *params,
1778                              struct link_vars *vars, u8 lb)
1779 {
1780         u32 val, xmac_base;
1781         struct bnx2x *bp = params->bp;
1782         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1783
1784         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1785
1786         bnx2x_xmac_init(params, vars->line_speed);
1787
1788         /* This register determines on which events the MAC will assert
1789          * error on the i/f to the NIG along w/ EOP.
1790          */
1791
1792         /* This register tells the NIG whether to send traffic to UMAC
1793          * or XMAC
1794          */
1795         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1796
1797         /* When XMAC is in XLGMII mode, disable sending idles for fault
1798          * detection.
1799          */
1800         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1801                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1802                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1803                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1804                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1805                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1806                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1807                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1808         }
1809         /* Set Max packet size */
1810         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1811
1812         /* CRC append for Tx packets */
1813         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1814
1815         /* update PFC */
1816         bnx2x_update_pfc_xmac(params, vars, 0);
1817
1818         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1819                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1820                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1821                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1822         } else {
1823                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1824         }
1825
1826         /* Enable TX and RX */
1827         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1828
1829         /* Set MAC in XLGMII mode for dual-mode */
1830         if ((vars->line_speed == SPEED_20000) &&
1831             (params->phy[INT_PHY].supported &
1832              SUPPORTED_20000baseKR2_Full))
1833                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1834
1835         /* Check loopback mode */
1836         if (lb)
1837                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1838         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1839         bnx2x_set_xumac_nig(params,
1840                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1841
1842         vars->mac_type = MAC_TYPE_XMAC;
1843
1844         return 0;
1845 }
1846
1847 static int bnx2x_emac_enable(struct link_params *params,
1848                              struct link_vars *vars, u8 lb)
1849 {
1850         struct bnx2x *bp = params->bp;
1851         u8 port = params->port;
1852         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1853         u32 val;
1854
1855         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1856
1857         /* Disable BMAC */
1858         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1859                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1860
1861         /* enable emac and not bmac */
1862         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1863
1864         /* ASIC */
1865         if (vars->phy_flags & PHY_XGXS_FLAG) {
1866                 u32 ser_lane = ((params->lane_config &
1867                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1868                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1869
1870                 DP(NETIF_MSG_LINK, "XGXS\n");
1871                 /* select the master lanes (out of 0-3) */
1872                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1873                 /* select XGXS */
1874                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1875
1876         } else { /* SerDes */
1877                 DP(NETIF_MSG_LINK, "SerDes\n");
1878                 /* select SerDes */
1879                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1880         }
1881
1882         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1883                       EMAC_RX_MODE_RESET);
1884         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1885                       EMAC_TX_MODE_RESET);
1886
1887                 /* pause enable/disable */
1888                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1889                                EMAC_RX_MODE_FLOW_EN);
1890
1891                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1892                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1893                                 EMAC_TX_MODE_FLOW_EN));
1894                 if (!(params->feature_config_flags &
1895                       FEATURE_CONFIG_PFC_ENABLED)) {
1896                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1897                                 bnx2x_bits_en(bp, emac_base +
1898                                               EMAC_REG_EMAC_RX_MODE,
1899                                               EMAC_RX_MODE_FLOW_EN);
1900
1901                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1902                                 bnx2x_bits_en(bp, emac_base +
1903                                               EMAC_REG_EMAC_TX_MODE,
1904                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1905                                                EMAC_TX_MODE_FLOW_EN));
1906                 } else
1907                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1908                                       EMAC_TX_MODE_FLOW_EN);
1909
1910         /* KEEP_VLAN_TAG, promiscuous */
1911         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1912         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1913
1914         /* Setting this bit causes MAC control frames (except for pause
1915          * frames) to be passed on for processing. This setting has no
1916          * affect on the operation of the pause frames. This bit effects
1917          * all packets regardless of RX Parser packet sorting logic.
1918          * Turn the PFC off to make sure we are in Xon state before
1919          * enabling it.
1920          */
1921         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1922         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1923                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1924                 /* Enable PFC again */
1925                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1926                         EMAC_REG_RX_PFC_MODE_RX_EN |
1927                         EMAC_REG_RX_PFC_MODE_TX_EN |
1928                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1929
1930                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1931                         ((0x0101 <<
1932                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1933                          (0x00ff <<
1934                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1935                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1936         }
1937         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1938
1939         /* Set Loopback */
1940         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1941         if (lb)
1942                 val |= 0x810;
1943         else
1944                 val &= ~0x810;
1945         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1946
1947         /* Enable emac */
1948         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1949
1950         /* Enable emac for jumbo packets */
1951         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1952                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1953                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1954
1955         /* Strip CRC */
1956         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1957
1958         /* Disable the NIG in/out to the bmac */
1959         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1960         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1961         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1962
1963         /* Enable the NIG in/out to the emac */
1964         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1965         val = 0;
1966         if ((params->feature_config_flags &
1967               FEATURE_CONFIG_PFC_ENABLED) ||
1968             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1969                 val = 1;
1970
1971         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1972         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1973
1974         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1975
1976         vars->mac_type = MAC_TYPE_EMAC;
1977         return 0;
1978 }
1979
1980 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1981                                    struct link_vars *vars)
1982 {
1983         u32 wb_data[2];
1984         struct bnx2x *bp = params->bp;
1985         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1986                 NIG_REG_INGRESS_BMAC0_MEM;
1987
1988         u32 val = 0x14;
1989         if ((!(params->feature_config_flags &
1990               FEATURE_CONFIG_PFC_ENABLED)) &&
1991                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1992                 /* Enable BigMAC to react on received Pause packets */
1993                 val |= (1<<5);
1994         wb_data[0] = val;
1995         wb_data[1] = 0;
1996         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1997
1998         /* TX control */
1999         val = 0xc0;
2000         if (!(params->feature_config_flags &
2001               FEATURE_CONFIG_PFC_ENABLED) &&
2002                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2003                 val |= 0x800000;
2004         wb_data[0] = val;
2005         wb_data[1] = 0;
2006         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2007 }
2008
2009 static void bnx2x_update_pfc_bmac2(struct link_params *params,
2010                                    struct link_vars *vars,
2011                                    u8 is_lb)
2012 {
2013         /* Set rx control: Strip CRC and enable BigMAC to relay
2014          * control packets to the system as well
2015          */
2016         u32 wb_data[2];
2017         struct bnx2x *bp = params->bp;
2018         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2019                 NIG_REG_INGRESS_BMAC0_MEM;
2020         u32 val = 0x14;
2021
2022         if ((!(params->feature_config_flags &
2023               FEATURE_CONFIG_PFC_ENABLED)) &&
2024                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
2025                 /* Enable BigMAC to react on received Pause packets */
2026                 val |= (1<<5);
2027         wb_data[0] = val;
2028         wb_data[1] = 0;
2029         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2030         udelay(30);
2031
2032         /* Tx control */
2033         val = 0xc0;
2034         if (!(params->feature_config_flags &
2035                                 FEATURE_CONFIG_PFC_ENABLED) &&
2036             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2037                 val |= 0x800000;
2038         wb_data[0] = val;
2039         wb_data[1] = 0;
2040         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2041
2042         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2043                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2044                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2045                 wb_data[0] = 0x0;
2046                 wb_data[0] |= (1<<0);  /* RX */
2047                 wb_data[0] |= (1<<1);  /* TX */
2048                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2049                 wb_data[0] |= (1<<3);  /* 8 cos */
2050                 wb_data[0] |= (1<<5);  /* STATS */
2051                 wb_data[1] = 0;
2052                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2053                             wb_data, 2);
2054                 /* Clear the force Xon */
2055                 wb_data[0] &= ~(1<<2);
2056         } else {
2057                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2058                 /* Disable PFC RX & TX & STATS and set 8 COS */
2059                 wb_data[0] = 0x8;
2060                 wb_data[1] = 0;
2061         }
2062
2063         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2064
2065         /* Set Time (based unit is 512 bit time) between automatic
2066          * re-sending of PP packets amd enable automatic re-send of
2067          * Per-Priroity Packet as long as pp_gen is asserted and
2068          * pp_disable is low.
2069          */
2070         val = 0x8000;
2071         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2072                 val |= (1<<16); /* enable automatic re-send */
2073
2074         wb_data[0] = val;
2075         wb_data[1] = 0;
2076         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2077                     wb_data, 2);
2078
2079         /* mac control */
2080         val = 0x3; /* Enable RX and TX */
2081         if (is_lb) {
2082                 val |= 0x4; /* Local loopback */
2083                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2084         }
2085         /* When PFC enabled, Pass pause frames towards the NIG. */
2086         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2087                 val |= ((1<<6)|(1<<5));
2088
2089         wb_data[0] = val;
2090         wb_data[1] = 0;
2091         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2092 }
2093
2094 /******************************************************************************
2095 * Description:
2096 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2097 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2098 ******************************************************************************/
2099 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2100                                            u8 cos_entry,
2101                                            u32 priority_mask, u8 port)
2102 {
2103         u32 nig_reg_rx_priority_mask_add = 0;
2104
2105         switch (cos_entry) {
2106         case 0:
2107              nig_reg_rx_priority_mask_add = (port) ?
2108                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2109                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2110              break;
2111         case 1:
2112             nig_reg_rx_priority_mask_add = (port) ?
2113                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2114                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2115             break;
2116         case 2:
2117             nig_reg_rx_priority_mask_add = (port) ?
2118                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2119                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2120             break;
2121         case 3:
2122             if (port)
2123                 return -EINVAL;
2124             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2125             break;
2126         case 4:
2127             if (port)
2128                 return -EINVAL;
2129             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2130             break;
2131         case 5:
2132             if (port)
2133                 return -EINVAL;
2134             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2135             break;
2136         }
2137
2138         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2139
2140         return 0;
2141 }
2142 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2143 {
2144         struct bnx2x *bp = params->bp;
2145
2146         REG_WR(bp, params->shmem_base +
2147                offsetof(struct shmem_region,
2148                         port_mb[params->port].link_status), link_status);
2149 }
2150
2151 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2152 {
2153         struct bnx2x *bp = params->bp;
2154
2155         if (SHMEM2_HAS(bp, link_attr_sync))
2156                 REG_WR(bp, params->shmem2_base +
2157                        offsetof(struct shmem2_region,
2158                                 link_attr_sync[params->port]), link_attr);
2159 }
2160
2161 static void bnx2x_update_pfc_nig(struct link_params *params,
2162                 struct link_vars *vars,
2163                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2164 {
2165         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2166         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2167         u32 pkt_priority_to_cos = 0;
2168         struct bnx2x *bp = params->bp;
2169         u8 port = params->port;
2170
2171         int set_pfc = params->feature_config_flags &
2172                 FEATURE_CONFIG_PFC_ENABLED;
2173         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2174
2175         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2176          * MAC control frames (that are not pause packets)
2177          * will be forwarded to the XCM.
2178          */
2179         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2180                           NIG_REG_LLH0_XCM_MASK);
2181         /* NIG params will override non PFC params, since it's possible to
2182          * do transition from PFC to SAFC
2183          */
2184         if (set_pfc) {
2185                 pause_enable = 0;
2186                 llfc_out_en = 0;
2187                 llfc_enable = 0;
2188                 if (CHIP_IS_E3(bp))
2189                         ppp_enable = 0;
2190                 else
2191                         ppp_enable = 1;
2192                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2193                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2194                 xcm_out_en = 0;
2195                 hwpfc_enable = 1;
2196         } else  {
2197                 if (nig_params) {
2198                         llfc_out_en = nig_params->llfc_out_en;
2199                         llfc_enable = nig_params->llfc_enable;
2200                         pause_enable = nig_params->pause_enable;
2201                 } else  /* Default non PFC mode - PAUSE */
2202                         pause_enable = 1;
2203
2204                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2205                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2206                 xcm_out_en = 1;
2207         }
2208
2209         if (CHIP_IS_E3(bp))
2210                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2211                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2212         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2213                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2214         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2215                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2216         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2217                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2218
2219         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2220                NIG_REG_PPP_ENABLE_0, ppp_enable);
2221
2222         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2223                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2224
2225         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2226                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2227
2228         /* Output enable for RX_XCM # IF */
2229         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2230                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2231
2232         /* HW PFC TX enable */
2233         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2234                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2235
2236         if (nig_params) {
2237                 u8 i = 0;
2238                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2239
2240                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2241                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2242                 nig_params->rx_cos_priority_mask[i], port);
2243
2244                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2245                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2246                        nig_params->llfc_high_priority_classes);
2247
2248                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2249                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2250                        nig_params->llfc_low_priority_classes);
2251         }
2252         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2253                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2254                pkt_priority_to_cos);
2255 }
2256
2257 int bnx2x_update_pfc(struct link_params *params,
2258                       struct link_vars *vars,
2259                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2260 {
2261         /* The PFC and pause are orthogonal to one another, meaning when
2262          * PFC is enabled, the pause are disabled, and when PFC is
2263          * disabled, pause are set according to the pause result.
2264          */
2265         u32 val;
2266         struct bnx2x *bp = params->bp;
2267         int bnx2x_status = 0;
2268         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2269
2270         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2271                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2272         else
2273                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2274
2275         bnx2x_update_mng(params, vars->link_status);
2276
2277         /* Update NIG params */
2278         bnx2x_update_pfc_nig(params, vars, pfc_params);
2279
2280         if (!vars->link_up)
2281                 return bnx2x_status;
2282
2283         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2284
2285         if (CHIP_IS_E3(bp)) {
2286                 if (vars->mac_type == MAC_TYPE_XMAC)
2287                         bnx2x_update_pfc_xmac(params, vars, 0);
2288         } else {
2289                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2290                 if ((val &
2291                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2292                     == 0) {
2293                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2294                         bnx2x_emac_enable(params, vars, 0);
2295                         return bnx2x_status;
2296                 }
2297                 if (CHIP_IS_E2(bp))
2298                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2299                 else
2300                         bnx2x_update_pfc_bmac1(params, vars);
2301
2302                 val = 0;
2303                 if ((params->feature_config_flags &
2304                      FEATURE_CONFIG_PFC_ENABLED) ||
2305                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2306                         val = 1;
2307                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2308         }
2309         return bnx2x_status;
2310 }
2311
2312 static int bnx2x_bmac1_enable(struct link_params *params,
2313                               struct link_vars *vars,
2314                               u8 is_lb)
2315 {
2316         struct bnx2x *bp = params->bp;
2317         u8 port = params->port;
2318         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2319                                NIG_REG_INGRESS_BMAC0_MEM;
2320         u32 wb_data[2];
2321         u32 val;
2322
2323         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2324
2325         /* XGXS control */
2326         wb_data[0] = 0x3c;
2327         wb_data[1] = 0;
2328         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2329                     wb_data, 2);
2330
2331         /* TX MAC SA */
2332         wb_data[0] = ((params->mac_addr[2] << 24) |
2333                        (params->mac_addr[3] << 16) |
2334                        (params->mac_addr[4] << 8) |
2335                         params->mac_addr[5]);
2336         wb_data[1] = ((params->mac_addr[0] << 8) |
2337                         params->mac_addr[1]);
2338         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2339
2340         /* MAC control */
2341         val = 0x3;
2342         if (is_lb) {
2343                 val |= 0x4;
2344                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2345         }
2346         wb_data[0] = val;
2347         wb_data[1] = 0;
2348         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2349
2350         /* Set rx mtu */
2351         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2352         wb_data[1] = 0;
2353         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2354
2355         bnx2x_update_pfc_bmac1(params, vars);
2356
2357         /* Set tx mtu */
2358         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2359         wb_data[1] = 0;
2360         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2361
2362         /* Set cnt max size */
2363         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2364         wb_data[1] = 0;
2365         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2366
2367         /* Configure SAFC */
2368         wb_data[0] = 0x1000200;
2369         wb_data[1] = 0;
2370         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2371                     wb_data, 2);
2372
2373         return 0;
2374 }
2375
2376 static int bnx2x_bmac2_enable(struct link_params *params,
2377                               struct link_vars *vars,
2378                               u8 is_lb)
2379 {
2380         struct bnx2x *bp = params->bp;
2381         u8 port = params->port;
2382         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2383                                NIG_REG_INGRESS_BMAC0_MEM;
2384         u32 wb_data[2];
2385
2386         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2387
2388         wb_data[0] = 0;
2389         wb_data[1] = 0;
2390         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2391         udelay(30);
2392
2393         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2394         wb_data[0] = 0x3c;
2395         wb_data[1] = 0;
2396         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2397                     wb_data, 2);
2398
2399         udelay(30);
2400
2401         /* TX MAC SA */
2402         wb_data[0] = ((params->mac_addr[2] << 24) |
2403                        (params->mac_addr[3] << 16) |
2404                        (params->mac_addr[4] << 8) |
2405                         params->mac_addr[5]);
2406         wb_data[1] = ((params->mac_addr[0] << 8) |
2407                         params->mac_addr[1]);
2408         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2409                     wb_data, 2);
2410
2411         udelay(30);
2412
2413         /* Configure SAFC */
2414         wb_data[0] = 0x1000200;
2415         wb_data[1] = 0;
2416         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2417                     wb_data, 2);
2418         udelay(30);
2419
2420         /* Set RX MTU */
2421         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2422         wb_data[1] = 0;
2423         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2424         udelay(30);
2425
2426         /* Set TX MTU */
2427         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2428         wb_data[1] = 0;
2429         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2430         udelay(30);
2431         /* Set cnt max size */
2432         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2433         wb_data[1] = 0;
2434         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2435         udelay(30);
2436         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2437
2438         return 0;
2439 }
2440
2441 static int bnx2x_bmac_enable(struct link_params *params,
2442                              struct link_vars *vars,
2443                              u8 is_lb, u8 reset_bmac)
2444 {
2445         int rc = 0;
2446         u8 port = params->port;
2447         struct bnx2x *bp = params->bp;
2448         u32 val;
2449         /* Reset and unreset the BigMac */
2450         if (reset_bmac) {
2451                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2452                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2453                 usleep_range(1000, 2000);
2454         }
2455
2456         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2457                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2458
2459         /* Enable access for bmac registers */
2460         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2461
2462         /* Enable BMAC according to BMAC type*/
2463         if (CHIP_IS_E2(bp))
2464                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2465         else
2466                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2467         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2468         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2469         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2470         val = 0;
2471         if ((params->feature_config_flags &
2472               FEATURE_CONFIG_PFC_ENABLED) ||
2473             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2474                 val = 1;
2475         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2476         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2477         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2478         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2479         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2480         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2481
2482         vars->mac_type = MAC_TYPE_BMAC;
2483         return rc;
2484 }
2485
2486 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2487 {
2488         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2489                         NIG_REG_INGRESS_BMAC0_MEM;
2490         u32 wb_data[2];
2491         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2492
2493         if (CHIP_IS_E2(bp))
2494                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2495         else
2496                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2497         /* Only if the bmac is out of reset */
2498         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2499                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2500             nig_bmac_enable) {
2501                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2502                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2503                 if (en)
2504                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2505                 else
2506                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2507                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2508                 usleep_range(1000, 2000);
2509         }
2510 }
2511
2512 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2513                             u32 line_speed)
2514 {
2515         struct bnx2x *bp = params->bp;
2516         u8 port = params->port;
2517         u32 init_crd, crd;
2518         u32 count = 1000;
2519
2520         /* Disable port */
2521         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2522
2523         /* Wait for init credit */
2524         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2525         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2526         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2527
2528         while ((init_crd != crd) && count) {
2529                 usleep_range(5000, 10000);
2530                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2531                 count--;
2532         }
2533         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2534         if (init_crd != crd) {
2535                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2536                           init_crd, crd);
2537                 return -EINVAL;
2538         }
2539
2540         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2541             line_speed == SPEED_10 ||
2542             line_speed == SPEED_100 ||
2543             line_speed == SPEED_1000 ||
2544             line_speed == SPEED_2500) {
2545                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2546                 /* Update threshold */
2547                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2548                 /* Update init credit */
2549                 init_crd = 778;         /* (800-18-4) */
2550
2551         } else {
2552                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2553                               ETH_OVREHEAD)/16;
2554                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2555                 /* Update threshold */
2556                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2557                 /* Update init credit */
2558                 switch (line_speed) {
2559                 case SPEED_10000:
2560                         init_crd = thresh + 553 - 22;
2561                         break;
2562                 default:
2563                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2564                                   line_speed);
2565                         return -EINVAL;
2566                 }
2567         }
2568         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2569         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2570                  line_speed, init_crd);
2571
2572         /* Probe the credit changes */
2573         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2574         usleep_range(5000, 10000);
2575         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2576
2577         /* Enable port */
2578         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2579         return 0;
2580 }
2581
2582 /**
2583  * bnx2x_get_emac_base - retrive emac base address
2584  *
2585  * @bp:                 driver handle
2586  * @mdc_mdio_access:    access type
2587  * @port:               port id
2588  *
2589  * This function selects the MDC/MDIO access (through emac0 or
2590  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2591  * phy has a default access mode, which could also be overridden
2592  * by nvram configuration. This parameter, whether this is the
2593  * default phy configuration, or the nvram overrun
2594  * configuration, is passed here as mdc_mdio_access and selects
2595  * the emac_base for the CL45 read/writes operations
2596  */
2597 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2598                                u32 mdc_mdio_access, u8 port)
2599 {
2600         u32 emac_base = 0;
2601         switch (mdc_mdio_access) {
2602         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2603                 break;
2604         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2605                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2606                         emac_base = GRCBASE_EMAC1;
2607                 else
2608                         emac_base = GRCBASE_EMAC0;
2609                 break;
2610         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2611                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2612                         emac_base = GRCBASE_EMAC0;
2613                 else
2614                         emac_base = GRCBASE_EMAC1;
2615                 break;
2616         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2617                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2618                 break;
2619         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2620                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2621                 break;
2622         default:
2623                 break;
2624         }
2625         return emac_base;
2626
2627 }
2628
2629 /******************************************************************/
2630 /*                      CL22 access functions                     */
2631 /******************************************************************/
2632 static int bnx2x_cl22_write(struct bnx2x *bp,
2633                                        struct bnx2x_phy *phy,
2634                                        u16 reg, u16 val)
2635 {
2636         u32 tmp, mode;
2637         u8 i;
2638         int rc = 0;
2639         /* Switch to CL22 */
2640         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2641         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2642                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2643
2644         /* Address */
2645         tmp = ((phy->addr << 21) | (reg << 16) | val |
2646                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2647                EMAC_MDIO_COMM_START_BUSY);
2648         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2649
2650         for (i = 0; i < 50; i++) {
2651                 udelay(10);
2652
2653                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2654                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2655                         udelay(5);
2656                         break;
2657                 }
2658         }
2659         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2660                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2661                 rc = -EFAULT;
2662         }
2663         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2664         return rc;
2665 }
2666
2667 static int bnx2x_cl22_read(struct bnx2x *bp,
2668                                       struct bnx2x_phy *phy,
2669                                       u16 reg, u16 *ret_val)
2670 {
2671         u32 val, mode;
2672         u16 i;
2673         int rc = 0;
2674
2675         /* Switch to CL22 */
2676         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2677         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2678                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2679
2680         /* Address */
2681         val = ((phy->addr << 21) | (reg << 16) |
2682                EMAC_MDIO_COMM_COMMAND_READ_22 |
2683                EMAC_MDIO_COMM_START_BUSY);
2684         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2685
2686         for (i = 0; i < 50; i++) {
2687                 udelay(10);
2688
2689                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2690                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2691                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2692                         udelay(5);
2693                         break;
2694                 }
2695         }
2696         if (val & EMAC_MDIO_COMM_START_BUSY) {
2697                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2698
2699                 *ret_val = 0;
2700                 rc = -EFAULT;
2701         }
2702         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2703         return rc;
2704 }
2705
2706 /******************************************************************/
2707 /*                      CL45 access functions                     */
2708 /******************************************************************/
2709 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2710                            u8 devad, u16 reg, u16 *ret_val)
2711 {
2712         u32 val;
2713         u16 i;
2714         int rc = 0;
2715         u32 chip_id;
2716         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2717                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2718                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2719                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2720         }
2721
2722         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2723                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2724                               EMAC_MDIO_STATUS_10MB);
2725         /* Address */
2726         val = ((phy->addr << 21) | (devad << 16) | reg |
2727                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2728                EMAC_MDIO_COMM_START_BUSY);
2729         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2730
2731         for (i = 0; i < 50; i++) {
2732                 udelay(10);
2733
2734                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2735                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2736                         udelay(5);
2737                         break;
2738                 }
2739         }
2740         if (val & EMAC_MDIO_COMM_START_BUSY) {
2741                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2742                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2743                 *ret_val = 0;
2744                 rc = -EFAULT;
2745         } else {
2746                 /* Data */
2747                 val = ((phy->addr << 21) | (devad << 16) |
2748                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2749                        EMAC_MDIO_COMM_START_BUSY);
2750                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2751
2752                 for (i = 0; i < 50; i++) {
2753                         udelay(10);
2754
2755                         val = REG_RD(bp, phy->mdio_ctrl +
2756                                      EMAC_REG_EMAC_MDIO_COMM);
2757                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2758                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2759                                 break;
2760                         }
2761                 }
2762                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2763                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2764                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2765                         *ret_val = 0;
2766                         rc = -EFAULT;
2767                 }
2768         }
2769         /* Work around for E3 A0 */
2770         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2771                 phy->flags ^= FLAGS_DUMMY_READ;
2772                 if (phy->flags & FLAGS_DUMMY_READ) {
2773                         u16 temp_val;
2774                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2775                 }
2776         }
2777
2778         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2779                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2780                                EMAC_MDIO_STATUS_10MB);
2781         return rc;
2782 }
2783
2784 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2785                             u8 devad, u16 reg, u16 val)
2786 {
2787         u32 tmp;
2788         u8 i;
2789         int rc = 0;
2790         u32 chip_id;
2791         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2792                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2793                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2794                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2795         }
2796
2797         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2798                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2799                               EMAC_MDIO_STATUS_10MB);
2800
2801         /* Address */
2802         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2803                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2804                EMAC_MDIO_COMM_START_BUSY);
2805         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2806
2807         for (i = 0; i < 50; i++) {
2808                 udelay(10);
2809
2810                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2811                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2812                         udelay(5);
2813                         break;
2814                 }
2815         }
2816         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2817                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2818                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2819                 rc = -EFAULT;
2820         } else {
2821                 /* Data */
2822                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2823                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2824                        EMAC_MDIO_COMM_START_BUSY);
2825                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2826
2827                 for (i = 0; i < 50; i++) {
2828                         udelay(10);
2829
2830                         tmp = REG_RD(bp, phy->mdio_ctrl +
2831                                      EMAC_REG_EMAC_MDIO_COMM);
2832                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2833                                 udelay(5);
2834                                 break;
2835                         }
2836                 }
2837                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2838                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2839                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2840                         rc = -EFAULT;
2841                 }
2842         }
2843         /* Work around for E3 A0 */
2844         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2845                 phy->flags ^= FLAGS_DUMMY_READ;
2846                 if (phy->flags & FLAGS_DUMMY_READ) {
2847                         u16 temp_val;
2848                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2849                 }
2850         }
2851         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2852                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2853                                EMAC_MDIO_STATUS_10MB);
2854         return rc;
2855 }
2856
2857 /******************************************************************/
2858 /*                      EEE section                                */
2859 /******************************************************************/
2860 static u8 bnx2x_eee_has_cap(struct link_params *params)
2861 {
2862         struct bnx2x *bp = params->bp;
2863
2864         if (REG_RD(bp, params->shmem2_base) <=
2865                    offsetof(struct shmem2_region, eee_status[params->port]))
2866                 return 0;
2867
2868         return 1;
2869 }
2870
2871 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2872 {
2873         switch (nvram_mode) {
2874         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2875                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2876                 break;
2877         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2878                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2879                 break;
2880         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2881                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2882                 break;
2883         default:
2884                 *idle_timer = 0;
2885                 break;
2886         }
2887
2888         return 0;
2889 }
2890
2891 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2892 {
2893         switch (idle_timer) {
2894         case EEE_MODE_NVRAM_BALANCED_TIME:
2895                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2896                 break;
2897         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2898                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2899                 break;
2900         case EEE_MODE_NVRAM_LATENCY_TIME:
2901                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2902                 break;
2903         default:
2904                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2905                 break;
2906         }
2907
2908         return 0;
2909 }
2910
2911 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2912 {
2913         u32 eee_mode, eee_idle;
2914         struct bnx2x *bp = params->bp;
2915
2916         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2917                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2918                         /* time value in eee_mode --> used directly*/
2919                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2920                 } else {
2921                         /* hsi value in eee_mode --> time */
2922                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2923                                                     EEE_MODE_NVRAM_MASK,
2924                                                     &eee_idle))
2925                                 return 0;
2926                 }
2927         } else {
2928                 /* hsi values in nvram --> time*/
2929                 eee_mode = ((REG_RD(bp, params->shmem_base +
2930                                     offsetof(struct shmem_region, dev_info.
2931                                     port_feature_config[params->port].
2932                                     eee_power_mode)) &
2933                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2934                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2935
2936                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2937                         return 0;
2938         }
2939
2940         return eee_idle;
2941 }
2942
2943 static int bnx2x_eee_set_timers(struct link_params *params,
2944                                    struct link_vars *vars)
2945 {
2946         u32 eee_idle = 0, eee_mode;
2947         struct bnx2x *bp = params->bp;
2948
2949         eee_idle = bnx2x_eee_calc_timer(params);
2950
2951         if (eee_idle) {
2952                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2953                        eee_idle);
2954         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2955                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2956                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2957                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2958                 return -EINVAL;
2959         }
2960
2961         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2962         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2963                 /* eee_idle in 1u --> eee_status in 16u */
2964                 eee_idle >>= 4;
2965                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2966                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2967         } else {
2968                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2969                         return -EINVAL;
2970                 vars->eee_status |= eee_mode;
2971         }
2972
2973         return 0;
2974 }
2975
2976 static int bnx2x_eee_initial_config(struct link_params *params,
2977                                      struct link_vars *vars, u8 mode)
2978 {
2979         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2980
2981         /* Propogate params' bits --> vars (for migration exposure) */
2982         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2983                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2984         else
2985                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2986
2987         if (params->eee_mode & EEE_MODE_ADV_LPI)
2988                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2989         else
2990                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2991
2992         return bnx2x_eee_set_timers(params, vars);
2993 }
2994
2995 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2996                                 struct link_params *params,
2997                                 struct link_vars *vars)
2998 {
2999         struct bnx2x *bp = params->bp;
3000
3001         /* Make Certain LPI is disabled */
3002         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3003
3004         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3005
3006         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3007
3008         return 0;
3009 }
3010
3011 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
3012                                   struct link_params *params,
3013                                   struct link_vars *vars, u8 modes)
3014 {
3015         struct bnx2x *bp = params->bp;
3016         u16 val = 0;
3017
3018         /* Mask events preventing LPI generation */
3019         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3020
3021         if (modes & SHMEM_EEE_10G_ADV) {
3022                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
3023                 val |= 0x8;
3024         }
3025         if (modes & SHMEM_EEE_1G_ADV) {
3026                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
3027                 val |= 0x4;
3028         }
3029
3030         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3031
3032         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3033         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3034
3035         return 0;
3036 }
3037
3038 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3039 {
3040         struct bnx2x *bp = params->bp;
3041
3042         if (bnx2x_eee_has_cap(params))
3043                 REG_WR(bp, params->shmem2_base +
3044                        offsetof(struct shmem2_region,
3045                                 eee_status[params->port]), eee_status);
3046 }
3047
3048 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3049                                   struct link_params *params,
3050                                   struct link_vars *vars)
3051 {
3052         struct bnx2x *bp = params->bp;
3053         u16 adv = 0, lp = 0;
3054         u32 lp_adv = 0;
3055         u8 neg = 0;
3056
3057         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3058         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3059
3060         if (lp & 0x2) {
3061                 lp_adv |= SHMEM_EEE_100M_ADV;
3062                 if (adv & 0x2) {
3063                         if (vars->line_speed == SPEED_100)
3064                                 neg = 1;
3065                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3066                 }
3067         }
3068         if (lp & 0x14) {
3069                 lp_adv |= SHMEM_EEE_1G_ADV;
3070                 if (adv & 0x14) {
3071                         if (vars->line_speed == SPEED_1000)
3072                                 neg = 1;
3073                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3074                 }
3075         }
3076         if (lp & 0x68) {
3077                 lp_adv |= SHMEM_EEE_10G_ADV;
3078                 if (adv & 0x68) {
3079                         if (vars->line_speed == SPEED_10000)
3080                                 neg = 1;
3081                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3082                 }
3083         }
3084
3085         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3086         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3087
3088         if (neg) {
3089                 DP(NETIF_MSG_LINK, "EEE is active\n");
3090                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3091         }
3092
3093 }
3094
3095 /******************************************************************/
3096 /*                      BSC access functions from E3              */
3097 /******************************************************************/
3098 static void bnx2x_bsc_module_sel(struct link_params *params)
3099 {
3100         int idx;
3101         u32 board_cfg, sfp_ctrl;
3102         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3103         struct bnx2x *bp = params->bp;
3104         u8 port = params->port;
3105         /* Read I2C output PINs */
3106         board_cfg = REG_RD(bp, params->shmem_base +
3107                            offsetof(struct shmem_region,
3108                                     dev_info.shared_hw_config.board));
3109         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3110         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3111                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3112
3113         /* Read I2C output value */
3114         sfp_ctrl = REG_RD(bp, params->shmem_base +
3115                           offsetof(struct shmem_region,
3116                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3117         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3118         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3119         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3120         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3121                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3122 }
3123
3124 static int bnx2x_bsc_read(struct link_params *params,
3125                           struct bnx2x_phy *phy,
3126                           u8 sl_devid,
3127                           u16 sl_addr,
3128                           u8 lc_addr,
3129                           u8 xfer_cnt,
3130                           u32 *data_array)
3131 {
3132         u32 val, i;
3133         int rc = 0;
3134         struct bnx2x *bp = params->bp;
3135
3136         if (xfer_cnt > 16) {
3137                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3138                                         xfer_cnt);
3139                 return -EINVAL;
3140         }
3141         bnx2x_bsc_module_sel(params);
3142
3143         xfer_cnt = 16 - lc_addr;
3144
3145         /* Enable the engine */
3146         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3147         val |= MCPR_IMC_COMMAND_ENABLE;
3148         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3149
3150         /* Program slave device ID */
3151         val = (sl_devid << 16) | sl_addr;
3152         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3153
3154         /* Start xfer with 0 byte to update the address pointer ???*/
3155         val = (MCPR_IMC_COMMAND_ENABLE) |
3156               (MCPR_IMC_COMMAND_WRITE_OP <<
3157                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3158                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3159         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3160
3161         /* Poll for completion */
3162         i = 0;
3163         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3164         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3165                 udelay(10);
3166                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3167                 if (i++ > 1000) {
3168                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3169                                                                 i);
3170                         rc = -EFAULT;
3171                         break;
3172                 }
3173         }
3174         if (rc == -EFAULT)
3175                 return rc;
3176
3177         /* Start xfer with read op */
3178         val = (MCPR_IMC_COMMAND_ENABLE) |
3179                 (MCPR_IMC_COMMAND_READ_OP <<
3180                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3181                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3182                   (xfer_cnt);
3183         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3184
3185         /* Poll for completion */
3186         i = 0;
3187         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3188         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3189                 udelay(10);
3190                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3191                 if (i++ > 1000) {
3192                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3193                         rc = -EFAULT;
3194                         break;
3195                 }
3196         }
3197         if (rc == -EFAULT)
3198                 return rc;
3199
3200         for (i = (lc_addr >> 2); i < 4; i++) {
3201                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3202 #ifdef __BIG_ENDIAN
3203                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3204                                 ((data_array[i] & 0x0000ff00) << 8) |
3205                                 ((data_array[i] & 0x00ff0000) >> 8) |
3206                                 ((data_array[i] & 0xff000000) >> 24);
3207 #endif
3208         }
3209         return rc;
3210 }
3211
3212 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3213                                      u8 devad, u16 reg, u16 or_val)
3214 {
3215         u16 val;
3216         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3217         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3218 }
3219
3220 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3221                                       struct bnx2x_phy *phy,
3222                                       u8 devad, u16 reg, u16 and_val)
3223 {
3224         u16 val;
3225         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3226         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3227 }
3228
3229 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3230                    u8 devad, u16 reg, u16 *ret_val)
3231 {
3232         u8 phy_index;
3233         /* Probe for the phy according to the given phy_addr, and execute
3234          * the read request on it
3235          */
3236         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3237                 if (params->phy[phy_index].addr == phy_addr) {
3238                         return bnx2x_cl45_read(params->bp,
3239                                                &params->phy[phy_index], devad,
3240                                                reg, ret_val);
3241                 }
3242         }
3243         return -EINVAL;
3244 }
3245
3246 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3247                     u8 devad, u16 reg, u16 val)
3248 {
3249         u8 phy_index;
3250         /* Probe for the phy according to the given phy_addr, and execute
3251          * the write request on it
3252          */
3253         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3254                 if (params->phy[phy_index].addr == phy_addr) {
3255                         return bnx2x_cl45_write(params->bp,
3256                                                 &params->phy[phy_index], devad,
3257                                                 reg, val);
3258                 }
3259         }
3260         return -EINVAL;
3261 }
3262 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3263                                   struct link_params *params)
3264 {
3265         u8 lane = 0;
3266         struct bnx2x *bp = params->bp;
3267         u32 path_swap, path_swap_ovr;
3268         u8 path, port;
3269
3270         path = BP_PATH(bp);
3271         port = params->port;
3272
3273         if (bnx2x_is_4_port_mode(bp)) {
3274                 u32 port_swap, port_swap_ovr;
3275
3276                 /* Figure out path swap value */
3277                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3278                 if (path_swap_ovr & 0x1)
3279                         path_swap = (path_swap_ovr & 0x2);
3280                 else
3281                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3282
3283                 if (path_swap)
3284                         path = path ^ 1;
3285
3286                 /* Figure out port swap value */
3287                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3288                 if (port_swap_ovr & 0x1)
3289                         port_swap = (port_swap_ovr & 0x2);
3290                 else
3291                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3292
3293                 if (port_swap)
3294                         port = port ^ 1;
3295
3296                 lane = (port<<1) + path;
3297         } else { /* Two port mode - no port swap */
3298
3299                 /* Figure out path swap value */
3300                 path_swap_ovr =
3301                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3302                 if (path_swap_ovr & 0x1) {
3303                         path_swap = (path_swap_ovr & 0x2);
3304                 } else {
3305                         path_swap =
3306                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3307                 }
3308                 if (path_swap)
3309                         path = path ^ 1;
3310
3311                 lane = path << 1 ;
3312         }
3313         return lane;
3314 }
3315
3316 static void bnx2x_set_aer_mmd(struct link_params *params,
3317                               struct bnx2x_phy *phy)
3318 {
3319         u32 ser_lane;
3320         u16 offset, aer_val;
3321         struct bnx2x *bp = params->bp;
3322         ser_lane = ((params->lane_config &
3323                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3324                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3325
3326         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3327                 (phy->addr + ser_lane) : 0;
3328
3329         if (USES_WARPCORE(bp)) {
3330                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3331                 /* In Dual-lane mode, two lanes are joined together,
3332                  * so in order to configure them, the AER broadcast method is
3333                  * used here.
3334                  * 0x200 is the broadcast address for lanes 0,1
3335                  * 0x201 is the broadcast address for lanes 2,3
3336                  */
3337                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3338                         aer_val = (aer_val >> 1) | 0x200;
3339         } else if (CHIP_IS_E2(bp))
3340                 aer_val = 0x3800 + offset - 1;
3341         else
3342                 aer_val = 0x3800 + offset;
3343
3344         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3345                           MDIO_AER_BLOCK_AER_REG, aer_val);
3346
3347 }
3348
3349 /******************************************************************/
3350 /*                      Internal phy section                      */
3351 /******************************************************************/
3352
3353 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3354 {
3355         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3356
3357         /* Set Clause 22 */
3358         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3359         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3360         udelay(500);
3361         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3362         udelay(500);
3363          /* Set Clause 45 */
3364         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3365 }
3366
3367 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3368 {
3369         u32 val;
3370
3371         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3372
3373         val = SERDES_RESET_BITS << (port*16);
3374
3375         /* Reset and unreset the SerDes/XGXS */
3376         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3377         udelay(500);
3378         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3379
3380         bnx2x_set_serdes_access(bp, port);
3381
3382         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3383                DEFAULT_PHY_DEV_ADDR);
3384 }
3385
3386 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3387                                      struct link_params *params,
3388                                      u32 action)
3389 {
3390         struct bnx2x *bp = params->bp;
3391         switch (action) {
3392         case PHY_INIT:
3393                 /* Set correct devad */
3394                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3395                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3396                        phy->def_md_devad);
3397                 break;
3398         }
3399 }
3400
3401 static void bnx2x_xgxs_deassert(struct link_params *params)
3402 {
3403         struct bnx2x *bp = params->bp;
3404         u8 port;
3405         u32 val;
3406         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3407         port = params->port;
3408
3409         val = XGXS_RESET_BITS << (port*16);
3410
3411         /* Reset and unreset the SerDes/XGXS */
3412         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3413         udelay(500);
3414         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3415         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3416                                  PHY_INIT);
3417 }
3418
3419 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3420                                      struct link_params *params, u16 *ieee_fc)
3421 {
3422         struct bnx2x *bp = params->bp;
3423         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3424         /* Resolve pause mode and advertisement Please refer to Table
3425          * 28B-3 of the 802.3ab-1999 spec
3426          */
3427
3428         switch (phy->req_flow_ctrl) {
3429         case BNX2X_FLOW_CTRL_AUTO:
3430                 switch (params->req_fc_auto_adv) {
3431                 case BNX2X_FLOW_CTRL_BOTH:
3432                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3433                         break;
3434                 case BNX2X_FLOW_CTRL_RX:
3435                 case BNX2X_FLOW_CTRL_TX:
3436                         *ieee_fc |=
3437                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3438                         break;
3439                 default:
3440                         break;
3441                 }
3442                 break;
3443         case BNX2X_FLOW_CTRL_TX:
3444                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3445                 break;
3446
3447         case BNX2X_FLOW_CTRL_RX:
3448         case BNX2X_FLOW_CTRL_BOTH:
3449                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3450                 break;
3451
3452         case BNX2X_FLOW_CTRL_NONE:
3453         default:
3454                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3455                 break;
3456         }
3457         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3458 }
3459
3460 static void set_phy_vars(struct link_params *params,
3461                          struct link_vars *vars)
3462 {
3463         struct bnx2x *bp = params->bp;
3464         u8 actual_phy_idx, phy_index, link_cfg_idx;
3465         u8 phy_config_swapped = params->multi_phy_config &
3466                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3467         for (phy_index = INT_PHY; phy_index < params->num_phys;
3468               phy_index++) {
3469                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3470                 actual_phy_idx = phy_index;
3471                 if (phy_config_swapped) {
3472                         if (phy_index == EXT_PHY1)
3473                                 actual_phy_idx = EXT_PHY2;
3474                         else if (phy_index == EXT_PHY2)
3475                                 actual_phy_idx = EXT_PHY1;
3476                 }
3477                 params->phy[actual_phy_idx].req_flow_ctrl =
3478                         params->req_flow_ctrl[link_cfg_idx];
3479
3480                 params->phy[actual_phy_idx].req_line_speed =
3481                         params->req_line_speed[link_cfg_idx];
3482
3483                 params->phy[actual_phy_idx].speed_cap_mask =
3484                         params->speed_cap_mask[link_cfg_idx];
3485
3486                 params->phy[actual_phy_idx].req_duplex =
3487                         params->req_duplex[link_cfg_idx];
3488
3489                 if (params->req_line_speed[link_cfg_idx] ==
3490                     SPEED_AUTO_NEG)
3491                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3492
3493                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3494                            " speed_cap_mask %x\n",
3495                            params->phy[actual_phy_idx].req_flow_ctrl,
3496                            params->phy[actual_phy_idx].req_line_speed,
3497                            params->phy[actual_phy_idx].speed_cap_mask);
3498         }
3499 }
3500
3501 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3502                                     struct bnx2x_phy *phy,
3503                                     struct link_vars *vars)
3504 {
3505         u16 val;
3506         struct bnx2x *bp = params->bp;
3507         /* Read modify write pause advertizing */
3508         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3509
3510         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3511
3512         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3513         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3514         if ((vars->ieee_fc &
3515             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3516             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3517                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3518         }
3519         if ((vars->ieee_fc &
3520             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3521             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3522                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3523         }
3524         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3525         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3526 }
3527
3528 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
3529 {                                               /*  LD      LP   */
3530         switch (pause_result) {                 /* ASYM P ASYM P */
3531         case 0xb:                               /*   1  0   1  1 */
3532                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3533                 break;
3534
3535         case 0xe:                               /*   1  1   1  0 */
3536                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3537                 break;
3538
3539         case 0x5:                               /*   0  1   0  1 */
3540         case 0x7:                               /*   0  1   1  1 */
3541         case 0xd:                               /*   1  1   0  1 */
3542         case 0xf:                               /*   1  1   1  1 */
3543                 vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3544                 break;
3545
3546         default:
3547                 break;
3548         }
3549         if (pause_result & (1<<0))
3550                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3551         if (pause_result & (1<<1))
3552                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3553
3554 }
3555
3556 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3557                                         struct link_params *params,
3558                                         struct link_vars *vars)
3559 {
3560         u16 ld_pause;           /* local */
3561         u16 lp_pause;           /* link partner */
3562         u16 pause_result;
3563         struct bnx2x *bp = params->bp;
3564         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3565                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3566                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3567         } else if (CHIP_IS_E3(bp) &&
3568                 SINGLE_MEDIA_DIRECT(params)) {
3569                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3570                 u16 gp_status, gp_mask;
3571                 bnx2x_cl45_read(bp, phy,
3572                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3573                                 &gp_status);
3574                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3575                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3576                         lane;
3577                 if ((gp_status & gp_mask) == gp_mask) {
3578                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3579                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3580                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3581                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3582                 } else {
3583                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3584                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3585                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3586                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3587                         ld_pause = ((ld_pause &
3588                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3589                                     << 3);
3590                         lp_pause = ((lp_pause &
3591                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3592                                     << 3);
3593                 }
3594         } else {
3595                 bnx2x_cl45_read(bp, phy,
3596                                 MDIO_AN_DEVAD,
3597                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3598                 bnx2x_cl45_read(bp, phy,
3599                                 MDIO_AN_DEVAD,
3600                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3601         }
3602         pause_result = (ld_pause &
3603                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3604         pause_result |= (lp_pause &
3605                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3606         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3607         bnx2x_pause_resolve(vars, pause_result);
3608
3609 }
3610
3611 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3612                                    struct link_params *params,
3613                                    struct link_vars *vars)
3614 {
3615         u8 ret = 0;
3616         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3617         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3618                 /* Update the advertised flow-controled of LD/LP in AN */
3619                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3620                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3621                 /* But set the flow-control result as the requested one */
3622                 vars->flow_ctrl = phy->req_flow_ctrl;
3623         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3624                 vars->flow_ctrl = params->req_fc_auto_adv;
3625         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3626                 ret = 1;
3627                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3628         }
3629         return ret;
3630 }
3631 /******************************************************************/
3632 /*                      Warpcore section                          */
3633 /******************************************************************/
3634 /* The init_internal_warpcore should mirror the xgxs,
3635  * i.e. reset the lane (if needed), set aer for the
3636  * init configuration, and set/clear SGMII flag. Internal
3637  * phy init is done purely in phy_init stage.
3638  */
3639 #define WC_TX_DRIVER(post2, idriver, ipre) \
3640         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3641          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3642          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
3643
3644 #define WC_TX_FIR(post, main, pre) \
3645         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3646          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3647          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3648
3649 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3650                                          struct link_params *params,
3651                                          struct link_vars *vars)
3652 {
3653         struct bnx2x *bp = params->bp;
3654         u16 i;
3655         static struct bnx2x_reg_set reg_set[] = {
3656                 /* Step 1 - Program the TX/RX alignment markers */
3657                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3658                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3659                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3660                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3661                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3662                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3663                 /* Step 2 - Configure the NP registers */
3664                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3665                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3666                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3667                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3668                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3669                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3670                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3671                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3672                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3673         };
3674         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3675
3676         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3677                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3678
3679         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3680                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3681                                  reg_set[i].val);
3682
3683         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3684         vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3685         bnx2x_update_link_attr(params, vars->link_attr_sync);
3686 }
3687
3688 static void bnx2x_disable_kr2(struct link_params *params,
3689                               struct link_vars *vars,
3690                               struct bnx2x_phy *phy)
3691 {
3692         struct bnx2x *bp = params->bp;
3693         int i;
3694         static struct bnx2x_reg_set reg_set[] = {
3695                 /* Step 1 - Program the TX/RX alignment markers */
3696                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3697                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3698                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3699                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3700                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3701                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3702                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3703                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3704                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3705                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3706                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3707                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3708                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3709                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3710                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3711         };
3712         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3713
3714         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3715                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3716                                  reg_set[i].val);
3717         vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3718         bnx2x_update_link_attr(params, vars->link_attr_sync);
3719
3720         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3721 }
3722
3723 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3724                                                struct link_params *params)
3725 {
3726         struct bnx2x *bp = params->bp;
3727
3728         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3729         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3730                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3731         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3732                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3733 }
3734
3735 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3736                                          struct link_params *params)
3737 {
3738         /* Restart autoneg on the leading lane only */
3739         struct bnx2x *bp = params->bp;
3740         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3741         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3742                           MDIO_AER_BLOCK_AER_REG, lane);
3743         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3744                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3745
3746         /* Restore AER */
3747         bnx2x_set_aer_mmd(params, phy);
3748 }
3749
3750 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3751                                         struct link_params *params,
3752                                         struct link_vars *vars) {
3753         u16 lane, i, cl72_ctrl, an_adv = 0;
3754         struct bnx2x *bp = params->bp;
3755         static struct bnx2x_reg_set reg_set[] = {
3756                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3757                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3758                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3759                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3760                 /* Disable Autoneg: re-enable it after adv is done. */
3761                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3762                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3763                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3764         };
3765         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3766         /* Set to default registers that may be overriden by 10G force */
3767         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3768                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3769                                  reg_set[i].val);
3770
3771         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3772                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3773         cl72_ctrl &= 0x08ff;
3774         cl72_ctrl |= 0x3800;
3775         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3776                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3777
3778         /* Check adding advertisement for 1G KX */
3779         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3780              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3781             (vars->line_speed == SPEED_1000)) {
3782                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3783                 an_adv |= (1<<5);
3784
3785                 /* Enable CL37 1G Parallel Detect */
3786                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3787                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3788         }
3789         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3790              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3791             (vars->line_speed ==  SPEED_10000)) {
3792                 /* Check adding advertisement for 10G KR */
3793                 an_adv |= (1<<7);
3794                 /* Enable 10G Parallel Detect */
3795                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3796                                   MDIO_AER_BLOCK_AER_REG, 0);
3797
3798                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3799                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3800                 bnx2x_set_aer_mmd(params, phy);
3801                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3802         }
3803
3804         /* Set Transmit PMD settings */
3805         lane = bnx2x_get_warpcore_lane(phy, params);
3806         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3807                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3808                          WC_TX_DRIVER(0x02, 0x06, 0x09));
3809         /* Configure the next lane if dual mode */
3810         if (phy->flags & FLAGS_WC_DUAL_MODE)
3811                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3812                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3813                                  WC_TX_DRIVER(0x02, 0x06, 0x09));
3814         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3815                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3816                          0x03f0);
3817         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3818                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3819                          0x03f0);
3820
3821         /* Advertised speeds */
3822         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3823                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3824
3825         /* Advertised and set FEC (Forward Error Correction) */
3826         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3827                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3828                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3829                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3830
3831         /* Enable CL37 BAM */
3832         if (REG_RD(bp, params->shmem_base +
3833                    offsetof(struct shmem_region, dev_info.
3834                             port_hw_config[params->port].default_cfg)) &
3835             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3836                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3837                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3838                                          1);
3839                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3840         }
3841
3842         /* Advertise pause */
3843         bnx2x_ext_phy_set_pause(params, phy, vars);
3844         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3845         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3846                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3847
3848         /* Over 1G - AN local device user page 1 */
3849         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3850                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3851
3852         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3853              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3854             (phy->req_line_speed == SPEED_20000)) {
3855
3856                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3857                                   MDIO_AER_BLOCK_AER_REG, lane);
3858
3859                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3860                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3861                                          (1<<11));
3862
3863                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3864                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3865                 bnx2x_set_aer_mmd(params, phy);
3866
3867                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3868         } else {
3869                 bnx2x_disable_kr2(params, vars, phy);
3870         }
3871
3872         /* Enable Autoneg: only on the main lane */
3873         bnx2x_warpcore_restart_AN_KR(phy, params);
3874 }
3875
3876 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3877                                       struct link_params *params,
3878                                       struct link_vars *vars)
3879 {
3880         struct bnx2x *bp = params->bp;
3881         u16 val16, i, lane;
3882         static struct bnx2x_reg_set reg_set[] = {
3883                 /* Disable Autoneg */
3884                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3885                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3886                         0x3f00},
3887                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3888                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3889                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3890                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3891                 /* Leave cl72 training enable, needed for KR */
3892                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3893         };
3894
3895         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3896                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3897                                  reg_set[i].val);
3898
3899         lane = bnx2x_get_warpcore_lane(phy, params);
3900         /* Global registers */
3901         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3902                           MDIO_AER_BLOCK_AER_REG, 0);
3903         /* Disable CL36 PCS Tx */
3904         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3905                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3906         val16 &= ~(0x0011 << lane);
3907         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3908                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3909
3910         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3911                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3912         val16 |= (0x0303 << (lane << 1));
3913         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3914                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3915         /* Restore AER */
3916         bnx2x_set_aer_mmd(params, phy);
3917         /* Set speed via PMA/PMD register */
3918         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3919                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3920
3921         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3922                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3923
3924         /* Enable encoded forced speed */
3925         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3926                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3927
3928         /* Turn TX scramble payload only the 64/66 scrambler */
3929         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3930                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3931
3932         /* Turn RX scramble payload only the 64/66 scrambler */
3933         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3934                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3935
3936         /* Set and clear loopback to cause a reset to 64/66 decoder */
3937         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3938                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3939         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3940                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3941
3942 }
3943
3944 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3945                                        struct link_params *params,
3946                                        u8 is_xfi)
3947 {
3948         struct bnx2x *bp = params->bp;
3949         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3950         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3951
3952         /* Hold rxSeqStart */
3953         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3954                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3955
3956         /* Hold tx_fifo_reset */
3957         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3958                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3959
3960         /* Disable CL73 AN */
3961         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3962
3963         /* Disable 100FX Enable and Auto-Detect */
3964         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3965                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3966
3967         /* Disable 100FX Idle detect */
3968         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3969                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3970
3971         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3972         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3973                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3974
3975         /* Turn off auto-detect & fiber mode */
3976         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3977                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3978                                   0xFFEE);
3979
3980         /* Set filter_force_link, disable_false_link and parallel_detect */
3981         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3982                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3983         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3984                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3985                          ((val | 0x0006) & 0xFFFE));
3986
3987         /* Set XFI / SFI */
3988         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3989                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
3990
3991         misc1_val &= ~(0x1f);
3992
3993         if (is_xfi) {
3994                 misc1_val |= 0x5;
3995                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
3996                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
3997         } else {
3998                 cfg_tap_val = REG_RD(bp, params->shmem_base +
3999                                      offsetof(struct shmem_region, dev_info.
4000                                               port_hw_config[params->port].
4001                                               sfi_tap_values));
4002
4003                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4004
4005                 tx_drv_brdct = (cfg_tap_val &
4006                                 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4007                                PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4008
4009                 misc1_val |= 0x9;
4010
4011                 /* TAP values are controlled by nvram, if value there isn't 0 */
4012                 if (tx_equal)
4013                         tap_val = (u16)tx_equal;
4014                 else
4015                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4016
4017                 if (tx_drv_brdct)
4018                         tx_driver_val = WC_TX_DRIVER(0x03, (u16)tx_drv_brdct,
4019                                                      0x06);
4020                 else
4021                         tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
4022         }
4023         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4024                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4025
4026         /* Set Transmit PMD settings */
4027         lane = bnx2x_get_warpcore_lane(phy, params);
4028         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4029                          MDIO_WC_REG_TX_FIR_TAP,
4030                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4031         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4032                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4033                          tx_driver_val);
4034
4035         /* Enable fiber mode, enable and invert sig_det */
4036         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4037                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4038
4039         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4040         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4041                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4042
4043         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4044
4045         /* 10G XFI Full Duplex */
4046         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4047                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4048
4049         /* Release tx_fifo_reset */
4050         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4051                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4052                                   0xFFFE);
4053         /* Release rxSeqStart */
4054         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4055                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4056 }
4057
4058 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4059                                              struct link_params *params)
4060 {
4061         u16 val;
4062         struct bnx2x *bp = params->bp;
4063         /* Set global registers, so set AER lane to 0 */
4064         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4065                           MDIO_AER_BLOCK_AER_REG, 0);
4066
4067         /* Disable sequencer */
4068         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4069                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4070
4071         bnx2x_set_aer_mmd(params, phy);
4072
4073         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4074                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4075         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4076                          MDIO_AN_REG_CTRL, 0);
4077         /* Turn off CL73 */
4078         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4079                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4080         val &= ~(1<<5);
4081         val |= (1<<6);
4082         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4083                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4084
4085         /* Set 20G KR2 force speed */
4086         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4087                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4088
4089         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4090                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4091
4092         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4093                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4094         val &= ~(3<<14);
4095         val |= (1<<15);
4096         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4097                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4098         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4099                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4100
4101         /* Enable sequencer (over lane 0) */
4102         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4103                           MDIO_AER_BLOCK_AER_REG, 0);
4104
4105         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4106                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4107
4108         bnx2x_set_aer_mmd(params, phy);
4109 }
4110
4111 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4112                                          struct bnx2x_phy *phy,
4113                                          u16 lane)
4114 {
4115         /* Rx0 anaRxControl1G */
4116         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4117                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4118
4119         /* Rx2 anaRxControl1G */
4120         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4121                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4122
4123         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4124                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4125
4126         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4127                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4128
4129         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4130                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4131
4132         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4133                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4134
4135         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4136                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4137
4138         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4139                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4140
4141         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4142                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4143
4144         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4145                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4146
4147         /* Serdes Digital Misc1 */
4148         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4149                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4150
4151         /* Serdes Digital4 Misc3 */
4152         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4153                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4154
4155         /* Set Transmit PMD settings */
4156         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4157                          MDIO_WC_REG_TX_FIR_TAP,
4158                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4159                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4160         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4161                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4162                          WC_TX_DRIVER(0x02, 0x02, 0x02));
4163 }
4164
4165 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4166                                            struct link_params *params,
4167                                            u8 fiber_mode,
4168                                            u8 always_autoneg)
4169 {
4170         struct bnx2x *bp = params->bp;
4171         u16 val16, digctrl_kx1, digctrl_kx2;
4172
4173         /* Clear XFI clock comp in non-10G single lane mode. */
4174         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4175                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4176
4177         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4178
4179         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4180                 /* SGMII Autoneg */
4181                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4182                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4183                                          0x1000);
4184                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4185         } else {
4186                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4187                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4188                 val16 &= 0xcebf;
4189                 switch (phy->req_line_speed) {
4190                 case SPEED_10:
4191                         break;
4192                 case SPEED_100:
4193                         val16 |= 0x2000;
4194                         break;
4195                 case SPEED_1000:
4196                         val16 |= 0x0040;
4197                         break;
4198                 default:
4199                         DP(NETIF_MSG_LINK,
4200                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4201                         return;
4202                 }
4203
4204                 if (phy->req_duplex == DUPLEX_FULL)
4205                         val16 |= 0x0100;
4206
4207                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4208                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4209
4210                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4211                                phy->req_line_speed);
4212                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4213                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4214                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4215         }
4216
4217         /* SGMII Slave mode and disable signal detect */
4218         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4219                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4220         if (fiber_mode)
4221                 digctrl_kx1 = 1;
4222         else
4223                 digctrl_kx1 &= 0xff4a;
4224
4225         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4226                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4227                         digctrl_kx1);
4228
4229         /* Turn off parallel detect */
4230         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4231                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4232         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4233                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4234                         (digctrl_kx2 & ~(1<<2)));
4235
4236         /* Re-enable parallel detect */
4237         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4238                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4239                         (digctrl_kx2 | (1<<2)));
4240
4241         /* Enable autodet */
4242         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4243                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4244                         (digctrl_kx1 | 0x10));
4245 }
4246
4247 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4248                                       struct bnx2x_phy *phy,
4249                                       u8 reset)
4250 {
4251         u16 val;
4252         /* Take lane out of reset after configuration is finished */
4253         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4254                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4255         if (reset)
4256                 val |= 0xC000;
4257         else
4258                 val &= 0x3FFF;
4259         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4260                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4261         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4262                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4263 }
4264 /* Clear SFI/XFI link settings registers */
4265 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4266                                       struct link_params *params,
4267                                       u16 lane)
4268 {
4269         struct bnx2x *bp = params->bp;
4270         u16 i;
4271         static struct bnx2x_reg_set wc_regs[] = {
4272                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4273                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4274                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4275                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4276                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4277                         0x0195},
4278                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4279                         0x0007},
4280                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4281                         0x0002},
4282                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4283                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4284                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4285                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4286         };
4287         /* Set XFI clock comp as default. */
4288         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4289                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4290
4291         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4292                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4293                                  wc_regs[i].val);
4294
4295         lane = bnx2x_get_warpcore_lane(phy, params);
4296         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4297                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4298
4299 }
4300
4301 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4302                                                 u32 chip_id,
4303                                                 u32 shmem_base, u8 port,
4304                                                 u8 *gpio_num, u8 *gpio_port)
4305 {
4306         u32 cfg_pin;
4307         *gpio_num = 0;
4308         *gpio_port = 0;
4309         if (CHIP_IS_E3(bp)) {
4310                 cfg_pin = (REG_RD(bp, shmem_base +
4311                                 offsetof(struct shmem_region,
4312                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4313                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4314                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4315
4316                 /* Should not happen. This function called upon interrupt
4317                  * triggered by GPIO ( since EPIO can only generate interrupts
4318                  * to MCP).
4319                  * So if this function was called and none of the GPIOs was set,
4320                  * it means the shit hit the fan.
4321                  */
4322                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4323                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4324                         DP(NETIF_MSG_LINK,
4325                            "No cfg pin %x for module detect indication\n",
4326                            cfg_pin);
4327                         return -EINVAL;
4328                 }
4329
4330                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4331                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4332         } else {
4333                 *gpio_num = MISC_REGISTERS_GPIO_3;
4334                 *gpio_port = port;
4335         }
4336
4337         return 0;
4338 }
4339
4340 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4341                                        struct link_params *params)
4342 {
4343         struct bnx2x *bp = params->bp;
4344         u8 gpio_num, gpio_port;
4345         u32 gpio_val;
4346         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4347                                       params->shmem_base, params->port,
4348                                       &gpio_num, &gpio_port) != 0)
4349                 return 0;
4350         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4351
4352         /* Call the handling function in case module is detected */
4353         if (gpio_val == 0)
4354                 return 1;
4355         else
4356                 return 0;
4357 }
4358 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4359                                      struct link_params *params)
4360 {
4361         u16 gp2_status_reg0, lane;
4362         struct bnx2x *bp = params->bp;
4363
4364         lane = bnx2x_get_warpcore_lane(phy, params);
4365
4366         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4367                                  &gp2_status_reg0);
4368
4369         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4370 }
4371
4372 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4373                                           struct link_params *params,
4374                                           struct link_vars *vars)
4375 {
4376         struct bnx2x *bp = params->bp;
4377         u32 serdes_net_if;
4378         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4379
4380         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4381
4382         if (!vars->turn_to_run_wc_rt)
4383                 return;
4384
4385         if (vars->rx_tx_asic_rst) {
4386                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4387                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4388                                 offsetof(struct shmem_region, dev_info.
4389                                 port_hw_config[params->port].default_cfg)) &
4390                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4391
4392                 switch (serdes_net_if) {
4393                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4394                         /* Do we get link yet? */
4395                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4396                                         &gp_status1);
4397                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4398                                 /*10G KR*/
4399                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4400
4401                         if (lnkup_kr || lnkup) {
4402                                 vars->rx_tx_asic_rst = 0;
4403                         } else {
4404                                 /* Reset the lane to see if link comes up.*/
4405                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4406                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4407
4408                                 /* Restart Autoneg */
4409                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4410                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4411
4412                                 vars->rx_tx_asic_rst--;
4413                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4414                                 vars->rx_tx_asic_rst);
4415                         }
4416                         break;
4417
4418                 default:
4419                         break;
4420                 }
4421
4422         } /*params->rx_tx_asic_rst*/
4423
4424 }
4425 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4426                                       struct link_params *params)
4427 {
4428         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4429         struct bnx2x *bp = params->bp;
4430         bnx2x_warpcore_clear_regs(phy, params, lane);
4431         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4432              SPEED_10000) &&
4433             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4434                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4435                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4436         } else {
4437                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4438                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4439         }
4440 }
4441
4442 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4443                                          struct bnx2x_phy *phy,
4444                                          u8 tx_en)
4445 {
4446         struct bnx2x *bp = params->bp;
4447         u32 cfg_pin;
4448         u8 port = params->port;
4449
4450         cfg_pin = REG_RD(bp, params->shmem_base +
4451                          offsetof(struct shmem_region,
4452                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4453                 PORT_HW_CFG_E3_TX_LASER_MASK;
4454         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4455         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4456
4457         /* For 20G, the expected pin to be used is 3 pins after the current */
4458         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4459         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4460                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4461 }
4462
4463 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4464                                        struct link_params *params,
4465                                        struct link_vars *vars)
4466 {
4467         struct bnx2x *bp = params->bp;
4468         u32 serdes_net_if;
4469         u8 fiber_mode;
4470         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4471         serdes_net_if = (REG_RD(bp, params->shmem_base +
4472                          offsetof(struct shmem_region, dev_info.
4473                                   port_hw_config[params->port].default_cfg)) &
4474                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4475         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4476                            "serdes_net_if = 0x%x\n",
4477                        vars->line_speed, serdes_net_if);
4478         bnx2x_set_aer_mmd(params, phy);
4479         bnx2x_warpcore_reset_lane(bp, phy, 1);
4480         vars->phy_flags |= PHY_XGXS_FLAG;
4481         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4482             (phy->req_line_speed &&
4483              ((phy->req_line_speed == SPEED_100) ||
4484               (phy->req_line_speed == SPEED_10)))) {
4485                 vars->phy_flags |= PHY_SGMII_FLAG;
4486                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4487                 bnx2x_warpcore_clear_regs(phy, params, lane);
4488                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4489         } else {
4490                 switch (serdes_net_if) {
4491                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4492                         /* Enable KR Auto Neg */
4493                         if (params->loopback_mode != LOOPBACK_EXT)
4494                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4495                         else {
4496                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4497                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4498                         }
4499                         break;
4500
4501                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4502                         bnx2x_warpcore_clear_regs(phy, params, lane);
4503                         if (vars->line_speed == SPEED_10000) {
4504                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4505                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4506                         } else {
4507                                 if (SINGLE_MEDIA_DIRECT(params)) {
4508                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4509                                         fiber_mode = 1;
4510                                 } else {
4511                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4512                                         fiber_mode = 0;
4513                                 }
4514                                 bnx2x_warpcore_set_sgmii_speed(phy,
4515                                                                 params,
4516                                                                 fiber_mode,
4517                                                                 0);
4518                         }
4519
4520                         break;
4521
4522                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4523                         /* Issue Module detection if module is plugged, or
4524                          * enabled transmitter to avoid current leakage in case
4525                          * no module is connected
4526                          */
4527                         if ((params->loopback_mode == LOOPBACK_NONE) ||
4528                             (params->loopback_mode == LOOPBACK_EXT)) {
4529                                 if (bnx2x_is_sfp_module_plugged(phy, params))
4530                                         bnx2x_sfp_module_detection(phy, params);
4531                                 else
4532                                         bnx2x_sfp_e3_set_transmitter(params,
4533                                                                      phy, 1);
4534                         }
4535
4536                         bnx2x_warpcore_config_sfi(phy, params);
4537                         break;
4538
4539                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4540                         if (vars->line_speed != SPEED_20000) {
4541                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4542                                 return;
4543                         }
4544                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4545                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4546                         /* Issue Module detection */
4547
4548                         bnx2x_sfp_module_detection(phy, params);
4549                         break;
4550                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4551                         if (!params->loopback_mode) {
4552                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4553                         } else {
4554                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4555                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4556                         }
4557                         break;
4558                 default:
4559                         DP(NETIF_MSG_LINK,
4560                            "Unsupported Serdes Net Interface 0x%x\n",
4561                            serdes_net_if);
4562                         return;
4563                 }
4564         }
4565
4566         /* Take lane out of reset after configuration is finished */
4567         bnx2x_warpcore_reset_lane(bp, phy, 0);
4568         DP(NETIF_MSG_LINK, "Exit config init\n");
4569 }
4570
4571 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4572                                       struct link_params *params)
4573 {
4574         struct bnx2x *bp = params->bp;
4575         u16 val16, lane;
4576         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4577         bnx2x_set_mdio_emac_per_phy(bp, params);
4578         bnx2x_set_aer_mmd(params, phy);
4579         /* Global register */
4580         bnx2x_warpcore_reset_lane(bp, phy, 1);
4581
4582         /* Clear loopback settings (if any) */
4583         /* 10G & 20G */
4584         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4585                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4586
4587         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4588                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4589
4590         /* Update those 1-copy registers */
4591         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4592                           MDIO_AER_BLOCK_AER_REG, 0);
4593         /* Enable 1G MDIO (1-copy) */
4594         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4595                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4596                                   ~0x10);
4597
4598         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4599                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4600         lane = bnx2x_get_warpcore_lane(phy, params);
4601         /* Disable CL36 PCS Tx */
4602         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4603                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4604         val16 |= (0x11 << lane);
4605         if (phy->flags & FLAGS_WC_DUAL_MODE)
4606                 val16 |= (0x22 << lane);
4607         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4608                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4609
4610         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4611                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4612         val16 &= ~(0x0303 << (lane << 1));
4613         val16 |= (0x0101 << (lane << 1));
4614         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4615                 val16 &= ~(0x0c0c << (lane << 1));
4616                 val16 |= (0x0404 << (lane << 1));
4617         }
4618
4619         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4620                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4621         /* Restore AER */
4622         bnx2x_set_aer_mmd(params, phy);
4623
4624 }
4625
4626 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4627                                         struct link_params *params)
4628 {
4629         struct bnx2x *bp = params->bp;
4630         u16 val16;
4631         u32 lane;
4632         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4633                        params->loopback_mode, phy->req_line_speed);
4634
4635         if (phy->req_line_speed < SPEED_10000 ||
4636             phy->supported & SUPPORTED_20000baseKR2_Full) {
4637                 /* 10/100/1000/20G-KR2 */
4638
4639                 /* Update those 1-copy registers */
4640                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4641                                   MDIO_AER_BLOCK_AER_REG, 0);
4642                 /* Enable 1G MDIO (1-copy) */
4643                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4644                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4645                                          0x10);
4646                 /* Set 1G loopback based on lane (1-copy) */
4647                 lane = bnx2x_get_warpcore_lane(phy, params);
4648                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4649                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4650                 val16 |= (1<<lane);
4651                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4652                         val16 |= (2<<lane);
4653                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4654                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4655                                  val16);
4656
4657                 /* Switch back to 4-copy registers */
4658                 bnx2x_set_aer_mmd(params, phy);
4659         } else {
4660                 /* 10G / 20G-DXGXS */
4661                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4662                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4663                                          0x4000);
4664                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4665                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4666         }
4667 }
4668
4669
4670
4671 static void bnx2x_sync_link(struct link_params *params,
4672                              struct link_vars *vars)
4673 {
4674         struct bnx2x *bp = params->bp;
4675         u8 link_10g_plus;
4676         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4677                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4678         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4679         if (vars->link_up) {
4680                 DP(NETIF_MSG_LINK, "phy link up\n");
4681
4682                 vars->phy_link_up = 1;
4683                 vars->duplex = DUPLEX_FULL;
4684                 switch (vars->link_status &
4685                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4686                 case LINK_10THD:
4687                         vars->duplex = DUPLEX_HALF;
4688                         /* Fall thru */
4689                 case LINK_10TFD:
4690                         vars->line_speed = SPEED_10;
4691                         break;
4692
4693                 case LINK_100TXHD:
4694                         vars->duplex = DUPLEX_HALF;
4695                         /* Fall thru */
4696                 case LINK_100T4:
4697                 case LINK_100TXFD:
4698                         vars->line_speed = SPEED_100;
4699                         break;
4700
4701                 case LINK_1000THD:
4702                         vars->duplex = DUPLEX_HALF;
4703                         /* Fall thru */
4704                 case LINK_1000TFD:
4705                         vars->line_speed = SPEED_1000;
4706                         break;
4707
4708                 case LINK_2500THD:
4709                         vars->duplex = DUPLEX_HALF;
4710                         /* Fall thru */
4711                 case LINK_2500TFD:
4712                         vars->line_speed = SPEED_2500;
4713                         break;
4714
4715                 case LINK_10GTFD:
4716                         vars->line_speed = SPEED_10000;
4717                         break;
4718                 case LINK_20GTFD:
4719                         vars->line_speed = SPEED_20000;
4720                         break;
4721                 default:
4722                         break;
4723                 }
4724                 vars->flow_ctrl = 0;
4725                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4726                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4727
4728                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4729                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4730
4731                 if (!vars->flow_ctrl)
4732                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4733
4734                 if (vars->line_speed &&
4735                     ((vars->line_speed == SPEED_10) ||
4736                      (vars->line_speed == SPEED_100))) {
4737                         vars->phy_flags |= PHY_SGMII_FLAG;
4738                 } else {
4739                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4740                 }
4741                 if (vars->line_speed &&
4742                     USES_WARPCORE(bp) &&
4743                     (vars->line_speed == SPEED_1000))
4744                         vars->phy_flags |= PHY_SGMII_FLAG;
4745                 /* Anything 10 and over uses the bmac */
4746                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4747
4748                 if (link_10g_plus) {
4749                         if (USES_WARPCORE(bp))
4750                                 vars->mac_type = MAC_TYPE_XMAC;
4751                         else
4752                                 vars->mac_type = MAC_TYPE_BMAC;
4753                 } else {
4754                         if (USES_WARPCORE(bp))
4755                                 vars->mac_type = MAC_TYPE_UMAC;
4756                         else
4757                                 vars->mac_type = MAC_TYPE_EMAC;
4758                 }
4759         } else { /* Link down */
4760                 DP(NETIF_MSG_LINK, "phy link down\n");
4761
4762                 vars->phy_link_up = 0;
4763
4764                 vars->line_speed = 0;
4765                 vars->duplex = DUPLEX_FULL;
4766                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4767
4768                 /* Indicate no mac active */
4769                 vars->mac_type = MAC_TYPE_NONE;
4770                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4771                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4772                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4773                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4774         }
4775 }
4776
4777 void bnx2x_link_status_update(struct link_params *params,
4778                               struct link_vars *vars)
4779 {
4780         struct bnx2x *bp = params->bp;
4781         u8 port = params->port;
4782         u32 sync_offset, media_types;
4783         /* Update PHY configuration */
4784         set_phy_vars(params, vars);
4785
4786         vars->link_status = REG_RD(bp, params->shmem_base +
4787                                    offsetof(struct shmem_region,
4788                                             port_mb[port].link_status));
4789
4790         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4791         if (params->loopback_mode != LOOPBACK_NONE &&
4792             params->loopback_mode != LOOPBACK_EXT)
4793                 vars->link_status |= LINK_STATUS_LINK_UP;
4794
4795         if (bnx2x_eee_has_cap(params))
4796                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4797                                           offsetof(struct shmem2_region,
4798                                                    eee_status[params->port]));
4799
4800         vars->phy_flags = PHY_XGXS_FLAG;
4801         bnx2x_sync_link(params, vars);
4802         /* Sync media type */
4803         sync_offset = params->shmem_base +
4804                         offsetof(struct shmem_region,
4805                                  dev_info.port_hw_config[port].media_type);
4806         media_types = REG_RD(bp, sync_offset);
4807
4808         params->phy[INT_PHY].media_type =
4809                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4810                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4811         params->phy[EXT_PHY1].media_type =
4812                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4813                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4814         params->phy[EXT_PHY2].media_type =
4815                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4816                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4817         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4818
4819         /* Sync AEU offset */
4820         sync_offset = params->shmem_base +
4821                         offsetof(struct shmem_region,
4822                                  dev_info.port_hw_config[port].aeu_int_mask);
4823
4824         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4825
4826         /* Sync PFC status */
4827         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4828                 params->feature_config_flags |=
4829                                         FEATURE_CONFIG_PFC_ENABLED;
4830         else
4831                 params->feature_config_flags &=
4832                                         ~FEATURE_CONFIG_PFC_ENABLED;
4833
4834         if (SHMEM2_HAS(bp, link_attr_sync))
4835                 vars->link_attr_sync = SHMEM2_RD(bp,
4836                                                  link_attr_sync[params->port]);
4837
4838         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4839                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4840         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4841                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4842 }
4843
4844 static void bnx2x_set_master_ln(struct link_params *params,
4845                                 struct bnx2x_phy *phy)
4846 {
4847         struct bnx2x *bp = params->bp;
4848         u16 new_master_ln, ser_lane;
4849         ser_lane = ((params->lane_config &
4850                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4851                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4852
4853         /* Set the master_ln for AN */
4854         CL22_RD_OVER_CL45(bp, phy,
4855                           MDIO_REG_BANK_XGXS_BLOCK2,
4856                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4857                           &new_master_ln);
4858
4859         CL22_WR_OVER_CL45(bp, phy,
4860                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4861                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4862                           (new_master_ln | ser_lane));
4863 }
4864
4865 static int bnx2x_reset_unicore(struct link_params *params,
4866                                struct bnx2x_phy *phy,
4867                                u8 set_serdes)
4868 {
4869         struct bnx2x *bp = params->bp;
4870         u16 mii_control;
4871         u16 i;
4872         CL22_RD_OVER_CL45(bp, phy,
4873                           MDIO_REG_BANK_COMBO_IEEE0,
4874                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4875
4876         /* Reset the unicore */
4877         CL22_WR_OVER_CL45(bp, phy,
4878                           MDIO_REG_BANK_COMBO_IEEE0,
4879                           MDIO_COMBO_IEEE0_MII_CONTROL,
4880                           (mii_control |
4881                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4882         if (set_serdes)
4883                 bnx2x_set_serdes_access(bp, params->port);
4884
4885         /* Wait for the reset to self clear */
4886         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4887                 udelay(5);
4888
4889                 /* The reset erased the previous bank value */
4890                 CL22_RD_OVER_CL45(bp, phy,
4891                                   MDIO_REG_BANK_COMBO_IEEE0,
4892                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4893                                   &mii_control);
4894
4895                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4896                         udelay(5);
4897                         return 0;
4898                 }
4899         }
4900
4901         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4902                               " Port %d\n",
4903                          params->port);
4904         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4905         return -EINVAL;
4906
4907 }
4908
4909 static void bnx2x_set_swap_lanes(struct link_params *params,
4910                                  struct bnx2x_phy *phy)
4911 {
4912         struct bnx2x *bp = params->bp;
4913         /* Each two bits represents a lane number:
4914          * No swap is 0123 => 0x1b no need to enable the swap
4915          */
4916         u16 rx_lane_swap, tx_lane_swap;
4917
4918         rx_lane_swap = ((params->lane_config &
4919                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4920                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4921         tx_lane_swap = ((params->lane_config &
4922                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4923                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4924
4925         if (rx_lane_swap != 0x1b) {
4926                 CL22_WR_OVER_CL45(bp, phy,
4927                                   MDIO_REG_BANK_XGXS_BLOCK2,
4928                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4929                                   (rx_lane_swap |
4930                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4931                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4932         } else {
4933                 CL22_WR_OVER_CL45(bp, phy,
4934                                   MDIO_REG_BANK_XGXS_BLOCK2,
4935                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4936         }
4937
4938         if (tx_lane_swap != 0x1b) {
4939                 CL22_WR_OVER_CL45(bp, phy,
4940                                   MDIO_REG_BANK_XGXS_BLOCK2,
4941                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4942                                   (tx_lane_swap |
4943                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4944         } else {
4945                 CL22_WR_OVER_CL45(bp, phy,
4946                                   MDIO_REG_BANK_XGXS_BLOCK2,
4947                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4948         }
4949 }
4950
4951 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4952                                          struct link_params *params)
4953 {
4954         struct bnx2x *bp = params->bp;
4955         u16 control2;
4956         CL22_RD_OVER_CL45(bp, phy,
4957                           MDIO_REG_BANK_SERDES_DIGITAL,
4958                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4959                           &control2);
4960         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4961                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4962         else
4963                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4964         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4965                 phy->speed_cap_mask, control2);
4966         CL22_WR_OVER_CL45(bp, phy,
4967                           MDIO_REG_BANK_SERDES_DIGITAL,
4968                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4969                           control2);
4970
4971         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
4972              (phy->speed_cap_mask &
4973                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
4974                 DP(NETIF_MSG_LINK, "XGXS\n");
4975
4976                 CL22_WR_OVER_CL45(bp, phy,
4977                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
4978                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
4979                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
4980
4981                 CL22_RD_OVER_CL45(bp, phy,
4982                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4983                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4984                                   &control2);
4985
4986
4987                 control2 |=
4988                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
4989
4990                 CL22_WR_OVER_CL45(bp, phy,
4991                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
4992                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
4993                                   control2);
4994
4995                 /* Disable parallel detection of HiG */
4996                 CL22_WR_OVER_CL45(bp, phy,
4997                                   MDIO_REG_BANK_XGXS_BLOCK2,
4998                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
4999                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5000                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5001         }
5002 }
5003
5004 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5005                               struct link_params *params,
5006                               struct link_vars *vars,
5007                               u8 enable_cl73)
5008 {
5009         struct bnx2x *bp = params->bp;
5010         u16 reg_val;
5011
5012         /* CL37 Autoneg */
5013         CL22_RD_OVER_CL45(bp, phy,
5014                           MDIO_REG_BANK_COMBO_IEEE0,
5015                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5016
5017         /* CL37 Autoneg Enabled */
5018         if (vars->line_speed == SPEED_AUTO_NEG)
5019                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5020         else /* CL37 Autoneg Disabled */
5021                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5022                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5023
5024         CL22_WR_OVER_CL45(bp, phy,
5025                           MDIO_REG_BANK_COMBO_IEEE0,
5026                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5027
5028         /* Enable/Disable Autodetection */
5029
5030         CL22_RD_OVER_CL45(bp, phy,
5031                           MDIO_REG_BANK_SERDES_DIGITAL,
5032                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5033         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5034                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5035         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5036         if (vars->line_speed == SPEED_AUTO_NEG)
5037                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5038         else
5039                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5040
5041         CL22_WR_OVER_CL45(bp, phy,
5042                           MDIO_REG_BANK_SERDES_DIGITAL,
5043                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5044
5045         /* Enable TetonII and BAM autoneg */
5046         CL22_RD_OVER_CL45(bp, phy,
5047                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5048                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5049                           &reg_val);
5050         if (vars->line_speed == SPEED_AUTO_NEG) {
5051                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5052                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5053                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5054         } else {
5055                 /* TetonII and BAM Autoneg Disabled */
5056                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5057                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5058         }
5059         CL22_WR_OVER_CL45(bp, phy,
5060                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5061                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5062                           reg_val);
5063
5064         if (enable_cl73) {
5065                 /* Enable Cl73 FSM status bits */
5066                 CL22_WR_OVER_CL45(bp, phy,
5067                                   MDIO_REG_BANK_CL73_USERB0,
5068                                   MDIO_CL73_USERB0_CL73_UCTRL,
5069                                   0xe);
5070
5071                 /* Enable BAM Station Manager*/
5072                 CL22_WR_OVER_CL45(bp, phy,
5073                         MDIO_REG_BANK_CL73_USERB0,
5074                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5075                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5076                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5077                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5078
5079                 /* Advertise CL73 link speeds */
5080                 CL22_RD_OVER_CL45(bp, phy,
5081                                   MDIO_REG_BANK_CL73_IEEEB1,
5082                                   MDIO_CL73_IEEEB1_AN_ADV2,
5083                                   &reg_val);
5084                 if (phy->speed_cap_mask &
5085                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5086                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5087                 if (phy->speed_cap_mask &
5088                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5089                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5090
5091                 CL22_WR_OVER_CL45(bp, phy,
5092                                   MDIO_REG_BANK_CL73_IEEEB1,
5093                                   MDIO_CL73_IEEEB1_AN_ADV2,
5094                                   reg_val);
5095
5096                 /* CL73 Autoneg Enabled */
5097                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5098
5099         } else /* CL73 Autoneg Disabled */
5100                 reg_val = 0;
5101
5102         CL22_WR_OVER_CL45(bp, phy,
5103                           MDIO_REG_BANK_CL73_IEEEB0,
5104                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5105 }
5106
5107 /* Program SerDes, forced speed */
5108 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5109                                  struct link_params *params,
5110                                  struct link_vars *vars)
5111 {
5112         struct bnx2x *bp = params->bp;
5113         u16 reg_val;
5114
5115         /* Program duplex, disable autoneg and sgmii*/
5116         CL22_RD_OVER_CL45(bp, phy,
5117                           MDIO_REG_BANK_COMBO_IEEE0,
5118                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5119         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5120                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5121                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5122         if (phy->req_duplex == DUPLEX_FULL)
5123                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5124         CL22_WR_OVER_CL45(bp, phy,
5125                           MDIO_REG_BANK_COMBO_IEEE0,
5126                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5127
5128         /* Program speed
5129          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5130          */
5131         CL22_RD_OVER_CL45(bp, phy,
5132                           MDIO_REG_BANK_SERDES_DIGITAL,
5133                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5134         /* Clearing the speed value before setting the right speed */
5135         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5136
5137         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5138                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5139
5140         if (!((vars->line_speed == SPEED_1000) ||
5141               (vars->line_speed == SPEED_100) ||
5142               (vars->line_speed == SPEED_10))) {
5143
5144                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5145                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5146                 if (vars->line_speed == SPEED_10000)
5147                         reg_val |=
5148                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5149         }
5150
5151         CL22_WR_OVER_CL45(bp, phy,
5152                           MDIO_REG_BANK_SERDES_DIGITAL,
5153                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5154
5155 }
5156
5157 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5158                                               struct link_params *params)
5159 {
5160         struct bnx2x *bp = params->bp;
5161         u16 val = 0;
5162
5163         /* Set extended capabilities */
5164         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5165                 val |= MDIO_OVER_1G_UP1_2_5G;
5166         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5167                 val |= MDIO_OVER_1G_UP1_10G;
5168         CL22_WR_OVER_CL45(bp, phy,
5169                           MDIO_REG_BANK_OVER_1G,
5170                           MDIO_OVER_1G_UP1, val);
5171
5172         CL22_WR_OVER_CL45(bp, phy,
5173                           MDIO_REG_BANK_OVER_1G,
5174                           MDIO_OVER_1G_UP3, 0x400);
5175 }
5176
5177 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5178                                               struct link_params *params,
5179                                               u16 ieee_fc)
5180 {
5181         struct bnx2x *bp = params->bp;
5182         u16 val;
5183         /* For AN, we are always publishing full duplex */
5184
5185         CL22_WR_OVER_CL45(bp, phy,
5186                           MDIO_REG_BANK_COMBO_IEEE0,
5187                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5188         CL22_RD_OVER_CL45(bp, phy,
5189                           MDIO_REG_BANK_CL73_IEEEB1,
5190                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5191         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5192         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5193         CL22_WR_OVER_CL45(bp, phy,
5194                           MDIO_REG_BANK_CL73_IEEEB1,
5195                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5196 }
5197
5198 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5199                                   struct link_params *params,
5200                                   u8 enable_cl73)
5201 {
5202         struct bnx2x *bp = params->bp;
5203         u16 mii_control;
5204
5205         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5206         /* Enable and restart BAM/CL37 aneg */
5207
5208         if (enable_cl73) {
5209                 CL22_RD_OVER_CL45(bp, phy,
5210                                   MDIO_REG_BANK_CL73_IEEEB0,
5211                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5212                                   &mii_control);
5213
5214                 CL22_WR_OVER_CL45(bp, phy,
5215                                   MDIO_REG_BANK_CL73_IEEEB0,
5216                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5217                                   (mii_control |
5218                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5219                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5220         } else {
5221
5222                 CL22_RD_OVER_CL45(bp, phy,
5223                                   MDIO_REG_BANK_COMBO_IEEE0,
5224                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5225                                   &mii_control);
5226                 DP(NETIF_MSG_LINK,
5227                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5228                          mii_control);
5229                 CL22_WR_OVER_CL45(bp, phy,
5230                                   MDIO_REG_BANK_COMBO_IEEE0,
5231                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5232                                   (mii_control |
5233                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5234                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5235         }
5236 }
5237
5238 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5239                                            struct link_params *params,
5240                                            struct link_vars *vars)
5241 {
5242         struct bnx2x *bp = params->bp;
5243         u16 control1;
5244
5245         /* In SGMII mode, the unicore is always slave */
5246
5247         CL22_RD_OVER_CL45(bp, phy,
5248                           MDIO_REG_BANK_SERDES_DIGITAL,
5249                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5250                           &control1);
5251         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5252         /* Set sgmii mode (and not fiber) */
5253         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5254                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5255                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5256         CL22_WR_OVER_CL45(bp, phy,
5257                           MDIO_REG_BANK_SERDES_DIGITAL,
5258                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5259                           control1);
5260
5261         /* If forced speed */
5262         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5263                 /* Set speed, disable autoneg */
5264                 u16 mii_control;
5265
5266                 CL22_RD_OVER_CL45(bp, phy,
5267                                   MDIO_REG_BANK_COMBO_IEEE0,
5268                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5269                                   &mii_control);
5270                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5271                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5272                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5273
5274                 switch (vars->line_speed) {
5275                 case SPEED_100:
5276                         mii_control |=
5277                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5278                         break;
5279                 case SPEED_1000:
5280                         mii_control |=
5281                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5282                         break;
5283                 case SPEED_10:
5284                         /* There is nothing to set for 10M */
5285                         break;
5286                 default:
5287                         /* Invalid speed for SGMII */
5288                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5289                                   vars->line_speed);
5290                         break;
5291                 }
5292
5293                 /* Setting the full duplex */
5294                 if (phy->req_duplex == DUPLEX_FULL)
5295                         mii_control |=
5296                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5297                 CL22_WR_OVER_CL45(bp, phy,
5298                                   MDIO_REG_BANK_COMBO_IEEE0,
5299                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5300                                   mii_control);
5301
5302         } else { /* AN mode */
5303                 /* Enable and restart AN */
5304                 bnx2x_restart_autoneg(phy, params, 0);
5305         }
5306 }
5307
5308 /* Link management
5309  */
5310 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5311                                              struct link_params *params)
5312 {
5313         struct bnx2x *bp = params->bp;
5314         u16 pd_10g, status2_1000x;
5315         if (phy->req_line_speed != SPEED_AUTO_NEG)
5316                 return 0;
5317         CL22_RD_OVER_CL45(bp, phy,
5318                           MDIO_REG_BANK_SERDES_DIGITAL,
5319                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5320                           &status2_1000x);
5321         CL22_RD_OVER_CL45(bp, phy,
5322                           MDIO_REG_BANK_SERDES_DIGITAL,
5323                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5324                           &status2_1000x);
5325         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5326                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5327                          params->port);
5328                 return 1;
5329         }
5330
5331         CL22_RD_OVER_CL45(bp, phy,
5332                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5333                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5334                           &pd_10g);
5335
5336         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5337                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5338                          params->port);
5339                 return 1;
5340         }
5341         return 0;
5342 }
5343
5344 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5345                                 struct link_params *params,
5346                                 struct link_vars *vars,
5347                                 u32 gp_status)
5348 {
5349         u16 ld_pause;   /* local driver */
5350         u16 lp_pause;   /* link partner */
5351         u16 pause_result;
5352         struct bnx2x *bp = params->bp;
5353         if ((gp_status &
5354              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5355               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5356             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5357              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5358
5359                 CL22_RD_OVER_CL45(bp, phy,
5360                                   MDIO_REG_BANK_CL73_IEEEB1,
5361                                   MDIO_CL73_IEEEB1_AN_ADV1,
5362                                   &ld_pause);
5363                 CL22_RD_OVER_CL45(bp, phy,
5364                                   MDIO_REG_BANK_CL73_IEEEB1,
5365                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5366                                   &lp_pause);
5367                 pause_result = (ld_pause &
5368                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5369                 pause_result |= (lp_pause &
5370                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5371                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5372         } else {
5373                 CL22_RD_OVER_CL45(bp, phy,
5374                                   MDIO_REG_BANK_COMBO_IEEE0,
5375                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5376                                   &ld_pause);
5377                 CL22_RD_OVER_CL45(bp, phy,
5378                         MDIO_REG_BANK_COMBO_IEEE0,
5379                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5380                         &lp_pause);
5381                 pause_result = (ld_pause &
5382                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5383                 pause_result |= (lp_pause &
5384                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5385                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5386         }
5387         bnx2x_pause_resolve(vars, pause_result);
5388
5389 }
5390
5391 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5392                                     struct link_params *params,
5393                                     struct link_vars *vars,
5394                                     u32 gp_status)
5395 {
5396         struct bnx2x *bp = params->bp;
5397         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5398
5399         /* Resolve from gp_status in case of AN complete and not sgmii */
5400         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5401                 /* Update the advertised flow-controled of LD/LP in AN */
5402                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5403                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5404                 /* But set the flow-control result as the requested one */
5405                 vars->flow_ctrl = phy->req_flow_ctrl;
5406         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5407                 vars->flow_ctrl = params->req_fc_auto_adv;
5408         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5409                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5410                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5411                         vars->flow_ctrl = params->req_fc_auto_adv;
5412                         return;
5413                 }
5414                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5415         }
5416         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5417 }
5418
5419 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5420                                          struct link_params *params)
5421 {
5422         struct bnx2x *bp = params->bp;
5423         u16 rx_status, ustat_val, cl37_fsm_received;
5424         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5425         /* Step 1: Make sure signal is detected */
5426         CL22_RD_OVER_CL45(bp, phy,
5427                           MDIO_REG_BANK_RX0,
5428                           MDIO_RX0_RX_STATUS,
5429                           &rx_status);
5430         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5431             (MDIO_RX0_RX_STATUS_SIGDET)) {
5432                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5433                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5434                 CL22_WR_OVER_CL45(bp, phy,
5435                                   MDIO_REG_BANK_CL73_IEEEB0,
5436                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5437                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5438                 return;
5439         }
5440         /* Step 2: Check CL73 state machine */
5441         CL22_RD_OVER_CL45(bp, phy,
5442                           MDIO_REG_BANK_CL73_USERB0,
5443                           MDIO_CL73_USERB0_CL73_USTAT1,
5444                           &ustat_val);
5445         if ((ustat_val &
5446              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5447               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5448             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5449               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5450                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5451                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5452                 return;
5453         }
5454         /* Step 3: Check CL37 Message Pages received to indicate LP
5455          * supports only CL37
5456          */
5457         CL22_RD_OVER_CL45(bp, phy,
5458                           MDIO_REG_BANK_REMOTE_PHY,
5459                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5460                           &cl37_fsm_received);
5461         if ((cl37_fsm_received &
5462              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5463              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5464             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5465               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5466                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5467                              "misc_rx_status(0x8330) = 0x%x\n",
5468                          cl37_fsm_received);
5469                 return;
5470         }
5471         /* The combined cl37/cl73 fsm state information indicating that
5472          * we are connected to a device which does not support cl73, but
5473          * does support cl37 BAM. In this case we disable cl73 and
5474          * restart cl37 auto-neg
5475          */
5476
5477         /* Disable CL73 */
5478         CL22_WR_OVER_CL45(bp, phy,
5479                           MDIO_REG_BANK_CL73_IEEEB0,
5480                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5481                           0);
5482         /* Restart CL37 autoneg */
5483         bnx2x_restart_autoneg(phy, params, 0);
5484         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5485 }
5486
5487 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5488                                   struct link_params *params,
5489                                   struct link_vars *vars,
5490                                   u32 gp_status)
5491 {
5492         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5493                 vars->link_status |=
5494                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5495
5496         if (bnx2x_direct_parallel_detect_used(phy, params))
5497                 vars->link_status |=
5498                         LINK_STATUS_PARALLEL_DETECTION_USED;
5499 }
5500 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5501                                      struct link_params *params,
5502                                       struct link_vars *vars,
5503                                       u16 is_link_up,
5504                                       u16 speed_mask,
5505                                       u16 is_duplex)
5506 {
5507         struct bnx2x *bp = params->bp;
5508         if (phy->req_line_speed == SPEED_AUTO_NEG)
5509                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5510         if (is_link_up) {
5511                 DP(NETIF_MSG_LINK, "phy link up\n");
5512
5513                 vars->phy_link_up = 1;
5514                 vars->link_status |= LINK_STATUS_LINK_UP;
5515
5516                 switch (speed_mask) {
5517                 case GP_STATUS_10M:
5518                         vars->line_speed = SPEED_10;
5519                         if (is_duplex == DUPLEX_FULL)
5520                                 vars->link_status |= LINK_10TFD;
5521                         else
5522                                 vars->link_status |= LINK_10THD;
5523                         break;
5524
5525                 case GP_STATUS_100M:
5526                         vars->line_speed = SPEED_100;
5527                         if (is_duplex == DUPLEX_FULL)
5528                                 vars->link_status |= LINK_100TXFD;
5529                         else
5530                                 vars->link_status |= LINK_100TXHD;
5531                         break;
5532
5533                 case GP_STATUS_1G:
5534                 case GP_STATUS_1G_KX:
5535                         vars->line_speed = SPEED_1000;
5536                         if (is_duplex == DUPLEX_FULL)
5537                                 vars->link_status |= LINK_1000TFD;
5538                         else
5539                                 vars->link_status |= LINK_1000THD;
5540                         break;
5541
5542                 case GP_STATUS_2_5G:
5543                         vars->line_speed = SPEED_2500;
5544                         if (is_duplex == DUPLEX_FULL)
5545                                 vars->link_status |= LINK_2500TFD;
5546                         else
5547                                 vars->link_status |= LINK_2500THD;
5548                         break;
5549
5550                 case GP_STATUS_5G:
5551                 case GP_STATUS_6G:
5552                         DP(NETIF_MSG_LINK,
5553                                  "link speed unsupported  gp_status 0x%x\n",
5554                                   speed_mask);
5555                         return -EINVAL;
5556
5557                 case GP_STATUS_10G_KX4:
5558                 case GP_STATUS_10G_HIG:
5559                 case GP_STATUS_10G_CX4:
5560                 case GP_STATUS_10G_KR:
5561                 case GP_STATUS_10G_SFI:
5562                 case GP_STATUS_10G_XFI:
5563                         vars->line_speed = SPEED_10000;
5564                         vars->link_status |= LINK_10GTFD;
5565                         break;
5566                 case GP_STATUS_20G_DXGXS:
5567                 case GP_STATUS_20G_KR2:
5568                         vars->line_speed = SPEED_20000;
5569                         vars->link_status |= LINK_20GTFD;
5570                         break;
5571                 default:
5572                         DP(NETIF_MSG_LINK,
5573                                   "link speed unsupported gp_status 0x%x\n",
5574                                   speed_mask);
5575                         return -EINVAL;
5576                 }
5577         } else { /* link_down */
5578                 DP(NETIF_MSG_LINK, "phy link down\n");
5579
5580                 vars->phy_link_up = 0;
5581
5582                 vars->duplex = DUPLEX_FULL;
5583                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5584                 vars->mac_type = MAC_TYPE_NONE;
5585         }
5586         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5587                     vars->phy_link_up, vars->line_speed);
5588         return 0;
5589 }
5590
5591 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5592                                       struct link_params *params,
5593                                       struct link_vars *vars)
5594 {
5595         struct bnx2x *bp = params->bp;
5596
5597         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5598         int rc = 0;
5599
5600         /* Read gp_status */
5601         CL22_RD_OVER_CL45(bp, phy,
5602                           MDIO_REG_BANK_GP_STATUS,
5603                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5604                           &gp_status);
5605         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5606                 duplex = DUPLEX_FULL;
5607         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5608                 link_up = 1;
5609         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5610         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5611                        gp_status, link_up, speed_mask);
5612         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5613                                          duplex);
5614         if (rc == -EINVAL)
5615                 return rc;
5616
5617         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5618                 if (SINGLE_MEDIA_DIRECT(params)) {
5619                         vars->duplex = duplex;
5620                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5621                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5622                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5623                                                       gp_status);
5624                 }
5625         } else { /* Link_down */
5626                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5627                     SINGLE_MEDIA_DIRECT(params)) {
5628                         /* Check signal is detected */
5629                         bnx2x_check_fallback_to_cl37(phy, params);
5630                 }
5631         }
5632
5633         /* Read LP advertised speeds*/
5634         if (SINGLE_MEDIA_DIRECT(params) &&
5635             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5636                 u16 val;
5637
5638                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5639                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5640
5641                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5642                         vars->link_status |=
5643                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5644                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5645                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5646                         vars->link_status |=
5647                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5648
5649                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5650                                   MDIO_OVER_1G_LP_UP1, &val);
5651
5652                 if (val & MDIO_OVER_1G_UP1_2_5G)
5653                         vars->link_status |=
5654                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5655                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5656                         vars->link_status |=
5657                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5658         }
5659
5660         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5661                    vars->duplex, vars->flow_ctrl, vars->link_status);
5662         return rc;
5663 }
5664
5665 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5666                                      struct link_params *params,
5667                                      struct link_vars *vars)
5668 {
5669         struct bnx2x *bp = params->bp;
5670         u8 lane;
5671         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5672         int rc = 0;
5673         lane = bnx2x_get_warpcore_lane(phy, params);
5674         /* Read gp_status */
5675         if ((params->loopback_mode) &&
5676             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5677                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5678                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5679                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5680                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5681                 link_up &= 0x1;
5682         } else if ((phy->req_line_speed > SPEED_10000) &&
5683                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5684                 u16 temp_link_up;
5685                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5686                                 1, &temp_link_up);
5687                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5688                                 1, &link_up);
5689                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5690                                temp_link_up, link_up);
5691                 link_up &= (1<<2);
5692                 if (link_up)
5693                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5694         } else {
5695                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5696                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5697                                 &gp_status1);
5698                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5699                 /* Check for either KR, 1G, or AN up. */
5700                 link_up = ((gp_status1 >> 8) |
5701                            (gp_status1 >> 12) |
5702                            (gp_status1)) &
5703                         (1 << lane);
5704                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5705                         u16 an_link;
5706                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5707                                         MDIO_AN_REG_STATUS, &an_link);
5708                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5709                                         MDIO_AN_REG_STATUS, &an_link);
5710                         link_up |= (an_link & (1<<2));
5711                 }
5712                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5713                         u16 pd, gp_status4;
5714                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5715                                 /* Check Autoneg complete */
5716                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5717                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5718                                                 &gp_status4);
5719                                 if (gp_status4 & ((1<<12)<<lane))
5720                                         vars->link_status |=
5721                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5722
5723                                 /* Check parallel detect used */
5724                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5725                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5726                                                 &pd);
5727                                 if (pd & (1<<15))
5728                                         vars->link_status |=
5729                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5730                         }
5731                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5732                         vars->duplex = duplex;
5733                 }
5734         }
5735
5736         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5737             SINGLE_MEDIA_DIRECT(params)) {
5738                 u16 val;
5739
5740                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5741                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5742
5743                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5744                         vars->link_status |=
5745                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5746                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5747                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5748                         vars->link_status |=
5749                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5750
5751                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5752                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5753
5754                 if (val & MDIO_OVER_1G_UP1_2_5G)
5755                         vars->link_status |=
5756                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5757                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5758                         vars->link_status |=
5759                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5760
5761         }
5762
5763
5764         if (lane < 2) {
5765                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5766                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5767         } else {
5768                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5769                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5770         }
5771         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5772
5773         if ((lane & 1) == 0)
5774                 gp_speed <<= 8;
5775         gp_speed &= 0x3f00;
5776         link_up = !!link_up;
5777
5778         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5779                                          duplex);
5780
5781         /* In case of KR link down, start up the recovering procedure */
5782         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5783             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5784                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5785
5786         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5787                    vars->duplex, vars->flow_ctrl, vars->link_status);
5788         return rc;
5789 }
5790 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5791 {
5792         struct bnx2x *bp = params->bp;
5793         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5794         u16 lp_up2;
5795         u16 tx_driver;
5796         u16 bank;
5797
5798         /* Read precomp */
5799         CL22_RD_OVER_CL45(bp, phy,
5800                           MDIO_REG_BANK_OVER_1G,
5801                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5802
5803         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5804         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5805                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5806                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5807
5808         if (lp_up2 == 0)
5809                 return;
5810
5811         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5812               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5813                 CL22_RD_OVER_CL45(bp, phy,
5814                                   bank,
5815                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5816
5817                 /* Replace tx_driver bits [15:12] */
5818                 if (lp_up2 !=
5819                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5820                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5821                         tx_driver |= lp_up2;
5822                         CL22_WR_OVER_CL45(bp, phy,
5823                                           bank,
5824                                           MDIO_TX0_TX_DRIVER, tx_driver);
5825                 }
5826         }
5827 }
5828
5829 static int bnx2x_emac_program(struct link_params *params,
5830                               struct link_vars *vars)
5831 {
5832         struct bnx2x *bp = params->bp;
5833         u8 port = params->port;
5834         u16 mode = 0;
5835
5836         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5837         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5838                        EMAC_REG_EMAC_MODE,
5839                        (EMAC_MODE_25G_MODE |
5840                         EMAC_MODE_PORT_MII_10M |
5841                         EMAC_MODE_HALF_DUPLEX));
5842         switch (vars->line_speed) {
5843         case SPEED_10:
5844                 mode |= EMAC_MODE_PORT_MII_10M;
5845                 break;
5846
5847         case SPEED_100:
5848                 mode |= EMAC_MODE_PORT_MII;
5849                 break;
5850
5851         case SPEED_1000:
5852                 mode |= EMAC_MODE_PORT_GMII;
5853                 break;
5854
5855         case SPEED_2500:
5856                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5857                 break;
5858
5859         default:
5860                 /* 10G not valid for EMAC */
5861                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5862                            vars->line_speed);
5863                 return -EINVAL;
5864         }
5865
5866         if (vars->duplex == DUPLEX_HALF)
5867                 mode |= EMAC_MODE_HALF_DUPLEX;
5868         bnx2x_bits_en(bp,
5869                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5870                       mode);
5871
5872         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5873         return 0;
5874 }
5875
5876 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5877                                   struct link_params *params)
5878 {
5879
5880         u16 bank, i = 0;
5881         struct bnx2x *bp = params->bp;
5882
5883         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5884               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5885                         CL22_WR_OVER_CL45(bp, phy,
5886                                           bank,
5887                                           MDIO_RX0_RX_EQ_BOOST,
5888                                           phy->rx_preemphasis[i]);
5889         }
5890
5891         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5892                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5893                         CL22_WR_OVER_CL45(bp, phy,
5894                                           bank,
5895                                           MDIO_TX0_TX_DRIVER,
5896                                           phy->tx_preemphasis[i]);
5897         }
5898 }
5899
5900 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5901                                    struct link_params *params,
5902                                    struct link_vars *vars)
5903 {
5904         struct bnx2x *bp = params->bp;
5905         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5906                           (params->loopback_mode == LOOPBACK_XGXS));
5907         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5908                 if (SINGLE_MEDIA_DIRECT(params) &&
5909                     (params->feature_config_flags &
5910                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5911                         bnx2x_set_preemphasis(phy, params);
5912
5913                 /* Forced speed requested? */
5914                 if (vars->line_speed != SPEED_AUTO_NEG ||
5915                     (SINGLE_MEDIA_DIRECT(params) &&
5916                      params->loopback_mode == LOOPBACK_EXT)) {
5917                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5918
5919                         /* Disable autoneg */
5920                         bnx2x_set_autoneg(phy, params, vars, 0);
5921
5922                         /* Program speed and duplex */
5923                         bnx2x_program_serdes(phy, params, vars);
5924
5925                 } else { /* AN_mode */
5926                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5927
5928                         /* AN enabled */
5929                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5930
5931                         /* Program duplex & pause advertisement (for aneg) */
5932                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5933                                                           vars->ieee_fc);
5934
5935                         /* Enable autoneg */
5936                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5937
5938                         /* Enable and restart AN */
5939                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5940                 }
5941
5942         } else { /* SGMII mode */
5943                 DP(NETIF_MSG_LINK, "SGMII\n");
5944
5945                 bnx2x_initialize_sgmii_process(phy, params, vars);
5946         }
5947 }
5948
5949 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5950                           struct link_params *params,
5951                           struct link_vars *vars)
5952 {
5953         int rc;
5954         vars->phy_flags |= PHY_XGXS_FLAG;
5955         if ((phy->req_line_speed &&
5956              ((phy->req_line_speed == SPEED_100) ||
5957               (phy->req_line_speed == SPEED_10))) ||
5958             (!phy->req_line_speed &&
5959              (phy->speed_cap_mask >=
5960               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5961              (phy->speed_cap_mask <
5962               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5963             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5964                 vars->phy_flags |= PHY_SGMII_FLAG;
5965         else
5966                 vars->phy_flags &= ~PHY_SGMII_FLAG;
5967
5968         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
5969         bnx2x_set_aer_mmd(params, phy);
5970         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
5971                 bnx2x_set_master_ln(params, phy);
5972
5973         rc = bnx2x_reset_unicore(params, phy, 0);
5974         /* Reset the SerDes and wait for reset bit return low */
5975         if (rc)
5976                 return rc;
5977
5978         bnx2x_set_aer_mmd(params, phy);
5979         /* Setting the masterLn_def again after the reset */
5980         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
5981                 bnx2x_set_master_ln(params, phy);
5982                 bnx2x_set_swap_lanes(params, phy);
5983         }
5984
5985         return rc;
5986 }
5987
5988 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
5989                                      struct bnx2x_phy *phy,
5990                                      struct link_params *params)
5991 {
5992         u16 cnt, ctrl;
5993         /* Wait for soft reset to get cleared up to 1 sec */
5994         for (cnt = 0; cnt < 1000; cnt++) {
5995                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5996                         bnx2x_cl22_read(bp, phy,
5997                                 MDIO_PMA_REG_CTRL, &ctrl);
5998                 else
5999                         bnx2x_cl45_read(bp, phy,
6000                                 MDIO_PMA_DEVAD,
6001                                 MDIO_PMA_REG_CTRL, &ctrl);
6002                 if (!(ctrl & (1<<15)))
6003                         break;
6004                 usleep_range(1000, 2000);
6005         }
6006
6007         if (cnt == 1000)
6008                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
6009                                       " Port %d\n",
6010                          params->port);
6011         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6012         return cnt;
6013 }
6014
6015 static void bnx2x_link_int_enable(struct link_params *params)
6016 {
6017         u8 port = params->port;
6018         u32 mask;
6019         struct bnx2x *bp = params->bp;
6020
6021         /* Setting the status to report on link up for either XGXS or SerDes */
6022         if (CHIP_IS_E3(bp)) {
6023                 mask = NIG_MASK_XGXS0_LINK_STATUS;
6024                 if (!(SINGLE_MEDIA_DIRECT(params)))
6025                         mask |= NIG_MASK_MI_INT;
6026         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6027                 mask = (NIG_MASK_XGXS0_LINK10G |
6028                         NIG_MASK_XGXS0_LINK_STATUS);
6029                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6030                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6031                         params->phy[INT_PHY].type !=
6032                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6033                         mask |= NIG_MASK_MI_INT;
6034                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6035                 }
6036
6037         } else { /* SerDes */
6038                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6039                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6040                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6041                         params->phy[INT_PHY].type !=
6042                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6043                         mask |= NIG_MASK_MI_INT;
6044                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6045                 }
6046         }
6047         bnx2x_bits_en(bp,
6048                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6049                       mask);
6050
6051         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6052                  (params->switch_cfg == SWITCH_CFG_10G),
6053                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6054         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6055                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6056                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6057                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6058         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6059            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6060            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6061 }
6062
6063 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6064                                      u8 exp_mi_int)
6065 {
6066         u32 latch_status = 0;
6067
6068         /* Disable the MI INT ( external phy int ) by writing 1 to the
6069          * status register. Link down indication is high-active-signal,
6070          * so in this case we need to write the status to clear the XOR
6071          */
6072         /* Read Latched signals */
6073         latch_status = REG_RD(bp,
6074                                     NIG_REG_LATCH_STATUS_0 + port*8);
6075         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6076         /* Handle only those with latched-signal=up.*/
6077         if (exp_mi_int)
6078                 bnx2x_bits_en(bp,
6079                               NIG_REG_STATUS_INTERRUPT_PORT0
6080                               + port*4,
6081                               NIG_STATUS_EMAC0_MI_INT);
6082         else
6083                 bnx2x_bits_dis(bp,
6084                                NIG_REG_STATUS_INTERRUPT_PORT0
6085                                + port*4,
6086                                NIG_STATUS_EMAC0_MI_INT);
6087
6088         if (latch_status & 1) {
6089
6090                 /* For all latched-signal=up : Re-Arm Latch signals */
6091                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6092                        (latch_status & 0xfffe) | (latch_status & 1));
6093         }
6094         /* For all latched-signal=up,Write original_signal to status */
6095 }
6096
6097 static void bnx2x_link_int_ack(struct link_params *params,
6098                                struct link_vars *vars, u8 is_10g_plus)
6099 {
6100         struct bnx2x *bp = params->bp;
6101         u8 port = params->port;
6102         u32 mask;
6103         /* First reset all status we assume only one line will be
6104          * change at a time
6105          */
6106         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6107                        (NIG_STATUS_XGXS0_LINK10G |
6108                         NIG_STATUS_XGXS0_LINK_STATUS |
6109                         NIG_STATUS_SERDES0_LINK_STATUS));
6110         if (vars->phy_link_up) {
6111                 if (USES_WARPCORE(bp))
6112                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6113                 else {
6114                         if (is_10g_plus)
6115                                 mask = NIG_STATUS_XGXS0_LINK10G;
6116                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6117                                 /* Disable the link interrupt by writing 1 to
6118                                  * the relevant lane in the status register
6119                                  */
6120                                 u32 ser_lane =
6121                                         ((params->lane_config &
6122                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6123                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6124                                 mask = ((1 << ser_lane) <<
6125                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6126                         } else
6127                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6128                 }
6129                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6130                                mask);
6131                 bnx2x_bits_en(bp,
6132                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6133                               mask);
6134         }
6135 }
6136
6137 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6138 {
6139         u8 *str_ptr = str;
6140         u32 mask = 0xf0000000;
6141         u8 shift = 8*4;
6142         u8 digit;
6143         u8 remove_leading_zeros = 1;
6144         if (*len < 10) {
6145                 /* Need more than 10chars for this format */
6146                 *str_ptr = '\0';
6147                 (*len)--;
6148                 return -EINVAL;
6149         }
6150         while (shift > 0) {
6151
6152                 shift -= 4;
6153                 digit = ((num & mask) >> shift);
6154                 if (digit == 0 && remove_leading_zeros) {
6155                         mask = mask >> 4;
6156                         continue;
6157                 } else if (digit < 0xa)
6158                         *str_ptr = digit + '0';
6159                 else
6160                         *str_ptr = digit - 0xa + 'a';
6161                 remove_leading_zeros = 0;
6162                 str_ptr++;
6163                 (*len)--;
6164                 mask = mask >> 4;
6165                 if (shift == 4*4) {
6166                         *str_ptr = '.';
6167                         str_ptr++;
6168                         (*len)--;
6169                         remove_leading_zeros = 1;
6170                 }
6171         }
6172         return 0;
6173 }
6174
6175
6176 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6177 {
6178         str[0] = '\0';
6179         (*len)--;
6180         return 0;
6181 }
6182
6183 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6184                                  u16 len)
6185 {
6186         struct bnx2x *bp;
6187         u32 spirom_ver = 0;
6188         int status = 0;
6189         u8 *ver_p = version;
6190         u16 remain_len = len;
6191         if (version == NULL || params == NULL)
6192                 return -EINVAL;
6193         bp = params->bp;
6194
6195         /* Extract first external phy*/
6196         version[0] = '\0';
6197         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6198
6199         if (params->phy[EXT_PHY1].format_fw_ver) {
6200                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6201                                                               ver_p,
6202                                                               &remain_len);
6203                 ver_p += (len - remain_len);
6204         }
6205         if ((params->num_phys == MAX_PHYS) &&
6206             (params->phy[EXT_PHY2].ver_addr != 0)) {
6207                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6208                 if (params->phy[EXT_PHY2].format_fw_ver) {
6209                         *ver_p = '/';
6210                         ver_p++;
6211                         remain_len--;
6212                         status |= params->phy[EXT_PHY2].format_fw_ver(
6213                                 spirom_ver,
6214                                 ver_p,
6215                                 &remain_len);
6216                         ver_p = version + (len - remain_len);
6217                 }
6218         }
6219         *ver_p = '\0';
6220         return status;
6221 }
6222
6223 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6224                                     struct link_params *params)
6225 {
6226         u8 port = params->port;
6227         struct bnx2x *bp = params->bp;
6228
6229         if (phy->req_line_speed != SPEED_1000) {
6230                 u32 md_devad = 0;
6231
6232                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6233
6234                 if (!CHIP_IS_E3(bp)) {
6235                         /* Change the uni_phy_addr in the nig */
6236                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6237                                                port*0x18));
6238
6239                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6240                                0x5);
6241                 }
6242
6243                 bnx2x_cl45_write(bp, phy,
6244                                  5,
6245                                  (MDIO_REG_BANK_AER_BLOCK +
6246                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6247                                  0x2800);
6248
6249                 bnx2x_cl45_write(bp, phy,
6250                                  5,
6251                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6252                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6253                                  0x6041);
6254                 msleep(200);
6255                 /* Set aer mmd back */
6256                 bnx2x_set_aer_mmd(params, phy);
6257
6258                 if (!CHIP_IS_E3(bp)) {
6259                         /* And md_devad */
6260                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6261                                md_devad);
6262                 }
6263         } else {
6264                 u16 mii_ctrl;
6265                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6266                 bnx2x_cl45_read(bp, phy, 5,
6267                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6268                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6269                                 &mii_ctrl);
6270                 bnx2x_cl45_write(bp, phy, 5,
6271                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6272                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6273                                  mii_ctrl |
6274                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6275         }
6276 }
6277
6278 int bnx2x_set_led(struct link_params *params,
6279                   struct link_vars *vars, u8 mode, u32 speed)
6280 {
6281         u8 port = params->port;
6282         u16 hw_led_mode = params->hw_led_mode;
6283         int rc = 0;
6284         u8 phy_idx;
6285         u32 tmp;
6286         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6287         struct bnx2x *bp = params->bp;
6288         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6289         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6290                  speed, hw_led_mode);
6291         /* In case */
6292         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6293                 if (params->phy[phy_idx].set_link_led) {
6294                         params->phy[phy_idx].set_link_led(
6295                                 &params->phy[phy_idx], params, mode);
6296                 }
6297         }
6298
6299         switch (mode) {
6300         case LED_MODE_FRONT_PANEL_OFF:
6301         case LED_MODE_OFF:
6302                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6303                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6304                        SHARED_HW_CFG_LED_MAC1);
6305
6306                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6307                 if (params->phy[EXT_PHY1].type ==
6308                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6309                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6310                                 EMAC_LED_100MB_OVERRIDE |
6311                                 EMAC_LED_10MB_OVERRIDE);
6312                 else
6313                         tmp |= EMAC_LED_OVERRIDE;
6314
6315                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6316                 break;
6317
6318         case LED_MODE_OPER:
6319                 /* For all other phys, OPER mode is same as ON, so in case
6320                  * link is down, do nothing
6321                  */
6322                 if (!vars->link_up)
6323                         break;
6324         case LED_MODE_ON:
6325                 if (((params->phy[EXT_PHY1].type ==
6326                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6327                          (params->phy[EXT_PHY1].type ==
6328                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6329                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6330                         /* This is a work-around for E2+8727 Configurations */
6331                         if (mode == LED_MODE_ON ||
6332                                 speed == SPEED_10000){
6333                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6334                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6335
6336                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6337                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6338                                         (tmp | EMAC_LED_OVERRIDE));
6339                                 /* Return here without enabling traffic
6340                                  * LED blink and setting rate in ON mode.
6341                                  * In oper mode, enabling LED blink
6342                                  * and setting rate is needed.
6343                                  */
6344                                 if (mode == LED_MODE_ON)
6345                                         return rc;
6346                         }
6347                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6348                         /* This is a work-around for HW issue found when link
6349                          * is up in CL73
6350                          */
6351                         if ((!CHIP_IS_E3(bp)) ||
6352                             (CHIP_IS_E3(bp) &&
6353                              mode == LED_MODE_ON))
6354                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6355
6356                         if (CHIP_IS_E1x(bp) ||
6357                             CHIP_IS_E2(bp) ||
6358                             (mode == LED_MODE_ON))
6359                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6360                         else
6361                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6362                                        hw_led_mode);
6363                 } else if ((params->phy[EXT_PHY1].type ==
6364                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6365                            (mode == LED_MODE_ON)) {
6366                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6367                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6368                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6369                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6370                         /* Break here; otherwise, it'll disable the
6371                          * intended override.
6372                          */
6373                         break;
6374                 } else
6375                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6376                                hw_led_mode);
6377
6378                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6379                 /* Set blinking rate to ~15.9Hz */
6380                 if (CHIP_IS_E3(bp))
6381                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6382                                LED_BLINK_RATE_VAL_E3);
6383                 else
6384                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6385                                LED_BLINK_RATE_VAL_E1X_E2);
6386                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6387                        port*4, 1);
6388                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6389                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6390                         (tmp & (~EMAC_LED_OVERRIDE)));
6391
6392                 if (CHIP_IS_E1(bp) &&
6393                     ((speed == SPEED_2500) ||
6394                      (speed == SPEED_1000) ||
6395                      (speed == SPEED_100) ||
6396                      (speed == SPEED_10))) {
6397                         /* For speeds less than 10G LED scheme is different */
6398                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6399                                + port*4, 1);
6400                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6401                                port*4, 0);
6402                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6403                                port*4, 1);
6404                 }
6405                 break;
6406
6407         default:
6408                 rc = -EINVAL;
6409                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6410                          mode);
6411                 break;
6412         }
6413         return rc;
6414
6415 }
6416
6417 /* This function comes to reflect the actual link state read DIRECTLY from the
6418  * HW
6419  */
6420 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6421                     u8 is_serdes)
6422 {
6423         struct bnx2x *bp = params->bp;
6424         u16 gp_status = 0, phy_index = 0;
6425         u8 ext_phy_link_up = 0, serdes_phy_type;
6426         struct link_vars temp_vars;
6427         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6428
6429         if (CHIP_IS_E3(bp)) {
6430                 u16 link_up;
6431                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6432                     > SPEED_10000) {
6433                         /* Check 20G link */
6434                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6435                                         1, &link_up);
6436                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6437                                         1, &link_up);
6438                         link_up &= (1<<2);
6439                 } else {
6440                         /* Check 10G link and below*/
6441                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6442                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6443                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6444                                         &gp_status);
6445                         gp_status = ((gp_status >> 8) & 0xf) |
6446                                 ((gp_status >> 12) & 0xf);
6447                         link_up = gp_status & (1 << lane);
6448                 }
6449                 if (!link_up)
6450                         return -ESRCH;
6451         } else {
6452                 CL22_RD_OVER_CL45(bp, int_phy,
6453                           MDIO_REG_BANK_GP_STATUS,
6454                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6455                           &gp_status);
6456         /* Link is up only if both local phy and external phy are up */
6457         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6458                 return -ESRCH;
6459         }
6460         /* In XGXS loopback mode, do not check external PHY */
6461         if (params->loopback_mode == LOOPBACK_XGXS)
6462                 return 0;
6463
6464         switch (params->num_phys) {
6465         case 1:
6466                 /* No external PHY */
6467                 return 0;
6468         case 2:
6469                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6470                         &params->phy[EXT_PHY1],
6471                         params, &temp_vars);
6472                 break;
6473         case 3: /* Dual Media */
6474                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6475                       phy_index++) {
6476                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6477                                             ETH_PHY_SFPP_10G_FIBER) ||
6478                                            (params->phy[phy_index].media_type ==
6479                                             ETH_PHY_SFP_1G_FIBER) ||
6480                                            (params->phy[phy_index].media_type ==
6481                                             ETH_PHY_XFP_FIBER) ||
6482                                            (params->phy[phy_index].media_type ==
6483                                             ETH_PHY_DA_TWINAX));
6484
6485                         if (is_serdes != serdes_phy_type)
6486                                 continue;
6487                         if (params->phy[phy_index].read_status) {
6488                                 ext_phy_link_up |=
6489                                         params->phy[phy_index].read_status(
6490                                                 &params->phy[phy_index],
6491                                                 params, &temp_vars);
6492                         }
6493                 }
6494                 break;
6495         }
6496         if (ext_phy_link_up)
6497                 return 0;
6498         return -ESRCH;
6499 }
6500
6501 static int bnx2x_link_initialize(struct link_params *params,
6502                                  struct link_vars *vars)
6503 {
6504         int rc = 0;
6505         u8 phy_index, non_ext_phy;
6506         struct bnx2x *bp = params->bp;
6507         /* In case of external phy existence, the line speed would be the
6508          * line speed linked up by the external phy. In case it is direct
6509          * only, then the line_speed during initialization will be
6510          * equal to the req_line_speed
6511          */
6512         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6513
6514         /* Initialize the internal phy in case this is a direct board
6515          * (no external phys), or this board has external phy which requires
6516          * to first.
6517          */
6518         if (!USES_WARPCORE(bp))
6519                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6520         /* init ext phy and enable link state int */
6521         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6522                        (params->loopback_mode == LOOPBACK_XGXS));
6523
6524         if (non_ext_phy ||
6525             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6526             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6527                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6528                 if (vars->line_speed == SPEED_AUTO_NEG &&
6529                     (CHIP_IS_E1x(bp) ||
6530                      CHIP_IS_E2(bp)))
6531                         bnx2x_set_parallel_detection(phy, params);
6532                 if (params->phy[INT_PHY].config_init)
6533                         params->phy[INT_PHY].config_init(phy, params, vars);
6534         }
6535
6536         /* Re-read this value in case it was changed inside config_init due to
6537          * limitations of optic module
6538          */
6539         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6540
6541         /* Init external phy*/
6542         if (non_ext_phy) {
6543                 if (params->phy[INT_PHY].supported &
6544                     SUPPORTED_FIBRE)
6545                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6546         } else {
6547                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6548                       phy_index++) {
6549                         /* No need to initialize second phy in case of first
6550                          * phy only selection. In case of second phy, we do
6551                          * need to initialize the first phy, since they are
6552                          * connected.
6553                          */
6554                         if (params->phy[phy_index].supported &
6555                             SUPPORTED_FIBRE)
6556                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6557
6558                         if (phy_index == EXT_PHY2 &&
6559                             (bnx2x_phy_selection(params) ==
6560                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6561                                 DP(NETIF_MSG_LINK,
6562                                    "Not initializing second phy\n");
6563                                 continue;
6564                         }
6565                         params->phy[phy_index].config_init(
6566                                 &params->phy[phy_index],
6567                                 params, vars);
6568                 }
6569         }
6570         /* Reset the interrupt indication after phy was initialized */
6571         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6572                        params->port*4,
6573                        (NIG_STATUS_XGXS0_LINK10G |
6574                         NIG_STATUS_XGXS0_LINK_STATUS |
6575                         NIG_STATUS_SERDES0_LINK_STATUS |
6576                         NIG_MASK_MI_INT));
6577         return rc;
6578 }
6579
6580 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6581                                  struct link_params *params)
6582 {
6583         /* Reset the SerDes/XGXS */
6584         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6585                (0x1ff << (params->port*16)));
6586 }
6587
6588 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6589                                         struct link_params *params)
6590 {
6591         struct bnx2x *bp = params->bp;
6592         u8 gpio_port;
6593         /* HW reset */
6594         if (CHIP_IS_E2(bp))
6595                 gpio_port = BP_PATH(bp);
6596         else
6597                 gpio_port = params->port;
6598         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6599                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6600                        gpio_port);
6601         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6602                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6603                        gpio_port);
6604         DP(NETIF_MSG_LINK, "reset external PHY\n");
6605 }
6606
6607 static int bnx2x_update_link_down(struct link_params *params,
6608                                   struct link_vars *vars)
6609 {
6610         struct bnx2x *bp = params->bp;
6611         u8 port = params->port;
6612
6613         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6614         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6615         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6616         /* Indicate no mac active */
6617         vars->mac_type = MAC_TYPE_NONE;
6618
6619         /* Update shared memory */
6620         vars->link_status &= ~LINK_UPDATE_MASK;
6621         vars->line_speed = 0;
6622         bnx2x_update_mng(params, vars->link_status);
6623
6624         /* Activate nig drain */
6625         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6626
6627         /* Disable emac */
6628         if (!CHIP_IS_E3(bp))
6629                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6630
6631         usleep_range(10000, 20000);
6632         /* Reset BigMac/Xmac */
6633         if (CHIP_IS_E1x(bp) ||
6634             CHIP_IS_E2(bp))
6635                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6636
6637         if (CHIP_IS_E3(bp)) {
6638                 /* Prevent LPI Generation by chip */
6639                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6640                        0);
6641                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6642                        0);
6643                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6644                                       SHMEM_EEE_ACTIVE_BIT);
6645
6646                 bnx2x_update_mng_eee(params, vars->eee_status);
6647                 bnx2x_set_xmac_rxtx(params, 0);
6648                 bnx2x_set_umac_rxtx(params, 0);
6649         }
6650
6651         return 0;
6652 }
6653
6654 static int bnx2x_update_link_up(struct link_params *params,
6655                                 struct link_vars *vars,
6656                                 u8 link_10g)
6657 {
6658         struct bnx2x *bp = params->bp;
6659         u8 phy_idx, port = params->port;
6660         int rc = 0;
6661
6662         vars->link_status |= (LINK_STATUS_LINK_UP |
6663                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6664         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6665
6666         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6667                 vars->link_status |=
6668                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6669
6670         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6671                 vars->link_status |=
6672                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6673         if (USES_WARPCORE(bp)) {
6674                 if (link_10g) {
6675                         if (bnx2x_xmac_enable(params, vars, 0) ==
6676                             -ESRCH) {
6677                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6678                                 vars->link_up = 0;
6679                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6680                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6681                         }
6682                 } else
6683                         bnx2x_umac_enable(params, vars, 0);
6684                 bnx2x_set_led(params, vars,
6685                               LED_MODE_OPER, vars->line_speed);
6686
6687                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6688                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6689                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6690                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6691                                (params->port << 2), 1);
6692                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6693                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6694                                (params->port << 2), 0xfc20);
6695                 }
6696         }
6697         if ((CHIP_IS_E1x(bp) ||
6698              CHIP_IS_E2(bp))) {
6699                 if (link_10g) {
6700                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6701                             -ESRCH) {
6702                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6703                                 vars->link_up = 0;
6704                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6705                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6706                         }
6707
6708                         bnx2x_set_led(params, vars,
6709                                       LED_MODE_OPER, SPEED_10000);
6710                 } else {
6711                         rc = bnx2x_emac_program(params, vars);
6712                         bnx2x_emac_enable(params, vars, 0);
6713
6714                         /* AN complete? */
6715                         if ((vars->link_status &
6716                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6717                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6718                             SINGLE_MEDIA_DIRECT(params))
6719                                 bnx2x_set_gmii_tx_driver(params);
6720                 }
6721         }
6722
6723         /* PBF - link up */
6724         if (CHIP_IS_E1x(bp))
6725                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6726                                        vars->line_speed);
6727
6728         /* Disable drain */
6729         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6730
6731         /* Update shared memory */
6732         bnx2x_update_mng(params, vars->link_status);
6733         bnx2x_update_mng_eee(params, vars->eee_status);
6734         /* Check remote fault */
6735         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6736                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6737                         bnx2x_check_half_open_conn(params, vars, 0);
6738                         break;
6739                 }
6740         }
6741         msleep(20);
6742         return rc;
6743 }
6744 /* The bnx2x_link_update function should be called upon link
6745  * interrupt.
6746  * Link is considered up as follows:
6747  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6748  *   to be up
6749  * - SINGLE_MEDIA - The link between the 577xx and the external
6750  *   phy (XGXS) need to up as well as the external link of the
6751  *   phy (PHY_EXT1)
6752  * - DUAL_MEDIA - The link between the 577xx and the first
6753  *   external phy needs to be up, and at least one of the 2
6754  *   external phy link must be up.
6755  */
6756 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6757 {
6758         struct bnx2x *bp = params->bp;
6759         struct link_vars phy_vars[MAX_PHYS];
6760         u8 port = params->port;
6761         u8 link_10g_plus, phy_index;
6762         u8 ext_phy_link_up = 0, cur_link_up;
6763         int rc = 0;
6764         u8 is_mi_int = 0;
6765         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6766         u8 active_external_phy = INT_PHY;
6767         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6768         vars->link_status &= ~LINK_UPDATE_MASK;
6769         for (phy_index = INT_PHY; phy_index < params->num_phys;
6770               phy_index++) {
6771                 phy_vars[phy_index].flow_ctrl = 0;
6772                 phy_vars[phy_index].link_status = 0;
6773                 phy_vars[phy_index].line_speed = 0;
6774                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6775                 phy_vars[phy_index].phy_link_up = 0;
6776                 phy_vars[phy_index].link_up = 0;
6777                 phy_vars[phy_index].fault_detected = 0;
6778                 /* different consideration, since vars holds inner state */
6779                 phy_vars[phy_index].eee_status = vars->eee_status;
6780         }
6781
6782         if (USES_WARPCORE(bp))
6783                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6784
6785         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6786                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6787                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6788
6789         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6790                                 port*0x18) > 0);
6791         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6792                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6793                  is_mi_int,
6794                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6795
6796         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6797           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6798           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6799
6800         /* Disable emac */
6801         if (!CHIP_IS_E3(bp))
6802                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6803
6804         /* Step 1:
6805          * Check external link change only for external phys, and apply
6806          * priority selection between them in case the link on both phys
6807          * is up. Note that instead of the common vars, a temporary
6808          * vars argument is used since each phy may have different link/
6809          * speed/duplex result
6810          */
6811         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6812               phy_index++) {
6813                 struct bnx2x_phy *phy = &params->phy[phy_index];
6814                 if (!phy->read_status)
6815                         continue;
6816                 /* Read link status and params of this ext phy */
6817                 cur_link_up = phy->read_status(phy, params,
6818                                                &phy_vars[phy_index]);
6819                 if (cur_link_up) {
6820                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6821                                    phy_index);
6822                 } else {
6823                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6824                                    phy_index);
6825                         continue;
6826                 }
6827
6828                 if (!ext_phy_link_up) {
6829                         ext_phy_link_up = 1;
6830                         active_external_phy = phy_index;
6831                 } else {
6832                         switch (bnx2x_phy_selection(params)) {
6833                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6834                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6835                         /* In this option, the first PHY makes sure to pass the
6836                          * traffic through itself only.
6837                          * Its not clear how to reset the link on the second phy
6838                          */
6839                                 active_external_phy = EXT_PHY1;
6840                                 break;
6841                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6842                         /* In this option, the first PHY makes sure to pass the
6843                          * traffic through the second PHY.
6844                          */
6845                                 active_external_phy = EXT_PHY2;
6846                                 break;
6847                         default:
6848                         /* Link indication on both PHYs with the following cases
6849                          * is invalid:
6850                          * - FIRST_PHY means that second phy wasn't initialized,
6851                          * hence its link is expected to be down
6852                          * - SECOND_PHY means that first phy should not be able
6853                          * to link up by itself (using configuration)
6854                          * - DEFAULT should be overriden during initialiazation
6855                          */
6856                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6857                                            "mpc=0x%x. DISABLING LINK !!!\n",
6858                                            params->multi_phy_config);
6859                                 ext_phy_link_up = 0;
6860                                 break;
6861                         }
6862                 }
6863         }
6864         prev_line_speed = vars->line_speed;
6865         /* Step 2:
6866          * Read the status of the internal phy. In case of
6867          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6868          * otherwise this is the link between the 577xx and the first
6869          * external phy
6870          */
6871         if (params->phy[INT_PHY].read_status)
6872                 params->phy[INT_PHY].read_status(
6873                         &params->phy[INT_PHY],
6874                         params, vars);
6875         /* The INT_PHY flow control reside in the vars. This include the
6876          * case where the speed or flow control are not set to AUTO.
6877          * Otherwise, the active external phy flow control result is set
6878          * to the vars. The ext_phy_line_speed is needed to check if the
6879          * speed is different between the internal phy and external phy.
6880          * This case may be result of intermediate link speed change.
6881          */
6882         if (active_external_phy > INT_PHY) {
6883                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6884                 /* Link speed is taken from the XGXS. AN and FC result from
6885                  * the external phy.
6886                  */
6887                 vars->link_status |= phy_vars[active_external_phy].link_status;
6888
6889                 /* if active_external_phy is first PHY and link is up - disable
6890                  * disable TX on second external PHY
6891                  */
6892                 if (active_external_phy == EXT_PHY1) {
6893                         if (params->phy[EXT_PHY2].phy_specific_func) {
6894                                 DP(NETIF_MSG_LINK,
6895                                    "Disabling TX on EXT_PHY2\n");
6896                                 params->phy[EXT_PHY2].phy_specific_func(
6897                                         &params->phy[EXT_PHY2],
6898                                         params, DISABLE_TX);
6899                         }
6900                 }
6901
6902                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
6903                 vars->duplex = phy_vars[active_external_phy].duplex;
6904                 if (params->phy[active_external_phy].supported &
6905                     SUPPORTED_FIBRE)
6906                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6907                 else
6908                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
6909
6910                 vars->eee_status = phy_vars[active_external_phy].eee_status;
6911
6912                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
6913                            active_external_phy);
6914         }
6915
6916         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6917               phy_index++) {
6918                 if (params->phy[phy_index].flags &
6919                     FLAGS_REARM_LATCH_SIGNAL) {
6920                         bnx2x_rearm_latch_signal(bp, port,
6921                                                  phy_index ==
6922                                                  active_external_phy);
6923                         break;
6924                 }
6925         }
6926         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6927                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
6928                    vars->link_status, ext_phy_line_speed);
6929         /* Upon link speed change set the NIG into drain mode. Comes to
6930          * deals with possible FIFO glitch due to clk change when speed
6931          * is decreased without link down indicator
6932          */
6933
6934         if (vars->phy_link_up) {
6935                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
6936                     (ext_phy_line_speed != vars->line_speed)) {
6937                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
6938                                    " different than the external"
6939                                    " link speed %d\n", vars->line_speed,
6940                                    ext_phy_line_speed);
6941                         vars->phy_link_up = 0;
6942                 } else if (prev_line_speed != vars->line_speed) {
6943                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
6944                                0);
6945                         usleep_range(1000, 2000);
6946                 }
6947         }
6948
6949         /* Anything 10 and over uses the bmac */
6950         link_10g_plus = (vars->line_speed >= SPEED_10000);
6951
6952         bnx2x_link_int_ack(params, vars, link_10g_plus);
6953
6954         /* In case external phy link is up, and internal link is down
6955          * (not initialized yet probably after link initialization, it
6956          * needs to be initialized.
6957          * Note that after link down-up as result of cable plug, the xgxs
6958          * link would probably become up again without the need
6959          * initialize it
6960          */
6961         if (!(SINGLE_MEDIA_DIRECT(params))) {
6962                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
6963                            " init_preceding = %d\n", ext_phy_link_up,
6964                            vars->phy_link_up,
6965                            params->phy[EXT_PHY1].flags &
6966                            FLAGS_INIT_XGXS_FIRST);
6967                 if (!(params->phy[EXT_PHY1].flags &
6968                       FLAGS_INIT_XGXS_FIRST)
6969                     && ext_phy_link_up && !vars->phy_link_up) {
6970                         vars->line_speed = ext_phy_line_speed;
6971                         if (vars->line_speed < SPEED_1000)
6972                                 vars->phy_flags |= PHY_SGMII_FLAG;
6973                         else
6974                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6975
6976                         if (params->phy[INT_PHY].config_init)
6977                                 params->phy[INT_PHY].config_init(
6978                                         &params->phy[INT_PHY], params,
6979                                                 vars);
6980                 }
6981         }
6982         /* Link is up only if both local phy and external phy (in case of
6983          * non-direct board) are up and no fault detected on active PHY.
6984          */
6985         vars->link_up = (vars->phy_link_up &&
6986                          (ext_phy_link_up ||
6987                           SINGLE_MEDIA_DIRECT(params)) &&
6988                          (phy_vars[active_external_phy].fault_detected == 0));
6989
6990         /* Update the PFC configuration in case it was changed */
6991         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
6992                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
6993         else
6994                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
6995
6996         if (vars->link_up)
6997                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
6998         else
6999                 rc = bnx2x_update_link_down(params, vars);
7000
7001         /* Update MCP link status was changed */
7002         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7003                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7004
7005         return rc;
7006 }
7007
7008 /*****************************************************************************/
7009 /*                          External Phy section                             */
7010 /*****************************************************************************/
7011 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7012 {
7013         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7014                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7015         usleep_range(1000, 2000);
7016         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7017                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7018 }
7019
7020 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7021                                       u32 spirom_ver, u32 ver_addr)
7022 {
7023         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7024                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7025
7026         if (ver_addr)
7027                 REG_WR(bp, ver_addr, spirom_ver);
7028 }
7029
7030 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7031                                       struct bnx2x_phy *phy,
7032                                       u8 port)
7033 {
7034         u16 fw_ver1, fw_ver2;
7035
7036         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7037                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7038         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7039                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7040         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7041                                   phy->ver_addr);
7042 }
7043
7044 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7045                                        struct bnx2x_phy *phy,
7046                                        struct link_vars *vars)
7047 {
7048         u16 val;
7049         bnx2x_cl45_read(bp, phy,
7050                         MDIO_AN_DEVAD,
7051                         MDIO_AN_REG_STATUS, &val);
7052         bnx2x_cl45_read(bp, phy,
7053                         MDIO_AN_DEVAD,
7054                         MDIO_AN_REG_STATUS, &val);
7055         if (val & (1<<5))
7056                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7057         if ((val & (1<<0)) == 0)
7058                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7059 }
7060
7061 /******************************************************************/
7062 /*              common BCM8073/BCM8727 PHY SECTION                */
7063 /******************************************************************/
7064 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7065                                   struct link_params *params,
7066                                   struct link_vars *vars)
7067 {
7068         struct bnx2x *bp = params->bp;
7069         if (phy->req_line_speed == SPEED_10 ||
7070             phy->req_line_speed == SPEED_100) {
7071                 vars->flow_ctrl = phy->req_flow_ctrl;
7072                 return;
7073         }
7074
7075         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7076             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7077                 u16 pause_result;
7078                 u16 ld_pause;           /* local */
7079                 u16 lp_pause;           /* link partner */
7080                 bnx2x_cl45_read(bp, phy,
7081                                 MDIO_AN_DEVAD,
7082                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7083
7084                 bnx2x_cl45_read(bp, phy,
7085                                 MDIO_AN_DEVAD,
7086                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7087                 pause_result = (ld_pause &
7088                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7089                 pause_result |= (lp_pause &
7090                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7091
7092                 bnx2x_pause_resolve(vars, pause_result);
7093                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7094                            pause_result);
7095         }
7096 }
7097 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7098                                              struct bnx2x_phy *phy,
7099                                              u8 port)
7100 {
7101         u32 count = 0;
7102         u16 fw_ver1, fw_msgout;
7103         int rc = 0;
7104
7105         /* Boot port from external ROM  */
7106         /* EDC grst */
7107         bnx2x_cl45_write(bp, phy,
7108                          MDIO_PMA_DEVAD,
7109                          MDIO_PMA_REG_GEN_CTRL,
7110                          0x0001);
7111
7112         /* Ucode reboot and rst */
7113         bnx2x_cl45_write(bp, phy,
7114                          MDIO_PMA_DEVAD,
7115                          MDIO_PMA_REG_GEN_CTRL,
7116                          0x008c);
7117
7118         bnx2x_cl45_write(bp, phy,
7119                          MDIO_PMA_DEVAD,
7120                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7121
7122         /* Reset internal microprocessor */
7123         bnx2x_cl45_write(bp, phy,
7124                          MDIO_PMA_DEVAD,
7125                          MDIO_PMA_REG_GEN_CTRL,
7126                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7127
7128         /* Release srst bit */
7129         bnx2x_cl45_write(bp, phy,
7130                          MDIO_PMA_DEVAD,
7131                          MDIO_PMA_REG_GEN_CTRL,
7132                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7133
7134         /* Delay 100ms per the PHY specifications */
7135         msleep(100);
7136
7137         /* 8073 sometimes taking longer to download */
7138         do {
7139                 count++;
7140                 if (count > 300) {
7141                         DP(NETIF_MSG_LINK,
7142                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7143                                  "Download failed. fw version = 0x%x\n",
7144                                  port, fw_ver1);
7145                         rc = -EINVAL;
7146                         break;
7147                 }
7148
7149                 bnx2x_cl45_read(bp, phy,
7150                                 MDIO_PMA_DEVAD,
7151                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7152                 bnx2x_cl45_read(bp, phy,
7153                                 MDIO_PMA_DEVAD,
7154                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7155
7156                 usleep_range(1000, 2000);
7157         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7158                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7159                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7160
7161         /* Clear ser_boot_ctl bit */
7162         bnx2x_cl45_write(bp, phy,
7163                          MDIO_PMA_DEVAD,
7164                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7165         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7166
7167         DP(NETIF_MSG_LINK,
7168                  "bnx2x_8073_8727_external_rom_boot port %x:"
7169                  "Download complete. fw version = 0x%x\n",
7170                  port, fw_ver1);
7171
7172         return rc;
7173 }
7174
7175 /******************************************************************/
7176 /*                      BCM8073 PHY SECTION                       */
7177 /******************************************************************/
7178 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7179 {
7180         /* This is only required for 8073A1, version 102 only */
7181         u16 val;
7182
7183         /* Read 8073 HW revision*/
7184         bnx2x_cl45_read(bp, phy,
7185                         MDIO_PMA_DEVAD,
7186                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7187
7188         if (val != 1) {
7189                 /* No need to workaround in 8073 A1 */
7190                 return 0;
7191         }
7192
7193         bnx2x_cl45_read(bp, phy,
7194                         MDIO_PMA_DEVAD,
7195                         MDIO_PMA_REG_ROM_VER2, &val);
7196
7197         /* SNR should be applied only for version 0x102 */
7198         if (val != 0x102)
7199                 return 0;
7200
7201         return 1;
7202 }
7203
7204 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7205 {
7206         u16 val, cnt, cnt1 ;
7207
7208         bnx2x_cl45_read(bp, phy,
7209                         MDIO_PMA_DEVAD,
7210                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7211
7212         if (val > 0) {
7213                 /* No need to workaround in 8073 A1 */
7214                 return 0;
7215         }
7216         /* XAUI workaround in 8073 A0: */
7217
7218         /* After loading the boot ROM and restarting Autoneg, poll
7219          * Dev1, Reg $C820:
7220          */
7221
7222         for (cnt = 0; cnt < 1000; cnt++) {
7223                 bnx2x_cl45_read(bp, phy,
7224                                 MDIO_PMA_DEVAD,
7225                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7226                                 &val);
7227                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7228                    * system initialization (XAUI work-around not required, as
7229                    * these bits indicate 2.5G or 1G link up).
7230                    */
7231                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7232                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7233                         return 0;
7234                 } else if (!(val & (1<<15))) {
7235                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7236                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7237                          * MSB (bit15) goes to 1 (indicating that the XAUI
7238                          * workaround has completed), then continue on with
7239                          * system initialization.
7240                          */
7241                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7242                                 bnx2x_cl45_read(bp, phy,
7243                                         MDIO_PMA_DEVAD,
7244                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7245                                 if (val & (1<<15)) {
7246                                         DP(NETIF_MSG_LINK,
7247                                           "XAUI workaround has completed\n");
7248                                         return 0;
7249                                  }
7250                                  usleep_range(3000, 6000);
7251                         }
7252                         break;
7253                 }
7254                 usleep_range(3000, 6000);
7255         }
7256         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7257         return -EINVAL;
7258 }
7259
7260 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7261 {
7262         /* Force KR or KX */
7263         bnx2x_cl45_write(bp, phy,
7264                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7265         bnx2x_cl45_write(bp, phy,
7266                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7267         bnx2x_cl45_write(bp, phy,
7268                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7269         bnx2x_cl45_write(bp, phy,
7270                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7271 }
7272
7273 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7274                                       struct bnx2x_phy *phy,
7275                                       struct link_vars *vars)
7276 {
7277         u16 cl37_val;
7278         struct bnx2x *bp = params->bp;
7279         bnx2x_cl45_read(bp, phy,
7280                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7281
7282         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7283         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7284         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7285         if ((vars->ieee_fc &
7286             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7287             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7288                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7289         }
7290         if ((vars->ieee_fc &
7291             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7292             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7293                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7294         }
7295         if ((vars->ieee_fc &
7296             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7297             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7298                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7299         }
7300         DP(NETIF_MSG_LINK,
7301                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7302
7303         bnx2x_cl45_write(bp, phy,
7304                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7305         msleep(500);
7306 }
7307
7308 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7309                                      struct link_params *params,
7310                                      u32 action)
7311 {
7312         struct bnx2x *bp = params->bp;
7313         switch (action) {
7314         case PHY_INIT:
7315                 /* Enable LASI */
7316                 bnx2x_cl45_write(bp, phy,
7317                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7318                 bnx2x_cl45_write(bp, phy,
7319                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7320                 break;
7321         }
7322 }
7323
7324 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7325                                   struct link_params *params,
7326                                   struct link_vars *vars)
7327 {
7328         struct bnx2x *bp = params->bp;
7329         u16 val = 0, tmp1;
7330         u8 gpio_port;
7331         DP(NETIF_MSG_LINK, "Init 8073\n");
7332
7333         if (CHIP_IS_E2(bp))
7334                 gpio_port = BP_PATH(bp);
7335         else
7336                 gpio_port = params->port;
7337         /* Restore normal power mode*/
7338         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7339                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7340
7341         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7342                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7343
7344         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7345         bnx2x_8073_set_pause_cl37(params, phy, vars);
7346
7347         bnx2x_cl45_read(bp, phy,
7348                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7349
7350         bnx2x_cl45_read(bp, phy,
7351                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7352
7353         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7354
7355         /* Swap polarity if required - Must be done only in non-1G mode */
7356         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7357                 /* Configure the 8073 to swap _P and _N of the KR lines */
7358                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7359                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7360                 bnx2x_cl45_read(bp, phy,
7361                                 MDIO_PMA_DEVAD,
7362                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7363                 bnx2x_cl45_write(bp, phy,
7364                                  MDIO_PMA_DEVAD,
7365                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7366                                  (val | (3<<9)));
7367         }
7368
7369
7370         /* Enable CL37 BAM */
7371         if (REG_RD(bp, params->shmem_base +
7372                          offsetof(struct shmem_region, dev_info.
7373                                   port_hw_config[params->port].default_cfg)) &
7374             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7375
7376                 bnx2x_cl45_read(bp, phy,
7377                                 MDIO_AN_DEVAD,
7378                                 MDIO_AN_REG_8073_BAM, &val);
7379                 bnx2x_cl45_write(bp, phy,
7380                                  MDIO_AN_DEVAD,
7381                                  MDIO_AN_REG_8073_BAM, val | 1);
7382                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7383         }
7384         if (params->loopback_mode == LOOPBACK_EXT) {
7385                 bnx2x_807x_force_10G(bp, phy);
7386                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7387                 return 0;
7388         } else {
7389                 bnx2x_cl45_write(bp, phy,
7390                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7391         }
7392         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7393                 if (phy->req_line_speed == SPEED_10000) {
7394                         val = (1<<7);
7395                 } else if (phy->req_line_speed ==  SPEED_2500) {
7396                         val = (1<<5);
7397                         /* Note that 2.5G works only when used with 1G
7398                          * advertisement
7399                          */
7400                 } else
7401                         val = (1<<5);
7402         } else {
7403                 val = 0;
7404                 if (phy->speed_cap_mask &
7405                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7406                         val |= (1<<7);
7407
7408                 /* Note that 2.5G works only when used with 1G advertisement */
7409                 if (phy->speed_cap_mask &
7410                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7411                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7412                         val |= (1<<5);
7413                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7414         }
7415
7416         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7417         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7418
7419         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7420              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7421             (phy->req_line_speed == SPEED_2500)) {
7422                 u16 phy_ver;
7423                 /* Allow 2.5G for A1 and above */
7424                 bnx2x_cl45_read(bp, phy,
7425                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7426                                 &phy_ver);
7427                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7428                 if (phy_ver > 0)
7429                         tmp1 |= 1;
7430                 else
7431                         tmp1 &= 0xfffe;
7432         } else {
7433                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7434                 tmp1 &= 0xfffe;
7435         }
7436
7437         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7438         /* Add support for CL37 (passive mode) II */
7439
7440         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7441         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7442                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7443                                   0x20 : 0x40)));
7444
7445         /* Add support for CL37 (passive mode) III */
7446         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7447
7448         /* The SNR will improve about 2db by changing BW and FEE main
7449          * tap. Rest commands are executed after link is up
7450          * Change FFE main cursor to 5 in EDC register
7451          */
7452         if (bnx2x_8073_is_snr_needed(bp, phy))
7453                 bnx2x_cl45_write(bp, phy,
7454                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7455                                  0xFB0C);
7456
7457         /* Enable FEC (Forware Error Correction) Request in the AN */
7458         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7459         tmp1 |= (1<<15);
7460         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7461
7462         bnx2x_ext_phy_set_pause(params, phy, vars);
7463
7464         /* Restart autoneg */
7465         msleep(500);
7466         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7467         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7468                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7469         return 0;
7470 }
7471
7472 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7473                                  struct link_params *params,
7474                                  struct link_vars *vars)
7475 {
7476         struct bnx2x *bp = params->bp;
7477         u8 link_up = 0;
7478         u16 val1, val2;
7479         u16 link_status = 0;
7480         u16 an1000_status = 0;
7481
7482         bnx2x_cl45_read(bp, phy,
7483                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7484
7485         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7486
7487         /* Clear the interrupt LASI status register */
7488         bnx2x_cl45_read(bp, phy,
7489                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7490         bnx2x_cl45_read(bp, phy,
7491                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7492         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7493         /* Clear MSG-OUT */
7494         bnx2x_cl45_read(bp, phy,
7495                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7496
7497         /* Check the LASI */
7498         bnx2x_cl45_read(bp, phy,
7499                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7500
7501         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7502
7503         /* Check the link status */
7504         bnx2x_cl45_read(bp, phy,
7505                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7506         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7507
7508         bnx2x_cl45_read(bp, phy,
7509                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7510         bnx2x_cl45_read(bp, phy,
7511                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7512         link_up = ((val1 & 4) == 4);
7513         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7514
7515         if (link_up &&
7516              ((phy->req_line_speed != SPEED_10000))) {
7517                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7518                         return 0;
7519         }
7520         bnx2x_cl45_read(bp, phy,
7521                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7522         bnx2x_cl45_read(bp, phy,
7523                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7524
7525         /* Check the link status on 1.1.2 */
7526         bnx2x_cl45_read(bp, phy,
7527                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7528         bnx2x_cl45_read(bp, phy,
7529                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7530         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7531                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7532
7533         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7534         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7535                 /* The SNR will improve about 2dbby changing the BW and FEE main
7536                  * tap. The 1st write to change FFE main tap is set before
7537                  * restart AN. Change PLL Bandwidth in EDC register
7538                  */
7539                 bnx2x_cl45_write(bp, phy,
7540                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7541                                  0x26BC);
7542
7543                 /* Change CDR Bandwidth in EDC register */
7544                 bnx2x_cl45_write(bp, phy,
7545                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7546                                  0x0333);
7547         }
7548         bnx2x_cl45_read(bp, phy,
7549                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7550                         &link_status);
7551
7552         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7553         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7554                 link_up = 1;
7555                 vars->line_speed = SPEED_10000;
7556                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7557                            params->port);
7558         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7559                 link_up = 1;
7560                 vars->line_speed = SPEED_2500;
7561                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7562                            params->port);
7563         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7564                 link_up = 1;
7565                 vars->line_speed = SPEED_1000;
7566                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7567                            params->port);
7568         } else {
7569                 link_up = 0;
7570                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7571                            params->port);
7572         }
7573
7574         if (link_up) {
7575                 /* Swap polarity if required */
7576                 if (params->lane_config &
7577                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7578                         /* Configure the 8073 to swap P and N of the KR lines */
7579                         bnx2x_cl45_read(bp, phy,
7580                                         MDIO_XS_DEVAD,
7581                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7582                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7583                          * when it`s in 10G mode.
7584                          */
7585                         if (vars->line_speed == SPEED_1000) {
7586                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7587                                               "the 8073\n");
7588                                 val1 |= (1<<3);
7589                         } else
7590                                 val1 &= ~(1<<3);
7591
7592                         bnx2x_cl45_write(bp, phy,
7593                                          MDIO_XS_DEVAD,
7594                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7595                                          val1);
7596                 }
7597                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7598                 bnx2x_8073_resolve_fc(phy, params, vars);
7599                 vars->duplex = DUPLEX_FULL;
7600         }
7601
7602         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7603                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7604                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7605
7606                 if (val1 & (1<<5))
7607                         vars->link_status |=
7608                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7609                 if (val1 & (1<<7))
7610                         vars->link_status |=
7611                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7612         }
7613
7614         return link_up;
7615 }
7616
7617 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7618                                   struct link_params *params)
7619 {
7620         struct bnx2x *bp = params->bp;
7621         u8 gpio_port;
7622         if (CHIP_IS_E2(bp))
7623                 gpio_port = BP_PATH(bp);
7624         else
7625                 gpio_port = params->port;
7626         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7627            gpio_port);
7628         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7629                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7630                        gpio_port);
7631 }
7632
7633 /******************************************************************/
7634 /*                      BCM8705 PHY SECTION                       */
7635 /******************************************************************/
7636 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7637                                   struct link_params *params,
7638                                   struct link_vars *vars)
7639 {
7640         struct bnx2x *bp = params->bp;
7641         DP(NETIF_MSG_LINK, "init 8705\n");
7642         /* Restore normal power mode*/
7643         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7644                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7645         /* HW reset */
7646         bnx2x_ext_phy_hw_reset(bp, params->port);
7647         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7648         bnx2x_wait_reset_complete(bp, phy, params);
7649
7650         bnx2x_cl45_write(bp, phy,
7651                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7652         bnx2x_cl45_write(bp, phy,
7653                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7654         bnx2x_cl45_write(bp, phy,
7655                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7656         bnx2x_cl45_write(bp, phy,
7657                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7658         /* BCM8705 doesn't have microcode, hence the 0 */
7659         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7660         return 0;
7661 }
7662
7663 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7664                                  struct link_params *params,
7665                                  struct link_vars *vars)
7666 {
7667         u8 link_up = 0;
7668         u16 val1, rx_sd;
7669         struct bnx2x *bp = params->bp;
7670         DP(NETIF_MSG_LINK, "read status 8705\n");
7671         bnx2x_cl45_read(bp, phy,
7672                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7673         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7674
7675         bnx2x_cl45_read(bp, phy,
7676                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7677         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7678
7679         bnx2x_cl45_read(bp, phy,
7680                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7681
7682         bnx2x_cl45_read(bp, phy,
7683                       MDIO_PMA_DEVAD, 0xc809, &val1);
7684         bnx2x_cl45_read(bp, phy,
7685                       MDIO_PMA_DEVAD, 0xc809, &val1);
7686
7687         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7688         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7689         if (link_up) {
7690                 vars->line_speed = SPEED_10000;
7691                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7692         }
7693         return link_up;
7694 }
7695
7696 /******************************************************************/
7697 /*                      SFP+ module Section                       */
7698 /******************************************************************/
7699 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7700                                            struct bnx2x_phy *phy,
7701                                            u8 pmd_dis)
7702 {
7703         struct bnx2x *bp = params->bp;
7704         /* Disable transmitter only for bootcodes which can enable it afterwards
7705          * (for D3 link)
7706          */
7707         if (pmd_dis) {
7708                 if (params->feature_config_flags &
7709                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7710                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7711                 else {
7712                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7713                         return;
7714                 }
7715         } else
7716                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7717         bnx2x_cl45_write(bp, phy,
7718                          MDIO_PMA_DEVAD,
7719                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7720 }
7721
7722 static u8 bnx2x_get_gpio_port(struct link_params *params)
7723 {
7724         u8 gpio_port;
7725         u32 swap_val, swap_override;
7726         struct bnx2x *bp = params->bp;
7727         if (CHIP_IS_E2(bp))
7728                 gpio_port = BP_PATH(bp);
7729         else
7730                 gpio_port = params->port;
7731         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7732         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7733         return gpio_port ^ (swap_val && swap_override);
7734 }
7735
7736 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7737                                            struct bnx2x_phy *phy,
7738                                            u8 tx_en)
7739 {
7740         u16 val;
7741         u8 port = params->port;
7742         struct bnx2x *bp = params->bp;
7743         u32 tx_en_mode;
7744
7745         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7746         tx_en_mode = REG_RD(bp, params->shmem_base +
7747                             offsetof(struct shmem_region,
7748                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7749                 PORT_HW_CFG_TX_LASER_MASK;
7750         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7751                            "mode = %x\n", tx_en, port, tx_en_mode);
7752         switch (tx_en_mode) {
7753         case PORT_HW_CFG_TX_LASER_MDIO:
7754
7755                 bnx2x_cl45_read(bp, phy,
7756                                 MDIO_PMA_DEVAD,
7757                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7758                                 &val);
7759
7760                 if (tx_en)
7761                         val &= ~(1<<15);
7762                 else
7763                         val |= (1<<15);
7764
7765                 bnx2x_cl45_write(bp, phy,
7766                                  MDIO_PMA_DEVAD,
7767                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7768                                  val);
7769         break;
7770         case PORT_HW_CFG_TX_LASER_GPIO0:
7771         case PORT_HW_CFG_TX_LASER_GPIO1:
7772         case PORT_HW_CFG_TX_LASER_GPIO2:
7773         case PORT_HW_CFG_TX_LASER_GPIO3:
7774         {
7775                 u16 gpio_pin;
7776                 u8 gpio_port, gpio_mode;
7777                 if (tx_en)
7778                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7779                 else
7780                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7781
7782                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7783                 gpio_port = bnx2x_get_gpio_port(params);
7784                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7785                 break;
7786         }
7787         default:
7788                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7789                 break;
7790         }
7791 }
7792
7793 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7794                                       struct bnx2x_phy *phy,
7795                                       u8 tx_en)
7796 {
7797         struct bnx2x *bp = params->bp;
7798         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7799         if (CHIP_IS_E3(bp))
7800                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7801         else
7802                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7803 }
7804
7805 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7806                                              struct link_params *params,
7807                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7808                                              u8 *o_buf, u8 is_init)
7809 {
7810         struct bnx2x *bp = params->bp;
7811         u16 val = 0;
7812         u16 i;
7813         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7814                 DP(NETIF_MSG_LINK,
7815                    "Reading from eeprom is limited to 0xf\n");
7816                 return -EINVAL;
7817         }
7818         /* Set the read command byte count */
7819         bnx2x_cl45_write(bp, phy,
7820                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7821                          (byte_cnt | (dev_addr << 8)));
7822
7823         /* Set the read command address */
7824         bnx2x_cl45_write(bp, phy,
7825                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7826                          addr);
7827
7828         /* Activate read command */
7829         bnx2x_cl45_write(bp, phy,
7830                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7831                          0x2c0f);
7832
7833         /* Wait up to 500us for command complete status */
7834         for (i = 0; i < 100; i++) {
7835                 bnx2x_cl45_read(bp, phy,
7836                                 MDIO_PMA_DEVAD,
7837                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7838                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7839                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7840                         break;
7841                 udelay(5);
7842         }
7843
7844         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7845                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7846                 DP(NETIF_MSG_LINK,
7847                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7848                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7849                 return -EINVAL;
7850         }
7851
7852         /* Read the buffer */
7853         for (i = 0; i < byte_cnt; i++) {
7854                 bnx2x_cl45_read(bp, phy,
7855                                 MDIO_PMA_DEVAD,
7856                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7857                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7858         }
7859
7860         for (i = 0; i < 100; i++) {
7861                 bnx2x_cl45_read(bp, phy,
7862                                 MDIO_PMA_DEVAD,
7863                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7864                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7865                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7866                         return 0;
7867                 usleep_range(1000, 2000);
7868         }
7869         return -EINVAL;
7870 }
7871
7872 static void bnx2x_warpcore_power_module(struct link_params *params,
7873                                         u8 power)
7874 {
7875         u32 pin_cfg;
7876         struct bnx2x *bp = params->bp;
7877
7878         pin_cfg = (REG_RD(bp, params->shmem_base +
7879                           offsetof(struct shmem_region,
7880                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7881                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7882                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7883
7884         if (pin_cfg == PIN_CFG_NA)
7885                 return;
7886         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
7887                        power, pin_cfg);
7888         /* Low ==> corresponding SFP+ module is powered
7889          * high ==> the SFP+ module is powered down
7890          */
7891         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
7892 }
7893 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7894                                                  struct link_params *params,
7895                                                  u8 dev_addr,
7896                                                  u16 addr, u8 byte_cnt,
7897                                                  u8 *o_buf, u8 is_init)
7898 {
7899         int rc = 0;
7900         u8 i, j = 0, cnt = 0;
7901         u32 data_array[4];
7902         u16 addr32;
7903         struct bnx2x *bp = params->bp;
7904
7905         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7906                 DP(NETIF_MSG_LINK,
7907                    "Reading from eeprom is limited to 16 bytes\n");
7908                 return -EINVAL;
7909         }
7910
7911         /* 4 byte aligned address */
7912         addr32 = addr & (~0x3);
7913         do {
7914                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
7915                         bnx2x_warpcore_power_module(params, 0);
7916                         /* Note that 100us are not enough here */
7917                         usleep_range(1000, 2000);
7918                         bnx2x_warpcore_power_module(params, 1);
7919                 }
7920                 rc = bnx2x_bsc_read(params, phy, dev_addr, addr32, 0, byte_cnt,
7921                                     data_array);
7922         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
7923
7924         if (rc == 0) {
7925                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
7926                         o_buf[j] = *((u8 *)data_array + i);
7927                         j++;
7928                 }
7929         }
7930
7931         return rc;
7932 }
7933
7934 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7935                                              struct link_params *params,
7936                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7937                                              u8 *o_buf, u8 is_init)
7938 {
7939         struct bnx2x *bp = params->bp;
7940         u16 val, i;
7941
7942         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7943                 DP(NETIF_MSG_LINK,
7944                    "Reading from eeprom is limited to 0xf\n");
7945                 return -EINVAL;
7946         }
7947
7948         /* Set 2-wire transfer rate of SFP+ module EEPROM
7949          * to 100Khz since some DACs(direct attached cables) do
7950          * not work at 400Khz.
7951          */
7952         bnx2x_cl45_write(bp, phy,
7953                          MDIO_PMA_DEVAD,
7954                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
7955                          ((dev_addr << 8) | 1));
7956
7957         /* Need to read from 1.8000 to clear it */
7958         bnx2x_cl45_read(bp, phy,
7959                         MDIO_PMA_DEVAD,
7960                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7961                         &val);
7962
7963         /* Set the read command byte count */
7964         bnx2x_cl45_write(bp, phy,
7965                          MDIO_PMA_DEVAD,
7966                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7967                          ((byte_cnt < 2) ? 2 : byte_cnt));
7968
7969         /* Set the read command address */
7970         bnx2x_cl45_write(bp, phy,
7971                          MDIO_PMA_DEVAD,
7972                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7973                          addr);
7974         /* Set the destination address */
7975         bnx2x_cl45_write(bp, phy,
7976                          MDIO_PMA_DEVAD,
7977                          0x8004,
7978                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
7979
7980         /* Activate read command */
7981         bnx2x_cl45_write(bp, phy,
7982                          MDIO_PMA_DEVAD,
7983                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7984                          0x8002);
7985         /* Wait appropriate time for two-wire command to finish before
7986          * polling the status register
7987          */
7988         usleep_range(1000, 2000);
7989
7990         /* Wait up to 500us for command complete status */
7991         for (i = 0; i < 100; i++) {
7992                 bnx2x_cl45_read(bp, phy,
7993                                 MDIO_PMA_DEVAD,
7994                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7995                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7996                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7997                         break;
7998                 udelay(5);
7999         }
8000
8001         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8002                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8003                 DP(NETIF_MSG_LINK,
8004                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8005                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8006                 return -EFAULT;
8007         }
8008
8009         /* Read the buffer */
8010         for (i = 0; i < byte_cnt; i++) {
8011                 bnx2x_cl45_read(bp, phy,
8012                                 MDIO_PMA_DEVAD,
8013                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8014                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8015         }
8016
8017         for (i = 0; i < 100; i++) {
8018                 bnx2x_cl45_read(bp, phy,
8019                                 MDIO_PMA_DEVAD,
8020                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8021                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8022                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8023                         return 0;
8024                 usleep_range(1000, 2000);
8025         }
8026
8027         return -EINVAL;
8028 }
8029 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8030                                  struct link_params *params, u8 dev_addr,
8031                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8032 {
8033         int rc = 0;
8034         struct bnx2x *bp = params->bp;
8035         u8 xfer_size;
8036         u8 *user_data = o_buf;
8037         read_sfp_module_eeprom_func_p read_func;
8038
8039         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8040                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8041                 return -EINVAL;
8042         }
8043
8044         switch (phy->type) {
8045         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8046                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8047                 break;
8048         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8049         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8050                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8051                 break;
8052         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8053                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8054                 break;
8055         default:
8056                 return -EOPNOTSUPP;
8057         }
8058
8059         while (!rc && (byte_cnt > 0)) {
8060                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8061                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8062                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8063                                user_data, 0);
8064                 byte_cnt -= xfer_size;
8065                 user_data += xfer_size;
8066                 addr += xfer_size;
8067         }
8068         return rc;
8069 }
8070
8071 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8072                               struct link_params *params,
8073                               u16 *edc_mode)
8074 {
8075         struct bnx2x *bp = params->bp;
8076         u32 sync_offset = 0, phy_idx, media_types;
8077         u8 gport, val[2], check_limiting_mode = 0;
8078         *edc_mode = EDC_MODE_LIMITING;
8079         phy->media_type = ETH_PHY_UNSPECIFIED;
8080         /* First check for copper cable */
8081         if (bnx2x_read_sfp_module_eeprom(phy,
8082                                          params,
8083                                          I2C_DEV_ADDR_A0,
8084                                          SFP_EEPROM_CON_TYPE_ADDR,
8085                                          2,
8086                                          (u8 *)val) != 0) {
8087                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8088                 return -EINVAL;
8089         }
8090
8091         switch (val[0]) {
8092         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8093         {
8094                 u8 copper_module_type;
8095                 phy->media_type = ETH_PHY_DA_TWINAX;
8096                 /* Check if its active cable (includes SFP+ module)
8097                  * of passive cable
8098                  */
8099                 if (bnx2x_read_sfp_module_eeprom(phy,
8100                                                params,
8101                                                I2C_DEV_ADDR_A0,
8102                                                SFP_EEPROM_FC_TX_TECH_ADDR,
8103                                                1,
8104                                                &copper_module_type) != 0) {
8105                         DP(NETIF_MSG_LINK,
8106                                 "Failed to read copper-cable-type"
8107                                 " from SFP+ EEPROM\n");
8108                         return -EINVAL;
8109                 }
8110
8111                 if (copper_module_type &
8112                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8113                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8114                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8115                                 *edc_mode = EDC_MODE_ACTIVE_DAC;
8116                         else
8117                                 check_limiting_mode = 1;
8118                 } else if (copper_module_type &
8119                         SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8120                                 DP(NETIF_MSG_LINK,
8121                                    "Passive Copper cable detected\n");
8122                                 *edc_mode =
8123                                       EDC_MODE_PASSIVE_DAC;
8124                 } else {
8125                         DP(NETIF_MSG_LINK,
8126                            "Unknown copper-cable-type 0x%x !!!\n",
8127                            copper_module_type);
8128                         return -EINVAL;
8129                 }
8130                 break;
8131         }
8132         case SFP_EEPROM_CON_TYPE_VAL_LC:
8133         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8134                 check_limiting_mode = 1;
8135                 if ((val[1] & (SFP_EEPROM_COMP_CODE_SR_MASK |
8136                                SFP_EEPROM_COMP_CODE_LR_MASK |
8137                                SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8138                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8139                         gport = params->port;
8140                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8141                         if (phy->req_line_speed != SPEED_1000) {
8142                                 phy->req_line_speed = SPEED_1000;
8143                                 if (!CHIP_IS_E1x(bp)) {
8144                                         gport = BP_PATH(bp) +
8145                                         (params->port << 1);
8146                                 }
8147                                 netdev_err(bp->dev,
8148                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8149                                            gport);
8150                         }
8151                 } else {
8152                         int idx, cfg_idx = 0;
8153                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8154                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8155                                 if (params->phy[idx].type == phy->type) {
8156                                         cfg_idx = LINK_CONFIG_IDX(idx);
8157                                         break;
8158                                 }
8159                         }
8160                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8161                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8162                 }
8163                 break;
8164         default:
8165                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8166                          val[0]);
8167                 return -EINVAL;
8168         }
8169         sync_offset = params->shmem_base +
8170                 offsetof(struct shmem_region,
8171                          dev_info.port_hw_config[params->port].media_type);
8172         media_types = REG_RD(bp, sync_offset);
8173         /* Update media type for non-PMF sync */
8174         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8175                 if (&(params->phy[phy_idx]) == phy) {
8176                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8177                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8178                         media_types |= ((phy->media_type &
8179                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8180                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8181                         break;
8182                 }
8183         }
8184         REG_WR(bp, sync_offset, media_types);
8185         if (check_limiting_mode) {
8186                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8187                 if (bnx2x_read_sfp_module_eeprom(phy,
8188                                                  params,
8189                                                  I2C_DEV_ADDR_A0,
8190                                                  SFP_EEPROM_OPTIONS_ADDR,
8191                                                  SFP_EEPROM_OPTIONS_SIZE,
8192                                                  options) != 0) {
8193                         DP(NETIF_MSG_LINK,
8194                            "Failed to read Option field from module EEPROM\n");
8195                         return -EINVAL;
8196                 }
8197                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8198                         *edc_mode = EDC_MODE_LINEAR;
8199                 else
8200                         *edc_mode = EDC_MODE_LIMITING;
8201         }
8202         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8203         return 0;
8204 }
8205 /* This function read the relevant field from the module (SFP+), and verify it
8206  * is compliant with this board
8207  */
8208 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8209                                    struct link_params *params)
8210 {
8211         struct bnx2x *bp = params->bp;
8212         u32 val, cmd;
8213         u32 fw_resp, fw_cmd_param;
8214         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8215         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8216         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8217         val = REG_RD(bp, params->shmem_base +
8218                          offsetof(struct shmem_region, dev_info.
8219                                   port_feature_config[params->port].config));
8220         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8221             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8222                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8223                 return 0;
8224         }
8225
8226         if (params->feature_config_flags &
8227             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8228                 /* Use specific phy request */
8229                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8230         } else if (params->feature_config_flags &
8231                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8232                 /* Use first phy request only in case of non-dual media*/
8233                 if (DUAL_MEDIA(params)) {
8234                         DP(NETIF_MSG_LINK,
8235                            "FW does not support OPT MDL verification\n");
8236                         return -EINVAL;
8237                 }
8238                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8239         } else {
8240                 /* No support in OPT MDL detection */
8241                 DP(NETIF_MSG_LINK,
8242                    "FW does not support OPT MDL verification\n");
8243                 return -EINVAL;
8244         }
8245
8246         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8247         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8248         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8249                 DP(NETIF_MSG_LINK, "Approved module\n");
8250                 return 0;
8251         }
8252
8253         /* Format the warning message */
8254         if (bnx2x_read_sfp_module_eeprom(phy,
8255                                          params,
8256                                          I2C_DEV_ADDR_A0,
8257                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8258                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8259                                          (u8 *)vendor_name))
8260                 vendor_name[0] = '\0';
8261         else
8262                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8263         if (bnx2x_read_sfp_module_eeprom(phy,
8264                                          params,
8265                                          I2C_DEV_ADDR_A0,
8266                                          SFP_EEPROM_PART_NO_ADDR,
8267                                          SFP_EEPROM_PART_NO_SIZE,
8268                                          (u8 *)vendor_pn))
8269                 vendor_pn[0] = '\0';
8270         else
8271                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8272
8273         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8274                               " Port %d from %s part number %s\n",
8275                          params->port, vendor_name, vendor_pn);
8276         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8277             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8278                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8279         return -EINVAL;
8280 }
8281
8282 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8283                                                  struct link_params *params)
8284
8285 {
8286         u8 val;
8287         int rc;
8288         struct bnx2x *bp = params->bp;
8289         u16 timeout;
8290         /* Initialization time after hot-plug may take up to 300ms for
8291          * some phys type ( e.g. JDSU )
8292          */
8293
8294         for (timeout = 0; timeout < 60; timeout++) {
8295                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8296                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8297                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8298                                 1);
8299                 else
8300                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8301                                                           I2C_DEV_ADDR_A0,
8302                                                           1, 1, &val);
8303                 if (rc == 0) {
8304                         DP(NETIF_MSG_LINK,
8305                            "SFP+ module initialization took %d ms\n",
8306                            timeout * 5);
8307                         return 0;
8308                 }
8309                 usleep_range(5000, 10000);
8310         }
8311         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8312                                           1, 1, &val);
8313         return rc;
8314 }
8315
8316 static void bnx2x_8727_power_module(struct bnx2x *bp,
8317                                     struct bnx2x_phy *phy,
8318                                     u8 is_power_up) {
8319         /* Make sure GPIOs are not using for LED mode */
8320         u16 val;
8321         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8322          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8323          * output
8324          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8325          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8326          * where the 1st bit is the over-current(only input), and 2nd bit is
8327          * for power( only output )
8328          *
8329          * In case of NOC feature is disabled and power is up, set GPIO control
8330          *  as input to enable listening of over-current indication
8331          */
8332         if (phy->flags & FLAGS_NOC)
8333                 return;
8334         if (is_power_up)
8335                 val = (1<<4);
8336         else
8337                 /* Set GPIO control to OUTPUT, and set the power bit
8338                  * to according to the is_power_up
8339                  */
8340                 val = (1<<1);
8341
8342         bnx2x_cl45_write(bp, phy,
8343                          MDIO_PMA_DEVAD,
8344                          MDIO_PMA_REG_8727_GPIO_CTRL,
8345                          val);
8346 }
8347
8348 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8349                                         struct bnx2x_phy *phy,
8350                                         u16 edc_mode)
8351 {
8352         u16 cur_limiting_mode;
8353
8354         bnx2x_cl45_read(bp, phy,
8355                         MDIO_PMA_DEVAD,
8356                         MDIO_PMA_REG_ROM_VER2,
8357                         &cur_limiting_mode);
8358         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8359                  cur_limiting_mode);
8360
8361         if (edc_mode == EDC_MODE_LIMITING) {
8362                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8363                 bnx2x_cl45_write(bp, phy,
8364                                  MDIO_PMA_DEVAD,
8365                                  MDIO_PMA_REG_ROM_VER2,
8366                                  EDC_MODE_LIMITING);
8367         } else { /* LRM mode ( default )*/
8368
8369                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8370
8371                 /* Changing to LRM mode takes quite few seconds. So do it only
8372                  * if current mode is limiting (default is LRM)
8373                  */
8374                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8375                         return 0;
8376
8377                 bnx2x_cl45_write(bp, phy,
8378                                  MDIO_PMA_DEVAD,
8379                                  MDIO_PMA_REG_LRM_MODE,
8380                                  0);
8381                 bnx2x_cl45_write(bp, phy,
8382                                  MDIO_PMA_DEVAD,
8383                                  MDIO_PMA_REG_ROM_VER2,
8384                                  0x128);
8385                 bnx2x_cl45_write(bp, phy,
8386                                  MDIO_PMA_DEVAD,
8387                                  MDIO_PMA_REG_MISC_CTRL0,
8388                                  0x4008);
8389                 bnx2x_cl45_write(bp, phy,
8390                                  MDIO_PMA_DEVAD,
8391                                  MDIO_PMA_REG_LRM_MODE,
8392                                  0xaaaa);
8393         }
8394         return 0;
8395 }
8396
8397 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8398                                         struct bnx2x_phy *phy,
8399                                         u16 edc_mode)
8400 {
8401         u16 phy_identifier;
8402         u16 rom_ver2_val;
8403         bnx2x_cl45_read(bp, phy,
8404                         MDIO_PMA_DEVAD,
8405                         MDIO_PMA_REG_PHY_IDENTIFIER,
8406                         &phy_identifier);
8407
8408         bnx2x_cl45_write(bp, phy,
8409                          MDIO_PMA_DEVAD,
8410                          MDIO_PMA_REG_PHY_IDENTIFIER,
8411                          (phy_identifier & ~(1<<9)));
8412
8413         bnx2x_cl45_read(bp, phy,
8414                         MDIO_PMA_DEVAD,
8415                         MDIO_PMA_REG_ROM_VER2,
8416                         &rom_ver2_val);
8417         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8418         bnx2x_cl45_write(bp, phy,
8419                          MDIO_PMA_DEVAD,
8420                          MDIO_PMA_REG_ROM_VER2,
8421                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8422
8423         bnx2x_cl45_write(bp, phy,
8424                          MDIO_PMA_DEVAD,
8425                          MDIO_PMA_REG_PHY_IDENTIFIER,
8426                          (phy_identifier | (1<<9)));
8427
8428         return 0;
8429 }
8430
8431 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8432                                      struct link_params *params,
8433                                      u32 action)
8434 {
8435         struct bnx2x *bp = params->bp;
8436         u16 val;
8437         switch (action) {
8438         case DISABLE_TX:
8439                 bnx2x_sfp_set_transmitter(params, phy, 0);
8440                 break;
8441         case ENABLE_TX:
8442                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8443                         bnx2x_sfp_set_transmitter(params, phy, 1);
8444                 break;
8445         case PHY_INIT:
8446                 bnx2x_cl45_write(bp, phy,
8447                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8448                                  (1<<2) | (1<<5));
8449                 bnx2x_cl45_write(bp, phy,
8450                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8451                                  0);
8452                 bnx2x_cl45_write(bp, phy,
8453                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8454                 /* Make MOD_ABS give interrupt on change */
8455                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8456                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8457                                 &val);
8458                 val |= (1<<12);
8459                 if (phy->flags & FLAGS_NOC)
8460                         val |= (3<<5);
8461                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8462                  * status which reflect SFP+ module over-current
8463                  */
8464                 if (!(phy->flags & FLAGS_NOC))
8465                         val &= 0xff8f; /* Reset bits 4-6 */
8466                 bnx2x_cl45_write(bp, phy,
8467                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8468                                  val);
8469                 break;
8470         default:
8471                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8472                    action);
8473                 return;
8474         }
8475 }
8476
8477 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8478                                            u8 gpio_mode)
8479 {
8480         struct bnx2x *bp = params->bp;
8481
8482         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8483                             offsetof(struct shmem_region,
8484                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8485                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8486         switch (fault_led_gpio) {
8487         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8488                 return;
8489         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8490         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8491         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8492         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8493         {
8494                 u8 gpio_port = bnx2x_get_gpio_port(params);
8495                 u16 gpio_pin = fault_led_gpio -
8496                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8497                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8498                                    "pin %x port %x mode %x\n",
8499                                gpio_pin, gpio_port, gpio_mode);
8500                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8501         }
8502         break;
8503         default:
8504                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8505                                fault_led_gpio);
8506         }
8507 }
8508
8509 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8510                                           u8 gpio_mode)
8511 {
8512         u32 pin_cfg;
8513         u8 port = params->port;
8514         struct bnx2x *bp = params->bp;
8515         pin_cfg = (REG_RD(bp, params->shmem_base +
8516                          offsetof(struct shmem_region,
8517                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8518                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8519                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8520         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8521                        gpio_mode, pin_cfg);
8522         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8523 }
8524
8525 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8526                                            u8 gpio_mode)
8527 {
8528         struct bnx2x *bp = params->bp;
8529         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8530         if (CHIP_IS_E3(bp)) {
8531                 /* Low ==> if SFP+ module is supported otherwise
8532                  * High ==> if SFP+ module is not on the approved vendor list
8533                  */
8534                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8535         } else
8536                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8537 }
8538
8539 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8540                                     struct link_params *params)
8541 {
8542         struct bnx2x *bp = params->bp;
8543         bnx2x_warpcore_power_module(params, 0);
8544         /* Put Warpcore in low power mode */
8545         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8546
8547         /* Put LCPLL in low power mode */
8548         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8549         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8550         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8551 }
8552
8553 static void bnx2x_power_sfp_module(struct link_params *params,
8554                                    struct bnx2x_phy *phy,
8555                                    u8 power)
8556 {
8557         struct bnx2x *bp = params->bp;
8558         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8559
8560         switch (phy->type) {
8561         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8562         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8563                 bnx2x_8727_power_module(params->bp, phy, power);
8564                 break;
8565         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8566                 bnx2x_warpcore_power_module(params, power);
8567                 break;
8568         default:
8569                 break;
8570         }
8571 }
8572 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8573                                              struct bnx2x_phy *phy,
8574                                              u16 edc_mode)
8575 {
8576         u16 val = 0;
8577         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8578         struct bnx2x *bp = params->bp;
8579
8580         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8581         /* This is a global register which controls all lanes */
8582         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8583                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8584         val &= ~(0xf << (lane << 2));
8585
8586         switch (edc_mode) {
8587         case EDC_MODE_LINEAR:
8588         case EDC_MODE_LIMITING:
8589                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8590                 break;
8591         case EDC_MODE_PASSIVE_DAC:
8592         case EDC_MODE_ACTIVE_DAC:
8593                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8594                 break;
8595         default:
8596                 break;
8597         }
8598
8599         val |= (mode << (lane << 2));
8600         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8601                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8602         /* A must read */
8603         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8604                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8605
8606         /* Restart microcode to re-read the new mode */
8607         bnx2x_warpcore_reset_lane(bp, phy, 1);
8608         bnx2x_warpcore_reset_lane(bp, phy, 0);
8609
8610 }
8611
8612 static void bnx2x_set_limiting_mode(struct link_params *params,
8613                                     struct bnx2x_phy *phy,
8614                                     u16 edc_mode)
8615 {
8616         switch (phy->type) {
8617         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8618                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8619                 break;
8620         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8621         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8622                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8623                 break;
8624         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8625                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8626                 break;
8627         }
8628 }
8629
8630 int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8631                                struct link_params *params)
8632 {
8633         struct bnx2x *bp = params->bp;
8634         u16 edc_mode;
8635         int rc = 0;
8636
8637         u32 val = REG_RD(bp, params->shmem_base +
8638                              offsetof(struct shmem_region, dev_info.
8639                                      port_feature_config[params->port].config));
8640         /* Enabled transmitter by default */
8641         bnx2x_sfp_set_transmitter(params, phy, 1);
8642         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8643                  params->port);
8644         /* Power up module */
8645         bnx2x_power_sfp_module(params, phy, 1);
8646         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8647                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8648                 return -EINVAL;
8649         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8650                 /* Check SFP+ module compatibility */
8651                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8652                 rc = -EINVAL;
8653                 /* Turn on fault module-detected led */
8654                 bnx2x_set_sfp_module_fault_led(params,
8655                                                MISC_REGISTERS_GPIO_HIGH);
8656
8657                 /* Check if need to power down the SFP+ module */
8658                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8659                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8660                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8661                         bnx2x_power_sfp_module(params, phy, 0);
8662                         return rc;
8663                 }
8664         } else {
8665                 /* Turn off fault module-detected led */
8666                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8667         }
8668
8669         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8670          * is done automatically
8671          */
8672         bnx2x_set_limiting_mode(params, phy, edc_mode);
8673
8674         /* Disable transmit for this module if the module is not approved, and
8675          * laser needs to be disabled.
8676          */
8677         if ((rc) &&
8678             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8679              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8680                 bnx2x_sfp_set_transmitter(params, phy, 0);
8681
8682         return rc;
8683 }
8684
8685 void bnx2x_handle_module_detect_int(struct link_params *params)
8686 {
8687         struct bnx2x *bp = params->bp;
8688         struct bnx2x_phy *phy;
8689         u32 gpio_val;
8690         u8 gpio_num, gpio_port;
8691         if (CHIP_IS_E3(bp)) {
8692                 phy = &params->phy[INT_PHY];
8693                 /* Always enable TX laser,will be disabled in case of fault */
8694                 bnx2x_sfp_set_transmitter(params, phy, 1);
8695         } else {
8696                 phy = &params->phy[EXT_PHY1];
8697         }
8698         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8699                                       params->port, &gpio_num, &gpio_port) ==
8700             -EINVAL) {
8701                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8702                 return;
8703         }
8704
8705         /* Set valid module led off */
8706         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8707
8708         /* Get current gpio val reflecting module plugged in / out*/
8709         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8710
8711         /* Call the handling function in case module is detected */
8712         if (gpio_val == 0) {
8713                 bnx2x_set_mdio_emac_per_phy(bp, params);
8714                 bnx2x_set_aer_mmd(params, phy);
8715
8716                 bnx2x_power_sfp_module(params, phy, 1);
8717                 bnx2x_set_gpio_int(bp, gpio_num,
8718                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8719                                    gpio_port);
8720                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8721                         bnx2x_sfp_module_detection(phy, params);
8722                         if (CHIP_IS_E3(bp)) {
8723                                 u16 rx_tx_in_reset;
8724                                 /* In case WC is out of reset, reconfigure the
8725                                  * link speed while taking into account 1G
8726                                  * module limitation.
8727                                  */
8728                                 bnx2x_cl45_read(bp, phy,
8729                                                 MDIO_WC_DEVAD,
8730                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8731                                                 &rx_tx_in_reset);
8732                                 if ((!rx_tx_in_reset) &&
8733                                     (params->link_flags &
8734                                      PHY_INITIALIZED)) {
8735                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8736                                         bnx2x_warpcore_config_sfi(phy, params);
8737                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8738                                 }
8739                         }
8740                 } else {
8741                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8742                 }
8743         } else {
8744                 bnx2x_set_gpio_int(bp, gpio_num,
8745                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8746                                    gpio_port);
8747                 /* Module was plugged out.
8748                  * Disable transmit for this module
8749                  */
8750                 phy->media_type = ETH_PHY_NOT_PRESENT;
8751         }
8752 }
8753
8754 /******************************************************************/
8755 /*              Used by 8706 and 8727                             */
8756 /******************************************************************/
8757 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8758                                  struct bnx2x_phy *phy,
8759                                  u16 alarm_status_offset,
8760                                  u16 alarm_ctrl_offset)
8761 {
8762         u16 alarm_status, val;
8763         bnx2x_cl45_read(bp, phy,
8764                         MDIO_PMA_DEVAD, alarm_status_offset,
8765                         &alarm_status);
8766         bnx2x_cl45_read(bp, phy,
8767                         MDIO_PMA_DEVAD, alarm_status_offset,
8768                         &alarm_status);
8769         /* Mask or enable the fault event. */
8770         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8771         if (alarm_status & (1<<0))
8772                 val &= ~(1<<0);
8773         else
8774                 val |= (1<<0);
8775         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8776 }
8777 /******************************************************************/
8778 /*              common BCM8706/BCM8726 PHY SECTION                */
8779 /******************************************************************/
8780 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8781                                       struct link_params *params,
8782                                       struct link_vars *vars)
8783 {
8784         u8 link_up = 0;
8785         u16 val1, val2, rx_sd, pcs_status;
8786         struct bnx2x *bp = params->bp;
8787         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8788         /* Clear RX Alarm*/
8789         bnx2x_cl45_read(bp, phy,
8790                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8791
8792         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8793                              MDIO_PMA_LASI_TXCTRL);
8794
8795         /* Clear LASI indication*/
8796         bnx2x_cl45_read(bp, phy,
8797                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8798         bnx2x_cl45_read(bp, phy,
8799                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8800         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8801
8802         bnx2x_cl45_read(bp, phy,
8803                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8804         bnx2x_cl45_read(bp, phy,
8805                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8806         bnx2x_cl45_read(bp, phy,
8807                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8808         bnx2x_cl45_read(bp, phy,
8809                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8810
8811         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8812                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8813         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8814          * are set, or if the autoneg bit 1 is set
8815          */
8816         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8817         if (link_up) {
8818                 if (val2 & (1<<1))
8819                         vars->line_speed = SPEED_1000;
8820                 else
8821                         vars->line_speed = SPEED_10000;
8822                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8823                 vars->duplex = DUPLEX_FULL;
8824         }
8825
8826         /* Capture 10G link fault. Read twice to clear stale value. */
8827         if (vars->line_speed == SPEED_10000) {
8828                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8829                             MDIO_PMA_LASI_TXSTAT, &val1);
8830                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8831                             MDIO_PMA_LASI_TXSTAT, &val1);
8832                 if (val1 & (1<<0))
8833                         vars->fault_detected = 1;
8834         }
8835
8836         return link_up;
8837 }
8838
8839 /******************************************************************/
8840 /*                      BCM8706 PHY SECTION                       */
8841 /******************************************************************/
8842 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8843                                  struct link_params *params,
8844                                  struct link_vars *vars)
8845 {
8846         u32 tx_en_mode;
8847         u16 cnt, val, tmp1;
8848         struct bnx2x *bp = params->bp;
8849
8850         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8851                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8852         /* HW reset */
8853         bnx2x_ext_phy_hw_reset(bp, params->port);
8854         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8855         bnx2x_wait_reset_complete(bp, phy, params);
8856
8857         /* Wait until fw is loaded */
8858         for (cnt = 0; cnt < 100; cnt++) {
8859                 bnx2x_cl45_read(bp, phy,
8860                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8861                 if (val)
8862                         break;
8863                 usleep_range(10000, 20000);
8864         }
8865         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8866         if ((params->feature_config_flags &
8867              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8868                 u8 i;
8869                 u16 reg;
8870                 for (i = 0; i < 4; i++) {
8871                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8872                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8873                                    MDIO_XS_8706_REG_BANK_RX0);
8874                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8875                         /* Clear first 3 bits of the control */
8876                         val &= ~0x7;
8877                         /* Set control bits according to configuration */
8878                         val |= (phy->rx_preemphasis[i] & 0x7);
8879                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
8880                                    " reg 0x%x <-- val 0x%x\n", reg, val);
8881                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
8882                 }
8883         }
8884         /* Force speed */
8885         if (phy->req_line_speed == SPEED_10000) {
8886                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
8887
8888                 bnx2x_cl45_write(bp, phy,
8889                                  MDIO_PMA_DEVAD,
8890                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
8891                 bnx2x_cl45_write(bp, phy,
8892                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8893                                  0);
8894                 /* Arm LASI for link and Tx fault. */
8895                 bnx2x_cl45_write(bp, phy,
8896                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
8897         } else {
8898                 /* Force 1Gbps using autoneg with 1G advertisement */
8899
8900                 /* Allow CL37 through CL73 */
8901                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
8902                 bnx2x_cl45_write(bp, phy,
8903                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
8904
8905                 /* Enable Full-Duplex advertisement on CL37 */
8906                 bnx2x_cl45_write(bp, phy,
8907                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
8908                 /* Enable CL37 AN */
8909                 bnx2x_cl45_write(bp, phy,
8910                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8911                 /* 1G support */
8912                 bnx2x_cl45_write(bp, phy,
8913                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
8914
8915                 /* Enable clause 73 AN */
8916                 bnx2x_cl45_write(bp, phy,
8917                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8918                 bnx2x_cl45_write(bp, phy,
8919                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8920                                  0x0400);
8921                 bnx2x_cl45_write(bp, phy,
8922                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
8923                                  0x0004);
8924         }
8925         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
8926
8927         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8928          * power mode, if TX Laser is disabled
8929          */
8930
8931         tx_en_mode = REG_RD(bp, params->shmem_base +
8932                             offsetof(struct shmem_region,
8933                                 dev_info.port_hw_config[params->port].sfp_ctrl))
8934                         & PORT_HW_CFG_TX_LASER_MASK;
8935
8936         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
8937                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
8938                 bnx2x_cl45_read(bp, phy,
8939                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
8940                 tmp1 |= 0x1;
8941                 bnx2x_cl45_write(bp, phy,
8942                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
8943         }
8944
8945         return 0;
8946 }
8947
8948 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
8949                                   struct link_params *params,
8950                                   struct link_vars *vars)
8951 {
8952         return bnx2x_8706_8726_read_status(phy, params, vars);
8953 }
8954
8955 /******************************************************************/
8956 /*                      BCM8726 PHY SECTION                       */
8957 /******************************************************************/
8958 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
8959                                        struct link_params *params)
8960 {
8961         struct bnx2x *bp = params->bp;
8962         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
8963         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
8964 }
8965
8966 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
8967                                          struct link_params *params)
8968 {
8969         struct bnx2x *bp = params->bp;
8970         /* Need to wait 100ms after reset */
8971         msleep(100);
8972
8973         /* Micro controller re-boot */
8974         bnx2x_cl45_write(bp, phy,
8975                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
8976
8977         /* Set soft reset */
8978         bnx2x_cl45_write(bp, phy,
8979                          MDIO_PMA_DEVAD,
8980                          MDIO_PMA_REG_GEN_CTRL,
8981                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8982
8983         bnx2x_cl45_write(bp, phy,
8984                          MDIO_PMA_DEVAD,
8985                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8986
8987         bnx2x_cl45_write(bp, phy,
8988                          MDIO_PMA_DEVAD,
8989                          MDIO_PMA_REG_GEN_CTRL,
8990                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8991
8992         /* Wait for 150ms for microcode load */
8993         msleep(150);
8994
8995         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8996         bnx2x_cl45_write(bp, phy,
8997                          MDIO_PMA_DEVAD,
8998                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8999
9000         msleep(200);
9001         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9002 }
9003
9004 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9005                                  struct link_params *params,
9006                                  struct link_vars *vars)
9007 {
9008         struct bnx2x *bp = params->bp;
9009         u16 val1;
9010         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9011         if (link_up) {
9012                 bnx2x_cl45_read(bp, phy,
9013                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9014                                 &val1);
9015                 if (val1 & (1<<15)) {
9016                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
9017                         link_up = 0;
9018                         vars->line_speed = 0;
9019                 }
9020         }
9021         return link_up;
9022 }
9023
9024
9025 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9026                                   struct link_params *params,
9027                                   struct link_vars *vars)
9028 {
9029         struct bnx2x *bp = params->bp;
9030         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9031
9032         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9033         bnx2x_wait_reset_complete(bp, phy, params);
9034
9035         bnx2x_8726_external_rom_boot(phy, params);
9036
9037         /* Need to call module detected on initialization since the module
9038          * detection triggered by actual module insertion might occur before
9039          * driver is loaded, and when driver is loaded, it reset all
9040          * registers, including the transmitter
9041          */
9042         bnx2x_sfp_module_detection(phy, params);
9043
9044         if (phy->req_line_speed == SPEED_1000) {
9045                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9046                 bnx2x_cl45_write(bp, phy,
9047                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9048                 bnx2x_cl45_write(bp, phy,
9049                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9050                 bnx2x_cl45_write(bp, phy,
9051                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9052                 bnx2x_cl45_write(bp, phy,
9053                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9054                                  0x400);
9055         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9056                    (phy->speed_cap_mask &
9057                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9058                    ((phy->speed_cap_mask &
9059                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9060                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9061                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9062                 /* Set Flow control */
9063                 bnx2x_ext_phy_set_pause(params, phy, vars);
9064                 bnx2x_cl45_write(bp, phy,
9065                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9066                 bnx2x_cl45_write(bp, phy,
9067                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9068                 bnx2x_cl45_write(bp, phy,
9069                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9070                 bnx2x_cl45_write(bp, phy,
9071                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9072                 bnx2x_cl45_write(bp, phy,
9073                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9074                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9075                  * change
9076                  */
9077                 bnx2x_cl45_write(bp, phy,
9078                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9079                 bnx2x_cl45_write(bp, phy,
9080                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9081                                  0x400);
9082
9083         } else { /* Default 10G. Set only LASI control */
9084                 bnx2x_cl45_write(bp, phy,
9085                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9086         }
9087
9088         /* Set TX PreEmphasis if needed */
9089         if ((params->feature_config_flags &
9090              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9091                 DP(NETIF_MSG_LINK,
9092                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9093                          phy->tx_preemphasis[0],
9094                          phy->tx_preemphasis[1]);
9095                 bnx2x_cl45_write(bp, phy,
9096                                  MDIO_PMA_DEVAD,
9097                                  MDIO_PMA_REG_8726_TX_CTRL1,
9098                                  phy->tx_preemphasis[0]);
9099
9100                 bnx2x_cl45_write(bp, phy,
9101                                  MDIO_PMA_DEVAD,
9102                                  MDIO_PMA_REG_8726_TX_CTRL2,
9103                                  phy->tx_preemphasis[1]);
9104         }
9105
9106         return 0;
9107
9108 }
9109
9110 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9111                                   struct link_params *params)
9112 {
9113         struct bnx2x *bp = params->bp;
9114         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9115         /* Set serial boot control for external load */
9116         bnx2x_cl45_write(bp, phy,
9117                          MDIO_PMA_DEVAD,
9118                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9119 }
9120
9121 /******************************************************************/
9122 /*                      BCM8727 PHY SECTION                       */
9123 /******************************************************************/
9124
9125 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9126                                     struct link_params *params, u8 mode)
9127 {
9128         struct bnx2x *bp = params->bp;
9129         u16 led_mode_bitmask = 0;
9130         u16 gpio_pins_bitmask = 0;
9131         u16 val;
9132         /* Only NOC flavor requires to set the LED specifically */
9133         if (!(phy->flags & FLAGS_NOC))
9134                 return;
9135         switch (mode) {
9136         case LED_MODE_FRONT_PANEL_OFF:
9137         case LED_MODE_OFF:
9138                 led_mode_bitmask = 0;
9139                 gpio_pins_bitmask = 0x03;
9140                 break;
9141         case LED_MODE_ON:
9142                 led_mode_bitmask = 0;
9143                 gpio_pins_bitmask = 0x02;
9144                 break;
9145         case LED_MODE_OPER:
9146                 led_mode_bitmask = 0x60;
9147                 gpio_pins_bitmask = 0x11;
9148                 break;
9149         }
9150         bnx2x_cl45_read(bp, phy,
9151                         MDIO_PMA_DEVAD,
9152                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9153                         &val);
9154         val &= 0xff8f;
9155         val |= led_mode_bitmask;
9156         bnx2x_cl45_write(bp, phy,
9157                          MDIO_PMA_DEVAD,
9158                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9159                          val);
9160         bnx2x_cl45_read(bp, phy,
9161                         MDIO_PMA_DEVAD,
9162                         MDIO_PMA_REG_8727_GPIO_CTRL,
9163                         &val);
9164         val &= 0xffe0;
9165         val |= gpio_pins_bitmask;
9166         bnx2x_cl45_write(bp, phy,
9167                          MDIO_PMA_DEVAD,
9168                          MDIO_PMA_REG_8727_GPIO_CTRL,
9169                          val);
9170 }
9171 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9172                                 struct link_params *params) {
9173         u32 swap_val, swap_override;
9174         u8 port;
9175         /* The PHY reset is controlled by GPIO 1. Fake the port number
9176          * to cancel the swap done in set_gpio()
9177          */
9178         struct bnx2x *bp = params->bp;
9179         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9180         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9181         port = (swap_val && swap_override) ^ 1;
9182         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9183                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9184 }
9185
9186 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9187                                     struct link_params *params)
9188 {
9189         struct bnx2x *bp = params->bp;
9190         u16 tmp1, val;
9191         /* Set option 1G speed */
9192         if ((phy->req_line_speed == SPEED_1000) ||
9193             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9194                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9195                 bnx2x_cl45_write(bp, phy,
9196                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9197                 bnx2x_cl45_write(bp, phy,
9198                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9199                 bnx2x_cl45_read(bp, phy,
9200                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9201                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9202                 /* Power down the XAUI until link is up in case of dual-media
9203                  * and 1G
9204                  */
9205                 if (DUAL_MEDIA(params)) {
9206                         bnx2x_cl45_read(bp, phy,
9207                                         MDIO_PMA_DEVAD,
9208                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9209                         val |= (3<<10);
9210                         bnx2x_cl45_write(bp, phy,
9211                                          MDIO_PMA_DEVAD,
9212                                          MDIO_PMA_REG_8727_PCS_GP, val);
9213                 }
9214         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9215                    ((phy->speed_cap_mask &
9216                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9217                    ((phy->speed_cap_mask &
9218                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9219                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9220
9221                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9222                 bnx2x_cl45_write(bp, phy,
9223                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9224                 bnx2x_cl45_write(bp, phy,
9225                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9226         } else {
9227                 /* Since the 8727 has only single reset pin, need to set the 10G
9228                  * registers although it is default
9229                  */
9230                 bnx2x_cl45_write(bp, phy,
9231                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9232                                  0x0020);
9233                 bnx2x_cl45_write(bp, phy,
9234                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9235                 bnx2x_cl45_write(bp, phy,
9236                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9237                 bnx2x_cl45_write(bp, phy,
9238                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9239                                  0x0008);
9240         }
9241 }
9242
9243 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9244                                   struct link_params *params,
9245                                   struct link_vars *vars)
9246 {
9247         u32 tx_en_mode;
9248         u16 tmp1, mod_abs, tmp2;
9249         struct bnx2x *bp = params->bp;
9250         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9251
9252         bnx2x_wait_reset_complete(bp, phy, params);
9253
9254         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9255
9256         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9257         /* Initially configure MOD_ABS to interrupt when module is
9258          * presence( bit 8)
9259          */
9260         bnx2x_cl45_read(bp, phy,
9261                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9262         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9263          * When the EDC is off it locks onto a reference clock and avoids
9264          * becoming 'lost'
9265          */
9266         mod_abs &= ~(1<<8);
9267         if (!(phy->flags & FLAGS_NOC))
9268                 mod_abs &= ~(1<<9);
9269         bnx2x_cl45_write(bp, phy,
9270                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9271
9272         /* Enable/Disable PHY transmitter output */
9273         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9274
9275         bnx2x_8727_power_module(bp, phy, 1);
9276
9277         bnx2x_cl45_read(bp, phy,
9278                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9279
9280         bnx2x_cl45_read(bp, phy,
9281                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9282
9283         bnx2x_8727_config_speed(phy, params);
9284
9285
9286         /* Set TX PreEmphasis if needed */
9287         if ((params->feature_config_flags &
9288              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9289                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9290                            phy->tx_preemphasis[0],
9291                            phy->tx_preemphasis[1]);
9292                 bnx2x_cl45_write(bp, phy,
9293                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9294                                  phy->tx_preemphasis[0]);
9295
9296                 bnx2x_cl45_write(bp, phy,
9297                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9298                                  phy->tx_preemphasis[1]);
9299         }
9300
9301         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9302          * power mode, if TX Laser is disabled
9303          */
9304         tx_en_mode = REG_RD(bp, params->shmem_base +
9305                             offsetof(struct shmem_region,
9306                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9307                         & PORT_HW_CFG_TX_LASER_MASK;
9308
9309         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9310
9311                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9312                 bnx2x_cl45_read(bp, phy,
9313                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9314                 tmp2 |= 0x1000;
9315                 tmp2 &= 0xFFEF;
9316                 bnx2x_cl45_write(bp, phy,
9317                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9318                 bnx2x_cl45_read(bp, phy,
9319                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9320                                 &tmp2);
9321                 bnx2x_cl45_write(bp, phy,
9322                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9323                                  (tmp2 & 0x7fff));
9324         }
9325
9326         return 0;
9327 }
9328
9329 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9330                                       struct link_params *params)
9331 {
9332         struct bnx2x *bp = params->bp;
9333         u16 mod_abs, rx_alarm_status;
9334         u32 val = REG_RD(bp, params->shmem_base +
9335                              offsetof(struct shmem_region, dev_info.
9336                                       port_feature_config[params->port].
9337                                       config));
9338         bnx2x_cl45_read(bp, phy,
9339                         MDIO_PMA_DEVAD,
9340                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9341         if (mod_abs & (1<<8)) {
9342
9343                 /* Module is absent */
9344                 DP(NETIF_MSG_LINK,
9345                    "MOD_ABS indication show module is absent\n");
9346                 phy->media_type = ETH_PHY_NOT_PRESENT;
9347                 /* 1. Set mod_abs to detect next module
9348                  *    presence event
9349                  * 2. Set EDC off by setting OPTXLOS signal input to low
9350                  *    (bit 9).
9351                  *    When the EDC is off it locks onto a reference clock and
9352                  *    avoids becoming 'lost'.
9353                  */
9354                 mod_abs &= ~(1<<8);
9355                 if (!(phy->flags & FLAGS_NOC))
9356                         mod_abs &= ~(1<<9);
9357                 bnx2x_cl45_write(bp, phy,
9358                                  MDIO_PMA_DEVAD,
9359                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9360
9361                 /* Clear RX alarm since it stays up as long as
9362                  * the mod_abs wasn't changed
9363                  */
9364                 bnx2x_cl45_read(bp, phy,
9365                                 MDIO_PMA_DEVAD,
9366                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9367
9368         } else {
9369                 /* Module is present */
9370                 DP(NETIF_MSG_LINK,
9371                    "MOD_ABS indication show module is present\n");
9372                 /* First disable transmitter, and if the module is ok, the
9373                  * module_detection will enable it
9374                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9375                  * 2. Restore the default polarity of the OPRXLOS signal and
9376                  * this signal will then correctly indicate the presence or
9377                  * absence of the Rx signal. (bit 9)
9378                  */
9379                 mod_abs |= (1<<8);
9380                 if (!(phy->flags & FLAGS_NOC))
9381                         mod_abs |= (1<<9);
9382                 bnx2x_cl45_write(bp, phy,
9383                                  MDIO_PMA_DEVAD,
9384                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9385
9386                 /* Clear RX alarm since it stays up as long as the mod_abs
9387                  * wasn't changed. This is need to be done before calling the
9388                  * module detection, otherwise it will clear* the link update
9389                  * alarm
9390                  */
9391                 bnx2x_cl45_read(bp, phy,
9392                                 MDIO_PMA_DEVAD,
9393                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9394
9395
9396                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9397                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9398                         bnx2x_sfp_set_transmitter(params, phy, 0);
9399
9400                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9401                         bnx2x_sfp_module_detection(phy, params);
9402                 else
9403                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9404
9405                 /* Reconfigure link speed based on module type limitations */
9406                 bnx2x_8727_config_speed(phy, params);
9407         }
9408
9409         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9410                    rx_alarm_status);
9411         /* No need to check link status in case of module plugged in/out */
9412 }
9413
9414 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9415                                  struct link_params *params,
9416                                  struct link_vars *vars)
9417
9418 {
9419         struct bnx2x *bp = params->bp;
9420         u8 link_up = 0, oc_port = params->port;
9421         u16 link_status = 0;
9422         u16 rx_alarm_status, lasi_ctrl, val1;
9423
9424         /* If PHY is not initialized, do not check link status */
9425         bnx2x_cl45_read(bp, phy,
9426                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9427                         &lasi_ctrl);
9428         if (!lasi_ctrl)
9429                 return 0;
9430
9431         /* Check the LASI on Rx */
9432         bnx2x_cl45_read(bp, phy,
9433                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9434                         &rx_alarm_status);
9435         vars->line_speed = 0;
9436         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9437
9438         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9439                              MDIO_PMA_LASI_TXCTRL);
9440
9441         bnx2x_cl45_read(bp, phy,
9442                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9443
9444         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9445
9446         /* Clear MSG-OUT */
9447         bnx2x_cl45_read(bp, phy,
9448                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9449
9450         /* If a module is present and there is need to check
9451          * for over current
9452          */
9453         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9454                 /* Check over-current using 8727 GPIO0 input*/
9455                 bnx2x_cl45_read(bp, phy,
9456                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9457                                 &val1);
9458
9459                 if ((val1 & (1<<8)) == 0) {
9460                         if (!CHIP_IS_E1x(bp))
9461                                 oc_port = BP_PATH(bp) + (params->port << 1);
9462                         DP(NETIF_MSG_LINK,
9463                            "8727 Power fault has been detected on port %d\n",
9464                            oc_port);
9465                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9466                                             "been detected and the power to "
9467                                             "that SFP+ module has been removed "
9468                                             "to prevent failure of the card. "
9469                                             "Please remove the SFP+ module and "
9470                                             "restart the system to clear this "
9471                                             "error.\n",
9472                          oc_port);
9473                         /* Disable all RX_ALARMs except for mod_abs */
9474                         bnx2x_cl45_write(bp, phy,
9475                                          MDIO_PMA_DEVAD,
9476                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9477
9478                         bnx2x_cl45_read(bp, phy,
9479                                         MDIO_PMA_DEVAD,
9480                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9481                         /* Wait for module_absent_event */
9482                         val1 |= (1<<8);
9483                         bnx2x_cl45_write(bp, phy,
9484                                          MDIO_PMA_DEVAD,
9485                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9486                         /* Clear RX alarm */
9487                         bnx2x_cl45_read(bp, phy,
9488                                 MDIO_PMA_DEVAD,
9489                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9490                         bnx2x_8727_power_module(params->bp, phy, 0);
9491                         return 0;
9492                 }
9493         } /* Over current check */
9494
9495         /* When module absent bit is set, check module */
9496         if (rx_alarm_status & (1<<5)) {
9497                 bnx2x_8727_handle_mod_abs(phy, params);
9498                 /* Enable all mod_abs and link detection bits */
9499                 bnx2x_cl45_write(bp, phy,
9500                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9501                                  ((1<<5) | (1<<2)));
9502         }
9503
9504         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9505                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9506                 bnx2x_sfp_set_transmitter(params, phy, 1);
9507         } else {
9508                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9509                 return 0;
9510         }
9511
9512         bnx2x_cl45_read(bp, phy,
9513                         MDIO_PMA_DEVAD,
9514                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9515
9516         /* Bits 0..2 --> speed detected,
9517          * Bits 13..15--> link is down
9518          */
9519         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9520                 link_up = 1;
9521                 vars->line_speed = SPEED_10000;
9522                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9523                            params->port);
9524         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9525                 link_up = 1;
9526                 vars->line_speed = SPEED_1000;
9527                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9528                            params->port);
9529         } else {
9530                 link_up = 0;
9531                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9532                            params->port);
9533         }
9534
9535         /* Capture 10G link fault. */
9536         if (vars->line_speed == SPEED_10000) {
9537                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9538                             MDIO_PMA_LASI_TXSTAT, &val1);
9539
9540                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9541                             MDIO_PMA_LASI_TXSTAT, &val1);
9542
9543                 if (val1 & (1<<0)) {
9544                         vars->fault_detected = 1;
9545                 }
9546         }
9547
9548         if (link_up) {
9549                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9550                 vars->duplex = DUPLEX_FULL;
9551                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9552         }
9553
9554         if ((DUAL_MEDIA(params)) &&
9555             (phy->req_line_speed == SPEED_1000)) {
9556                 bnx2x_cl45_read(bp, phy,
9557                                 MDIO_PMA_DEVAD,
9558                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9559                 /* In case of dual-media board and 1G, power up the XAUI side,
9560                  * otherwise power it down. For 10G it is done automatically
9561                  */
9562                 if (link_up)
9563                         val1 &= ~(3<<10);
9564                 else
9565                         val1 |= (3<<10);
9566                 bnx2x_cl45_write(bp, phy,
9567                                  MDIO_PMA_DEVAD,
9568                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9569         }
9570         return link_up;
9571 }
9572
9573 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9574                                   struct link_params *params)
9575 {
9576         struct bnx2x *bp = params->bp;
9577
9578         /* Enable/Disable PHY transmitter output */
9579         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9580
9581         /* Disable Transmitter */
9582         bnx2x_sfp_set_transmitter(params, phy, 0);
9583         /* Clear LASI */
9584         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9585
9586 }
9587
9588 /******************************************************************/
9589 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9590 /******************************************************************/
9591 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9592                                             struct bnx2x *bp,
9593                                             u8 port)
9594 {
9595         u16 val, fw_ver2, cnt, i;
9596         static struct bnx2x_reg_set reg_set[] = {
9597                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9598                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9599                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9600                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9601                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9602         };
9603         u16 fw_ver1;
9604
9605         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9606             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9607                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9608                 bnx2x_save_spirom_version(bp, port, fw_ver1 & 0xfff,
9609                                 phy->ver_addr);
9610         } else {
9611                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9612                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9613                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9614                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9615                                          reg_set[i].reg, reg_set[i].val);
9616
9617                 for (cnt = 0; cnt < 100; cnt++) {
9618                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9619                         if (val & 1)
9620                                 break;
9621                         udelay(5);
9622                 }
9623                 if (cnt == 100) {
9624                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9625                                         "phy fw version(1)\n");
9626                         bnx2x_save_spirom_version(bp, port, 0,
9627                                                   phy->ver_addr);
9628                         return;
9629                 }
9630
9631
9632                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9633                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9634                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9635                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9636                 for (cnt = 0; cnt < 100; cnt++) {
9637                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9638                         if (val & 1)
9639                                 break;
9640                         udelay(5);
9641                 }
9642                 if (cnt == 100) {
9643                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9644                                         "version(2)\n");
9645                         bnx2x_save_spirom_version(bp, port, 0,
9646                                                   phy->ver_addr);
9647                         return;
9648                 }
9649
9650                 /* lower 16 bits of the register SPI_FW_STATUS */
9651                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9652                 /* upper 16 bits of register SPI_FW_STATUS */
9653                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9654
9655                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9656                                           phy->ver_addr);
9657         }
9658
9659 }
9660 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9661                                 struct bnx2x_phy *phy)
9662 {
9663         u16 val, offset, i;
9664         static struct bnx2x_reg_set reg_set[] = {
9665                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9666                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9667                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9668                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
9669                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9670                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9671                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9672         };
9673         /* PHYC_CTL_LED_CTL */
9674         bnx2x_cl45_read(bp, phy,
9675                         MDIO_PMA_DEVAD,
9676                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9677         val &= 0xFE00;
9678         val |= 0x0092;
9679
9680         bnx2x_cl45_write(bp, phy,
9681                          MDIO_PMA_DEVAD,
9682                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9683
9684         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9685                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9686                                  reg_set[i].val);
9687
9688         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9689             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
9690                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9691         else
9692                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9693
9694         /* stretch_en for LED3*/
9695         bnx2x_cl45_read_or_write(bp, phy,
9696                                  MDIO_PMA_DEVAD, offset,
9697                                  MDIO_PMA_REG_84823_LED3_STRETCH_EN);
9698 }
9699
9700 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9701                                       struct link_params *params,
9702                                       u32 action)
9703 {
9704         struct bnx2x *bp = params->bp;
9705         switch (action) {
9706         case PHY_INIT:
9707                 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9708                     (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
9709                         /* Save spirom version */
9710                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9711                 }
9712                 /* This phy uses the NIG latch mechanism since link indication
9713                  * arrives through its LED4 and not via its LASI signal, so we
9714                  * get steady signal instead of clear on read
9715                  */
9716                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9717                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9718
9719                 bnx2x_848xx_set_led(bp, phy);
9720                 break;
9721         }
9722 }
9723
9724 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9725                                        struct link_params *params,
9726                                        struct link_vars *vars)
9727 {
9728         struct bnx2x *bp = params->bp;
9729         u16 autoneg_val, an_1000_val, an_10_100_val;
9730
9731         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9732         bnx2x_cl45_write(bp, phy,
9733                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9734
9735         /* set 1000 speed advertisement */
9736         bnx2x_cl45_read(bp, phy,
9737                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9738                         &an_1000_val);
9739
9740         bnx2x_ext_phy_set_pause(params, phy, vars);
9741         bnx2x_cl45_read(bp, phy,
9742                         MDIO_AN_DEVAD,
9743                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9744                         &an_10_100_val);
9745         bnx2x_cl45_read(bp, phy,
9746                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9747                         &autoneg_val);
9748         /* Disable forced speed */
9749         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9750         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9751
9752         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9753              (phy->speed_cap_mask &
9754              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9755             (phy->req_line_speed == SPEED_1000)) {
9756                 an_1000_val |= (1<<8);
9757                 autoneg_val |= (1<<9 | 1<<12);
9758                 if (phy->req_duplex == DUPLEX_FULL)
9759                         an_1000_val |= (1<<9);
9760                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9761         } else
9762                 an_1000_val &= ~((1<<8) | (1<<9));
9763
9764         bnx2x_cl45_write(bp, phy,
9765                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9766                          an_1000_val);
9767
9768         /* Set 10/100 speed advertisement */
9769         if (phy->req_line_speed == SPEED_AUTO_NEG) {
9770                 if (phy->speed_cap_mask &
9771                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9772                         /* Enable autoneg and restart autoneg for legacy speeds
9773                          */
9774                         autoneg_val |= (1<<9 | 1<<12);
9775                         an_10_100_val |= (1<<8);
9776                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9777                 }
9778
9779                 if (phy->speed_cap_mask &
9780                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9781                         /* Enable autoneg and restart autoneg for legacy speeds
9782                          */
9783                         autoneg_val |= (1<<9 | 1<<12);
9784                         an_10_100_val |= (1<<7);
9785                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9786                 }
9787
9788                 if ((phy->speed_cap_mask &
9789                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9790                     (phy->supported & SUPPORTED_10baseT_Full)) {
9791                         an_10_100_val |= (1<<6);
9792                         autoneg_val |= (1<<9 | 1<<12);
9793                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9794                 }
9795
9796                 if ((phy->speed_cap_mask &
9797                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9798                     (phy->supported & SUPPORTED_10baseT_Half)) {
9799                         an_10_100_val |= (1<<5);
9800                         autoneg_val |= (1<<9 | 1<<12);
9801                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9802                 }
9803         }
9804
9805         /* Only 10/100 are allowed to work in FORCE mode */
9806         if ((phy->req_line_speed == SPEED_100) &&
9807             (phy->supported &
9808              (SUPPORTED_100baseT_Half |
9809               SUPPORTED_100baseT_Full))) {
9810                 autoneg_val |= (1<<13);
9811                 /* Enabled AUTO-MDIX when autoneg is disabled */
9812                 bnx2x_cl45_write(bp, phy,
9813                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9814                                  (1<<15 | 1<<9 | 7<<0));
9815                 /* The PHY needs this set even for forced link. */
9816                 an_10_100_val |= (1<<8) | (1<<7);
9817                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9818         }
9819         if ((phy->req_line_speed == SPEED_10) &&
9820             (phy->supported &
9821              (SUPPORTED_10baseT_Half |
9822               SUPPORTED_10baseT_Full))) {
9823                 /* Enabled AUTO-MDIX when autoneg is disabled */
9824                 bnx2x_cl45_write(bp, phy,
9825                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9826                                  (1<<15 | 1<<9 | 7<<0));
9827                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9828         }
9829
9830         bnx2x_cl45_write(bp, phy,
9831                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9832                          an_10_100_val);
9833
9834         if (phy->req_duplex == DUPLEX_FULL)
9835                 autoneg_val |= (1<<8);
9836
9837         /* Always write this if this is not 84833/4.
9838          * For 84833/4, write it only when it's a forced speed.
9839          */
9840         if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
9841              (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
9842             ((autoneg_val & (1<<12)) == 0))
9843                 bnx2x_cl45_write(bp, phy,
9844                          MDIO_AN_DEVAD,
9845                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9846
9847         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9848             (phy->speed_cap_mask &
9849              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
9850                 (phy->req_line_speed == SPEED_10000)) {
9851                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
9852                         /* Restart autoneg for 10G*/
9853
9854                         bnx2x_cl45_read_or_write(
9855                                 bp, phy,
9856                                 MDIO_AN_DEVAD,
9857                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9858                                 0x1000);
9859                         bnx2x_cl45_write(bp, phy,
9860                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
9861                                          0x3200);
9862         } else
9863                 bnx2x_cl45_write(bp, phy,
9864                                  MDIO_AN_DEVAD,
9865                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
9866                                  1);
9867
9868         return 0;
9869 }
9870
9871 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
9872                                   struct link_params *params,
9873                                   struct link_vars *vars)
9874 {
9875         struct bnx2x *bp = params->bp;
9876         /* Restore normal power mode*/
9877         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
9878                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9879
9880         /* HW reset */
9881         bnx2x_ext_phy_hw_reset(bp, params->port);
9882         bnx2x_wait_reset_complete(bp, phy, params);
9883
9884         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9885         return bnx2x_848xx_cmn_config_init(phy, params, vars);
9886 }
9887
9888 #define PHY84833_CMDHDLR_WAIT 300
9889 #define PHY84833_CMDHDLR_MAX_ARGS 5
9890 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
9891                                 struct link_params *params, u16 fw_cmd,
9892                                 u16 cmd_args[], int argc)
9893 {
9894         int idx;
9895         u16 val;
9896         struct bnx2x *bp = params->bp;
9897         /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9898         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9899                         MDIO_84833_CMD_HDLR_STATUS,
9900                         PHY84833_STATUS_CMD_OPEN_OVERRIDE);
9901         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9902                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9903                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9904                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
9905                         break;
9906                 usleep_range(1000, 2000);
9907         }
9908         if (idx >= PHY84833_CMDHDLR_WAIT) {
9909                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
9910                 return -EINVAL;
9911         }
9912
9913         /* Prepare argument(s) and issue command */
9914         for (idx = 0; idx < argc; idx++) {
9915                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9916                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9917                                 cmd_args[idx]);
9918         }
9919         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9920                         MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
9921         for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
9922                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9923                                 MDIO_84833_CMD_HDLR_STATUS, &val);
9924                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
9925                         (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
9926                         break;
9927                 usleep_range(1000, 2000);
9928         }
9929         if ((idx >= PHY84833_CMDHDLR_WAIT) ||
9930                 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
9931                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
9932                 return -EINVAL;
9933         }
9934         /* Gather returning data */
9935         for (idx = 0; idx < argc; idx++) {
9936                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
9937                                 MDIO_84833_CMD_HDLR_DATA1 + idx,
9938                                 &cmd_args[idx]);
9939         }
9940         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
9941                         MDIO_84833_CMD_HDLR_STATUS,
9942                         PHY84833_STATUS_CMD_CLEAR_COMPLETE);
9943         return 0;
9944 }
9945
9946 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy *phy,
9947                                    struct link_params *params,
9948                                    struct link_vars *vars)
9949 {
9950         u32 pair_swap;
9951         u16 data[PHY84833_CMDHDLR_MAX_ARGS];
9952         int status;
9953         struct bnx2x *bp = params->bp;
9954
9955         /* Check for configuration. */
9956         pair_swap = REG_RD(bp, params->shmem_base +
9957                            offsetof(struct shmem_region,
9958                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
9959                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
9960
9961         if (pair_swap == 0)
9962                 return 0;
9963
9964         /* Only the second argument is used for this command */
9965         data[1] = (u16)pair_swap;
9966
9967         status = bnx2x_84833_cmd_hdlr(phy, params,
9968                 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
9969         if (status == 0)
9970                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
9971
9972         return status;
9973 }
9974
9975 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
9976                                       u32 shmem_base_path[],
9977                                       u32 chip_id)
9978 {
9979         u32 reset_pin[2];
9980         u32 idx;
9981         u8 reset_gpios;
9982         if (CHIP_IS_E3(bp)) {
9983                 /* Assume that these will be GPIOs, not EPIOs. */
9984                 for (idx = 0; idx < 2; idx++) {
9985                         /* Map config param to register bit. */
9986                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
9987                                 offsetof(struct shmem_region,
9988                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
9989                         reset_pin[idx] = (reset_pin[idx] &
9990                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
9991                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
9992                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
9993                         reset_pin[idx] = (1 << reset_pin[idx]);
9994                 }
9995                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
9996         } else {
9997                 /* E2, look from diff place of shmem. */
9998                 for (idx = 0; idx < 2; idx++) {
9999                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10000                                 offsetof(struct shmem_region,
10001                                 dev_info.port_hw_config[0].default_cfg));
10002                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10003                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10004                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10005                         reset_pin[idx] = (1 << reset_pin[idx]);
10006                 }
10007                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10008         }
10009
10010         return reset_gpios;
10011 }
10012
10013 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10014                                 struct link_params *params)
10015 {
10016         struct bnx2x *bp = params->bp;
10017         u8 reset_gpios;
10018         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10019                                 offsetof(struct shmem2_region,
10020                                 other_shmem_base_addr));
10021
10022         u32 shmem_base_path[2];
10023
10024         /* Work around for 84833 LED failure inside RESET status */
10025         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10026                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10027                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10028         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10029                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10030                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10031
10032         shmem_base_path[0] = params->shmem_base;
10033         shmem_base_path[1] = other_shmem_base_addr;
10034
10035         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10036                                                   params->chip_id);
10037
10038         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10039         udelay(10);
10040         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10041                 reset_gpios);
10042
10043         return 0;
10044 }
10045
10046 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10047                                    struct link_params *params,
10048                                    struct link_vars *vars)
10049 {
10050         int rc;
10051         struct bnx2x *bp = params->bp;
10052         u16 cmd_args = 0;
10053
10054         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10055
10056         /* Prevent Phy from working in EEE and advertising it */
10057         rc = bnx2x_84833_cmd_hdlr(phy, params,
10058                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10059         if (rc) {
10060                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10061                 return rc;
10062         }
10063
10064         return bnx2x_eee_disable(phy, params, vars);
10065 }
10066
10067 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10068                                    struct link_params *params,
10069                                    struct link_vars *vars)
10070 {
10071         int rc;
10072         struct bnx2x *bp = params->bp;
10073         u16 cmd_args = 1;
10074
10075         rc = bnx2x_84833_cmd_hdlr(phy, params,
10076                 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10077         if (rc) {
10078                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10079                 return rc;
10080         }
10081
10082         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10083 }
10084
10085 #define PHY84833_CONSTANT_LATENCY 1193
10086 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10087                                    struct link_params *params,
10088                                    struct link_vars *vars)
10089 {
10090         struct bnx2x *bp = params->bp;
10091         u8 port, initialize = 1;
10092         u16 val;
10093         u32 actual_phy_selection;
10094         u16 cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10095         int rc = 0;
10096
10097         usleep_range(1000, 2000);
10098
10099         if (!(CHIP_IS_E1x(bp)))
10100                 port = BP_PATH(bp);
10101         else
10102                 port = params->port;
10103
10104         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10105                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10106                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10107                                port);
10108         } else {
10109                 /* MDIO reset */
10110                 bnx2x_cl45_write(bp, phy,
10111                                 MDIO_PMA_DEVAD,
10112                                 MDIO_PMA_REG_CTRL, 0x8000);
10113         }
10114
10115         bnx2x_wait_reset_complete(bp, phy, params);
10116
10117         /* Wait for GPHY to come out of reset */
10118         msleep(50);
10119         if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10120             (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10121                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10122                  * behavior.
10123                  */
10124                 u16 temp;
10125                 temp = vars->line_speed;
10126                 vars->line_speed = SPEED_10000;
10127                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10128                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10129                 vars->line_speed = temp;
10130         }
10131
10132         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10133                         MDIO_CTL_REG_84823_MEDIA, &val);
10134         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10135                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10136                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10137                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10138                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10139
10140         if (CHIP_IS_E3(bp)) {
10141                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10142                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10143         } else {
10144                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10145                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10146         }
10147
10148         actual_phy_selection = bnx2x_phy_selection(params);
10149
10150         switch (actual_phy_selection) {
10151         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10152                 /* Do nothing. Essentially this is like the priority copper */
10153                 break;
10154         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10155                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10156                 break;
10157         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10158                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10159                 break;
10160         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10161                 /* Do nothing here. The first PHY won't be initialized at all */
10162                 break;
10163         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10164                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10165                 initialize = 0;
10166                 break;
10167         }
10168         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10169                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10170
10171         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10172                          MDIO_CTL_REG_84823_MEDIA, val);
10173         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10174                    params->multi_phy_config, val);
10175
10176         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10177             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10178                 bnx2x_84833_pair_swap_cfg(phy, params, vars);
10179
10180                 /* Keep AutogrEEEn disabled. */
10181                 cmd_args[0] = 0x0;
10182                 cmd_args[1] = 0x0;
10183                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10184                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10185                 rc = bnx2x_84833_cmd_hdlr(phy, params,
10186                         PHY84833_CMD_SET_EEE_MODE, cmd_args,
10187                         PHY84833_CMDHDLR_MAX_ARGS);
10188                 if (rc)
10189                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10190         }
10191         if (initialize)
10192                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10193         else
10194                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10195         /* 84833 PHY has a better feature and doesn't need to support this. */
10196         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10197                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10198                         offsetof(struct shmem_region,
10199                         dev_info.port_hw_config[params->port].default_cfg)) &
10200                         PORT_HW_CFG_ENABLE_CMS_MASK;
10201
10202                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10203                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10204                 if (cms_enable)
10205                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10206                 else
10207                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10208                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10209                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10210         }
10211
10212         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10213                         MDIO_84833_TOP_CFG_FW_REV, &val);
10214
10215         /* Configure EEE support */
10216         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10217             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10218             bnx2x_eee_has_cap(params)) {
10219                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10220                 if (rc) {
10221                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10222                         bnx2x_8483x_disable_eee(phy, params, vars);
10223                         return rc;
10224                 }
10225
10226                 if ((phy->req_duplex == DUPLEX_FULL) &&
10227                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10228                     (bnx2x_eee_calc_timer(params) ||
10229                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10230                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10231                 else
10232                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10233                 if (rc) {
10234                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10235                         return rc;
10236                 }
10237         } else {
10238                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10239         }
10240
10241         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10242             (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10243                 /* Bring PHY out of super isolate mode as the final step. */
10244                 bnx2x_cl45_read_and_write(bp, phy,
10245                                           MDIO_CTL_DEVAD,
10246                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10247                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10248         }
10249         return rc;
10250 }
10251
10252 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10253                                   struct link_params *params,
10254                                   struct link_vars *vars)
10255 {
10256         struct bnx2x *bp = params->bp;
10257         u16 val, val1, val2;
10258         u8 link_up = 0;
10259
10260
10261         /* Check 10G-BaseT link status */
10262         /* Check PMD signal ok */
10263         bnx2x_cl45_read(bp, phy,
10264                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10265         bnx2x_cl45_read(bp, phy,
10266                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10267                         &val2);
10268         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10269
10270         /* Check link 10G */
10271         if (val2 & (1<<11)) {
10272                 vars->line_speed = SPEED_10000;
10273                 vars->duplex = DUPLEX_FULL;
10274                 link_up = 1;
10275                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10276         } else { /* Check Legacy speed link */
10277                 u16 legacy_status, legacy_speed;
10278
10279                 /* Enable expansion register 0x42 (Operation mode status) */
10280                 bnx2x_cl45_write(bp, phy,
10281                                  MDIO_AN_DEVAD,
10282                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10283
10284                 /* Get legacy speed operation status */
10285                 bnx2x_cl45_read(bp, phy,
10286                                 MDIO_AN_DEVAD,
10287                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10288                                 &legacy_status);
10289
10290                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10291                    legacy_status);
10292                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10293                 legacy_speed = (legacy_status & (3<<9));
10294                 if (legacy_speed == (0<<9))
10295                         vars->line_speed = SPEED_10;
10296                 else if (legacy_speed == (1<<9))
10297                         vars->line_speed = SPEED_100;
10298                 else if (legacy_speed == (2<<9))
10299                         vars->line_speed = SPEED_1000;
10300                 else { /* Should not happen: Treat as link down */
10301                         vars->line_speed = 0;
10302                         link_up = 0;
10303                 }
10304
10305                 if (link_up) {
10306                         if (legacy_status & (1<<8))
10307                                 vars->duplex = DUPLEX_FULL;
10308                         else
10309                                 vars->duplex = DUPLEX_HALF;
10310
10311                         DP(NETIF_MSG_LINK,
10312                            "Link is up in %dMbps, is_duplex_full= %d\n",
10313                            vars->line_speed,
10314                            (vars->duplex == DUPLEX_FULL));
10315                         /* Check legacy speed AN resolution */
10316                         bnx2x_cl45_read(bp, phy,
10317                                         MDIO_AN_DEVAD,
10318                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10319                                         &val);
10320                         if (val & (1<<5))
10321                                 vars->link_status |=
10322                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10323                         bnx2x_cl45_read(bp, phy,
10324                                         MDIO_AN_DEVAD,
10325                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10326                                         &val);
10327                         if ((val & (1<<0)) == 0)
10328                                 vars->link_status |=
10329                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10330                 }
10331         }
10332         if (link_up) {
10333                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10334                            vars->line_speed);
10335                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10336
10337                 /* Read LP advertised speeds */
10338                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10339                                 MDIO_AN_REG_CL37_FC_LP, &val);
10340                 if (val & (1<<5))
10341                         vars->link_status |=
10342                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10343                 if (val & (1<<6))
10344                         vars->link_status |=
10345                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10346                 if (val & (1<<7))
10347                         vars->link_status |=
10348                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10349                 if (val & (1<<8))
10350                         vars->link_status |=
10351                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10352                 if (val & (1<<9))
10353                         vars->link_status |=
10354                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10355
10356                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10357                                 MDIO_AN_REG_1000T_STATUS, &val);
10358
10359                 if (val & (1<<10))
10360                         vars->link_status |=
10361                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10362                 if (val & (1<<11))
10363                         vars->link_status |=
10364                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10365
10366                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10367                                 MDIO_AN_REG_MASTER_STATUS, &val);
10368
10369                 if (val & (1<<11))
10370                         vars->link_status |=
10371                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10372
10373                 /* Determine if EEE was negotiated */
10374                 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10375                     (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10376                         bnx2x_eee_an_resolve(phy, params, vars);
10377         }
10378
10379         return link_up;
10380 }
10381
10382 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10383 {
10384         int status = 0;
10385         u32 spirom_ver;
10386         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10387         status = bnx2x_format_ver(spirom_ver, str, len);
10388         return status;
10389 }
10390
10391 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10392                                 struct link_params *params)
10393 {
10394         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10395                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10396         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10397                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10398 }
10399
10400 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10401                                         struct link_params *params)
10402 {
10403         bnx2x_cl45_write(params->bp, phy,
10404                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10405         bnx2x_cl45_write(params->bp, phy,
10406                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10407 }
10408
10409 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10410                                    struct link_params *params)
10411 {
10412         struct bnx2x *bp = params->bp;
10413         u8 port;
10414         u16 val16;
10415
10416         if (!(CHIP_IS_E1x(bp)))
10417                 port = BP_PATH(bp);
10418         else
10419                 port = params->port;
10420
10421         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10422                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10423                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10424                                port);
10425         } else {
10426                 bnx2x_cl45_read(bp, phy,
10427                                 MDIO_CTL_DEVAD,
10428                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10429                 val16 |= MDIO_84833_SUPER_ISOLATE;
10430                 bnx2x_cl45_write(bp, phy,
10431                                  MDIO_CTL_DEVAD,
10432                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10433         }
10434 }
10435
10436 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10437                                      struct link_params *params, u8 mode)
10438 {
10439         struct bnx2x *bp = params->bp;
10440         u16 val;
10441         u8 port;
10442
10443         if (!(CHIP_IS_E1x(bp)))
10444                 port = BP_PATH(bp);
10445         else
10446                 port = params->port;
10447
10448         switch (mode) {
10449         case LED_MODE_OFF:
10450
10451                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10452
10453                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10454                     SHARED_HW_CFG_LED_EXTPHY1) {
10455
10456                         /* Set LED masks */
10457                         bnx2x_cl45_write(bp, phy,
10458                                         MDIO_PMA_DEVAD,
10459                                         MDIO_PMA_REG_8481_LED1_MASK,
10460                                         0x0);
10461
10462                         bnx2x_cl45_write(bp, phy,
10463                                         MDIO_PMA_DEVAD,
10464                                         MDIO_PMA_REG_8481_LED2_MASK,
10465                                         0x0);
10466
10467                         bnx2x_cl45_write(bp, phy,
10468                                         MDIO_PMA_DEVAD,
10469                                         MDIO_PMA_REG_8481_LED3_MASK,
10470                                         0x0);
10471
10472                         bnx2x_cl45_write(bp, phy,
10473                                         MDIO_PMA_DEVAD,
10474                                         MDIO_PMA_REG_8481_LED5_MASK,
10475                                         0x0);
10476
10477                 } else {
10478                         bnx2x_cl45_write(bp, phy,
10479                                          MDIO_PMA_DEVAD,
10480                                          MDIO_PMA_REG_8481_LED1_MASK,
10481                                          0x0);
10482                 }
10483                 break;
10484         case LED_MODE_FRONT_PANEL_OFF:
10485
10486                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10487                    port);
10488
10489                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10490                     SHARED_HW_CFG_LED_EXTPHY1) {
10491
10492                         /* Set LED masks */
10493                         bnx2x_cl45_write(bp, phy,
10494                                          MDIO_PMA_DEVAD,
10495                                          MDIO_PMA_REG_8481_LED1_MASK,
10496                                          0x0);
10497
10498                         bnx2x_cl45_write(bp, phy,
10499                                          MDIO_PMA_DEVAD,
10500                                          MDIO_PMA_REG_8481_LED2_MASK,
10501                                          0x0);
10502
10503                         bnx2x_cl45_write(bp, phy,
10504                                          MDIO_PMA_DEVAD,
10505                                          MDIO_PMA_REG_8481_LED3_MASK,
10506                                          0x0);
10507
10508                         bnx2x_cl45_write(bp, phy,
10509                                          MDIO_PMA_DEVAD,
10510                                          MDIO_PMA_REG_8481_LED5_MASK,
10511                                          0x20);
10512
10513                 } else {
10514                         bnx2x_cl45_write(bp, phy,
10515                                          MDIO_PMA_DEVAD,
10516                                          MDIO_PMA_REG_8481_LED1_MASK,
10517                                          0x0);
10518                         if (phy->type ==
10519                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10520                                 /* Disable MI_INT interrupt before setting LED4
10521                                  * source to constant off.
10522                                  */
10523                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10524                                            params->port*4) &
10525                                     NIG_MASK_MI_INT) {
10526                                         params->link_flags |=
10527                                         LINK_FLAGS_INT_DISABLED;
10528
10529                                         bnx2x_bits_dis(
10530                                                 bp,
10531                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10532                                                 params->port*4,
10533                                                 NIG_MASK_MI_INT);
10534                                 }
10535                                 bnx2x_cl45_write(bp, phy,
10536                                                  MDIO_PMA_DEVAD,
10537                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10538                                                  0x0);
10539                         }
10540                 }
10541                 break;
10542         case LED_MODE_ON:
10543
10544                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10545
10546                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10547                     SHARED_HW_CFG_LED_EXTPHY1) {
10548                         /* Set control reg */
10549                         bnx2x_cl45_read(bp, phy,
10550                                         MDIO_PMA_DEVAD,
10551                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10552                                         &val);
10553                         val &= 0x8000;
10554                         val |= 0x2492;
10555
10556                         bnx2x_cl45_write(bp, phy,
10557                                          MDIO_PMA_DEVAD,
10558                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10559                                          val);
10560
10561                         /* Set LED masks */
10562                         bnx2x_cl45_write(bp, phy,
10563                                          MDIO_PMA_DEVAD,
10564                                          MDIO_PMA_REG_8481_LED1_MASK,
10565                                          0x0);
10566
10567                         bnx2x_cl45_write(bp, phy,
10568                                          MDIO_PMA_DEVAD,
10569                                          MDIO_PMA_REG_8481_LED2_MASK,
10570                                          0x20);
10571
10572                         bnx2x_cl45_write(bp, phy,
10573                                          MDIO_PMA_DEVAD,
10574                                          MDIO_PMA_REG_8481_LED3_MASK,
10575                                          0x20);
10576
10577                         bnx2x_cl45_write(bp, phy,
10578                                          MDIO_PMA_DEVAD,
10579                                          MDIO_PMA_REG_8481_LED5_MASK,
10580                                          0x0);
10581                 } else {
10582                         bnx2x_cl45_write(bp, phy,
10583                                          MDIO_PMA_DEVAD,
10584                                          MDIO_PMA_REG_8481_LED1_MASK,
10585                                          0x20);
10586                         if (phy->type ==
10587                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10588                                 /* Disable MI_INT interrupt before setting LED4
10589                                  * source to constant on.
10590                                  */
10591                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10592                                            params->port*4) &
10593                                     NIG_MASK_MI_INT) {
10594                                         params->link_flags |=
10595                                         LINK_FLAGS_INT_DISABLED;
10596
10597                                         bnx2x_bits_dis(
10598                                                 bp,
10599                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10600                                                 params->port*4,
10601                                                 NIG_MASK_MI_INT);
10602                                 }
10603                                 bnx2x_cl45_write(bp, phy,
10604                                                  MDIO_PMA_DEVAD,
10605                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10606                                                  0x20);
10607                         }
10608                 }
10609                 break;
10610
10611         case LED_MODE_OPER:
10612
10613                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10614
10615                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10616                     SHARED_HW_CFG_LED_EXTPHY1) {
10617
10618                         /* Set control reg */
10619                         bnx2x_cl45_read(bp, phy,
10620                                         MDIO_PMA_DEVAD,
10621                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10622                                         &val);
10623
10624                         if (!((val &
10625                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10626                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10627                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10628                                 bnx2x_cl45_write(bp, phy,
10629                                                  MDIO_PMA_DEVAD,
10630                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10631                                                  0xa492);
10632                         }
10633
10634                         /* Set LED masks */
10635                         bnx2x_cl45_write(bp, phy,
10636                                          MDIO_PMA_DEVAD,
10637                                          MDIO_PMA_REG_8481_LED1_MASK,
10638                                          0x10);
10639
10640                         bnx2x_cl45_write(bp, phy,
10641                                          MDIO_PMA_DEVAD,
10642                                          MDIO_PMA_REG_8481_LED2_MASK,
10643                                          0x80);
10644
10645                         bnx2x_cl45_write(bp, phy,
10646                                          MDIO_PMA_DEVAD,
10647                                          MDIO_PMA_REG_8481_LED3_MASK,
10648                                          0x98);
10649
10650                         bnx2x_cl45_write(bp, phy,
10651                                          MDIO_PMA_DEVAD,
10652                                          MDIO_PMA_REG_8481_LED5_MASK,
10653                                          0x40);
10654
10655                 } else {
10656                         bnx2x_cl45_write(bp, phy,
10657                                          MDIO_PMA_DEVAD,
10658                                          MDIO_PMA_REG_8481_LED1_MASK,
10659                                          0x80);
10660
10661                         /* Tell LED3 to blink on source */
10662                         bnx2x_cl45_read(bp, phy,
10663                                         MDIO_PMA_DEVAD,
10664                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10665                                         &val);
10666                         val &= ~(7<<6);
10667                         val |= (1<<6); /* A83B[8:6]= 1 */
10668                         bnx2x_cl45_write(bp, phy,
10669                                          MDIO_PMA_DEVAD,
10670                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10671                                          val);
10672                         if (phy->type ==
10673                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10674                                 /* Restore LED4 source to external link,
10675                                  * and re-enable interrupts.
10676                                  */
10677                                 bnx2x_cl45_write(bp, phy,
10678                                                  MDIO_PMA_DEVAD,
10679                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10680                                                  0x40);
10681                                 if (params->link_flags &
10682                                     LINK_FLAGS_INT_DISABLED) {
10683                                         bnx2x_link_int_enable(params);
10684                                         params->link_flags &=
10685                                                 ~LINK_FLAGS_INT_DISABLED;
10686                                 }
10687                         }
10688                 }
10689                 break;
10690         }
10691
10692         /* This is a workaround for E3+84833 until autoneg
10693          * restart is fixed in f/w
10694          */
10695         if (CHIP_IS_E3(bp)) {
10696                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
10697                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
10698         }
10699 }
10700
10701 /******************************************************************/
10702 /*                      54618SE PHY SECTION                       */
10703 /******************************************************************/
10704 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
10705                                         struct link_params *params,
10706                                         u32 action)
10707 {
10708         struct bnx2x *bp = params->bp;
10709         u16 temp;
10710         switch (action) {
10711         case PHY_INIT:
10712                 /* Configure LED4: set to INTR (0x6). */
10713                 /* Accessing shadow register 0xe. */
10714                 bnx2x_cl22_write(bp, phy,
10715                                  MDIO_REG_GPHY_SHADOW,
10716                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
10717                 bnx2x_cl22_read(bp, phy,
10718                                 MDIO_REG_GPHY_SHADOW,
10719                                 &temp);
10720                 temp &= ~(0xf << 4);
10721                 temp |= (0x6 << 4);
10722                 bnx2x_cl22_write(bp, phy,
10723                                  MDIO_REG_GPHY_SHADOW,
10724                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10725                 /* Configure INTR based on link status change. */
10726                 bnx2x_cl22_write(bp, phy,
10727                                  MDIO_REG_INTR_MASK,
10728                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
10729                 break;
10730         }
10731 }
10732
10733 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10734                                                struct link_params *params,
10735                                                struct link_vars *vars)
10736 {
10737         struct bnx2x *bp = params->bp;
10738         u8 port;
10739         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
10740         u32 cfg_pin;
10741
10742         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
10743         usleep_range(1000, 2000);
10744
10745         /* This works with E3 only, no need to check the chip
10746          * before determining the port.
10747          */
10748         port = params->port;
10749
10750         cfg_pin = (REG_RD(bp, params->shmem_base +
10751                         offsetof(struct shmem_region,
10752                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10753                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10754                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10755
10756         /* Drive pin high to bring the GPHY out of reset. */
10757         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
10758
10759         /* wait for GPHY to reset */
10760         msleep(50);
10761
10762         /* reset phy */
10763         bnx2x_cl22_write(bp, phy,
10764                          MDIO_PMA_REG_CTRL, 0x8000);
10765         bnx2x_wait_reset_complete(bp, phy, params);
10766
10767         /* Wait for GPHY to reset */
10768         msleep(50);
10769
10770
10771         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
10772         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10773         bnx2x_cl22_write(bp, phy,
10774                         MDIO_REG_GPHY_SHADOW,
10775                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
10776         bnx2x_cl22_read(bp, phy,
10777                         MDIO_REG_GPHY_SHADOW,
10778                         &temp);
10779         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
10780         bnx2x_cl22_write(bp, phy,
10781                         MDIO_REG_GPHY_SHADOW,
10782                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10783
10784         /* Set up fc */
10785         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10786         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
10787         fc_val = 0;
10788         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
10789                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
10790                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
10791
10792         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
10793                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
10794                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
10795
10796         /* Read all advertisement */
10797         bnx2x_cl22_read(bp, phy,
10798                         0x09,
10799                         &an_1000_val);
10800
10801         bnx2x_cl22_read(bp, phy,
10802                         0x04,
10803                         &an_10_100_val);
10804
10805         bnx2x_cl22_read(bp, phy,
10806                         MDIO_PMA_REG_CTRL,
10807                         &autoneg_val);
10808
10809         /* Disable forced speed */
10810         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10811         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10812                            (1<<11));
10813
10814         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10815                         (phy->speed_cap_mask &
10816                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10817                         (phy->req_line_speed == SPEED_1000)) {
10818                 an_1000_val |= (1<<8);
10819                 autoneg_val |= (1<<9 | 1<<12);
10820                 if (phy->req_duplex == DUPLEX_FULL)
10821                         an_1000_val |= (1<<9);
10822                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
10823         } else
10824                 an_1000_val &= ~((1<<8) | (1<<9));
10825
10826         bnx2x_cl22_write(bp, phy,
10827                         0x09,
10828                         an_1000_val);
10829         bnx2x_cl22_read(bp, phy,
10830                         0x09,
10831                         &an_1000_val);
10832
10833         /* Set 100 speed advertisement */
10834         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10835                         (phy->speed_cap_mask &
10836                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL |
10837                         PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)))) {
10838                 an_10_100_val |= (1<<7);
10839                 /* Enable autoneg and restart autoneg for legacy speeds */
10840                 autoneg_val |= (1<<9 | 1<<12);
10841
10842                 if (phy->req_duplex == DUPLEX_FULL)
10843                         an_10_100_val |= (1<<8);
10844                 DP(NETIF_MSG_LINK, "Advertising 100M\n");
10845         }
10846
10847         /* Set 10 speed advertisement */
10848         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
10849                         (phy->speed_cap_mask &
10850                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL |
10851                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)))) {
10852                 an_10_100_val |= (1<<5);
10853                 autoneg_val |= (1<<9 | 1<<12);
10854                 if (phy->req_duplex == DUPLEX_FULL)
10855                         an_10_100_val |= (1<<6);
10856                 DP(NETIF_MSG_LINK, "Advertising 10M\n");
10857         }
10858
10859         /* Only 10/100 are allowed to work in FORCE mode */
10860         if (phy->req_line_speed == SPEED_100) {
10861                 autoneg_val |= (1<<13);
10862                 /* Enabled AUTO-MDIX when autoneg is disabled */
10863                 bnx2x_cl22_write(bp, phy,
10864                                 0x18,
10865                                 (1<<15 | 1<<9 | 7<<0));
10866                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
10867         }
10868         if (phy->req_line_speed == SPEED_10) {
10869                 /* Enabled AUTO-MDIX when autoneg is disabled */
10870                 bnx2x_cl22_write(bp, phy,
10871                                 0x18,
10872                                 (1<<15 | 1<<9 | 7<<0));
10873                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
10874         }
10875
10876         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
10877                 int rc;
10878
10879                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
10880                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
10881                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
10882                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
10883                 temp &= 0xfffe;
10884                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
10885
10886                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
10887                 if (rc) {
10888                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10889                         bnx2x_eee_disable(phy, params, vars);
10890                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
10891                            (phy->req_duplex == DUPLEX_FULL) &&
10892                            (bnx2x_eee_calc_timer(params) ||
10893                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
10894                         /* Need to advertise EEE only when requested,
10895                          * and either no LPI assertion was requested,
10896                          * or it was requested and a valid timer was set.
10897                          * Also notice full duplex is required for EEE.
10898                          */
10899                         bnx2x_eee_advertise(phy, params, vars,
10900                                             SHMEM_EEE_1G_ADV);
10901                 } else {
10902                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
10903                         bnx2x_eee_disable(phy, params, vars);
10904                 }
10905         } else {
10906                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
10907                                     SHMEM_EEE_SUPPORTED_SHIFT;
10908
10909                 if (phy->flags & FLAGS_EEE) {
10910                         /* Handle legacy auto-grEEEn */
10911                         if (params->feature_config_flags &
10912                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
10913                                 temp = 6;
10914                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
10915                         } else {
10916                                 temp = 0;
10917                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
10918                         }
10919                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10920                                          MDIO_AN_REG_EEE_ADV, temp);
10921                 }
10922         }
10923
10924         bnx2x_cl22_write(bp, phy,
10925                         0x04,
10926                         an_10_100_val | fc_val);
10927
10928         if (phy->req_duplex == DUPLEX_FULL)
10929                 autoneg_val |= (1<<8);
10930
10931         bnx2x_cl22_write(bp, phy,
10932                         MDIO_PMA_REG_CTRL, autoneg_val);
10933
10934         return 0;
10935 }
10936
10937
10938 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
10939                                        struct link_params *params, u8 mode)
10940 {
10941         struct bnx2x *bp = params->bp;
10942         u16 temp;
10943
10944         bnx2x_cl22_write(bp, phy,
10945                 MDIO_REG_GPHY_SHADOW,
10946                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
10947         bnx2x_cl22_read(bp, phy,
10948                 MDIO_REG_GPHY_SHADOW,
10949                 &temp);
10950         temp &= 0xff00;
10951
10952         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
10953         switch (mode) {
10954         case LED_MODE_FRONT_PANEL_OFF:
10955         case LED_MODE_OFF:
10956                 temp |= 0x00ee;
10957                 break;
10958         case LED_MODE_OPER:
10959                 temp |= 0x0001;
10960                 break;
10961         case LED_MODE_ON:
10962                 temp |= 0x00ff;
10963                 break;
10964         default:
10965                 break;
10966         }
10967         bnx2x_cl22_write(bp, phy,
10968                 MDIO_REG_GPHY_SHADOW,
10969                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
10970         return;
10971 }
10972
10973
10974 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10975                                      struct link_params *params)
10976 {
10977         struct bnx2x *bp = params->bp;
10978         u32 cfg_pin;
10979         u8 port;
10980
10981         /* In case of no EPIO routed to reset the GPHY, put it
10982          * in low power mode.
10983          */
10984         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
10985         /* This works with E3 only, no need to check the chip
10986          * before determining the port.
10987          */
10988         port = params->port;
10989         cfg_pin = (REG_RD(bp, params->shmem_base +
10990                         offsetof(struct shmem_region,
10991                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
10992                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10993                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10994
10995         /* Drive pin low to put GPHY in reset. */
10996         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
10997 }
10998
10999 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11000                                     struct link_params *params,
11001                                     struct link_vars *vars)
11002 {
11003         struct bnx2x *bp = params->bp;
11004         u16 val;
11005         u8 link_up = 0;
11006         u16 legacy_status, legacy_speed;
11007
11008         /* Get speed operation status */
11009         bnx2x_cl22_read(bp, phy,
11010                         MDIO_REG_GPHY_AUX_STATUS,
11011                         &legacy_status);
11012         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11013
11014         /* Read status to clear the PHY interrupt. */
11015         bnx2x_cl22_read(bp, phy,
11016                         MDIO_REG_INTR_STATUS,
11017                         &val);
11018
11019         link_up = ((legacy_status & (1<<2)) == (1<<2));
11020
11021         if (link_up) {
11022                 legacy_speed = (legacy_status & (7<<8));
11023                 if (legacy_speed == (7<<8)) {
11024                         vars->line_speed = SPEED_1000;
11025                         vars->duplex = DUPLEX_FULL;
11026                 } else if (legacy_speed == (6<<8)) {
11027                         vars->line_speed = SPEED_1000;
11028                         vars->duplex = DUPLEX_HALF;
11029                 } else if (legacy_speed == (5<<8)) {
11030                         vars->line_speed = SPEED_100;
11031                         vars->duplex = DUPLEX_FULL;
11032                 }
11033                 /* Omitting 100Base-T4 for now */
11034                 else if (legacy_speed == (3<<8)) {
11035                         vars->line_speed = SPEED_100;
11036                         vars->duplex = DUPLEX_HALF;
11037                 } else if (legacy_speed == (2<<8)) {
11038                         vars->line_speed = SPEED_10;
11039                         vars->duplex = DUPLEX_FULL;
11040                 } else if (legacy_speed == (1<<8)) {
11041                         vars->line_speed = SPEED_10;
11042                         vars->duplex = DUPLEX_HALF;
11043                 } else /* Should not happen */
11044                         vars->line_speed = 0;
11045
11046                 DP(NETIF_MSG_LINK,
11047                    "Link is up in %dMbps, is_duplex_full= %d\n",
11048                    vars->line_speed,
11049                    (vars->duplex == DUPLEX_FULL));
11050
11051                 /* Check legacy speed AN resolution */
11052                 bnx2x_cl22_read(bp, phy,
11053                                 0x01,
11054                                 &val);
11055                 if (val & (1<<5))
11056                         vars->link_status |=
11057                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11058                 bnx2x_cl22_read(bp, phy,
11059                                 0x06,
11060                                 &val);
11061                 if ((val & (1<<0)) == 0)
11062                         vars->link_status |=
11063                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11064
11065                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11066                            vars->line_speed);
11067
11068                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11069
11070                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11071                         /* Report LP advertised speeds */
11072                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11073
11074                         if (val & (1<<5))
11075                                 vars->link_status |=
11076                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11077                         if (val & (1<<6))
11078                                 vars->link_status |=
11079                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11080                         if (val & (1<<7))
11081                                 vars->link_status |=
11082                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11083                         if (val & (1<<8))
11084                                 vars->link_status |=
11085                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11086                         if (val & (1<<9))
11087                                 vars->link_status |=
11088                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11089
11090                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11091                         if (val & (1<<10))
11092                                 vars->link_status |=
11093                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11094                         if (val & (1<<11))
11095                                 vars->link_status |=
11096                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11097
11098                         if ((phy->flags & FLAGS_EEE) &&
11099                             bnx2x_eee_has_cap(params))
11100                                 bnx2x_eee_an_resolve(phy, params, vars);
11101                 }
11102         }
11103         return link_up;
11104 }
11105
11106 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11107                                           struct link_params *params)
11108 {
11109         struct bnx2x *bp = params->bp;
11110         u16 val;
11111         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11112
11113         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11114
11115         /* Enable master/slave manual mmode and set to master */
11116         /* mii write 9 [bits set 11 12] */
11117         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11118
11119         /* forced 1G and disable autoneg */
11120         /* set val [mii read 0] */
11121         /* set val [expr $val & [bits clear 6 12 13]] */
11122         /* set val [expr $val | [bits set 6 8]] */
11123         /* mii write 0 $val */
11124         bnx2x_cl22_read(bp, phy, 0x00, &val);
11125         val &= ~((1<<6) | (1<<12) | (1<<13));
11126         val |= (1<<6) | (1<<8);
11127         bnx2x_cl22_write(bp, phy, 0x00, val);
11128
11129         /* Set external loopback and Tx using 6dB coding */
11130         /* mii write 0x18 7 */
11131         /* set val [mii read 0x18] */
11132         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11133         bnx2x_cl22_write(bp, phy, 0x18, 7);
11134         bnx2x_cl22_read(bp, phy, 0x18, &val);
11135         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11136
11137         /* This register opens the gate for the UMAC despite its name */
11138         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11139
11140         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11141          * length used by the MAC receive logic to check frames.
11142          */
11143         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11144 }
11145
11146 /******************************************************************/
11147 /*                      SFX7101 PHY SECTION                       */
11148 /******************************************************************/
11149 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11150                                        struct link_params *params)
11151 {
11152         struct bnx2x *bp = params->bp;
11153         /* SFX7101_XGXS_TEST1 */
11154         bnx2x_cl45_write(bp, phy,
11155                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11156 }
11157
11158 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11159                                   struct link_params *params,
11160                                   struct link_vars *vars)
11161 {
11162         u16 fw_ver1, fw_ver2, val;
11163         struct bnx2x *bp = params->bp;
11164         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11165
11166         /* Restore normal power mode*/
11167         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11168                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11169         /* HW reset */
11170         bnx2x_ext_phy_hw_reset(bp, params->port);
11171         bnx2x_wait_reset_complete(bp, phy, params);
11172
11173         bnx2x_cl45_write(bp, phy,
11174                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11175         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11176         bnx2x_cl45_write(bp, phy,
11177                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11178
11179         bnx2x_ext_phy_set_pause(params, phy, vars);
11180         /* Restart autoneg */
11181         bnx2x_cl45_read(bp, phy,
11182                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11183         val |= 0x200;
11184         bnx2x_cl45_write(bp, phy,
11185                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11186
11187         /* Save spirom version */
11188         bnx2x_cl45_read(bp, phy,
11189                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11190
11191         bnx2x_cl45_read(bp, phy,
11192                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11193         bnx2x_save_spirom_version(bp, params->port,
11194                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11195         return 0;
11196 }
11197
11198 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11199                                  struct link_params *params,
11200                                  struct link_vars *vars)
11201 {
11202         struct bnx2x *bp = params->bp;
11203         u8 link_up;
11204         u16 val1, val2;
11205         bnx2x_cl45_read(bp, phy,
11206                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11207         bnx2x_cl45_read(bp, phy,
11208                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11209         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11210                    val2, val1);
11211         bnx2x_cl45_read(bp, phy,
11212                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11213         bnx2x_cl45_read(bp, phy,
11214                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11215         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11216                    val2, val1);
11217         link_up = ((val1 & 4) == 4);
11218         /* If link is up print the AN outcome of the SFX7101 PHY */
11219         if (link_up) {
11220                 bnx2x_cl45_read(bp, phy,
11221                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11222                                 &val2);
11223                 vars->line_speed = SPEED_10000;
11224                 vars->duplex = DUPLEX_FULL;
11225                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11226                            val2, (val2 & (1<<14)));
11227                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11228                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11229
11230                 /* Read LP advertised speeds */
11231                 if (val2 & (1<<11))
11232                         vars->link_status |=
11233                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11234         }
11235         return link_up;
11236 }
11237
11238 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11239 {
11240         if (*len < 5)
11241                 return -EINVAL;
11242         str[0] = (spirom_ver & 0xFF);
11243         str[1] = (spirom_ver & 0xFF00) >> 8;
11244         str[2] = (spirom_ver & 0xFF0000) >> 16;
11245         str[3] = (spirom_ver & 0xFF000000) >> 24;
11246         str[4] = '\0';
11247         *len -= 5;
11248         return 0;
11249 }
11250
11251 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11252 {
11253         u16 val, cnt;
11254
11255         bnx2x_cl45_read(bp, phy,
11256                         MDIO_PMA_DEVAD,
11257                         MDIO_PMA_REG_7101_RESET, &val);
11258
11259         for (cnt = 0; cnt < 10; cnt++) {
11260                 msleep(50);
11261                 /* Writes a self-clearing reset */
11262                 bnx2x_cl45_write(bp, phy,
11263                                  MDIO_PMA_DEVAD,
11264                                  MDIO_PMA_REG_7101_RESET,
11265                                  (val | (1<<15)));
11266                 /* Wait for clear */
11267                 bnx2x_cl45_read(bp, phy,
11268                                 MDIO_PMA_DEVAD,
11269                                 MDIO_PMA_REG_7101_RESET, &val);
11270
11271                 if ((val & (1<<15)) == 0)
11272                         break;
11273         }
11274 }
11275
11276 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11277                                 struct link_params *params) {
11278         /* Low power mode is controlled by GPIO 2 */
11279         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11280                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11281         /* The PHY reset is controlled by GPIO 1 */
11282         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11283                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11284 }
11285
11286 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11287                                     struct link_params *params, u8 mode)
11288 {
11289         u16 val = 0;
11290         struct bnx2x *bp = params->bp;
11291         switch (mode) {
11292         case LED_MODE_FRONT_PANEL_OFF:
11293         case LED_MODE_OFF:
11294                 val = 2;
11295                 break;
11296         case LED_MODE_ON:
11297                 val = 1;
11298                 break;
11299         case LED_MODE_OPER:
11300                 val = 0;
11301                 break;
11302         }
11303         bnx2x_cl45_write(bp, phy,
11304                          MDIO_PMA_DEVAD,
11305                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11306                          val);
11307 }
11308
11309 /******************************************************************/
11310 /*                      STATIC PHY DECLARATION                    */
11311 /******************************************************************/
11312
11313 static const struct bnx2x_phy phy_null = {
11314         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11315         .addr           = 0,
11316         .def_md_devad   = 0,
11317         .flags          = FLAGS_INIT_XGXS_FIRST,
11318         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11319         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11320         .mdio_ctrl      = 0,
11321         .supported      = 0,
11322         .media_type     = ETH_PHY_NOT_PRESENT,
11323         .ver_addr       = 0,
11324         .req_flow_ctrl  = 0,
11325         .req_line_speed = 0,
11326         .speed_cap_mask = 0,
11327         .req_duplex     = 0,
11328         .rsrv           = 0,
11329         .config_init    = (config_init_t)NULL,
11330         .read_status    = (read_status_t)NULL,
11331         .link_reset     = (link_reset_t)NULL,
11332         .config_loopback = (config_loopback_t)NULL,
11333         .format_fw_ver  = (format_fw_ver_t)NULL,
11334         .hw_reset       = (hw_reset_t)NULL,
11335         .set_link_led   = (set_link_led_t)NULL,
11336         .phy_specific_func = (phy_specific_func_t)NULL
11337 };
11338
11339 static const struct bnx2x_phy phy_serdes = {
11340         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11341         .addr           = 0xff,
11342         .def_md_devad   = 0,
11343         .flags          = 0,
11344         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11345         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11346         .mdio_ctrl      = 0,
11347         .supported      = (SUPPORTED_10baseT_Half |
11348                            SUPPORTED_10baseT_Full |
11349                            SUPPORTED_100baseT_Half |
11350                            SUPPORTED_100baseT_Full |
11351                            SUPPORTED_1000baseT_Full |
11352                            SUPPORTED_2500baseX_Full |
11353                            SUPPORTED_TP |
11354                            SUPPORTED_Autoneg |
11355                            SUPPORTED_Pause |
11356                            SUPPORTED_Asym_Pause),
11357         .media_type     = ETH_PHY_BASE_T,
11358         .ver_addr       = 0,
11359         .req_flow_ctrl  = 0,
11360         .req_line_speed = 0,
11361         .speed_cap_mask = 0,
11362         .req_duplex     = 0,
11363         .rsrv           = 0,
11364         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11365         .read_status    = (read_status_t)bnx2x_link_settings_status,
11366         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11367         .config_loopback = (config_loopback_t)NULL,
11368         .format_fw_ver  = (format_fw_ver_t)NULL,
11369         .hw_reset       = (hw_reset_t)NULL,
11370         .set_link_led   = (set_link_led_t)NULL,
11371         .phy_specific_func = (phy_specific_func_t)NULL
11372 };
11373
11374 static const struct bnx2x_phy phy_xgxs = {
11375         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11376         .addr           = 0xff,
11377         .def_md_devad   = 0,
11378         .flags          = 0,
11379         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11380         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11381         .mdio_ctrl      = 0,
11382         .supported      = (SUPPORTED_10baseT_Half |
11383                            SUPPORTED_10baseT_Full |
11384                            SUPPORTED_100baseT_Half |
11385                            SUPPORTED_100baseT_Full |
11386                            SUPPORTED_1000baseT_Full |
11387                            SUPPORTED_2500baseX_Full |
11388                            SUPPORTED_10000baseT_Full |
11389                            SUPPORTED_FIBRE |
11390                            SUPPORTED_Autoneg |
11391                            SUPPORTED_Pause |
11392                            SUPPORTED_Asym_Pause),
11393         .media_type     = ETH_PHY_CX4,
11394         .ver_addr       = 0,
11395         .req_flow_ctrl  = 0,
11396         .req_line_speed = 0,
11397         .speed_cap_mask = 0,
11398         .req_duplex     = 0,
11399         .rsrv           = 0,
11400         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11401         .read_status    = (read_status_t)bnx2x_link_settings_status,
11402         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11403         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11404         .format_fw_ver  = (format_fw_ver_t)NULL,
11405         .hw_reset       = (hw_reset_t)NULL,
11406         .set_link_led   = (set_link_led_t)NULL,
11407         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11408 };
11409 static const struct bnx2x_phy phy_warpcore = {
11410         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11411         .addr           = 0xff,
11412         .def_md_devad   = 0,
11413         .flags          = FLAGS_TX_ERROR_CHECK,
11414         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11415         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11416         .mdio_ctrl      = 0,
11417         .supported      = (SUPPORTED_10baseT_Half |
11418                            SUPPORTED_10baseT_Full |
11419                            SUPPORTED_100baseT_Half |
11420                            SUPPORTED_100baseT_Full |
11421                            SUPPORTED_1000baseT_Full |
11422                            SUPPORTED_10000baseT_Full |
11423                            SUPPORTED_20000baseKR2_Full |
11424                            SUPPORTED_20000baseMLD2_Full |
11425                            SUPPORTED_FIBRE |
11426                            SUPPORTED_Autoneg |
11427                            SUPPORTED_Pause |
11428                            SUPPORTED_Asym_Pause),
11429         .media_type     = ETH_PHY_UNSPECIFIED,
11430         .ver_addr       = 0,
11431         .req_flow_ctrl  = 0,
11432         .req_line_speed = 0,
11433         .speed_cap_mask = 0,
11434         /* req_duplex = */0,
11435         /* rsrv = */0,
11436         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11437         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11438         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11439         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11440         .format_fw_ver  = (format_fw_ver_t)NULL,
11441         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11442         .set_link_led   = (set_link_led_t)NULL,
11443         .phy_specific_func = (phy_specific_func_t)NULL
11444 };
11445
11446
11447 static const struct bnx2x_phy phy_7101 = {
11448         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11449         .addr           = 0xff,
11450         .def_md_devad   = 0,
11451         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11452         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11453         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11454         .mdio_ctrl      = 0,
11455         .supported      = (SUPPORTED_10000baseT_Full |
11456                            SUPPORTED_TP |
11457                            SUPPORTED_Autoneg |
11458                            SUPPORTED_Pause |
11459                            SUPPORTED_Asym_Pause),
11460         .media_type     = ETH_PHY_BASE_T,
11461         .ver_addr       = 0,
11462         .req_flow_ctrl  = 0,
11463         .req_line_speed = 0,
11464         .speed_cap_mask = 0,
11465         .req_duplex     = 0,
11466         .rsrv           = 0,
11467         .config_init    = (config_init_t)bnx2x_7101_config_init,
11468         .read_status    = (read_status_t)bnx2x_7101_read_status,
11469         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11470         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11471         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11472         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11473         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11474         .phy_specific_func = (phy_specific_func_t)NULL
11475 };
11476 static const struct bnx2x_phy phy_8073 = {
11477         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11478         .addr           = 0xff,
11479         .def_md_devad   = 0,
11480         .flags          = 0,
11481         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11482         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11483         .mdio_ctrl      = 0,
11484         .supported      = (SUPPORTED_10000baseT_Full |
11485                            SUPPORTED_2500baseX_Full |
11486                            SUPPORTED_1000baseT_Full |
11487                            SUPPORTED_FIBRE |
11488                            SUPPORTED_Autoneg |
11489                            SUPPORTED_Pause |
11490                            SUPPORTED_Asym_Pause),
11491         .media_type     = ETH_PHY_KR,
11492         .ver_addr       = 0,
11493         .req_flow_ctrl  = 0,
11494         .req_line_speed = 0,
11495         .speed_cap_mask = 0,
11496         .req_duplex     = 0,
11497         .rsrv           = 0,
11498         .config_init    = (config_init_t)bnx2x_8073_config_init,
11499         .read_status    = (read_status_t)bnx2x_8073_read_status,
11500         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11501         .config_loopback = (config_loopback_t)NULL,
11502         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11503         .hw_reset       = (hw_reset_t)NULL,
11504         .set_link_led   = (set_link_led_t)NULL,
11505         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11506 };
11507 static const struct bnx2x_phy phy_8705 = {
11508         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11509         .addr           = 0xff,
11510         .def_md_devad   = 0,
11511         .flags          = FLAGS_INIT_XGXS_FIRST,
11512         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11513         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11514         .mdio_ctrl      = 0,
11515         .supported      = (SUPPORTED_10000baseT_Full |
11516                            SUPPORTED_FIBRE |
11517                            SUPPORTED_Pause |
11518                            SUPPORTED_Asym_Pause),
11519         .media_type     = ETH_PHY_XFP_FIBER,
11520         .ver_addr       = 0,
11521         .req_flow_ctrl  = 0,
11522         .req_line_speed = 0,
11523         .speed_cap_mask = 0,
11524         .req_duplex     = 0,
11525         .rsrv           = 0,
11526         .config_init    = (config_init_t)bnx2x_8705_config_init,
11527         .read_status    = (read_status_t)bnx2x_8705_read_status,
11528         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11529         .config_loopback = (config_loopback_t)NULL,
11530         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11531         .hw_reset       = (hw_reset_t)NULL,
11532         .set_link_led   = (set_link_led_t)NULL,
11533         .phy_specific_func = (phy_specific_func_t)NULL
11534 };
11535 static const struct bnx2x_phy phy_8706 = {
11536         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11537         .addr           = 0xff,
11538         .def_md_devad   = 0,
11539         .flags          = FLAGS_INIT_XGXS_FIRST,
11540         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11541         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11542         .mdio_ctrl      = 0,
11543         .supported      = (SUPPORTED_10000baseT_Full |
11544                            SUPPORTED_1000baseT_Full |
11545                            SUPPORTED_FIBRE |
11546                            SUPPORTED_Pause |
11547                            SUPPORTED_Asym_Pause),
11548         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11549         .ver_addr       = 0,
11550         .req_flow_ctrl  = 0,
11551         .req_line_speed = 0,
11552         .speed_cap_mask = 0,
11553         .req_duplex     = 0,
11554         .rsrv           = 0,
11555         .config_init    = (config_init_t)bnx2x_8706_config_init,
11556         .read_status    = (read_status_t)bnx2x_8706_read_status,
11557         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11558         .config_loopback = (config_loopback_t)NULL,
11559         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11560         .hw_reset       = (hw_reset_t)NULL,
11561         .set_link_led   = (set_link_led_t)NULL,
11562         .phy_specific_func = (phy_specific_func_t)NULL
11563 };
11564
11565 static const struct bnx2x_phy phy_8726 = {
11566         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11567         .addr           = 0xff,
11568         .def_md_devad   = 0,
11569         .flags          = (FLAGS_INIT_XGXS_FIRST |
11570                            FLAGS_TX_ERROR_CHECK),
11571         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11572         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11573         .mdio_ctrl      = 0,
11574         .supported      = (SUPPORTED_10000baseT_Full |
11575                            SUPPORTED_1000baseT_Full |
11576                            SUPPORTED_Autoneg |
11577                            SUPPORTED_FIBRE |
11578                            SUPPORTED_Pause |
11579                            SUPPORTED_Asym_Pause),
11580         .media_type     = ETH_PHY_NOT_PRESENT,
11581         .ver_addr       = 0,
11582         .req_flow_ctrl  = 0,
11583         .req_line_speed = 0,
11584         .speed_cap_mask = 0,
11585         .req_duplex     = 0,
11586         .rsrv           = 0,
11587         .config_init    = (config_init_t)bnx2x_8726_config_init,
11588         .read_status    = (read_status_t)bnx2x_8726_read_status,
11589         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11590         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11591         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11592         .hw_reset       = (hw_reset_t)NULL,
11593         .set_link_led   = (set_link_led_t)NULL,
11594         .phy_specific_func = (phy_specific_func_t)NULL
11595 };
11596
11597 static const struct bnx2x_phy phy_8727 = {
11598         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11599         .addr           = 0xff,
11600         .def_md_devad   = 0,
11601         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11602                            FLAGS_TX_ERROR_CHECK),
11603         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11604         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11605         .mdio_ctrl      = 0,
11606         .supported      = (SUPPORTED_10000baseT_Full |
11607                            SUPPORTED_1000baseT_Full |
11608                            SUPPORTED_FIBRE |
11609                            SUPPORTED_Pause |
11610                            SUPPORTED_Asym_Pause),
11611         .media_type     = ETH_PHY_NOT_PRESENT,
11612         .ver_addr       = 0,
11613         .req_flow_ctrl  = 0,
11614         .req_line_speed = 0,
11615         .speed_cap_mask = 0,
11616         .req_duplex     = 0,
11617         .rsrv           = 0,
11618         .config_init    = (config_init_t)bnx2x_8727_config_init,
11619         .read_status    = (read_status_t)bnx2x_8727_read_status,
11620         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
11621         .config_loopback = (config_loopback_t)NULL,
11622         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11623         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
11624         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
11625         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
11626 };
11627 static const struct bnx2x_phy phy_8481 = {
11628         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
11629         .addr           = 0xff,
11630         .def_md_devad   = 0,
11631         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11632                           FLAGS_REARM_LATCH_SIGNAL,
11633         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11634         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11635         .mdio_ctrl      = 0,
11636         .supported      = (SUPPORTED_10baseT_Half |
11637                            SUPPORTED_10baseT_Full |
11638                            SUPPORTED_100baseT_Half |
11639                            SUPPORTED_100baseT_Full |
11640                            SUPPORTED_1000baseT_Full |
11641                            SUPPORTED_10000baseT_Full |
11642                            SUPPORTED_TP |
11643                            SUPPORTED_Autoneg |
11644                            SUPPORTED_Pause |
11645                            SUPPORTED_Asym_Pause),
11646         .media_type     = ETH_PHY_BASE_T,
11647         .ver_addr       = 0,
11648         .req_flow_ctrl  = 0,
11649         .req_line_speed = 0,
11650         .speed_cap_mask = 0,
11651         .req_duplex     = 0,
11652         .rsrv           = 0,
11653         .config_init    = (config_init_t)bnx2x_8481_config_init,
11654         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11655         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
11656         .config_loopback = (config_loopback_t)NULL,
11657         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11658         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
11659         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11660         .phy_specific_func = (phy_specific_func_t)NULL
11661 };
11662
11663 static const struct bnx2x_phy phy_84823 = {
11664         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
11665         .addr           = 0xff,
11666         .def_md_devad   = 0,
11667         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11668                            FLAGS_REARM_LATCH_SIGNAL |
11669                            FLAGS_TX_ERROR_CHECK),
11670         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11671         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11672         .mdio_ctrl      = 0,
11673         .supported      = (SUPPORTED_10baseT_Half |
11674                            SUPPORTED_10baseT_Full |
11675                            SUPPORTED_100baseT_Half |
11676                            SUPPORTED_100baseT_Full |
11677                            SUPPORTED_1000baseT_Full |
11678                            SUPPORTED_10000baseT_Full |
11679                            SUPPORTED_TP |
11680                            SUPPORTED_Autoneg |
11681                            SUPPORTED_Pause |
11682                            SUPPORTED_Asym_Pause),
11683         .media_type     = ETH_PHY_BASE_T,
11684         .ver_addr       = 0,
11685         .req_flow_ctrl  = 0,
11686         .req_line_speed = 0,
11687         .speed_cap_mask = 0,
11688         .req_duplex     = 0,
11689         .rsrv           = 0,
11690         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11691         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11692         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11693         .config_loopback = (config_loopback_t)NULL,
11694         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11695         .hw_reset       = (hw_reset_t)NULL,
11696         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11697         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11698 };
11699
11700 static const struct bnx2x_phy phy_84833 = {
11701         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
11702         .addr           = 0xff,
11703         .def_md_devad   = 0,
11704         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11705                            FLAGS_REARM_LATCH_SIGNAL |
11706                            FLAGS_TX_ERROR_CHECK),
11707         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11708         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11709         .mdio_ctrl      = 0,
11710         .supported      = (SUPPORTED_100baseT_Half |
11711                            SUPPORTED_100baseT_Full |
11712                            SUPPORTED_1000baseT_Full |
11713                            SUPPORTED_10000baseT_Full |
11714                            SUPPORTED_TP |
11715                            SUPPORTED_Autoneg |
11716                            SUPPORTED_Pause |
11717                            SUPPORTED_Asym_Pause),
11718         .media_type     = ETH_PHY_BASE_T,
11719         .ver_addr       = 0,
11720         .req_flow_ctrl  = 0,
11721         .req_line_speed = 0,
11722         .speed_cap_mask = 0,
11723         .req_duplex     = 0,
11724         .rsrv           = 0,
11725         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11726         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11727         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11728         .config_loopback = (config_loopback_t)NULL,
11729         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11730         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11731         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11732         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11733 };
11734
11735 static const struct bnx2x_phy phy_84834 = {
11736         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
11737         .addr           = 0xff,
11738         .def_md_devad   = 0,
11739         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
11740                             FLAGS_REARM_LATCH_SIGNAL,
11741         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11742         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11743         .mdio_ctrl      = 0,
11744         .supported      = (SUPPORTED_100baseT_Half |
11745                            SUPPORTED_100baseT_Full |
11746                            SUPPORTED_1000baseT_Full |
11747                            SUPPORTED_10000baseT_Full |
11748                            SUPPORTED_TP |
11749                            SUPPORTED_Autoneg |
11750                            SUPPORTED_Pause |
11751                            SUPPORTED_Asym_Pause),
11752         .media_type     = ETH_PHY_BASE_T,
11753         .ver_addr       = 0,
11754         .req_flow_ctrl  = 0,
11755         .req_line_speed = 0,
11756         .speed_cap_mask = 0,
11757         .req_duplex     = 0,
11758         .rsrv           = 0,
11759         .config_init    = (config_init_t)bnx2x_848x3_config_init,
11760         .read_status    = (read_status_t)bnx2x_848xx_read_status,
11761         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
11762         .config_loopback = (config_loopback_t)NULL,
11763         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
11764         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
11765         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
11766         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
11767 };
11768
11769 static const struct bnx2x_phy phy_54618se = {
11770         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
11771         .addr           = 0xff,
11772         .def_md_devad   = 0,
11773         .flags          = FLAGS_INIT_XGXS_FIRST,
11774         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11775         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11776         .mdio_ctrl      = 0,
11777         .supported      = (SUPPORTED_10baseT_Half |
11778                            SUPPORTED_10baseT_Full |
11779                            SUPPORTED_100baseT_Half |
11780                            SUPPORTED_100baseT_Full |
11781                            SUPPORTED_1000baseT_Full |
11782                            SUPPORTED_TP |
11783                            SUPPORTED_Autoneg |
11784                            SUPPORTED_Pause |
11785                            SUPPORTED_Asym_Pause),
11786         .media_type     = ETH_PHY_BASE_T,
11787         .ver_addr       = 0,
11788         .req_flow_ctrl  = 0,
11789         .req_line_speed = 0,
11790         .speed_cap_mask = 0,
11791         /* req_duplex = */0,
11792         /* rsrv = */0,
11793         .config_init    = (config_init_t)bnx2x_54618se_config_init,
11794         .read_status    = (read_status_t)bnx2x_54618se_read_status,
11795         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
11796         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
11797         .format_fw_ver  = (format_fw_ver_t)NULL,
11798         .hw_reset       = (hw_reset_t)NULL,
11799         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
11800         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
11801 };
11802 /*****************************************************************/
11803 /*                                                               */
11804 /* Populate the phy according. Main function: bnx2x_populate_phy   */
11805 /*                                                               */
11806 /*****************************************************************/
11807
11808 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
11809                                      struct bnx2x_phy *phy, u8 port,
11810                                      u8 phy_index)
11811 {
11812         /* Get the 4 lanes xgxs config rx and tx */
11813         u32 rx = 0, tx = 0, i;
11814         for (i = 0; i < 2; i++) {
11815                 /* INT_PHY and EXT_PHY1 share the same value location in
11816                  * the shmem. When num_phys is greater than 1, than this value
11817                  * applies only to EXT_PHY1
11818                  */
11819                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
11820                         rx = REG_RD(bp, shmem_base +
11821                                     offsetof(struct shmem_region,
11822                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
11823
11824                         tx = REG_RD(bp, shmem_base +
11825                                     offsetof(struct shmem_region,
11826                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
11827                 } else {
11828                         rx = REG_RD(bp, shmem_base +
11829                                     offsetof(struct shmem_region,
11830                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11831
11832                         tx = REG_RD(bp, shmem_base +
11833                                     offsetof(struct shmem_region,
11834                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
11835                 }
11836
11837                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
11838                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
11839
11840                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
11841                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
11842         }
11843 }
11844
11845 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
11846                                     u8 phy_index, u8 port)
11847 {
11848         u32 ext_phy_config = 0;
11849         switch (phy_index) {
11850         case EXT_PHY1:
11851                 ext_phy_config = REG_RD(bp, shmem_base +
11852                                               offsetof(struct shmem_region,
11853                         dev_info.port_hw_config[port].external_phy_config));
11854                 break;
11855         case EXT_PHY2:
11856                 ext_phy_config = REG_RD(bp, shmem_base +
11857                                               offsetof(struct shmem_region,
11858                         dev_info.port_hw_config[port].external_phy_config2));
11859                 break;
11860         default:
11861                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
11862                 return -EINVAL;
11863         }
11864
11865         return ext_phy_config;
11866 }
11867 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
11868                                   struct bnx2x_phy *phy)
11869 {
11870         u32 phy_addr;
11871         u32 chip_id;
11872         u32 switch_cfg = (REG_RD(bp, shmem_base +
11873                                        offsetof(struct shmem_region,
11874                         dev_info.port_feature_config[port].link_config)) &
11875                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
11876         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
11877                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
11878
11879         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
11880         if (USES_WARPCORE(bp)) {
11881                 u32 serdes_net_if;
11882                 phy_addr = REG_RD(bp,
11883                                   MISC_REG_WC0_CTRL_PHY_ADDR);
11884                 *phy = phy_warpcore;
11885                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
11886                         phy->flags |= FLAGS_4_PORT_MODE;
11887                 else
11888                         phy->flags &= ~FLAGS_4_PORT_MODE;
11889                         /* Check Dual mode */
11890                 serdes_net_if = (REG_RD(bp, shmem_base +
11891                                         offsetof(struct shmem_region, dev_info.
11892                                         port_hw_config[port].default_cfg)) &
11893                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
11894                 /* Set the appropriate supported and flags indications per
11895                  * interface type of the chip
11896                  */
11897                 switch (serdes_net_if) {
11898                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
11899                         phy->supported &= (SUPPORTED_10baseT_Half |
11900                                            SUPPORTED_10baseT_Full |
11901                                            SUPPORTED_100baseT_Half |
11902                                            SUPPORTED_100baseT_Full |
11903                                            SUPPORTED_1000baseT_Full |
11904                                            SUPPORTED_FIBRE |
11905                                            SUPPORTED_Autoneg |
11906                                            SUPPORTED_Pause |
11907                                            SUPPORTED_Asym_Pause);
11908                         phy->media_type = ETH_PHY_BASE_T;
11909                         break;
11910                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
11911                         phy->supported &= (SUPPORTED_1000baseT_Full |
11912                                            SUPPORTED_10000baseT_Full |
11913                                            SUPPORTED_FIBRE |
11914                                            SUPPORTED_Pause |
11915                                            SUPPORTED_Asym_Pause);
11916                         phy->media_type = ETH_PHY_XFP_FIBER;
11917                         break;
11918                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
11919                         phy->supported &= (SUPPORTED_1000baseT_Full |
11920                                            SUPPORTED_10000baseT_Full |
11921                                            SUPPORTED_FIBRE |
11922                                            SUPPORTED_Pause |
11923                                            SUPPORTED_Asym_Pause);
11924                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
11925                         break;
11926                 case PORT_HW_CFG_NET_SERDES_IF_KR:
11927                         phy->media_type = ETH_PHY_KR;
11928                         phy->supported &= (SUPPORTED_1000baseT_Full |
11929                                            SUPPORTED_10000baseT_Full |
11930                                            SUPPORTED_FIBRE |
11931                                            SUPPORTED_Autoneg |
11932                                            SUPPORTED_Pause |
11933                                            SUPPORTED_Asym_Pause);
11934                         break;
11935                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
11936                         phy->media_type = ETH_PHY_KR;
11937                         phy->flags |= FLAGS_WC_DUAL_MODE;
11938                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
11939                                            SUPPORTED_FIBRE |
11940                                            SUPPORTED_Pause |
11941                                            SUPPORTED_Asym_Pause);
11942                         break;
11943                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
11944                         phy->media_type = ETH_PHY_KR;
11945                         phy->flags |= FLAGS_WC_DUAL_MODE;
11946                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
11947                                            SUPPORTED_10000baseT_Full |
11948                                            SUPPORTED_1000baseT_Full |
11949                                            SUPPORTED_Autoneg |
11950                                            SUPPORTED_FIBRE |
11951                                            SUPPORTED_Pause |
11952                                            SUPPORTED_Asym_Pause);
11953                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
11954                         break;
11955                 default:
11956                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
11957                                        serdes_net_if);
11958                         break;
11959                 }
11960
11961                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11962                  * was not set as expected. For B0, ECO will be enabled so there
11963                  * won't be an issue there
11964                  */
11965                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11966                         phy->flags |= FLAGS_MDC_MDIO_WA;
11967                 else
11968                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
11969         } else {
11970                 switch (switch_cfg) {
11971                 case SWITCH_CFG_1G:
11972                         phy_addr = REG_RD(bp,
11973                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
11974                                           port * 0x10);
11975                         *phy = phy_serdes;
11976                         break;
11977                 case SWITCH_CFG_10G:
11978                         phy_addr = REG_RD(bp,
11979                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
11980                                           port * 0x18);
11981                         *phy = phy_xgxs;
11982                         break;
11983                 default:
11984                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
11985                         return -EINVAL;
11986                 }
11987         }
11988         phy->addr = (u8)phy_addr;
11989         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
11990                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
11991                                             port);
11992         if (CHIP_IS_E2(bp))
11993                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
11994         else
11995                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
11996
11997         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11998                    port, phy->addr, phy->mdio_ctrl);
11999
12000         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12001         return 0;
12002 }
12003
12004 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12005                                   u8 phy_index,
12006                                   u32 shmem_base,
12007                                   u32 shmem2_base,
12008                                   u8 port,
12009                                   struct bnx2x_phy *phy)
12010 {
12011         u32 ext_phy_config, phy_type, config2;
12012         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12013         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12014                                                   phy_index, port);
12015         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12016         /* Select the phy type */
12017         switch (phy_type) {
12018         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12019                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12020                 *phy = phy_8073;
12021                 break;
12022         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12023                 *phy = phy_8705;
12024                 break;
12025         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12026                 *phy = phy_8706;
12027                 break;
12028         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12029                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12030                 *phy = phy_8726;
12031                 break;
12032         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12033                 /* BCM8727_NOC => BCM8727 no over current */
12034                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12035                 *phy = phy_8727;
12036                 phy->flags |= FLAGS_NOC;
12037                 break;
12038         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12039         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12040                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12041                 *phy = phy_8727;
12042                 break;
12043         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12044                 *phy = phy_8481;
12045                 break;
12046         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12047                 *phy = phy_84823;
12048                 break;
12049         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12050                 *phy = phy_84833;
12051                 break;
12052         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12053                 *phy = phy_84834;
12054                 break;
12055         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12056         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12057                 *phy = phy_54618se;
12058                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12059                         phy->flags |= FLAGS_EEE;
12060                 break;
12061         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12062                 *phy = phy_7101;
12063                 break;
12064         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12065                 *phy = phy_null;
12066                 return -EINVAL;
12067         default:
12068                 *phy = phy_null;
12069                 /* In case external PHY wasn't found */
12070                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12071                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12072                         return -EINVAL;
12073                 return 0;
12074         }
12075
12076         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12077         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12078
12079         /* The shmem address of the phy version is located on different
12080          * structures. In case this structure is too old, do not set
12081          * the address
12082          */
12083         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12084                                         dev_info.shared_hw_config.config2));
12085         if (phy_index == EXT_PHY1) {
12086                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12087                                 port_mb[port].ext_phy_fw_version);
12088
12089                 /* Check specific mdc mdio settings */
12090                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12091                         mdc_mdio_access = config2 &
12092                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12093         } else {
12094                 u32 size = REG_RD(bp, shmem2_base);
12095
12096                 if (size >
12097                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12098                         phy->ver_addr = shmem2_base +
12099                             offsetof(struct shmem2_region,
12100                                      ext_phy_fw_version2[port]);
12101                 }
12102                 /* Check specific mdc mdio settings */
12103                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12104                         mdc_mdio_access = (config2 &
12105                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12106                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12107                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12108         }
12109         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12110
12111         if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12112              (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12113             (phy->ver_addr)) {
12114                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12115                  * version lower than or equal to 1.39
12116                  */
12117                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12118                 if (((raw_ver & 0x7F) <= 39) &&
12119                     (((raw_ver & 0xF80) >> 7) <= 1))
12120                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12121                                             SUPPORTED_100baseT_Full);
12122         }
12123
12124         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12125                    phy_type, port, phy_index);
12126         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12127                    phy->addr, phy->mdio_ctrl);
12128         return 0;
12129 }
12130
12131 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12132                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12133 {
12134         int status = 0;
12135         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12136         if (phy_index == INT_PHY)
12137                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12138         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12139                                         port, phy);
12140         return status;
12141 }
12142
12143 static void bnx2x_phy_def_cfg(struct link_params *params,
12144                               struct bnx2x_phy *phy,
12145                               u8 phy_index)
12146 {
12147         struct bnx2x *bp = params->bp;
12148         u32 link_config;
12149         /* Populate the default phy configuration for MF mode */
12150         if (phy_index == EXT_PHY2) {
12151                 link_config = REG_RD(bp, params->shmem_base +
12152                                      offsetof(struct shmem_region, dev_info.
12153                         port_feature_config[params->port].link_config2));
12154                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12155                                              offsetof(struct shmem_region,
12156                                                       dev_info.
12157                         port_hw_config[params->port].speed_capability_mask2));
12158         } else {
12159                 link_config = REG_RD(bp, params->shmem_base +
12160                                      offsetof(struct shmem_region, dev_info.
12161                                 port_feature_config[params->port].link_config));
12162                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12163                                              offsetof(struct shmem_region,
12164                                                       dev_info.
12165                         port_hw_config[params->port].speed_capability_mask));
12166         }
12167         DP(NETIF_MSG_LINK,
12168            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12169            phy_index, link_config, phy->speed_cap_mask);
12170
12171         phy->req_duplex = DUPLEX_FULL;
12172         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12173         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12174                 phy->req_duplex = DUPLEX_HALF;
12175         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12176                 phy->req_line_speed = SPEED_10;
12177                 break;
12178         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12179                 phy->req_duplex = DUPLEX_HALF;
12180         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12181                 phy->req_line_speed = SPEED_100;
12182                 break;
12183         case PORT_FEATURE_LINK_SPEED_1G:
12184                 phy->req_line_speed = SPEED_1000;
12185                 break;
12186         case PORT_FEATURE_LINK_SPEED_2_5G:
12187                 phy->req_line_speed = SPEED_2500;
12188                 break;
12189         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12190                 phy->req_line_speed = SPEED_10000;
12191                 break;
12192         default:
12193                 phy->req_line_speed = SPEED_AUTO_NEG;
12194                 break;
12195         }
12196
12197         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12198         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12199                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12200                 break;
12201         case PORT_FEATURE_FLOW_CONTROL_TX:
12202                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12203                 break;
12204         case PORT_FEATURE_FLOW_CONTROL_RX:
12205                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12206                 break;
12207         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12208                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12209                 break;
12210         default:
12211                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12212                 break;
12213         }
12214 }
12215
12216 u32 bnx2x_phy_selection(struct link_params *params)
12217 {
12218         u32 phy_config_swapped, prio_cfg;
12219         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12220
12221         phy_config_swapped = params->multi_phy_config &
12222                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12223
12224         prio_cfg = params->multi_phy_config &
12225                         PORT_HW_CFG_PHY_SELECTION_MASK;
12226
12227         if (phy_config_swapped) {
12228                 switch (prio_cfg) {
12229                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12230                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12231                      break;
12232                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12233                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12234                      break;
12235                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12236                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12237                      break;
12238                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12239                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12240                      break;
12241                 }
12242         } else
12243                 return_cfg = prio_cfg;
12244
12245         return return_cfg;
12246 }
12247
12248 int bnx2x_phy_probe(struct link_params *params)
12249 {
12250         u8 phy_index, actual_phy_idx;
12251         u32 phy_config_swapped, sync_offset, media_types;
12252         struct bnx2x *bp = params->bp;
12253         struct bnx2x_phy *phy;
12254         params->num_phys = 0;
12255         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12256         phy_config_swapped = params->multi_phy_config &
12257                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12258
12259         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12260               phy_index++) {
12261                 actual_phy_idx = phy_index;
12262                 if (phy_config_swapped) {
12263                         if (phy_index == EXT_PHY1)
12264                                 actual_phy_idx = EXT_PHY2;
12265                         else if (phy_index == EXT_PHY2)
12266                                 actual_phy_idx = EXT_PHY1;
12267                 }
12268                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12269                                " actual_phy_idx %x\n", phy_config_swapped,
12270                            phy_index, actual_phy_idx);
12271                 phy = &params->phy[actual_phy_idx];
12272                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12273                                        params->shmem2_base, params->port,
12274                                        phy) != 0) {
12275                         params->num_phys = 0;
12276                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12277                                    phy_index);
12278                         for (phy_index = INT_PHY;
12279                               phy_index < MAX_PHYS;
12280                               phy_index++)
12281                                 *phy = phy_null;
12282                         return -EINVAL;
12283                 }
12284                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12285                         break;
12286
12287                 if (params->feature_config_flags &
12288                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12289                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12290
12291                 if (!(params->feature_config_flags &
12292                       FEATURE_CONFIG_MT_SUPPORT))
12293                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12294
12295                 sync_offset = params->shmem_base +
12296                         offsetof(struct shmem_region,
12297                         dev_info.port_hw_config[params->port].media_type);
12298                 media_types = REG_RD(bp, sync_offset);
12299
12300                 /* Update media type for non-PMF sync only for the first time
12301                  * In case the media type changes afterwards, it will be updated
12302                  * using the update_status function
12303                  */
12304                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12305                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12306                                      actual_phy_idx))) == 0) {
12307                         media_types |= ((phy->media_type &
12308                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12309                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12310                                  actual_phy_idx));
12311                 }
12312                 REG_WR(bp, sync_offset, media_types);
12313
12314                 bnx2x_phy_def_cfg(params, phy, phy_index);
12315                 params->num_phys++;
12316         }
12317
12318         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12319         return 0;
12320 }
12321
12322 static void bnx2x_init_bmac_loopback(struct link_params *params,
12323                                      struct link_vars *vars)
12324 {
12325         struct bnx2x *bp = params->bp;
12326                 vars->link_up = 1;
12327                 vars->line_speed = SPEED_10000;
12328                 vars->duplex = DUPLEX_FULL;
12329                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12330                 vars->mac_type = MAC_TYPE_BMAC;
12331
12332                 vars->phy_flags = PHY_XGXS_FLAG;
12333
12334                 bnx2x_xgxs_deassert(params);
12335
12336                 /* Set bmac loopback */
12337                 bnx2x_bmac_enable(params, vars, 1, 1);
12338
12339                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12340 }
12341
12342 static void bnx2x_init_emac_loopback(struct link_params *params,
12343                                      struct link_vars *vars)
12344 {
12345         struct bnx2x *bp = params->bp;
12346                 vars->link_up = 1;
12347                 vars->line_speed = SPEED_1000;
12348                 vars->duplex = DUPLEX_FULL;
12349                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12350                 vars->mac_type = MAC_TYPE_EMAC;
12351
12352                 vars->phy_flags = PHY_XGXS_FLAG;
12353
12354                 bnx2x_xgxs_deassert(params);
12355                 /* Set bmac loopback */
12356                 bnx2x_emac_enable(params, vars, 1);
12357                 bnx2x_emac_program(params, vars);
12358                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12359 }
12360
12361 static void bnx2x_init_xmac_loopback(struct link_params *params,
12362                                      struct link_vars *vars)
12363 {
12364         struct bnx2x *bp = params->bp;
12365         vars->link_up = 1;
12366         if (!params->req_line_speed[0])
12367                 vars->line_speed = SPEED_10000;
12368         else
12369                 vars->line_speed = params->req_line_speed[0];
12370         vars->duplex = DUPLEX_FULL;
12371         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12372         vars->mac_type = MAC_TYPE_XMAC;
12373         vars->phy_flags = PHY_XGXS_FLAG;
12374         /* Set WC to loopback mode since link is required to provide clock
12375          * to the XMAC in 20G mode
12376          */
12377         bnx2x_set_aer_mmd(params, &params->phy[0]);
12378         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12379         params->phy[INT_PHY].config_loopback(
12380                         &params->phy[INT_PHY],
12381                         params);
12382
12383         bnx2x_xmac_enable(params, vars, 1);
12384         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12385 }
12386
12387 static void bnx2x_init_umac_loopback(struct link_params *params,
12388                                      struct link_vars *vars)
12389 {
12390         struct bnx2x *bp = params->bp;
12391         vars->link_up = 1;
12392         vars->line_speed = SPEED_1000;
12393         vars->duplex = DUPLEX_FULL;
12394         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12395         vars->mac_type = MAC_TYPE_UMAC;
12396         vars->phy_flags = PHY_XGXS_FLAG;
12397         bnx2x_umac_enable(params, vars, 1);
12398
12399         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12400 }
12401
12402 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12403                                      struct link_vars *vars)
12404 {
12405         struct bnx2x *bp = params->bp;
12406         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12407         vars->link_up = 1;
12408         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12409         vars->duplex = DUPLEX_FULL;
12410         if (params->req_line_speed[0] == SPEED_1000)
12411                 vars->line_speed = SPEED_1000;
12412         else if ((params->req_line_speed[0] == SPEED_20000) ||
12413                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12414                 vars->line_speed = SPEED_20000;
12415         else
12416                 vars->line_speed = SPEED_10000;
12417
12418         if (!USES_WARPCORE(bp))
12419                 bnx2x_xgxs_deassert(params);
12420         bnx2x_link_initialize(params, vars);
12421
12422         if (params->req_line_speed[0] == SPEED_1000) {
12423                 if (USES_WARPCORE(bp))
12424                         bnx2x_umac_enable(params, vars, 0);
12425                 else {
12426                         bnx2x_emac_program(params, vars);
12427                         bnx2x_emac_enable(params, vars, 0);
12428                 }
12429         } else {
12430                 if (USES_WARPCORE(bp))
12431                         bnx2x_xmac_enable(params, vars, 0);
12432                 else
12433                         bnx2x_bmac_enable(params, vars, 0, 1);
12434         }
12435
12436         if (params->loopback_mode == LOOPBACK_XGXS) {
12437                 /* Set 10G XGXS loopback */
12438                 int_phy->config_loopback(int_phy, params);
12439         } else {
12440                 /* Set external phy loopback */
12441                 u8 phy_index;
12442                 for (phy_index = EXT_PHY1;
12443                       phy_index < params->num_phys; phy_index++)
12444                         if (params->phy[phy_index].config_loopback)
12445                                 params->phy[phy_index].config_loopback(
12446                                         &params->phy[phy_index],
12447                                         params);
12448         }
12449         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12450
12451         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12452 }
12453
12454 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12455 {
12456         struct bnx2x *bp = params->bp;
12457         u8 val = en * 0x1F;
12458
12459         /* Open / close the gate between the NIG and the BRB */
12460         if (!CHIP_IS_E1x(bp))
12461                 val |= en * 0x20;
12462         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12463
12464         if (!CHIP_IS_E1(bp)) {
12465                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12466                        en*0x3);
12467         }
12468
12469         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12470                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12471 }
12472 static int bnx2x_avoid_link_flap(struct link_params *params,
12473                                             struct link_vars *vars)
12474 {
12475         u32 phy_idx;
12476         u32 dont_clear_stat, lfa_sts;
12477         struct bnx2x *bp = params->bp;
12478
12479         /* Sync the link parameters */
12480         bnx2x_link_status_update(params, vars);
12481
12482         /*
12483          * The module verification was already done by previous link owner,
12484          * so this call is meant only to get warning message
12485          */
12486
12487         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12488                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12489                 if (phy->phy_specific_func) {
12490                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12491                         phy->phy_specific_func(phy, params, PHY_INIT);
12492                 }
12493                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12494                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12495                     (phy->media_type == ETH_PHY_DA_TWINAX))
12496                         bnx2x_verify_sfp_module(phy, params);
12497         }
12498         lfa_sts = REG_RD(bp, params->lfa_base +
12499                          offsetof(struct shmem_lfa,
12500                                   lfa_sts));
12501
12502         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12503
12504         /* Re-enable the NIG/MAC */
12505         if (CHIP_IS_E3(bp)) {
12506                 if (!dont_clear_stat) {
12507                         REG_WR(bp, GRCBASE_MISC +
12508                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12509                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12510                                 params->port));
12511                         REG_WR(bp, GRCBASE_MISC +
12512                                MISC_REGISTERS_RESET_REG_2_SET,
12513                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12514                                 params->port));
12515                 }
12516                 if (vars->line_speed < SPEED_10000)
12517                         bnx2x_umac_enable(params, vars, 0);
12518                 else
12519                         bnx2x_xmac_enable(params, vars, 0);
12520         } else {
12521                 if (vars->line_speed < SPEED_10000)
12522                         bnx2x_emac_enable(params, vars, 0);
12523                 else
12524                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12525         }
12526
12527         /* Increment LFA count */
12528         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12529                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12530                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12531                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12532         /* Clear link flap reason */
12533         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12534
12535         REG_WR(bp, params->lfa_base +
12536                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12537
12538         /* Disable NIG DRAIN */
12539         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12540
12541         /* Enable interrupts */
12542         bnx2x_link_int_enable(params);
12543         return 0;
12544 }
12545
12546 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12547                                          struct link_vars *vars,
12548                                          int lfa_status)
12549 {
12550         u32 lfa_sts, cfg_idx, tmp_val;
12551         struct bnx2x *bp = params->bp;
12552
12553         bnx2x_link_reset(params, vars, 1);
12554
12555         if (!params->lfa_base)
12556                 return;
12557         /* Store the new link parameters */
12558         REG_WR(bp, params->lfa_base +
12559                offsetof(struct shmem_lfa, req_duplex),
12560                params->req_duplex[0] | (params->req_duplex[1] << 16));
12561
12562         REG_WR(bp, params->lfa_base +
12563                offsetof(struct shmem_lfa, req_flow_ctrl),
12564                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12565
12566         REG_WR(bp, params->lfa_base +
12567                offsetof(struct shmem_lfa, req_line_speed),
12568                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12569
12570         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12571                 REG_WR(bp, params->lfa_base +
12572                        offsetof(struct shmem_lfa,
12573                                 speed_cap_mask[cfg_idx]),
12574                        params->speed_cap_mask[cfg_idx]);
12575         }
12576
12577         tmp_val = REG_RD(bp, params->lfa_base +
12578                          offsetof(struct shmem_lfa, additional_config));
12579         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
12580         tmp_val |= params->req_fc_auto_adv;
12581
12582         REG_WR(bp, params->lfa_base +
12583                offsetof(struct shmem_lfa, additional_config), tmp_val);
12584
12585         lfa_sts = REG_RD(bp, params->lfa_base +
12586                          offsetof(struct shmem_lfa, lfa_sts));
12587
12588         /* Clear the "Don't Clear Statistics" bit, and set reason */
12589         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
12590
12591         /* Set link flap reason */
12592         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12593         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
12594                     LFA_LINK_FLAP_REASON_OFFSET);
12595
12596         /* Increment link flap counter */
12597         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
12598                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
12599                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
12600                     << LINK_FLAP_COUNT_OFFSET));
12601         REG_WR(bp, params->lfa_base +
12602                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12603         /* Proceed with regular link initialization */
12604 }
12605
12606 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
12607 {
12608         int lfa_status;
12609         struct bnx2x *bp = params->bp;
12610         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
12611         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
12612                    params->req_line_speed[0], params->req_flow_ctrl[0]);
12613         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
12614                    params->req_line_speed[1], params->req_flow_ctrl[1]);
12615         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
12616         vars->link_status = 0;
12617         vars->phy_link_up = 0;
12618         vars->link_up = 0;
12619         vars->line_speed = 0;
12620         vars->duplex = DUPLEX_FULL;
12621         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12622         vars->mac_type = MAC_TYPE_NONE;
12623         vars->phy_flags = 0;
12624         vars->check_kr2_recovery_cnt = 0;
12625         params->link_flags = PHY_INITIALIZED;
12626         /* Driver opens NIG-BRB filters */
12627         bnx2x_set_rx_filter(params, 1);
12628         /* Check if link flap can be avoided */
12629         lfa_status = bnx2x_check_lfa(params);
12630
12631         if (lfa_status == 0) {
12632                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
12633                 return bnx2x_avoid_link_flap(params, vars);
12634         }
12635
12636         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
12637                        lfa_status);
12638         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
12639
12640         /* Disable attentions */
12641         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
12642                        (NIG_MASK_XGXS0_LINK_STATUS |
12643                         NIG_MASK_XGXS0_LINK10G |
12644                         NIG_MASK_SERDES0_LINK_STATUS |
12645                         NIG_MASK_MI_INT));
12646
12647         bnx2x_emac_init(params, vars);
12648
12649         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
12650                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
12651
12652         if (params->num_phys == 0) {
12653                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
12654                 return -EINVAL;
12655         }
12656         set_phy_vars(params, vars);
12657
12658         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
12659         switch (params->loopback_mode) {
12660         case LOOPBACK_BMAC:
12661                 bnx2x_init_bmac_loopback(params, vars);
12662                 break;
12663         case LOOPBACK_EMAC:
12664                 bnx2x_init_emac_loopback(params, vars);
12665                 break;
12666         case LOOPBACK_XMAC:
12667                 bnx2x_init_xmac_loopback(params, vars);
12668                 break;
12669         case LOOPBACK_UMAC:
12670                 bnx2x_init_umac_loopback(params, vars);
12671                 break;
12672         case LOOPBACK_XGXS:
12673         case LOOPBACK_EXT_PHY:
12674                 bnx2x_init_xgxs_loopback(params, vars);
12675                 break;
12676         default:
12677                 if (!CHIP_IS_E3(bp)) {
12678                         if (params->switch_cfg == SWITCH_CFG_10G)
12679                                 bnx2x_xgxs_deassert(params);
12680                         else
12681                                 bnx2x_serdes_deassert(bp, params->port);
12682                 }
12683                 bnx2x_link_initialize(params, vars);
12684                 msleep(30);
12685                 bnx2x_link_int_enable(params);
12686                 break;
12687         }
12688         bnx2x_update_mng(params, vars->link_status);
12689
12690         bnx2x_update_mng_eee(params, vars->eee_status);
12691         return 0;
12692 }
12693
12694 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
12695                      u8 reset_ext_phy)
12696 {
12697         struct bnx2x *bp = params->bp;
12698         u8 phy_index, port = params->port, clear_latch_ind = 0;
12699         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
12700         /* Disable attentions */
12701         vars->link_status = 0;
12702         bnx2x_update_mng(params, vars->link_status);
12703         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
12704                               SHMEM_EEE_ACTIVE_BIT);
12705         bnx2x_update_mng_eee(params, vars->eee_status);
12706         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
12707                        (NIG_MASK_XGXS0_LINK_STATUS |
12708                         NIG_MASK_XGXS0_LINK10G |
12709                         NIG_MASK_SERDES0_LINK_STATUS |
12710                         NIG_MASK_MI_INT));
12711
12712         /* Activate nig drain */
12713         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
12714
12715         /* Disable nig egress interface */
12716         if (!CHIP_IS_E3(bp)) {
12717                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
12718                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
12719         }
12720
12721                 if (!CHIP_IS_E3(bp)) {
12722                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
12723                 } else {
12724                         bnx2x_set_xmac_rxtx(params, 0);
12725                         bnx2x_set_umac_rxtx(params, 0);
12726                 }
12727         /* Disable emac */
12728         if (!CHIP_IS_E3(bp))
12729                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
12730
12731         usleep_range(10000, 20000);
12732         /* The PHY reset is controlled by GPIO 1
12733          * Hold it as vars low
12734          */
12735          /* Clear link led */
12736         bnx2x_set_mdio_emac_per_phy(bp, params);
12737         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
12738
12739         if (reset_ext_phy) {
12740                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
12741                       phy_index++) {
12742                         if (params->phy[phy_index].link_reset) {
12743                                 bnx2x_set_aer_mmd(params,
12744                                                   &params->phy[phy_index]);
12745                                 params->phy[phy_index].link_reset(
12746                                         &params->phy[phy_index],
12747                                         params);
12748                         }
12749                         if (params->phy[phy_index].flags &
12750                             FLAGS_REARM_LATCH_SIGNAL)
12751                                 clear_latch_ind = 1;
12752                 }
12753         }
12754
12755         if (clear_latch_ind) {
12756                 /* Clear latching indication */
12757                 bnx2x_rearm_latch_signal(bp, port, 0);
12758                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
12759                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
12760         }
12761         if (params->phy[INT_PHY].link_reset)
12762                 params->phy[INT_PHY].link_reset(
12763                         &params->phy[INT_PHY], params);
12764
12765         /* Disable nig ingress interface */
12766         if (!CHIP_IS_E3(bp)) {
12767                 /* Reset BigMac */
12768                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
12769                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
12770                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
12771                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
12772         } else {
12773                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
12774                 bnx2x_set_xumac_nig(params, 0, 0);
12775                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
12776                     MISC_REGISTERS_RESET_REG_2_XMAC)
12777                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
12778                                XMAC_CTRL_REG_SOFT_RESET);
12779         }
12780         vars->link_up = 0;
12781         vars->phy_flags = 0;
12782         return 0;
12783 }
12784 int bnx2x_lfa_reset(struct link_params *params,
12785                                struct link_vars *vars)
12786 {
12787         struct bnx2x *bp = params->bp;
12788         vars->link_up = 0;
12789         vars->phy_flags = 0;
12790         params->link_flags &= ~PHY_INITIALIZED;
12791         if (!params->lfa_base)
12792                 return bnx2x_link_reset(params, vars, 1);
12793         /*
12794          * Activate NIG drain so that during this time the device won't send
12795          * anything while it is unable to response.
12796          */
12797         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
12798
12799         /*
12800          * Close gracefully the gate from BMAC to NIG such that no half packets
12801          * are passed.
12802          */
12803         if (!CHIP_IS_E3(bp))
12804                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
12805
12806         if (CHIP_IS_E3(bp)) {
12807                 bnx2x_set_xmac_rxtx(params, 0);
12808                 bnx2x_set_umac_rxtx(params, 0);
12809         }
12810         /* Wait 10ms for the pipe to clean up*/
12811         usleep_range(10000, 20000);
12812
12813         /* Clean the NIG-BRB using the network filters in a way that will
12814          * not cut a packet in the middle.
12815          */
12816         bnx2x_set_rx_filter(params, 0);
12817
12818         /*
12819          * Re-open the gate between the BMAC and the NIG, after verifying the
12820          * gate to the BRB is closed, otherwise packets may arrive to the
12821          * firmware before driver had initialized it. The target is to achieve
12822          * minimum management protocol down time.
12823          */
12824         if (!CHIP_IS_E3(bp))
12825                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
12826
12827         if (CHIP_IS_E3(bp)) {
12828                 bnx2x_set_xmac_rxtx(params, 1);
12829                 bnx2x_set_umac_rxtx(params, 1);
12830         }
12831         /* Disable NIG drain */
12832         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12833         return 0;
12834 }
12835
12836 /****************************************************************************/
12837 /*                              Common function                             */
12838 /****************************************************************************/
12839 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
12840                                       u32 shmem_base_path[],
12841                                       u32 shmem2_base_path[], u8 phy_index,
12842                                       u32 chip_id)
12843 {
12844         struct bnx2x_phy phy[PORT_MAX];
12845         struct bnx2x_phy *phy_blk[PORT_MAX];
12846         u16 val;
12847         s8 port = 0;
12848         s8 port_of_path = 0;
12849         u32 swap_val, swap_override;
12850         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
12851         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
12852         port ^= (swap_val && swap_override);
12853         bnx2x_ext_phy_hw_reset(bp, port);
12854         /* PART1 - Reset both phys */
12855         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12856                 u32 shmem_base, shmem2_base;
12857                 /* In E2, same phy is using for port0 of the two paths */
12858                 if (CHIP_IS_E1x(bp)) {
12859                         shmem_base = shmem_base_path[0];
12860                         shmem2_base = shmem2_base_path[0];
12861                         port_of_path = port;
12862                 } else {
12863                         shmem_base = shmem_base_path[port];
12864                         shmem2_base = shmem2_base_path[port];
12865                         port_of_path = 0;
12866                 }
12867
12868                 /* Extract the ext phy address for the port */
12869                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12870                                        port_of_path, &phy[port]) !=
12871                     0) {
12872                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
12873                         return -EINVAL;
12874                 }
12875                 /* Disable attentions */
12876                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
12877                                port_of_path*4,
12878                                (NIG_MASK_XGXS0_LINK_STATUS |
12879                                 NIG_MASK_XGXS0_LINK10G |
12880                                 NIG_MASK_SERDES0_LINK_STATUS |
12881                                 NIG_MASK_MI_INT));
12882
12883                 /* Need to take the phy out of low power mode in order
12884                  * to write to access its registers
12885                  */
12886                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12887                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
12888                                port);
12889
12890                 /* Reset the phy */
12891                 bnx2x_cl45_write(bp, &phy[port],
12892                                  MDIO_PMA_DEVAD,
12893                                  MDIO_PMA_REG_CTRL,
12894                                  1<<15);
12895         }
12896
12897         /* Add delay of 150ms after reset */
12898         msleep(150);
12899
12900         if (phy[PORT_0].addr & 0x1) {
12901                 phy_blk[PORT_0] = &(phy[PORT_1]);
12902                 phy_blk[PORT_1] = &(phy[PORT_0]);
12903         } else {
12904                 phy_blk[PORT_0] = &(phy[PORT_0]);
12905                 phy_blk[PORT_1] = &(phy[PORT_1]);
12906         }
12907
12908         /* PART2 - Download firmware to both phys */
12909         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12910                 if (CHIP_IS_E1x(bp))
12911                         port_of_path = port;
12912                 else
12913                         port_of_path = 0;
12914
12915                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
12916                            phy_blk[port]->addr);
12917                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
12918                                                       port_of_path))
12919                         return -EINVAL;
12920
12921                 /* Only set bit 10 = 1 (Tx power down) */
12922                 bnx2x_cl45_read(bp, phy_blk[port],
12923                                 MDIO_PMA_DEVAD,
12924                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12925
12926                 /* Phase1 of TX_POWER_DOWN reset */
12927                 bnx2x_cl45_write(bp, phy_blk[port],
12928                                  MDIO_PMA_DEVAD,
12929                                  MDIO_PMA_REG_TX_POWER_DOWN,
12930                                  (val | 1<<10));
12931         }
12932
12933         /* Toggle Transmitter: Power down and then up with 600ms delay
12934          * between
12935          */
12936         msleep(600);
12937
12938         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12939         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
12940                 /* Phase2 of POWER_DOWN_RESET */
12941                 /* Release bit 10 (Release Tx power down) */
12942                 bnx2x_cl45_read(bp, phy_blk[port],
12943                                 MDIO_PMA_DEVAD,
12944                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
12945
12946                 bnx2x_cl45_write(bp, phy_blk[port],
12947                                 MDIO_PMA_DEVAD,
12948                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
12949                 usleep_range(15000, 30000);
12950
12951                 /* Read modify write the SPI-ROM version select register */
12952                 bnx2x_cl45_read(bp, phy_blk[port],
12953                                 MDIO_PMA_DEVAD,
12954                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
12955                 bnx2x_cl45_write(bp, phy_blk[port],
12956                                  MDIO_PMA_DEVAD,
12957                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
12958
12959                 /* set GPIO2 back to LOW */
12960                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
12961                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
12962         }
12963         return 0;
12964 }
12965 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
12966                                       u32 shmem_base_path[],
12967                                       u32 shmem2_base_path[], u8 phy_index,
12968                                       u32 chip_id)
12969 {
12970         u32 val;
12971         s8 port;
12972         struct bnx2x_phy phy;
12973         /* Use port1 because of the static port-swap */
12974         /* Enable the module detection interrupt */
12975         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
12976         val |= ((1<<MISC_REGISTERS_GPIO_3)|
12977                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
12978         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
12979
12980         bnx2x_ext_phy_hw_reset(bp, 0);
12981         usleep_range(5000, 10000);
12982         for (port = 0; port < PORT_MAX; port++) {
12983                 u32 shmem_base, shmem2_base;
12984
12985                 /* In E2, same phy is using for port0 of the two paths */
12986                 if (CHIP_IS_E1x(bp)) {
12987                         shmem_base = shmem_base_path[0];
12988                         shmem2_base = shmem2_base_path[0];
12989                 } else {
12990                         shmem_base = shmem_base_path[port];
12991                         shmem2_base = shmem2_base_path[port];
12992                 }
12993                 /* Extract the ext phy address for the port */
12994                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
12995                                        port, &phy) !=
12996                     0) {
12997                         DP(NETIF_MSG_LINK, "populate phy failed\n");
12998                         return -EINVAL;
12999                 }
13000
13001                 /* Reset phy*/
13002                 bnx2x_cl45_write(bp, &phy,
13003                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13004
13005
13006                 /* Set fault module detected LED on */
13007                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13008                                MISC_REGISTERS_GPIO_HIGH,
13009                                port);
13010         }
13011
13012         return 0;
13013 }
13014 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13015                                          u8 *io_gpio, u8 *io_port)
13016 {
13017
13018         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13019                                           offsetof(struct shmem_region,
13020                                 dev_info.port_hw_config[PORT_0].default_cfg));
13021         switch (phy_gpio_reset) {
13022         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13023                 *io_gpio = 0;
13024                 *io_port = 0;
13025                 break;
13026         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13027                 *io_gpio = 1;
13028                 *io_port = 0;
13029                 break;
13030         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13031                 *io_gpio = 2;
13032                 *io_port = 0;
13033                 break;
13034         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13035                 *io_gpio = 3;
13036                 *io_port = 0;
13037                 break;
13038         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13039                 *io_gpio = 0;
13040                 *io_port = 1;
13041                 break;
13042         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13043                 *io_gpio = 1;
13044                 *io_port = 1;
13045                 break;
13046         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13047                 *io_gpio = 2;
13048                 *io_port = 1;
13049                 break;
13050         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13051                 *io_gpio = 3;
13052                 *io_port = 1;
13053                 break;
13054         default:
13055                 /* Don't override the io_gpio and io_port */
13056                 break;
13057         }
13058 }
13059
13060 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13061                                       u32 shmem_base_path[],
13062                                       u32 shmem2_base_path[], u8 phy_index,
13063                                       u32 chip_id)
13064 {
13065         s8 port, reset_gpio;
13066         u32 swap_val, swap_override;
13067         struct bnx2x_phy phy[PORT_MAX];
13068         struct bnx2x_phy *phy_blk[PORT_MAX];
13069         s8 port_of_path;
13070         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13071         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13072
13073         reset_gpio = MISC_REGISTERS_GPIO_1;
13074         port = 1;
13075
13076         /* Retrieve the reset gpio/port which control the reset.
13077          * Default is GPIO1, PORT1
13078          */
13079         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13080                                      (u8 *)&reset_gpio, (u8 *)&port);
13081
13082         /* Calculate the port based on port swap */
13083         port ^= (swap_val && swap_override);
13084
13085         /* Initiate PHY reset*/
13086         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13087                        port);
13088         usleep_range(1000, 2000);
13089         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13090                        port);
13091
13092         usleep_range(5000, 10000);
13093
13094         /* PART1 - Reset both phys */
13095         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13096                 u32 shmem_base, shmem2_base;
13097
13098                 /* In E2, same phy is using for port0 of the two paths */
13099                 if (CHIP_IS_E1x(bp)) {
13100                         shmem_base = shmem_base_path[0];
13101                         shmem2_base = shmem2_base_path[0];
13102                         port_of_path = port;
13103                 } else {
13104                         shmem_base = shmem_base_path[port];
13105                         shmem2_base = shmem2_base_path[port];
13106                         port_of_path = 0;
13107                 }
13108
13109                 /* Extract the ext phy address for the port */
13110                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13111                                        port_of_path, &phy[port]) !=
13112                                        0) {
13113                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13114                         return -EINVAL;
13115                 }
13116                 /* disable attentions */
13117                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13118                                port_of_path*4,
13119                                (NIG_MASK_XGXS0_LINK_STATUS |
13120                                 NIG_MASK_XGXS0_LINK10G |
13121                                 NIG_MASK_SERDES0_LINK_STATUS |
13122                                 NIG_MASK_MI_INT));
13123
13124
13125                 /* Reset the phy */
13126                 bnx2x_cl45_write(bp, &phy[port],
13127                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13128         }
13129
13130         /* Add delay of 150ms after reset */
13131         msleep(150);
13132         if (phy[PORT_0].addr & 0x1) {
13133                 phy_blk[PORT_0] = &(phy[PORT_1]);
13134                 phy_blk[PORT_1] = &(phy[PORT_0]);
13135         } else {
13136                 phy_blk[PORT_0] = &(phy[PORT_0]);
13137                 phy_blk[PORT_1] = &(phy[PORT_1]);
13138         }
13139         /* PART2 - Download firmware to both phys */
13140         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13141                 if (CHIP_IS_E1x(bp))
13142                         port_of_path = port;
13143                 else
13144                         port_of_path = 0;
13145                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13146                            phy_blk[port]->addr);
13147                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13148                                                       port_of_path))
13149                         return -EINVAL;
13150                 /* Disable PHY transmitter output */
13151                 bnx2x_cl45_write(bp, phy_blk[port],
13152                                  MDIO_PMA_DEVAD,
13153                                  MDIO_PMA_REG_TX_DISABLE, 1);
13154
13155         }
13156         return 0;
13157 }
13158
13159 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13160                                                 u32 shmem_base_path[],
13161                                                 u32 shmem2_base_path[],
13162                                                 u8 phy_index,
13163                                                 u32 chip_id)
13164 {
13165         u8 reset_gpios;
13166         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13167         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13168         udelay(10);
13169         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13170         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13171                 reset_gpios);
13172         return 0;
13173 }
13174
13175 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13176                                      u32 shmem2_base_path[], u8 phy_index,
13177                                      u32 ext_phy_type, u32 chip_id)
13178 {
13179         int rc = 0;
13180
13181         switch (ext_phy_type) {
13182         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13183                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13184                                                 shmem2_base_path,
13185                                                 phy_index, chip_id);
13186                 break;
13187         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13188         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13189         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13190                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13191                                                 shmem2_base_path,
13192                                                 phy_index, chip_id);
13193                 break;
13194
13195         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13196                 /* GPIO1 affects both ports, so there's need to pull
13197                  * it for single port alone
13198                  */
13199                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13200                                                 shmem2_base_path,
13201                                                 phy_index, chip_id);
13202                 break;
13203         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13204         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13205                 /* GPIO3's are linked, and so both need to be toggled
13206                  * to obtain required 2us pulse.
13207                  */
13208                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13209                                                 shmem2_base_path,
13210                                                 phy_index, chip_id);
13211                 break;
13212         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13213                 rc = -EINVAL;
13214                 break;
13215         default:
13216                 DP(NETIF_MSG_LINK,
13217                            "ext_phy 0x%x common init not required\n",
13218                            ext_phy_type);
13219                 break;
13220         }
13221
13222         if (rc)
13223                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13224                                       " Port %d\n",
13225                          0);
13226         return rc;
13227 }
13228
13229 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13230                           u32 shmem2_base_path[], u32 chip_id)
13231 {
13232         int rc = 0;
13233         u32 phy_ver, val;
13234         u8 phy_index = 0;
13235         u32 ext_phy_type, ext_phy_config;
13236
13237         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13238         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13239         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13240         if (CHIP_IS_E3(bp)) {
13241                 /* Enable EPIO */
13242                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13243                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13244         }
13245         /* Check if common init was already done */
13246         phy_ver = REG_RD(bp, shmem_base_path[0] +
13247                          offsetof(struct shmem_region,
13248                                   port_mb[PORT_0].ext_phy_fw_version));
13249         if (phy_ver) {
13250                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13251                                phy_ver);
13252                 return 0;
13253         }
13254
13255         /* Read the ext_phy_type for arbitrary port(0) */
13256         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13257               phy_index++) {
13258                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13259                                                           shmem_base_path[0],
13260                                                           phy_index, 0);
13261                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13262                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13263                                                 shmem2_base_path,
13264                                                 phy_index, ext_phy_type,
13265                                                 chip_id);
13266         }
13267         return rc;
13268 }
13269
13270 static void bnx2x_check_over_curr(struct link_params *params,
13271                                   struct link_vars *vars)
13272 {
13273         struct bnx2x *bp = params->bp;
13274         u32 cfg_pin;
13275         u8 port = params->port;
13276         u32 pin_val;
13277
13278         cfg_pin = (REG_RD(bp, params->shmem_base +
13279                           offsetof(struct shmem_region,
13280                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13281                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13282                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13283
13284         /* Ignore check if no external input PIN available */
13285         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13286                 return;
13287
13288         if (!pin_val) {
13289                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13290                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13291                                             " been detected and the power to "
13292                                             "that SFP+ module has been removed"
13293                                             " to prevent failure of the card."
13294                                             " Please remove the SFP+ module and"
13295                                             " restart the system to clear this"
13296                                             " error.\n",
13297                          params->port);
13298                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13299                         bnx2x_warpcore_power_module(params, 0);
13300                 }
13301         } else
13302                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13303 }
13304
13305 /* Returns 0 if no change occured since last check; 1 otherwise. */
13306 static u8 bnx2x_analyze_link_error(struct link_params *params,
13307                                     struct link_vars *vars, u32 status,
13308                                     u32 phy_flag, u32 link_flag, u8 notify)
13309 {
13310         struct bnx2x *bp = params->bp;
13311         /* Compare new value with previous value */
13312         u8 led_mode;
13313         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13314
13315         if ((status ^ old_status) == 0)
13316                 return 0;
13317
13318         /* If values differ */
13319         switch (phy_flag) {
13320         case PHY_HALF_OPEN_CONN_FLAG:
13321                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13322                 break;
13323         case PHY_SFP_TX_FAULT_FLAG:
13324                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13325                 break;
13326         default:
13327                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13328         }
13329         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13330            old_status, status);
13331
13332         /* a. Update shmem->link_status accordingly
13333          * b. Update link_vars->link_up
13334          */
13335         if (status) {
13336                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13337                 vars->link_status |= link_flag;
13338                 vars->link_up = 0;
13339                 vars->phy_flags |= phy_flag;
13340
13341                 /* activate nig drain */
13342                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13343                 /* Set LED mode to off since the PHY doesn't know about these
13344                  * errors
13345                  */
13346                 led_mode = LED_MODE_OFF;
13347         } else {
13348                 vars->link_status |= LINK_STATUS_LINK_UP;
13349                 vars->link_status &= ~link_flag;
13350                 vars->link_up = 1;
13351                 vars->phy_flags &= ~phy_flag;
13352                 led_mode = LED_MODE_OPER;
13353
13354                 /* Clear nig drain */
13355                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13356         }
13357         bnx2x_sync_link(params, vars);
13358         /* Update the LED according to the link state */
13359         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13360
13361         /* Update link status in the shared memory */
13362         bnx2x_update_mng(params, vars->link_status);
13363
13364         /* C. Trigger General Attention */
13365         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13366         if (notify)
13367                 bnx2x_notify_link_changed(bp);
13368
13369         return 1;
13370 }
13371
13372 /******************************************************************************
13373 * Description:
13374 *       This function checks for half opened connection change indication.
13375 *       When such change occurs, it calls the bnx2x_analyze_link_error
13376 *       to check if Remote Fault is set or cleared. Reception of remote fault
13377 *       status message in the MAC indicates that the peer's MAC has detected
13378 *       a fault, for example, due to break in the TX side of fiber.
13379 *
13380 ******************************************************************************/
13381 int bnx2x_check_half_open_conn(struct link_params *params,
13382                                 struct link_vars *vars,
13383                                 u8 notify)
13384 {
13385         struct bnx2x *bp = params->bp;
13386         u32 lss_status = 0;
13387         u32 mac_base;
13388         /* In case link status is physically up @ 10G do */
13389         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13390             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13391                 return 0;
13392
13393         if (CHIP_IS_E3(bp) &&
13394             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13395               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13396                 /* Check E3 XMAC */
13397                 /* Note that link speed cannot be queried here, since it may be
13398                  * zero while link is down. In case UMAC is active, LSS will
13399                  * simply not be set
13400                  */
13401                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13402
13403                 /* Clear stick bits (Requires rising edge) */
13404                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13405                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13406                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13407                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13408                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13409                         lss_status = 1;
13410
13411                 bnx2x_analyze_link_error(params, vars, lss_status,
13412                                          PHY_HALF_OPEN_CONN_FLAG,
13413                                          LINK_STATUS_NONE, notify);
13414         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13415                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13416                 /* Check E1X / E2 BMAC */
13417                 u32 lss_status_reg;
13418                 u32 wb_data[2];
13419                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13420                         NIG_REG_INGRESS_BMAC0_MEM;
13421                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13422                 if (CHIP_IS_E2(bp))
13423                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13424                 else
13425                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13426
13427                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13428                 lss_status = (wb_data[0] > 0);
13429
13430                 bnx2x_analyze_link_error(params, vars, lss_status,
13431                                          PHY_HALF_OPEN_CONN_FLAG,
13432                                          LINK_STATUS_NONE, notify);
13433         }
13434         return 0;
13435 }
13436 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13437                                          struct link_params *params,
13438                                          struct link_vars *vars)
13439 {
13440         struct bnx2x *bp = params->bp;
13441         u32 cfg_pin, value = 0;
13442         u8 led_change, port = params->port;
13443
13444         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13445         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13446                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13447                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13448                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13449
13450         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13451                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13452                 return;
13453         }
13454
13455         led_change = bnx2x_analyze_link_error(params, vars, value,
13456                                               PHY_SFP_TX_FAULT_FLAG,
13457                                               LINK_STATUS_SFP_TX_FAULT, 1);
13458
13459         if (led_change) {
13460                 /* Change TX_Fault led, set link status for further syncs */
13461                 u8 led_mode;
13462
13463                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13464                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13465                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13466                 } else {
13467                         led_mode = MISC_REGISTERS_GPIO_LOW;
13468                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13469                 }
13470
13471                 /* If module is unapproved, led should be on regardless */
13472                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13473                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13474                            led_mode);
13475                         bnx2x_set_e3_module_fault_led(params, led_mode);
13476                 }
13477         }
13478 }
13479 static void bnx2x_kr2_recovery(struct link_params *params,
13480                                struct link_vars *vars,
13481                                struct bnx2x_phy *phy)
13482 {
13483         struct bnx2x *bp = params->bp;
13484         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13485         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13486         bnx2x_warpcore_restart_AN_KR(phy, params);
13487 }
13488
13489 static void bnx2x_check_kr2_wa(struct link_params *params,
13490                                struct link_vars *vars,
13491                                struct bnx2x_phy *phy)
13492 {
13493         struct bnx2x *bp = params->bp;
13494         u16 base_page, next_page, not_kr2_device, lane;
13495         int sigdet;
13496
13497         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13498          * Since some switches tend to reinit the AN process and clear the
13499          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13500          * and recovered many times
13501          */
13502         if (vars->check_kr2_recovery_cnt > 0) {
13503                 vars->check_kr2_recovery_cnt--;
13504                 return;
13505         }
13506
13507         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13508         if (!sigdet) {
13509                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13510                         bnx2x_kr2_recovery(params, vars, phy);
13511                         DP(NETIF_MSG_LINK, "No sigdet\n");
13512                 }
13513                 return;
13514         }
13515
13516         lane = bnx2x_get_warpcore_lane(phy, params);
13517         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13518                           MDIO_AER_BLOCK_AER_REG, lane);
13519         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13520                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13521         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13522                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13523         bnx2x_set_aer_mmd(params, phy);
13524
13525         /* CL73 has not begun yet */
13526         if (base_page == 0) {
13527                 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13528                         bnx2x_kr2_recovery(params, vars, phy);
13529                         DP(NETIF_MSG_LINK, "No BP\n");
13530                 }
13531                 return;
13532         }
13533
13534         /* In case NP bit is not set in the BasePage, or it is set,
13535          * but only KX is advertised, declare this link partner as non-KR2
13536          * device.
13537          */
13538         not_kr2_device = (((base_page & 0x8000) == 0) ||
13539                           (((base_page & 0x8000) &&
13540                             ((next_page & 0xe0) == 0x2))));
13541
13542         /* In case KR2 is already disabled, check if we need to re-enable it */
13543         if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13544                 if (!not_kr2_device) {
13545                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13546                            next_page);
13547                         bnx2x_kr2_recovery(params, vars, phy);
13548                 }
13549                 return;
13550         }
13551         /* KR2 is enabled, but not KR2 device */
13552         if (not_kr2_device) {
13553                 /* Disable KR2 on both lanes */
13554                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13555                 bnx2x_disable_kr2(params, vars, phy);
13556                 /* Restart AN on leading lane */
13557                 bnx2x_warpcore_restart_AN_KR(phy, params);
13558                 return;
13559         }
13560 }
13561
13562 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13563 {
13564         u16 phy_idx;
13565         struct bnx2x *bp = params->bp;
13566         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13567                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13568                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13569                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
13570                             0)
13571                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
13572                         break;
13573                 }
13574         }
13575
13576         if (CHIP_IS_E3(bp)) {
13577                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
13578                 bnx2x_set_aer_mmd(params, phy);
13579                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
13580                     (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
13581                         bnx2x_check_kr2_wa(params, vars, phy);
13582                 bnx2x_check_over_curr(params, vars);
13583                 if (vars->rx_tx_asic_rst)
13584                         bnx2x_warpcore_config_runtime(phy, params, vars);
13585
13586                 if ((REG_RD(bp, params->shmem_base +
13587                             offsetof(struct shmem_region, dev_info.
13588                                 port_hw_config[params->port].default_cfg))
13589                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
13590                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
13591                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
13592                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
13593                         } else if (vars->link_status &
13594                                 LINK_STATUS_SFP_TX_FAULT) {
13595                                 /* Clean trail, interrupt corrects the leds */
13596                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13597                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
13598                                 /* Update link status in the shared memory */
13599                                 bnx2x_update_mng(params, vars->link_status);
13600                         }
13601                 }
13602         }
13603 }
13604
13605 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
13606                              u32 shmem_base,
13607                              u32 shmem2_base,
13608                              u8 port)
13609 {
13610         u8 phy_index, fan_failure_det_req = 0;
13611         struct bnx2x_phy phy;
13612         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13613               phy_index++) {
13614                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13615                                        port, &phy)
13616                     != 0) {
13617                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13618                         return 0;
13619                 }
13620                 fan_failure_det_req |= (phy.flags &
13621                                         FLAGS_FAN_FAILURE_DET_REQ);
13622         }
13623         return fan_failure_det_req;
13624 }
13625
13626 void bnx2x_hw_reset_phy(struct link_params *params)
13627 {
13628         u8 phy_index;
13629         struct bnx2x *bp = params->bp;
13630         bnx2x_update_mng(params, 0);
13631         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13632                        (NIG_MASK_XGXS0_LINK_STATUS |
13633                         NIG_MASK_XGXS0_LINK10G |
13634                         NIG_MASK_SERDES0_LINK_STATUS |
13635                         NIG_MASK_MI_INT));
13636
13637         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
13638               phy_index++) {
13639                 if (params->phy[phy_index].hw_reset) {
13640                         params->phy[phy_index].hw_reset(
13641                                 &params->phy[phy_index],
13642                                 params);
13643                         params->phy[phy_index] = phy_null;
13644                 }
13645         }
13646 }
13647
13648 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
13649                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
13650                             u8 port)
13651 {
13652         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
13653         u32 val;
13654         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
13655         if (CHIP_IS_E3(bp)) {
13656                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
13657                                               shmem_base,
13658                                               port,
13659                                               &gpio_num,
13660                                               &gpio_port) != 0)
13661                         return;
13662         } else {
13663                 struct bnx2x_phy phy;
13664                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13665                       phy_index++) {
13666                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
13667                                                shmem2_base, port, &phy)
13668                             != 0) {
13669                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
13670                                 return;
13671                         }
13672                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
13673                                 gpio_num = MISC_REGISTERS_GPIO_3;
13674                                 gpio_port = port;
13675                                 break;
13676                         }
13677                 }
13678         }
13679
13680         if (gpio_num == 0xff)
13681                 return;
13682
13683         /* Set GPIO3 to trigger SFP+ module insertion/removal */
13684         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
13685
13686         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13687         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13688         gpio_port ^= (swap_val && swap_override);
13689
13690         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
13691                 (gpio_num + (gpio_port << 2));
13692
13693         sync_offset = shmem_base +
13694                 offsetof(struct shmem_region,
13695                          dev_info.port_hw_config[port].aeu_int_mask);
13696         REG_WR(bp, sync_offset, vars->aeu_int_mask);
13697
13698         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13699                        gpio_num, gpio_port, vars->aeu_int_mask);
13700
13701         if (port == 0)
13702                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13703         else
13704                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13705
13706         /* Open appropriate AEU for interrupts */
13707         aeu_mask = REG_RD(bp, offset);
13708         aeu_mask |= vars->aeu_int_mask;
13709         REG_WR(bp, offset, aeu_mask);
13710
13711         /* Enable the GPIO to trigger interrupt */
13712         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13713         val |= 1 << (gpio_num + (gpio_port << 2));
13714         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13715 }