1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
13 #include "bnx2x_mfw_req.h"
15 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
22 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
23 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
24 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
29 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
30 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
31 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
32 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
37 /****************************************************************************
38 * Shared HW configuration *
39 ****************************************************************************/
40 #define PIN_CFG_NA 0x00000000
41 #define PIN_CFG_GPIO0_P0 0x00000001
42 #define PIN_CFG_GPIO1_P0 0x00000002
43 #define PIN_CFG_GPIO2_P0 0x00000003
44 #define PIN_CFG_GPIO3_P0 0x00000004
45 #define PIN_CFG_GPIO0_P1 0x00000005
46 #define PIN_CFG_GPIO1_P1 0x00000006
47 #define PIN_CFG_GPIO2_P1 0x00000007
48 #define PIN_CFG_GPIO3_P1 0x00000008
49 #define PIN_CFG_EPIO0 0x00000009
50 #define PIN_CFG_EPIO1 0x0000000a
51 #define PIN_CFG_EPIO2 0x0000000b
52 #define PIN_CFG_EPIO3 0x0000000c
53 #define PIN_CFG_EPIO4 0x0000000d
54 #define PIN_CFG_EPIO5 0x0000000e
55 #define PIN_CFG_EPIO6 0x0000000f
56 #define PIN_CFG_EPIO7 0x00000010
57 #define PIN_CFG_EPIO8 0x00000011
58 #define PIN_CFG_EPIO9 0x00000012
59 #define PIN_CFG_EPIO10 0x00000013
60 #define PIN_CFG_EPIO11 0x00000014
61 #define PIN_CFG_EPIO12 0x00000015
62 #define PIN_CFG_EPIO13 0x00000016
63 #define PIN_CFG_EPIO14 0x00000017
64 #define PIN_CFG_EPIO15 0x00000018
65 #define PIN_CFG_EPIO16 0x00000019
66 #define PIN_CFG_EPIO17 0x0000001a
67 #define PIN_CFG_EPIO18 0x0000001b
68 #define PIN_CFG_EPIO19 0x0000001c
69 #define PIN_CFG_EPIO20 0x0000001d
70 #define PIN_CFG_EPIO21 0x0000001e
71 #define PIN_CFG_EPIO22 0x0000001f
72 #define PIN_CFG_EPIO23 0x00000020
73 #define PIN_CFG_EPIO24 0x00000021
74 #define PIN_CFG_EPIO25 0x00000022
75 #define PIN_CFG_EPIO26 0x00000023
76 #define PIN_CFG_EPIO27 0x00000024
77 #define PIN_CFG_EPIO28 0x00000025
78 #define PIN_CFG_EPIO29 0x00000026
79 #define PIN_CFG_EPIO30 0x00000027
80 #define PIN_CFG_EPIO31 0x00000028
83 #define EPIO_CFG_NA 0x00000000
84 #define EPIO_CFG_EPIO0 0x00000001
85 #define EPIO_CFG_EPIO1 0x00000002
86 #define EPIO_CFG_EPIO2 0x00000003
87 #define EPIO_CFG_EPIO3 0x00000004
88 #define EPIO_CFG_EPIO4 0x00000005
89 #define EPIO_CFG_EPIO5 0x00000006
90 #define EPIO_CFG_EPIO6 0x00000007
91 #define EPIO_CFG_EPIO7 0x00000008
92 #define EPIO_CFG_EPIO8 0x00000009
93 #define EPIO_CFG_EPIO9 0x0000000a
94 #define EPIO_CFG_EPIO10 0x0000000b
95 #define EPIO_CFG_EPIO11 0x0000000c
96 #define EPIO_CFG_EPIO12 0x0000000d
97 #define EPIO_CFG_EPIO13 0x0000000e
98 #define EPIO_CFG_EPIO14 0x0000000f
99 #define EPIO_CFG_EPIO15 0x00000010
100 #define EPIO_CFG_EPIO16 0x00000011
101 #define EPIO_CFG_EPIO17 0x00000012
102 #define EPIO_CFG_EPIO18 0x00000013
103 #define EPIO_CFG_EPIO19 0x00000014
104 #define EPIO_CFG_EPIO20 0x00000015
105 #define EPIO_CFG_EPIO21 0x00000016
106 #define EPIO_CFG_EPIO22 0x00000017
107 #define EPIO_CFG_EPIO23 0x00000018
108 #define EPIO_CFG_EPIO24 0x00000019
109 #define EPIO_CFG_EPIO25 0x0000001a
110 #define EPIO_CFG_EPIO26 0x0000001b
111 #define EPIO_CFG_EPIO27 0x0000001c
112 #define EPIO_CFG_EPIO28 0x0000001d
113 #define EPIO_CFG_EPIO29 0x0000001e
114 #define EPIO_CFG_EPIO30 0x0000001f
115 #define EPIO_CFG_EPIO31 0x00000020
122 struct shared_hw_cfg { /* NVRAM Offset */
123 /* Up to 16 bytes of NULL-terminated string */
124 u8 part_num[16]; /* 0x104 */
126 u32 config; /* 0x114 */
127 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
128 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
131 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
133 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
135 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
137 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
138 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
140 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
141 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
142 /* Whatever MFW found in NVM
143 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
144 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
145 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
146 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
147 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
148 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
149 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
150 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
151 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
152 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
153 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
154 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
155 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
156 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
158 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
159 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
160 #define SHARED_HW_CFG_LED_MAC1 0x00000000
161 #define SHARED_HW_CFG_LED_PHY1 0x00010000
162 #define SHARED_HW_CFG_LED_PHY2 0x00020000
163 #define SHARED_HW_CFG_LED_PHY3 0x00030000
164 #define SHARED_HW_CFG_LED_MAC2 0x00040000
165 #define SHARED_HW_CFG_LED_PHY4 0x00050000
166 #define SHARED_HW_CFG_LED_PHY5 0x00060000
167 #define SHARED_HW_CFG_LED_PHY6 0x00070000
168 #define SHARED_HW_CFG_LED_MAC3 0x00080000
169 #define SHARED_HW_CFG_LED_PHY7 0x00090000
170 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
171 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
172 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
173 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
174 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
177 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
178 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
179 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
180 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
181 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
182 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
183 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
184 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
186 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
187 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
188 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
190 #define SHARED_HW_CFG_ATC_MASK 0x80000000
191 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
192 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
194 u32 config2; /* 0x118 */
195 /* one time auto detect grace period (in sec) */
196 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
197 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
199 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
200 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
202 /* The default value for the core clock is 250MHz and it is
203 achieved by setting the clock change to 4 */
204 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
205 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
207 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
208 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
209 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
211 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
213 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
214 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
215 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
217 /* Output low when PERST is asserted */
218 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
222 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
229 /* The fan failure mechanism is usually related to the PHY type
230 since the power consumption of the board is determined by the PHY.
231 Currently, fan is required for most designs with SFX7101, BCM8727
232 and BCM8481. If a fan is not required for a board which uses one
233 of those PHYs, this field should be set to "Disabled". If a fan is
234 required for a different PHY type, this option should be set to
235 "Enabled". The fan failure indication is expected on SPIO5 */
236 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
237 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
238 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
239 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
240 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
242 /* ASPM Power Management support */
243 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
244 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
245 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
250 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
251 tl_control_0 (register 0x2800) */
252 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
256 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
257 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
258 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
260 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
261 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
262 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
264 /* Set the MDC/MDIO access for the first external phy */
265 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
273 /* Set the MDC/MDIO access for the second external phy */
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
283 u32 power_dissipated; /* 0x11c */
284 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
286 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
287 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
288 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
289 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
291 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
292 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
294 u32 ump_nc_si_config; /* 0x120 */
295 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
302 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
305 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
310 u32 board; /* 0x124 */
311 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
312 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
315 /* Use the PIN_CFG_XXX defines on top */
316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
325 u32 wc_lane_config; /* 0x128 */
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
337 /* TX lane Polarity swap */
338 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
339 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
340 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
341 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
342 /* TX lane Polarity swap */
343 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
344 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
345 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
346 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
348 /* Selects the port layout of the board */
349 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
360 /****************************************************************************
361 * Port HW configuration *
362 ****************************************************************************/
363 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
366 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
367 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
370 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
371 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
373 u32 power_dissipated;
374 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
375 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
376 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
377 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
378 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
379 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
380 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
381 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
384 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
385 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
386 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
387 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
388 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
389 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
390 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
391 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
394 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
395 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
398 u32 iscsi_mac_upper; /* Upper 16 bits are always zeroes */
401 u32 rdma_mac_upper; /* Upper 16 bits are always zeroes */
405 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
408 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
412 /* Default values: 2P-64, 4P-32 */
413 u32 pf_config; /* 0x158 */
414 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
415 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
417 /* Default values: 17 */
418 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
421 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
422 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
424 u32 vf_config; /* 0x15C */
425 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
428 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
431 u32 mf_pci_id; /* 0x160 */
432 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
435 /* Controls the TX laser of the SFP+ module */
436 u32 sfp_ctrl; /* 0x164 */
437 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
438 #define PORT_HW_CFG_TX_LASER_SHIFT 0
439 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
440 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
441 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
442 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
443 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
445 /* Controls the fault module LED of the SFP+ */
446 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
447 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
452 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
454 /* The output pin TX_DIS that controls the TX laser of the SFP+
455 module. Use the PIN_CFG_XXX defines on top */
456 u32 e3_sfp_ctrl; /* 0x168 */
457 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
458 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
460 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
461 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
464 /* The input pin MOD_ABS that indicates whether SFP+ module is
465 present or not. Use the PIN_CFG_XXX defines on top */
466 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
467 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
469 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
470 module. Use the PIN_CFG_XXX defines on top */
471 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
472 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
475 * The input pin which signals module transmit fault. Use the
476 * PIN_CFG_XXX defines on top
478 u32 e3_cmn_pin_cfg; /* 0x16C */
479 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
480 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
482 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
484 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
485 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
488 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
491 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
492 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
494 /* The output pin values BSC_SEL which selects the I2C for this port
496 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
497 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
501 * The input pin I_FAULT which indicate over-current has occurred.
502 * Use the PIN_CFG_XXX defines on top
504 u32 e3_cmn_pin_cfg1; /* 0x170 */
505 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
506 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
508 /* pause on host ring */
509 u32 generic_features; /* 0x174 */
510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
512 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
513 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
515 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
516 * LOM recommended and tested value is 0xBEB2. Using a different
517 * value means using a value not tested by BRCM
519 u32 sfi_tap_values; /* 0x178 */
520 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
521 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
523 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
524 * value is 0x2. LOM recommended and tested value is 0x2. Using a
525 * different value means using a value not tested by BRCM
527 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
528 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
530 u32 reserved0[5]; /* 0x17c */
532 u32 aeu_int_mask; /* 0x190 */
534 u32 media_type; /* 0x194 */
535 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
536 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
538 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
539 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
541 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
542 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
544 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
545 (not direct mode), those values will not take effect on the 4 XGXS
546 lanes. For some external PHYs (such as 8706 and 8726) the values
547 will be used to configure the external PHY in those cases, not
548 all 4 values are needed. */
549 u16 xgxs_config_rx[4]; /* 0x198 */
550 u16 xgxs_config_tx[4]; /* 0x1A0 */
552 /* For storing FCOE mac on shared memory */
553 u32 fcoe_fip_mac_upper;
554 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
555 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
556 u32 fcoe_fip_mac_lower;
558 u32 fcoe_wwn_port_name_upper;
559 u32 fcoe_wwn_port_name_lower;
561 u32 fcoe_wwn_node_name_upper;
562 u32 fcoe_wwn_node_name_lower;
564 u32 Reserved1[49]; /* 0x1C0 */
566 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
568 u32 xgbt_phy_cfg; /* 0x284 */
569 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
570 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
572 u32 default_cfg; /* 0x288 */
573 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
574 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
575 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
576 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
577 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
578 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
580 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
581 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
582 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
583 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
584 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
585 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
587 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
588 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
589 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
590 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
591 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
592 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
594 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
595 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
596 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
597 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
598 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
599 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
601 /* When KR link is required to be set to force which is not
602 KR-compliant, this parameter determine what is the trigger for it.
603 When GPIO is selected, low input will force the speed. Currently
604 default speed is 1G. In the future, it may be widen to select the
605 forced speed in with another parameter. Note when force-1G is
606 enabled, it override option 56: Link Speed option. */
607 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
608 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
609 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
610 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
611 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
612 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
613 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
614 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
615 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
616 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
617 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
618 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
619 /* Enable to determine with which GPIO to reset the external phy */
620 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
621 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
622 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
623 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
624 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
625 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
626 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
627 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
628 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
629 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
630 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
632 /* Enable BAM on KR */
633 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
634 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
635 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
636 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
638 /* Enable Common Mode Sense */
639 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
640 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
641 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
642 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
644 /* Determine the Serdes electrical interface */
645 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
646 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
647 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
648 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
649 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
650 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
651 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
652 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
655 u32 speed_capability_mask2; /* 0x28C */
656 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
657 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
658 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
659 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
660 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
661 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
662 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
663 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
664 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
665 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
667 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
668 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
669 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
670 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
671 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
672 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
673 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
674 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
675 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
676 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
679 /* In the case where two media types (e.g. copper and fiber) are
680 present and electrically active at the same time, PHY Selection
681 will determine which of the two PHYs will be designated as the
682 Active PHY and used for a connection to the network. */
683 u32 multi_phy_config; /* 0x290 */
684 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
685 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
686 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
687 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
688 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
689 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
690 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
692 /* When enabled, all second phy nvram parameters will be swapped
693 with the first phy parameters */
694 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
695 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
696 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
697 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
700 /* Address of the second external phy */
701 u32 external_phy_config2; /* 0x294 */
702 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
703 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
705 /* The second XGXS external PHY type */
706 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
707 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
708 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
709 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
710 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
711 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
712 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
713 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
714 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
715 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
716 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
717 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
718 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
719 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
720 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
721 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
722 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
723 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
724 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
725 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
726 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
727 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
730 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
731 8706, 8726 and 8727) not all 4 values are needed. */
732 u16 xgxs_config2_rx[4]; /* 0x296 */
733 u16 xgxs_config2_tx[4]; /* 0x2A0 */
736 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
737 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
739 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
741 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
743 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
745 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
746 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
747 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
748 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
749 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
750 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
751 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
753 /* Indicate whether to swap the external phy polarity */
754 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
755 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
756 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
759 u32 external_phy_config;
760 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
761 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
763 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
764 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
765 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
766 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
767 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
768 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
769 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
770 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
771 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
772 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
773 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
774 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
775 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
776 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
777 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
778 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
779 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
780 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
781 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
782 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
783 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
784 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
785 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
787 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
788 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
790 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
791 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
792 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
793 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
794 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
795 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
797 u32 speed_capability_mask;
798 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
799 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
800 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
801 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
802 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
803 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
804 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
805 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
806 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
807 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
808 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
810 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
811 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
812 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
813 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
814 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
815 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
816 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
817 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
818 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
819 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
820 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
822 /* A place to hold the original MAC address as a backup */
823 u32 backup_mac_upper; /* 0x2B4 */
824 u32 backup_mac_lower; /* 0x2B8 */
829 /****************************************************************************
830 * Shared Feature configuration *
831 ****************************************************************************/
832 struct shared_feat_cfg { /* NVRAM Offset */
834 u32 config; /* 0x450 */
835 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
837 /* Use NVRAM values instead of HW default values */
838 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
840 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
842 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
845 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
846 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
847 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
849 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
850 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
852 /* Override the OTP back to single function mode. When using GPIO,
853 high means only SF, 0 is according to CLP configuration */
854 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
855 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
856 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
857 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
858 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
859 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
860 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
862 /* The interval in seconds between sending LLDP packets. Set to zero
863 to disable the feature */
864 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
865 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
867 /* The assigned device type ID for LLDP usage */
868 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
869 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
874 /****************************************************************************
875 * Port Feature configuration *
876 ****************************************************************************/
877 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
880 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
881 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
882 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
883 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
884 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
885 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
886 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
887 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
888 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
889 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
890 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
891 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
892 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
893 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
894 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
895 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
896 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
897 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
898 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
899 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
900 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
901 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
902 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
903 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
904 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
905 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
906 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
907 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
908 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
909 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
910 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
911 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
912 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
913 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
914 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
915 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
917 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
918 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
919 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
921 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
922 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
923 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
925 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
926 #define PORT_FEATURE_EN_SIZE_SHIFT 24
927 #define PORT_FEATURE_WOL_ENABLED 0x01000000
928 #define PORT_FEATURE_MBA_ENABLED 0x02000000
929 #define PORT_FEATURE_MFW_ENABLED 0x04000000
931 /* Advertise expansion ROM even if MBA is disabled */
932 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
933 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
934 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
936 /* Check the optic vendor via i2c against a list of approved modules
937 in a separate nvram image */
938 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
939 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
940 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
942 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
944 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
945 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
948 /* Default is used when driver sets to "auto" mode */
949 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
950 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
951 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
952 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
953 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
954 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
955 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
956 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
957 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
960 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
961 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
962 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
963 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
964 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
965 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
966 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
967 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
969 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
970 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
972 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
973 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
974 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
975 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
976 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
977 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
978 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
979 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
980 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
981 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
982 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
983 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
984 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
985 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
986 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
987 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
988 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
989 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
990 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
991 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
992 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
993 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
994 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
995 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
996 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
997 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
998 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
999 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
1000 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1001 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1002 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1003 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1004 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
1005 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
1006 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1007 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
1008 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
1009 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
1010 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
1011 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
1012 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
1013 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
1014 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
1016 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
1017 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
1018 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
1021 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
1022 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1023 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1026 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
1027 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
1028 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1029 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1030 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1033 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1034 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1037 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1038 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1039 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1040 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1041 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1042 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1043 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1044 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1045 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1046 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1047 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1048 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1049 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1050 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1051 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1052 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1053 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1054 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1056 u32 link_config; /* Used as HW defaults for the driver */
1057 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1058 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1059 /* (forced) low speed switch (< 10G) */
1060 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1061 /* (forced) high speed switch (>= 10G) */
1062 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1063 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1064 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1066 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1067 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1068 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1069 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1070 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1071 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1072 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1073 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1074 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1075 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1076 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1078 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1079 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1080 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1081 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1082 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1083 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1084 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1086 /* The default for MCP link configuration,
1087 uses the same defines as link_config */
1088 u32 mfw_wol_link_cfg;
1090 /* The default for the driver of the second external phy,
1091 uses the same defines as link_config */
1092 u32 link_config2; /* 0x47C */
1094 /* The default for MCP of the second external phy,
1095 uses the same defines as link_config */
1096 u32 mfw_wol_link_cfg2; /* 0x480 */
1099 /* EEE power saving mode */
1100 u32 eee_power_mode; /* 0x484 */
1101 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1102 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1103 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1104 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1105 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1106 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1109 u32 Reserved2[16]; /* 0x488 */
1113 /****************************************************************************
1114 * Device Information *
1115 ****************************************************************************/
1116 struct shm_dev_info { /* size */
1118 u32 bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1120 struct shared_hw_cfg shared_hw_config; /* 40 */
1122 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1124 struct shared_feat_cfg shared_feature_config; /* 4 */
1126 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1131 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1132 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1143 #define E1_FUNC_MAX 2
1144 #define E1H_FUNC_MAX 8
1145 #define E2_FUNC_MAX 4 /* per path */
1154 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1155 /* This value (in milliseconds) determines the frequency of the driver
1156 * issuing the PULSE message code. The firmware monitors this periodic
1157 * pulse to determine when to switch to an OS-absent mode. */
1158 #define DRV_PULSE_PERIOD_MS 250
1160 /* This value (in milliseconds) determines how long the driver should
1161 * wait for an acknowledgement from the firmware before timing out. Once
1162 * the firmware has timed out, the driver will assume there is no firmware
1163 * running and there won't be any firmware-driver synchronization during a
1165 #define FW_ACK_TIME_OUT_MS 5000
1167 #define FW_ACK_POLL_TIME_MS 1
1169 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1171 #define MFW_TRACE_SIGNATURE 0x54524342
1173 /****************************************************************************
1174 * Driver <-> FW Mailbox *
1175 ****************************************************************************/
1176 struct drv_port_mb {
1179 /* Driver should update this field on any link change event */
1181 #define LINK_STATUS_NONE (0<<0)
1182 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1183 #define LINK_STATUS_LINK_UP 0x00000001
1184 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1185 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1186 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1187 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1188 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1189 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1190 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1191 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1192 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1193 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1194 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1195 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1196 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1197 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1198 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1199 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1200 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1202 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1203 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1205 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1206 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1207 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1209 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1210 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1211 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1212 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1213 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1214 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1215 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1217 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1218 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1220 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1221 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1223 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1224 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1225 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1226 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1227 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1229 #define LINK_STATUS_SERDES_LINK 0x00100000
1231 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1232 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1233 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1234 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1236 #define LINK_STATUS_PFC_ENABLED 0x20000000
1238 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1239 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1245 /* MCP firmware does not use this field */
1246 u32 ext_phy_fw_version;
1251 struct drv_func_mb {
1254 #define DRV_MSG_CODE_MASK 0xffff0000
1255 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1256 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1257 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1258 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1259 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1260 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1261 #define DRV_MSG_CODE_DCC_OK 0x30000000
1262 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1263 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1264 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1265 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1266 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1267 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1268 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1269 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1271 * The optic module verification command requires bootcode
1272 * v5.0.6 or later, te specific optic module verification command
1273 * requires bootcode v5.2.12 or later
1275 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1276 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1277 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1278 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1279 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1280 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1281 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1282 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1283 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1284 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1286 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1287 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1288 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1290 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1292 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1293 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1294 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1295 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1296 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1298 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1299 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1301 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1303 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1304 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1305 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1307 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1309 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1310 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1312 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1313 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1314 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1315 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1317 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1320 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1321 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1323 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1325 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1326 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1329 #define FW_MSG_CODE_MASK 0xffff0000
1330 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1331 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1332 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1333 /* Load common chip is supported from bc 6.0.0 */
1334 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1335 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1337 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1338 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1339 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1340 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1341 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1342 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1343 #define FW_MSG_CODE_DCC_DONE 0x30100000
1344 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1345 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1346 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1347 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1348 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1349 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1350 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1351 #define FW_MSG_CODE_NO_KEY 0x80f00000
1352 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1353 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1354 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1355 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1356 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1357 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1358 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1359 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1360 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1361 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1362 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1364 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1365 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1366 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1367 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1368 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1370 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1371 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1373 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1375 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1376 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1378 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1380 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1381 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1382 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1383 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1385 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1390 #define DRV_PULSE_SEQ_MASK 0x00007fff
1391 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1393 * The system time is in the format of
1394 * (year-2001)*12*32 + month*32 + day.
1396 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1398 * Indicate to the firmware not to go into the
1399 * OS-absent when it is not getting driver pulse.
1400 * This is used for debugging as well for PXE(MBA).
1404 #define MCP_PULSE_SEQ_MASK 0x00007fff
1405 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1406 /* Indicates to the driver not to assert due to lack
1407 * of MCP response */
1408 #define MCP_EVENT_MASK 0xffff0000
1409 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1411 u32 iscsi_boot_signature;
1412 u32 iscsi_boot_block_offset;
1415 #define DRV_STATUS_PMF 0x00000001
1416 #define DRV_STATUS_VF_DISABLED 0x00000002
1417 #define DRV_STATUS_SET_MF_BW 0x00000004
1418 #define DRV_STATUS_LINK_EVENT 0x00000008
1420 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1421 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1422 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1423 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1424 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1425 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1426 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1428 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1429 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1430 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1431 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1432 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1433 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1434 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1436 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1438 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1441 #define VIRT_MAC_SIGN_MASK 0xffff0000
1442 #define VIRT_MAC_SIGNATURE 0x564d0000
1448 /****************************************************************************
1449 * Management firmware state *
1450 ****************************************************************************/
1451 /* Allocate 440 bytes for management firmware */
1452 #define MGMTFW_STATE_WORD_SIZE 110
1454 struct mgmtfw_state {
1455 u32 opaque[MGMTFW_STATE_WORD_SIZE];
1459 /****************************************************************************
1460 * Multi-Function configuration *
1461 ****************************************************************************/
1462 struct shared_mf_cfg {
1465 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1467 #define SHARED_MF_CLP_EXIT 0x00000001
1469 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1473 struct port_mf_cfg {
1475 u32 dynamic_cfg; /* device control channel */
1476 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1477 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1478 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1484 struct func_mf_cfg {
1488 /* function 0 of each port cannot be hidden */
1489 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1491 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1492 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1493 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1494 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1495 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1496 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1497 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1499 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1500 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1503 /* 0 - low priority, 3 - high priority */
1504 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1505 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1506 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1509 /* value range - 0..100, increments in 100Mbps */
1510 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1511 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1512 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1513 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1514 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1515 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1517 u32 mac_upper; /* MAC */
1518 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1519 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1520 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1522 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1524 u32 e1hov_tag; /* VNI */
1525 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1526 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1527 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1529 /* afex default VLAN ID - 12 bits */
1530 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1531 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
1534 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
1535 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
1536 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
1537 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
1538 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
1539 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
1540 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
1545 enum mf_cfg_afex_vlan_mode {
1546 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
1547 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
1548 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
1551 /* This structure is not applicable and should not be accessed on 57711 */
1552 struct func_ext_cfg {
1554 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
1555 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1556 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1557 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1558 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1559 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1560 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
1562 u32 iscsi_mac_addr_upper;
1563 u32 iscsi_mac_addr_lower;
1565 u32 fcoe_mac_addr_upper;
1566 u32 fcoe_mac_addr_lower;
1568 u32 fcoe_wwn_port_name_upper;
1569 u32 fcoe_wwn_port_name_lower;
1571 u32 fcoe_wwn_node_name_upper;
1572 u32 fcoe_wwn_node_name_lower;
1575 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1576 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1577 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1578 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1579 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1580 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1585 struct shared_mf_cfg shared_mf_config; /* 0x4 */
1587 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
1588 /* for all chips, there are 8 mf functions */
1589 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
1591 * Extended configuration per function - this array does not exist and
1592 * should not be accessed on 57711
1594 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
1597 /****************************************************************************
1598 * Shared Memory Region *
1599 ****************************************************************************/
1600 struct shmem_region { /* SharedMem Offset (size) */
1602 u32 validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
1603 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1604 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1606 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1607 #define SHR_MEM_VALIDITY_MB 0x00200000
1608 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1609 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1610 /* One licensing bit should be set */
1611 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1612 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1613 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1614 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1616 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1617 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1618 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1619 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1620 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1621 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1623 struct shm_dev_info dev_info; /* 0x8 (0x438) */
1625 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
1627 /* FW information (for internal FW use) */
1628 u32 fw_info_fio_offset; /* 0x4a8 (0x4) */
1629 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
1631 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
1634 /* This is a variable length array */
1635 /* the number of function depends on the chip type */
1636 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1638 /* the number of function depends on the chip type */
1639 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1642 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1644 /****************************************************************************
1645 * Shared Memory 2 Region *
1646 ****************************************************************************/
1647 /* The fw_flr_ack is actually built in the following way: */
1649 /* 64 bit: VF ack */
1650 /* 8 bit: ios_dis_ack */
1651 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1652 /* u32. The fw must have the VF right after the PF since this is how it */
1653 /* access arrays(it expects always the VF to reside after the PF, and that */
1654 /* makes the calculation much easier for it. ) */
1655 /* In order to answer both limitations, and keep the struct small, the code */
1656 /* will abuse the structure defined here to achieve the actual partition */
1658 /****************************************************************************/
1668 struct fw_flr_ack ack;
1671 struct eee_remote_vals {
1676 /**** SUPPORT FOR SHMEM ARRRAYS ***
1677 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1678 * define arrays with storage types smaller then unsigned dwords.
1679 * The macros below add generic support for SHMEM arrays with numeric elements
1680 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1681 * array with individual bit-filed elements accessed using shifts and masks.
1685 /* eb is the bitwidth of a single element */
1686 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1687 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1689 /* the bit-position macro allows the used to flip the order of the arrays
1690 * elements on a per byte or word boundary.
1692 * example: an array with 8 entries each 4 bit wide. This array will fit into
1693 * a single dword. The diagrmas below show the array order of the nibbles.
1695 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1698 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1701 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1704 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1707 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1710 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1713 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1714 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1715 (((i)%((fb)/(eb))) * (eb)))
1717 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1718 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1719 SHMEM_ARRAY_MASK(eb))
1721 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1723 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1724 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1725 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1726 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1730 /****START OF DCBX STRUCTURES DECLARATIONS****/
1731 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1732 #define DCBX_PRI_PG_BITWIDTH 4
1733 #define DCBX_PRI_PG_FBITS 8
1734 #define DCBX_PRI_PG_GET(a, i) \
1735 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1736 #define DCBX_PRI_PG_SET(a, i, val) \
1737 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1738 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1739 #define DCBX_BW_PG_BITWIDTH 8
1740 #define DCBX_PG_BW_GET(a, i) \
1741 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1742 #define DCBX_PG_BW_SET(a, i, val) \
1743 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1744 #define DCBX_STRICT_PRI_PG 15
1745 #define DCBX_MAX_APP_PROTOCOL 16
1746 #define FCOE_APP_IDX 0
1747 #define ISCSI_APP_IDX 1
1748 #define PREDEFINED_APP_IDX_MAX 2
1751 /* Big/Little endian have the same representation. */
1752 struct dcbx_ets_feature {
1754 * For Admin MIB - is this feature supported by the
1755 * driver | For Local MIB - should this feature be enabled.
1762 /* Driver structure in LE */
1763 struct dcbx_pfc_feature {
1766 #define DCBX_PFC_PRI_0 0x01
1767 #define DCBX_PFC_PRI_1 0x02
1768 #define DCBX_PFC_PRI_2 0x04
1769 #define DCBX_PFC_PRI_3 0x08
1770 #define DCBX_PFC_PRI_4 0x10
1771 #define DCBX_PFC_PRI_5 0x20
1772 #define DCBX_PFC_PRI_6 0x40
1773 #define DCBX_PFC_PRI_7 0x80
1777 #elif defined(__LITTLE_ENDIAN)
1782 #define DCBX_PFC_PRI_0 0x01
1783 #define DCBX_PFC_PRI_1 0x02
1784 #define DCBX_PFC_PRI_2 0x04
1785 #define DCBX_PFC_PRI_3 0x08
1786 #define DCBX_PFC_PRI_4 0x10
1787 #define DCBX_PFC_PRI_5 0x20
1788 #define DCBX_PFC_PRI_6 0x40
1789 #define DCBX_PFC_PRI_7 0x80
1793 struct dcbx_app_priority_entry {
1798 #define DCBX_APP_ENTRY_VALID 0x01
1799 #define DCBX_APP_ENTRY_SF_MASK 0x30
1800 #define DCBX_APP_ENTRY_SF_SHIFT 4
1801 #define DCBX_APP_SF_ETH_TYPE 0x10
1802 #define DCBX_APP_SF_PORT 0x20
1803 #elif defined(__LITTLE_ENDIAN)
1805 #define DCBX_APP_ENTRY_VALID 0x01
1806 #define DCBX_APP_ENTRY_SF_MASK 0x30
1807 #define DCBX_APP_ENTRY_SF_SHIFT 4
1808 #define DCBX_APP_SF_ETH_TYPE 0x10
1809 #define DCBX_APP_SF_PORT 0x20
1816 /* FW structure in BE */
1817 struct dcbx_app_priority_feature {
1823 #elif defined(__LITTLE_ENDIAN)
1829 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
1832 /* FW structure in BE */
1833 struct dcbx_features {
1835 struct dcbx_ets_feature ets;
1837 struct dcbx_pfc_feature pfc;
1839 struct dcbx_app_priority_feature app;
1842 /* LLDP protocol parameters */
1843 /* FW structure in BE */
1844 struct lldp_params {
1846 u8 msg_fast_tx_interval;
1850 #define LLDP_TX_ONLY 0x01
1851 #define LLDP_RX_ONLY 0x02
1852 #define LLDP_TX_RX 0x03
1853 #define LLDP_DISABLED 0x04
1858 #elif defined(__LITTLE_ENDIAN)
1860 #define LLDP_TX_ONLY 0x01
1861 #define LLDP_RX_ONLY 0x02
1862 #define LLDP_TX_RX 0x03
1863 #define LLDP_DISABLED 0x04
1866 u8 msg_fast_tx_interval;
1872 #define REM_CHASSIS_ID_STAT_LEN 4
1873 #define REM_PORT_ID_STAT_LEN 4
1874 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1875 u32 peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
1876 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1877 u32 peer_port_id[REM_PORT_ID_STAT_LEN];
1880 struct lldp_dcbx_stat {
1881 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1882 #define LOCAL_PORT_ID_STAT_LEN 2
1883 /* Holds local Chassis ID 8B payload of constant subtype 4. */
1884 u32 local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
1885 /* Holds local Port ID 8B payload of constant subtype 3. */
1886 u32 local_port_id[LOCAL_PORT_ID_STAT_LEN];
1887 /* Number of DCBX frames transmitted. */
1888 u32 num_tx_dcbx_pkts;
1889 /* Number of DCBX frames received. */
1890 u32 num_rx_dcbx_pkts;
1893 /* ADMIN MIB - DCBX local machine default configuration. */
1894 struct lldp_admin_mib {
1896 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1897 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1898 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1899 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1900 #define DCBX_ETS_RECO_VALID 0x00000010
1901 #define DCBX_ETS_WILLING 0x00000020
1902 #define DCBX_PFC_WILLING 0x00000040
1903 #define DCBX_APP_WILLING 0x00000080
1904 #define DCBX_VERSION_CEE 0x00000100
1905 #define DCBX_VERSION_IEEE 0x00000200
1906 #define DCBX_DCBX_ENABLED 0x00000400
1907 #define DCBX_CEE_VERSION_MASK 0x0000f000
1908 #define DCBX_CEE_VERSION_SHIFT 12
1909 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1910 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1911 struct dcbx_features features;
1914 /* REMOTE MIB - remote machine DCBX configuration. */
1915 struct lldp_remote_mib {
1918 #define DCBX_ETS_TLV_RX 0x00000001
1919 #define DCBX_PFC_TLV_RX 0x00000002
1920 #define DCBX_APP_TLV_RX 0x00000004
1921 #define DCBX_ETS_RX_ERROR 0x00000010
1922 #define DCBX_PFC_RX_ERROR 0x00000020
1923 #define DCBX_APP_RX_ERROR 0x00000040
1924 #define DCBX_ETS_REM_WILLING 0x00000100
1925 #define DCBX_PFC_REM_WILLING 0x00000200
1926 #define DCBX_APP_REM_WILLING 0x00000400
1927 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1928 #define DCBX_REMOTE_MIB_VALID 0x00002000
1929 struct dcbx_features features;
1933 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1934 struct lldp_local_mib {
1936 /* Indicates if there is mismatch with negotiation results. */
1938 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1939 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1940 #define DCBX_LOCAL_APP_ERROR 0x00000004
1941 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1942 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1943 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1944 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1945 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1946 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1947 struct dcbx_features features;
1950 /***END OF DCBX STRUCTURES DECLARATIONS***/
1952 /***********************************************************/
1954 /***********************************************************/
1955 #define SHMEM_LINK_CONFIG_SIZE 2
1958 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
1959 #define REQ_DUPLEX_PHY0_SHIFT 0
1960 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
1961 #define REQ_DUPLEX_PHY1_SHIFT 16
1963 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
1964 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
1965 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
1966 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
1967 u32 req_line_speed; /* Also determine AutoNeg */
1968 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
1969 #define REQ_LINE_SPD_PHY0_SHIFT 0
1970 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
1971 #define REQ_LINE_SPD_PHY1_SHIFT 16
1972 u32 speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
1973 u32 additional_config;
1974 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
1975 #define REQ_FC_AUTO_ADV0_SHIFT 0
1976 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
1978 #define LFA_LINK_FLAP_REASON_OFFSET 0
1979 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
1980 #define LFA_LINK_DOWN 0x1
1981 #define LFA_LOOPBACK_ENABLED 0x2
1982 #define LFA_DUPLEX_MISMATCH 0x3
1983 #define LFA_MFW_IS_TOO_OLD 0x4
1984 #define LFA_LINK_SPEED_MISMATCH 0x5
1985 #define LFA_FLOW_CTRL_MISMATCH 0x6
1986 #define LFA_SPEED_CAP_MISMATCH 0x7
1987 #define LFA_DCC_LFA_DISABLED 0x8
1988 #define LFA_EEE_MISMATCH 0x9
1990 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
1991 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
1993 #define LINK_FLAP_COUNT_OFFSET 16
1994 #define LINK_FLAP_COUNT_MASK 0x00ff0000
1996 #define LFA_FLAGS_MASK 0xff000000
1997 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
2000 struct ncsi_oem_fcoe_features {
2002 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
2003 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
2005 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
2006 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
2009 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
2010 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
2012 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
2013 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
2016 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
2017 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
2019 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
2020 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
2023 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
2024 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
2027 struct ncsi_oem_data {
2028 u32 driver_version[4];
2029 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features;
2032 struct shmem2_region {
2034 u32 size; /* 0x0000 */
2036 u32 dcc_support; /* 0x0004 */
2037 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2038 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2039 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2040 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2041 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2042 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2044 u32 ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2046 * For backwards compatibility, if the mf_cfg_addr does not exist
2047 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2048 * end of struct shmem_region
2050 u32 mf_cfg_addr; /* 0x0010 */
2051 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2053 struct fw_flr_mb flr_mb; /* 0x0014 */
2054 u32 dcbx_lldp_params_offset; /* 0x0028 */
2055 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2056 u32 dcbx_neg_res_offset; /* 0x002c */
2057 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2058 u32 dcbx_remote_mib_offset; /* 0x0030 */
2059 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2061 * The other shmemX_base_addr holds the other path's shmem address
2062 * required for example in case of common phy init, or for path1 to know
2063 * the address of mcp debug trace which is located in offset from shmem
2066 u32 other_shmem_base_addr; /* 0x0034 */
2067 u32 other_shmem2_base_addr; /* 0x0038 */
2069 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2070 * which were disabled/flred
2072 u32 mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2075 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2078 u32 drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2080 u32 dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2081 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2084 * edebug_driver_if field is used to transfer messages between edebug
2085 * app to the driver through shmem2.
2088 * bits 0-2 - function number / instance of driver to perform request
2089 * bits 3-5 - op code / is_ack?
2092 u32 edebug_driver_if[2]; /* 0x0068 */
2093 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2094 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2095 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2097 u32 nvm_retain_bitmap_addr; /* 0x0070 */
2099 /* afex support of that driver */
2100 u32 afex_driver_support; /* 0x0074 */
2101 #define SHMEM_AFEX_VERSION_MASK 0x100f
2102 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2103 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2105 /* driver receives addr in scratchpad to which it should respond */
2106 u32 afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2108 /* generic params from MCP to driver (value depends on the msg sent
2111 u32 afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2112 u32 afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2114 u32 swim_base_addr; /* 0x0108 */
2118 /* bitmap notifying which VIF profiles stored in nvram are enabled by
2121 u32 afex_profiles_enabled[2];
2123 /* generic flags controlled by the driver */
2125 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2126 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2127 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2129 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2130 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2131 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2132 /* pointer to extended dev_info shared data copied from nvm image */
2133 u32 extended_dev_info_shared_addr;
2134 u32 ncsi_oem_data_addr;
2136 u32 ocsd_host_addr; /* initialized by option ROM */
2137 u32 ocbb_host_addr; /* initialized by option ROM */
2138 u32 ocsd_req_update_interval; /* initialized by option ROM */
2139 u32 temperature_in_half_celsius;
2140 u32 glob_struct_in_host;
2142 u32 dcbx_neg_res_ext_offset;
2143 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2145 u32 drv_capabilities_flag[E2_FUNC_MAX];
2146 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2147 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2148 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2149 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2151 u32 extended_dev_info_shared_cfg_size;
2153 u32 dcbx_en[PORT_MAX];
2155 /* The offset points to the multi threaded meta structure */
2156 u32 multi_thread_data_offset;
2158 /* address of DMAable host address holding values from the drivers */
2159 u32 drv_info_host_addr_lo;
2160 u32 drv_info_host_addr_hi;
2162 /* general values written by the MFW (such as current version) */
2163 u32 drv_info_control;
2164 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2165 #define DRV_INFO_CONTROL_VER_SHIFT 0
2166 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2167 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2168 u32 ibft_host_addr; /* initialized by option ROM */
2169 struct eee_remote_vals eee_remote_vals[PORT_MAX];
2170 u32 reserved[E2_FUNC_MAX];
2173 /* the status of EEE auto-negotiation
2174 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2175 * bits 19:16 the supported modes for EEE.
2176 * bits 23:20 the speeds advertised for EEE.
2177 * bits 27:24 the speeds the Link partner advertised for EEE.
2178 * The supported/adv. modes in bits 27:19 originate from the
2179 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2180 * bit 28 when 1'b1 EEE was requested.
2181 * bit 29 when 1'b1 tx lpi was requested.
2182 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2184 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2185 * value. When 1'b1 those bits contains a value times 16 microseconds.
2187 u32 eee_status[PORT_MAX];
2188 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2189 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2190 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2191 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2192 #define SHMEM_EEE_100M_ADV (1<<0)
2193 #define SHMEM_EEE_1G_ADV (1<<1)
2194 #define SHMEM_EEE_10G_ADV (1<<2)
2195 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2196 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2197 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2198 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2199 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2200 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2201 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2203 u32 sizeof_port_stats;
2205 /* Link Flap Avoidance */
2206 u32 lfa_host_addr[PORT_MAX];
2209 u32 reserved2; /* Offset 0x148 */
2210 u32 reserved3; /* Offset 0x14C */
2211 u32 reserved4; /* Offset 0x150 */
2212 u32 link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2213 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0)
2218 u32 rx_stat_ifhcinoctets;
2219 u32 rx_stat_ifhcinbadoctets;
2220 u32 rx_stat_etherstatsfragments;
2221 u32 rx_stat_ifhcinucastpkts;
2222 u32 rx_stat_ifhcinmulticastpkts;
2223 u32 rx_stat_ifhcinbroadcastpkts;
2224 u32 rx_stat_dot3statsfcserrors;
2225 u32 rx_stat_dot3statsalignmenterrors;
2226 u32 rx_stat_dot3statscarriersenseerrors;
2227 u32 rx_stat_xonpauseframesreceived;
2228 u32 rx_stat_xoffpauseframesreceived;
2229 u32 rx_stat_maccontrolframesreceived;
2230 u32 rx_stat_xoffstateentered;
2231 u32 rx_stat_dot3statsframestoolong;
2232 u32 rx_stat_etherstatsjabbers;
2233 u32 rx_stat_etherstatsundersizepkts;
2234 u32 rx_stat_etherstatspkts64octets;
2235 u32 rx_stat_etherstatspkts65octetsto127octets;
2236 u32 rx_stat_etherstatspkts128octetsto255octets;
2237 u32 rx_stat_etherstatspkts256octetsto511octets;
2238 u32 rx_stat_etherstatspkts512octetsto1023octets;
2239 u32 rx_stat_etherstatspkts1024octetsto1522octets;
2240 u32 rx_stat_etherstatspktsover1522octets;
2242 u32 rx_stat_falsecarriererrors;
2244 u32 tx_stat_ifhcoutoctets;
2245 u32 tx_stat_ifhcoutbadoctets;
2246 u32 tx_stat_etherstatscollisions;
2247 u32 tx_stat_outxonsent;
2248 u32 tx_stat_outxoffsent;
2249 u32 tx_stat_flowcontroldone;
2250 u32 tx_stat_dot3statssinglecollisionframes;
2251 u32 tx_stat_dot3statsmultiplecollisionframes;
2252 u32 tx_stat_dot3statsdeferredtransmissions;
2253 u32 tx_stat_dot3statsexcessivecollisions;
2254 u32 tx_stat_dot3statslatecollisions;
2255 u32 tx_stat_ifhcoutucastpkts;
2256 u32 tx_stat_ifhcoutmulticastpkts;
2257 u32 tx_stat_ifhcoutbroadcastpkts;
2258 u32 tx_stat_etherstatspkts64octets;
2259 u32 tx_stat_etherstatspkts65octetsto127octets;
2260 u32 tx_stat_etherstatspkts128octetsto255octets;
2261 u32 tx_stat_etherstatspkts256octetsto511octets;
2262 u32 tx_stat_etherstatspkts512octetsto1023octets;
2263 u32 tx_stat_etherstatspkts1024octetsto1522octets;
2264 u32 tx_stat_etherstatspktsover1522octets;
2265 u32 tx_stat_dot3statsinternalmactransmiterrors;
2269 struct bmac1_stats {
2270 u32 tx_stat_gtpkt_lo;
2271 u32 tx_stat_gtpkt_hi;
2272 u32 tx_stat_gtxpf_lo;
2273 u32 tx_stat_gtxpf_hi;
2274 u32 tx_stat_gtfcs_lo;
2275 u32 tx_stat_gtfcs_hi;
2276 u32 tx_stat_gtmca_lo;
2277 u32 tx_stat_gtmca_hi;
2278 u32 tx_stat_gtbca_lo;
2279 u32 tx_stat_gtbca_hi;
2280 u32 tx_stat_gtfrg_lo;
2281 u32 tx_stat_gtfrg_hi;
2282 u32 tx_stat_gtovr_lo;
2283 u32 tx_stat_gtovr_hi;
2284 u32 tx_stat_gt64_lo;
2285 u32 tx_stat_gt64_hi;
2286 u32 tx_stat_gt127_lo;
2287 u32 tx_stat_gt127_hi;
2288 u32 tx_stat_gt255_lo;
2289 u32 tx_stat_gt255_hi;
2290 u32 tx_stat_gt511_lo;
2291 u32 tx_stat_gt511_hi;
2292 u32 tx_stat_gt1023_lo;
2293 u32 tx_stat_gt1023_hi;
2294 u32 tx_stat_gt1518_lo;
2295 u32 tx_stat_gt1518_hi;
2296 u32 tx_stat_gt2047_lo;
2297 u32 tx_stat_gt2047_hi;
2298 u32 tx_stat_gt4095_lo;
2299 u32 tx_stat_gt4095_hi;
2300 u32 tx_stat_gt9216_lo;
2301 u32 tx_stat_gt9216_hi;
2302 u32 tx_stat_gt16383_lo;
2303 u32 tx_stat_gt16383_hi;
2304 u32 tx_stat_gtmax_lo;
2305 u32 tx_stat_gtmax_hi;
2306 u32 tx_stat_gtufl_lo;
2307 u32 tx_stat_gtufl_hi;
2308 u32 tx_stat_gterr_lo;
2309 u32 tx_stat_gterr_hi;
2310 u32 tx_stat_gtbyt_lo;
2311 u32 tx_stat_gtbyt_hi;
2313 u32 rx_stat_gr64_lo;
2314 u32 rx_stat_gr64_hi;
2315 u32 rx_stat_gr127_lo;
2316 u32 rx_stat_gr127_hi;
2317 u32 rx_stat_gr255_lo;
2318 u32 rx_stat_gr255_hi;
2319 u32 rx_stat_gr511_lo;
2320 u32 rx_stat_gr511_hi;
2321 u32 rx_stat_gr1023_lo;
2322 u32 rx_stat_gr1023_hi;
2323 u32 rx_stat_gr1518_lo;
2324 u32 rx_stat_gr1518_hi;
2325 u32 rx_stat_gr2047_lo;
2326 u32 rx_stat_gr2047_hi;
2327 u32 rx_stat_gr4095_lo;
2328 u32 rx_stat_gr4095_hi;
2329 u32 rx_stat_gr9216_lo;
2330 u32 rx_stat_gr9216_hi;
2331 u32 rx_stat_gr16383_lo;
2332 u32 rx_stat_gr16383_hi;
2333 u32 rx_stat_grmax_lo;
2334 u32 rx_stat_grmax_hi;
2335 u32 rx_stat_grpkt_lo;
2336 u32 rx_stat_grpkt_hi;
2337 u32 rx_stat_grfcs_lo;
2338 u32 rx_stat_grfcs_hi;
2339 u32 rx_stat_grmca_lo;
2340 u32 rx_stat_grmca_hi;
2341 u32 rx_stat_grbca_lo;
2342 u32 rx_stat_grbca_hi;
2343 u32 rx_stat_grxcf_lo;
2344 u32 rx_stat_grxcf_hi;
2345 u32 rx_stat_grxpf_lo;
2346 u32 rx_stat_grxpf_hi;
2347 u32 rx_stat_grxuo_lo;
2348 u32 rx_stat_grxuo_hi;
2349 u32 rx_stat_grjbr_lo;
2350 u32 rx_stat_grjbr_hi;
2351 u32 rx_stat_grovr_lo;
2352 u32 rx_stat_grovr_hi;
2353 u32 rx_stat_grflr_lo;
2354 u32 rx_stat_grflr_hi;
2355 u32 rx_stat_grmeg_lo;
2356 u32 rx_stat_grmeg_hi;
2357 u32 rx_stat_grmeb_lo;
2358 u32 rx_stat_grmeb_hi;
2359 u32 rx_stat_grbyt_lo;
2360 u32 rx_stat_grbyt_hi;
2361 u32 rx_stat_grund_lo;
2362 u32 rx_stat_grund_hi;
2363 u32 rx_stat_grfrg_lo;
2364 u32 rx_stat_grfrg_hi;
2365 u32 rx_stat_grerb_lo;
2366 u32 rx_stat_grerb_hi;
2367 u32 rx_stat_grfre_lo;
2368 u32 rx_stat_grfre_hi;
2369 u32 rx_stat_gripj_lo;
2370 u32 rx_stat_gripj_hi;
2373 struct bmac2_stats {
2374 u32 tx_stat_gtpk_lo; /* gtpok */
2375 u32 tx_stat_gtpk_hi; /* gtpok */
2376 u32 tx_stat_gtxpf_lo; /* gtpf */
2377 u32 tx_stat_gtxpf_hi; /* gtpf */
2378 u32 tx_stat_gtpp_lo; /* NEW BMAC2 */
2379 u32 tx_stat_gtpp_hi; /* NEW BMAC2 */
2380 u32 tx_stat_gtfcs_lo;
2381 u32 tx_stat_gtfcs_hi;
2382 u32 tx_stat_gtuca_lo; /* NEW BMAC2 */
2383 u32 tx_stat_gtuca_hi; /* NEW BMAC2 */
2384 u32 tx_stat_gtmca_lo;
2385 u32 tx_stat_gtmca_hi;
2386 u32 tx_stat_gtbca_lo;
2387 u32 tx_stat_gtbca_hi;
2388 u32 tx_stat_gtovr_lo;
2389 u32 tx_stat_gtovr_hi;
2390 u32 tx_stat_gtfrg_lo;
2391 u32 tx_stat_gtfrg_hi;
2392 u32 tx_stat_gtpkt1_lo; /* gtpkt */
2393 u32 tx_stat_gtpkt1_hi; /* gtpkt */
2394 u32 tx_stat_gt64_lo;
2395 u32 tx_stat_gt64_hi;
2396 u32 tx_stat_gt127_lo;
2397 u32 tx_stat_gt127_hi;
2398 u32 tx_stat_gt255_lo;
2399 u32 tx_stat_gt255_hi;
2400 u32 tx_stat_gt511_lo;
2401 u32 tx_stat_gt511_hi;
2402 u32 tx_stat_gt1023_lo;
2403 u32 tx_stat_gt1023_hi;
2404 u32 tx_stat_gt1518_lo;
2405 u32 tx_stat_gt1518_hi;
2406 u32 tx_stat_gt2047_lo;
2407 u32 tx_stat_gt2047_hi;
2408 u32 tx_stat_gt4095_lo;
2409 u32 tx_stat_gt4095_hi;
2410 u32 tx_stat_gt9216_lo;
2411 u32 tx_stat_gt9216_hi;
2412 u32 tx_stat_gt16383_lo;
2413 u32 tx_stat_gt16383_hi;
2414 u32 tx_stat_gtmax_lo;
2415 u32 tx_stat_gtmax_hi;
2416 u32 tx_stat_gtufl_lo;
2417 u32 tx_stat_gtufl_hi;
2418 u32 tx_stat_gterr_lo;
2419 u32 tx_stat_gterr_hi;
2420 u32 tx_stat_gtbyt_lo;
2421 u32 tx_stat_gtbyt_hi;
2423 u32 rx_stat_gr64_lo;
2424 u32 rx_stat_gr64_hi;
2425 u32 rx_stat_gr127_lo;
2426 u32 rx_stat_gr127_hi;
2427 u32 rx_stat_gr255_lo;
2428 u32 rx_stat_gr255_hi;
2429 u32 rx_stat_gr511_lo;
2430 u32 rx_stat_gr511_hi;
2431 u32 rx_stat_gr1023_lo;
2432 u32 rx_stat_gr1023_hi;
2433 u32 rx_stat_gr1518_lo;
2434 u32 rx_stat_gr1518_hi;
2435 u32 rx_stat_gr2047_lo;
2436 u32 rx_stat_gr2047_hi;
2437 u32 rx_stat_gr4095_lo;
2438 u32 rx_stat_gr4095_hi;
2439 u32 rx_stat_gr9216_lo;
2440 u32 rx_stat_gr9216_hi;
2441 u32 rx_stat_gr16383_lo;
2442 u32 rx_stat_gr16383_hi;
2443 u32 rx_stat_grmax_lo;
2444 u32 rx_stat_grmax_hi;
2445 u32 rx_stat_grpkt_lo;
2446 u32 rx_stat_grpkt_hi;
2447 u32 rx_stat_grfcs_lo;
2448 u32 rx_stat_grfcs_hi;
2449 u32 rx_stat_gruca_lo;
2450 u32 rx_stat_gruca_hi;
2451 u32 rx_stat_grmca_lo;
2452 u32 rx_stat_grmca_hi;
2453 u32 rx_stat_grbca_lo;
2454 u32 rx_stat_grbca_hi;
2455 u32 rx_stat_grxpf_lo; /* grpf */
2456 u32 rx_stat_grxpf_hi; /* grpf */
2457 u32 rx_stat_grpp_lo;
2458 u32 rx_stat_grpp_hi;
2459 u32 rx_stat_grxuo_lo; /* gruo */
2460 u32 rx_stat_grxuo_hi; /* gruo */
2461 u32 rx_stat_grjbr_lo;
2462 u32 rx_stat_grjbr_hi;
2463 u32 rx_stat_grovr_lo;
2464 u32 rx_stat_grovr_hi;
2465 u32 rx_stat_grxcf_lo; /* grcf */
2466 u32 rx_stat_grxcf_hi; /* grcf */
2467 u32 rx_stat_grflr_lo;
2468 u32 rx_stat_grflr_hi;
2469 u32 rx_stat_grpok_lo;
2470 u32 rx_stat_grpok_hi;
2471 u32 rx_stat_grmeg_lo;
2472 u32 rx_stat_grmeg_hi;
2473 u32 rx_stat_grmeb_lo;
2474 u32 rx_stat_grmeb_hi;
2475 u32 rx_stat_grbyt_lo;
2476 u32 rx_stat_grbyt_hi;
2477 u32 rx_stat_grund_lo;
2478 u32 rx_stat_grund_hi;
2479 u32 rx_stat_grfrg_lo;
2480 u32 rx_stat_grfrg_hi;
2481 u32 rx_stat_grerb_lo; /* grerrbyt */
2482 u32 rx_stat_grerb_hi; /* grerrbyt */
2483 u32 rx_stat_grfre_lo; /* grfrerr */
2484 u32 rx_stat_grfre_hi; /* grfrerr */
2485 u32 rx_stat_gripj_lo;
2486 u32 rx_stat_gripj_hi;
2489 struct mstat_stats {
2491 /* OTE MSTAT on E3 has a bug where this register's contents are
2492 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2536 u32 tx_collisions_lo;
2537 u32 tx_collisions_hi;
2538 u32 tx_singlecollision_lo;
2539 u32 tx_singlecollision_hi;
2540 u32 tx_multiplecollisions_lo;
2541 u32 tx_multiplecollisions_hi;
2544 u32 tx_excessivecollisions_lo;
2545 u32 tx_excessivecollisions_hi;
2546 u32 tx_latecollisions_lo;
2547 u32 tx_latecollisions_hi;
2606 u32 rx_alignmenterrors_lo;
2607 u32 rx_alignmenterrors_hi;
2608 u32 rx_falsecarrier_lo;
2609 u32 rx_falsecarrier_hi;
2610 u32 rx_llfcmsgcnt_lo;
2611 u32 rx_llfcmsgcnt_hi;
2616 struct emac_stats emac_stats;
2617 struct bmac1_stats bmac1_stats;
2618 struct bmac2_stats bmac2_stats;
2619 struct mstat_stats mstat_stats;
2625 u32 rx_stat_ifhcinbadoctets_hi;
2626 u32 rx_stat_ifhcinbadoctets_lo;
2628 /* out_bad_octets */
2629 u32 tx_stat_ifhcoutbadoctets_hi;
2630 u32 tx_stat_ifhcoutbadoctets_lo;
2632 /* crc_receive_errors */
2633 u32 rx_stat_dot3statsfcserrors_hi;
2634 u32 rx_stat_dot3statsfcserrors_lo;
2635 /* alignment_errors */
2636 u32 rx_stat_dot3statsalignmenterrors_hi;
2637 u32 rx_stat_dot3statsalignmenterrors_lo;
2638 /* carrier_sense_errors */
2639 u32 rx_stat_dot3statscarriersenseerrors_hi;
2640 u32 rx_stat_dot3statscarriersenseerrors_lo;
2641 /* false_carrier_detections */
2642 u32 rx_stat_falsecarriererrors_hi;
2643 u32 rx_stat_falsecarriererrors_lo;
2645 /* runt_packets_received */
2646 u32 rx_stat_etherstatsundersizepkts_hi;
2647 u32 rx_stat_etherstatsundersizepkts_lo;
2648 /* jabber_packets_received */
2649 u32 rx_stat_dot3statsframestoolong_hi;
2650 u32 rx_stat_dot3statsframestoolong_lo;
2652 /* error_runt_packets_received */
2653 u32 rx_stat_etherstatsfragments_hi;
2654 u32 rx_stat_etherstatsfragments_lo;
2655 /* error_jabber_packets_received */
2656 u32 rx_stat_etherstatsjabbers_hi;
2657 u32 rx_stat_etherstatsjabbers_lo;
2659 /* control_frames_received */
2660 u32 rx_stat_maccontrolframesreceived_hi;
2661 u32 rx_stat_maccontrolframesreceived_lo;
2662 u32 rx_stat_mac_xpf_hi;
2663 u32 rx_stat_mac_xpf_lo;
2664 u32 rx_stat_mac_xcf_hi;
2665 u32 rx_stat_mac_xcf_lo;
2667 /* xoff_state_entered */
2668 u32 rx_stat_xoffstateentered_hi;
2669 u32 rx_stat_xoffstateentered_lo;
2670 /* pause_xon_frames_received */
2671 u32 rx_stat_xonpauseframesreceived_hi;
2672 u32 rx_stat_xonpauseframesreceived_lo;
2673 /* pause_xoff_frames_received */
2674 u32 rx_stat_xoffpauseframesreceived_hi;
2675 u32 rx_stat_xoffpauseframesreceived_lo;
2676 /* pause_xon_frames_transmitted */
2677 u32 tx_stat_outxonsent_hi;
2678 u32 tx_stat_outxonsent_lo;
2679 /* pause_xoff_frames_transmitted */
2680 u32 tx_stat_outxoffsent_hi;
2681 u32 tx_stat_outxoffsent_lo;
2682 /* flow_control_done */
2683 u32 tx_stat_flowcontroldone_hi;
2684 u32 tx_stat_flowcontroldone_lo;
2686 /* ether_stats_collisions */
2687 u32 tx_stat_etherstatscollisions_hi;
2688 u32 tx_stat_etherstatscollisions_lo;
2689 /* single_collision_transmit_frames */
2690 u32 tx_stat_dot3statssinglecollisionframes_hi;
2691 u32 tx_stat_dot3statssinglecollisionframes_lo;
2692 /* multiple_collision_transmit_frames */
2693 u32 tx_stat_dot3statsmultiplecollisionframes_hi;
2694 u32 tx_stat_dot3statsmultiplecollisionframes_lo;
2695 /* deferred_transmissions */
2696 u32 tx_stat_dot3statsdeferredtransmissions_hi;
2697 u32 tx_stat_dot3statsdeferredtransmissions_lo;
2698 /* excessive_collision_frames */
2699 u32 tx_stat_dot3statsexcessivecollisions_hi;
2700 u32 tx_stat_dot3statsexcessivecollisions_lo;
2701 /* late_collision_frames */
2702 u32 tx_stat_dot3statslatecollisions_hi;
2703 u32 tx_stat_dot3statslatecollisions_lo;
2705 /* frames_transmitted_64_bytes */
2706 u32 tx_stat_etherstatspkts64octets_hi;
2707 u32 tx_stat_etherstatspkts64octets_lo;
2708 /* frames_transmitted_65_127_bytes */
2709 u32 tx_stat_etherstatspkts65octetsto127octets_hi;
2710 u32 tx_stat_etherstatspkts65octetsto127octets_lo;
2711 /* frames_transmitted_128_255_bytes */
2712 u32 tx_stat_etherstatspkts128octetsto255octets_hi;
2713 u32 tx_stat_etherstatspkts128octetsto255octets_lo;
2714 /* frames_transmitted_256_511_bytes */
2715 u32 tx_stat_etherstatspkts256octetsto511octets_hi;
2716 u32 tx_stat_etherstatspkts256octetsto511octets_lo;
2717 /* frames_transmitted_512_1023_bytes */
2718 u32 tx_stat_etherstatspkts512octetsto1023octets_hi;
2719 u32 tx_stat_etherstatspkts512octetsto1023octets_lo;
2720 /* frames_transmitted_1024_1522_bytes */
2721 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi;
2722 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo;
2723 /* frames_transmitted_1523_9022_bytes */
2724 u32 tx_stat_etherstatspktsover1522octets_hi;
2725 u32 tx_stat_etherstatspktsover1522octets_lo;
2726 u32 tx_stat_mac_2047_hi;
2727 u32 tx_stat_mac_2047_lo;
2728 u32 tx_stat_mac_4095_hi;
2729 u32 tx_stat_mac_4095_lo;
2730 u32 tx_stat_mac_9216_hi;
2731 u32 tx_stat_mac_9216_lo;
2732 u32 tx_stat_mac_16383_hi;
2733 u32 tx_stat_mac_16383_lo;
2735 /* internal_mac_transmit_errors */
2736 u32 tx_stat_dot3statsinternalmactransmiterrors_hi;
2737 u32 tx_stat_dot3statsinternalmactransmiterrors_lo;
2739 /* if_out_discards */
2740 u32 tx_stat_mac_ufl_hi;
2741 u32 tx_stat_mac_ufl_lo;
2745 #define MAC_STX_IDX_MAX 2
2747 struct host_port_stats {
2748 u32 host_port_stats_counter;
2750 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
2755 u32 not_used; /* obsolete */
2756 u32 pfc_frames_tx_hi;
2757 u32 pfc_frames_tx_lo;
2758 u32 pfc_frames_rx_hi;
2759 u32 pfc_frames_rx_lo;
2761 u32 eee_lpi_count_hi;
2762 u32 eee_lpi_count_lo;
2766 struct host_func_stats {
2767 u32 host_func_stats_start;
2769 u32 total_bytes_received_hi;
2770 u32 total_bytes_received_lo;
2772 u32 total_bytes_transmitted_hi;
2773 u32 total_bytes_transmitted_lo;
2775 u32 total_unicast_packets_received_hi;
2776 u32 total_unicast_packets_received_lo;
2778 u32 total_multicast_packets_received_hi;
2779 u32 total_multicast_packets_received_lo;
2781 u32 total_broadcast_packets_received_hi;
2782 u32 total_broadcast_packets_received_lo;
2784 u32 total_unicast_packets_transmitted_hi;
2785 u32 total_unicast_packets_transmitted_lo;
2787 u32 total_multicast_packets_transmitted_hi;
2788 u32 total_multicast_packets_transmitted_lo;
2790 u32 total_broadcast_packets_transmitted_hi;
2791 u32 total_broadcast_packets_transmitted_lo;
2793 u32 valid_bytes_received_hi;
2794 u32 valid_bytes_received_lo;
2796 u32 host_func_stats_end;
2799 /* VIC definitions */
2800 #define VICSTATST_UIF_INDEX 2
2803 /* stats collected for afex.
2804 * NOTE: structure is exactly as expected to be received by the switch.
2805 * order must remain exactly as is unless protocol changes !
2808 u32 tx_unicast_frames_hi;
2809 u32 tx_unicast_frames_lo;
2810 u32 tx_unicast_bytes_hi;
2811 u32 tx_unicast_bytes_lo;
2812 u32 tx_multicast_frames_hi;
2813 u32 tx_multicast_frames_lo;
2814 u32 tx_multicast_bytes_hi;
2815 u32 tx_multicast_bytes_lo;
2816 u32 tx_broadcast_frames_hi;
2817 u32 tx_broadcast_frames_lo;
2818 u32 tx_broadcast_bytes_hi;
2819 u32 tx_broadcast_bytes_lo;
2820 u32 tx_frames_discarded_hi;
2821 u32 tx_frames_discarded_lo;
2822 u32 tx_frames_dropped_hi;
2823 u32 tx_frames_dropped_lo;
2825 u32 rx_unicast_frames_hi;
2826 u32 rx_unicast_frames_lo;
2827 u32 rx_unicast_bytes_hi;
2828 u32 rx_unicast_bytes_lo;
2829 u32 rx_multicast_frames_hi;
2830 u32 rx_multicast_frames_lo;
2831 u32 rx_multicast_bytes_hi;
2832 u32 rx_multicast_bytes_lo;
2833 u32 rx_broadcast_frames_hi;
2834 u32 rx_broadcast_frames_lo;
2835 u32 rx_broadcast_bytes_hi;
2836 u32 rx_broadcast_bytes_lo;
2837 u32 rx_frames_discarded_hi;
2838 u32 rx_frames_discarded_lo;
2839 u32 rx_frames_dropped_hi;
2840 u32 rx_frames_dropped_lo;
2843 #define BCM_5710_FW_MAJOR_VERSION 7
2844 #define BCM_5710_FW_MINOR_VERSION 8
2845 #define BCM_5710_FW_REVISION_VERSION 17
2846 #define BCM_5710_FW_ENGINEERING_VERSION 0
2847 #define BCM_5710_FW_COMPILE_FLAGS 1
2853 struct atten_sp_status_block {
2855 __le32 attn_bits_ack;
2858 __le16 attn_bits_index;
2864 * The eth aggregative context of Cstorm
2866 struct cstorm_eth_ag_context {
2867 u32 __reserved0[10];
2872 * dmae command structure
2874 struct dmae_command {
2876 #define DMAE_COMMAND_SRC (0x1<<0)
2877 #define DMAE_COMMAND_SRC_SHIFT 0
2878 #define DMAE_COMMAND_DST (0x3<<1)
2879 #define DMAE_COMMAND_DST_SHIFT 1
2880 #define DMAE_COMMAND_C_DST (0x1<<3)
2881 #define DMAE_COMMAND_C_DST_SHIFT 3
2882 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2883 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2884 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2885 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2886 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2887 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2888 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2889 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2890 #define DMAE_COMMAND_PORT (0x1<<11)
2891 #define DMAE_COMMAND_PORT_SHIFT 11
2892 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2893 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2894 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2895 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2896 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2897 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2898 #define DMAE_COMMAND_E1HVN (0x3<<15)
2899 #define DMAE_COMMAND_E1HVN_SHIFT 15
2900 #define DMAE_COMMAND_DST_VN (0x3<<17)
2901 #define DMAE_COMMAND_DST_VN_SHIFT 17
2902 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2903 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2904 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2905 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2906 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2907 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2912 #if defined(__BIG_ENDIAN)
2914 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2915 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2916 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2917 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2918 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2919 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2920 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2921 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2922 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2923 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2924 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2925 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2927 #elif defined(__LITTLE_ENDIAN)
2930 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2931 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2932 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2933 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2934 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2935 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2936 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2937 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2938 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2939 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2940 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2941 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2948 #if defined(__BIG_ENDIAN)
2951 #elif defined(__LITTLE_ENDIAN)
2955 #if defined(__BIG_ENDIAN)
2958 #elif defined(__LITTLE_ENDIAN)
2962 #if defined(__BIG_ENDIAN)
2965 #elif defined(__LITTLE_ENDIAN)
2973 * common data for all protocols
2975 struct doorbell_hdr {
2977 #define DOORBELL_HDR_RX (0x1<<0)
2978 #define DOORBELL_HDR_RX_SHIFT 0
2979 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2980 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2981 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2982 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2983 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2984 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2990 struct eth_tx_doorbell {
2991 #if defined(__BIG_ENDIAN)
2994 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2995 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2996 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2997 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2998 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2999 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3000 struct doorbell_hdr hdr;
3001 #elif defined(__LITTLE_ENDIAN)
3002 struct doorbell_hdr hdr;
3004 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
3005 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3006 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
3007 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3008 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
3009 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3016 * 3 lines. status block
3018 struct hc_status_block_e1x {
3019 __le16 index_values[HC_SB_MAX_INDICES_E1X];
3020 __le16 running_index[HC_SB_MAX_SM];
3027 struct host_hc_status_block_e1x {
3028 struct hc_status_block_e1x sb;
3033 * 3 lines. status block
3035 struct hc_status_block_e2 {
3036 __le16 index_values[HC_SB_MAX_INDICES_E2];
3037 __le16 running_index[HC_SB_MAX_SM];
3038 __le32 reserved[11];
3044 struct host_hc_status_block_e2 {
3045 struct hc_status_block_e2 sb;
3050 * 5 lines. slow-path status block
3052 struct hc_sp_status_block {
3053 __le16 index_values[HC_SP_SB_MAX_INDICES];
3054 __le16 running_index;
3062 struct host_sp_status_block {
3063 struct atten_sp_status_block atten_status_block;
3064 struct hc_sp_status_block sp_sb;
3069 * IGU driver acknowledgment register
3071 struct igu_ack_register {
3072 #if defined(__BIG_ENDIAN)
3073 u16 sb_id_and_flags;
3074 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3075 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3076 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3077 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3078 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3079 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3080 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3081 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3082 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3083 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3084 u16 status_block_index;
3085 #elif defined(__LITTLE_ENDIAN)
3086 u16 status_block_index;
3087 u16 sb_id_and_flags;
3088 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
3089 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3090 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
3091 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3092 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
3093 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3094 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
3095 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3096 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
3097 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3103 * IGU driver acknowledgement register
3105 struct igu_backward_compatible {
3106 u32 sb_id_and_flags;
3107 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
3108 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3109 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
3110 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3111 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
3112 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3113 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
3114 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3115 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
3116 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3117 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
3118 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3124 * IGU driver acknowledgement register
3126 struct igu_regular {
3127 u32 sb_id_and_flags;
3128 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
3129 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3130 #define IGU_REGULAR_RESERVED0 (0x1<<20)
3131 #define IGU_REGULAR_RESERVED0_SHIFT 20
3132 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
3133 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
3134 #define IGU_REGULAR_BUPDATE (0x1<<24)
3135 #define IGU_REGULAR_BUPDATE_SHIFT 24
3136 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
3137 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
3138 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
3139 #define IGU_REGULAR_RESERVED_1_SHIFT 27
3140 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
3141 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
3142 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
3143 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
3144 #define IGU_REGULAR_BCLEANUP (0x1<<31)
3145 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3150 * IGU driver acknowledgement register
3152 union igu_consprod_reg {
3153 struct igu_regular regular;
3154 struct igu_backward_compatible backward_compatible;
3159 * Igu control commands
3162 IGU_CTRL_CMD_TYPE_RD,
3163 IGU_CTRL_CMD_TYPE_WR,
3169 * Control register for the IGU command register
3171 struct igu_ctrl_reg {
3173 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3174 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3175 #define IGU_CTRL_REG_FID (0x7F<<12)
3176 #define IGU_CTRL_REG_FID_SHIFT 12
3177 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3178 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3179 #define IGU_CTRL_REG_TYPE (0x1<<20)
3180 #define IGU_CTRL_REG_TYPE_SHIFT 20
3181 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3182 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3187 * Igu interrupt command
3201 enum igu_seg_access {
3202 IGU_SEG_ACCESS_NORM,
3204 IGU_SEG_ACCESS_ATTN,
3210 * Parser parsing flags field
3212 struct parsing_flags {
3214 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3215 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3216 #define PARSING_FLAGS_VLAN (0x1<<1)
3217 #define PARSING_FLAGS_VLAN_SHIFT 1
3218 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3219 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3220 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3221 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3222 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3223 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3224 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3225 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3226 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3227 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3228 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3229 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3230 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3231 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3232 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3233 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3234 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3235 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3236 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3237 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3238 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3239 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3244 * Parsing flags for TCP ACK type
3246 enum prs_flags_ack_type {
3247 PRS_FLAG_PUREACK_PIGGY,
3248 PRS_FLAG_PUREACK_PURE,
3249 MAX_PRS_FLAGS_ACK_TYPE
3254 * Parsing flags for Ethernet address type
3256 enum prs_flags_eth_addr_type {
3257 PRS_FLAG_ETHTYPE_NON_UNICAST,
3258 PRS_FLAG_ETHTYPE_UNICAST,
3259 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3264 * Parsing flags for over-ethernet protocol
3266 enum prs_flags_over_eth {
3267 PRS_FLAG_OVERETH_UNKNOWN,
3268 PRS_FLAG_OVERETH_IPV4,
3269 PRS_FLAG_OVERETH_IPV6,
3270 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
3271 MAX_PRS_FLAGS_OVER_ETH
3276 * Parsing flags for over-IP protocol
3278 enum prs_flags_over_ip {
3279 PRS_FLAG_OVERIP_UNKNOWN,
3280 PRS_FLAG_OVERIP_TCP,
3281 PRS_FLAG_OVERIP_UDP,
3282 MAX_PRS_FLAGS_OVER_IP
3287 * SDM operation gen command (generate aggregative interrupt)
3291 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3292 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3293 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3294 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3295 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3296 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3297 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3298 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3299 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3300 #define SDM_OP_GEN_RESERVED_SHIFT 17
3305 * Timers connection context
3307 struct timers_block_context {
3312 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3313 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3314 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3315 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3316 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3317 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3322 * The eth aggregative context of Tstorm
3324 struct tstorm_eth_ag_context {
3325 u32 __reserved0[14];
3330 * The eth aggregative context of Ustorm
3332 struct ustorm_eth_ag_context {
3334 #if defined(__BIG_ENDIAN)
3338 #elif defined(__LITTLE_ENDIAN)
3348 * The eth aggregative context of Xstorm
3350 struct xstorm_eth_ag_context {
3352 #if defined(__BIG_ENDIAN)
3356 #elif defined(__LITTLE_ENDIAN)
3366 * doorbell message sent to the chip
3369 #if defined(__BIG_ENDIAN)
3372 struct doorbell_hdr header;
3373 #elif defined(__LITTLE_ENDIAN)
3374 struct doorbell_hdr header;
3382 * doorbell message sent to the chip
3384 struct doorbell_set_prod {
3385 #if defined(__BIG_ENDIAN)
3388 struct doorbell_hdr header;
3389 #elif defined(__LITTLE_ENDIAN)
3390 struct doorbell_hdr header;
3402 struct regpair_native {
3408 * Classify rule opcodes in E2/E3
3410 enum classify_rule {
3411 CLASSIFY_RULE_OPCODE_MAC,
3412 CLASSIFY_RULE_OPCODE_VLAN,
3413 CLASSIFY_RULE_OPCODE_PAIR,
3419 * Classify rule types in E2/E3
3421 enum classify_rule_action_type {
3422 CLASSIFY_RULE_REMOVE,
3424 MAX_CLASSIFY_RULE_ACTION_TYPE
3429 * client init ramrod data
3431 struct client_init_general_data {
3433 u8 statistics_counter_id;
3434 u8 statistics_en_flg;
3439 u8 statistics_zero_flg;
3448 * client init rx data
3450 struct client_init_rx_data {
3452 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3453 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3454 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3455 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3456 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3457 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3458 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3459 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3460 u8 vmqueue_mode_en_flg;
3461 u8 extra_data_over_sgl_en_flg;
3462 u8 cache_line_alignment_log_size;
3463 u8 enable_dynamic_hc;
3464 u8 max_sges_for_packet;
3466 u8 drop_ip_cs_err_flg;
3467 u8 drop_tcp_cs_err_flg;
3469 u8 drop_udp_cs_err_flg;
3470 u8 inner_vlan_removal_enable_flg;
3471 u8 outer_vlan_removal_enable_flg;
3473 u8 rx_sb_index_number;
3474 u8 dont_verify_rings_pause_thr_flg;
3476 u8 silent_vlan_removal_flg;
3477 __le16 max_bytes_on_bd;
3478 __le16 sge_buff_size;
3479 u8 approx_mcast_engine_id;
3481 struct regpair bd_page_base;
3482 struct regpair sge_page_base;
3483 struct regpair cqe_page_base;
3486 __le16 max_agg_size;
3488 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3489 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3490 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3491 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3492 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3493 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3494 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3495 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3496 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3497 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3498 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3499 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3500 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3501 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3502 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3503 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3504 __le16 cqe_pause_thr_low;
3505 __le16 cqe_pause_thr_high;
3506 __le16 bd_pause_thr_low;
3507 __le16 bd_pause_thr_high;
3508 __le16 sge_pause_thr_low;
3509 __le16 sge_pause_thr_high;
3511 __le16 silent_vlan_value;
3512 __le16 silent_vlan_mask;
3513 __le32 reserved6[2];
3517 * client init tx data
3519 struct client_init_tx_data {
3520 u8 enforce_security_flg;
3521 u8 tx_status_block_id;
3522 u8 tx_sb_index_number;
3523 u8 tss_leading_client_id;
3524 u8 tx_switching_flg;
3525 u8 anti_spoofing_flg;
3526 __le16 default_vlan;
3527 struct regpair tx_bd_page_base;
3529 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3530 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3531 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3532 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3533 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3534 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3535 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3536 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3537 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4)
3538 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
3539 u8 default_vlan_flg;
3540 u8 force_default_pri_flg;
3541 u8 tunnel_lso_inc_ip_id;
3542 u8 refuse_outband_vlan_flg;
3543 u8 tunnel_non_lso_pcsum_location;
3548 * client init ramrod data
3550 struct client_init_ramrod_data {
3551 struct client_init_general_data general;
3552 struct client_init_rx_data rx;
3553 struct client_init_tx_data tx;
3558 * client update ramrod data
3560 struct client_update_ramrod_data {
3563 u8 inner_vlan_removal_enable_flg;
3564 u8 inner_vlan_removal_change_flg;
3565 u8 outer_vlan_removal_enable_flg;
3566 u8 outer_vlan_removal_change_flg;
3567 u8 anti_spoofing_enable_flg;
3568 u8 anti_spoofing_change_flg;
3570 u8 activate_change_flg;
3571 __le16 default_vlan;
3572 u8 default_vlan_enable_flg;
3573 u8 default_vlan_change_flg;
3574 __le16 silent_vlan_value;
3575 __le16 silent_vlan_mask;
3576 u8 silent_vlan_removal_flg;
3577 u8 silent_vlan_change_flg;
3578 u8 refuse_outband_vlan_flg;
3579 u8 refuse_outband_vlan_change_flg;
3580 u8 tx_switching_flg;
3581 u8 tx_switching_change_flg;
3588 * The eth storm context of Cstorm
3590 struct cstorm_eth_st_context {
3595 struct double_regpair {
3604 * Ethernet address typesm used in ethernet tx BDs
3606 enum eth_addr_type {
3618 struct eth_classify_cmd_header {
3619 u8 cmd_general_data;
3620 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3621 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3622 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3623 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3624 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3625 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3626 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3627 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3628 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3629 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3637 * header for eth classification config ramrod
3639 struct eth_classify_header {
3648 * Command for adding/removing a MAC classification rule
3650 struct eth_classify_mac_cmd {
3651 struct eth_classify_cmd_header header;
3662 * Command for adding/removing a MAC-VLAN pair classification rule
3664 struct eth_classify_pair_cmd {
3665 struct eth_classify_cmd_header header;
3676 * Command for adding/removing a VLAN classification rule
3678 struct eth_classify_vlan_cmd {
3679 struct eth_classify_cmd_header header;
3687 * union for eth classification rule
3689 union eth_classify_rule_cmd {
3690 struct eth_classify_mac_cmd mac;
3691 struct eth_classify_vlan_cmd vlan;
3692 struct eth_classify_pair_cmd pair;
3696 * parameters for eth classification configuration ramrod
3698 struct eth_classify_rules_ramrod_data {
3699 struct eth_classify_header header;
3700 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3705 * The data contain client ID need to the ramrod
3707 struct eth_common_ramrod_data {
3714 * The eth storm context of Ustorm
3716 struct ustorm_eth_st_context {
3721 * The eth storm context of Tstorm
3723 struct tstorm_eth_st_context {
3724 u32 __reserved0[28];
3728 * The eth storm context of Xstorm
3730 struct xstorm_eth_st_context {
3735 * Ethernet connection context
3737 struct eth_context {
3738 struct ustorm_eth_st_context ustorm_st_context;
3739 struct tstorm_eth_st_context tstorm_st_context;
3740 struct xstorm_eth_ag_context xstorm_ag_context;
3741 struct tstorm_eth_ag_context tstorm_ag_context;
3742 struct cstorm_eth_ag_context cstorm_ag_context;
3743 struct ustorm_eth_ag_context ustorm_ag_context;
3744 struct timers_block_context timers_context;
3745 struct xstorm_eth_st_context xstorm_st_context;
3746 struct cstorm_eth_st_context cstorm_st_context;
3751 * union for sgl and raw data.
3753 union eth_sgl_or_raw_data {
3759 * eth FP end aggregation CQE parameters struct
3761 struct eth_end_agg_rx_cqe {
3762 u8 type_error_flags;
3763 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3764 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3765 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3766 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3767 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3768 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3772 __le32 timestamp_delta;
3773 __le16 num_of_coalesced_segs;
3778 union eth_sgl_or_raw_data sgl_or_raw_data;
3779 __le32 reserved5[8];
3784 * regular eth FP CQE parameters struct
3786 struct eth_fast_path_rx_cqe {
3787 u8 type_error_flags;
3788 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3789 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3790 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3791 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3792 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3793 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3794 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3795 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3796 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3797 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3798 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3799 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3801 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3802 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3803 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3804 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3805 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3806 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3807 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3808 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3809 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3810 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3811 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3812 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3814 u8 placement_offset;
3815 __le32 rss_hash_result;
3817 __le16 pkt_len_or_gro_seg_len;
3819 struct parsing_flags pars_flags;
3820 union eth_sgl_or_raw_data sgl_or_raw_data;
3821 __le32 reserved1[7];
3827 * Command for setting classification flags for a client
3829 struct eth_filter_rules_cmd {
3830 u8 cmd_general_data;
3831 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3832 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3833 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3834 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3835 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3836 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3841 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3842 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3843 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3844 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3845 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3846 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3847 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3848 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3849 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3850 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3851 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3852 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3853 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3854 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3855 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3856 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3858 struct regpair reserved4;
3863 * parameters for eth classification filters ramrod
3865 struct eth_filter_rules_ramrod_data {
3866 struct eth_classify_header header;
3867 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
3872 * parameters for eth classification configuration ramrod
3874 struct eth_general_rules_ramrod_data {
3875 struct eth_classify_header header;
3876 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
3881 * The data for Halt ramrod
3883 struct eth_halt_ramrod_data {
3890 * destination and source mac address.
3892 struct eth_mac_addresses {
3893 #if defined(__BIG_ENDIAN)
3896 #elif defined(__LITTLE_ENDIAN)
3900 #if defined(__BIG_ENDIAN)
3903 #elif defined(__LITTLE_ENDIAN)
3907 #if defined(__BIG_ENDIAN)
3910 #elif defined(__LITTLE_ENDIAN)
3916 /* tunneling related data */
3917 struct eth_tunnel_data {
3918 #if defined(__BIG_ENDIAN)
3921 #elif defined(__LITTLE_ENDIAN)
3925 #if defined(__BIG_ENDIAN)
3928 #elif defined(__LITTLE_ENDIAN)
3932 #if defined(__BIG_ENDIAN)
3934 u8 ip_hdr_start_inner_w;
3936 #elif defined(__LITTLE_ENDIAN)
3938 u8 ip_hdr_start_inner_w;
3943 /* union for mac addresses and for tunneling data.
3944 * considered as tunneling data only if (tunnel_exist == 1).
3946 union eth_mac_addr_or_tunnel_data {
3947 struct eth_mac_addresses mac_addr;
3948 struct eth_tunnel_data tunnel_data;
3951 /*Command for setting multicast classification for a client */
3952 struct eth_multicast_rules_cmd {
3953 u8 cmd_general_data;
3954 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3955 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3956 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3957 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3958 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3959 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3960 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3961 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3966 struct regpair reserved3;
3970 * parameters for multicast classification ramrod
3972 struct eth_multicast_rules_ramrod_data {
3973 struct eth_classify_header header;
3974 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
3978 * Place holder for ramrods protocol specific data
3980 struct ramrod_data {
3986 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3988 union eth_ramrod_data {
3989 struct ramrod_data general;
3994 * RSS toeplitz hash type, as reported in CQE
3996 enum eth_rss_hash_type {
4003 E1HOV_PRI_HASH_TYPE,
4005 MAX_ETH_RSS_HASH_TYPE
4013 ETH_RSS_MODE_DISABLED,
4014 ETH_RSS_MODE_REGULAR,
4015 ETH_RSS_MODE_VLAN_PRI,
4016 ETH_RSS_MODE_E1HOV_PRI,
4017 ETH_RSS_MODE_IP_DSCP,
4023 * parameters for RSS update ramrod (E2)
4025 struct eth_rss_update_ramrod_data {
4028 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
4029 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
4030 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
4031 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
4032 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
4033 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
4034 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
4035 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
4036 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
4037 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
4038 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
4039 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
4040 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6)
4041 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
4042 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
4043 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
4046 __le16 udp_4tuple_dst_port_mask;
4047 __le16 udp_4tuple_dst_port_value;
4048 u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
4049 __le32 rss_key[T_ETH_RSS_KEY];
4056 * The eth Rx Buffer Descriptor
4065 * Eth Rx Cqe structure- general structure for ramrods
4067 struct common_ramrod_eth_rx_cqe {
4069 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
4070 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
4071 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
4072 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
4073 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
4074 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
4077 __le32 conn_and_cmd_data;
4078 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
4079 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
4080 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
4081 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
4082 struct ramrod_data protocol_data;
4084 __le32 reserved2[11];
4088 * Rx Last CQE in page (in ETH)
4090 struct eth_rx_cqe_next_page {
4093 __le32 reserved[14];
4097 * union for all eth rx cqe types (fix their sizes)
4100 struct eth_fast_path_rx_cqe fast_path_cqe;
4101 struct common_ramrod_eth_rx_cqe ramrod_cqe;
4102 struct eth_rx_cqe_next_page next_page_cqe;
4103 struct eth_end_agg_rx_cqe end_agg_cqe;
4108 * Values for RX ETH CQE type field
4110 enum eth_rx_cqe_type {
4111 RX_ETH_CQE_TYPE_ETH_FASTPATH,
4112 RX_ETH_CQE_TYPE_ETH_RAMROD,
4113 RX_ETH_CQE_TYPE_ETH_START_AGG,
4114 RX_ETH_CQE_TYPE_ETH_STOP_AGG,
4120 * Type of SGL/Raw field in ETH RX fast path CQE
4122 enum eth_rx_fp_sel {
4130 * The eth Rx SGE Descriptor
4139 * common data for all protocols
4142 __le32 conn_and_cmd_data;
4143 #define SPE_HDR_CID (0xFFFFFF<<0)
4144 #define SPE_HDR_CID_SHIFT 0
4145 #define SPE_HDR_CMD_ID (0xFF<<24)
4146 #define SPE_HDR_CMD_ID_SHIFT 24
4148 #define SPE_HDR_CONN_TYPE (0xFF<<0)
4149 #define SPE_HDR_CONN_TYPE_SHIFT 0
4150 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
4151 #define SPE_HDR_FUNCTION_ID_SHIFT 8
4156 * specific data for ethernet slow path element
4158 union eth_specific_data {
4159 u8 protocol_data[8];
4160 struct regpair client_update_ramrod_data;
4161 struct regpair client_init_ramrod_init_data;
4162 struct eth_halt_ramrod_data halt_ramrod_data;
4163 struct regpair update_data_addr;
4164 struct eth_common_ramrod_data common_ramrod_data;
4165 struct regpair classify_cfg_addr;
4166 struct regpair filter_cfg_addr;
4167 struct regpair mcast_cfg_addr;
4171 * Ethernet slow path element
4175 union eth_specific_data data;
4180 * Ethernet command ID for slow path elements
4182 enum eth_spqe_cmd_id {
4183 RAMROD_CMD_ID_ETH_UNUSED,
4184 RAMROD_CMD_ID_ETH_CLIENT_SETUP,
4185 RAMROD_CMD_ID_ETH_HALT,
4186 RAMROD_CMD_ID_ETH_FORWARD_SETUP,
4187 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP,
4188 RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
4189 RAMROD_CMD_ID_ETH_EMPTY,
4190 RAMROD_CMD_ID_ETH_TERMINATE,
4191 RAMROD_CMD_ID_ETH_TPA_UPDATE,
4192 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES,
4193 RAMROD_CMD_ID_ETH_FILTER_RULES,
4194 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
4195 RAMROD_CMD_ID_ETH_RSS_UPDATE,
4196 RAMROD_CMD_ID_ETH_SET_MAC,
4202 * eth tpa update command
4204 enum eth_tpa_update_command {
4205 TPA_UPDATE_NONE_COMMAND,
4206 TPA_UPDATE_ENABLE_COMMAND,
4207 TPA_UPDATE_DISABLE_COMMAND,
4208 MAX_ETH_TPA_UPDATE_COMMAND
4211 /* In case of LSO over IPv4 tunnel, whether to increment
4212 * IP ID on external IP header or internal IP header
4214 enum eth_tunnel_lso_inc_ip_id {
4217 MAX_ETH_TUNNEL_LSO_INC_IP_ID
4220 /* In case tunnel exist and L4 checksum offload,
4221 * the pseudo checksum location, on packet or on BD.
4223 enum eth_tunnel_non_lso_pcsum_location {
4226 MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION
4230 * Tx regular BD structure
4235 __le16 total_pkt_bytes;
4242 * structure for easy accessibility to assembler
4244 struct eth_tx_bd_flags {
4246 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4247 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4248 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4249 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4250 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4251 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4252 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4253 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4254 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4255 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4256 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4257 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4258 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4259 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4263 * The eth Tx Buffer Descriptor
4265 struct eth_tx_start_bd {
4270 __le16 vlan_or_ethertype;
4271 struct eth_tx_bd_flags bd_flags;
4273 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4274 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4275 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4276 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4277 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
4278 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
4279 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7)
4280 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
4284 * Tx parsing BD structure for ETH E1/E1h
4286 struct eth_tx_parse_bd_e1x {
4288 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4289 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4290 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4)
4291 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
4292 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6)
4293 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
4294 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7)
4295 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
4296 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8)
4297 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
4298 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9)
4299 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
4301 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4302 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4303 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4304 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4305 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4306 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4307 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4308 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4309 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4310 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4311 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4312 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4313 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4314 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4315 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4316 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4318 __le16 total_hlen_w;
4319 __le16 tcp_pseudo_csum;
4322 __le32 tcp_send_seq;
4326 * Tx parsing BD structure for ETH E2
4328 struct eth_tx_parse_bd_e2 {
4329 union eth_mac_addr_or_tunnel_data data;
4330 __le32 parsing_data;
4331 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0)
4332 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
4333 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11)
4334 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
4335 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15)
4336 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
4337 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16)
4338 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
4339 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30)
4340 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
4344 * Tx 2nd parsing BD structure for ETH packet
4346 struct eth_tx_parse_2nd_bd {
4348 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
4349 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
4350 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4)
4351 #define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4
4352 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
4353 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
4354 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
4355 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
4356 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7)
4357 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
4358 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
4359 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
4360 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13)
4361 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13
4364 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
4365 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
4366 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1)
4367 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
4368 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2)
4369 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
4370 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3)
4371 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
4372 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4)
4373 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
4374 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5)
4375 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
4376 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6)
4377 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
4378 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
4379 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
4381 u8 tunnel_udp_hdr_start_w;
4382 u8 fw_ip_hdr_to_payload_w;
4383 __le16 fw_ip_csum_wo_len_flags_frag;
4385 __le32 tcp_send_seq;
4388 /* The last BD in the BD memory will hold a pointer to the next BD memory */
4389 struct eth_tx_next_bd {
4396 * union for 4 Bd types
4398 union eth_tx_bd_types {
4399 struct eth_tx_start_bd start_bd;
4400 struct eth_tx_bd reg_bd;
4401 struct eth_tx_parse_bd_e1x parse_bd_e1x;
4402 struct eth_tx_parse_bd_e2 parse_bd_e2;
4403 struct eth_tx_parse_2nd_bd parse_2nd_bd;
4404 struct eth_tx_next_bd next_bd;
4408 * array of 13 bds as appears in the eth xstorm context
4410 struct eth_tx_bds_array {
4411 union eth_tx_bd_types bds[13];
4416 * VLAN mode on TX BDs
4418 enum eth_tx_vlan_type {
4422 X_ETH_FW_ADDED_VLAN,
4423 MAX_ETH_TX_VLAN_TYPE
4428 * Ethernet VLAN filtering mode in E1x
4430 enum eth_vlan_filter_mode {
4431 ETH_VLAN_FILTER_ANY_VLAN,
4432 ETH_VLAN_FILTER_SPECIFIC_VLAN,
4433 ETH_VLAN_FILTER_CLASSIFY,
4434 MAX_ETH_VLAN_FILTER_MODE
4439 * MAC filtering configuration command header
4441 struct mac_configuration_hdr {
4449 * MAC address in list for ramrod
4451 struct mac_configuration_entry {
4452 __le16 lsb_mac_addr;
4453 __le16 middle_mac_addr;
4454 __le16 msb_mac_addr;
4458 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4459 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4460 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4461 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4462 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4463 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4464 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4465 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4466 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4467 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4468 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4469 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4471 __le32 clients_bit_vector;
4475 * MAC filtering configuration command
4477 struct mac_configuration_cmd {
4478 struct mac_configuration_hdr hdr;
4479 struct mac_configuration_entry config_table[64];
4484 * Set-MAC command type (in E1x)
4486 enum set_mac_action_type {
4487 T_ETH_MAC_COMMAND_INVALIDATE,
4488 T_ETH_MAC_COMMAND_SET,
4489 MAX_SET_MAC_ACTION_TYPE
4494 * Ethernet TPA Modes
4503 * tpa update ramrod data
4505 struct tpa_update_ramrod_data {
4510 u8 max_sges_for_packet;
4511 u8 complete_on_both_clients;
4512 u8 dont_verify_rings_pause_thr_flg;
4514 __le16 sge_buff_size;
4515 __le16 max_agg_size;
4516 __le32 sge_page_base_lo;
4517 __le32 sge_page_base_hi;
4518 __le16 sge_pause_thr_low;
4519 __le16 sge_pause_thr_high;
4524 * approximate-match multicast filtering for E1H per function in Tstorm
4526 struct tstorm_eth_approximate_match_multicast_filtering {
4527 u32 mcast_add_hash_bit_array[8];
4532 * Common configuration parameters per function in Tstorm
4534 struct tstorm_eth_function_common_config {
4535 __le16 config_flags;
4536 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4537 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4538 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4539 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4540 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4541 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4542 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4543 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4544 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4545 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4546 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4547 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4548 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4549 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4557 * MAC filtering configuration parameters per port in Tstorm
4559 struct tstorm_eth_mac_filter_config {
4561 u32 ucast_accept_all;
4563 u32 mcast_accept_all;
4564 u32 bcast_accept_all;
4566 u32 unmatched_unicast;
4571 * tx only queue init ramrod data
4573 struct tx_queue_init_ramrod_data {
4574 struct client_init_general_data general;
4575 struct client_init_tx_data tx;
4580 * Three RX producers for ETH
4582 struct ustorm_eth_rx_producers {
4583 #if defined(__BIG_ENDIAN)
4586 #elif defined(__LITTLE_ENDIAN)
4590 #if defined(__BIG_ENDIAN)
4593 #elif defined(__LITTLE_ENDIAN)
4601 * FCoE RX statistics parameters section#0
4603 struct fcoe_rx_stat_params_section0 {
4604 __le32 fcoe_rx_pkt_cnt;
4605 __le32 fcoe_rx_byte_cnt;
4610 * FCoE RX statistics parameters section#1
4612 struct fcoe_rx_stat_params_section1 {
4613 __le32 fcoe_ver_cnt;
4614 __le32 fcoe_rx_drop_pkt_cnt;
4619 * FCoE RX statistics parameters section#2
4621 struct fcoe_rx_stat_params_section2 {
4623 __le32 eofa_del_cnt;
4624 __le32 miss_frame_cnt;
4625 __le32 seq_timeout_cnt;
4626 __le32 drop_seq_cnt;
4627 __le32 fcoe_rx_drop_pkt_cnt;
4628 __le32 fcp_rx_pkt_cnt;
4634 * FCoE TX statistics parameters
4636 struct fcoe_tx_stat_params {
4637 __le32 fcoe_tx_pkt_cnt;
4638 __le32 fcoe_tx_byte_cnt;
4639 __le32 fcp_tx_pkt_cnt;
4644 * FCoE statistics parameters
4646 struct fcoe_statistics_params {
4647 struct fcoe_tx_stat_params tx_stat;
4648 struct fcoe_rx_stat_params_section0 rx_stat0;
4649 struct fcoe_rx_stat_params_section1 rx_stat1;
4650 struct fcoe_rx_stat_params_section2 rx_stat2;
4655 * The data afex vif list ramrod need
4657 struct afex_vif_list_ramrod_data {
4658 u8 afex_vif_list_command;
4660 __le16 vif_list_index;
4668 * cfc delete event data
4670 struct cfc_del_event_data {
4678 * per-port SAFC demo variables
4680 struct cmng_flags_per_port {
4682 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4683 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4684 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4685 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4686 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4687 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4688 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4689 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4690 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4691 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4697 * per-port rate shaping variables
4699 struct rate_shaping_vars_per_port {
4700 u32 rs_periodic_timeout;
4705 * per-port fairness variables
4707 struct fairness_vars_per_port {
4710 u32 fairness_timeout;
4715 * per-port SAFC variables
4717 struct safc_struct_per_port {
4718 #if defined(__BIG_ENDIAN)
4721 u8 safc_timeout_usec;
4722 #elif defined(__LITTLE_ENDIAN)
4723 u8 safc_timeout_usec;
4727 u8 cos_to_traffic_types[MAX_COS_NUMBER];
4728 u16 cos_to_pause_mask[NUM_OF_SAFC_BITS];
4732 * Per-port congestion management variables
4734 struct cmng_struct_per_port {
4735 struct rate_shaping_vars_per_port rs_vars;
4736 struct fairness_vars_per_port fair_vars;
4737 struct safc_struct_per_port safc_vars;
4738 struct cmng_flags_per_port flags;
4742 * a single rate shaping counter. can be used as protocol or vnic counter
4744 struct rate_shaping_counter {
4746 #if defined(__BIG_ENDIAN)
4749 #elif defined(__LITTLE_ENDIAN)
4756 * per-vnic rate shaping variables
4758 struct rate_shaping_vars_per_vn {
4759 struct rate_shaping_counter vn_counter;
4763 * per-vnic fairness variables
4765 struct fairness_vars_per_vn {
4766 u32 cos_credit_delta[MAX_COS_NUMBER];
4767 u32 vn_credit_delta;
4772 * cmng port init state
4775 struct rate_shaping_vars_per_vn vnic_max_rate[4];
4776 struct fairness_vars_per_vn vnic_min_rate[4];
4780 * cmng port init state
4783 struct cmng_struct_per_port port;
4784 struct cmng_vnic vnic;
4789 * driver parameters for congestion management init, all rates are in Mbps
4791 struct cmng_init_input {
4793 u16 vnic_min_rate[4];
4794 u16 vnic_max_rate[4];
4795 u16 cos_min_rate[MAX_COS_NUMBER];
4796 u16 cos_to_pause_mask[MAX_COS_NUMBER];
4797 struct cmng_flags_per_port flags;
4802 * Protocol-common command ID for slow path elements
4804 enum common_spqe_cmd_id {
4805 RAMROD_CMD_ID_COMMON_UNUSED,
4806 RAMROD_CMD_ID_COMMON_FUNCTION_START,
4807 RAMROD_CMD_ID_COMMON_FUNCTION_STOP,
4808 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE,
4809 RAMROD_CMD_ID_COMMON_CFC_DEL,
4810 RAMROD_CMD_ID_COMMON_CFC_DEL_WB,
4811 RAMROD_CMD_ID_COMMON_STAT_QUERY,
4812 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC,
4813 RAMROD_CMD_ID_COMMON_START_TRAFFIC,
4814 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS,
4815 RAMROD_CMD_ID_COMMON_SET_TIMESYNC,
4816 MAX_COMMON_SPQE_CMD_ID
4820 * Per-protocol connection types
4822 enum connection_type {
4823 ETH_CONNECTION_TYPE,
4824 TOE_CONNECTION_TYPE,
4825 RDMA_CONNECTION_TYPE,
4826 ISCSI_CONNECTION_TYPE,
4827 FCOE_CONNECTION_TYPE,
4828 RESERVED_CONNECTION_TYPE_0,
4829 RESERVED_CONNECTION_TYPE_1,
4830 RESERVED_CONNECTION_TYPE_2,
4831 NONE_CONNECTION_TYPE,
4848 * Dynamic HC counters set by the driver
4850 struct hc_dynamic_drv_counter {
4851 u32 val[HC_SB_MAX_DYNAMIC_INDICES];
4855 * zone A per-queue data
4857 struct cstorm_queue_zone_data {
4858 struct hc_dynamic_drv_counter hc_dyn_drv_cnt;
4859 struct regpair reserved[2];
4864 * Vf-PF channel data in cstorm ram (non-triggered zone)
4866 struct vf_pf_channel_zone_data {
4872 * zone for VF non-triggered data
4874 struct non_trigger_vf_zone {
4875 struct vf_pf_channel_zone_data vf_pf_channel;
4879 * Vf-PF channel trigger zone in cstorm ram
4881 struct vf_pf_channel_zone_trigger {
4886 * zone that triggers the in-bound interrupt
4888 struct trigger_vf_zone {
4889 #if defined(__BIG_ENDIAN)
4892 struct vf_pf_channel_zone_trigger vf_pf_channel;
4893 #elif defined(__LITTLE_ENDIAN)
4894 struct vf_pf_channel_zone_trigger vf_pf_channel;
4902 * zone B per-VF data
4904 struct cstorm_vf_zone_data {
4905 struct non_trigger_vf_zone non_trigger;
4906 struct trigger_vf_zone trigger;
4911 * Dynamic host coalescing init parameters, per state machine
4913 struct dynamic_hc_sm_config {
4915 u8 shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES];
4916 u8 hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES];
4917 u8 hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES];
4918 u8 hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES];
4919 u8 hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES];
4923 * Dynamic host coalescing init parameters
4925 struct dynamic_hc_config {
4926 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM];
4930 struct e2_integ_data {
4931 #if defined(__BIG_ENDIAN)
4933 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4934 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4935 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4936 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4937 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4938 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4939 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4940 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4941 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4942 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4943 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4944 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4948 #elif defined(__LITTLE_ENDIAN)
4953 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4954 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4955 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4956 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4957 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4958 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4959 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4960 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4961 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4962 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4963 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4964 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4966 #if defined(__BIG_ENDIAN)
4970 #elif defined(__LITTLE_ENDIAN)
4979 * set mac event data
4981 struct eth_event_data {
4991 struct vf_pf_event_data {
5002 struct vf_flr_event_data {
5011 * malicious VF event data
5013 struct malicious_vf_event_data {
5022 * vif list event data
5024 struct vif_list_event_data {
5032 /* function update event data */
5033 struct function_update_event_data {
5042 /* union for all event ring message types */
5044 struct vf_pf_event_data vf_pf_event;
5045 struct eth_event_data eth_event;
5046 struct cfc_del_event_data cfc_del_event;
5047 struct vf_flr_event_data vf_flr_event;
5048 struct malicious_vf_event_data malicious_vf_event;
5049 struct vif_list_event_data vif_list_event;
5050 struct function_update_event_data function_update_event;
5055 * per PF event ring data
5057 struct event_ring_data {
5058 struct regpair_native base_addr;
5059 #if defined(__BIG_ENDIAN)
5063 #elif defined(__LITTLE_ENDIAN)
5073 * event ring message element (each element is 128 bits)
5075 struct event_ring_msg {
5079 union event_data data;
5083 * event ring next page element (128 bits)
5085 struct event_ring_next {
5086 struct regpair addr;
5091 * union for event ring element types (each element is 128 bits)
5093 union event_ring_elem {
5094 struct event_ring_msg message;
5095 struct event_ring_next next_page;
5100 * Common event ring opcodes
5102 enum event_ring_opcode {
5103 EVENT_RING_OPCODE_VF_PF_CHANNEL,
5104 EVENT_RING_OPCODE_FUNCTION_START,
5105 EVENT_RING_OPCODE_FUNCTION_STOP,
5106 EVENT_RING_OPCODE_CFC_DEL,
5107 EVENT_RING_OPCODE_CFC_DEL_WB,
5108 EVENT_RING_OPCODE_STAT_QUERY,
5109 EVENT_RING_OPCODE_STOP_TRAFFIC,
5110 EVENT_RING_OPCODE_START_TRAFFIC,
5111 EVENT_RING_OPCODE_VF_FLR,
5112 EVENT_RING_OPCODE_MALICIOUS_VF,
5113 EVENT_RING_OPCODE_FORWARD_SETUP,
5114 EVENT_RING_OPCODE_RSS_UPDATE_RULES,
5115 EVENT_RING_OPCODE_FUNCTION_UPDATE,
5116 EVENT_RING_OPCODE_AFEX_VIF_LISTS,
5117 EVENT_RING_OPCODE_SET_MAC,
5118 EVENT_RING_OPCODE_CLASSIFICATION_RULES,
5119 EVENT_RING_OPCODE_FILTERS_RULES,
5120 EVENT_RING_OPCODE_MULTICAST_RULES,
5121 EVENT_RING_OPCODE_SET_TIMESYNC,
5122 MAX_EVENT_RING_OPCODE
5126 * Modes for fairness algorithm
5128 enum fairness_mode {
5129 FAIRNESS_COS_WRR_MODE,
5130 FAIRNESS_COS_ETS_MODE,
5138 struct priority_cos {
5145 * The data for flow control configuration
5147 struct flow_control_configuration {
5148 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
5151 u8 dont_add_pri_0_en;
5160 struct function_start_data {
5162 u8 allow_npar_tx_switching;
5166 u8 network_cos_mode;
5171 __le16 reserved1[2];
5174 struct function_update_data {
5175 u8 vif_id_change_flg;
5176 u8 afex_default_vlan_change_flg;
5177 u8 allowed_priorities_change_flg;
5178 u8 network_cos_mode_change_flg;
5180 __le16 afex_default_vlan;
5181 u8 allowed_priorities;
5182 u8 network_cos_mode;
5183 u8 lb_mode_en_change_flg;
5185 u8 tx_switch_suspend_change_flg;
5186 u8 tx_switch_suspend;
5189 u8 update_gre_cfg_flg;
5197 * FW version stored in the Xstorm RAM
5200 #if defined(__BIG_ENDIAN)
5205 #elif defined(__LITTLE_ENDIAN)
5212 #define FW_VERSION_OPTIMIZED (0x1<<0)
5213 #define FW_VERSION_OPTIMIZED_SHIFT 0
5214 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
5215 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
5216 #define FW_VERSION_CHIP_VERSION (0x3<<2)
5217 #define FW_VERSION_CHIP_VERSION_SHIFT 2
5218 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
5219 #define __FW_VERSION_RESERVED_SHIFT 4
5224 GRE_OUTER_HEADERS_RSS,
5225 GRE_INNER_HEADERS_RSS,
5226 NVGRE_KEY_ENTROPY_RSS,
5230 /* GRE Tunnel Mode */
5231 enum gre_tunnel_type {
5240 * Dynamic Host-Coalescing - Driver(host) counters
5242 struct hc_dynamic_sb_drv_counters {
5243 u32 dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES];
5248 * 2 bytes. configuration/state parameters for a single protocol index
5250 struct hc_index_data {
5251 #if defined(__BIG_ENDIAN)
5253 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5254 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5255 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5256 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5257 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5258 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5259 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5260 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5262 #elif defined(__LITTLE_ENDIAN)
5265 #define HC_INDEX_DATA_SM_ID (0x1<<0)
5266 #define HC_INDEX_DATA_SM_ID_SHIFT 0
5267 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
5268 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
5269 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
5270 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
5271 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
5272 #define HC_INDEX_DATA_RESERVE_SHIFT 3
5280 struct hc_status_block_sm {
5281 #if defined(__BIG_ENDIAN)
5286 #elif defined(__LITTLE_ENDIAN)
5296 * hold PCI identification variables- used in various places in firmware
5299 #if defined(__BIG_ENDIAN)
5304 #elif defined(__LITTLE_ENDIAN)
5313 * The fast-path status block meta-data, common to all chips
5316 struct regpair_native host_sb_addr;
5317 struct hc_status_block_sm state_machine[HC_SB_MAX_SM];
5318 struct pci_entity p_func;
5319 #if defined(__BIG_ENDIAN)
5324 #elif defined(__LITTLE_ENDIAN)
5330 struct regpair_native rsrv1[2];
5335 * Segment types for host coaslescing
5345 * The fast-path status block meta-data
5347 struct hc_sp_status_block_data {
5348 struct regpair_native host_sb_addr;
5349 #if defined(__BIG_ENDIAN)
5354 #elif defined(__LITTLE_ENDIAN)
5360 struct pci_entity p_func;
5365 * The fast-path status block meta-data
5367 struct hc_status_block_data_e1x {
5368 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X];
5369 struct hc_sb_data common;
5374 * The fast-path status block meta-data
5376 struct hc_status_block_data_e2 {
5377 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2];
5378 struct hc_sb_data common;
5383 * IGU block operartion modes (in Everest2)
5402 * Malicious VF error ID
5404 enum malicious_vf_error_id {
5405 VF_PF_CHANNEL_NOT_READY,
5406 ETH_ILLEGAL_BD_LENGTHS,
5407 ETH_PACKET_TOO_SHORT,
5408 ETH_PAYLOAD_TOO_BIG,
5409 ETH_ILLEGAL_ETH_TYPE,
5410 ETH_ILLEGAL_LSO_HDR_LEN,
5413 ETH_START_BD_NOT_SET,
5414 ETH_ILLEGAL_PARSE_NBDS,
5415 ETH_IPV6_AND_CHECKSUM,
5416 ETH_VLAN_FLG_INCORRECT,
5417 ETH_ILLEGAL_LSO_MSS,
5418 ETH_TUNNEL_NOT_SUPPORTED,
5419 MAX_MALICIOUS_VF_ERROR_ID
5423 * Multi-function modes
5429 MULTI_FUNCTION_AFEX,
5434 * Protocol-common statistics collected by the Tstorm (per pf)
5436 struct tstorm_per_pf_stats {
5437 struct regpair rcv_error_bytes;
5443 struct per_pf_stats {
5444 struct tstorm_per_pf_stats tstorm_pf_statistics;
5449 * Protocol-common statistics collected by the Tstorm (per port)
5451 struct tstorm_per_port_stats {
5453 __le32 mac_filter_discard;
5454 __le32 brb_truncate_discard;
5455 __le32 mf_tag_discard;
5463 struct per_port_stats {
5464 struct tstorm_per_port_stats tstorm_port_statistics;
5469 * Protocol-common statistics collected by the Tstorm (per client)
5471 struct tstorm_per_queue_stats {
5472 struct regpair rcv_ucast_bytes;
5473 __le32 rcv_ucast_pkts;
5474 __le32 checksum_discard;
5475 struct regpair rcv_bcast_bytes;
5476 __le32 rcv_bcast_pkts;
5477 __le32 pkts_too_big_discard;
5478 struct regpair rcv_mcast_bytes;
5479 __le32 rcv_mcast_pkts;
5480 __le32 ttl0_discard;
5481 __le16 no_buff_discard;
5487 * Protocol-common statistics collected by the Ustorm (per client)
5489 struct ustorm_per_queue_stats {
5490 struct regpair ucast_no_buff_bytes;
5491 struct regpair mcast_no_buff_bytes;
5492 struct regpair bcast_no_buff_bytes;
5493 __le32 ucast_no_buff_pkts;
5494 __le32 mcast_no_buff_pkts;
5495 __le32 bcast_no_buff_pkts;
5496 __le32 coalesced_pkts;
5497 struct regpair coalesced_bytes;
5498 __le32 coalesced_events;
5499 __le32 coalesced_aborts;
5503 * Protocol-common statistics collected by the Xstorm (per client)
5505 struct xstorm_per_queue_stats {
5506 struct regpair ucast_bytes_sent;
5507 struct regpair mcast_bytes_sent;
5508 struct regpair bcast_bytes_sent;
5509 __le32 ucast_pkts_sent;
5510 __le32 mcast_pkts_sent;
5511 __le32 bcast_pkts_sent;
5512 __le32 error_drop_pkts;
5518 struct per_queue_stats {
5519 struct tstorm_per_queue_stats tstorm_queue_statistics;
5520 struct ustorm_per_queue_stats ustorm_queue_statistics;
5521 struct xstorm_per_queue_stats xstorm_queue_statistics;
5526 * FW version stored in first line of pram
5528 struct pram_fw_version {
5534 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5535 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5536 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5537 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5538 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5539 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5540 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5541 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5542 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5543 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5548 * Ethernet slow path element
5550 union protocol_common_specific_data {
5551 u8 protocol_data[8];
5552 struct regpair phy_address;
5553 struct regpair mac_config_addr;
5554 struct afex_vif_list_ramrod_data afex_vif_list_data;
5558 * The send queue element
5560 struct protocol_common_spe {
5562 union protocol_common_specific_data data;
5566 * The send queue element
5568 struct slow_path_element {
5570 struct regpair protocol_data;
5575 * Protocol-common statistics counter
5577 struct stats_counter {
5578 __le16 xstats_counter;
5581 __le16 tstats_counter;
5584 __le16 ustats_counter;
5587 __le16 cstats_counter;
5596 struct stats_query_entry {
5601 struct regpair address;
5607 struct stats_query_cmd_group {
5608 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
5613 * statistic command header
5615 struct stats_query_header {
5618 __le16 drv_stats_counter;
5620 struct regpair stats_counters_addrs;
5625 * Types of statistcis query entry
5627 enum stats_query_type {
5633 MAX_STATS_QUERY_TYPE
5638 * Indicate of the function status block state
5640 enum status_block_state {
5644 MAX_STATUS_BLOCK_STATE
5649 * Storm IDs (including attentions for IGU related enums)
5662 * Taffic types used in ETS and flow control algorithms
5665 LLFC_TRAFFIC_TYPE_NW,
5666 LLFC_TRAFFIC_TYPE_FCOE,
5667 LLFC_TRAFFIC_TYPE_ISCSI,
5673 * zone A per-queue data
5675 struct tstorm_queue_zone_data {
5676 struct regpair reserved[4];
5681 * zone B per-VF data
5683 struct tstorm_vf_zone_data {
5684 struct regpair reserved;
5689 * zone A per-queue data
5691 struct ustorm_queue_zone_data {
5692 struct ustorm_eth_rx_producers eth_rx_producers;
5693 struct regpair reserved[3];
5698 * zone B per-VF data
5700 struct ustorm_vf_zone_data {
5701 struct regpair reserved;
5706 * data per VF-PF channel
5708 struct vf_pf_channel_data {
5709 #if defined(__BIG_ENDIAN)
5713 #elif defined(__LITTLE_ENDIAN)
5723 * State of VF-PF channel
5725 enum vf_pf_channel_state {
5726 VF_PF_CHANNEL_STATE_READY,
5727 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK,
5728 MAX_VF_PF_CHANNEL_STATE
5733 * vif_list_rule_kind
5735 enum vif_list_rule_kind {
5738 VIF_LIST_RULE_CLEAR_ALL,
5739 VIF_LIST_RULE_CLEAR_FUNC,
5740 MAX_VIF_LIST_RULE_KIND
5745 * zone A per-queue data
5747 struct xstorm_queue_zone_data {
5748 struct regpair reserved[4];
5753 * zone B per-VF data
5755 struct xstorm_vf_zone_data {
5756 struct regpair reserved;
5759 #endif /* BNX2X_HSI_H */
projects / firefly-linux-kernel-4.4.55.git / blob