1 /* bnx2x.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
17 #include <linux/pci.h>
18 #include <linux/netdevice.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/types.h>
21 #include <linux/pci_regs.h>
23 #include <linux/ptp_clock_kernel.h>
24 #include <linux/net_tstamp.h>
25 #include <linux/timecounter.h>
27 /* compilation time flags */
29 /* define this to make the driver freeze on error to allow getting debug info
30 * (you will need to reboot afterwards) */
31 /* #define BNX2X_STOP_ON_ERROR */
33 #define DRV_MODULE_VERSION "1.710.51-0"
34 #define DRV_MODULE_RELDATE "2014/02/10"
35 #define BNX2X_BC_VER 0x040200
37 #if defined(CONFIG_DCB)
41 #include "bnx2x_hsi.h"
43 #include "../cnic_if.h"
45 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
47 #include <linux/mdio.h>
49 #include "bnx2x_reg.h"
50 #include "bnx2x_fw_defs.h"
51 #include "bnx2x_mfw_req.h"
52 #include "bnx2x_link.h"
54 #include "bnx2x_dcb.h"
55 #include "bnx2x_stats.h"
56 #include "bnx2x_vfpf.h"
64 /* error/debug prints */
66 #define DRV_MODULE_NAME "bnx2x"
68 /* for messages that are currently off */
69 #define BNX2X_MSG_OFF 0x0
70 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
71 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
72 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
73 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
74 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
75 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
76 #define BNX2X_MSG_IOV 0x0800000
77 #define BNX2X_MSG_PTP 0x1000000
78 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
79 #define BNX2X_MSG_ETHTOOL 0x4000000
80 #define BNX2X_MSG_DCB 0x8000000
82 /* regular debug print */
83 #define DP_INNER(fmt, ...) \
84 pr_notice("[%s:%d(%s)]" fmt, \
86 bp->dev ? (bp->dev->name) : "?", \
89 #define DP(__mask, fmt, ...) \
91 if (unlikely(bp->msg_enable & (__mask))) \
92 DP_INNER(fmt, ##__VA_ARGS__); \
95 #define DP_AND(__mask, fmt, ...) \
97 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \
98 DP_INNER(fmt, ##__VA_ARGS__); \
101 #define DP_CONT(__mask, fmt, ...) \
103 if (unlikely(bp->msg_enable & (__mask))) \
104 pr_cont(fmt, ##__VA_ARGS__); \
107 /* errors debug print */
108 #define BNX2X_DBG_ERR(fmt, ...) \
110 if (unlikely(netif_msg_probe(bp))) \
111 pr_err("[%s:%d(%s)]" fmt, \
112 __func__, __LINE__, \
113 bp->dev ? (bp->dev->name) : "?", \
117 /* for errors (never masked) */
118 #define BNX2X_ERR(fmt, ...) \
120 pr_err("[%s:%d(%s)]" fmt, \
121 __func__, __LINE__, \
122 bp->dev ? (bp->dev->name) : "?", \
126 #define BNX2X_ERROR(fmt, ...) \
127 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
129 /* before we have a dev->name use dev_info() */
130 #define BNX2X_DEV_INFO(fmt, ...) \
132 if (unlikely(netif_msg_probe(bp))) \
133 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
137 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
138 #ifdef BNX2X_STOP_ON_ERROR
139 #define bnx2x_panic() \
142 BNX2X_ERR("driver assert\n"); \
143 bnx2x_panic_dump(bp, true); \
146 #define bnx2x_panic() \
149 BNX2X_ERR("driver assert\n"); \
150 bnx2x_panic_dump(bp, false); \
154 #define bnx2x_mc_addr(ha) ((ha)->addr)
155 #define bnx2x_uc_addr(ha) ((ha)->addr)
157 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
158 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
159 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
161 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
163 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
164 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
165 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
167 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
168 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
169 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
171 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
172 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
174 #define REG_RD_DMAE(bp, offset, valp, len32) \
176 bnx2x_read_dmae(bp, offset, len32);\
177 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
180 #define REG_WR_DMAE(bp, offset, valp, len32) \
182 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
183 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
187 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
188 REG_WR_DMAE(bp, offset, valp, len32)
190 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
192 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
193 bnx2x_write_big_buf_wb(bp, addr, len32); \
196 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
197 offsetof(struct shmem_region, field))
198 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
199 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
201 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
202 offsetof(struct shmem2_region, field))
203 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
204 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
205 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
206 offsetof(struct mf_cfg, field))
207 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
208 offsetof(struct mf2_cfg, field))
210 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
211 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
212 MF_CFG_ADDR(bp, field), (val))
213 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
215 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
216 (SHMEM2_RD((bp), size) > \
217 offsetof(struct shmem2_region, field)))
219 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
220 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
224 /* General SP events - stats query, cfc delete, etc */
225 #define HC_SP_INDEX_ETH_DEF_CONS 3
228 #define HC_SP_INDEX_EQ_CONS 7
230 /* FCoE L2 connection completions */
231 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
232 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
234 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
235 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
237 /* Special clients parameters */
241 #define BNX2X_FCOE_L2_RX_INDEX \
242 (&bp->def_status_blk->sp_sb.\
243 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
245 #define BNX2X_FCOE_L2_TX_INDEX \
246 (&bp->def_status_blk->sp_sb.\
247 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
251 * CLIDs below is a CLID for func 0, then the CLID for other
252 * functions will be calculated by the formula:
254 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
258 BNX2X_ISCSI_ETH_CL_ID_IDX,
259 BNX2X_FCOE_ETH_CL_ID_IDX,
260 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
263 /* use a value high enough to be above all the PFs, which has least significant
264 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
265 * calculate doorbell address according to old doorbell configuration scheme
266 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
267 * We must avoid coming up with cid 8 for iscsi since according to this method
268 * the designated UIO cid will come out 0 and it has a special handling for that
269 * case which doesn't suit us. Therefore will will cieling to closes cid which
270 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
273 #define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
275 /* amount of cids traversed by UIO's DPM addition to doorbell */
277 /* roundup to DPM offset */
278 #define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
280 /* offset to nearest value which has lsb nibble matching DPM */
281 #define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \
283 /* add offset to rounded-up cid to get a value which could be used with UIO */
284 #define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
285 /* but wait - avoid UIO special case for cid 0 */
286 #define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \
287 (UIO_DPM_ALIGN(bp) == UIO_DPM))
288 /* Properly DPM aligned CID dajusted to cid 0 secal case */
289 #define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \
290 (UIO_DPM_CID0_OFFSET(bp)))
291 /* how many cids were wasted - need this value for cid allocation */
292 #define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \
293 BNX2X_1st_NON_L2_ETH_CID(bp))
295 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
297 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
299 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
300 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
301 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
302 #define FCOE_INIT(bp) ((bp)->fcoe_init)
304 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
305 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
310 /* defines for multiple tx priority indices */
311 #define FIRST_TX_ONLY_COS_INDEX 1
312 #define FIRST_TX_COS_INDEX 0
314 /* rules for calculating the cids of tx-only connections */
315 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
316 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
317 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
319 /* fp index inside class of service range */
320 #define FP_COS_TO_TXQ(fp, cos, bp) \
321 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
323 /* Indexes for transmission queues array:
324 * txdata for RSS i CoS j is at location i + (j * num of RSS)
325 * txdata for FCoE (if exist) is at location max cos * num of RSS
326 * txdata for FWD (if exist) is one location after FCoE
327 * txdata for OOO (if exist) is one location after FWD
334 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
335 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
339 * This driver uses new build_skb() API :
340 * RX ring buffer contains pointer to kmalloc() data only,
341 * skb are built only after Hardware filled the frame.
345 DEFINE_DMA_UNMAP_ADDR(mapping);
352 /* Set on the first BD descriptor when there is a split BD */
353 #define BNX2X_TSO_SPLIT_BD (1<<0)
354 #define BNX2X_HAS_SECOND_PBD (1<<1)
359 DEFINE_DMA_UNMAP_ADDR(mapping);
363 struct doorbell_set_prod data;
367 /* dropless fc FW/HW related params */
368 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
369 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
370 ETH_MAX_AGGREGATION_QUEUES_E1 :\
371 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
372 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
373 #define FW_PREFETCH_CNT 16
374 #define DROPLESS_FC_HEADROOM 100
377 #define BCM_PAGE_SHIFT 12
378 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
379 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
380 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
382 #define PAGES_PER_SGE_SHIFT 0
383 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
384 #define SGE_PAGE_SIZE PAGE_SIZE
385 #define SGE_PAGE_SHIFT PAGE_SHIFT
386 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
387 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
388 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
391 /* SGE ring related macros */
392 #define NUM_RX_SGE_PAGES 2
393 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
394 #define NEXT_PAGE_SGE_DESC_CNT 2
395 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
396 /* RX_SGE_CNT is promised to be a power of 2 */
397 #define RX_SGE_MASK (RX_SGE_CNT - 1)
398 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
399 #define MAX_RX_SGE (NUM_RX_SGE - 1)
400 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
401 (MAX_RX_SGE_CNT - 1)) ? \
402 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
404 #define RX_SGE(x) ((x) & MAX_RX_SGE)
407 * Number of required SGEs is the sum of two:
408 * 1. Number of possible opened aggregations (next packet for
409 * these aggregations will probably consume SGE immediately)
410 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
411 * after placement on BD for new TPA aggregation)
413 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
415 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
416 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
417 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
419 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
420 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
421 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
423 /* Manipulate a bit vector defined as an array of u64 */
425 /* Number of bits in one sge_mask array element */
426 #define BIT_VEC64_ELEM_SZ 64
427 #define BIT_VEC64_ELEM_SHIFT 6
428 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
430 #define __BIT_VEC64_SET_BIT(el, bit) \
432 el = ((el) | ((u64)0x1 << (bit))); \
435 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
437 el = ((el) & (~((u64)0x1 << (bit)))); \
440 #define BIT_VEC64_SET_BIT(vec64, idx) \
441 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
442 (idx) & BIT_VEC64_ELEM_MASK)
444 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
445 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
446 (idx) & BIT_VEC64_ELEM_MASK)
448 #define BIT_VEC64_TEST_BIT(vec64, idx) \
449 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
450 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
452 /* Creates a bitmask of all ones in less significant bits.
453 idx - index of the most significant bit in the created mask */
454 #define BIT_VEC64_ONES_MASK(idx) \
455 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
456 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
458 /*******************************************************/
460 /* Number of u64 elements in SGE mask array */
461 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
462 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
463 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
465 union host_hc_status_block {
466 /* pointer to fp status block e1x */
467 struct host_hc_status_block_e1x *e1x_sb;
468 /* pointer to fp status block e2 */
469 struct host_hc_status_block_e2 *e2_sb;
472 struct bnx2x_agg_info {
474 * First aggregation buffer is a data buffer, the following - are pages.
475 * We will preallocate the data buffer for each aggregation when
476 * we open the interface and will replace the BD at the consumer
477 * with this one when we receive the TPA_START CQE in order to
478 * keep the Rx BD ring consistent.
480 struct sw_rx_bd first_buf;
482 #define BNX2X_TPA_START 1
483 #define BNX2X_TPA_STOP 2
484 #define BNX2X_TPA_ERROR 3
490 enum pkt_hash_types rxhash_type;
495 #define Q_STATS_OFFSET32(stat_name) \
496 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
498 struct bnx2x_fp_txdata {
500 struct sw_tx_bd *tx_buf_ring;
502 union eth_tx_bd_types *tx_desc_ring;
503 dma_addr_t tx_desc_mapping;
514 unsigned long tx_pkt;
519 struct bnx2x_fastpath *parent_fp;
523 enum bnx2x_tpa_mode_t {
528 struct bnx2x_fastpath {
529 struct bnx2x *bp; /* parent */
531 struct napi_struct napi;
533 #ifdef CONFIG_NET_RX_BUSY_POLL
534 unsigned long busy_poll_state;
537 union host_hc_status_block status_blk;
538 /* chip independent shortcuts into sb structure */
539 __le16 *sb_index_values;
540 __le16 *sb_running_index;
541 /* chip independent shortcut into rx_prods_offset memory */
542 u32 ustorm_rx_prods_offset;
545 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
546 dma_addr_t status_blk_mapping;
548 enum bnx2x_tpa_mode_t mode;
550 u8 max_cos; /* actual number of active tx coses */
551 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
553 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
554 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
556 struct eth_rx_bd *rx_desc_ring;
557 dma_addr_t rx_desc_mapping;
559 union eth_rx_cqe *rx_comp_ring;
560 dma_addr_t rx_comp_mapping;
563 struct eth_rx_sge *rx_sge_ring;
564 dma_addr_t rx_sge_mapping;
566 u64 sge_mask[RX_SGE_MASK_LEN];
572 u8 index; /* number in fp array */
573 u8 rx_queue; /* index for skb_record */
574 u8 cl_id; /* eth client id */
576 u8 fw_sb_id; /* status block number in FW */
577 u8 igu_sb_id; /* status block number in HW */
584 /* The last maximal completed SGE */
587 unsigned long rx_pkt,
591 struct bnx2x_agg_info *tpa_info;
593 #ifdef BNX2X_STOP_ON_ERROR
596 /* The size is calculated using the following:
597 sizeof name field from netdev structure +
599 4 (for the digits and to make it DWORD aligned) */
600 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
601 char name[FP_NAME_SIZE];
604 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
605 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
606 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
607 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
609 #ifdef CONFIG_NET_RX_BUSY_POLL
611 enum bnx2x_fp_state {
612 BNX2X_STATE_FP_NAPI = BIT(0), /* NAPI handler owns the queue */
614 BNX2X_STATE_FP_NAPI_REQ_BIT = 1, /* NAPI would like to own the queue */
615 BNX2X_STATE_FP_NAPI_REQ = BIT(1),
617 BNX2X_STATE_FP_POLL_BIT = 2,
618 BNX2X_STATE_FP_POLL = BIT(2), /* busy_poll owns the queue */
620 BNX2X_STATE_FP_DISABLE_BIT = 3, /* queue is dismantled */
623 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp)
625 WRITE_ONCE(fp->busy_poll_state, 0);
628 /* called from the device poll routine to get ownership of a FP */
629 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
631 unsigned long prev, old = READ_ONCE(fp->busy_poll_state);
635 case BNX2X_STATE_FP_POLL:
636 /* make sure bnx2x_fp_lock_poll() wont starve us */
637 set_bit(BNX2X_STATE_FP_NAPI_REQ_BIT,
638 &fp->busy_poll_state);
640 case BNX2X_STATE_FP_POLL | BNX2X_STATE_FP_NAPI_REQ:
645 prev = cmpxchg(&fp->busy_poll_state, old, BNX2X_STATE_FP_NAPI);
646 if (unlikely(prev != old)) {
654 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
657 fp->busy_poll_state = 0;
660 /* called from bnx2x_low_latency_poll() */
661 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
663 return cmpxchg(&fp->busy_poll_state, 0, BNX2X_STATE_FP_POLL) == 0;
666 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
668 smp_mb__before_atomic();
669 clear_bit(BNX2X_STATE_FP_POLL_BIT, &fp->busy_poll_state);
672 /* true if a socket is polling */
673 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
675 return READ_ONCE(fp->busy_poll_state) & BNX2X_STATE_FP_POLL;
678 /* false if fp is currently owned */
679 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
681 set_bit(BNX2X_STATE_FP_DISABLE_BIT, &fp->busy_poll_state);
682 return !bnx2x_fp_ll_polling(fp);
686 static inline void bnx2x_fp_busy_poll_init(struct bnx2x_fastpath *fp)
690 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
695 static inline void bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
699 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
704 static inline void bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
708 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
712 static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
716 #endif /* CONFIG_NET_RX_BUSY_POLL */
718 /* Use 2500 as a mini-jumbo MTU for FCoE */
719 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
721 #define FCOE_IDX_OFFSET 0
723 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
725 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
726 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
727 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
728 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
729 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
730 txdata_ptr[FIRST_TX_COS_INDEX] \
733 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
734 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
735 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
738 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
739 #define RX_COPY_THRESH 92
741 #define NUM_TX_RINGS 16
742 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
743 #define NEXT_PAGE_TX_DESC_CNT 1
744 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
745 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
746 #define MAX_TX_BD (NUM_TX_BD - 1)
747 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
748 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
749 (MAX_TX_DESC_CNT - 1)) ? \
750 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
752 #define TX_BD(x) ((x) & MAX_TX_BD)
753 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
755 /* number of NEXT_PAGE descriptors may be required during placement */
756 #define NEXT_CNT_PER_TX_PKT(bds) \
757 (((bds) + MAX_TX_DESC_CNT - 1) / \
758 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
759 /* max BDs per tx packet w/o next_pages:
760 * START_BD - describes packed
761 * START_BD(splitted) - includes unpaged data segment for GSO
762 * PARSING_BD - for TSO and CSUM data
763 * PARSING_BD2 - for encapsulation data
764 * Frag BDs - describes pages for frags
766 #define BDS_PER_TX_PKT 4
767 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
768 /* max BDs per tx packet including next pages */
769 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
770 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
772 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
773 #define NUM_RX_RINGS 8
774 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
775 #define NEXT_PAGE_RX_DESC_CNT 2
776 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
777 #define RX_DESC_MASK (RX_DESC_CNT - 1)
778 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
779 #define MAX_RX_BD (NUM_RX_BD - 1)
780 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
782 /* dropless fc calculations for BDs
784 * Number of BDs should as number of buffers in BRB:
785 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
786 * "next" elements on each page
788 #define NUM_BD_REQ BRB_SIZE(bp)
789 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
791 #define BD_TH_LO(bp) (NUM_BD_REQ + \
792 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
794 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
796 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
798 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
799 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
800 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
801 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
802 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
803 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
806 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
807 (MAX_RX_DESC_CNT - 1)) ? \
808 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
810 #define RX_BD(x) ((x) & MAX_RX_BD)
813 * As long as CQE is X times bigger than BD entry we have to allocate X times
814 * more pages for CQ ring in order to keep it balanced with BD ring
816 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
817 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
818 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
819 #define NEXT_PAGE_RCQ_DESC_CNT 1
820 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
821 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
822 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
823 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
824 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
825 (MAX_RCQ_DESC_CNT - 1)) ? \
826 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
828 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
830 /* dropless fc calculations for RCQs
832 * Number of RCQs should be as number of buffers in BRB:
833 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
834 * "next" elements on each page
836 #define NUM_RCQ_REQ BRB_SIZE(bp)
837 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
839 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
840 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
842 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
844 /* This is needed for determining of last_max */
845 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
846 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
848 #define BNX2X_SWCID_SHIFT 17
849 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
851 /* used on a CID received from the HW */
852 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
853 #define CQE_CMD(x) (le32_to_cpu(x) >> \
854 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
856 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
857 le32_to_cpu((bd)->addr_lo))
858 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
860 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
861 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/
862 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
863 #error "Min DB doorbell stride is 8"
865 #define DOORBELL(bp, cid, val) \
867 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
870 /* TX CSUM helpers */
871 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
873 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
876 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
879 #define XMIT_CSUM_V4 (1 << 0)
880 #define XMIT_CSUM_V6 (1 << 1)
881 #define XMIT_CSUM_TCP (1 << 2)
882 #define XMIT_GSO_V4 (1 << 3)
883 #define XMIT_GSO_V6 (1 << 4)
884 #define XMIT_CSUM_ENC_V4 (1 << 5)
885 #define XMIT_CSUM_ENC_V6 (1 << 6)
886 #define XMIT_GSO_ENC_V4 (1 << 7)
887 #define XMIT_GSO_ENC_V6 (1 << 8)
889 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
890 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
892 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
893 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
895 /* stuff added to make the code fit 80Col */
896 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
897 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
898 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
899 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
900 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
902 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
904 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
905 (((le16_to_cpu(flags) & \
906 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
907 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
908 == PRS_FLAG_OVERETH_IPV4)
909 #define BNX2X_RX_SUM_FIX(cqe) \
910 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
912 #define FP_USB_FUNC_OFF \
913 offsetof(struct cstorm_status_block_u, func)
914 #define FP_CSB_FUNC_OFF \
915 offsetof(struct cstorm_status_block_c, func)
917 #define HC_INDEX_ETH_RX_CQ_CONS 1
919 #define HC_INDEX_OOO_TX_CQ_CONS 4
921 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
923 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
925 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
927 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
929 #define BNX2X_RX_SB_INDEX \
930 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
932 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
934 #define BNX2X_TX_SB_INDEX_COS0 \
935 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
937 /* end of fast path */
941 struct bnx2x_common {
944 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
945 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
947 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
948 #define CHIP_NUM_57710 0x164e
949 #define CHIP_NUM_57711 0x164f
950 #define CHIP_NUM_57711E 0x1650
951 #define CHIP_NUM_57712 0x1662
952 #define CHIP_NUM_57712_MF 0x1663
953 #define CHIP_NUM_57712_VF 0x166f
954 #define CHIP_NUM_57713 0x1651
955 #define CHIP_NUM_57713E 0x1652
956 #define CHIP_NUM_57800 0x168a
957 #define CHIP_NUM_57800_MF 0x16a5
958 #define CHIP_NUM_57800_VF 0x16a9
959 #define CHIP_NUM_57810 0x168e
960 #define CHIP_NUM_57810_MF 0x16ae
961 #define CHIP_NUM_57810_VF 0x16af
962 #define CHIP_NUM_57811 0x163d
963 #define CHIP_NUM_57811_MF 0x163e
964 #define CHIP_NUM_57811_VF 0x163f
965 #define CHIP_NUM_57840_OBSOLETE 0x168d
966 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
967 #define CHIP_NUM_57840_4_10 0x16a1
968 #define CHIP_NUM_57840_2_20 0x16a2
969 #define CHIP_NUM_57840_MF 0x16a4
970 #define CHIP_NUM_57840_VF 0x16ad
971 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
972 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
973 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
974 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
975 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
976 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
977 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
978 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
979 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
980 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
981 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
982 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
983 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
984 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
985 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
986 #define CHIP_IS_57840(bp) \
987 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
988 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
989 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
990 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
991 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
992 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
993 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
995 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
996 CHIP_IS_57811_MF(bp) || \
997 CHIP_IS_57811_VF(bp))
998 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
999 CHIP_IS_57712_MF(bp) || \
1000 CHIP_IS_57712_VF(bp))
1001 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
1002 CHIP_IS_57800_MF(bp) || \
1003 CHIP_IS_57800_VF(bp) || \
1004 CHIP_IS_57810(bp) || \
1005 CHIP_IS_57810_MF(bp) || \
1006 CHIP_IS_57810_VF(bp) || \
1007 CHIP_IS_57811xx(bp) || \
1008 CHIP_IS_57840(bp) || \
1009 CHIP_IS_57840_MF(bp) || \
1010 CHIP_IS_57840_VF(bp))
1011 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
1012 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
1013 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
1015 #define CHIP_REV_SHIFT 12
1016 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1017 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
1018 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1019 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1020 /* assume maximum 5 revisions */
1021 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
1022 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
1023 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
1024 !(CHIP_REV_VAL(bp) & 0x00001000))
1025 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
1026 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
1027 (CHIP_REV_VAL(bp) & 0x00001000))
1029 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
1030 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
1032 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
1033 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
1034 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
1035 (CHIP_REV_SHIFT + 1)) \
1037 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
1040 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
1041 (CHIP_REV(bp) == CHIP_REV_Bx))
1042 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
1043 (CHIP_REV(bp) == CHIP_REV_Ax))
1044 /* This define is used in two main places:
1045 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
1046 * to nic-only mode or to offload mode. Offload mode is configured if either the
1047 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
1048 * registered for this port (which means that the user wants storage services).
1049 * 2. During cnic-related load, to know if offload mode is already configured in
1050 * the HW or needs to be configured.
1051 * Since the transition from nic-mode to offload-mode in HW causes traffic
1052 * corruption, nic-mode is configured only in ports on which storage services
1053 * where never requested.
1055 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
1058 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
1059 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
1060 #define BNX2X_NVRAM_PAGE_SIZE 256
1072 #define INT_BLOCK_HC 0
1073 #define INT_BLOCK_IGU 1
1074 #define INT_BLOCK_MODE_NORMAL 0
1075 #define INT_BLOCK_MODE_BW_COMP 2
1076 #define CHIP_INT_MODE_IS_NBC(bp) \
1077 (!CHIP_IS_E1x(bp) && \
1078 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1079 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
1082 #define CHIP_4_PORT_MODE 0x0
1083 #define CHIP_2_PORT_MODE 0x1
1084 #define CHIP_PORT_MODE_NONE 0x2
1085 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
1086 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
1091 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
1092 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
1093 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
1095 #define MAX_IGU_ATTN_ACK_TO 100
1103 u32 link_config[LINK_CONFIG_SIZE];
1105 u32 supported[LINK_CONFIG_SIZE];
1107 u32 advertising[LINK_CONFIG_SIZE];
1111 /* used to synchronize phy accesses */
1112 struct mutex phy_mutex;
1116 struct nig_stats old_nig_stats;
1121 #define STATS_OFFSET32(stat_name) \
1122 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1125 #define BNX2X_MAX_NUM_OF_VFS 64
1126 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */
1127 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
1129 /* We need to reserve doorbell addresses for all VF and queue combinations */
1130 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1132 /* The doorbell is configured to have the same number of CIDs for PFs and for
1133 * VFs. For this reason the PF CID zone is as large as the VF zone.
1135 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1136 #define BNX2X_MAX_NUM_VF_QUEUES 64
1137 #define BNX2X_VF_ID_INVALID 0xFF
1139 /* the number of VF CIDS multiplied by the amount of bytes reserved for each
1140 * cid must not exceed the size of the VF doorbell
1142 #define BNX2X_VF_BAR_SIZE 512
1143 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1144 #error "VF doorbell bar size is 512"
1148 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1149 * control by the number of fast-path status blocks supported by the
1150 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1151 * status block represents an independent interrupts context that can
1152 * serve a regular L2 networking queue. However special L2 queues such
1153 * as the FCoE queue do not require a FP-SB and other components like
1154 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1156 * If the maximum number of FP-SB available is X then:
1157 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1158 * regular L2 queues is Y=X-1
1159 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1160 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1162 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1163 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1164 * FP interrupt context for the CNIC).
1165 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1166 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1169 /* fast-path interrupt contexts E1x */
1170 #define FP_SB_MAX_E1x 16
1171 /* fast-path interrupt contexts E2 */
1172 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1175 struct eth_context eth;
1179 /* CDU host DB constants */
1180 #define CDU_ILT_PAGE_SZ_HW 2
1181 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1182 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1184 #define CNIC_ISCSI_CID_MAX 256
1185 #define CNIC_FCOE_CID_MAX 2048
1186 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1187 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1189 #define QM_ILT_PAGE_SZ_HW 0
1190 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1191 #define QM_CID_ROUND 1024
1193 /* TM (timers) host DB constants */
1194 #define TM_ILT_PAGE_SZ_HW 0
1195 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1196 #define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
1199 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1200 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1202 /* SRC (Searcher) host DB constants */
1203 #define SRC_ILT_PAGE_SZ_HW 0
1204 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1205 #define SRC_HASH_BITS 10
1206 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1207 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1208 #define SRC_T2_SZ SRC_ILT_SZ
1209 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1211 #define MAX_DMAE_C 8
1213 /* DMA memory not used in fastpath */
1214 struct bnx2x_slowpath {
1216 struct mac_configuration_cmd e1x;
1217 struct eth_classify_rules_ramrod_data e2;
1221 struct tstorm_eth_mac_filter_config e1x;
1222 struct eth_filter_rules_ramrod_data e2;
1226 struct mac_configuration_cmd e1;
1227 struct eth_multicast_rules_ramrod_data e2;
1230 struct eth_rss_update_ramrod_data rss_rdata;
1232 /* Queue State related ramrods are always sent under rtnl_lock */
1234 struct client_init_ramrod_data init_data;
1235 struct client_update_ramrod_data update_data;
1236 struct tpa_update_ramrod_data tpa_data;
1240 struct function_start_data func_start;
1241 /* pfc configuration for DCBX ramrod */
1242 struct flow_control_configuration pfc_config;
1245 /* afex ramrod can not be a part of func_rdata union because these
1246 * events might arrive in parallel to other events from func_rdata.
1247 * Therefore, if they would have been defined in the same union,
1248 * data can get corrupted.
1251 struct afex_vif_list_ramrod_data viflist_data;
1252 struct function_update_data func_update;
1255 /* used by dmae command executer */
1256 struct dmae_command dmae[MAX_DMAE_C];
1259 union mac_stats mac_stats;
1260 struct nig_stats nig_stats;
1261 struct host_port_stats port_stats;
1262 struct host_func_stats func_stats;
1267 union drv_info_to_mcp drv_info_to_mcp;
1270 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1271 #define bnx2x_sp_mapping(bp, var) \
1272 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1274 /* attn group wiring */
1275 #define MAX_DYNAMIC_ATTN_GRPS 8
1290 union cdu_context *vcxt;
1291 dma_addr_t cxt_mapping;
1300 enum bnx2x_recovery_state {
1301 BNX2X_RECOVERY_DONE,
1302 BNX2X_RECOVERY_INIT,
1303 BNX2X_RECOVERY_WAIT,
1304 BNX2X_RECOVERY_FAILED,
1305 BNX2X_RECOVERY_NIC_LOADING
1309 * Event queue (EQ or event ring) MC hsi
1310 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1312 #define NUM_EQ_PAGES 1
1313 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1314 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1315 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1316 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1317 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1319 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1320 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1321 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1323 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1324 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1326 #define BNX2X_EQ_INDEX \
1327 (&bp->def_status_blk->sp_sb.\
1328 index_values[HC_SP_INDEX_EQ_CONS])
1330 /* This is a data that will be used to create a link report message.
1331 * We will keep the data used for the last link report in order
1332 * to prevent reporting the same link parameters twice.
1334 struct bnx2x_link_report_data {
1335 u16 line_speed; /* Effective line speed */
1336 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1340 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1341 BNX2X_LINK_REPORT_LINK_DOWN,
1342 BNX2X_LINK_REPORT_RX_FC_ON,
1343 BNX2X_LINK_REPORT_TX_FC_ON,
1347 BNX2X_PORT_QUERY_IDX,
1349 BNX2X_FCOE_QUERY_IDX,
1350 BNX2X_FIRST_QUEUE_QUERY_IDX,
1353 struct bnx2x_fw_stats_req {
1354 struct stats_query_header hdr;
1355 struct stats_query_entry query[FP_SB_MAX_E1x+
1356 BNX2X_FIRST_QUEUE_QUERY_IDX];
1359 struct bnx2x_fw_stats_data {
1360 struct stats_counter storm_counters;
1361 struct per_port_stats port;
1362 struct per_pf_stats pf;
1363 struct fcoe_statistics_params fcoe;
1364 struct per_queue_stats queue_stats[1];
1367 /* Public slow path states */
1369 BNX2X_SP_RTNL_SETUP_TC,
1370 BNX2X_SP_RTNL_TX_TIMEOUT,
1371 BNX2X_SP_RTNL_FAN_FAILURE,
1372 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1373 BNX2X_SP_RTNL_ENABLE_SRIOV,
1374 BNX2X_SP_RTNL_VFPF_MCAST,
1375 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1376 BNX2X_SP_RTNL_RX_MODE,
1377 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1378 BNX2X_SP_RTNL_TX_STOP,
1379 BNX2X_SP_RTNL_GET_DRV_VERSION,
1382 enum bnx2x_iov_flag {
1383 BNX2X_IOV_HANDLE_VF_MSG,
1384 BNX2X_IOV_HANDLE_FLR,
1387 struct bnx2x_prev_path_list {
1388 struct list_head list;
1396 struct bnx2x_sp_objs {
1398 struct bnx2x_vlan_mac_obj mac_obj;
1400 /* Queue State object */
1401 struct bnx2x_queue_sp_obj q_obj;
1404 struct bnx2x_fp_stats {
1405 struct tstorm_per_queue_stats old_tclient;
1406 struct ustorm_per_queue_stats old_uclient;
1407 struct xstorm_per_queue_stats old_xclient;
1408 struct bnx2x_eth_q_stats eth_q_stats;
1409 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1413 SUB_MF_MODE_UNKNOWN = 0,
1415 SUB_MF_MODE_NPAR1_DOT_5,
1419 /* Fields used in the tx and intr/napi performance paths
1420 * are grouped together in the beginning of the structure
1422 struct bnx2x_fastpath *fp;
1423 struct bnx2x_sp_objs *sp_objs;
1424 struct bnx2x_fp_stats *fp_stats;
1425 struct bnx2x_fp_txdata *bnx2x_txq;
1426 void __iomem *regview;
1427 void __iomem *doorbells;
1430 u8 pf_num; /* absolute PF number */
1431 u8 pfid; /* per-path PF number */
1432 int base_fw_ndsb; /**/
1433 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1434 #define BP_PORT(bp) (bp->pfid & 1)
1435 #define BP_FUNC(bp) (bp->pfid)
1436 #define BP_ABS_FUNC(bp) (bp->pf_num)
1437 #define BP_VN(bp) ((bp)->pfid >> 1)
1438 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1439 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1440 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1441 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1442 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1444 #ifdef CONFIG_BNX2X_SRIOV
1445 /* protects vf2pf mailbox from simultaneous access */
1446 struct mutex vf2pf_mutex;
1447 /* vf pf channel mailbox contains request and response buffers */
1448 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1449 dma_addr_t vf2pf_mbox_mapping;
1451 /* we set aside a copy of the acquire response */
1452 struct pfvf_acquire_resp_tlv acquire_resp;
1454 /* bulletin board for messages from pf to vf */
1455 union pf_vf_bulletin *pf2vf_bulletin;
1456 dma_addr_t pf2vf_bulletin_mapping;
1458 union pf_vf_bulletin shadow_bulletin;
1459 struct pf_vf_bulletin_content old_bulletin;
1461 u16 requested_nr_virtfn;
1462 #endif /* CONFIG_BNX2X_SRIOV */
1464 struct net_device *dev;
1465 struct pci_dev *pdev;
1467 const struct iro *iro_arr;
1468 #define IRO (bp->iro_arr)
1470 enum bnx2x_recovery_state recovery_state;
1472 struct msix_entry *msix_table;
1476 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1477 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1478 #define ETH_MIN_PACKET_SIZE 60
1479 #define ETH_MAX_PACKET_SIZE 1500
1480 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1481 /* TCP with Timestamp Option (32) + IPv6 (40) */
1482 #define ETH_MAX_TPA_HEADER_SIZE 72
1484 /* Max supported alignment is 256 (8 shift)
1485 * minimal alignment shift 6 is optimal for 57xxx HW performance
1487 #define BNX2X_RX_ALIGN_SHIFT max(6, min(8, L1_CACHE_SHIFT))
1489 /* FW uses 2 Cache lines Alignment for start packet and size
1491 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1492 * at the end of skb->data, to avoid wasting a full cache line.
1493 * This reduces memory use (skb->truesize).
1495 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1497 #define BNX2X_FW_RX_ALIGN_END \
1498 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1499 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1501 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1503 struct host_sp_status_block *def_status_blk;
1504 #define DEF_SB_IGU_ID 16
1505 #define DEF_SB_ID HC_SP_SB_ID
1509 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1511 /* slow path ring */
1512 struct eth_spe *spq;
1513 dma_addr_t spq_mapping;
1515 struct eth_spe *spq_prod_bd;
1516 struct eth_spe *spq_last_bd;
1517 __le16 *dsb_sp_prod;
1518 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1519 /* used to synchronize spq accesses */
1520 spinlock_t spq_lock;
1523 union event_ring_elem *eq_ring;
1524 dma_addr_t eq_mapping;
1528 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1530 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1532 /* Counter for completed statistics ramrods */
1535 /* End of fields used in the performance code paths */
1541 #define PCIX_FLAG (1 << 0)
1542 #define PCI_32BIT_FLAG (1 << 1)
1543 #define ONE_PORT_FLAG (1 << 2)
1544 #define NO_WOL_FLAG (1 << 3)
1545 #define USING_MSIX_FLAG (1 << 5)
1546 #define USING_MSI_FLAG (1 << 6)
1547 #define DISABLE_MSI_FLAG (1 << 7)
1548 #define TPA_ENABLE_FLAG (1 << 8)
1549 #define NO_MCP_FLAG (1 << 9)
1550 #define GRO_ENABLE_FLAG (1 << 10)
1551 #define MF_FUNC_DIS (1 << 11)
1552 #define OWN_CNIC_IRQ (1 << 12)
1553 #define NO_ISCSI_OOO_FLAG (1 << 13)
1554 #define NO_ISCSI_FLAG (1 << 14)
1555 #define NO_FCOE_FLAG (1 << 15)
1556 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1557 #define TX_SWITCHING (1 << 18)
1558 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1559 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1560 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1561 #define IS_VF_FLAG (1 << 22)
1562 #define BC_SUPPORTS_RMMOD_CMD (1 << 23)
1563 #define HAS_PHYS_PORT_ID (1 << 24)
1564 #define AER_ENABLED (1 << 25)
1565 #define PTP_SUPPORTED (1 << 26)
1566 #define TX_TIMESTAMPING_EN (1 << 27)
1568 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1570 #ifdef CONFIG_BNX2X_SRIOV
1571 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1572 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1574 #define IS_VF(bp) false
1575 #define IS_PF(bp) true
1578 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1579 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1580 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1585 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1587 /* Flag that indicates that we can start looking for FCoE L2 queue
1588 * completions in the default status block.
1594 struct delayed_work sp_task;
1595 struct delayed_work iov_task;
1597 atomic_t interrupt_occurred;
1598 struct delayed_work sp_rtnl_task;
1600 struct delayed_work period_task;
1601 struct timer_list timer;
1602 int current_interval;
1605 u16 fw_drv_pulse_wr_seq;
1608 struct link_params link_params;
1609 struct link_vars link_vars;
1611 struct bnx2x_link_report_data last_reported_link;
1613 struct mdio_if_info mdio;
1615 struct bnx2x_common common;
1616 struct bnx2x_port port;
1618 struct cmng_init cmng;
1620 u32 mf_config[E1HVN_MAX];
1622 u32 path_has_ovlan; /* E3 */
1625 #define IS_MF(bp) (bp->mf_mode != 0)
1626 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1627 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1628 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1630 #define IS_MF_UFP(bp) (IS_MF_SD(bp) && \
1631 bp->mf_sub_mode == SUB_MF_MODE_UFP)
1637 u16 tx_quick_cons_trip_int;
1638 u16 tx_quick_cons_trip;
1642 u16 rx_quick_cons_trip_int;
1643 u16 rx_quick_cons_trip;
1646 /* Maximal coalescing timeout in us */
1647 #define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
1652 #define BNX2X_STATE_CLOSED 0
1653 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1654 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1655 #define BNX2X_STATE_OPEN 0x3000
1656 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1657 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1659 #define BNX2X_STATE_DIAG 0xe000
1660 #define BNX2X_STATE_ERROR 0xf000
1662 #define BNX2X_MAX_PRIORITY 8
1664 uint num_ethernet_queues;
1665 uint num_cnic_queues;
1669 #define BNX2X_RX_MODE_NONE 0
1670 #define BNX2X_RX_MODE_NORMAL 1
1671 #define BNX2X_RX_MODE_ALLMULTI 2
1672 #define BNX2X_RX_MODE_PROMISC 3
1673 #define BNX2X_MAX_MULTICAST 64
1678 u8 min_msix_vec_cnt;
1681 dma_addr_t def_status_blk_mapping;
1683 struct bnx2x_slowpath *slowpath;
1684 dma_addr_t slowpath_mapping;
1686 /* Mechanism protecting the drv_info_to_mcp */
1687 struct mutex drv_info_mutex;
1688 bool drv_info_mng_owner;
1690 /* Total number of FW statistics requests */
1694 * This is a memory buffer that will contain both statistics
1695 * ramrod request and data.
1698 dma_addr_t fw_stats_mapping;
1701 * FW statistics request shortcut (points at the
1702 * beginning of fw_stats buffer).
1704 struct bnx2x_fw_stats_req *fw_stats_req;
1705 dma_addr_t fw_stats_req_mapping;
1706 int fw_stats_req_sz;
1709 * FW statistics data shortcut (points at the beginning of
1710 * fw_stats buffer + fw_stats_req_sz).
1712 struct bnx2x_fw_stats_data *fw_stats_data;
1713 dma_addr_t fw_stats_data_mapping;
1714 int fw_stats_data_sz;
1716 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1717 * context size we need 8 ILT entries.
1719 #define ILT_MAX_L2_LINES 32
1720 struct hw_context context[ILT_MAX_L2_LINES];
1722 struct bnx2x_ilt *ilt;
1723 #define BP_ILT(bp) ((bp)->ilt)
1724 #define ILT_MAX_LINES 256
1726 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1729 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1732 * Maximum CID count that might be required by the bnx2x:
1733 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1736 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1737 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1738 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1739 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1740 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1748 dma_addr_t t2_mapping;
1749 struct cnic_ops __rcu *cnic_ops;
1752 struct cnic_eth_dev cnic_eth_dev;
1753 union host_hc_status_block cnic_sb;
1754 dma_addr_t cnic_sb_mapping;
1755 struct eth_spe *cnic_kwq;
1756 struct eth_spe *cnic_kwq_prod;
1757 struct eth_spe *cnic_kwq_cons;
1758 struct eth_spe *cnic_kwq_last;
1759 u16 cnic_kwq_pending;
1760 u16 cnic_spq_pending;
1761 u8 fip_mac[ETH_ALEN];
1762 struct mutex cnic_mutex;
1763 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1765 /* Start index of the "special" (CNIC related) L2 clients */
1769 /* used to synchronize dmae accesses */
1770 spinlock_t dmae_lock;
1772 /* used to protect the FW mail box */
1773 struct mutex fw_mb_mutex;
1775 /* used to synchronize stats collecting */
1778 /* used for synchronization of concurrent threads statistics handling */
1779 struct mutex stats_lock;
1781 /* used by dmae command loader */
1782 struct dmae_command stats_dmae;
1786 struct bnx2x_eth_stats eth_stats;
1787 struct host_func_stats func_stats;
1788 struct bnx2x_eth_stats_old eth_stats_old;
1789 struct bnx2x_net_stats_old net_stats_old;
1790 struct bnx2x_fw_port_stats_old fw_stats_old;
1793 struct z_stream_s *strm;
1795 dma_addr_t gunzip_mapping;
1797 #define FW_BUF_SIZE 0x8000
1798 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1799 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1800 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1802 struct raw_op *init_ops;
1803 /* Init blocks offsets inside init_ops */
1804 u16 *init_ops_offsets;
1805 /* Data blob - has 32 bit granularity */
1807 u32 init_mode_flags;
1808 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1809 /* Zipped PRAM blobs - raw data */
1810 const u8 *tsem_int_table_data;
1811 const u8 *tsem_pram_data;
1812 const u8 *usem_int_table_data;
1813 const u8 *usem_pram_data;
1814 const u8 *xsem_int_table_data;
1815 const u8 *xsem_pram_data;
1816 const u8 *csem_int_table_data;
1817 const u8 *csem_pram_data;
1818 #define INIT_OPS(bp) (bp->init_ops)
1819 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1820 #define INIT_DATA(bp) (bp->init_data)
1821 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1822 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1823 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1824 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1825 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1826 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1827 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1828 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1830 #define PHY_FW_VER_LEN 20
1832 const struct firmware *firmware;
1834 struct bnx2x_vfdb *vfdb;
1835 #define IS_SRIOV(bp) ((bp)->vfdb)
1837 /* DCB support on/off */
1839 #define BNX2X_DCB_STATE_OFF 0
1840 #define BNX2X_DCB_STATE_ON 1
1842 /* DCBX engine mode */
1844 #define BNX2X_DCBX_ENABLED_OFF 0
1845 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1846 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1847 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1849 bool dcbx_mode_uset;
1851 struct bnx2x_config_dcbx_params dcbx_config_params;
1852 struct bnx2x_dcbx_port_params dcbx_port_params;
1855 /* CAM credit pools */
1857 /* used only in sriov */
1858 struct bnx2x_credit_pool_obj vlans_pool;
1860 struct bnx2x_credit_pool_obj macs_pool;
1862 /* RX_MODE object */
1863 struct bnx2x_rx_mode_obj rx_mode_obj;
1866 struct bnx2x_mcast_obj mcast_obj;
1868 /* RSS configuration object */
1869 struct bnx2x_rss_config_obj rss_conf_obj;
1871 /* Function State controlling object */
1872 struct bnx2x_func_sp_obj func_obj;
1874 unsigned long sp_state;
1876 /* operation indication for the sp_rtnl task */
1877 unsigned long sp_rtnl_state;
1879 /* Indication of the IOV tasks */
1880 unsigned long iov_task_state;
1882 /* DCBX Negotiation results */
1883 struct dcbx_features dcbx_local_feat;
1887 struct dcbx_features dcbx_remote_feat;
1888 u32 dcbx_remote_flags;
1890 /* AFEX: store default vlan used */
1891 int afex_def_vlan_tag;
1892 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1895 /* multiple tx classes of service */
1898 /* priority to cos mapping */
1902 u32 dump_preset_idx;
1904 u8 phys_port_id[ETH_ALEN];
1906 /* PTP related context */
1907 struct ptp_clock *ptp_clock;
1908 struct ptp_clock_info ptp_clock_info;
1909 struct work_struct ptp_task;
1910 struct cyclecounter cyclecounter;
1911 struct timecounter timecounter;
1912 bool timecounter_init_done;
1913 struct sk_buff *ptp_tx_skb;
1914 unsigned long ptp_tx_start;
1915 bool hwtstamp_ioctl_called;
1919 struct bnx2x_link_report_data vf_link_vars;
1922 /* Tx queues may be less or equal to Rx queues */
1923 extern int num_queues;
1924 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1925 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1926 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1927 (bp)->num_cnic_queues)
1928 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1930 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1932 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1933 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1935 #define RSS_IPV4_CAP_MASK \
1936 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1938 #define RSS_IPV4_TCP_CAP_MASK \
1939 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1941 #define RSS_IPV6_CAP_MASK \
1942 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1944 #define RSS_IPV6_TCP_CAP_MASK \
1945 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1947 /* func init flags */
1948 #define FUNC_FLG_RSS 0x0001
1949 #define FUNC_FLG_STATS 0x0002
1950 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1951 #define FUNC_FLG_TPA 0x0008
1952 #define FUNC_FLG_SPQ 0x0010
1953 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1954 #define FUNC_FLG_LEADING_STATS 0x0040
1955 struct bnx2x_func_init_params {
1957 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1958 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1961 u16 func_id; /* abs fid */
1963 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1966 #define for_each_cnic_queue(bp, var) \
1967 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1969 if (skip_queue(bp, var)) \
1973 #define for_each_eth_queue(bp, var) \
1974 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1976 #define for_each_nondefault_eth_queue(bp, var) \
1977 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1979 #define for_each_queue(bp, var) \
1980 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1981 if (skip_queue(bp, var)) \
1985 /* Skip forwarding FP */
1986 #define for_each_valid_rx_queue(bp, var) \
1988 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1989 BNX2X_NUM_ETH_QUEUES(bp)); \
1991 if (skip_rx_queue(bp, var)) \
1995 #define for_each_rx_queue_cnic(bp, var) \
1996 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1998 if (skip_rx_queue(bp, var)) \
2002 #define for_each_rx_queue(bp, var) \
2003 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2004 if (skip_rx_queue(bp, var)) \
2009 #define for_each_valid_tx_queue(bp, var) \
2011 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
2012 BNX2X_NUM_ETH_QUEUES(bp)); \
2014 if (skip_tx_queue(bp, var)) \
2018 #define for_each_tx_queue_cnic(bp, var) \
2019 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2021 if (skip_tx_queue(bp, var)) \
2025 #define for_each_tx_queue(bp, var) \
2026 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2027 if (skip_tx_queue(bp, var)) \
2031 #define for_each_nondefault_queue(bp, var) \
2032 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2033 if (skip_queue(bp, var)) \
2037 #define for_each_cos_in_tx_queue(fp, var) \
2038 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
2041 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2043 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2046 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2048 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2050 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
2053 * bnx2x_set_mac_one - configure a single MAC address
2055 * @bp: driver handle
2056 * @mac: MAC to configure
2057 * @obj: MAC object handle
2058 * @set: if 'true' add a new MAC, otherwise - delete
2059 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
2060 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
2062 * Configures one MAC according to provided parameters or continues the
2063 * execution of previously scheduled commands if RAMROD_CONT is set in
2066 * Returns zero if operation has successfully completed, a positive value if the
2067 * operation has been successfully scheduled and a negative - if a requested
2068 * operations has failed.
2070 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
2071 struct bnx2x_vlan_mac_obj *obj, bool set,
2072 int mac_type, unsigned long *ramrod_flags);
2074 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2076 * @bp: driver handle
2077 * @mac_obj: MAC object handle
2078 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
2079 * @wait_for_comp: if 'true' block until completion
2081 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2083 * Returns zero if operation has successfully completed, a positive value if the
2084 * operation has been successfully scheduled and a negative - if a requested
2085 * operations has failed.
2087 int bnx2x_del_all_macs(struct bnx2x *bp,
2088 struct bnx2x_vlan_mac_obj *mac_obj,
2089 int mac_type, bool wait_for_comp);
2091 /* Init Function API */
2092 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2093 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2094 u8 vf_valid, int fw_sb_id, int igu_sb_id);
2095 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2096 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2097 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2098 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2099 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2101 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2104 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2105 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2107 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2108 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2109 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2110 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2111 bool with_comp, u8 comp_type);
2113 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2114 u8 src_type, u8 dst_type);
2115 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2118 /* FLR related routines */
2119 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2120 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2121 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2122 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2123 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2124 char *msg, u32 poll_cnt);
2126 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2127 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2128 u32 data_hi, u32 data_lo, int cmd_type);
2129 void bnx2x_update_coalesce(struct bnx2x *bp);
2130 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2132 bool bnx2x_port_after_undi(struct bnx2x *bp);
2134 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2140 val = REG_RD(bp, reg);
2141 if (val == expected)
2151 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2154 #define BNX2X_ILT_ZALLOC(x, y, size) \
2155 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2157 #define BNX2X_ILT_FREE(x, y, size) \
2160 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2166 #define ILOG2(x) (ilog2((x)))
2168 #define ILT_NUM_PAGE_ENTRIES (3072)
2169 /* In 57710/11 we use whole table since we have 8 func
2170 * In 57712 we have only 4 func, but use same size per func, then only half of
2173 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2175 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2177 * the phys address is shifted right 12 bits and has an added
2178 * 1=valid bit added to the 53rd bit
2179 * then since this is a wide register(TM)
2180 * we split it into two 32 bit writes
2182 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2183 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
2185 /* load/unload mode */
2186 #define LOAD_NORMAL 0
2189 #define LOAD_LOOPBACK_EXT 3
2190 #define UNLOAD_NORMAL 0
2191 #define UNLOAD_CLOSE 1
2192 #define UNLOAD_RECOVERY 2
2194 /* DMAE command defines */
2195 #define DMAE_TIMEOUT -1
2196 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2197 #define DMAE_NOT_RDY -3
2198 #define DMAE_PCI_ERR_FLAG 0x80000000
2200 #define DMAE_SRC_PCI 0
2201 #define DMAE_SRC_GRC 1
2203 #define DMAE_DST_NONE 0
2204 #define DMAE_DST_PCI 1
2205 #define DMAE_DST_GRC 2
2207 #define DMAE_COMP_PCI 0
2208 #define DMAE_COMP_GRC 1
2210 /* E2 and onward - PCI error handling in the completion */
2212 #define DMAE_COMP_REGULAR 0
2213 #define DMAE_COM_SET_ERR 1
2215 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2216 DMAE_COMMAND_SRC_SHIFT)
2217 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2218 DMAE_COMMAND_SRC_SHIFT)
2220 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2221 DMAE_COMMAND_DST_SHIFT)
2222 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2223 DMAE_COMMAND_DST_SHIFT)
2225 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2226 DMAE_COMMAND_C_DST_SHIFT)
2227 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2228 DMAE_COMMAND_C_DST_SHIFT)
2230 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2232 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2233 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2234 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2235 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2237 #define DMAE_CMD_PORT_0 0
2238 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2240 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2241 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2242 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2244 #define DMAE_SRC_PF 0
2245 #define DMAE_SRC_VF 1
2247 #define DMAE_DST_PF 0
2248 #define DMAE_DST_VF 1
2250 #define DMAE_C_SRC 0
2251 #define DMAE_C_DST 1
2253 #define DMAE_LEN32_RD_MAX 0x80
2254 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2256 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2260 #define MAX_DMAE_C_PER_PORT 8
2261 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2263 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2266 /* PCIE link and speed */
2267 #define PCICFG_LINK_WIDTH 0x1f00000
2268 #define PCICFG_LINK_WIDTH_SHIFT 20
2269 #define PCICFG_LINK_SPEED 0xf0000
2270 #define PCICFG_LINK_SPEED_SHIFT 16
2272 #define BNX2X_NUM_TESTS_SF 7
2273 #define BNX2X_NUM_TESTS_MF 3
2274 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2275 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2277 #define BNX2X_PHY_LOOPBACK 0
2278 #define BNX2X_MAC_LOOPBACK 1
2279 #define BNX2X_EXT_LOOPBACK 2
2280 #define BNX2X_PHY_LOOPBACK_FAILED 1
2281 #define BNX2X_MAC_LOOPBACK_FAILED 2
2282 #define BNX2X_EXT_LOOPBACK_FAILED 3
2283 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2284 BNX2X_PHY_LOOPBACK_FAILED)
2286 #define STROM_ASSERT_ARRAY_SIZE 50
2288 /* must be used on a CID before placing it on a HW ring */
2289 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2290 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2293 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2294 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2297 #define MAX_SPQ_PENDING 8
2299 /* CMNG constants, as derived from system spec calculations */
2300 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2301 #define DEF_MIN_RATE 100
2302 /* resolution of the rate shaping timer - 400 usec */
2303 #define RS_PERIODIC_TIMEOUT_USEC 400
2304 /* number of bytes in single QM arbitration cycle -
2305 * coefficient for calculating the fairness timer */
2306 #define QM_ARB_BYTES 160000
2307 /* resolution of Min algorithm 1:100 */
2309 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2310 #define MIN_ABOVE_THRESH 32768
2311 /* Fairness algorithm integration time coefficient -
2312 * for calculating the actual Tfair */
2313 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2314 /* Memory of fairness algorithm . 2 cycles */
2317 #define ATTN_NIG_FOR_FUNC (1L << 8)
2318 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2319 #define GPIO_2_FUNC (1L << 10)
2320 #define GPIO_3_FUNC (1L << 11)
2321 #define GPIO_4_FUNC (1L << 12)
2322 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2323 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2324 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2325 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2326 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2327 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2329 #define ATTN_HARD_WIRED_MASK 0xff00
2330 #define ATTENTION_ID 4
2332 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_PERSONALITY_ONLY(bp) || \
2333 IS_MF_FCOE_AFEX(bp))
2335 /* stuff added to make the code fit 80Col */
2337 #define BNX2X_PMF_LINK_ASSERT \
2338 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2340 #define BNX2X_MC_ASSERT_BITS \
2341 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2342 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2343 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2344 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2346 #define BNX2X_MCP_ASSERT \
2347 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2349 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2350 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2351 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2352 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2353 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2354 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2355 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2357 #define HW_INTERRUT_ASSERT_SET_0 \
2358 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2359 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2360 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2361 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2362 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2363 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2364 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2365 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2366 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2367 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2368 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2369 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2370 #define HW_INTERRUT_ASSERT_SET_1 \
2371 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2372 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2373 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2374 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2375 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2376 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2377 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2378 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2379 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2380 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2381 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2382 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2383 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2384 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2385 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2386 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2387 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2388 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2389 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2390 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2391 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2392 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2393 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2394 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2395 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2396 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2397 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2398 #define HW_INTERRUT_ASSERT_SET_2 \
2399 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2400 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2401 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2402 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2403 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2404 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2405 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2406 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2407 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2408 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2409 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2410 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2411 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2413 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2414 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2415 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2416 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2418 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2419 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2421 #define MULTI_MASK 0x7f
2423 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2424 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2425 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2426 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2428 #define DEF_USB_IGU_INDEX_OFF \
2429 offsetof(struct cstorm_def_status_block_u, igu_index)
2430 #define DEF_CSB_IGU_INDEX_OFF \
2431 offsetof(struct cstorm_def_status_block_c, igu_index)
2432 #define DEF_XSB_IGU_INDEX_OFF \
2433 offsetof(struct xstorm_def_status_block, igu_index)
2434 #define DEF_TSB_IGU_INDEX_OFF \
2435 offsetof(struct tstorm_def_status_block, igu_index)
2437 #define DEF_USB_SEGMENT_OFF \
2438 offsetof(struct cstorm_def_status_block_u, segment)
2439 #define DEF_CSB_SEGMENT_OFF \
2440 offsetof(struct cstorm_def_status_block_c, segment)
2441 #define DEF_XSB_SEGMENT_OFF \
2442 offsetof(struct xstorm_def_status_block, segment)
2443 #define DEF_TSB_SEGMENT_OFF \
2444 offsetof(struct tstorm_def_status_block, segment)
2446 #define BNX2X_SP_DSB_INDEX \
2447 (&bp->def_status_blk->sp_sb.\
2448 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2450 #define CAM_IS_INVALID(x) \
2451 (GET_FLAG(x.flags, \
2452 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2453 (T_ETH_MAC_COMMAND_INVALIDATE))
2455 /* Number of u32 elements in MC hash array */
2456 #define MC_HASH_SIZE 8
2457 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2458 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2460 #ifndef PXP2_REG_PXP2_INT_STS
2461 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2464 #ifndef ETH_MAX_RX_CLIENTS_E2
2465 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2468 #define BNX2X_VPD_LEN 128
2469 #define VENDOR_ID_LEN 4
2471 #define VF_ACQUIRE_THRESH 3
2472 #define VF_ACQUIRE_MAC_FILTERS 1
2473 #define VF_ACQUIRE_MC_FILTERS 10
2475 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2476 (!((me_reg) & ME_REG_VF_ERR)))
2477 int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2479 /* Congestion management fairness mode */
2480 #define CMNG_FNS_NONE 0
2481 #define CMNG_FNS_MINMAX 1
2483 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2484 #define HC_SEG_ACCESS_ATTN 4
2485 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2487 static const u32 dmae_reg_go_c[] = {
2488 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2489 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2490 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2491 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2494 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2495 void bnx2x_notify_link_changed(struct bnx2x *bp);
2497 #define BNX2X_MF_SD_PROTOCOL(bp) \
2498 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2500 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2501 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2503 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2504 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2506 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2507 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2508 #define IS_MF_ISCSI_SI(bp) (IS_MF_SI(bp) && BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp))
2510 #define IS_MF_ISCSI_ONLY(bp) (IS_MF_ISCSI_SD(bp) || IS_MF_ISCSI_SI(bp))
2512 #define BNX2X_MF_EXT_PROTOCOL_MASK \
2513 (MACP_FUNC_CFG_FLAGS_ETHERNET | \
2514 MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD | \
2515 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2517 #define BNX2X_MF_EXT_PROT(bp) ((bp)->mf_ext_config & \
2518 BNX2X_MF_EXT_PROTOCOL_MASK)
2520 #define BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp) \
2521 (BNX2X_MF_EXT_PROT(bp) & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2523 #define BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp) \
2524 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2526 #define BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) \
2527 (BNX2X_MF_EXT_PROT(bp) == MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD)
2529 #define IS_MF_FCOE_AFEX(bp) \
2530 (IS_MF_AFEX(bp) && BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp))
2532 #define IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) \
2534 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2535 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2537 #define IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp) \
2539 (BNX2X_IS_MF_EXT_PROTOCOL_ISCSI(bp) || \
2540 BNX2X_IS_MF_EXT_PROTOCOL_FCOE(bp)))
2542 #define IS_MF_STORAGE_PERSONALITY_ONLY(bp) \
2543 (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp) || \
2544 IS_MF_SI_STORAGE_PERSONALITY_ONLY(bp))
2547 #define SET_FLAG(value, mask, flag) \
2549 (value) &= ~(mask);\
2550 (value) |= ((flag) << (mask##_SHIFT));\
2553 #define GET_FLAG(value, mask) \
2554 (((value) & (mask)) >> (mask##_SHIFT))
2556 #define GET_FIELD(value, fname) \
2557 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2566 void bnx2x_set_local_cmng(struct bnx2x *bp);
2568 void bnx2x_update_mng_version(struct bnx2x *bp);
2570 #define MCPR_SCRATCH_BASE(bp) \
2571 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2573 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2575 void bnx2x_init_ptp(struct bnx2x *bp);
2576 int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2577 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
2579 #define BNX2X_MAX_PHC_DRIFT 31000000
2580 #define BNX2X_PTP_TX_TIMEOUT
2582 #endif /* bnx2x.h */