1 /* Applied Micro X-Gene SoC Ethernet Driver
3 * Copyright (c) 2014, Applied Micro Circuits Corporation
4 * Authors: Iyappan Subramanian <isubramanian@apm.com>
5 * Ravi Patel <rapatel@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "xgene_enet_main.h"
23 #include "xgene_enet_hw.h"
25 static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
27 u32 *ring_cfg = ring->state;
29 enum xgene_enet_ring_cfgsize cfgsize = ring->cfgsize;
31 ring_cfg[4] |= (1 << SELTHRSH_POS) &
32 CREATE_MASK(SELTHRSH_POS, SELTHRSH_LEN);
33 ring_cfg[3] |= ACCEPTLERR;
34 ring_cfg[2] |= QCOHERENT;
37 ring_cfg[2] |= (addr << RINGADDRL_POS) &
38 CREATE_MASK_ULL(RINGADDRL_POS, RINGADDRL_LEN);
39 addr >>= RINGADDRL_LEN;
40 ring_cfg[3] |= addr & CREATE_MASK_ULL(RINGADDRH_POS, RINGADDRH_LEN);
41 ring_cfg[3] |= ((u32)cfgsize << RINGSIZE_POS) &
42 CREATE_MASK(RINGSIZE_POS, RINGSIZE_LEN);
45 static void xgene_enet_ring_set_type(struct xgene_enet_desc_ring *ring)
47 u32 *ring_cfg = ring->state;
51 is_bufpool = xgene_enet_is_bufpool(ring->id);
52 val = (is_bufpool) ? RING_BUFPOOL : RING_REGULAR;
53 ring_cfg[4] |= (val << RINGTYPE_POS) &
54 CREATE_MASK(RINGTYPE_POS, RINGTYPE_LEN);
57 ring_cfg[3] |= (BUFPOOL_MODE << RINGMODE_POS) &
58 CREATE_MASK(RINGMODE_POS, RINGMODE_LEN);
62 static void xgene_enet_ring_set_recombbuf(struct xgene_enet_desc_ring *ring)
64 u32 *ring_cfg = ring->state;
66 ring_cfg[3] |= RECOMBBUF;
67 ring_cfg[3] |= (0xf << RECOMTIMEOUTL_POS) &
68 CREATE_MASK(RECOMTIMEOUTL_POS, RECOMTIMEOUTL_LEN);
69 ring_cfg[4] |= 0x7 & CREATE_MASK(RECOMTIMEOUTH_POS, RECOMTIMEOUTH_LEN);
72 static void xgene_enet_ring_wr32(struct xgene_enet_desc_ring *ring,
75 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
77 iowrite32(data, pdata->ring_csr_addr + offset);
80 static void xgene_enet_ring_rd32(struct xgene_enet_desc_ring *ring,
81 u32 offset, u32 *data)
83 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
85 *data = ioread32(pdata->ring_csr_addr + offset);
88 static void xgene_enet_write_ring_state(struct xgene_enet_desc_ring *ring)
92 xgene_enet_ring_wr32(ring, CSR_RING_CONFIG, ring->num);
93 for (i = 0; i < NUM_RING_CONFIG; i++) {
94 xgene_enet_ring_wr32(ring, CSR_RING_WR_BASE + (i * 4),
99 static void xgene_enet_clr_ring_state(struct xgene_enet_desc_ring *ring)
101 memset(ring->state, 0, sizeof(u32) * NUM_RING_CONFIG);
102 xgene_enet_write_ring_state(ring);
105 static void xgene_enet_set_ring_state(struct xgene_enet_desc_ring *ring)
107 xgene_enet_ring_set_type(ring);
109 if (xgene_enet_ring_owner(ring->id) == RING_OWNER_ETH0)
110 xgene_enet_ring_set_recombbuf(ring);
112 xgene_enet_ring_init(ring);
113 xgene_enet_write_ring_state(ring);
116 static void xgene_enet_set_ring_id(struct xgene_enet_desc_ring *ring)
118 u32 ring_id_val, ring_id_buf;
121 is_bufpool = xgene_enet_is_bufpool(ring->id);
123 ring_id_val = ring->id & GENMASK(9, 0);
124 ring_id_val |= OVERWRITE;
126 ring_id_buf = (ring->num << 9) & GENMASK(18, 9);
127 ring_id_buf |= PREFETCH_BUF_EN;
129 ring_id_buf |= IS_BUFFER_POOL;
131 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id_val);
132 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, ring_id_buf);
135 static void xgene_enet_clr_desc_ring_id(struct xgene_enet_desc_ring *ring)
139 ring_id = ring->id | OVERWRITE;
140 xgene_enet_ring_wr32(ring, CSR_RING_ID, ring_id);
141 xgene_enet_ring_wr32(ring, CSR_RING_ID_BUF, 0);
144 struct xgene_enet_desc_ring *xgene_enet_setup_ring(
145 struct xgene_enet_desc_ring *ring)
147 u32 size = ring->size;
151 xgene_enet_clr_ring_state(ring);
152 xgene_enet_set_ring_state(ring);
153 xgene_enet_set_ring_id(ring);
155 ring->slots = xgene_enet_get_numslots(ring->id, size);
157 is_bufpool = xgene_enet_is_bufpool(ring->id);
158 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
161 for (i = 0; i < ring->slots; i++)
162 xgene_enet_mark_desc_slot_empty(&ring->raw_desc[i]);
164 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
165 data |= BIT(31 - xgene_enet_ring_bufnum(ring->id));
166 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
171 void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring)
176 is_bufpool = xgene_enet_is_bufpool(ring->id);
177 if (is_bufpool || xgene_enet_ring_owner(ring->id) != RING_OWNER_CPU)
180 xgene_enet_ring_rd32(ring, CSR_RING_NE_INT_MODE, &data);
181 data &= ~BIT(31 - xgene_enet_ring_bufnum(ring->id));
182 xgene_enet_ring_wr32(ring, CSR_RING_NE_INT_MODE, data);
185 xgene_enet_clr_desc_ring_id(ring);
186 xgene_enet_clr_ring_state(ring);
189 void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
190 struct xgene_enet_pdata *pdata,
191 enum xgene_enet_err_code status)
193 struct rtnl_link_stats64 *stats = &pdata->stats;
197 stats->rx_crc_errors++;
199 case INGRESS_CHECKSUM:
200 case INGRESS_CHECKSUM_COMPUTE:
203 case INGRESS_TRUNC_FRAME:
204 stats->rx_frame_errors++;
206 case INGRESS_PKT_LEN:
207 stats->rx_length_errors++;
209 case INGRESS_PKT_UNDER:
210 stats->rx_frame_errors++;
212 case INGRESS_FIFO_OVERRUN:
213 stats->rx_fifo_errors++;
220 static void xgene_enet_wr_csr(struct xgene_enet_pdata *pdata,
223 void __iomem *addr = pdata->eth_csr_addr + offset;
225 iowrite32(val, addr);
228 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *pdata,
231 void __iomem *addr = pdata->eth_ring_if_addr + offset;
233 iowrite32(val, addr);
236 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *pdata,
239 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
241 iowrite32(val, addr);
244 static void xgene_enet_wr_mcx_csr(struct xgene_enet_pdata *pdata,
247 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
249 iowrite32(val, addr);
252 static bool xgene_enet_wr_indirect(void __iomem *addr, void __iomem *wr,
253 void __iomem *cmd, void __iomem *cmd_done,
254 u32 wr_addr, u32 wr_data)
259 iowrite32(wr_addr, addr);
260 iowrite32(wr_data, wr);
261 iowrite32(XGENE_ENET_WR_CMD, cmd);
263 /* wait for write command to complete */
264 while (!(done = ioread32(cmd_done)) && wait--)
275 static void xgene_enet_wr_mcx_mac(struct xgene_enet_pdata *pdata,
276 u32 wr_addr, u32 wr_data)
278 void __iomem *addr, *wr, *cmd, *cmd_done;
280 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
281 wr = pdata->mcx_mac_addr + MAC_WRITE_REG_OFFSET;
282 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
283 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
285 if (!xgene_enet_wr_indirect(addr, wr, cmd, cmd_done, wr_addr, wr_data))
286 netdev_err(pdata->ndev, "MCX mac write failed, addr: %04x\n",
290 static void xgene_enet_rd_csr(struct xgene_enet_pdata *pdata,
291 u32 offset, u32 *val)
293 void __iomem *addr = pdata->eth_csr_addr + offset;
295 *val = ioread32(addr);
298 static void xgene_enet_rd_diag_csr(struct xgene_enet_pdata *pdata,
299 u32 offset, u32 *val)
301 void __iomem *addr = pdata->eth_diag_csr_addr + offset;
303 *val = ioread32(addr);
306 static void xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *pdata,
307 u32 offset, u32 *val)
309 void __iomem *addr = pdata->mcx_mac_csr_addr + offset;
311 *val = ioread32(addr);
314 static bool xgene_enet_rd_indirect(void __iomem *addr, void __iomem *rd,
315 void __iomem *cmd, void __iomem *cmd_done,
316 u32 rd_addr, u32 *rd_data)
321 iowrite32(rd_addr, addr);
322 iowrite32(XGENE_ENET_RD_CMD, cmd);
324 /* wait for read command to complete */
325 while (!(done = ioread32(cmd_done)) && wait--)
331 *rd_data = ioread32(rd);
337 static void xgene_enet_rd_mcx_mac(struct xgene_enet_pdata *pdata,
338 u32 rd_addr, u32 *rd_data)
340 void __iomem *addr, *rd, *cmd, *cmd_done;
342 addr = pdata->mcx_mac_addr + MAC_ADDR_REG_OFFSET;
343 rd = pdata->mcx_mac_addr + MAC_READ_REG_OFFSET;
344 cmd = pdata->mcx_mac_addr + MAC_COMMAND_REG_OFFSET;
345 cmd_done = pdata->mcx_mac_addr + MAC_COMMAND_DONE_REG_OFFSET;
347 if (!xgene_enet_rd_indirect(addr, rd, cmd, cmd_done, rd_addr, rd_data))
348 netdev_err(pdata->ndev, "MCX mac read failed, addr: %04x\n",
352 static int xgene_mii_phy_write(struct xgene_enet_pdata *pdata, int phy_id,
355 u32 addr = 0, wr_data = 0;
359 PHY_ADDR_SET(&addr, phy_id);
360 REG_ADDR_SET(&addr, reg);
361 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
363 PHY_CONTROL_SET(&wr_data, data);
364 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONTROL_ADDR, wr_data);
367 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
368 } while ((done & BUSY_MASK) && wait--);
370 if (done & BUSY_MASK) {
371 netdev_err(pdata->ndev, "MII_MGMT write failed\n");
378 static int xgene_mii_phy_read(struct xgene_enet_pdata *pdata,
385 PHY_ADDR_SET(&addr, phy_id);
386 REG_ADDR_SET(&addr, reg);
387 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_ADDRESS_ADDR, addr);
388 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK);
391 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_INDICATORS_ADDR, &done);
392 } while ((done & BUSY_MASK) && wait--);
394 if (done & BUSY_MASK) {
395 netdev_err(pdata->ndev, "MII_MGMT read failed\n");
399 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_STATUS_ADDR, &data);
400 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_COMMAND_ADDR, 0);
405 static void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata)
408 u8 *dev_addr = pdata->ndev->dev_addr;
410 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
411 (dev_addr[1] << 8) | dev_addr[0];
412 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
414 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR0_ADDR, addr0);
415 xgene_enet_wr_mcx_mac(pdata, STATION_ADDR1_ADDR, addr1);
418 static int xgene_enet_ecc_init(struct xgene_enet_pdata *pdata)
420 struct net_device *ndev = pdata->ndev;
424 xgene_enet_wr_diag_csr(pdata, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0x0);
426 usleep_range(100, 110);
427 xgene_enet_rd_diag_csr(pdata, ENET_BLOCK_MEM_RDY_ADDR, &data);
428 } while ((data != 0xffffffff) && wait--);
430 if (data != 0xffffffff) {
431 netdev_err(ndev, "Failed to release memory from shutdown\n");
438 static void xgene_gmac_reset(struct xgene_enet_pdata *pdata)
440 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1);
441 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, 0);
444 static void xgene_gmac_init(struct xgene_enet_pdata *pdata)
450 xgene_gmac_reset(pdata);
452 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, &icm0);
453 xgene_enet_rd_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, &icm2);
454 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_2_ADDR, &mc2);
455 xgene_enet_rd_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, &intf_ctl);
456 xgene_enet_rd_csr(pdata, RGMII_REG_0_ADDR, &rgmii);
458 switch (pdata->phy_speed) {
460 ENET_INTERFACE_MODE2_SET(&mc2, 1);
461 CFG_MACMODE_SET(&icm0, 0);
462 CFG_WAITASYNCRD_SET(&icm2, 500);
463 rgmii &= ~CFG_SPEED_1250;
466 ENET_INTERFACE_MODE2_SET(&mc2, 1);
467 intf_ctl |= ENET_LHD_MODE;
468 CFG_MACMODE_SET(&icm0, 1);
469 CFG_WAITASYNCRD_SET(&icm2, 80);
470 rgmii &= ~CFG_SPEED_1250;
473 ENET_INTERFACE_MODE2_SET(&mc2, 2);
474 intf_ctl |= ENET_GHD_MODE;
475 CFG_TXCLK_MUXSEL0_SET(&rgmii, 4);
476 xgene_enet_rd_csr(pdata, DEBUG_REG_ADDR, &value);
477 value |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX;
478 xgene_enet_wr_csr(pdata, DEBUG_REG_ADDR, value);
483 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_2_ADDR, mc2);
484 xgene_enet_wr_mcx_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl);
486 xgene_gmac_set_mac_addr(pdata);
488 /* Adjust MDC clock frequency */
489 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &value);
490 MGMT_CLOCK_SEL_SET(&value, 7);
491 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, value);
493 /* Enable drop if bufpool not available */
494 xgene_enet_rd_csr(pdata, RSIF_CONFIG_REG_ADDR, &value);
495 value |= CFG_RSIF_FPBUFF_TIMEOUT_EN;
496 xgene_enet_wr_csr(pdata, RSIF_CONFIG_REG_ADDR, value);
498 /* Rtype should be copied from FP */
499 xgene_enet_wr_csr(pdata, RSIF_RAM_DBG_REG0_ADDR, 0);
500 xgene_enet_wr_csr(pdata, RGMII_REG_0_ADDR, rgmii);
502 /* Rx-Tx traffic resume */
503 xgene_enet_wr_csr(pdata, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0);
505 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG0_REG_0_ADDR, icm0);
506 xgene_enet_wr_mcx_csr(pdata, ICM_CONFIG2_REG_0_ADDR, icm2);
508 xgene_enet_rd_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, &value);
509 value &= ~TX_DV_GATE_EN0;
510 value &= ~RX_DV_GATE_EN0;
512 xgene_enet_wr_mcx_csr(pdata, RX_DV_GATE_REG_0_ADDR, value);
514 xgene_enet_wr_csr(pdata, CFG_BYPASS_ADDR, RESUME_TX);
517 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *pdata)
519 u32 val = 0xffffffff;
521 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQASSOC_ADDR, val);
522 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPQASSOC_ADDR, val);
523 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEWQASSOC_ADDR, val);
524 xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIQMLITEFPQASSOC_ADDR, val);
527 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
528 u32 dst_ring_num, u16 bufpool_id)
533 fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;
535 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);
536 cb |= CFG_CLE_BYPASS_EN0;
537 CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);
538 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG0_0_ADDR, cb);
540 xgene_enet_rd_csr(pdata, CLE_BYPASS_REG1_0_ADDR, &cb);
541 CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);
542 CFG_CLE_FPSEL0_SET(&cb, fpsel);
543 xgene_enet_wr_csr(pdata, CLE_BYPASS_REG1_0_ADDR, cb);
546 static void xgene_gmac_rx_enable(struct xgene_enet_pdata *pdata)
550 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
551 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | RX_EN);
554 static void xgene_gmac_tx_enable(struct xgene_enet_pdata *pdata)
558 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
559 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data | TX_EN);
562 static void xgene_gmac_rx_disable(struct xgene_enet_pdata *pdata)
566 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
567 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~RX_EN);
570 static void xgene_gmac_tx_disable(struct xgene_enet_pdata *pdata)
574 xgene_enet_rd_mcx_mac(pdata, MAC_CONFIG_1_ADDR, &data);
575 xgene_enet_wr_mcx_mac(pdata, MAC_CONFIG_1_ADDR, data & ~TX_EN);
578 bool xgene_ring_mgr_init(struct xgene_enet_pdata *p)
580 if (!ioread32(p->ring_csr_addr + CLKEN_ADDR))
583 if (ioread32(p->ring_csr_addr + SRST_ADDR))
589 static int xgene_enet_reset(struct xgene_enet_pdata *pdata)
593 if (!xgene_ring_mgr_init(pdata))
597 clk_prepare_enable(pdata->clk);
598 clk_disable_unprepare(pdata->clk);
599 clk_prepare_enable(pdata->clk);
600 xgene_enet_ecc_init(pdata);
602 xgene_enet_config_ring_if_assoc(pdata);
604 /* Enable auto-incr for scanning */
605 xgene_enet_rd_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, &val);
606 val |= SCAN_AUTO_INCR;
607 MGMT_CLOCK_SEL_SET(&val, 1);
608 xgene_enet_wr_mcx_mac(pdata, MII_MGMT_CONFIG_ADDR, val);
613 static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata)
615 clk_disable_unprepare(pdata->clk);
618 static int xgene_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
620 struct xgene_enet_pdata *pdata = bus->priv;
623 val = xgene_mii_phy_read(pdata, mii_id, regnum);
624 netdev_dbg(pdata->ndev, "mdio_rd: bus=%d reg=%d val=%x\n",
625 mii_id, regnum, val);
630 static int xgene_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
633 struct xgene_enet_pdata *pdata = bus->priv;
635 netdev_dbg(pdata->ndev, "mdio_wr: bus=%d reg=%d val=%x\n",
636 mii_id, regnum, val);
637 return xgene_mii_phy_write(pdata, mii_id, regnum, val);
640 static void xgene_enet_adjust_link(struct net_device *ndev)
642 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
643 struct phy_device *phydev = pdata->phy_dev;
646 if (pdata->phy_speed != phydev->speed) {
647 pdata->phy_speed = phydev->speed;
648 xgene_gmac_init(pdata);
649 xgene_gmac_rx_enable(pdata);
650 xgene_gmac_tx_enable(pdata);
651 phy_print_status(phydev);
654 xgene_gmac_rx_disable(pdata);
655 xgene_gmac_tx_disable(pdata);
656 pdata->phy_speed = SPEED_UNKNOWN;
657 phy_print_status(phydev);
661 static int xgene_enet_phy_connect(struct net_device *ndev)
663 struct xgene_enet_pdata *pdata = netdev_priv(ndev);
664 struct device_node *phy_np;
665 struct phy_device *phy_dev;
666 struct device *dev = &pdata->pdev->dev;
669 phy_np = of_parse_phandle(dev->of_node, "phy-handle", 0);
671 netdev_dbg(ndev, "No phy-handle found in DT\n");
674 pdata->phy_dev = of_phy_find_device(phy_np);
677 phy_dev = pdata->phy_dev;
680 phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link,
682 netdev_err(ndev, "Could not connect to PHY\n");
686 pdata->phy_speed = SPEED_UNKNOWN;
687 phy_dev->supported &= ~SUPPORTED_10baseT_Half &
688 ~SUPPORTED_100baseT_Half &
689 ~SUPPORTED_1000baseT_Half;
690 phy_dev->advertising = phy_dev->supported;
695 static int xgene_mdiobus_register(struct xgene_enet_pdata *pdata,
696 struct mii_bus *mdio)
698 struct device *dev = &pdata->pdev->dev;
699 struct net_device *ndev = pdata->ndev;
700 struct phy_device *phy;
701 struct device_node *child_np;
702 struct device_node *mdio_np = NULL;
707 for_each_child_of_node(dev->of_node, child_np) {
708 if (of_device_is_compatible(child_np,
716 netdev_dbg(ndev, "No mdio node in the dts\n");
720 return of_mdiobus_register(mdio, mdio_np);
723 /* Mask out all PHYs from auto probing. */
726 /* Register the MDIO bus */
727 ret = mdiobus_register(mdio);
731 ret = device_property_read_u32(dev, "phy-channel", &phy_id);
733 ret = device_property_read_u32(dev, "phy-addr", &phy_id);
737 phy = get_phy_device(mdio, phy_id, true);
738 if (!phy || IS_ERR(phy))
741 ret = phy_device_register(phy);
743 phy_device_free(phy);
745 pdata->phy_dev = phy;
750 int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
752 struct net_device *ndev = pdata->ndev;
753 struct mii_bus *mdio_bus;
756 mdio_bus = mdiobus_alloc();
760 mdio_bus->name = "APM X-Gene MDIO bus";
761 mdio_bus->read = xgene_enet_mdio_read;
762 mdio_bus->write = xgene_enet_mdio_write;
763 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "xgene-mii",
766 mdio_bus->priv = pdata;
767 mdio_bus->parent = &ndev->dev;
769 ret = xgene_mdiobus_register(pdata, mdio_bus);
771 netdev_err(ndev, "Failed to register MDIO bus\n");
772 mdiobus_free(mdio_bus);
775 pdata->mdio_bus = mdio_bus;
777 ret = xgene_enet_phy_connect(ndev);
779 xgene_enet_mdio_remove(pdata);
784 void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata)
786 mdiobus_unregister(pdata->mdio_bus);
787 mdiobus_free(pdata->mdio_bus);
788 pdata->mdio_bus = NULL;
791 struct xgene_mac_ops xgene_gmac_ops = {
792 .init = xgene_gmac_init,
793 .reset = xgene_gmac_reset,
794 .rx_enable = xgene_gmac_rx_enable,
795 .tx_enable = xgene_gmac_tx_enable,
796 .rx_disable = xgene_gmac_rx_disable,
797 .tx_disable = xgene_gmac_tx_disable,
798 .set_mac_addr = xgene_gmac_set_mac_addr,
801 struct xgene_port_ops xgene_gport_ops = {
802 .reset = xgene_enet_reset,
803 .cle_bypass = xgene_enet_cle_bypass,
804 .shutdown = xgene_gport_shutdown,