3 * Alchemy Au1x00 ethernet driver
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
18 * ########################################################################
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, see <http://www.gnu.org/licenses/>.
32 * ########################################################################
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38 #include <linux/capability.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/string.h>
43 #include <linux/timer.h>
44 #include <linux/errno.h>
46 #include <linux/ioport.h>
47 #include <linux/bitops.h>
48 #include <linux/slab.h>
49 #include <linux/interrupt.h>
50 #include <linux/netdevice.h>
51 #include <linux/etherdevice.h>
52 #include <linux/ethtool.h>
53 #include <linux/mii.h>
54 #include <linux/skbuff.h>
55 #include <linux/delay.h>
56 #include <linux/crc32.h>
57 #include <linux/phy.h>
58 #include <linux/platform_device.h>
59 #include <linux/cpu.h>
62 #include <asm/mipsregs.h>
64 #include <asm/processor.h>
67 #include <au1xxx_eth.h>
70 #include "au1000_eth.h"
72 #ifdef AU1000_ETH_DEBUG
73 static int au1000_debug = 5;
75 static int au1000_debug = 3;
78 #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
82 #define DRV_NAME "au1000_eth"
83 #define DRV_VERSION "1.7"
84 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
85 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
87 MODULE_AUTHOR(DRV_AUTHOR);
88 MODULE_DESCRIPTION(DRV_DESC);
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_VERSION);
92 /* AU1000 MAC registers and bits */
93 #define MAC_CONTROL 0x0
94 # define MAC_RX_ENABLE (1 << 2)
95 # define MAC_TX_ENABLE (1 << 3)
96 # define MAC_DEF_CHECK (1 << 5)
97 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
98 # define MAC_AUTO_PAD (1 << 8)
99 # define MAC_DISABLE_RETRY (1 << 10)
100 # define MAC_DISABLE_BCAST (1 << 11)
101 # define MAC_LATE_COL (1 << 12)
102 # define MAC_HASH_MODE (1 << 13)
103 # define MAC_HASH_ONLY (1 << 15)
104 # define MAC_PASS_ALL (1 << 16)
105 # define MAC_INVERSE_FILTER (1 << 17)
106 # define MAC_PROMISCUOUS (1 << 18)
107 # define MAC_PASS_ALL_MULTI (1 << 19)
108 # define MAC_FULL_DUPLEX (1 << 20)
109 # define MAC_NORMAL_MODE 0
110 # define MAC_INT_LOOPBACK (1 << 21)
111 # define MAC_EXT_LOOPBACK (1 << 22)
112 # define MAC_DISABLE_RX_OWN (1 << 23)
113 # define MAC_BIG_ENDIAN (1 << 30)
114 # define MAC_RX_ALL (1 << 31)
115 #define MAC_ADDRESS_HIGH 0x4
116 #define MAC_ADDRESS_LOW 0x8
117 #define MAC_MCAST_HIGH 0xC
118 #define MAC_MCAST_LOW 0x10
119 #define MAC_MII_CNTRL 0x14
120 # define MAC_MII_BUSY (1 << 0)
121 # define MAC_MII_READ 0
122 # define MAC_MII_WRITE (1 << 1)
123 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125 #define MAC_MII_DATA 0x18
126 #define MAC_FLOW_CNTRL 0x1C
127 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
128 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129 # define MAC_PASS_CONTROL (1 << 2)
130 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
131 #define MAC_VLAN1_TAG 0x20
132 #define MAC_VLAN2_TAG 0x24
134 /* Ethernet Controller Enable */
135 # define MAC_EN_CLOCK_ENABLE (1 << 0)
136 # define MAC_EN_RESET0 (1 << 1)
137 # define MAC_EN_TOSS (0 << 2)
138 # define MAC_EN_CACHEABLE (1 << 3)
139 # define MAC_EN_RESET1 (1 << 4)
140 # define MAC_EN_RESET2 (1 << 5)
141 # define MAC_DMA_RESET (1 << 6)
143 /* Ethernet Controller DMA Channels */
144 /* offsets from MAC_TX_RING_ADDR address */
145 #define MAC_TX_BUFF0_STATUS 0x0
146 # define TX_FRAME_ABORTED (1 << 0)
147 # define TX_JAB_TIMEOUT (1 << 1)
148 # define TX_NO_CARRIER (1 << 2)
149 # define TX_LOSS_CARRIER (1 << 3)
150 # define TX_EXC_DEF (1 << 4)
151 # define TX_LATE_COLL_ABORT (1 << 5)
152 # define TX_EXC_COLL (1 << 6)
153 # define TX_UNDERRUN (1 << 7)
154 # define TX_DEFERRED (1 << 8)
155 # define TX_LATE_COLL (1 << 9)
156 # define TX_COLL_CNT_MASK (0xF << 10)
157 # define TX_PKT_RETRY (1 << 31)
158 #define MAC_TX_BUFF0_ADDR 0x4
159 # define TX_DMA_ENABLE (1 << 0)
160 # define TX_T_DONE (1 << 1)
161 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
162 #define MAC_TX_BUFF0_LEN 0x8
163 #define MAC_TX_BUFF1_STATUS 0x10
164 #define MAC_TX_BUFF1_ADDR 0x14
165 #define MAC_TX_BUFF1_LEN 0x18
166 #define MAC_TX_BUFF2_STATUS 0x20
167 #define MAC_TX_BUFF2_ADDR 0x24
168 #define MAC_TX_BUFF2_LEN 0x28
169 #define MAC_TX_BUFF3_STATUS 0x30
170 #define MAC_TX_BUFF3_ADDR 0x34
171 #define MAC_TX_BUFF3_LEN 0x38
173 /* offsets from MAC_RX_RING_ADDR */
174 #define MAC_RX_BUFF0_STATUS 0x0
175 # define RX_FRAME_LEN_MASK 0x3fff
176 # define RX_WDOG_TIMER (1 << 14)
177 # define RX_RUNT (1 << 15)
178 # define RX_OVERLEN (1 << 16)
179 # define RX_COLL (1 << 17)
180 # define RX_ETHER (1 << 18)
181 # define RX_MII_ERROR (1 << 19)
182 # define RX_DRIBBLING (1 << 20)
183 # define RX_CRC_ERROR (1 << 21)
184 # define RX_VLAN1 (1 << 22)
185 # define RX_VLAN2 (1 << 23)
186 # define RX_LEN_ERROR (1 << 24)
187 # define RX_CNTRL_FRAME (1 << 25)
188 # define RX_U_CNTRL_FRAME (1 << 26)
189 # define RX_MCAST_FRAME (1 << 27)
190 # define RX_BCAST_FRAME (1 << 28)
191 # define RX_FILTER_FAIL (1 << 29)
192 # define RX_PACKET_FILTER (1 << 30)
193 # define RX_MISSED_FRAME (1 << 31)
195 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
196 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198 #define MAC_RX_BUFF0_ADDR 0x4
199 # define RX_DMA_ENABLE (1 << 0)
200 # define RX_T_DONE (1 << 1)
201 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
202 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
203 #define MAC_RX_BUFF1_STATUS 0x10
204 #define MAC_RX_BUFF1_ADDR 0x14
205 #define MAC_RX_BUFF2_STATUS 0x20
206 #define MAC_RX_BUFF2_ADDR 0x24
207 #define MAC_RX_BUFF3_STATUS 0x30
208 #define MAC_RX_BUFF3_ADDR 0x34
211 * Theory of operation
213 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
214 * There are four receive and four transmit descriptors. These
215 * descriptors are not in memory; rather, they are just a set of
216 * hardware registers.
218 * Since the Au1000 has a coherent data cache, the receive and
219 * transmit buffers are allocated from the KSEG0 segment. The
220 * hardware registers, however, are still mapped at KSEG1 to
221 * make sure there's no out-of-order writes, and that all writes
222 * complete immediately.
226 * board-specific configurations
228 * PHY detection algorithm
230 * If phy_static_config is undefined, the PHY setup is
233 * mii_probe() first searches the current MAC's MII bus for a PHY,
234 * selecting the first (or last, if phy_search_highest_addr is
235 * defined) PHY address not already claimed by another netdev.
237 * If nothing was found that way when searching for the 2nd ethernet
238 * controller's PHY and phy1_search_mac0 is defined, then
239 * the first MII bus is searched as well for an unclaimed PHY; this is
240 * needed in case of a dual-PHY accessible only through the MAC0's MII
243 * Finally, if no PHY is found, then the corresponding ethernet
244 * controller is not registered to the network subsystem.
247 /* autodetection defaults: phy1_search_mac0 */
251 * most boards PHY setup should be detectable properly with the
252 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
253 * you have a switch attached, or want to use the PHY's interrupt
254 * notification capabilities) you can provide a static PHY
257 * IRQs may only be set, if a PHY address was configured
258 * If a PHY address is given, also a bus id is required to be set
260 * ps: make sure the used irqs are configured properly in the board
264 static void au1000_enable_mac(struct net_device *dev, int force_reset)
267 struct au1000_private *aup = netdev_priv(dev);
269 spin_lock_irqsave(&aup->lock, flags);
271 if (force_reset || (!aup->mac_enabled)) {
272 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
274 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
275 | MAC_EN_CLOCK_ENABLE), aup->enable);
278 aup->mac_enabled = 1;
281 spin_unlock_irqrestore(&aup->lock, flags);
287 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
289 struct au1000_private *aup = netdev_priv(dev);
290 u32 *const mii_control_reg = &aup->mac->mii_control;
291 u32 *const mii_data_reg = &aup->mac->mii_data;
295 while (readl(mii_control_reg) & MAC_MII_BUSY) {
297 if (--timedout == 0) {
298 netdev_err(dev, "read_MII busy timeout!!\n");
303 mii_control = MAC_SET_MII_SELECT_REG(reg) |
304 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
306 writel(mii_control, mii_control_reg);
309 while (readl(mii_control_reg) & MAC_MII_BUSY) {
311 if (--timedout == 0) {
312 netdev_err(dev, "mdio_read busy timeout!!\n");
316 return readl(mii_data_reg);
319 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
322 struct au1000_private *aup = netdev_priv(dev);
323 u32 *const mii_control_reg = &aup->mac->mii_control;
324 u32 *const mii_data_reg = &aup->mac->mii_data;
328 while (readl(mii_control_reg) & MAC_MII_BUSY) {
330 if (--timedout == 0) {
331 netdev_err(dev, "mdio_write busy timeout!!\n");
336 mii_control = MAC_SET_MII_SELECT_REG(reg) |
337 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
339 writel(value, mii_data_reg);
340 writel(mii_control, mii_control_reg);
343 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
345 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
346 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
348 struct net_device *const dev = bus->priv;
350 /* make sure the MAC associated with this
353 au1000_enable_mac(dev, 0);
355 return au1000_mdio_read(dev, phy_addr, regnum);
358 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
361 struct net_device *const dev = bus->priv;
363 /* make sure the MAC associated with this
366 au1000_enable_mac(dev, 0);
368 au1000_mdio_write(dev, phy_addr, regnum, value);
372 static int au1000_mdiobus_reset(struct mii_bus *bus)
374 struct net_device *const dev = bus->priv;
376 /* make sure the MAC associated with this
379 au1000_enable_mac(dev, 0);
384 static void au1000_hard_stop(struct net_device *dev)
386 struct au1000_private *aup = netdev_priv(dev);
389 netif_dbg(aup, drv, dev, "hard stop\n");
391 reg = readl(&aup->mac->control);
392 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
393 writel(reg, &aup->mac->control);
397 static void au1000_enable_rx_tx(struct net_device *dev)
399 struct au1000_private *aup = netdev_priv(dev);
402 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
404 reg = readl(&aup->mac->control);
405 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
406 writel(reg, &aup->mac->control);
411 au1000_adjust_link(struct net_device *dev)
413 struct au1000_private *aup = netdev_priv(dev);
414 struct phy_device *phydev = aup->phy_dev;
418 int status_change = 0;
420 BUG_ON(!aup->phy_dev);
422 spin_lock_irqsave(&aup->lock, flags);
424 if (phydev->link && (aup->old_speed != phydev->speed)) {
427 switch (phydev->speed) {
432 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
437 aup->old_speed = phydev->speed;
442 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
443 /* duplex mode changed */
445 /* switching duplex mode requires to disable rx and tx! */
446 au1000_hard_stop(dev);
448 reg = readl(&aup->mac->control);
449 if (DUPLEX_FULL == phydev->duplex) {
450 reg |= MAC_FULL_DUPLEX;
451 reg &= ~MAC_DISABLE_RX_OWN;
453 reg &= ~MAC_FULL_DUPLEX;
454 reg |= MAC_DISABLE_RX_OWN;
456 writel(reg, &aup->mac->control);
459 au1000_enable_rx_tx(dev);
460 aup->old_duplex = phydev->duplex;
465 if (phydev->link != aup->old_link) {
466 /* link state changed */
471 aup->old_duplex = -1;
474 aup->old_link = phydev->link;
478 spin_unlock_irqrestore(&aup->lock, flags);
482 netdev_info(dev, "link up (%d/%s)\n",
484 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
486 netdev_info(dev, "link down\n");
490 static int au1000_mii_probe(struct net_device *dev)
492 struct au1000_private *const aup = netdev_priv(dev);
493 struct phy_device *phydev = NULL;
496 if (aup->phy_static_config) {
497 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
500 phydev = aup->mii_bus->phy_map[aup->phy_addr];
502 netdev_info(dev, "using PHY-less setup\n");
506 /* find the first (lowest address) PHY
507 * on the current MAC's MII bus
509 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
510 if (aup->mii_bus->phy_map[phy_addr]) {
511 phydev = aup->mii_bus->phy_map[phy_addr];
512 if (!aup->phy_search_highest_addr)
513 /* break out with first one found */
517 if (aup->phy1_search_mac0) {
518 /* try harder to find a PHY */
519 if (!phydev && (aup->mac_id == 1)) {
520 /* no PHY found, maybe we have a dual PHY? */
521 dev_info(&dev->dev, ": no PHY found on MAC1, "
522 "let's see if it's attached to MAC0...\n");
524 /* find the first (lowest address) non-attached
525 * PHY on the MAC0 MII bus
527 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
528 struct phy_device *const tmp_phydev =
529 aup->mii_bus->phy_map[phy_addr];
531 if (aup->mac_id == 1)
538 /* already claimed by MAC0 */
539 if (tmp_phydev->attached_dev)
543 break; /* found it */
549 netdev_err(dev, "no PHY found\n");
553 /* now we are supposed to have a proper phydev, to attach to... */
554 BUG_ON(phydev->attached_dev);
556 phydev = phy_connect(dev, dev_name(&phydev->dev),
557 &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
559 if (IS_ERR(phydev)) {
560 netdev_err(dev, "Could not attach to PHY\n");
561 return PTR_ERR(phydev);
564 /* mask with MAC supported features */
565 phydev->supported &= (SUPPORTED_10baseT_Half
566 | SUPPORTED_10baseT_Full
567 | SUPPORTED_100baseT_Half
568 | SUPPORTED_100baseT_Full
570 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
574 phydev->advertising = phydev->supported;
578 aup->old_duplex = -1;
579 aup->phy_dev = phydev;
581 netdev_info(dev, "attached PHY driver [%s] "
582 "(mii_bus:phy_addr=%s, irq=%d)\n",
583 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
590 * Buffer allocation/deallocation routines. The buffer descriptor returned
591 * has the virtual and dma address of a buffer suitable for
592 * both, receive and transmit operations.
594 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
600 aup->pDBfree = pDB->pnext;
605 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
607 struct db_dest *pDBfree = aup->pDBfree;
609 pDBfree->pnext = pDB;
613 static void au1000_reset_mac_unlocked(struct net_device *dev)
615 struct au1000_private *const aup = netdev_priv(dev);
618 au1000_hard_stop(dev);
620 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
622 writel(0, aup->enable);
626 for (i = 0; i < NUM_RX_DMA; i++) {
627 /* reset control bits */
628 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
630 for (i = 0; i < NUM_TX_DMA; i++) {
631 /* reset control bits */
632 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
635 aup->mac_enabled = 0;
639 static void au1000_reset_mac(struct net_device *dev)
641 struct au1000_private *const aup = netdev_priv(dev);
644 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
647 spin_lock_irqsave(&aup->lock, flags);
649 au1000_reset_mac_unlocked(dev);
651 spin_unlock_irqrestore(&aup->lock, flags);
655 * Setup the receive and transmit "rings". These pointers are the addresses
656 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
657 * these are not descriptors sitting in memory.
660 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
664 for (i = 0; i < NUM_RX_DMA; i++) {
665 aup->rx_dma_ring[i] = (struct rx_dma *)
666 (tx_base + 0x100 + sizeof(struct rx_dma) * i);
668 for (i = 0; i < NUM_TX_DMA; i++) {
669 aup->tx_dma_ring[i] = (struct tx_dma *)
670 (tx_base + sizeof(struct tx_dma) * i);
678 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
680 struct au1000_private *aup = netdev_priv(dev);
683 return phy_ethtool_gset(aup->phy_dev, cmd);
688 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
690 struct au1000_private *aup = netdev_priv(dev);
692 if (!capable(CAP_NET_ADMIN))
696 return phy_ethtool_sset(aup->phy_dev, cmd);
702 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
704 struct au1000_private *aup = netdev_priv(dev);
706 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
707 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
708 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
710 info->regdump_len = 0;
713 static void au1000_set_msglevel(struct net_device *dev, u32 value)
715 struct au1000_private *aup = netdev_priv(dev);
716 aup->msg_enable = value;
719 static u32 au1000_get_msglevel(struct net_device *dev)
721 struct au1000_private *aup = netdev_priv(dev);
722 return aup->msg_enable;
725 static const struct ethtool_ops au1000_ethtool_ops = {
726 .get_settings = au1000_get_settings,
727 .set_settings = au1000_set_settings,
728 .get_drvinfo = au1000_get_drvinfo,
729 .get_link = ethtool_op_get_link,
730 .get_msglevel = au1000_get_msglevel,
731 .set_msglevel = au1000_set_msglevel,
736 * Initialize the interface.
738 * When the device powers up, the clocks are disabled and the
739 * mac is in reset state. When the interface is closed, we
740 * do the same -- reset the device and disable the clocks to
741 * conserve power. Thus, whenever au1000_init() is called,
742 * the device should already be in reset state.
744 static int au1000_init(struct net_device *dev)
746 struct au1000_private *aup = netdev_priv(dev);
751 netif_dbg(aup, hw, dev, "au1000_init\n");
753 /* bring the device out of reset */
754 au1000_enable_mac(dev, 1);
756 spin_lock_irqsave(&aup->lock, flags);
758 writel(0, &aup->mac->control);
759 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
760 aup->tx_tail = aup->tx_head;
761 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
763 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
764 &aup->mac->mac_addr_high);
765 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
766 dev->dev_addr[1]<<8 | dev->dev_addr[0],
767 &aup->mac->mac_addr_low);
770 for (i = 0; i < NUM_RX_DMA; i++)
771 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
775 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
776 #ifndef CONFIG_CPU_LITTLE_ENDIAN
777 control |= MAC_BIG_ENDIAN;
780 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
781 control |= MAC_FULL_DUPLEX;
783 control |= MAC_DISABLE_RX_OWN;
784 } else { /* PHY-less op, assume full-duplex */
785 control |= MAC_FULL_DUPLEX;
788 writel(control, &aup->mac->control);
789 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
792 spin_unlock_irqrestore(&aup->lock, flags);
796 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
798 struct net_device_stats *ps = &dev->stats;
801 if (status & RX_MCAST_FRAME)
804 if (status & RX_ERROR) {
806 if (status & RX_MISSED_FRAME)
807 ps->rx_missed_errors++;
808 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
809 ps->rx_length_errors++;
810 if (status & RX_CRC_ERROR)
812 if (status & RX_COLL)
815 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
820 * Au1000 receive routine.
822 static int au1000_rx(struct net_device *dev)
824 struct au1000_private *aup = netdev_priv(dev);
827 u32 buff_stat, status;
831 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
833 prxd = aup->rx_dma_ring[aup->rx_head];
834 buff_stat = prxd->buff_stat;
835 while (buff_stat & RX_T_DONE) {
836 status = prxd->status;
837 pDB = aup->rx_db_inuse[aup->rx_head];
838 au1000_update_rx_stats(dev, status);
839 if (!(status & RX_ERROR)) {
842 frmlen = (status & RX_FRAME_LEN_MASK);
843 frmlen -= 4; /* Remove FCS */
844 skb = netdev_alloc_skb(dev, frmlen + 2);
846 dev->stats.rx_dropped++;
849 skb_reserve(skb, 2); /* 16 byte IP header align */
850 skb_copy_to_linear_data(skb,
851 (unsigned char *)pDB->vaddr, frmlen);
852 skb_put(skb, frmlen);
853 skb->protocol = eth_type_trans(skb, dev);
854 netif_rx(skb); /* pass the packet to upper layers */
856 if (au1000_debug > 4) {
857 pr_err("rx_error(s):");
858 if (status & RX_MISSED_FRAME)
860 if (status & RX_WDOG_TIMER)
862 if (status & RX_RUNT)
864 if (status & RX_OVERLEN)
866 if (status & RX_COLL)
868 if (status & RX_MII_ERROR)
869 pr_cont(" mii error");
870 if (status & RX_CRC_ERROR)
871 pr_cont(" crc error");
872 if (status & RX_LEN_ERROR)
873 pr_cont(" len error");
874 if (status & RX_U_CNTRL_FRAME)
875 pr_cont(" u control frame");
879 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
880 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
883 /* next descriptor */
884 prxd = aup->rx_dma_ring[aup->rx_head];
885 buff_stat = prxd->buff_stat;
890 static void au1000_update_tx_stats(struct net_device *dev, u32 status)
892 struct au1000_private *aup = netdev_priv(dev);
893 struct net_device_stats *ps = &dev->stats;
895 if (status & TX_FRAME_ABORTED) {
896 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
897 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
898 /* any other tx errors are only valid
899 * in half duplex mode
902 ps->tx_aborted_errors++;
906 ps->tx_aborted_errors++;
907 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
908 ps->tx_carrier_errors++;
914 * Called from the interrupt service routine to acknowledge
915 * the TX DONE bits. This is a must if the irq is setup as
918 static void au1000_tx_ack(struct net_device *dev)
920 struct au1000_private *aup = netdev_priv(dev);
923 ptxd = aup->tx_dma_ring[aup->tx_tail];
925 while (ptxd->buff_stat & TX_T_DONE) {
926 au1000_update_tx_stats(dev, ptxd->status);
927 ptxd->buff_stat &= ~TX_T_DONE;
931 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
932 ptxd = aup->tx_dma_ring[aup->tx_tail];
936 netif_wake_queue(dev);
942 * Au1000 interrupt service routine.
944 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
946 struct net_device *dev = dev_id;
948 /* Handle RX interrupts first to minimize chance of overrun */
952 return IRQ_RETVAL(1);
955 static int au1000_open(struct net_device *dev)
958 struct au1000_private *aup = netdev_priv(dev);
960 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
962 retval = request_irq(dev->irq, au1000_interrupt, 0,
965 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
969 retval = au1000_init(dev);
971 netdev_err(dev, "error in au1000_init\n");
972 free_irq(dev->irq, dev);
977 /* cause the PHY state machine to schedule a link state check */
978 aup->phy_dev->state = PHY_CHANGELINK;
979 phy_start(aup->phy_dev);
982 netif_start_queue(dev);
984 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
989 static int au1000_close(struct net_device *dev)
992 struct au1000_private *const aup = netdev_priv(dev);
994 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
997 phy_stop(aup->phy_dev);
999 spin_lock_irqsave(&aup->lock, flags);
1001 au1000_reset_mac_unlocked(dev);
1003 /* stop the device */
1004 netif_stop_queue(dev);
1006 /* disable the interrupt */
1007 free_irq(dev->irq, dev);
1008 spin_unlock_irqrestore(&aup->lock, flags);
1014 * Au1000 transmit routine.
1016 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1018 struct au1000_private *aup = netdev_priv(dev);
1019 struct net_device_stats *ps = &dev->stats;
1020 struct tx_dma *ptxd;
1022 struct db_dest *pDB;
1025 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
1026 (unsigned)aup, skb->len,
1027 skb->data, aup->tx_head);
1029 ptxd = aup->tx_dma_ring[aup->tx_head];
1030 buff_stat = ptxd->buff_stat;
1031 if (buff_stat & TX_DMA_ENABLE) {
1032 /* We've wrapped around and the transmitter is still busy */
1033 netif_stop_queue(dev);
1035 return NETDEV_TX_BUSY;
1036 } else if (buff_stat & TX_T_DONE) {
1037 au1000_update_tx_stats(dev, ptxd->status);
1043 netif_wake_queue(dev);
1046 pDB = aup->tx_db_inuse[aup->tx_head];
1047 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1048 if (skb->len < ETH_ZLEN) {
1049 for (i = skb->len; i < ETH_ZLEN; i++)
1050 ((char *)pDB->vaddr)[i] = 0;
1052 ptxd->len = ETH_ZLEN;
1054 ptxd->len = skb->len;
1057 ps->tx_bytes += ptxd->len;
1059 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1062 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1063 return NETDEV_TX_OK;
1067 * The Tx ring has been full longer than the watchdog timeout
1068 * value. The transmitter must be hung?
1070 static void au1000_tx_timeout(struct net_device *dev)
1072 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1073 au1000_reset_mac(dev);
1075 dev->trans_start = jiffies; /* prevent tx timeout */
1076 netif_wake_queue(dev);
1079 static void au1000_multicast_list(struct net_device *dev)
1081 struct au1000_private *aup = netdev_priv(dev);
1084 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1085 reg = readl(&aup->mac->control);
1086 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1087 reg |= MAC_PROMISCUOUS;
1088 } else if ((dev->flags & IFF_ALLMULTI) ||
1089 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1090 reg |= MAC_PASS_ALL_MULTI;
1091 reg &= ~MAC_PROMISCUOUS;
1092 netdev_info(dev, "Pass all multicast\n");
1094 struct netdev_hw_addr *ha;
1095 u32 mc_filter[2]; /* Multicast hash filter */
1097 mc_filter[1] = mc_filter[0] = 0;
1098 netdev_for_each_mc_addr(ha, dev)
1099 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1101 writel(mc_filter[1], &aup->mac->multi_hash_high);
1102 writel(mc_filter[0], &aup->mac->multi_hash_low);
1103 reg &= ~MAC_PROMISCUOUS;
1104 reg |= MAC_HASH_MODE;
1106 writel(reg, &aup->mac->control);
1109 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1111 struct au1000_private *aup = netdev_priv(dev);
1113 if (!netif_running(dev))
1117 return -EINVAL; /* PHY not controllable */
1119 return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1122 static const struct net_device_ops au1000_netdev_ops = {
1123 .ndo_open = au1000_open,
1124 .ndo_stop = au1000_close,
1125 .ndo_start_xmit = au1000_tx,
1126 .ndo_set_rx_mode = au1000_multicast_list,
1127 .ndo_do_ioctl = au1000_ioctl,
1128 .ndo_tx_timeout = au1000_tx_timeout,
1129 .ndo_set_mac_address = eth_mac_addr,
1130 .ndo_validate_addr = eth_validate_addr,
1131 .ndo_change_mtu = eth_change_mtu,
1134 static int au1000_probe(struct platform_device *pdev)
1136 static unsigned version_printed;
1137 struct au1000_private *aup = NULL;
1138 struct au1000_eth_platform_data *pd;
1139 struct net_device *dev = NULL;
1140 struct db_dest *pDB, *pDBfree;
1141 int irq, i, err = 0;
1142 struct resource *base, *macen, *macdma;
1144 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146 dev_err(&pdev->dev, "failed to retrieve base register\n");
1151 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1153 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1158 irq = platform_get_irq(pdev, 0);
1160 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
1165 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1167 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1172 if (!request_mem_region(base->start, resource_size(base),
1174 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1179 if (!request_mem_region(macen->start, resource_size(macen),
1181 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1186 if (!request_mem_region(macdma->start, resource_size(macdma),
1188 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1193 dev = alloc_etherdev(sizeof(struct au1000_private));
1199 SET_NETDEV_DEV(dev, &pdev->dev);
1200 platform_set_drvdata(pdev, dev);
1201 aup = netdev_priv(dev);
1203 spin_lock_init(&aup->lock);
1204 aup->msg_enable = (au1000_debug < 4 ?
1205 AU1000_DEF_MSG_ENABLE : au1000_debug);
1207 /* Allocate the data buffers
1208 * Snooping works fine with eth on all au1xxx
1210 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1211 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1214 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1219 /* aup->mac is the base address of the MAC's registers */
1220 aup->mac = (struct mac_reg *)
1221 ioremap_nocache(base->start, resource_size(base));
1223 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1228 /* Setup some variables for quick register address access */
1229 aup->enable = (u32 *)ioremap_nocache(macen->start,
1230 resource_size(macen));
1232 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1236 aup->mac_id = pdev->id;
1238 aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
1240 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1245 au1000_setup_hw_rings(aup, aup->macdma);
1247 writel(0, aup->enable);
1248 aup->mac_enabled = 0;
1250 pd = dev_get_platdata(&pdev->dev);
1252 dev_info(&pdev->dev, "no platform_data passed,"
1253 " PHY search on MAC0\n");
1254 aup->phy1_search_mac0 = 1;
1256 if (is_valid_ether_addr(pd->mac)) {
1257 memcpy(dev->dev_addr, pd->mac, ETH_ALEN);
1259 /* Set a random MAC since no valid provided by platform_data. */
1260 eth_hw_addr_random(dev);
1263 aup->phy_static_config = pd->phy_static_config;
1264 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1265 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1266 aup->phy_addr = pd->phy_addr;
1267 aup->phy_busid = pd->phy_busid;
1268 aup->phy_irq = pd->phy_irq;
1271 if (aup->phy_busid && aup->phy_busid > 0) {
1272 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1274 goto err_mdiobus_alloc;
1277 aup->mii_bus = mdiobus_alloc();
1278 if (aup->mii_bus == NULL) {
1279 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1281 goto err_mdiobus_alloc;
1284 aup->mii_bus->priv = dev;
1285 aup->mii_bus->read = au1000_mdiobus_read;
1286 aup->mii_bus->write = au1000_mdiobus_write;
1287 aup->mii_bus->reset = au1000_mdiobus_reset;
1288 aup->mii_bus->name = "au1000_eth_mii";
1289 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1290 pdev->name, aup->mac_id);
1291 aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1292 if (aup->mii_bus->irq == NULL) {
1297 for (i = 0; i < PHY_MAX_ADDR; ++i)
1298 aup->mii_bus->irq[i] = PHY_POLL;
1299 /* if known, set corresponding PHY IRQs */
1300 if (aup->phy_static_config)
1301 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1302 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1304 err = mdiobus_register(aup->mii_bus);
1306 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1307 goto err_mdiobus_reg;
1310 err = au1000_mii_probe(dev);
1315 /* setup the data buffer descriptors and attach a buffer to each one */
1317 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1318 pDB->pnext = pDBfree;
1320 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1321 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1324 aup->pDBfree = pDBfree;
1327 for (i = 0; i < NUM_RX_DMA; i++) {
1328 pDB = au1000_GetFreeDB(aup);
1332 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1333 aup->rx_db_inuse[i] = pDB;
1337 for (i = 0; i < NUM_TX_DMA; i++) {
1338 pDB = au1000_GetFreeDB(aup);
1342 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1343 aup->tx_dma_ring[i]->len = 0;
1344 aup->tx_db_inuse[i] = pDB;
1347 dev->base_addr = base->start;
1349 dev->netdev_ops = &au1000_netdev_ops;
1350 dev->ethtool_ops = &au1000_ethtool_ops;
1351 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1354 * The boot code uses the ethernet controller, so reset it to start
1355 * fresh. au1000_init() expects that the device is in reset state.
1357 au1000_reset_mac(dev);
1359 err = register_netdev(dev);
1361 netdev_err(dev, "Cannot register net device, aborting.\n");
1365 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1366 (unsigned long)base->start, irq);
1367 if (version_printed++ == 0)
1368 pr_info("%s version %s %s\n",
1369 DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1374 if (aup->mii_bus != NULL)
1375 mdiobus_unregister(aup->mii_bus);
1377 /* here we should have a valid dev plus aup-> register addresses
1378 * so we can reset the mac properly.
1380 au1000_reset_mac(dev);
1382 for (i = 0; i < NUM_RX_DMA; i++) {
1383 if (aup->rx_db_inuse[i])
1384 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1386 for (i = 0; i < NUM_TX_DMA; i++) {
1387 if (aup->tx_db_inuse[i])
1388 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1391 mdiobus_free(aup->mii_bus);
1393 iounmap(aup->macdma);
1395 iounmap(aup->enable);
1399 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1400 (void *)aup->vaddr, aup->dma_addr);
1404 release_mem_region(macdma->start, resource_size(macdma));
1406 release_mem_region(macen->start, resource_size(macen));
1408 release_mem_region(base->start, resource_size(base));
1413 static int au1000_remove(struct platform_device *pdev)
1415 struct net_device *dev = platform_get_drvdata(pdev);
1416 struct au1000_private *aup = netdev_priv(dev);
1418 struct resource *base, *macen;
1420 unregister_netdev(dev);
1421 mdiobus_unregister(aup->mii_bus);
1422 mdiobus_free(aup->mii_bus);
1424 for (i = 0; i < NUM_RX_DMA; i++)
1425 if (aup->rx_db_inuse[i])
1426 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1428 for (i = 0; i < NUM_TX_DMA; i++)
1429 if (aup->tx_db_inuse[i])
1430 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1432 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1433 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1434 (void *)aup->vaddr, aup->dma_addr);
1436 iounmap(aup->macdma);
1438 iounmap(aup->enable);
1440 base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1441 release_mem_region(base->start, resource_size(base));
1443 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1444 release_mem_region(base->start, resource_size(base));
1446 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1447 release_mem_region(macen->start, resource_size(macen));
1454 static struct platform_driver au1000_eth_driver = {
1455 .probe = au1000_probe,
1456 .remove = au1000_remove,
1458 .name = "au1000-eth",
1459 .owner = THIS_MODULE,
1463 module_platform_driver(au1000_eth_driver);
1465 MODULE_ALIAS("platform:au1000-eth");