drivers/net/enc28j60.c

   1 /*
   2  * Microchip ENC28J60 ethernet driver (MAC + PHY)
   3  *
   4  * Copyright (C) 2007 Eurek srl
   5  * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
   6  * based on enc28j60.c written by David Anders for 2.4 kernel version
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/fcntl.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/string.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/tcp.h>
  28 #include <linux/skbuff.h>
  29 #include <linux/delay.h>
  30 #include <linux/spi/spi.h>
  31 #include <mach/gpio.h>
  32
  33 #include "enc28j60_hw.h"
  34
  35 #define MAC_INT_PORT    RK2818_PIN_PE2
  36 #define DRV_NAME        "enc28j60"
  37 #define DRV_VERSION     "1.01"
  38
  39 #define SPI_OPLEN       1
  40
  41 #define ENC28J60_MSG_DEFAULT    \
  42         (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
  43
  44 /* Buffer size required for the largest SPI transfer (i.e., reading a
  45  * frame). */
  46 #define SPI_TRANSFER_BUF_LEN    (4 + MAX_FRAMELEN)
  47
  48 #define TX_TIMEOUT      (4 * HZ)
  49
  50 /* Max TX retries in case of collision as suggested by errata datasheet */
  51 #define MAX_TX_RETRYCOUNT       16
  52
  53 enum {
  54         RXFILTER_NORMAL,
  55         RXFILTER_MULTI,
  56         RXFILTER_PROMISC
  57 };
  58
  59 /* Driver local data */
  60 struct enc28j60_net {
  61         struct net_device *netdev;
  62         struct spi_device *spi;
  63         struct mutex lock;
  64         struct sk_buff *tx_skb;
  65         struct work_struct tx_work;
  66         struct work_struct irq_work;
  67         struct work_struct setrx_work;
  68         struct work_struct restart_work;
  69         u8 bank;                /* current register bank selected */
  70         u16 next_pk_ptr;        /* next packet pointer within FIFO */
  71         u16 max_pk_counter;     /* statistics: max packet counter */
  72         u16 tx_retry_count;
  73         bool hw_enable;
  74         bool full_duplex;
  75         int rxfilter;
  76         u32 msg_enable;
  77         u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
  78 };
  79
  80 /* use ethtool to change the level for any given device */
  81 static struct {
  82         u32 msg_enable;
  83 } debug = { -1 };
  84
  85 /*
  86  * SPI read buffer
  87  * wait for the SPI transfer and copy received data to destination
  88  */
  89 static int
  90 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
  91 {
  92         u8 *rx_buf = priv->spi_transfer_buf + 4;
  93         u8 *tx_buf = priv->spi_transfer_buf;
  94         struct spi_transfer t = {
  95                 .tx_buf = tx_buf,
  96                 .rx_buf = rx_buf,
  97                 .len = SPI_OPLEN + len,
  98         };
  99         struct spi_message msg;
 100         int ret;
 101
 102         tx_buf[0] = ENC28J60_READ_BUF_MEM;
 103         tx_buf[1] = tx_buf[2] = tx_buf[3] = 0;  /* don't care */
 104
 105         spi_message_init(&msg);
 106         spi_message_add_tail(&t, &msg);
 107         ret = spi_sync(priv->spi, &msg);
 108         if (ret == 0) {
 109                 memcpy(data, &rx_buf[SPI_OPLEN], len);
 110                 ret = msg.status;
 111         }
 112         if (ret && netif_msg_drv(priv))
 113                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 114                         __func__, ret);
 115
 116         return ret;
 117 }
 118
 119 /*
 120  * SPI write buffer
 121  */
 122 static int spi_write_buf(struct enc28j60_net *priv, int len,
 123                          const u8 *data)
 124 {
 125         int ret;
 126
 127         if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
 128                 ret = -EINVAL;
 129         else {
 130                 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
 131                 memcpy(&priv->spi_transfer_buf[1], data, len);
 132                 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
 133                 if (ret && netif_msg_drv(priv))
 134                         printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 135                                 __func__, ret);
 136         }
 137         return ret;
 138 }
 139
 140 /*
 141  * basic SPI read operation
 142  */
 143 static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
 144                            u8 addr)
 145 {
 146         u8 tx_buf[2];
 147         u8 rx_buf[4];
 148         u8 val = 0;
 149         int ret;
 150         int slen = SPI_OPLEN;
 151
 152         /* do dummy read if needed */
 153         if (addr & SPRD_MASK)
 154                 slen++;
 155
 156         tx_buf[0] = op | (addr & ADDR_MASK);
 157         ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
 158         if (ret)
 159                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 160                         __func__, ret);
 161         else
 162                 val = rx_buf[slen - 1];
 163
 164         return val;
 165 }
 166
 167 /*
 168  * basic SPI write operation
 169  */
 170 static int spi_write_op(struct enc28j60_net *priv, u8 op,
 171                         u8 addr, u8 val)
 172 {
 173         int ret;
 174
 175         priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
 176         priv->spi_transfer_buf[1] = val;
 177         ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
 178         if (ret && netif_msg_drv(priv))
 179                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 180                         __func__, ret);
 181         return ret;
 182 }
 183
 184 static void enc28j60_soft_reset(struct enc28j60_net *priv)
 185 {
 186         if (netif_msg_hw(priv))
 187                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
 188
 189         spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
 190         /* Errata workaround #1, CLKRDY check is unreliable,
 191          * delay at least 1 mS instead */
 192         udelay(2000);
 193 }
 194
 195 /*
 196  * select the current register bank if necessary
 197  */
 198 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
 199 {
 200         u8 b = (addr & BANK_MASK) >> 5;
 201
 202         /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
 203          * are present in all banks, no need to switch bank
 204          */
 205         if (addr >= EIE && addr <= ECON1)
 206                 return;
 207
 208         /* Clear or set each bank selection bit as needed */
 209         if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
 210                 if (b & ECON1_BSEL0)
 211                         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
 212                                         ECON1_BSEL0);
 213                 else
 214                         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
 215                                         ECON1_BSEL0);
 216         }
 217         if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
 218                 if (b & ECON1_BSEL1)
 219                         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
 220                                         ECON1_BSEL1);
 221                 else
 222                         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
 223                                         ECON1_BSEL1);
 224         }
 225         priv->bank = b;
 226 }
 227
 228 /*
 229  * Register access routines through the SPI bus.
 230  * Every register access comes in two flavours:
 231  * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
 232  *   atomically more than one register
 233  * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
 234  *
 235  * Some registers can be accessed through the bit field clear and
 236  * bit field set to avoid a read modify write cycle.
 237  */
 238
 239 /*
 240  * Register bit field Set
 241  */
 242 static void nolock_reg_bfset(struct enc28j60_net *priv,
 243                                       u8 addr, u8 mask)
 244 {
 245         enc28j60_set_bank(priv, addr);
 246         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
 247 }
 248
 249 static void locked_reg_bfset(struct enc28j60_net *priv,
 250                                       u8 addr, u8 mask)
 251 {
 252         mutex_lock(&priv->lock);
 253         nolock_reg_bfset(priv, addr, mask);
 254         mutex_unlock(&priv->lock);
 255 }
 256
 257 /*
 258  * Register bit field Clear
 259  */
 260 static void nolock_reg_bfclr(struct enc28j60_net *priv,
 261                                       u8 addr, u8 mask)
 262 {
 263         enc28j60_set_bank(priv, addr);
 264         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
 265 }
 266
 267 static void locked_reg_bfclr(struct enc28j60_net *priv,
 268                                       u8 addr, u8 mask)
 269 {
 270         mutex_lock(&priv->lock);
 271         nolock_reg_bfclr(priv, addr, mask);
 272         mutex_unlock(&priv->lock);
 273 }
 274
 275 /*
 276  * Register byte read
 277  */
 278 static int nolock_regb_read(struct enc28j60_net *priv,
 279                                      u8 address)
 280 {
 281         enc28j60_set_bank(priv, address);
 282         return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
 283 }
 284
 285 static int locked_regb_read(struct enc28j60_net *priv,
 286                                      u8 address)
 287 {
 288         int ret;
 289
 290         mutex_lock(&priv->lock);
 291         ret = nolock_regb_read(priv, address);
 292         mutex_unlock(&priv->lock);
 293
 294         return ret;
 295 }
 296
 297 /*
 298  * Register word read
 299  */
 300 static int nolock_regw_read(struct enc28j60_net *priv,
 301                                      u8 address)
 302 {
 303         int rl, rh;
 304
 305         enc28j60_set_bank(priv, address);
 306         rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
 307         rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
 308
 309         return (rh << 8) | rl;
 310 }
 311
 312 static int locked_regw_read(struct enc28j60_net *priv,
 313                                      u8 address)
 314 {
 315         int ret;
 316
 317         mutex_lock(&priv->lock);
 318         ret = nolock_regw_read(priv, address);
 319         mutex_unlock(&priv->lock);
 320
 321         return ret;
 322 }
 323
 324 /*
 325  * Register byte write
 326  */
 327 static void nolock_regb_write(struct enc28j60_net *priv,
 328                                        u8 address, u8 data)
 329 {
 330         enc28j60_set_bank(priv, address);
 331         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
 332 }
 333
 334 static void locked_regb_write(struct enc28j60_net *priv,
 335                                        u8 address, u8 data)
 336 {
 337         mutex_lock(&priv->lock);
 338         nolock_regb_write(priv, address, data);
 339         mutex_unlock(&priv->lock);
 340 }
 341
 342 /*
 343  * Register word write
 344  */
 345 static void nolock_regw_write(struct enc28j60_net *priv,
 346                                        u8 address, u16 data)
 347 {
 348         enc28j60_set_bank(priv, address);
 349         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
 350         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
 351                      (u8) (data >> 8));
 352 }
 353
 354 static void locked_regw_write(struct enc28j60_net *priv,
 355                                        u8 address, u16 data)
 356 {
 357         mutex_lock(&priv->lock);
 358         nolock_regw_write(priv, address, data);
 359         mutex_unlock(&priv->lock);
 360 }
 361
 362 /*
 363  * Buffer memory read
 364  * Select the starting address and execute a SPI buffer read
 365  */
 366 static void enc28j60_mem_read(struct enc28j60_net *priv,
 367                                      u16 addr, int len, u8 *data)
 368 {
 369         mutex_lock(&priv->lock);
 370         nolock_regw_write(priv, ERDPTL, addr);
 371 #ifdef CONFIG_ENC28J60_WRITEVERIFY
 372         if (netif_msg_drv(priv)) {
 373                 u16 reg;
 374                 reg = nolock_regw_read(priv, ERDPTL);
 375                 if (reg != addr)
 376                         printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
 377                                 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
 378         }
 379 #endif
 380         spi_read_buf(priv, len, data);
 381         mutex_unlock(&priv->lock);
 382 }
 383
 384 /*
 385  * Write packet to enc28j60 TX buffer memory
 386  */
 387 static void
 388 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
 389 {
 390         mutex_lock(&priv->lock);
 391         /* Set the write pointer to start of transmit buffer area */
 392         nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
 393 #ifdef CONFIG_ENC28J60_WRITEVERIFY
 394         if (netif_msg_drv(priv)) {
 395                 u16 reg;
 396                 reg = nolock_regw_read(priv, EWRPTL);
 397                 if (reg != TXSTART_INIT)
 398                         printk(KERN_DEBUG DRV_NAME
 399                                 ": %s() ERWPT:0x%04x != 0x%04x\n",
 400                                 __func__, reg, TXSTART_INIT);
 401         }
 402 #endif
 403         /* Set the TXND pointer to correspond to the packet size given */
 404         nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
 405         /* write per-packet control byte */
 406         spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
 407         if (netif_msg_hw(priv))
 408                 printk(KERN_DEBUG DRV_NAME
 409                         ": %s() after control byte ERWPT:0x%04x\n",
 410                         __func__, nolock_regw_read(priv, EWRPTL));
 411         /* copy the packet into the transmit buffer */
 412         spi_write_buf(priv, len, data);
 413         if (netif_msg_hw(priv))
 414                 printk(KERN_DEBUG DRV_NAME
 415                          ": %s() after write packet ERWPT:0x%04x, len=%d\n",
 416                          __func__, nolock_regw_read(priv, EWRPTL), len);
 417         mutex_unlock(&priv->lock);
 418 }
 419
 420 static unsigned long msec20_to_jiffies;
 421
 422 static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
 423 {
 424         unsigned long timeout = jiffies + msec20_to_jiffies;
 425
 426         /* 20 msec timeout read */
 427         while ((nolock_regb_read(priv, reg) & mask) != val) {
 428                 if (time_after(jiffies, timeout)) {
 429                         if (netif_msg_drv(priv))
 430                                 dev_dbg(&priv->spi->dev,
 431                                         "reg %02x ready timeout!\n", reg);
 432                         return -ETIMEDOUT;
 433                 }
 434                 cpu_relax();
 435         }
 436         return 0;
 437 }
 438
 439 /*
 440  * Wait until the PHY operation is complete.
 441  */
 442 static int wait_phy_ready(struct enc28j60_net *priv)
 443 {
 444         return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
 445 }
 446
 447 /*
 448  * PHY register read
 449  * PHY registers are not accessed directly, but through the MII
 450  */
 451 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
 452 {
 453         u16 ret;
 454
 455         mutex_lock(&priv->lock);
 456         /* set the PHY register address */
 457         nolock_regb_write(priv, MIREGADR, address);
 458         /* start the register read operation */
 459         nolock_regb_write(priv, MICMD, MICMD_MIIRD);
 460         /* wait until the PHY read completes */
 461         wait_phy_ready(priv);
 462         /* quit reading */
 463         nolock_regb_write(priv, MICMD, 0x00);
 464         /* return the data */
 465         ret  = nolock_regw_read(priv, MIRDL);
 466         mutex_unlock(&priv->lock);
 467
 468         return ret;
 469 }
 470
 471 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
 472 {
 473         int ret;
 474
 475         mutex_lock(&priv->lock);
 476         /* set the PHY register address */
 477         nolock_regb_write(priv, MIREGADR, address);
 478         /* write the PHY data */
 479         nolock_regw_write(priv, MIWRL, data);
 480         /* wait until the PHY write completes and return */
 481         ret = wait_phy_ready(priv);
 482         mutex_unlock(&priv->lock);
 483
 484         return ret;
 485 }
 486
 487 /*
 488  * Program the hardware MAC address from dev->dev_addr.
 489  */
 490 static int enc28j60_set_hw_macaddr(struct net_device *ndev)
 491 {
 492         int ret;
 493         struct enc28j60_net *priv = netdev_priv(ndev);
 494
 495         mutex_lock(&priv->lock);
 496         if (!priv->hw_enable) {
 497                 if (netif_msg_drv(priv))
 498                         printk(KERN_INFO DRV_NAME
 499                                 ": %s: Setting MAC address to %pM\n",
 500                                 ndev->name, ndev->dev_addr);
 501                 /* NOTE: MAC address in ENC28J60 is byte-backward */
 502                 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
 503                 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
 504                 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
 505                 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
 506                 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
 507                 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
 508                 ret = 0;
 509         } else {
 510                 if (netif_msg_drv(priv))
 511                         printk(KERN_DEBUG DRV_NAME
 512                                 ": %s() Hardware must be disabled to set "
 513                                 "Mac address\n", __func__);
 514                 ret = -EBUSY;
 515         }
 516         mutex_unlock(&priv->lock);
 517         return ret;
 518 }
 519
 520 /*
 521  * Store the new hardware address in dev->dev_addr, and update the MAC.
 522  */
 523 static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
 524 {
 525         struct sockaddr *address = addr;
 526
 527         if (netif_running(dev))
 528                 return -EBUSY;
 529         if (!is_valid_ether_addr(address->sa_data))
 530                 return -EADDRNOTAVAIL;
 531
 532         memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
 533         return enc28j60_set_hw_macaddr(dev);
 534 }
 535
 536 /*
 537  * Debug routine to dump useful register contents
 538  */
 539 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
 540 {
 541         mutex_lock(&priv->lock);
 542         printk(KERN_DEBUG DRV_NAME " %s\n"
 543                 "HwRevID: 0x%02x\n"
 544                 "Cntrl: ECON1 ECON2 ESTAT  EIR  EIE\n"
 545                 "       0x%02x  0x%02x  0x%02x  0x%02x  0x%02x\n"
 546                 "MAC  : MACON1 MACON3 MACON4\n"
 547                 "       0x%02x   0x%02x   0x%02x\n"
 548                 "Rx   : ERXST  ERXND  ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
 549                 "       0x%04x 0x%04x 0x%04x  0x%04x  "
 550                 "0x%02x    0x%02x    0x%04x\n"
 551                 "Tx   : ETXST  ETXND  MACLCON1 MACLCON2 MAPHSUP\n"
 552                 "       0x%04x 0x%04x 0x%02x     0x%02x     0x%02x\n",
 553                 msg, nolock_regb_read(priv, EREVID),
 554                 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
 555                 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
 556                 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
 557                 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
 558                 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
 559                 nolock_regw_read(priv, ERXWRPTL),
 560                 nolock_regw_read(priv, ERXRDPTL),
 561                 nolock_regb_read(priv, ERXFCON),
 562                 nolock_regb_read(priv, EPKTCNT),
 563                 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
 564                 nolock_regw_read(priv, ETXNDL),
 565                 nolock_regb_read(priv, MACLCON1),
 566                 nolock_regb_read(priv, MACLCON2),
 567                 nolock_regb_read(priv, MAPHSUP));
 568         mutex_unlock(&priv->lock);
 569 }
 570
 571 /*
 572  * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
 573  */
 574 static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
 575 {
 576         u16 erxrdpt;
 577
 578         if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
 579                 erxrdpt = end;
 580         else
 581                 erxrdpt = next_packet_ptr - 1;
 582
 583         return erxrdpt;
 584 }
 585
 586 /*
 587  * Calculate wrap around when reading beyond the end of the RX buffer
 588  */
 589 static u16 rx_packet_start(u16 ptr)
 590 {
 591         if (ptr + RSV_SIZE > RXEND_INIT)
 592                 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
 593         else
 594                 return ptr + RSV_SIZE;
 595 }
 596
 597 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
 598 {
 599         u16 erxrdpt;
 600
 601         if (start > 0x1FFF || end > 0x1FFF || start > end) {
 602                 if (netif_msg_drv(priv))
 603                         printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
 604                                 "bad parameters!\n", __func__, start, end);
 605                 return;
 606         }
 607         /* set receive buffer start + end */
 608         priv->next_pk_ptr = start;
 609         nolock_regw_write(priv, ERXSTL, start);
 610         erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
 611         nolock_regw_write(priv, ERXRDPTL, erxrdpt);
 612         nolock_regw_write(priv, ERXNDL, end);
 613 }
 614
 615 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
 616 {
 617         if (start > 0x1FFF || end > 0x1FFF || start > end) {
 618                 if (netif_msg_drv(priv))
 619                         printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
 620                                 "bad parameters!\n", __func__, start, end);
 621                 return;
 622         }
 623         /* set transmit buffer start + end */
 624         nolock_regw_write(priv, ETXSTL, start);
 625         nolock_regw_write(priv, ETXNDL, end);
 626 }
 627
 628 /*
 629  * Low power mode shrinks power consumption about 100x, so we'd like
 630  * the chip to be in that mode whenever it's inactive.  (However, we
 631  * can't stay in lowpower mode during suspend with WOL active.)
 632  */
 633 static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
 634 {
 635         if (netif_msg_drv(priv))
 636                 dev_dbg(&priv->spi->dev, "%s power...\n",
 637                                 is_low ? "low" : "high");
 638
 639         mutex_lock(&priv->lock);
 640         if (is_low) {
 641                 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 642                 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
 643                 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
 644                 /* ECON2_VRPS was set during initialization */
 645                 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
 646         } else {
 647                 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
 648                 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
 649                 /* caller sets ECON1_RXEN */
 650         }
 651         mutex_unlock(&priv->lock);
 652 }
 653
 654 static int enc28j60_hw_init(struct enc28j60_net *priv)
 655 {
 656         u8 reg;
 657
 658         if (netif_msg_drv(priv))
 659                 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
 660                         priv->full_duplex ? "FullDuplex" : "HalfDuplex");
 661
 662         mutex_lock(&priv->lock);
 663         /* first reset the chip */
 664         enc28j60_soft_reset(priv);
 665         /* Clear ECON1 */
 666         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
 667         priv->bank = 0;
 668         priv->hw_enable = false;
 669         priv->tx_retry_count = 0;
 670         priv->max_pk_counter = 0;
 671         priv->rxfilter = RXFILTER_NORMAL;
 672         /* enable address auto increment and voltage regulator powersave */
 673         nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
 674
 675         nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
 676         nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
 677         mutex_unlock(&priv->lock);
 678
 679         /*
 680          * Check the RevID.
 681          * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
 682          * damaged
 683          */
 684         reg = locked_regb_read(priv, EREVID);
 685         if (netif_msg_drv(priv))
 686                 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
 687         if (reg == 0x00 || reg == 0xff) {
 688                 if (netif_msg_drv(priv))
 689                         printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
 690                                 __func__, reg);
 691                 return 0;
 692         }
 693
 694         /* default filter mode: (unicast OR broadcast) AND crc valid */
 695         locked_regb_write(priv, ERXFCON,
 696                             ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
 697
 698         /* enable MAC receive */
 699         locked_regb_write(priv, MACON1,
 700                             MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
 701         /* enable automatic padding and CRC operations */
 702         if (priv->full_duplex) {
 703                 locked_regb_write(priv, MACON3,
 704                                     MACON3_PADCFG0 | MACON3_TXCRCEN |
 705                                     MACON3_FRMLNEN | MACON3_FULDPX);
 706                 /* set inter-frame gap (non-back-to-back) */
 707                 locked_regb_write(priv, MAIPGL, 0x12);
 708                 /* set inter-frame gap (back-to-back) */
 709                 locked_regb_write(priv, MABBIPG, 0x15);
 710         } else {
 711                 locked_regb_write(priv, MACON3,
 712                                     MACON3_PADCFG0 | MACON3_TXCRCEN |
 713                                     MACON3_FRMLNEN);
 714                 locked_regb_write(priv, MACON4, 1 << 6);        /* DEFER bit */
 715                 /* set inter-frame gap (non-back-to-back) */
 716                 locked_regw_write(priv, MAIPGL, 0x0C12);
 717                 /* set inter-frame gap (back-to-back) */
 718                 locked_regb_write(priv, MABBIPG, 0x12);
 719         }
 720         /*
 721          * MACLCON1 (default)
 722          * MACLCON2 (default)
 723          * Set the maximum packet size which the controller will accept
 724          */
 725         locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
 726
 727         /* Configure LEDs */
 728         if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
 729                 return 0;
 730
 731         if (priv->full_duplex) {
 732                 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
 733                         return 0;
 734                 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
 735                         return 0;
 736         } else {
 737                 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
 738                         return 0;
 739                 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
 740                         return 0;
 741         }
 742         if (netif_msg_hw(priv))
 743                 enc28j60_dump_regs(priv, "Hw initialized.");
 744
 745         return 1;
 746 }
 747
 748 static void enc28j60_hw_enable(struct enc28j60_net *priv)
 749 {
 750         /* enable interrupts */
 751         if (netif_msg_hw(priv))
 752                 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
 753                         __func__);
 754
 755         enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
 756
 757         mutex_lock(&priv->lock);
 758         nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
 759                          EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
 760         nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
 761                           EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
 762
 763         /* enable receive logic */
 764         nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
 765         priv->hw_enable = true;
 766         mutex_unlock(&priv->lock);
 767 }
 768
 769 static void enc28j60_hw_disable(struct enc28j60_net *priv)
 770 {
 771         mutex_lock(&priv->lock);
 772         /* disable interrutps and packet reception */
 773         nolock_regb_write(priv, EIE, 0x00);
 774         nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 775         priv->hw_enable = false;
 776         mutex_unlock(&priv->lock);
 777 }
 778
 779 static int
 780 enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
 781 {
 782         struct enc28j60_net *priv = netdev_priv(ndev);
 783         int ret = 0;
 784
 785         if (!priv->hw_enable) {
 786                 /* link is in low power mode now; duplex setting
 787                  * will take effect on next enc28j60_hw_init().
 788                  */
 789                 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
 790                         priv->full_duplex = (duplex == DUPLEX_FULL);
 791                 else {
 792                         if (netif_msg_link(priv))
 793                                 dev_warn(&ndev->dev,
 794                                         "unsupported link setting\n");
 795                         ret = -EOPNOTSUPP;
 796                 }
 797         } else {
 798                 if (netif_msg_link(priv))
 799                         dev_warn(&ndev->dev, "Warning: hw must be disabled "
 800                                 "to set link mode\n");
 801                 ret = -EBUSY;
 802         }
 803         return ret;
 804 }
 805
 806 /*
 807  * Read the Transmit Status Vector
 808  */
 809 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
 810 {
 811         int endptr;
 812
 813         endptr = locked_regw_read(priv, ETXNDL);
 814         if (netif_msg_hw(priv))
 815                 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
 816                          endptr + 1);
 817         enc28j60_mem_read(priv, endptr + 1, sizeof(tsv), tsv);
 818 }
 819
 820 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
 821                                 u8 tsv[TSV_SIZE])
 822 {
 823         u16 tmp1, tmp2;
 824
 825         printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
 826         tmp1 = tsv[1];
 827         tmp1 <<= 8;
 828         tmp1 |= tsv[0];
 829
 830         tmp2 = tsv[5];
 831         tmp2 <<= 8;
 832         tmp2 |= tsv[4];
 833
 834         printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
 835                 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
 836         printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
 837                 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
 838                 TSV_GETBIT(tsv, TSV_TXCRCERROR),
 839                 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
 840                 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
 841         printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
 842                 "PacketDefer: %d, ExDefer: %d\n",
 843                 TSV_GETBIT(tsv, TSV_TXMULTICAST),
 844                 TSV_GETBIT(tsv, TSV_TXBROADCAST),
 845                 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
 846                 TSV_GETBIT(tsv, TSV_TXEXDEFER));
 847         printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
 848                  "Giant: %d, Underrun: %d\n",
 849                  TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
 850                  TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
 851                  TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
 852         printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
 853                  "BackPressApp: %d, VLanTagFrame: %d\n",
 854                  TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
 855                  TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
 856                  TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
 857                  TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
 858 }
 859
 860 /*
 861  * Receive Status vector
 862  */
 863 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
 864                               u16 pk_ptr, int len, u16 sts)
 865 {
 866         printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
 867                 msg, pk_ptr);
 868         printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
 869                  RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
 870         printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
 871                  " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
 872                  RSV_GETBIT(sts, RSV_CRCERROR),
 873                  RSV_GETBIT(sts, RSV_LENCHECKERR),
 874                  RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
 875         printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
 876                  "LongDropEvent: %d, CarrierEvent: %d\n",
 877                  RSV_GETBIT(sts, RSV_RXMULTICAST),
 878                  RSV_GETBIT(sts, RSV_RXBROADCAST),
 879                  RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
 880                  RSV_GETBIT(sts, RSV_CARRIEREV));
 881         printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
 882                  " UnknownOp: %d, VLanTagFrame: %d\n",
 883                  RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
 884                  RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
 885                  RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
 886                  RSV_GETBIT(sts, RSV_RXTYPEVLAN));
 887 }
 888
 889 static void dump_packet(const char *msg, int len, const char *data)
 890 {
 891         printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
 892         print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
 893                         data, len, true);
 894 }
 895
 896 /*
 897  * Hardware receive function.
 898  * Read the buffer memory, update the FIFO pointer to free the buffer,
 899  * check the status vector and decrement the packet counter.
 900  */
 901 static void enc28j60_hw_rx(struct net_device *ndev)
 902 {
 903         struct enc28j60_net *priv = netdev_priv(ndev);
 904         struct sk_buff *skb = NULL;
 905         u16 erxrdpt, next_packet, rxstat;
 906         u8 rsv[RSV_SIZE];
 907         int len;
 908
 909         if (netif_msg_rx_status(priv))
 910                 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
 911                         priv->next_pk_ptr);
 912
 913         if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
 914                 if (netif_msg_rx_err(priv))
 915                         dev_err(&ndev->dev,
 916                                 "%s() Invalid packet address!! 0x%04x\n",
 917                                 __func__, priv->next_pk_ptr);
 918                 /* packet address corrupted: reset RX logic */
 919                 mutex_lock(&priv->lock);
 920                 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 921                 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
 922                 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
 923                 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
 924                 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
 925                 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
 926                 mutex_unlock(&priv->lock);
 927                 ndev->stats.rx_errors++;
 928                 return;
 929         }
 930         /* Read next packet pointer and rx status vector */
 931         enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
 932
 933         next_packet = rsv[1];
 934         next_packet <<= 8;
 935         next_packet |= rsv[0];
 936
 937         len = rsv[3];
 938         len <<= 8;
 939         len |= rsv[2];
 940
 941         rxstat = rsv[5];
 942         rxstat <<= 8;
 943         rxstat |= rsv[4];
 944
 945         if (netif_msg_rx_status(priv))
 946                 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
 947
 948         if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
 949                 if (netif_msg_rx_err(priv))
 950                         dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
 951                 ndev->stats.rx_errors++;
 952                 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
 953                         ndev->stats.rx_crc_errors++;
 954                 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
 955                         ndev->stats.rx_frame_errors++;
 956                 if (len > MAX_FRAMELEN)
 957                         ndev->stats.rx_over_errors++;
 958         } else {
 959                 skb = dev_alloc_skb(len + NET_IP_ALIGN);
 960                 if (!skb) {
 961                         if (netif_msg_rx_err(priv))
 962                                 dev_err(&ndev->dev,
 963                                         "out of memory for Rx'd frame\n");
 964                         ndev->stats.rx_dropped++;
 965                 } else {
 966                         skb->dev = ndev;
 967                         skb_reserve(skb, NET_IP_ALIGN);
 968                         /* copy the packet from the receive buffer */
 969                         enc28j60_mem_read(priv,
 970                                 rx_packet_start(priv->next_pk_ptr),
 971                                 len, skb_put(skb, len));
 972                         if (netif_msg_pktdata(priv))
 973                                 dump_packet(__func__, skb->len, skb->data);
 974                         skb->protocol = eth_type_trans(skb, ndev);
 975                         /* update statistics */
 976                         ndev->stats.rx_packets++;
 977                         ndev->stats.rx_bytes += len;
 978                         netif_rx_ni(skb);
 979                 }
 980         }
 981         /*
 982          * Move the RX read pointer to the start of the next
 983          * received packet.
 984          * This frees the memory we just read out
 985          */
 986         erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
 987         if (netif_msg_hw(priv))
 988                 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
 989                         __func__, erxrdpt);
 990
 991         mutex_lock(&priv->lock);
 992         nolock_regw_write(priv, ERXRDPTL, erxrdpt);
 993 #ifdef CONFIG_ENC28J60_WRITEVERIFY
 994         if (netif_msg_drv(priv)) {
 995                 u16 reg;
 996                 reg = nolock_regw_read(priv, ERXRDPTL);
 997                 if (reg != erxrdpt)
 998                         printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
 999                                 "error (0x%04x - 0x%04x)\n", __func__,
1000                                 reg, erxrdpt);
1001         }
1002 #endif
1003         priv->next_pk_ptr = next_packet;
1004         /* we are done with this packet, decrement the packet counter */
1005         nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1006         mutex_unlock(&priv->lock);
1007 }
1008
1009 /*
1010  * Calculate free space in RxFIFO
1011  */
1012 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1013 {
1014         int epkcnt, erxst, erxnd, erxwr, erxrd;
1015         int free_space;
1016
1017         mutex_lock(&priv->lock);
1018         epkcnt = nolock_regb_read(priv, EPKTCNT);
1019         if (epkcnt >= 255)
1020                 free_space = -1;
1021         else {
1022                 erxst = nolock_regw_read(priv, ERXSTL);
1023                 erxnd = nolock_regw_read(priv, ERXNDL);
1024                 erxwr = nolock_regw_read(priv, ERXWRPTL);
1025                 erxrd = nolock_regw_read(priv, ERXRDPTL);
1026
1027                 if (erxwr > erxrd)
1028                         free_space = (erxnd - erxst) - (erxwr - erxrd);
1029                 else if (erxwr == erxrd)
1030                         free_space = (erxnd - erxst);
1031                 else
1032                         free_space = erxrd - erxwr - 1;
1033         }
1034         mutex_unlock(&priv->lock);
1035         if (netif_msg_rx_status(priv))
1036                 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
1037                         __func__, free_space);
1038         return free_space;
1039 }
1040
1041 /*
1042  * Access the PHY to determine link status
1043  */
1044 static void enc28j60_check_link_status(struct net_device *ndev)
1045 {
1046         struct enc28j60_net *priv = netdev_priv(ndev);
1047         u16 reg;
1048         int duplex;
1049
1050         reg = enc28j60_phy_read(priv, PHSTAT2);
1051         if (netif_msg_hw(priv))
1052                 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1053                         "PHSTAT2: %04x\n", __func__,
1054                         enc28j60_phy_read(priv, PHSTAT1), reg);
1055         duplex = reg & PHSTAT2_DPXSTAT;
1056
1057         if (reg & PHSTAT2_LSTAT) {
1058                 netif_carrier_on(ndev);
1059                 if (netif_msg_ifup(priv))
1060                         dev_info(&ndev->dev, "link up - %s\n",
1061                                 duplex ? "Full duplex" : "Half duplex");
1062         } else {
1063                 if (netif_msg_ifdown(priv))
1064                         dev_info(&ndev->dev, "link down\n");
1065                 netif_carrier_off(ndev);
1066         }
1067 }
1068
1069 static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1070 {
1071         struct enc28j60_net *priv = netdev_priv(ndev);
1072
1073         if (err)
1074                 ndev->stats.tx_errors++;
1075         else
1076                 ndev->stats.tx_packets++;
1077
1078         if (priv->tx_skb) {
1079                 if (!err)
1080                         ndev->stats.tx_bytes += priv->tx_skb->len;
1081                 dev_kfree_skb(priv->tx_skb);
1082                 priv->tx_skb = NULL;
1083         }
1084         locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1085         netif_wake_queue(ndev);
1086 }
1087
1088 /*
1089  * RX handler
1090  * ignore PKTIF because is unreliable! (look at the errata datasheet)
1091  * check EPKTCNT is the suggested workaround.
1092  * We don't need to clear interrupt flag, automatically done when
1093  * enc28j60_hw_rx() decrements the packet counter.
1094  * Returns how many packet processed.
1095  */
1096 static int enc28j60_rx_interrupt(struct net_device *ndev)
1097 {
1098         struct enc28j60_net *priv = netdev_priv(ndev);
1099         int pk_counter, ret;
1100
1101         pk_counter = locked_regb_read(priv, EPKTCNT);
1102         if (pk_counter && netif_msg_intr(priv))
1103                 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1104         if (pk_counter > priv->max_pk_counter) {
1105                 /* update statistics */
1106                 priv->max_pk_counter = pk_counter;
1107                 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1108                         printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1109                                 priv->max_pk_counter);
1110         }
1111         ret = pk_counter;
1112         while (pk_counter-- > 0)
1113                 enc28j60_hw_rx(ndev);
1114
1115         return ret;
1116 }
1117
1118 static void enc28j60_irq_work_handler(struct work_struct *work)
1119 {
1120         struct enc28j60_net *priv =
1121                 container_of(work, struct enc28j60_net, irq_work);
1122         struct net_device *ndev = priv->netdev;
1123         int intflags, loop;
1124
1125         if (netif_msg_intr(priv))
1126                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1127         /* disable further interrupts */
1128         locked_reg_bfclr(priv, EIE, EIE_INTIE);
1129
1130         do {
1131                 loop = 0;
1132                 intflags = locked_regb_read(priv, EIR);
1133                 /* DMA interrupt handler (not currently used) */
1134                 if ((intflags & EIR_DMAIF) != 0) {
1135                         loop++;
1136                         if (netif_msg_intr(priv))
1137                                 printk(KERN_DEBUG DRV_NAME
1138                                         ": intDMA(%d)\n", loop);
1139                         locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1140                 }
1141                 /* LINK changed handler */
1142                 if ((intflags & EIR_LINKIF) != 0) {
1143                         loop++;
1144                         if (netif_msg_intr(priv))
1145                                 printk(KERN_DEBUG DRV_NAME
1146                                         ": intLINK(%d)\n", loop);
1147                         enc28j60_check_link_status(ndev);
1148                         /* read PHIR to clear the flag */
1149                         enc28j60_phy_read(priv, PHIR);
1150                 }
1151                 /* TX complete handler */
1152                 if ((intflags & EIR_TXIF) != 0) {
1153                         bool err = false;
1154                         loop++;
1155                         if (netif_msg_intr(priv))
1156                                 printk(KERN_DEBUG DRV_NAME
1157                                         ": intTX(%d)\n", loop);
1158                         priv->tx_retry_count = 0;
1159                         if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1160                                 if (netif_msg_tx_err(priv))
1161                                         dev_err(&ndev->dev,
1162                                                 "Tx Error (aborted)\n");
1163                                 err = true;
1164                         }
1165                         if (netif_msg_tx_done(priv)) {
1166                                 u8 tsv[TSV_SIZE];
1167                                 enc28j60_read_tsv(priv, tsv);
1168                                 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1169                         }
1170                         enc28j60_tx_clear(ndev, err);
1171                         locked_reg_bfclr(priv, EIR, EIR_TXIF);
1172                 }
1173                 /* TX Error handler */
1174                 if ((intflags & EIR_TXERIF) != 0) {
1175                         u8 tsv[TSV_SIZE];
1176
1177                         loop++;
1178                         if (netif_msg_intr(priv))
1179                                 printk(KERN_DEBUG DRV_NAME
1180                                         ": intTXErr(%d)\n", loop);
1181                         locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1182                         enc28j60_read_tsv(priv, tsv);
1183                         if (netif_msg_tx_err(priv))
1184                                 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1185                         /* Reset TX logic */
1186                         mutex_lock(&priv->lock);
1187                         nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1188                         nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1189                         nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1190                         mutex_unlock(&priv->lock);
1191                         /* Transmit Late collision check for retransmit */
1192                         if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1193                                 if (netif_msg_tx_err(priv))
1194                                         printk(KERN_DEBUG DRV_NAME
1195                                                 ": LateCollision TXErr (%d)\n",
1196                                                 priv->tx_retry_count);
1197                                 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1198                                         locked_reg_bfset(priv, ECON1,
1199                                                            ECON1_TXRTS);
1200                                 else
1201                                         enc28j60_tx_clear(ndev, true);
1202                         } else
1203                                 enc28j60_tx_clear(ndev, true);
1204                         locked_reg_bfclr(priv, EIR, EIR_TXERIF);
1205                 }
1206                 /* RX Error handler */
1207                 if ((intflags & EIR_RXERIF) != 0) {
1208                         loop++;
1209                         if (netif_msg_intr(priv))
1210                                 printk(KERN_DEBUG DRV_NAME
1211                                         ": intRXErr(%d)\n", loop);
1212                         /* Check free FIFO space to flag RX overrun */
1213                         if (enc28j60_get_free_rxfifo(priv) <= 0) {
1214                                 if (netif_msg_rx_err(priv))
1215                                         printk(KERN_DEBUG DRV_NAME
1216                                                 ": RX Overrun\n");
1217                                 ndev->stats.rx_dropped++;
1218                         }
1219                         locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1220                 }
1221                 /* RX handler */
1222                 if (enc28j60_rx_interrupt(ndev))
1223                         loop++;
1224         } while (loop);
1225
1226         /* re-enable interrupts */
1227         locked_reg_bfset(priv, EIE, EIE_INTIE);
1228         if (netif_msg_intr(priv))
1229                 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
1230 }
1231
1232 /*
1233  * Hardware transmit function.
1234  * Fill the buffer memory and send the contents of the transmit buffer
1235  * onto the network
1236  */
1237 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1238 {
1239         if (netif_msg_tx_queued(priv))
1240                 printk(KERN_DEBUG DRV_NAME
1241                         ": Tx Packet Len:%d\n", priv->tx_skb->len);
1242
1243         if (netif_msg_pktdata(priv))
1244                 dump_packet(__func__,
1245                             priv->tx_skb->len, priv->tx_skb->data);
1246         enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1247
1248 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1249         /* readback and verify written data */
1250         if (netif_msg_drv(priv)) {
1251                 int test_len, k;
1252                 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1253                 int okflag;
1254
1255                 test_len = priv->tx_skb->len;
1256                 if (test_len > sizeof(test_buf))
1257                         test_len = sizeof(test_buf);
1258
1259                 /* + 1 to skip control byte */
1260                 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1261                 okflag = 1;
1262                 for (k = 0; k < test_len; k++) {
1263                         if (priv->tx_skb->data[k] != test_buf[k]) {
1264                                 printk(KERN_DEBUG DRV_NAME
1265                                          ": Error, %d location differ: "
1266                                          "0x%02x-0x%02x\n", k,
1267                                          priv->tx_skb->data[k], test_buf[k]);
1268                                 okflag = 0;
1269                         }
1270                 }
1271                 if (!okflag)
1272                         printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1273                                 "verify ERROR!\n");
1274         }
1275 #endif
1276         /* set TX request flag */
1277         locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1278 }
1279
1280 static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1281                                         struct net_device *dev)
1282 {
1283         struct enc28j60_net *priv = netdev_priv(dev);
1284
1285         if (netif_msg_tx_queued(priv))
1286                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1287
1288         /* If some error occurs while trying to transmit this
1289          * packet, you should return '1' from this function.
1290          * In such a case you _may not_ do anything to the
1291          * SKB, it is still owned by the network queueing
1292          * layer when an error is returned.  This means you
1293          * may not modify any SKB fields, you may not free
1294          * the SKB, etc.
1295          */
1296         netif_stop_queue(dev);
1297
1298         /* Remember the skb for deferred processing */
1299         priv->tx_skb = skb;
1300         schedule_work(&priv->tx_work);
1301
1302         return NETDEV_TX_OK;
1303 }
1304
1305 static void enc28j60_tx_work_handler(struct work_struct *work)
1306 {
1307         struct enc28j60_net *priv =
1308                 container_of(work, struct enc28j60_net, tx_work);
1309
1310         /* actual delivery of data */
1311         enc28j60_hw_tx(priv);
1312 }
1313
1314 static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1315 {
1316         struct enc28j60_net *priv = dev_id;
1317
1318         /*
1319          * Can't do anything in interrupt context because we need to
1320          * block (spi_sync() is blocking) so fire of the interrupt
1321          * handling workqueue.
1322          * Remember that we access enc28j60 registers through SPI bus
1323          * via spi_sync() call.
1324          */
1325         schedule_work(&priv->irq_work);
1326
1327         return IRQ_HANDLED;
1328 }
1329
1330 static void enc28j60_tx_timeout(struct net_device *ndev)
1331 {
1332         struct enc28j60_net *priv = netdev_priv(ndev);
1333
1334         if (netif_msg_timer(priv))
1335                 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1336
1337         ndev->stats.tx_errors++;
1338         /* can't restart safely under softirq */
1339         schedule_work(&priv->restart_work);
1340 }
1341
1342 /*
1343  * Open/initialize the board. This is called (in the current kernel)
1344  * sometime after booting when the 'ifconfig' program is run.
1345  *
1346  * This routine should set everything up anew at each open, even
1347  * registers that "should" only need to be set once at boot, so that
1348  * there is non-reboot way to recover if something goes wrong.
1349  */
1350 static int enc28j60_net_open(struct net_device *dev)
1351 {
1352         struct enc28j60_net *priv = netdev_priv(dev);
1353
1354         if (netif_msg_drv(priv))
1355                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1356
1357         if (!is_valid_ether_addr(dev->dev_addr)) {
1358                 if (netif_msg_ifup(priv))
1359                         dev_err(&dev->dev, "invalid MAC address %pM\n",
1360                                 dev->dev_addr);
1361                 return -EADDRNOTAVAIL;
1362         }
1363         /* Reset the hardware here (and take it out of low power mode) */
1364         enc28j60_lowpower(priv, false);
1365         enc28j60_hw_disable(priv);
1366         if (!enc28j60_hw_init(priv)) {
1367                 if (netif_msg_ifup(priv))
1368                         dev_err(&dev->dev, "hw_reset() failed\n");
1369                 return -EINVAL;
1370         }
1371         /* Update the MAC address (in case user has changed it) */
1372         enc28j60_set_hw_macaddr(dev);
1373         /* Enable interrupts */
1374         enc28j60_hw_enable(priv);
1375         /* check link status */
1376         enc28j60_check_link_status(dev);
1377         /* We are now ready to accept transmit requests from
1378          * the queueing layer of the networking.
1379          */
1380         netif_start_queue(dev);
1381
1382         return 0;
1383 }
1384
1385 /* The inverse routine to net_open(). */
1386 static int enc28j60_net_close(struct net_device *dev)
1387 {
1388         struct enc28j60_net *priv = netdev_priv(dev);
1389
1390         if (netif_msg_drv(priv))
1391                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1392
1393         enc28j60_hw_disable(priv);
1394         enc28j60_lowpower(priv, true);
1395         netif_stop_queue(dev);
1396
1397         return 0;
1398 }
1399
1400 /*
1401  * Set or clear the multicast filter for this adapter
1402  * num_addrs == -1      Promiscuous mode, receive all packets
1403  * num_addrs == 0       Normal mode, filter out multicast packets
1404  * num_addrs > 0        Multicast mode, receive normal and MC packets
1405  */
1406 static void enc28j60_set_multicast_list(struct net_device *dev)
1407 {
1408         struct enc28j60_net *priv = netdev_priv(dev);
1409         int oldfilter = priv->rxfilter;
1410
1411         if (dev->flags & IFF_PROMISC) {
1412                 if (netif_msg_link(priv))
1413                         dev_info(&dev->dev, "promiscuous mode\n");
1414                 priv->rxfilter = RXFILTER_PROMISC;
1415         } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1416                 if (netif_msg_link(priv))
1417                         dev_info(&dev->dev, "%smulticast mode\n",
1418                                 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1419                 priv->rxfilter = RXFILTER_MULTI;
1420         } else {
1421                 if (netif_msg_link(priv))
1422                         dev_info(&dev->dev, "normal mode\n");
1423                 priv->rxfilter = RXFILTER_NORMAL;
1424         }
1425
1426         if (oldfilter != priv->rxfilter)
1427                 schedule_work(&priv->setrx_work);
1428 }
1429
1430 static void enc28j60_setrx_work_handler(struct work_struct *work)
1431 {
1432         struct enc28j60_net *priv =
1433                 container_of(work, struct enc28j60_net, setrx_work);
1434
1435         if (priv->rxfilter == RXFILTER_PROMISC) {
1436                 if (netif_msg_drv(priv))
1437                         printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1438                 locked_regb_write(priv, ERXFCON, 0x00);
1439         } else if (priv->rxfilter == RXFILTER_MULTI) {
1440                 if (netif_msg_drv(priv))
1441                         printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1442                 locked_regb_write(priv, ERXFCON,
1443                                         ERXFCON_UCEN | ERXFCON_CRCEN |
1444                                         ERXFCON_BCEN | ERXFCON_MCEN);
1445         } else {
1446                 if (netif_msg_drv(priv))
1447                         printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1448                 locked_regb_write(priv, ERXFCON,
1449                                         ERXFCON_UCEN | ERXFCON_CRCEN |
1450                                         ERXFCON_BCEN);
1451         }
1452 }
1453
1454 static void enc28j60_restart_work_handler(struct work_struct *work)
1455 {
1456         struct enc28j60_net *priv =
1457                         container_of(work, struct enc28j60_net, restart_work);
1458         struct net_device *ndev = priv->netdev;
1459         int ret;
1460
1461         rtnl_lock();
1462         if (netif_running(ndev)) {
1463                 enc28j60_net_close(ndev);
1464                 ret = enc28j60_net_open(ndev);
1465                 if (unlikely(ret)) {
1466                         dev_info(&ndev->dev, " could not restart %d\n", ret);
1467                         dev_close(ndev);
1468                 }
1469         }
1470         rtnl_unlock();
1471 }
1472
1473 /* ......................... ETHTOOL SUPPORT ........................... */
1474
1475 static void
1476 enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1477 {
1478         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1479         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1480         strlcpy(info->bus_info,
1481                 dev_name(dev->dev.parent), sizeof(info->bus_info));
1482 }
1483
1484 static int
1485 enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1486 {
1487         struct enc28j60_net *priv = netdev_priv(dev);
1488
1489         cmd->transceiver = XCVR_INTERNAL;
1490         cmd->supported  = SUPPORTED_10baseT_Half
1491                         | SUPPORTED_10baseT_Full
1492                         | SUPPORTED_TP;
1493         cmd->speed      = SPEED_10;
1494         cmd->duplex     = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1495         cmd->port       = PORT_TP;
1496         cmd->autoneg    = AUTONEG_DISABLE;
1497
1498         return 0;
1499 }
1500
1501 static int
1502 enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1503 {
1504         return enc28j60_setlink(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1505 }
1506
1507 static u32 enc28j60_get_msglevel(struct net_device *dev)
1508 {
1509         struct enc28j60_net *priv = netdev_priv(dev);
1510         return priv->msg_enable;
1511 }
1512
1513 static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1514 {
1515         struct enc28j60_net *priv = netdev_priv(dev);
1516         priv->msg_enable = val;
1517 }
1518
1519 static const struct ethtool_ops enc28j60_ethtool_ops = {
1520         .get_settings   = enc28j60_get_settings,
1521         .set_settings   = enc28j60_set_settings,
1522         .get_drvinfo    = enc28j60_get_drvinfo,
1523         .get_msglevel   = enc28j60_get_msglevel,
1524         .set_msglevel   = enc28j60_set_msglevel,
1525 };
1526
1527 static int enc28j60_chipset_init(struct net_device *dev)
1528 {
1529         struct enc28j60_net *priv = netdev_priv(dev);
1530
1531         return enc28j60_hw_init(priv);
1532 }
1533
1534 static const struct net_device_ops enc28j60_netdev_ops = {
1535         .ndo_open               = enc28j60_net_open,
1536         .ndo_stop               = enc28j60_net_close,
1537         .ndo_start_xmit         = enc28j60_send_packet,
1538         .ndo_set_multicast_list = enc28j60_set_multicast_list,
1539         .ndo_set_mac_address    = enc28j60_set_mac_address,
1540         .ndo_tx_timeout         = enc28j60_tx_timeout,
1541         .ndo_change_mtu         = eth_change_mtu,
1542         .ndo_validate_addr      = eth_validate_addr,
1543 };
1544
1545 static int __devinit enc28j60_probe(struct spi_device *spi)
1546 {
1547         struct net_device *dev;
1548         struct enc28j60_net *priv;
1549         int ret = 0;
1550         unsigned long req_flags = IRQF_TRIGGER_FALLING;
1551         int gpioToIrq = gpio_to_irq (MAC_INT_PORT);
1552
1553         gpio_request(MAC_INT_PORT, "DRV_NAME");
1554         if (netif_msg_drv(&debug))
1555                 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1556                         DRV_VERSION);
1557
1558         dev = alloc_etherdev(sizeof(struct enc28j60_net));
1559         if (!dev) {
1560                 if (netif_msg_drv(&debug))
1561                         dev_err(&spi->dev, DRV_NAME
1562                                 ": unable to alloc new ethernet\n");
1563                 ret = -ENOMEM;
1564                 goto error_alloc;
1565         }
1566         priv = netdev_priv(dev);
1567
1568         priv->netdev = dev;     /* priv to netdev reference */
1569         priv->spi = spi;        /* priv to spi reference */
1570         priv->msg_enable = netif_msg_init(debug.msg_enable,
1571                                                 ENC28J60_MSG_DEFAULT);
1572         mutex_init(&priv->lock);
1573         INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1574         INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1575         INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1576         INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1577         dev_set_drvdata(&spi->dev, priv);       /* spi to priv reference */
1578         SET_NETDEV_DEV(dev, &spi->dev);
1579
1580         if (!enc28j60_chipset_init(dev)) {
1581                 if (netif_msg_probe(priv))
1582                         dev_info(&spi->dev, DRV_NAME " chip not found\n");
1583                 ret = -EIO;
1584                 goto error_irq;
1585         }
1586         random_ether_addr(dev->dev_addr);
1587         enc28j60_set_hw_macaddr(dev);
1588
1589         /* Board setup must set the relevant edge trigger type;
1590          * level triggers won't currently work.
1591          */
1592         gpio_pull_updown(MAC_INT_PORT, GPIOPullUp);
1593         if(gpioToIrq != -1)
1594                 ret = request_irq(gpioToIrq, enc28j60_irq,req_flags, "DRV_NAME", priv);
1595         else
1596                 ret = -1;
1597
1598         ///ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1599         if (ret < 0) {
1600                 if (netif_msg_probe(priv))
1601                         dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1602                                 "(ret = %d)\n", spi->irq, ret);
1603                 goto error_irq;
1604         }
1605
1606         dev->if_port = IF_PORT_10BASET;
1607         dev->irq = spi->irq;
1608         dev->netdev_ops = &enc28j60_netdev_ops;
1609         dev->watchdog_timeo = TX_TIMEOUT;
1610         SET_ETHTOOL_OPS(dev, &enc28j60_ethtool_ops);
1611
1612         enc28j60_lowpower(priv, true);
1613
1614         ret = register_netdev(dev);
1615         if (ret) {
1616                 if (netif_msg_probe(priv))
1617                         dev_err(&spi->dev, "register netdev " DRV_NAME
1618                                 " failed (ret = %d)\n", ret);
1619                 goto error_register;
1620         }
1621         dev_info(&dev->dev, DRV_NAME " driver registered\n");
1622
1623         return 0;
1624
1625 error_register:
1626         free_irq(spi->irq, priv);
1627 error_irq:
1628         free_netdev(dev);
1629 error_alloc:
1630         return ret;
1631 }
1632
1633 static int __devexit enc28j60_remove(struct spi_device *spi)
1634 {
1635         struct enc28j60_net *priv = dev_get_drvdata(&spi->dev);
1636
1637         if (netif_msg_drv(priv))
1638                 printk(KERN_DEBUG DRV_NAME ": remove\n");
1639
1640         unregister_netdev(priv->netdev);
1641         free_irq(spi->irq, priv);
1642         free_netdev(priv->netdev);
1643
1644         return 0;
1645 }
1646
1647 static struct spi_driver enc28j60_driver = {
1648         .driver = {
1649                    .name = DRV_NAME,
1650                    .owner = THIS_MODULE,
1651          },
1652         .probe = enc28j60_probe,
1653         .remove = __devexit_p(enc28j60_remove),
1654 };
1655
1656 static int __init enc28j60_init(void)
1657 {
1658         msec20_to_jiffies = msecs_to_jiffies(20);
1659
1660         return spi_register_driver(&enc28j60_driver);
1661 }
1662
1663 module_init(enc28j60_init);
1664
1665 static void __exit enc28j60_exit(void)
1666 {
1667         spi_unregister_driver(&enc28j60_driver);
1668 }
1669
1670 module_exit(enc28j60_exit);
1671
1672 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1673 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1674 MODULE_LICENSE("GPL");
1675 module_param_named(debug, debug.msg_enable, int, 0);
1676 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
1677 MODULE_ALIAS("spi:" DRV_NAME);