drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  */
  56
  57 #include "e1000.h"
  58
  59 #define ICH_FLASH_GFPREG                0x0000
  60 #define ICH_FLASH_HSFSTS                0x0004
  61 #define ICH_FLASH_HSFCTL                0x0006
  62 #define ICH_FLASH_FADDR                 0x0008
  63 #define ICH_FLASH_FDATA0                0x0010
  64 #define ICH_FLASH_PR0                   0x0074
  65
  66 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  67 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  68 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  69 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  70 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  71
  72 #define ICH_CYCLE_READ                  0
  73 #define ICH_CYCLE_WRITE                 2
  74 #define ICH_CYCLE_ERASE                 3
  75
  76 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  77 #define FLASH_SECTOR_ADDR_SHIFT         12
  78
  79 #define ICH_FLASH_SEG_SIZE_256          256
  80 #define ICH_FLASH_SEG_SIZE_4K           4096
  81 #define ICH_FLASH_SEG_SIZE_8K           8192
  82 #define ICH_FLASH_SEG_SIZE_64K          65536
  83
  84
  85 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  86 /* FW established a valid mode */
  87 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  88
  89 #define E1000_ICH_MNG_IAMT_MODE         0x2
  90
  91 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  92                                  (ID_LED_DEF1_OFF2 <<  8) | \
  93                                  (ID_LED_DEF1_ON2  <<  4) | \
  94                                  (ID_LED_DEF1_DEF2))
  95
  96 #define E1000_ICH_NVM_SIG_WORD          0x13
  97 #define E1000_ICH_NVM_SIG_MASK          0xC000
  98 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
  99 #define E1000_ICH_NVM_SIG_VALUE         0x80
 100
 101 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 102
 103 #define E1000_FEXTNVM_SW_CONFIG         1
 104 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 105
 106 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 107
 108 #define E1000_ICH_RAR_ENTRIES           7
 109
 110 #define PHY_PAGE_SHIFT 5
 111 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 112                            ((reg) & MAX_PHY_REG_ADDRESS))
 113 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 114 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 115
 116 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 117 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 118 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 119
 120 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 121
 122 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 123
 124 /* SMBus Address Phy Register */
 125 #define HV_SMB_ADDR            PHY_REG(768, 26)
 126 #define HV_SMB_ADDR_PEC_EN     0x0200
 127 #define HV_SMB_ADDR_VALID      0x0080
 128
 129 /* Strapping Option Register - RO */
 130 #define E1000_STRAP                     0x0000C
 131 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 132 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 133
 134 /* OEM Bits Phy Register */
 135 #define HV_OEM_BITS            PHY_REG(768, 25)
 136 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 137 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 138 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 139
 140 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 141 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 142
 143 /* KMRN Mode Control */
 144 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 145 #define HV_KMRN_MDIO_SLOW      0x0400
 146
 147 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 148 /* Offset 04h HSFSTS */
 149 union ich8_hws_flash_status {
 150         struct ich8_hsfsts {
 151                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 152                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 153                 u16 dael       :1; /* bit 2 Direct Access error Log */
 154                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 155                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 156                 u16 reserved1  :2; /* bit 13:6 Reserved */
 157                 u16 reserved2  :6; /* bit 13:6 Reserved */
 158                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 159                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 160         } hsf_status;
 161         u16 regval;
 162 };
 163
 164 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 165 /* Offset 06h FLCTL */
 166 union ich8_hws_flash_ctrl {
 167         struct ich8_hsflctl {
 168                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 169                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 170                 u16 reserved   :5;   /* 7:3 Reserved  */
 171                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 172                 u16 flockdn    :6;   /* 15:10 Reserved */
 173         } hsf_ctrl;
 174         u16 regval;
 175 };
 176
 177 /* ICH Flash Region Access Permissions */
 178 union ich8_hws_flash_regacc {
 179         struct ich8_flracc {
 180                 u32 grra      :8; /* 0:7 GbE region Read Access */
 181                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 182                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 183                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 184         } hsf_flregacc;
 185         u16 regval;
 186 };
 187
 188 /* ICH Flash Protected Region */
 189 union ich8_flash_protected_range {
 190         struct ich8_pr {
 191                 u32 base:13;     /* 0:12 Protected Range Base */
 192                 u32 reserved1:2; /* 13:14 Reserved */
 193                 u32 rpe:1;       /* 15 Read Protection Enable */
 194                 u32 limit:13;    /* 16:28 Protected Range Limit */
 195                 u32 reserved2:2; /* 29:30 Reserved */
 196                 u32 wpe:1;       /* 31 Write Protection Enable */
 197         } range;
 198         u32 regval;
 199 };
 200
 201 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 202 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 203 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 204 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 205 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 206                                                 u32 offset, u8 byte);
 207 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 208                                          u8 *data);
 209 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 210                                          u16 *data);
 211 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 212                                          u8 size, u16 *data);
 213 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 214 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 215 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 216 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 217 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 218 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 219 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 220 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 221 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 222 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 223 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 224 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 225 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 226 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 227 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 228 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 229 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 230 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 231
 232 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 233 {
 234         return readw(hw->flash_address + reg);
 235 }
 236
 237 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 238 {
 239         return readl(hw->flash_address + reg);
 240 }
 241
 242 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 243 {
 244         writew(val, hw->flash_address + reg);
 245 }
 246
 247 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 248 {
 249         writel(val, hw->flash_address + reg);
 250 }
 251
 252 #define er16flash(reg)          __er16flash(hw, (reg))
 253 #define er32flash(reg)          __er32flash(hw, (reg))
 254 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 255 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 256
 257 /**
 258  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 259  *  @hw: pointer to the HW structure
 260  *
 261  *  Initialize family-specific PHY parameters and function pointers.
 262  **/
 263 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 264 {
 265         struct e1000_phy_info *phy = &hw->phy;
 266         u32 ctrl;
 267         s32 ret_val = 0;
 268
 269         phy->addr                     = 1;
 270         phy->reset_delay_us           = 100;
 271
 272         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 273         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 274         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 275         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 276         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 277         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 278         phy->ops.power_up             = e1000_power_up_phy_copper;
 279         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 280         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 281
 282         if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 283                 /*
 284                  * The MAC-PHY interconnect may still be in SMBus mode
 285                  * after Sx->S0.  Toggle the LANPHYPC Value bit to force
 286                  * the interconnect to PCIe mode, but only if there is no
 287                  * firmware present otherwise firmware will have done it.
 288                  */
 289                 ctrl = er32(CTRL);
 290                 ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
 291                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 292                 ew32(CTRL, ctrl);
 293                 udelay(10);
 294                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 295                 ew32(CTRL, ctrl);
 296                 msleep(50);
 297         }
 298
 299         /*
 300          * Reset the PHY before any acccess to it.  Doing so, ensures that
 301          * the PHY is in a known good state before we read/write PHY registers.
 302          * The generic reset is sufficient here, because we haven't determined
 303          * the PHY type yet.
 304          */
 305         ret_val = e1000e_phy_hw_reset_generic(hw);
 306         if (ret_val)
 307                 goto out;
 308
 309         phy->id = e1000_phy_unknown;
 310         ret_val = e1000e_get_phy_id(hw);
 311         if (ret_val)
 312                 goto out;
 313         if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
 314                 /*
 315                  * In case the PHY needs to be in mdio slow mode (eg. 82577),
 316                  * set slow mode and try to get the PHY id again.
 317                  */
 318                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 319                 if (ret_val)
 320                         goto out;
 321                 ret_val = e1000e_get_phy_id(hw);
 322                 if (ret_val)
 323                         goto out;
 324         }
 325         phy->type = e1000e_get_phy_type_from_id(phy->id);
 326
 327         switch (phy->type) {
 328         case e1000_phy_82577:
 329                 phy->ops.check_polarity = e1000_check_polarity_82577;
 330                 phy->ops.force_speed_duplex =
 331                         e1000_phy_force_speed_duplex_82577;
 332                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 333                 phy->ops.get_info = e1000_get_phy_info_82577;
 334                 phy->ops.commit = e1000e_phy_sw_reset;
 335                 break;
 336         case e1000_phy_82578:
 337                 phy->ops.check_polarity = e1000_check_polarity_m88;
 338                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 339                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 340                 phy->ops.get_info = e1000e_get_phy_info_m88;
 341                 break;
 342         default:
 343                 ret_val = -E1000_ERR_PHY;
 344                 break;
 345         }
 346
 347 out:
 348         return ret_val;
 349 }
 350
 351 /**
 352  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 353  *  @hw: pointer to the HW structure
 354  *
 355  *  Initialize family-specific PHY parameters and function pointers.
 356  **/
 357 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 358 {
 359         struct e1000_phy_info *phy = &hw->phy;
 360         s32 ret_val;
 361         u16 i = 0;
 362
 363         phy->addr                       = 1;
 364         phy->reset_delay_us             = 100;
 365
 366         phy->ops.power_up               = e1000_power_up_phy_copper;
 367         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 368
 369         /*
 370          * We may need to do this twice - once for IGP and if that fails,
 371          * we'll set BM func pointers and try again
 372          */
 373         ret_val = e1000e_determine_phy_address(hw);
 374         if (ret_val) {
 375                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 376                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 377                 ret_val = e1000e_determine_phy_address(hw);
 378                 if (ret_val) {
 379                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 380                         return ret_val;
 381                 }
 382         }
 383
 384         phy->id = 0;
 385         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 386                (i++ < 100)) {
 387                 msleep(1);
 388                 ret_val = e1000e_get_phy_id(hw);
 389                 if (ret_val)
 390                         return ret_val;
 391         }
 392
 393         /* Verify phy id */
 394         switch (phy->id) {
 395         case IGP03E1000_E_PHY_ID:
 396                 phy->type = e1000_phy_igp_3;
 397                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 398                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 399                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 400                 phy->ops.get_info = e1000e_get_phy_info_igp;
 401                 phy->ops.check_polarity = e1000_check_polarity_igp;
 402                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 403                 break;
 404         case IFE_E_PHY_ID:
 405         case IFE_PLUS_E_PHY_ID:
 406         case IFE_C_E_PHY_ID:
 407                 phy->type = e1000_phy_ife;
 408                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 409                 phy->ops.get_info = e1000_get_phy_info_ife;
 410                 phy->ops.check_polarity = e1000_check_polarity_ife;
 411                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 412                 break;
 413         case BME1000_E_PHY_ID:
 414                 phy->type = e1000_phy_bm;
 415                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 416                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 417                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 418                 phy->ops.commit = e1000e_phy_sw_reset;
 419                 phy->ops.get_info = e1000e_get_phy_info_m88;
 420                 phy->ops.check_polarity = e1000_check_polarity_m88;
 421                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 422                 break;
 423         default:
 424                 return -E1000_ERR_PHY;
 425                 break;
 426         }
 427
 428         return 0;
 429 }
 430
 431 /**
 432  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 433  *  @hw: pointer to the HW structure
 434  *
 435  *  Initialize family-specific NVM parameters and function
 436  *  pointers.
 437  **/
 438 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 439 {
 440         struct e1000_nvm_info *nvm = &hw->nvm;
 441         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 442         u32 gfpreg, sector_base_addr, sector_end_addr;
 443         u16 i;
 444
 445         /* Can't read flash registers if the register set isn't mapped. */
 446         if (!hw->flash_address) {
 447                 e_dbg("ERROR: Flash registers not mapped\n");
 448                 return -E1000_ERR_CONFIG;
 449         }
 450
 451         nvm->type = e1000_nvm_flash_sw;
 452
 453         gfpreg = er32flash(ICH_FLASH_GFPREG);
 454
 455         /*
 456          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 457          * Add 1 to sector_end_addr since this sector is included in
 458          * the overall size.
 459          */
 460         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 461         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 462
 463         /* flash_base_addr is byte-aligned */
 464         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 465
 466         /*
 467          * find total size of the NVM, then cut in half since the total
 468          * size represents two separate NVM banks.
 469          */
 470         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 471                                 << FLASH_SECTOR_ADDR_SHIFT;
 472         nvm->flash_bank_size /= 2;
 473         /* Adjust to word count */
 474         nvm->flash_bank_size /= sizeof(u16);
 475
 476         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 477
 478         /* Clear shadow ram */
 479         for (i = 0; i < nvm->word_size; i++) {
 480                 dev_spec->shadow_ram[i].modified = false;
 481                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 482         }
 483
 484         return 0;
 485 }
 486
 487 /**
 488  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 489  *  @hw: pointer to the HW structure
 490  *
 491  *  Initialize family-specific MAC parameters and function
 492  *  pointers.
 493  **/
 494 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 495 {
 496         struct e1000_hw *hw = &adapter->hw;
 497         struct e1000_mac_info *mac = &hw->mac;
 498
 499         /* Set media type function pointer */
 500         hw->phy.media_type = e1000_media_type_copper;
 501
 502         /* Set mta register count */
 503         mac->mta_reg_count = 32;
 504         /* Set rar entry count */
 505         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 506         if (mac->type == e1000_ich8lan)
 507                 mac->rar_entry_count--;
 508         /* FWSM register */
 509         mac->has_fwsm = true;
 510         /* ARC subsystem not supported */
 511         mac->arc_subsystem_valid = false;
 512         /* Adaptive IFS supported */
 513         mac->adaptive_ifs = true;
 514
 515         /* LED operations */
 516         switch (mac->type) {
 517         case e1000_ich8lan:
 518         case e1000_ich9lan:
 519         case e1000_ich10lan:
 520                 /* check management mode */
 521                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 522                 /* ID LED init */
 523                 mac->ops.id_led_init = e1000e_id_led_init;
 524                 /* setup LED */
 525                 mac->ops.setup_led = e1000e_setup_led_generic;
 526                 /* cleanup LED */
 527                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 528                 /* turn on/off LED */
 529                 mac->ops.led_on = e1000_led_on_ich8lan;
 530                 mac->ops.led_off = e1000_led_off_ich8lan;
 531                 break;
 532         case e1000_pchlan:
 533                 /* check management mode */
 534                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 535                 /* ID LED init */
 536                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 537                 /* setup LED */
 538                 mac->ops.setup_led = e1000_setup_led_pchlan;
 539                 /* cleanup LED */
 540                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 541                 /* turn on/off LED */
 542                 mac->ops.led_on = e1000_led_on_pchlan;
 543                 mac->ops.led_off = e1000_led_off_pchlan;
 544                 break;
 545         default:
 546                 break;
 547         }
 548
 549         /* Enable PCS Lock-loss workaround for ICH8 */
 550         if (mac->type == e1000_ich8lan)
 551                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 552
 553         return 0;
 554 }
 555
 556 /**
 557  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 558  *  @hw: pointer to the HW structure
 559  *
 560  *  Checks to see of the link status of the hardware has changed.  If a
 561  *  change in link status has been detected, then we read the PHY registers
 562  *  to get the current speed/duplex if link exists.
 563  **/
 564 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 565 {
 566         struct e1000_mac_info *mac = &hw->mac;
 567         s32 ret_val;
 568         bool link;
 569
 570         /*
 571          * We only want to go out to the PHY registers to see if Auto-Neg
 572          * has completed and/or if our link status has changed.  The
 573          * get_link_status flag is set upon receiving a Link Status
 574          * Change or Rx Sequence Error interrupt.
 575          */
 576         if (!mac->get_link_status) {
 577                 ret_val = 0;
 578                 goto out;
 579         }
 580
 581         /*
 582          * First we want to see if the MII Status Register reports
 583          * link.  If so, then we want to get the current speed/duplex
 584          * of the PHY.
 585          */
 586         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 587         if (ret_val)
 588                 goto out;
 589
 590         if (hw->mac.type == e1000_pchlan) {
 591                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 592                 if (ret_val)
 593                         goto out;
 594         }
 595
 596         if (!link)
 597                 goto out; /* No link detected */
 598
 599         mac->get_link_status = false;
 600
 601         if (hw->phy.type == e1000_phy_82578) {
 602                 ret_val = e1000_link_stall_workaround_hv(hw);
 603                 if (ret_val)
 604                         goto out;
 605         }
 606
 607         /*
 608          * Check if there was DownShift, must be checked
 609          * immediately after link-up
 610          */
 611         e1000e_check_downshift(hw);
 612
 613         /*
 614          * If we are forcing speed/duplex, then we simply return since
 615          * we have already determined whether we have link or not.
 616          */
 617         if (!mac->autoneg) {
 618                 ret_val = -E1000_ERR_CONFIG;
 619                 goto out;
 620         }
 621
 622         /*
 623          * Auto-Neg is enabled.  Auto Speed Detection takes care
 624          * of MAC speed/duplex configuration.  So we only need to
 625          * configure Collision Distance in the MAC.
 626          */
 627         e1000e_config_collision_dist(hw);
 628
 629         /*
 630          * Configure Flow Control now that Auto-Neg has completed.
 631          * First, we need to restore the desired flow control
 632          * settings because we may have had to re-autoneg with a
 633          * different link partner.
 634          */
 635         ret_val = e1000e_config_fc_after_link_up(hw);
 636         if (ret_val)
 637                 e_dbg("Error configuring flow control\n");
 638
 639 out:
 640         return ret_val;
 641 }
 642
 643 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 644 {
 645         struct e1000_hw *hw = &adapter->hw;
 646         s32 rc;
 647
 648         rc = e1000_init_mac_params_ich8lan(adapter);
 649         if (rc)
 650                 return rc;
 651
 652         rc = e1000_init_nvm_params_ich8lan(hw);
 653         if (rc)
 654                 return rc;
 655
 656         if (hw->mac.type == e1000_pchlan)
 657                 rc = e1000_init_phy_params_pchlan(hw);
 658         else
 659                 rc = e1000_init_phy_params_ich8lan(hw);
 660         if (rc)
 661                 return rc;
 662
 663         if (adapter->hw.phy.type == e1000_phy_ife) {
 664                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 665                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 666         }
 667
 668         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 669             (adapter->hw.phy.type == e1000_phy_igp_3))
 670                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 671
 672         return 0;
 673 }
 674
 675 static DEFINE_MUTEX(nvm_mutex);
 676
 677 /**
 678  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 679  *  @hw: pointer to the HW structure
 680  *
 681  *  Acquires the mutex for performing NVM operations.
 682  **/
 683 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 684 {
 685         mutex_lock(&nvm_mutex);
 686
 687         return 0;
 688 }
 689
 690 /**
 691  *  e1000_release_nvm_ich8lan - Release NVM mutex
 692  *  @hw: pointer to the HW structure
 693  *
 694  *  Releases the mutex used while performing NVM operations.
 695  **/
 696 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 697 {
 698         mutex_unlock(&nvm_mutex);
 699 }
 700
 701 static DEFINE_MUTEX(swflag_mutex);
 702
 703 /**
 704  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 705  *  @hw: pointer to the HW structure
 706  *
 707  *  Acquires the software control flag for performing PHY and select
 708  *  MAC CSR accesses.
 709  **/
 710 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 711 {
 712         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 713         s32 ret_val = 0;
 714
 715         mutex_lock(&swflag_mutex);
 716
 717         while (timeout) {
 718                 extcnf_ctrl = er32(EXTCNF_CTRL);
 719                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 720                         break;
 721
 722                 mdelay(1);
 723                 timeout--;
 724         }
 725
 726         if (!timeout) {
 727                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 728                 ret_val = -E1000_ERR_CONFIG;
 729                 goto out;
 730         }
 731
 732         timeout = SW_FLAG_TIMEOUT;
 733
 734         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 735         ew32(EXTCNF_CTRL, extcnf_ctrl);
 736
 737         while (timeout) {
 738                 extcnf_ctrl = er32(EXTCNF_CTRL);
 739                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 740                         break;
 741
 742                 mdelay(1);
 743                 timeout--;
 744         }
 745
 746         if (!timeout) {
 747                 e_dbg("Failed to acquire the semaphore.\n");
 748                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 749                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 750                 ret_val = -E1000_ERR_CONFIG;
 751                 goto out;
 752         }
 753
 754 out:
 755         if (ret_val)
 756                 mutex_unlock(&swflag_mutex);
 757
 758         return ret_val;
 759 }
 760
 761 /**
 762  *  e1000_release_swflag_ich8lan - Release software control flag
 763  *  @hw: pointer to the HW structure
 764  *
 765  *  Releases the software control flag for performing PHY and select
 766  *  MAC CSR accesses.
 767  **/
 768 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 769 {
 770         u32 extcnf_ctrl;
 771
 772         extcnf_ctrl = er32(EXTCNF_CTRL);
 773         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 774         ew32(EXTCNF_CTRL, extcnf_ctrl);
 775
 776         mutex_unlock(&swflag_mutex);
 777 }
 778
 779 /**
 780  *  e1000_check_mng_mode_ich8lan - Checks management mode
 781  *  @hw: pointer to the HW structure
 782  *
 783  *  This checks if the adapter has any manageability enabled.
 784  *  This is a function pointer entry point only called by read/write
 785  *  routines for the PHY and NVM parts.
 786  **/
 787 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 788 {
 789         u32 fwsm;
 790
 791         fwsm = er32(FWSM);
 792         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 793                ((fwsm & E1000_FWSM_MODE_MASK) ==
 794                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 795 }
 796
 797 /**
 798  *  e1000_check_mng_mode_pchlan - Checks management mode
 799  *  @hw: pointer to the HW structure
 800  *
 801  *  This checks if the adapter has iAMT enabled.
 802  *  This is a function pointer entry point only called by read/write
 803  *  routines for the PHY and NVM parts.
 804  **/
 805 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 806 {
 807         u32 fwsm;
 808
 809         fwsm = er32(FWSM);
 810         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 811                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 812 }
 813
 814 /**
 815  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 816  *  @hw: pointer to the HW structure
 817  *
 818  *  Checks if firmware is blocking the reset of the PHY.
 819  *  This is a function pointer entry point only called by
 820  *  reset routines.
 821  **/
 822 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 823 {
 824         u32 fwsm;
 825
 826         fwsm = er32(FWSM);
 827
 828         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 829 }
 830
 831 /**
 832  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 833  *  @hw:   pointer to the HW structure
 834  *
 835  *  SW should configure the LCD from the NVM extended configuration region
 836  *  as a workaround for certain parts.
 837  **/
 838 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 839 {
 840         struct e1000_adapter *adapter = hw->adapter;
 841         struct e1000_phy_info *phy = &hw->phy;
 842         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 843         s32 ret_val = 0;
 844         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 845
 846         /*
 847          * Initialize the PHY from the NVM on ICH platforms.  This
 848          * is needed due to an issue where the NVM configuration is
 849          * not properly autoloaded after power transitions.
 850          * Therefore, after each PHY reset, we will load the
 851          * configuration data out of the NVM manually.
 852          */
 853         switch (hw->mac.type) {
 854         case e1000_ich8lan:
 855                 if (phy->type != e1000_phy_igp_3)
 856                         return ret_val;
 857
 858                 if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
 859                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 860                         break;
 861                 }
 862                 /* Fall-thru */
 863         case e1000_pchlan:
 864                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 865                 break;
 866         default:
 867                 return ret_val;
 868         }
 869
 870         ret_val = hw->phy.ops.acquire(hw);
 871         if (ret_val)
 872                 return ret_val;
 873
 874         data = er32(FEXTNVM);
 875         if (!(data & sw_cfg_mask))
 876                 goto out;
 877
 878         /*
 879          * Make sure HW does not configure LCD from PHY
 880          * extended configuration before SW configuration
 881          */
 882         data = er32(EXTCNF_CTRL);
 883         if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 884                 goto out;
 885
 886         cnf_size = er32(EXTCNF_SIZE);
 887         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 888         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 889         if (!cnf_size)
 890                 goto out;
 891
 892         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 893         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 894
 895         if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
 896             (hw->mac.type == e1000_pchlan)) {
 897                 /*
 898                  * HW configures the SMBus address and LEDs when the
 899                  * OEM and LCD Write Enable bits are set in the NVM.
 900                  * When both NVM bits are cleared, SW will configure
 901                  * them instead.
 902                  */
 903                 data = er32(STRAP);
 904                 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 905                 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
 906                 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 907                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
 908                                                         reg_data);
 909                 if (ret_val)
 910                         goto out;
 911
 912                 data = er32(LEDCTL);
 913                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
 914                                                         (u16)data);
 915                 if (ret_val)
 916                         goto out;
 917         }
 918
 919         /* Configure LCD from extended configuration region. */
 920
 921         /* cnf_base_addr is in DWORD */
 922         word_addr = (u16)(cnf_base_addr << 1);
 923
 924         for (i = 0; i < cnf_size; i++) {
 925                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
 926                                          &reg_data);
 927                 if (ret_val)
 928                         goto out;
 929
 930                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
 931                                          1, &reg_addr);
 932                 if (ret_val)
 933                         goto out;
 934
 935                 /* Save off the PHY page for future writes. */
 936                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 937                         phy_page = reg_data;
 938                         continue;
 939                 }
 940
 941                 reg_addr &= PHY_REG_MASK;
 942                 reg_addr |= phy_page;
 943
 944                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
 945                                                     reg_data);
 946                 if (ret_val)
 947                         goto out;
 948         }
 949
 950 out:
 951         hw->phy.ops.release(hw);
 952         return ret_val;
 953 }
 954
 955 /**
 956  *  e1000_k1_gig_workaround_hv - K1 Si workaround
 957  *  @hw:   pointer to the HW structure
 958  *  @link: link up bool flag
 959  *
 960  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
 961  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
 962  *  If link is down, the function will restore the default K1 setting located
 963  *  in the NVM.
 964  **/
 965 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
 966 {
 967         s32 ret_val = 0;
 968         u16 status_reg = 0;
 969         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
 970
 971         if (hw->mac.type != e1000_pchlan)
 972                 goto out;
 973
 974         /* Wrap the whole flow with the sw flag */
 975         ret_val = hw->phy.ops.acquire(hw);
 976         if (ret_val)
 977                 goto out;
 978
 979         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
 980         if (link) {
 981                 if (hw->phy.type == e1000_phy_82578) {
 982                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
 983                                                                   &status_reg);
 984                         if (ret_val)
 985                                 goto release;
 986
 987                         status_reg &= BM_CS_STATUS_LINK_UP |
 988                                       BM_CS_STATUS_RESOLVED |
 989                                       BM_CS_STATUS_SPEED_MASK;
 990
 991                         if (status_reg == (BM_CS_STATUS_LINK_UP |
 992                                            BM_CS_STATUS_RESOLVED |
 993                                            BM_CS_STATUS_SPEED_1000))
 994                                 k1_enable = false;
 995                 }
 996
 997                 if (hw->phy.type == e1000_phy_82577) {
 998                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
 999                                                                   &status_reg);
1000                         if (ret_val)
1001                                 goto release;
1002
1003                         status_reg &= HV_M_STATUS_LINK_UP |
1004                                       HV_M_STATUS_AUTONEG_COMPLETE |
1005                                       HV_M_STATUS_SPEED_MASK;
1006
1007                         if (status_reg == (HV_M_STATUS_LINK_UP |
1008                                            HV_M_STATUS_AUTONEG_COMPLETE |
1009                                            HV_M_STATUS_SPEED_1000))
1010                                 k1_enable = false;
1011                 }
1012
1013                 /* Link stall fix for link up */
1014                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1015                                                            0x0100);
1016                 if (ret_val)
1017                         goto release;
1018
1019         } else {
1020                 /* Link stall fix for link down */
1021                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1022                                                            0x4100);
1023                 if (ret_val)
1024                         goto release;
1025         }
1026
1027         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1028
1029 release:
1030         hw->phy.ops.release(hw);
1031 out:
1032         return ret_val;
1033 }
1034
1035 /**
1036  *  e1000_configure_k1_ich8lan - Configure K1 power state
1037  *  @hw: pointer to the HW structure
1038  *  @enable: K1 state to configure
1039  *
1040  *  Configure the K1 power state based on the provided parameter.
1041  *  Assumes semaphore already acquired.
1042  *
1043  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1044  **/
1045 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1046 {
1047         s32 ret_val = 0;
1048         u32 ctrl_reg = 0;
1049         u32 ctrl_ext = 0;
1050         u32 reg = 0;
1051         u16 kmrn_reg = 0;
1052
1053         ret_val = e1000e_read_kmrn_reg_locked(hw,
1054                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1055                                              &kmrn_reg);
1056         if (ret_val)
1057                 goto out;
1058
1059         if (k1_enable)
1060                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1061         else
1062                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1063
1064         ret_val = e1000e_write_kmrn_reg_locked(hw,
1065                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1066                                               kmrn_reg);
1067         if (ret_val)
1068                 goto out;
1069
1070         udelay(20);
1071         ctrl_ext = er32(CTRL_EXT);
1072         ctrl_reg = er32(CTRL);
1073
1074         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1075         reg |= E1000_CTRL_FRCSPD;
1076         ew32(CTRL, reg);
1077
1078         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1079         udelay(20);
1080         ew32(CTRL, ctrl_reg);
1081         ew32(CTRL_EXT, ctrl_ext);
1082         udelay(20);
1083
1084 out:
1085         return ret_val;
1086 }
1087
1088 /**
1089  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1090  *  @hw:       pointer to the HW structure
1091  *  @d0_state: boolean if entering d0 or d3 device state
1092  *
1093  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1094  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1095  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1096  **/
1097 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1098 {
1099         s32 ret_val = 0;
1100         u32 mac_reg;
1101         u16 oem_reg;
1102
1103         if (hw->mac.type != e1000_pchlan)
1104                 return ret_val;
1105
1106         ret_val = hw->phy.ops.acquire(hw);
1107         if (ret_val)
1108                 return ret_val;
1109
1110         mac_reg = er32(EXTCNF_CTRL);
1111         if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1112                 goto out;
1113
1114         mac_reg = er32(FEXTNVM);
1115         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1116                 goto out;
1117
1118         mac_reg = er32(PHY_CTRL);
1119
1120         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1121         if (ret_val)
1122                 goto out;
1123
1124         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1125
1126         if (d0_state) {
1127                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1128                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1129
1130                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1131                         oem_reg |= HV_OEM_BITS_LPLU;
1132         } else {
1133                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1134                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1135
1136                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1137                         oem_reg |= HV_OEM_BITS_LPLU;
1138         }
1139         /* Restart auto-neg to activate the bits */
1140         if (!e1000_check_reset_block(hw))
1141                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1142         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1143
1144 out:
1145         hw->phy.ops.release(hw);
1146
1147         return ret_val;
1148 }
1149
1150
1151 /**
1152  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1153  *  @hw:   pointer to the HW structure
1154  **/
1155 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1156 {
1157         s32 ret_val;
1158         u16 data;
1159
1160         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1161         if (ret_val)
1162                 return ret_val;
1163
1164         data |= HV_KMRN_MDIO_SLOW;
1165
1166         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1167
1168         return ret_val;
1169 }
1170
1171 /**
1172  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1173  *  done after every PHY reset.
1174  **/
1175 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1176 {
1177         s32 ret_val = 0;
1178         u16 phy_data;
1179
1180         if (hw->mac.type != e1000_pchlan)
1181                 return ret_val;
1182
1183         /* Set MDIO slow mode before any other MDIO access */
1184         if (hw->phy.type == e1000_phy_82577) {
1185                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1186                 if (ret_val)
1187                         goto out;
1188         }
1189
1190         if (((hw->phy.type == e1000_phy_82577) &&
1191              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1192             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1193                 /* Disable generation of early preamble */
1194                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1195                 if (ret_val)
1196                         return ret_val;
1197
1198                 /* Preamble tuning for SSC */
1199                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1200                 if (ret_val)
1201                         return ret_val;
1202         }
1203
1204         if (hw->phy.type == e1000_phy_82578) {
1205                 /*
1206                  * Return registers to default by doing a soft reset then
1207                  * writing 0x3140 to the control register.
1208                  */
1209                 if (hw->phy.revision < 2) {
1210                         e1000e_phy_sw_reset(hw);
1211                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1212                 }
1213         }
1214
1215         /* Select page 0 */
1216         ret_val = hw->phy.ops.acquire(hw);
1217         if (ret_val)
1218                 return ret_val;
1219
1220         hw->phy.addr = 1;
1221         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1222         hw->phy.ops.release(hw);
1223         if (ret_val)
1224                 goto out;
1225
1226         /*
1227          * Configure the K1 Si workaround during phy reset assuming there is
1228          * link so that it disables K1 if link is in 1Gbps.
1229          */
1230         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1231         if (ret_val)
1232                 goto out;
1233
1234         /* Workaround for link disconnects on a busy hub in half duplex */
1235         ret_val = hw->phy.ops.acquire(hw);
1236         if (ret_val)
1237                 goto out;
1238         ret_val = hw->phy.ops.read_reg_locked(hw,
1239                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1240                                               &phy_data);
1241         if (ret_val)
1242                 goto release;
1243         ret_val = hw->phy.ops.write_reg_locked(hw,
1244                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1245                                                phy_data & 0x00FF);
1246 release:
1247         hw->phy.ops.release(hw);
1248 out:
1249         return ret_val;
1250 }
1251
1252 /**
1253  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1254  *  @hw: pointer to the HW structure
1255  *
1256  *  Check the appropriate indication the MAC has finished configuring the
1257  *  PHY after a software reset.
1258  **/
1259 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1260 {
1261         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1262
1263         /* Wait for basic configuration completes before proceeding */
1264         do {
1265                 data = er32(STATUS);
1266                 data &= E1000_STATUS_LAN_INIT_DONE;
1267                 udelay(100);
1268         } while ((!data) && --loop);
1269
1270         /*
1271          * If basic configuration is incomplete before the above loop
1272          * count reaches 0, loading the configuration from NVM will
1273          * leave the PHY in a bad state possibly resulting in no link.
1274          */
1275         if (loop == 0)
1276                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1277
1278         /* Clear the Init Done bit for the next init event */
1279         data = er32(STATUS);
1280         data &= ~E1000_STATUS_LAN_INIT_DONE;
1281         ew32(STATUS, data);
1282 }
1283
1284 /**
1285  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1286  *  @hw: pointer to the HW structure
1287  **/
1288 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1289 {
1290         s32 ret_val = 0;
1291         u16 reg;
1292
1293         if (e1000_check_reset_block(hw))
1294                 goto out;
1295
1296         /* Perform any necessary post-reset workarounds */
1297         switch (hw->mac.type) {
1298         case e1000_pchlan:
1299                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1300                 if (ret_val)
1301                         goto out;
1302                 break;
1303         default:
1304                 break;
1305         }
1306
1307         /* Dummy read to clear the phy wakeup bit after lcd reset */
1308         if (hw->mac.type == e1000_pchlan)
1309                 e1e_rphy(hw, BM_WUC, &reg);
1310
1311         /* Configure the LCD with the extended configuration region in NVM */
1312         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1313         if (ret_val)
1314                 goto out;
1315
1316         /* Configure the LCD with the OEM bits in NVM */
1317         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1318
1319 out:
1320         return ret_val;
1321 }
1322
1323 /**
1324  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1325  *  @hw: pointer to the HW structure
1326  *
1327  *  Resets the PHY
1328  *  This is a function pointer entry point called by drivers
1329  *  or other shared routines.
1330  **/
1331 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1332 {
1333         s32 ret_val = 0;
1334
1335         ret_val = e1000e_phy_hw_reset_generic(hw);
1336         if (ret_val)
1337                 goto out;
1338
1339         ret_val = e1000_post_phy_reset_ich8lan(hw);
1340
1341 out:
1342         return ret_val;
1343 }
1344
1345 /**
1346  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1347  *  @hw: pointer to the HW structure
1348  *  @active: true to enable LPLU, false to disable
1349  *
1350  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1351  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1352  *  the phy speed. This function will manually set the LPLU bit and restart
1353  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1354  *  since it configures the same bit.
1355  **/
1356 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1357 {
1358         s32 ret_val = 0;
1359         u16 oem_reg;
1360
1361         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1362         if (ret_val)
1363                 goto out;
1364
1365         if (active)
1366                 oem_reg |= HV_OEM_BITS_LPLU;
1367         else
1368                 oem_reg &= ~HV_OEM_BITS_LPLU;
1369
1370         oem_reg |= HV_OEM_BITS_RESTART_AN;
1371         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1372
1373 out:
1374         return ret_val;
1375 }
1376
1377 /**
1378  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1379  *  @hw: pointer to the HW structure
1380  *  @active: true to enable LPLU, false to disable
1381  *
1382  *  Sets the LPLU D0 state according to the active flag.  When
1383  *  activating LPLU this function also disables smart speed
1384  *  and vice versa.  LPLU will not be activated unless the
1385  *  device autonegotiation advertisement meets standards of
1386  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1387  *  This is a function pointer entry point only called by
1388  *  PHY setup routines.
1389  **/
1390 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1391 {
1392         struct e1000_phy_info *phy = &hw->phy;
1393         u32 phy_ctrl;
1394         s32 ret_val = 0;
1395         u16 data;
1396
1397         if (phy->type == e1000_phy_ife)
1398                 return ret_val;
1399
1400         phy_ctrl = er32(PHY_CTRL);
1401
1402         if (active) {
1403                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1404                 ew32(PHY_CTRL, phy_ctrl);
1405
1406                 if (phy->type != e1000_phy_igp_3)
1407                         return 0;
1408
1409                 /*
1410                  * Call gig speed drop workaround on LPLU before accessing
1411                  * any PHY registers
1412                  */
1413                 if (hw->mac.type == e1000_ich8lan)
1414                         e1000e_gig_downshift_workaround_ich8lan(hw);
1415
1416                 /* When LPLU is enabled, we should disable SmartSpeed */
1417                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1418                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1419                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1420                 if (ret_val)
1421                         return ret_val;
1422         } else {
1423                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1424                 ew32(PHY_CTRL, phy_ctrl);
1425
1426                 if (phy->type != e1000_phy_igp_3)
1427                         return 0;
1428
1429                 /*
1430                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1431                  * during Dx states where the power conservation is most
1432                  * important.  During driver activity we should enable
1433                  * SmartSpeed, so performance is maintained.
1434                  */
1435                 if (phy->smart_speed == e1000_smart_speed_on) {
1436                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1437                                            &data);
1438                         if (ret_val)
1439                                 return ret_val;
1440
1441                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1442                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1443                                            data);
1444                         if (ret_val)
1445                                 return ret_val;
1446                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1447                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1448                                            &data);
1449                         if (ret_val)
1450                                 return ret_val;
1451
1452                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1453                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1454                                            data);
1455                         if (ret_val)
1456                                 return ret_val;
1457                 }
1458         }
1459
1460         return 0;
1461 }
1462
1463 /**
1464  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1465  *  @hw: pointer to the HW structure
1466  *  @active: true to enable LPLU, false to disable
1467  *
1468  *  Sets the LPLU D3 state according to the active flag.  When
1469  *  activating LPLU this function also disables smart speed
1470  *  and vice versa.  LPLU will not be activated unless the
1471  *  device autonegotiation advertisement meets standards of
1472  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1473  *  This is a function pointer entry point only called by
1474  *  PHY setup routines.
1475  **/
1476 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1477 {
1478         struct e1000_phy_info *phy = &hw->phy;
1479         u32 phy_ctrl;
1480         s32 ret_val;
1481         u16 data;
1482
1483         phy_ctrl = er32(PHY_CTRL);
1484
1485         if (!active) {
1486                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1487                 ew32(PHY_CTRL, phy_ctrl);
1488
1489                 if (phy->type != e1000_phy_igp_3)
1490                         return 0;
1491
1492                 /*
1493                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1494                  * during Dx states where the power conservation is most
1495                  * important.  During driver activity we should enable
1496                  * SmartSpeed, so performance is maintained.
1497                  */
1498                 if (phy->smart_speed == e1000_smart_speed_on) {
1499                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1500                                            &data);
1501                         if (ret_val)
1502                                 return ret_val;
1503
1504                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1505                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1506                                            data);
1507                         if (ret_val)
1508                                 return ret_val;
1509                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1510                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1511                                            &data);
1512                         if (ret_val)
1513                                 return ret_val;
1514
1515                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1516                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1517                                            data);
1518                         if (ret_val)
1519                                 return ret_val;
1520                 }
1521         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1522                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1523                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1524                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1525                 ew32(PHY_CTRL, phy_ctrl);
1526
1527                 if (phy->type != e1000_phy_igp_3)
1528                         return 0;
1529
1530                 /*
1531                  * Call gig speed drop workaround on LPLU before accessing
1532                  * any PHY registers
1533                  */
1534                 if (hw->mac.type == e1000_ich8lan)
1535                         e1000e_gig_downshift_workaround_ich8lan(hw);
1536
1537                 /* When LPLU is enabled, we should disable SmartSpeed */
1538                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1539                 if (ret_val)
1540                         return ret_val;
1541
1542                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1543                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1544         }
1545
1546         return 0;
1547 }
1548
1549 /**
1550  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1551  *  @hw: pointer to the HW structure
1552  *  @bank:  pointer to the variable that returns the active bank
1553  *
1554  *  Reads signature byte from the NVM using the flash access registers.
1555  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1556  **/
1557 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1558 {
1559         u32 eecd;
1560         struct e1000_nvm_info *nvm = &hw->nvm;
1561         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1562         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1563         u8 sig_byte = 0;
1564         s32 ret_val = 0;
1565
1566         switch (hw->mac.type) {
1567         case e1000_ich8lan:
1568         case e1000_ich9lan:
1569                 eecd = er32(EECD);
1570                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1571                     E1000_EECD_SEC1VAL_VALID_MASK) {
1572                         if (eecd & E1000_EECD_SEC1VAL)
1573                                 *bank = 1;
1574                         else
1575                                 *bank = 0;
1576
1577                         return 0;
1578                 }
1579                 e_dbg("Unable to determine valid NVM bank via EEC - "
1580                        "reading flash signature\n");
1581                 /* fall-thru */
1582         default:
1583                 /* set bank to 0 in case flash read fails */
1584                 *bank = 0;
1585
1586                 /* Check bank 0 */
1587                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1588                                                         &sig_byte);
1589                 if (ret_val)
1590                         return ret_val;
1591                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1592                     E1000_ICH_NVM_SIG_VALUE) {
1593                         *bank = 0;
1594                         return 0;
1595                 }
1596
1597                 /* Check bank 1 */
1598                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1599                                                         bank1_offset,
1600                                                         &sig_byte);
1601                 if (ret_val)
1602                         return ret_val;
1603                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1604                     E1000_ICH_NVM_SIG_VALUE) {
1605                         *bank = 1;
1606                         return 0;
1607                 }
1608
1609                 e_dbg("ERROR: No valid NVM bank present\n");
1610                 return -E1000_ERR_NVM;
1611         }
1612
1613         return 0;
1614 }
1615
1616 /**
1617  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1618  *  @hw: pointer to the HW structure
1619  *  @offset: The offset (in bytes) of the word(s) to read.
1620  *  @words: Size of data to read in words
1621  *  @data: Pointer to the word(s) to read at offset.
1622  *
1623  *  Reads a word(s) from the NVM using the flash access registers.
1624  **/
1625 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1626                                   u16 *data)
1627 {
1628         struct e1000_nvm_info *nvm = &hw->nvm;
1629         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1630         u32 act_offset;
1631         s32 ret_val = 0;
1632         u32 bank = 0;
1633         u16 i, word;
1634
1635         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1636             (words == 0)) {
1637                 e_dbg("nvm parameter(s) out of bounds\n");
1638                 ret_val = -E1000_ERR_NVM;
1639                 goto out;
1640         }
1641
1642         nvm->ops.acquire(hw);
1643
1644         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1645         if (ret_val) {
1646                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1647                 bank = 0;
1648         }
1649
1650         act_offset = (bank) ? nvm->flash_bank_size : 0;
1651         act_offset += offset;
1652
1653         ret_val = 0;
1654         for (i = 0; i < words; i++) {
1655                 if ((dev_spec->shadow_ram) &&
1656                     (dev_spec->shadow_ram[offset+i].modified)) {
1657                         data[i] = dev_spec->shadow_ram[offset+i].value;
1658                 } else {
1659                         ret_val = e1000_read_flash_word_ich8lan(hw,
1660                                                                 act_offset + i,
1661                                                                 &word);
1662                         if (ret_val)
1663                                 break;
1664                         data[i] = word;
1665                 }
1666         }
1667
1668         nvm->ops.release(hw);
1669
1670 out:
1671         if (ret_val)
1672                 e_dbg("NVM read error: %d\n", ret_val);
1673
1674         return ret_val;
1675 }
1676
1677 /**
1678  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1679  *  @hw: pointer to the HW structure
1680  *
1681  *  This function does initial flash setup so that a new read/write/erase cycle
1682  *  can be started.
1683  **/
1684 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1685 {
1686         union ich8_hws_flash_status hsfsts;
1687         s32 ret_val = -E1000_ERR_NVM;
1688         s32 i = 0;
1689
1690         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1691
1692         /* Check if the flash descriptor is valid */
1693         if (hsfsts.hsf_status.fldesvalid == 0) {
1694                 e_dbg("Flash descriptor invalid.  "
1695                          "SW Sequencing must be used.\n");
1696                 return -E1000_ERR_NVM;
1697         }
1698
1699         /* Clear FCERR and DAEL in hw status by writing 1 */
1700         hsfsts.hsf_status.flcerr = 1;
1701         hsfsts.hsf_status.dael = 1;
1702
1703         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1704
1705         /*
1706          * Either we should have a hardware SPI cycle in progress
1707          * bit to check against, in order to start a new cycle or
1708          * FDONE bit should be changed in the hardware so that it
1709          * is 1 after hardware reset, which can then be used as an
1710          * indication whether a cycle is in progress or has been
1711          * completed.
1712          */
1713
1714         if (hsfsts.hsf_status.flcinprog == 0) {
1715                 /*
1716                  * There is no cycle running at present,
1717                  * so we can start a cycle.
1718                  * Begin by setting Flash Cycle Done.
1719                  */
1720                 hsfsts.hsf_status.flcdone = 1;
1721                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1722                 ret_val = 0;
1723         } else {
1724                 /*
1725                  * Otherwise poll for sometime so the current
1726                  * cycle has a chance to end before giving up.
1727                  */
1728                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1729                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1730                         if (hsfsts.hsf_status.flcinprog == 0) {
1731                                 ret_val = 0;
1732                                 break;
1733                         }
1734                         udelay(1);
1735                 }
1736                 if (ret_val == 0) {
1737                         /*
1738                          * Successful in waiting for previous cycle to timeout,
1739                          * now set the Flash Cycle Done.
1740                          */
1741                         hsfsts.hsf_status.flcdone = 1;
1742                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1743                 } else {
1744                         e_dbg("Flash controller busy, cannot get access\n");
1745                 }
1746         }
1747
1748         return ret_val;
1749 }
1750
1751 /**
1752  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1753  *  @hw: pointer to the HW structure
1754  *  @timeout: maximum time to wait for completion
1755  *
1756  *  This function starts a flash cycle and waits for its completion.
1757  **/
1758 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1759 {
1760         union ich8_hws_flash_ctrl hsflctl;
1761         union ich8_hws_flash_status hsfsts;
1762         s32 ret_val = -E1000_ERR_NVM;
1763         u32 i = 0;
1764
1765         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1766         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1767         hsflctl.hsf_ctrl.flcgo = 1;
1768         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1769
1770         /* wait till FDONE bit is set to 1 */
1771         do {
1772                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1773                 if (hsfsts.hsf_status.flcdone == 1)
1774                         break;
1775                 udelay(1);
1776         } while (i++ < timeout);
1777
1778         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1779                 return 0;
1780
1781         return ret_val;
1782 }
1783
1784 /**
1785  *  e1000_read_flash_word_ich8lan - Read word from flash
1786  *  @hw: pointer to the HW structure
1787  *  @offset: offset to data location
1788  *  @data: pointer to the location for storing the data
1789  *
1790  *  Reads the flash word at offset into data.  Offset is converted
1791  *  to bytes before read.
1792  **/
1793 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1794                                          u16 *data)
1795 {
1796         /* Must convert offset into bytes. */
1797         offset <<= 1;
1798
1799         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1800 }
1801
1802 /**
1803  *  e1000_read_flash_byte_ich8lan - Read byte from flash
1804  *  @hw: pointer to the HW structure
1805  *  @offset: The offset of the byte to read.
1806  *  @data: Pointer to a byte to store the value read.
1807  *
1808  *  Reads a single byte from the NVM using the flash access registers.
1809  **/
1810 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1811                                          u8 *data)
1812 {
1813         s32 ret_val;
1814         u16 word = 0;
1815
1816         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
1817         if (ret_val)
1818                 return ret_val;
1819
1820         *data = (u8)word;
1821
1822         return 0;
1823 }
1824
1825 /**
1826  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1827  *  @hw: pointer to the HW structure
1828  *  @offset: The offset (in bytes) of the byte or word to read.
1829  *  @size: Size of data to read, 1=byte 2=word
1830  *  @data: Pointer to the word to store the value read.
1831  *
1832  *  Reads a byte or word from the NVM using the flash access registers.
1833  **/
1834 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1835                                          u8 size, u16 *data)
1836 {
1837         union ich8_hws_flash_status hsfsts;
1838         union ich8_hws_flash_ctrl hsflctl;
1839         u32 flash_linear_addr;
1840         u32 flash_data = 0;
1841         s32 ret_val = -E1000_ERR_NVM;
1842         u8 count = 0;
1843
1844         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1845                 return -E1000_ERR_NVM;
1846
1847         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1848                             hw->nvm.flash_base_addr;
1849
1850         do {
1851                 udelay(1);
1852                 /* Steps */
1853                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1854                 if (ret_val != 0)
1855                         break;
1856
1857                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1858                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1859                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1860                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1861                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1862
1863                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1864
1865                 ret_val = e1000_flash_cycle_ich8lan(hw,
1866                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1867
1868                 /*
1869                  * Check if FCERR is set to 1, if set to 1, clear it
1870                  * and try the whole sequence a few more times, else
1871                  * read in (shift in) the Flash Data0, the order is
1872                  * least significant byte first msb to lsb
1873                  */
1874                 if (ret_val == 0) {
1875                         flash_data = er32flash(ICH_FLASH_FDATA0);
1876                         if (size == 1) {
1877                                 *data = (u8)(flash_data & 0x000000FF);
1878                         } else if (size == 2) {
1879                                 *data = (u16)(flash_data & 0x0000FFFF);
1880                         }
1881                         break;
1882                 } else {
1883                         /*
1884                          * If we've gotten here, then things are probably
1885                          * completely hosed, but if the error condition is
1886                          * detected, it won't hurt to give it another try...
1887                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1888                          */
1889                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1890                         if (hsfsts.hsf_status.flcerr == 1) {
1891                                 /* Repeat for some time before giving up. */
1892                                 continue;
1893                         } else if (hsfsts.hsf_status.flcdone == 0) {
1894                                 e_dbg("Timeout error - flash cycle "
1895                                          "did not complete.\n");
1896                                 break;
1897                         }
1898                 }
1899         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1900
1901         return ret_val;
1902 }
1903
1904 /**
1905  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1906  *  @hw: pointer to the HW structure
1907  *  @offset: The offset (in bytes) of the word(s) to write.
1908  *  @words: Size of data to write in words
1909  *  @data: Pointer to the word(s) to write at offset.
1910  *
1911  *  Writes a byte or word to the NVM using the flash access registers.
1912  **/
1913 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1914                                    u16 *data)
1915 {
1916         struct e1000_nvm_info *nvm = &hw->nvm;
1917         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1918         u16 i;
1919
1920         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1921             (words == 0)) {
1922                 e_dbg("nvm parameter(s) out of bounds\n");
1923                 return -E1000_ERR_NVM;
1924         }
1925
1926         nvm->ops.acquire(hw);
1927
1928         for (i = 0; i < words; i++) {
1929                 dev_spec->shadow_ram[offset+i].modified = true;
1930                 dev_spec->shadow_ram[offset+i].value = data[i];
1931         }
1932
1933         nvm->ops.release(hw);
1934
1935         return 0;
1936 }
1937
1938 /**
1939  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1940  *  @hw: pointer to the HW structure
1941  *
1942  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1943  *  which writes the checksum to the shadow ram.  The changes in the shadow
1944  *  ram are then committed to the EEPROM by processing each bank at a time
1945  *  checking for the modified bit and writing only the pending changes.
1946  *  After a successful commit, the shadow ram is cleared and is ready for
1947  *  future writes.
1948  **/
1949 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1950 {
1951         struct e1000_nvm_info *nvm = &hw->nvm;
1952         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1953         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
1954         s32 ret_val;
1955         u16 data;
1956
1957         ret_val = e1000e_update_nvm_checksum_generic(hw);
1958         if (ret_val)
1959                 goto out;
1960
1961         if (nvm->type != e1000_nvm_flash_sw)
1962                 goto out;
1963
1964         nvm->ops.acquire(hw);
1965
1966         /*
1967          * We're writing to the opposite bank so if we're on bank 1,
1968          * write to bank 0 etc.  We also need to erase the segment that
1969          * is going to be written
1970          */
1971         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1972         if (ret_val) {
1973                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1974                 bank = 0;
1975         }
1976
1977         if (bank == 0) {
1978                 new_bank_offset = nvm->flash_bank_size;
1979                 old_bank_offset = 0;
1980                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
1981                 if (ret_val)
1982                         goto release;
1983         } else {
1984                 old_bank_offset = nvm->flash_bank_size;
1985                 new_bank_offset = 0;
1986                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
1987                 if (ret_val)
1988                         goto release;
1989         }
1990
1991         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1992                 /*
1993                  * Determine whether to write the value stored
1994                  * in the other NVM bank or a modified value stored
1995                  * in the shadow RAM
1996                  */
1997                 if (dev_spec->shadow_ram[i].modified) {
1998                         data = dev_spec->shadow_ram[i].value;
1999                 } else {
2000                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2001                                                                 old_bank_offset,
2002                                                                 &data);
2003                         if (ret_val)
2004                                 break;
2005                 }
2006
2007                 /*
2008                  * If the word is 0x13, then make sure the signature bits
2009                  * (15:14) are 11b until the commit has completed.
2010                  * This will allow us to write 10b which indicates the
2011                  * signature is valid.  We want to do this after the write
2012                  * has completed so that we don't mark the segment valid
2013                  * while the write is still in progress
2014                  */
2015                 if (i == E1000_ICH_NVM_SIG_WORD)
2016                         data |= E1000_ICH_NVM_SIG_MASK;
2017
2018                 /* Convert offset to bytes. */
2019                 act_offset = (i + new_bank_offset) << 1;
2020
2021                 udelay(100);
2022                 /* Write the bytes to the new bank. */
2023                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2024                                                                act_offset,
2025                                                                (u8)data);
2026                 if (ret_val)
2027                         break;
2028
2029                 udelay(100);
2030                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2031                                                           act_offset + 1,
2032                                                           (u8)(data >> 8));
2033                 if (ret_val)
2034                         break;
2035         }
2036
2037         /*
2038          * Don't bother writing the segment valid bits if sector
2039          * programming failed.
2040          */
2041         if (ret_val) {
2042                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2043                 e_dbg("Flash commit failed.\n");
2044                 goto release;
2045         }
2046
2047         /*
2048          * Finally validate the new segment by setting bit 15:14
2049          * to 10b in word 0x13 , this can be done without an
2050          * erase as well since these bits are 11 to start with
2051          * and we need to change bit 14 to 0b
2052          */
2053         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2054         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2055         if (ret_val)
2056                 goto release;
2057
2058         data &= 0xBFFF;
2059         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2060                                                        act_offset * 2 + 1,
2061                                                        (u8)(data >> 8));
2062         if (ret_val)
2063                 goto release;
2064
2065         /*
2066          * And invalidate the previously valid segment by setting
2067          * its signature word (0x13) high_byte to 0b. This can be
2068          * done without an erase because flash erase sets all bits
2069          * to 1's. We can write 1's to 0's without an erase
2070          */
2071         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2072         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2073         if (ret_val)
2074                 goto release;
2075
2076         /* Great!  Everything worked, we can now clear the cached entries. */
2077         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2078                 dev_spec->shadow_ram[i].modified = false;
2079                 dev_spec->shadow_ram[i].value = 0xFFFF;
2080         }
2081
2082 release:
2083         nvm->ops.release(hw);
2084
2085         /*
2086          * Reload the EEPROM, or else modifications will not appear
2087          * until after the next adapter reset.
2088          */
2089         if (!ret_val) {
2090                 e1000e_reload_nvm(hw);
2091                 msleep(10);
2092         }
2093
2094 out:
2095         if (ret_val)
2096                 e_dbg("NVM update error: %d\n", ret_val);
2097
2098         return ret_val;
2099 }
2100
2101 /**
2102  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2103  *  @hw: pointer to the HW structure
2104  *
2105  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2106  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2107  *  calculated, in which case we need to calculate the checksum and set bit 6.
2108  **/
2109 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2110 {
2111         s32 ret_val;
2112         u16 data;
2113
2114         /*
2115          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2116          * needs to be fixed.  This bit is an indication that the NVM
2117          * was prepared by OEM software and did not calculate the
2118          * checksum...a likely scenario.
2119          */
2120         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2121         if (ret_val)
2122                 return ret_val;
2123
2124         if ((data & 0x40) == 0) {
2125                 data |= 0x40;
2126                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2127                 if (ret_val)
2128                         return ret_val;
2129                 ret_val = e1000e_update_nvm_checksum(hw);
2130                 if (ret_val)
2131                         return ret_val;
2132         }
2133
2134         return e1000e_validate_nvm_checksum_generic(hw);
2135 }
2136
2137 /**
2138  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2139  *  @hw: pointer to the HW structure
2140  *
2141  *  To prevent malicious write/erase of the NVM, set it to be read-only
2142  *  so that the hardware ignores all write/erase cycles of the NVM via
2143  *  the flash control registers.  The shadow-ram copy of the NVM will
2144  *  still be updated, however any updates to this copy will not stick
2145  *  across driver reloads.
2146  **/
2147 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2148 {
2149         struct e1000_nvm_info *nvm = &hw->nvm;
2150         union ich8_flash_protected_range pr0;
2151         union ich8_hws_flash_status hsfsts;
2152         u32 gfpreg;
2153
2154         nvm->ops.acquire(hw);
2155
2156         gfpreg = er32flash(ICH_FLASH_GFPREG);
2157
2158         /* Write-protect GbE Sector of NVM */
2159         pr0.regval = er32flash(ICH_FLASH_PR0);
2160         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2161         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2162         pr0.range.wpe = true;
2163         ew32flash(ICH_FLASH_PR0, pr0.regval);
2164
2165         /*
2166          * Lock down a subset of GbE Flash Control Registers, e.g.
2167          * PR0 to prevent the write-protection from being lifted.
2168          * Once FLOCKDN is set, the registers protected by it cannot
2169          * be written until FLOCKDN is cleared by a hardware reset.
2170          */
2171         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2172         hsfsts.hsf_status.flockdn = true;
2173         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2174
2175         nvm->ops.release(hw);
2176 }
2177
2178 /**
2179  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2180  *  @hw: pointer to the HW structure
2181  *  @offset: The offset (in bytes) of the byte/word to read.
2182  *  @size: Size of data to read, 1=byte 2=word
2183  *  @data: The byte(s) to write to the NVM.
2184  *
2185  *  Writes one/two bytes to the NVM using the flash access registers.
2186  **/
2187 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2188                                           u8 size, u16 data)
2189 {
2190         union ich8_hws_flash_status hsfsts;
2191         union ich8_hws_flash_ctrl hsflctl;
2192         u32 flash_linear_addr;
2193         u32 flash_data = 0;
2194         s32 ret_val;
2195         u8 count = 0;
2196
2197         if (size < 1 || size > 2 || data > size * 0xff ||
2198             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2199                 return -E1000_ERR_NVM;
2200
2201         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2202                             hw->nvm.flash_base_addr;
2203
2204         do {
2205                 udelay(1);
2206                 /* Steps */
2207                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2208                 if (ret_val)
2209                         break;
2210
2211                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2212                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2213                 hsflctl.hsf_ctrl.fldbcount = size -1;
2214                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2215                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2216
2217                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2218
2219                 if (size == 1)
2220                         flash_data = (u32)data & 0x00FF;
2221                 else
2222                         flash_data = (u32)data;
2223
2224                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2225
2226                 /*
2227                  * check if FCERR is set to 1 , if set to 1, clear it
2228                  * and try the whole sequence a few more times else done
2229                  */
2230                 ret_val = e1000_flash_cycle_ich8lan(hw,
2231                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2232                 if (!ret_val)
2233                         break;
2234
2235                 /*
2236                  * If we're here, then things are most likely
2237                  * completely hosed, but if the error condition
2238                  * is detected, it won't hurt to give it another
2239                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2240                  */
2241                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2242                 if (hsfsts.hsf_status.flcerr == 1)
2243                         /* Repeat for some time before giving up. */
2244                         continue;
2245                 if (hsfsts.hsf_status.flcdone == 0) {
2246                         e_dbg("Timeout error - flash cycle "
2247                                  "did not complete.");
2248                         break;
2249                 }
2250         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2251
2252         return ret_val;
2253 }
2254
2255 /**
2256  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2257  *  @hw: pointer to the HW structure
2258  *  @offset: The index of the byte to read.
2259  *  @data: The byte to write to the NVM.
2260  *
2261  *  Writes a single byte to the NVM using the flash access registers.
2262  **/
2263 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2264                                           u8 data)
2265 {
2266         u16 word = (u16)data;
2267
2268         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2269 }
2270
2271 /**
2272  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2273  *  @hw: pointer to the HW structure
2274  *  @offset: The offset of the byte to write.
2275  *  @byte: The byte to write to the NVM.
2276  *
2277  *  Writes a single byte to the NVM using the flash access registers.
2278  *  Goes through a retry algorithm before giving up.
2279  **/
2280 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2281                                                 u32 offset, u8 byte)
2282 {
2283         s32 ret_val;
2284         u16 program_retries;
2285
2286         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2287         if (!ret_val)
2288                 return ret_val;
2289
2290         for (program_retries = 0; program_retries < 100; program_retries++) {
2291                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2292                 udelay(100);
2293                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2294                 if (!ret_val)
2295                         break;
2296         }
2297         if (program_retries == 100)
2298                 return -E1000_ERR_NVM;
2299
2300         return 0;
2301 }
2302
2303 /**
2304  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2305  *  @hw: pointer to the HW structure
2306  *  @bank: 0 for first bank, 1 for second bank, etc.
2307  *
2308  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2309  *  bank N is 4096 * N + flash_reg_addr.
2310  **/
2311 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2312 {
2313         struct e1000_nvm_info *nvm = &hw->nvm;
2314         union ich8_hws_flash_status hsfsts;
2315         union ich8_hws_flash_ctrl hsflctl;
2316         u32 flash_linear_addr;
2317         /* bank size is in 16bit words - adjust to bytes */
2318         u32 flash_bank_size = nvm->flash_bank_size * 2;
2319         s32 ret_val;
2320         s32 count = 0;
2321         s32 j, iteration, sector_size;
2322
2323         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2324
2325         /*
2326          * Determine HW Sector size: Read BERASE bits of hw flash status
2327          * register
2328          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2329          *     consecutive sectors.  The start index for the nth Hw sector
2330          *     can be calculated as = bank * 4096 + n * 256
2331          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2332          *     The start index for the nth Hw sector can be calculated
2333          *     as = bank * 4096
2334          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2335          *     (ich9 only, otherwise error condition)
2336          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2337          */
2338         switch (hsfsts.hsf_status.berasesz) {
2339         case 0:
2340                 /* Hw sector size 256 */
2341                 sector_size = ICH_FLASH_SEG_SIZE_256;
2342                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2343                 break;
2344         case 1:
2345                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2346                 iteration = 1;
2347                 break;
2348         case 2:
2349                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2350                 iteration = 1;
2351                 break;
2352         case 3:
2353                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2354                 iteration = 1;
2355                 break;
2356         default:
2357                 return -E1000_ERR_NVM;
2358         }
2359
2360         /* Start with the base address, then add the sector offset. */
2361         flash_linear_addr = hw->nvm.flash_base_addr;
2362         flash_linear_addr += (bank) ? flash_bank_size : 0;
2363
2364         for (j = 0; j < iteration ; j++) {
2365                 do {
2366                         /* Steps */
2367                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2368                         if (ret_val)
2369                                 return ret_val;
2370
2371                         /*
2372                          * Write a value 11 (block Erase) in Flash
2373                          * Cycle field in hw flash control
2374                          */
2375                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2376                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2377                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2378
2379                         /*
2380                          * Write the last 24 bits of an index within the
2381                          * block into Flash Linear address field in Flash
2382                          * Address.
2383                          */
2384                         flash_linear_addr += (j * sector_size);
2385                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2386
2387                         ret_val = e1000_flash_cycle_ich8lan(hw,
2388                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2389                         if (ret_val == 0)
2390                                 break;
2391
2392                         /*
2393                          * Check if FCERR is set to 1.  If 1,
2394                          * clear it and try the whole sequence
2395                          * a few more times else Done
2396                          */
2397                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2398                         if (hsfsts.hsf_status.flcerr == 1)
2399                                 /* repeat for some time before giving up */
2400                                 continue;
2401                         else if (hsfsts.hsf_status.flcdone == 0)
2402                                 return ret_val;
2403                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2404         }
2405
2406         return 0;
2407 }
2408
2409 /**
2410  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2411  *  @hw: pointer to the HW structure
2412  *  @data: Pointer to the LED settings
2413  *
2414  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2415  *  settings is all 0's or F's, set the LED default to a valid LED default
2416  *  setting.
2417  **/
2418 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2419 {
2420         s32 ret_val;
2421
2422         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2423         if (ret_val) {
2424                 e_dbg("NVM Read Error\n");
2425                 return ret_val;
2426         }
2427
2428         if (*data == ID_LED_RESERVED_0000 ||
2429             *data == ID_LED_RESERVED_FFFF)
2430                 *data = ID_LED_DEFAULT_ICH8LAN;
2431
2432         return 0;
2433 }
2434
2435 /**
2436  *  e1000_id_led_init_pchlan - store LED configurations
2437  *  @hw: pointer to the HW structure
2438  *
2439  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2440  *  the PHY LED configuration register.
2441  *
2442  *  PCH also does not have an "always on" or "always off" mode which
2443  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2444  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2445  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2446  *  link based on logic in e1000_led_[on|off]_pchlan().
2447  **/
2448 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2449 {
2450         struct e1000_mac_info *mac = &hw->mac;
2451         s32 ret_val;
2452         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2453         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2454         u16 data, i, temp, shift;
2455
2456         /* Get default ID LED modes */
2457         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2458         if (ret_val)
2459                 goto out;
2460
2461         mac->ledctl_default = er32(LEDCTL);
2462         mac->ledctl_mode1 = mac->ledctl_default;
2463         mac->ledctl_mode2 = mac->ledctl_default;
2464
2465         for (i = 0; i < 4; i++) {
2466                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2467                 shift = (i * 5);
2468                 switch (temp) {
2469                 case ID_LED_ON1_DEF2:
2470                 case ID_LED_ON1_ON2:
2471                 case ID_LED_ON1_OFF2:
2472                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2473                         mac->ledctl_mode1 |= (ledctl_on << shift);
2474                         break;
2475                 case ID_LED_OFF1_DEF2:
2476                 case ID_LED_OFF1_ON2:
2477                 case ID_LED_OFF1_OFF2:
2478                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2479                         mac->ledctl_mode1 |= (ledctl_off << shift);
2480                         break;
2481                 default:
2482                         /* Do nothing */
2483                         break;
2484                 }
2485                 switch (temp) {
2486                 case ID_LED_DEF1_ON2:
2487                 case ID_LED_ON1_ON2:
2488                 case ID_LED_OFF1_ON2:
2489                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2490                         mac->ledctl_mode2 |= (ledctl_on << shift);
2491                         break;
2492                 case ID_LED_DEF1_OFF2:
2493                 case ID_LED_ON1_OFF2:
2494                 case ID_LED_OFF1_OFF2:
2495                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2496                         mac->ledctl_mode2 |= (ledctl_off << shift);
2497                         break;
2498                 default:
2499                         /* Do nothing */
2500                         break;
2501                 }
2502         }
2503
2504 out:
2505         return ret_val;
2506 }
2507
2508 /**
2509  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2510  *  @hw: pointer to the HW structure
2511  *
2512  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2513  *  register, so the the bus width is hard coded.
2514  **/
2515 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2516 {
2517         struct e1000_bus_info *bus = &hw->bus;
2518         s32 ret_val;
2519
2520         ret_val = e1000e_get_bus_info_pcie(hw);
2521
2522         /*
2523          * ICH devices are "PCI Express"-ish.  They have
2524          * a configuration space, but do not contain
2525          * PCI Express Capability registers, so bus width
2526          * must be hardcoded.
2527          */
2528         if (bus->width == e1000_bus_width_unknown)
2529                 bus->width = e1000_bus_width_pcie_x1;
2530
2531         return ret_val;
2532 }
2533
2534 /**
2535  *  e1000_reset_hw_ich8lan - Reset the hardware
2536  *  @hw: pointer to the HW structure
2537  *
2538  *  Does a full reset of the hardware which includes a reset of the PHY and
2539  *  MAC.
2540  **/
2541 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2542 {
2543         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2544         u16 reg;
2545         u32 ctrl, icr, kab;
2546         s32 ret_val;
2547
2548         /*
2549          * Prevent the PCI-E bus from sticking if there is no TLP connection
2550          * on the last TLP read/write transaction when MAC is reset.
2551          */
2552         ret_val = e1000e_disable_pcie_master(hw);
2553         if (ret_val)
2554                 e_dbg("PCI-E Master disable polling has failed.\n");
2555
2556         e_dbg("Masking off all interrupts\n");
2557         ew32(IMC, 0xffffffff);
2558
2559         /*
2560          * Disable the Transmit and Receive units.  Then delay to allow
2561          * any pending transactions to complete before we hit the MAC
2562          * with the global reset.
2563          */
2564         ew32(RCTL, 0);
2565         ew32(TCTL, E1000_TCTL_PSP);
2566         e1e_flush();
2567
2568         msleep(10);
2569
2570         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2571         if (hw->mac.type == e1000_ich8lan) {
2572                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2573                 ew32(PBA, E1000_PBA_8K);
2574                 /* Set Packet Buffer Size to 16k. */
2575                 ew32(PBS, E1000_PBS_16K);
2576         }
2577
2578         if (hw->mac.type == e1000_pchlan) {
2579                 /* Save the NVM K1 bit setting*/
2580                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2581                 if (ret_val)
2582                         return ret_val;
2583
2584                 if (reg & E1000_NVM_K1_ENABLE)
2585                         dev_spec->nvm_k1_enabled = true;
2586                 else
2587                         dev_spec->nvm_k1_enabled = false;
2588         }
2589
2590         ctrl = er32(CTRL);
2591
2592         if (!e1000_check_reset_block(hw)) {
2593                 /*
2594                  * Full-chip reset requires MAC and PHY reset at the same
2595                  * time to make sure the interface between MAC and the
2596                  * external PHY is reset.
2597                  */
2598                 ctrl |= E1000_CTRL_PHY_RST;
2599         }
2600         ret_val = e1000_acquire_swflag_ich8lan(hw);
2601         e_dbg("Issuing a global reset to ich8lan\n");
2602         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2603         msleep(20);
2604
2605         if (!ret_val)
2606                 e1000_release_swflag_ich8lan(hw);
2607
2608         if (ctrl & E1000_CTRL_PHY_RST) {
2609                 ret_val = hw->phy.ops.get_cfg_done(hw);
2610                 if (ret_val)
2611                         goto out;
2612
2613                 ret_val = e1000_post_phy_reset_ich8lan(hw);
2614                 if (ret_val)
2615                         goto out;
2616         }
2617
2618         /*
2619          * For PCH, this write will make sure that any noise
2620          * will be detected as a CRC error and be dropped rather than show up
2621          * as a bad packet to the DMA engine.
2622          */
2623         if (hw->mac.type == e1000_pchlan)
2624                 ew32(CRC_OFFSET, 0x65656565);
2625
2626         ew32(IMC, 0xffffffff);
2627         icr = er32(ICR);
2628
2629         kab = er32(KABGTXD);
2630         kab |= E1000_KABGTXD_BGSQLBIAS;
2631         ew32(KABGTXD, kab);
2632
2633 out:
2634         return ret_val;
2635 }
2636
2637 /**
2638  *  e1000_init_hw_ich8lan - Initialize the hardware
2639  *  @hw: pointer to the HW structure
2640  *
2641  *  Prepares the hardware for transmit and receive by doing the following:
2642  *   - initialize hardware bits
2643  *   - initialize LED identification
2644  *   - setup receive address registers
2645  *   - setup flow control
2646  *   - setup transmit descriptors
2647  *   - clear statistics
2648  **/
2649 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2650 {
2651         struct e1000_mac_info *mac = &hw->mac;
2652         u32 ctrl_ext, txdctl, snoop;
2653         s32 ret_val;
2654         u16 i;
2655
2656         e1000_initialize_hw_bits_ich8lan(hw);
2657
2658         /* Initialize identification LED */
2659         ret_val = mac->ops.id_led_init(hw);
2660         if (ret_val)
2661                 e_dbg("Error initializing identification LED\n");
2662                 /* This is not fatal and we should not stop init due to this */
2663
2664         /* Setup the receive address. */
2665         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2666
2667         /* Zero out the Multicast HASH table */
2668         e_dbg("Zeroing the MTA\n");
2669         for (i = 0; i < mac->mta_reg_count; i++)
2670                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2671
2672         /*
2673          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2674          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2675          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2676          */
2677         if (hw->phy.type == e1000_phy_82578) {
2678                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2679                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2680                 if (ret_val)
2681                         return ret_val;
2682         }
2683
2684         /* Setup link and flow control */
2685         ret_val = e1000_setup_link_ich8lan(hw);
2686
2687         /* Set the transmit descriptor write-back policy for both queues */
2688         txdctl = er32(TXDCTL(0));
2689         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2690                  E1000_TXDCTL_FULL_TX_DESC_WB;
2691         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2692                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2693         ew32(TXDCTL(0), txdctl);
2694         txdctl = er32(TXDCTL(1));
2695         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
2696                  E1000_TXDCTL_FULL_TX_DESC_WB;
2697         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
2698                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
2699         ew32(TXDCTL(1), txdctl);
2700
2701         /*
2702          * ICH8 has opposite polarity of no_snoop bits.
2703          * By default, we should use snoop behavior.
2704          */
2705         if (mac->type == e1000_ich8lan)
2706                 snoop = PCIE_ICH8_SNOOP_ALL;
2707         else
2708                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
2709         e1000e_set_pcie_no_snoop(hw, snoop);
2710
2711         ctrl_ext = er32(CTRL_EXT);
2712         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
2713         ew32(CTRL_EXT, ctrl_ext);
2714
2715         /*
2716          * Clear all of the statistics registers (clear on read).  It is
2717          * important that we do this after we have tried to establish link
2718          * because the symbol error count will increment wildly if there
2719          * is no link.
2720          */
2721         e1000_clear_hw_cntrs_ich8lan(hw);
2722
2723         return 0;
2724 }
2725 /**
2726  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
2727  *  @hw: pointer to the HW structure
2728  *
2729  *  Sets/Clears required hardware bits necessary for correctly setting up the
2730  *  hardware for transmit and receive.
2731  **/
2732 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
2733 {
2734         u32 reg;
2735
2736         /* Extended Device Control */
2737         reg = er32(CTRL_EXT);
2738         reg |= (1 << 22);
2739         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
2740         if (hw->mac.type >= e1000_pchlan)
2741                 reg |= E1000_CTRL_EXT_PHYPDEN;
2742         ew32(CTRL_EXT, reg);
2743
2744         /* Transmit Descriptor Control 0 */
2745         reg = er32(TXDCTL(0));
2746         reg |= (1 << 22);
2747         ew32(TXDCTL(0), reg);
2748
2749         /* Transmit Descriptor Control 1 */
2750         reg = er32(TXDCTL(1));
2751         reg |= (1 << 22);
2752         ew32(TXDCTL(1), reg);
2753
2754         /* Transmit Arbitration Control 0 */
2755         reg = er32(TARC(0));
2756         if (hw->mac.type == e1000_ich8lan)
2757                 reg |= (1 << 28) | (1 << 29);
2758         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
2759         ew32(TARC(0), reg);
2760
2761         /* Transmit Arbitration Control 1 */
2762         reg = er32(TARC(1));
2763         if (er32(TCTL) & E1000_TCTL_MULR)
2764                 reg &= ~(1 << 28);
2765         else
2766                 reg |= (1 << 28);
2767         reg |= (1 << 24) | (1 << 26) | (1 << 30);
2768         ew32(TARC(1), reg);
2769
2770         /* Device Status */
2771         if (hw->mac.type == e1000_ich8lan) {
2772                 reg = er32(STATUS);
2773                 reg &= ~(1 << 31);
2774                 ew32(STATUS, reg);
2775         }
2776
2777         /*
2778          * work-around descriptor data corruption issue during nfs v2 udp
2779          * traffic, just disable the nfs filtering capability
2780          */
2781         reg = er32(RFCTL);
2782         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
2783         ew32(RFCTL, reg);
2784 }
2785
2786 /**
2787  *  e1000_setup_link_ich8lan - Setup flow control and link settings
2788  *  @hw: pointer to the HW structure
2789  *
2790  *  Determines which flow control settings to use, then configures flow
2791  *  control.  Calls the appropriate media-specific link configuration
2792  *  function.  Assuming the adapter has a valid link partner, a valid link
2793  *  should be established.  Assumes the hardware has previously been reset
2794  *  and the transmitter and receiver are not enabled.
2795  **/
2796 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
2797 {
2798         s32 ret_val;
2799
2800         if (e1000_check_reset_block(hw))
2801                 return 0;
2802
2803         /*
2804          * ICH parts do not have a word in the NVM to determine
2805          * the default flow control setting, so we explicitly
2806          * set it to full.
2807          */
2808         if (hw->fc.requested_mode == e1000_fc_default) {
2809                 /* Workaround h/w hang when Tx flow control enabled */
2810                 if (hw->mac.type == e1000_pchlan)
2811                         hw->fc.requested_mode = e1000_fc_rx_pause;
2812                 else
2813                         hw->fc.requested_mode = e1000_fc_full;
2814         }
2815
2816         /*
2817          * Save off the requested flow control mode for use later.  Depending
2818          * on the link partner's capabilities, we may or may not use this mode.
2819          */
2820         hw->fc.current_mode = hw->fc.requested_mode;
2821
2822         e_dbg("After fix-ups FlowControl is now = %x\n",
2823                 hw->fc.current_mode);
2824
2825         /* Continue to configure the copper link. */
2826         ret_val = e1000_setup_copper_link_ich8lan(hw);
2827         if (ret_val)
2828                 return ret_val;
2829
2830         ew32(FCTTV, hw->fc.pause_time);
2831         if ((hw->phy.type == e1000_phy_82578) ||
2832             (hw->phy.type == e1000_phy_82577)) {
2833                 ew32(FCRTV_PCH, hw->fc.refresh_time);
2834
2835                 ret_val = hw->phy.ops.write_reg(hw,
2836                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
2837                                              hw->fc.pause_time);
2838                 if (ret_val)
2839                         return ret_val;
2840         }
2841
2842         return e1000e_set_fc_watermarks(hw);
2843 }
2844
2845 /**
2846  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
2847  *  @hw: pointer to the HW structure
2848  *
2849  *  Configures the kumeran interface to the PHY to wait the appropriate time
2850  *  when polling the PHY, then call the generic setup_copper_link to finish
2851  *  configuring the copper link.
2852  **/
2853 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
2854 {
2855         u32 ctrl;
2856         s32 ret_val;
2857         u16 reg_data;
2858
2859         ctrl = er32(CTRL);
2860         ctrl |= E1000_CTRL_SLU;
2861         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2862         ew32(CTRL, ctrl);
2863
2864         /*
2865          * Set the mac to wait the maximum time between each iteration
2866          * and increase the max iterations when polling the phy;
2867          * this fixes erroneous timeouts at 10Mbps.
2868          */
2869         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
2870         if (ret_val)
2871                 return ret_val;
2872         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2873                                        &reg_data);
2874         if (ret_val)
2875                 return ret_val;
2876         reg_data |= 0x3F;
2877         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
2878                                         reg_data);
2879         if (ret_val)
2880                 return ret_val;
2881
2882         switch (hw->phy.type) {
2883         case e1000_phy_igp_3:
2884                 ret_val = e1000e_copper_link_setup_igp(hw);
2885                 if (ret_val)
2886                         return ret_val;
2887                 break;
2888         case e1000_phy_bm:
2889         case e1000_phy_82578:
2890                 ret_val = e1000e_copper_link_setup_m88(hw);
2891                 if (ret_val)
2892                         return ret_val;
2893                 break;
2894         case e1000_phy_82577:
2895                 ret_val = e1000_copper_link_setup_82577(hw);
2896                 if (ret_val)
2897                         return ret_val;
2898                 break;
2899         case e1000_phy_ife:
2900                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
2901                                                &reg_data);
2902                 if (ret_val)
2903                         return ret_val;
2904
2905                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2906
2907                 switch (hw->phy.mdix) {
2908                 case 1:
2909                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2910                         break;
2911                 case 2:
2912                         reg_data |= IFE_PMC_FORCE_MDIX;
2913                         break;
2914                 case 0:
2915                 default:
2916                         reg_data |= IFE_PMC_AUTO_MDIX;
2917                         break;
2918                 }
2919                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
2920                                                 reg_data);
2921                 if (ret_val)
2922                         return ret_val;
2923                 break;
2924         default:
2925                 break;
2926         }
2927         return e1000e_setup_copper_link(hw);
2928 }
2929
2930 /**
2931  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2932  *  @hw: pointer to the HW structure
2933  *  @speed: pointer to store current link speed
2934  *  @duplex: pointer to store the current link duplex
2935  *
2936  *  Calls the generic get_speed_and_duplex to retrieve the current link
2937  *  information and then calls the Kumeran lock loss workaround for links at
2938  *  gigabit speeds.
2939  **/
2940 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2941                                           u16 *duplex)
2942 {
2943         s32 ret_val;
2944
2945         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2946         if (ret_val)
2947                 return ret_val;
2948
2949         if ((hw->mac.type == e1000_ich8lan) &&
2950             (hw->phy.type == e1000_phy_igp_3) &&
2951             (*speed == SPEED_1000)) {
2952                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2953         }
2954
2955         return ret_val;
2956 }
2957
2958 /**
2959  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2960  *  @hw: pointer to the HW structure
2961  *
2962  *  Work-around for 82566 Kumeran PCS lock loss:
2963  *  On link status change (i.e. PCI reset, speed change) and link is up and
2964  *  speed is gigabit-
2965  *    0) if workaround is optionally disabled do nothing
2966  *    1) wait 1ms for Kumeran link to come up
2967  *    2) check Kumeran Diagnostic register PCS lock loss bit
2968  *    3) if not set the link is locked (all is good), otherwise...
2969  *    4) reset the PHY
2970  *    5) repeat up to 10 times
2971  *  Note: this is only called for IGP3 copper when speed is 1gb.
2972  **/
2973 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2974 {
2975         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2976         u32 phy_ctrl;
2977         s32 ret_val;
2978         u16 i, data;
2979         bool link;
2980
2981         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2982                 return 0;
2983
2984         /*
2985          * Make sure link is up before proceeding.  If not just return.
2986          * Attempting this while link is negotiating fouled up link
2987          * stability
2988          */
2989         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2990         if (!link)
2991                 return 0;
2992
2993         for (i = 0; i < 10; i++) {
2994                 /* read once to clear */
2995                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2996                 if (ret_val)
2997                         return ret_val;
2998                 /* and again to get new status */
2999                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3000                 if (ret_val)
3001                         return ret_val;
3002
3003                 /* check for PCS lock */
3004                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3005                         return 0;
3006
3007                 /* Issue PHY reset */
3008                 e1000_phy_hw_reset(hw);
3009                 mdelay(5);
3010         }
3011         /* Disable GigE link negotiation */
3012         phy_ctrl = er32(PHY_CTRL);
3013         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3014                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3015         ew32(PHY_CTRL, phy_ctrl);
3016
3017         /*
3018          * Call gig speed drop workaround on Gig disable before accessing
3019          * any PHY registers
3020          */
3021         e1000e_gig_downshift_workaround_ich8lan(hw);
3022
3023         /* unable to acquire PCS lock */
3024         return -E1000_ERR_PHY;
3025 }
3026
3027 /**
3028  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3029  *  @hw: pointer to the HW structure
3030  *  @state: boolean value used to set the current Kumeran workaround state
3031  *
3032  *  If ICH8, set the current Kumeran workaround state (enabled - true
3033  *  /disabled - false).
3034  **/
3035 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3036                                                  bool state)
3037 {
3038         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3039
3040         if (hw->mac.type != e1000_ich8lan) {
3041                 e_dbg("Workaround applies to ICH8 only.\n");
3042                 return;
3043         }
3044
3045         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3046 }
3047
3048 /**
3049  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3050  *  @hw: pointer to the HW structure
3051  *
3052  *  Workaround for 82566 power-down on D3 entry:
3053  *    1) disable gigabit link
3054  *    2) write VR power-down enable
3055  *    3) read it back
3056  *  Continue if successful, else issue LCD reset and repeat
3057  **/
3058 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3059 {
3060         u32 reg;
3061         u16 data;
3062         u8  retry = 0;
3063
3064         if (hw->phy.type != e1000_phy_igp_3)
3065                 return;
3066
3067         /* Try the workaround twice (if needed) */
3068         do {
3069                 /* Disable link */
3070                 reg = er32(PHY_CTRL);
3071                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3072                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3073                 ew32(PHY_CTRL, reg);
3074
3075                 /*
3076                  * Call gig speed drop workaround on Gig disable before
3077                  * accessing any PHY registers
3078                  */
3079                 if (hw->mac.type == e1000_ich8lan)
3080                         e1000e_gig_downshift_workaround_ich8lan(hw);
3081
3082                 /* Write VR power-down enable */
3083                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3084                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3085                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3086
3087                 /* Read it back and test */
3088                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3089                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3090                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3091                         break;
3092
3093                 /* Issue PHY reset and repeat at most one more time */
3094                 reg = er32(CTRL);
3095                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3096                 retry++;
3097         } while (retry);
3098 }
3099
3100 /**
3101  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3102  *  @hw: pointer to the HW structure
3103  *
3104  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3105  *  LPLU, Gig disable, MDIC PHY reset):
3106  *    1) Set Kumeran Near-end loopback
3107  *    2) Clear Kumeran Near-end loopback
3108  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3109  **/
3110 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3111 {
3112         s32 ret_val;
3113         u16 reg_data;
3114
3115         if ((hw->mac.type != e1000_ich8lan) ||
3116             (hw->phy.type != e1000_phy_igp_3))
3117                 return;
3118
3119         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3120                                       &reg_data);
3121         if (ret_val)
3122                 return;
3123         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3124         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3125                                        reg_data);
3126         if (ret_val)
3127                 return;
3128         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3129         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3130                                        reg_data);
3131 }
3132
3133 /**
3134  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3135  *  @hw: pointer to the HW structure
3136  *
3137  *  During S0 to Sx transition, it is possible the link remains at gig
3138  *  instead of negotiating to a lower speed.  Before going to Sx, set
3139  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3140  *  to a lower speed.
3141  *
3142  *  Should only be called for applicable parts.
3143  **/
3144 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3145 {
3146         u32 phy_ctrl;
3147
3148         switch (hw->mac.type) {
3149         case e1000_ich8lan:
3150         case e1000_ich9lan:
3151         case e1000_ich10lan:
3152         case e1000_pchlan:
3153                 phy_ctrl = er32(PHY_CTRL);
3154                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
3155                             E1000_PHY_CTRL_GBE_DISABLE;
3156                 ew32(PHY_CTRL, phy_ctrl);
3157
3158                 if (hw->mac.type == e1000_pchlan)
3159                         e1000_phy_hw_reset_ich8lan(hw);
3160         default:
3161                 break;
3162         }
3163 }
3164
3165 /**
3166  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3167  *  @hw: pointer to the HW structure
3168  *
3169  *  Return the LED back to the default configuration.
3170  **/
3171 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3172 {
3173         if (hw->phy.type == e1000_phy_ife)
3174                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3175
3176         ew32(LEDCTL, hw->mac.ledctl_default);
3177         return 0;
3178 }
3179
3180 /**
3181  *  e1000_led_on_ich8lan - Turn LEDs on
3182  *  @hw: pointer to the HW structure
3183  *
3184  *  Turn on the LEDs.
3185  **/
3186 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3187 {
3188         if (hw->phy.type == e1000_phy_ife)
3189                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3190                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3191
3192         ew32(LEDCTL, hw->mac.ledctl_mode2);
3193         return 0;
3194 }
3195
3196 /**
3197  *  e1000_led_off_ich8lan - Turn LEDs off
3198  *  @hw: pointer to the HW structure
3199  *
3200  *  Turn off the LEDs.
3201  **/
3202 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3203 {
3204         if (hw->phy.type == e1000_phy_ife)
3205                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3206                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3207
3208         ew32(LEDCTL, hw->mac.ledctl_mode1);
3209         return 0;
3210 }
3211
3212 /**
3213  *  e1000_setup_led_pchlan - Configures SW controllable LED
3214  *  @hw: pointer to the HW structure
3215  *
3216  *  This prepares the SW controllable LED for use.
3217  **/
3218 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3219 {
3220         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3221                                         (u16)hw->mac.ledctl_mode1);
3222 }
3223
3224 /**
3225  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3226  *  @hw: pointer to the HW structure
3227  *
3228  *  Return the LED back to the default configuration.
3229  **/
3230 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3231 {
3232         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3233                                         (u16)hw->mac.ledctl_default);
3234 }
3235
3236 /**
3237  *  e1000_led_on_pchlan - Turn LEDs on
3238  *  @hw: pointer to the HW structure
3239  *
3240  *  Turn on the LEDs.
3241  **/
3242 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3243 {
3244         u16 data = (u16)hw->mac.ledctl_mode2;
3245         u32 i, led;
3246
3247         /*
3248          * If no link, then turn LED on by setting the invert bit
3249          * for each LED that's mode is "link_up" in ledctl_mode2.
3250          */
3251         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3252                 for (i = 0; i < 3; i++) {
3253                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3254                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3255                             E1000_LEDCTL_MODE_LINK_UP)
3256                                 continue;
3257                         if (led & E1000_PHY_LED0_IVRT)
3258                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3259                         else
3260                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3261                 }
3262         }
3263
3264         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3265 }
3266
3267 /**
3268  *  e1000_led_off_pchlan - Turn LEDs off
3269  *  @hw: pointer to the HW structure
3270  *
3271  *  Turn off the LEDs.
3272  **/
3273 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3274 {
3275         u16 data = (u16)hw->mac.ledctl_mode1;
3276         u32 i, led;
3277
3278         /*
3279          * If no link, then turn LED off by clearing the invert bit
3280          * for each LED that's mode is "link_up" in ledctl_mode1.
3281          */
3282         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3283                 for (i = 0; i < 3; i++) {
3284                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3285                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3286                             E1000_LEDCTL_MODE_LINK_UP)
3287                                 continue;
3288                         if (led & E1000_PHY_LED0_IVRT)
3289                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3290                         else
3291                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3292                 }
3293         }
3294
3295         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3296 }
3297
3298 /**
3299  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3300  *  @hw: pointer to the HW structure
3301  *
3302  *  Read appropriate register for the config done bit for completion status
3303  *  and configure the PHY through s/w for EEPROM-less parts.
3304  *
3305  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3306  *  config done bit, so only an error is logged and continues.  If we were
3307  *  to return with error, EEPROM-less silicon would not be able to be reset
3308  *  or change link.
3309  **/
3310 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3311 {
3312         s32 ret_val = 0;
3313         u32 bank = 0;
3314         u32 status;
3315
3316         e1000e_get_cfg_done(hw);
3317
3318         /* Wait for indication from h/w that it has completed basic config */
3319         if (hw->mac.type >= e1000_ich10lan) {
3320                 e1000_lan_init_done_ich8lan(hw);
3321         } else {
3322                 ret_val = e1000e_get_auto_rd_done(hw);
3323                 if (ret_val) {
3324                         /*
3325                          * When auto config read does not complete, do not
3326                          * return with an error. This can happen in situations
3327                          * where there is no eeprom and prevents getting link.
3328                          */
3329                         e_dbg("Auto Read Done did not complete\n");
3330                         ret_val = 0;
3331                 }
3332         }
3333
3334         /* Clear PHY Reset Asserted bit */
3335         status = er32(STATUS);
3336         if (status & E1000_STATUS_PHYRA)
3337                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3338         else
3339                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3340
3341         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3342         if (hw->mac.type <= e1000_ich9lan) {
3343                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3344                     (hw->phy.type == e1000_phy_igp_3)) {
3345                         e1000e_phy_init_script_igp3(hw);
3346                 }
3347         } else {
3348                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3349                         /* Maybe we should do a basic PHY config */
3350                         e_dbg("EEPROM not present\n");
3351                         ret_val = -E1000_ERR_CONFIG;
3352                 }
3353         }
3354
3355         return ret_val;
3356 }
3357
3358 /**
3359  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3360  * @hw: pointer to the HW structure
3361  *
3362  * In the case of a PHY power down to save power, or to turn off link during a
3363  * driver unload, or wake on lan is not enabled, remove the link.
3364  **/
3365 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3366 {
3367         /* If the management interface is not enabled, then power down */
3368         if (!(hw->mac.ops.check_mng_mode(hw) ||
3369               hw->phy.ops.check_reset_block(hw)))
3370                 e1000_power_down_phy_copper(hw);
3371 }
3372
3373 /**
3374  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3375  *  @hw: pointer to the HW structure
3376  *
3377  *  Clears hardware counters specific to the silicon family and calls
3378  *  clear_hw_cntrs_generic to clear all general purpose counters.
3379  **/
3380 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3381 {
3382         u16 phy_data;
3383
3384         e1000e_clear_hw_cntrs_base(hw);
3385
3386         er32(ALGNERRC);
3387         er32(RXERRC);
3388         er32(TNCRS);
3389         er32(CEXTERR);
3390         er32(TSCTC);
3391         er32(TSCTFC);
3392
3393         er32(MGTPRC);
3394         er32(MGTPDC);
3395         er32(MGTPTC);
3396
3397         er32(IAC);
3398         er32(ICRXOC);
3399
3400         /* Clear PHY statistics registers */
3401         if ((hw->phy.type == e1000_phy_82578) ||
3402             (hw->phy.type == e1000_phy_82577)) {
3403                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3404                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3405                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3406                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3407                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3408                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3409                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3410                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3411                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3412                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3413                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3414                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3415                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3416                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3417         }
3418 }
3419
3420 static struct e1000_mac_operations ich8_mac_ops = {
3421         .id_led_init            = e1000e_id_led_init,
3422         /* check_mng_mode dependent on mac type */
3423         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3424         /* cleanup_led dependent on mac type */
3425         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3426         .get_bus_info           = e1000_get_bus_info_ich8lan,
3427         .set_lan_id             = e1000_set_lan_id_single_port,
3428         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3429         /* led_on dependent on mac type */
3430         /* led_off dependent on mac type */
3431         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3432         .reset_hw               = e1000_reset_hw_ich8lan,
3433         .init_hw                = e1000_init_hw_ich8lan,
3434         .setup_link             = e1000_setup_link_ich8lan,
3435         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3436         /* id_led_init dependent on mac type */
3437 };
3438
3439 static struct e1000_phy_operations ich8_phy_ops = {
3440         .acquire                = e1000_acquire_swflag_ich8lan,
3441         .check_reset_block      = e1000_check_reset_block_ich8lan,
3442         .commit                 = NULL,
3443         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3444         .get_cable_length       = e1000e_get_cable_length_igp_2,
3445         .read_reg               = e1000e_read_phy_reg_igp,
3446         .release                = e1000_release_swflag_ich8lan,
3447         .reset                  = e1000_phy_hw_reset_ich8lan,
3448         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3449         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3450         .write_reg              = e1000e_write_phy_reg_igp,
3451 };
3452
3453 static struct e1000_nvm_operations ich8_nvm_ops = {
3454         .acquire                = e1000_acquire_nvm_ich8lan,
3455         .read                   = e1000_read_nvm_ich8lan,
3456         .release                = e1000_release_nvm_ich8lan,
3457         .update                 = e1000_update_nvm_checksum_ich8lan,
3458         .valid_led_default      = e1000_valid_led_default_ich8lan,
3459         .validate               = e1000_validate_nvm_checksum_ich8lan,
3460         .write                  = e1000_write_nvm_ich8lan,
3461 };
3462
3463 struct e1000_info e1000_ich8_info = {
3464         .mac                    = e1000_ich8lan,
3465         .flags                  = FLAG_HAS_WOL
3466                                   | FLAG_IS_ICH
3467                                   | FLAG_RX_CSUM_ENABLED
3468                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3469                                   | FLAG_HAS_AMT
3470                                   | FLAG_HAS_FLASH
3471                                   | FLAG_APME_IN_WUC,
3472         .pba                    = 8,
3473         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3474         .get_variants           = e1000_get_variants_ich8lan,
3475         .mac_ops                = &ich8_mac_ops,
3476         .phy_ops                = &ich8_phy_ops,
3477         .nvm_ops                = &ich8_nvm_ops,
3478 };
3479
3480 struct e1000_info e1000_ich9_info = {
3481         .mac                    = e1000_ich9lan,
3482         .flags                  = FLAG_HAS_JUMBO_FRAMES
3483                                   | FLAG_IS_ICH
3484                                   | FLAG_HAS_WOL
3485                                   | FLAG_RX_CSUM_ENABLED
3486                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3487                                   | FLAG_HAS_AMT
3488                                   | FLAG_HAS_ERT
3489                                   | FLAG_HAS_FLASH
3490                                   | FLAG_APME_IN_WUC,
3491         .pba                    = 10,
3492         .max_hw_frame_size      = DEFAULT_JUMBO,
3493         .get_variants           = e1000_get_variants_ich8lan,
3494         .mac_ops                = &ich8_mac_ops,
3495         .phy_ops                = &ich8_phy_ops,
3496         .nvm_ops                = &ich8_nvm_ops,
3497 };
3498
3499 struct e1000_info e1000_ich10_info = {
3500         .mac                    = e1000_ich10lan,
3501         .flags                  = FLAG_HAS_JUMBO_FRAMES
3502                                   | FLAG_IS_ICH
3503                                   | FLAG_HAS_WOL
3504                                   | FLAG_RX_CSUM_ENABLED
3505                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3506                                   | FLAG_HAS_AMT
3507                                   | FLAG_HAS_ERT
3508                                   | FLAG_HAS_FLASH
3509                                   | FLAG_APME_IN_WUC,
3510         .pba                    = 10,
3511         .max_hw_frame_size      = DEFAULT_JUMBO,
3512         .get_variants           = e1000_get_variants_ich8lan,
3513         .mac_ops                = &ich8_mac_ops,
3514         .phy_ops                = &ich8_phy_ops,
3515         .nvm_ops                = &ich8_nvm_ops,
3516 };
3517
3518 struct e1000_info e1000_pch_info = {
3519         .mac                    = e1000_pchlan,
3520         .flags                  = FLAG_IS_ICH
3521                                   | FLAG_HAS_WOL
3522                                   | FLAG_RX_CSUM_ENABLED
3523                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3524                                   | FLAG_HAS_AMT
3525                                   | FLAG_HAS_FLASH
3526                                   | FLAG_HAS_JUMBO_FRAMES
3527                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3528                                   | FLAG_APME_IN_WUC,
3529         .flags2                 = FLAG2_HAS_PHY_STATS,
3530         .pba                    = 26,
3531         .max_hw_frame_size      = 4096,
3532         .get_variants           = e1000_get_variants_ich8lan,
3533         .mac_ops                = &ich8_mac_ops,
3534         .phy_ops                = &ich8_phy_ops,
3535         .nvm_ops                = &ich8_nvm_ops,
3536 };