drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G 10/100 Network Connection
  31  * 82562G-2 10/100 Network Connection
  32  * 82562GT 10/100 Network Connection
  33  * 82562GT-2 10/100 Network Connection
  34  * 82562V 10/100 Network Connection
  35  * 82562V-2 10/100 Network Connection
  36  * 82566DC-2 Gigabit Network Connection
  37  * 82566DC Gigabit Network Connection
  38  * 82566DM-2 Gigabit Network Connection
  39  * 82566DM Gigabit Network Connection
  40  * 82566MC Gigabit Network Connection
  41  * 82566MM Gigabit Network Connection
  42  * 82567LM Gigabit Network Connection
  43  * 82567LF Gigabit Network Connection
  44  * 82567V Gigabit Network Connection
  45  * 82567LM-2 Gigabit Network Connection
  46  * 82567LF-2 Gigabit Network Connection
  47  * 82567V-2 Gigabit Network Connection
  48  * 82567LF-3 Gigabit Network Connection
  49  * 82567LM-3 Gigabit Network Connection
  50  * 82567LM-4 Gigabit Network Connection
  51  * 82577LM Gigabit Network Connection
  52  * 82577LC Gigabit Network Connection
  53  * 82578DM Gigabit Network Connection
  54  * 82578DC Gigabit Network Connection
  55  * 82579LM Gigabit Network Connection
  56  * 82579V Gigabit Network Connection
  57  */
  58
  59 #include "e1000.h"
  60
  61 #define ICH_FLASH_GFPREG                0x0000
  62 #define ICH_FLASH_HSFSTS                0x0004
  63 #define ICH_FLASH_HSFCTL                0x0006
  64 #define ICH_FLASH_FADDR                 0x0008
  65 #define ICH_FLASH_FDATA0                0x0010
  66 #define ICH_FLASH_PR0                   0x0074
  67
  68 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  71 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  72 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  73
  74 #define ICH_CYCLE_READ                  0
  75 #define ICH_CYCLE_WRITE                 2
  76 #define ICH_CYCLE_ERASE                 3
  77
  78 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  79 #define FLASH_SECTOR_ADDR_SHIFT         12
  80
  81 #define ICH_FLASH_SEG_SIZE_256          256
  82 #define ICH_FLASH_SEG_SIZE_4K           4096
  83 #define ICH_FLASH_SEG_SIZE_8K           8192
  84 #define ICH_FLASH_SEG_SIZE_64K          65536
  85
  86
  87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  88 /* FW established a valid mode */
  89 #define E1000_ICH_FWSM_FW_VALID         0x00008000
  90
  91 #define E1000_ICH_MNG_IAMT_MODE         0x2
  92
  93 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  94                                  (ID_LED_DEF1_OFF2 <<  8) | \
  95                                  (ID_LED_DEF1_ON2  <<  4) | \
  96                                  (ID_LED_DEF1_DEF2))
  97
  98 #define E1000_ICH_NVM_SIG_WORD          0x13
  99 #define E1000_ICH_NVM_SIG_MASK          0xC000
 100 #define E1000_ICH_NVM_VALID_SIG_MASK    0xC0
 101 #define E1000_ICH_NVM_SIG_VALUE         0x80
 102
 103 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
 104
 105 #define E1000_FEXTNVM_SW_CONFIG         1
 106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
 107
 108 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 109
 110 #define E1000_ICH_RAR_ENTRIES           7
 111
 112 #define PHY_PAGE_SHIFT 5
 113 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 114                            ((reg) & MAX_PHY_REG_ADDRESS))
 115 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 116 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 117
 118 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 119 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 120 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 121
 122 #define HV_LED_CONFIG           PHY_REG(768, 30) /* LED Configuration */
 123
 124 #define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
 125
 126 /* SMBus Address Phy Register */
 127 #define HV_SMB_ADDR            PHY_REG(768, 26)
 128 #define HV_SMB_ADDR_PEC_EN     0x0200
 129 #define HV_SMB_ADDR_VALID      0x0080
 130
 131 /* PHY Power Management Control */
 132 #define HV_PM_CTRL              PHY_REG(770, 17)
 133
 134 /* PHY Low Power Idle Control */
 135 #define I82579_LPI_CTRL                 PHY_REG(772, 20)
 136 #define I82579_LPI_CTRL_ENABLE_MASK     0x6000
 137
 138 /* Strapping Option Register - RO */
 139 #define E1000_STRAP                     0x0000C
 140 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
 141 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
 142
 143 /* OEM Bits Phy Register */
 144 #define HV_OEM_BITS            PHY_REG(768, 25)
 145 #define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
 146 #define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
 147 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
 148
 149 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
 150 #define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
 151
 152 /* KMRN Mode Control */
 153 #define HV_KMRN_MODE_CTRL      PHY_REG(769, 16)
 154 #define HV_KMRN_MDIO_SLOW      0x0400
 155
 156 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 157 /* Offset 04h HSFSTS */
 158 union ich8_hws_flash_status {
 159         struct ich8_hsfsts {
 160                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 161                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 162                 u16 dael       :1; /* bit 2 Direct Access error Log */
 163                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 164                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 165                 u16 reserved1  :2; /* bit 13:6 Reserved */
 166                 u16 reserved2  :6; /* bit 13:6 Reserved */
 167                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 168                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 169         } hsf_status;
 170         u16 regval;
 171 };
 172
 173 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 174 /* Offset 06h FLCTL */
 175 union ich8_hws_flash_ctrl {
 176         struct ich8_hsflctl {
 177                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 178                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 179                 u16 reserved   :5;   /* 7:3 Reserved  */
 180                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 181                 u16 flockdn    :6;   /* 15:10 Reserved */
 182         } hsf_ctrl;
 183         u16 regval;
 184 };
 185
 186 /* ICH Flash Region Access Permissions */
 187 union ich8_hws_flash_regacc {
 188         struct ich8_flracc {
 189                 u32 grra      :8; /* 0:7 GbE region Read Access */
 190                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 191                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 192                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 193         } hsf_flregacc;
 194         u16 regval;
 195 };
 196
 197 /* ICH Flash Protected Region */
 198 union ich8_flash_protected_range {
 199         struct ich8_pr {
 200                 u32 base:13;     /* 0:12 Protected Range Base */
 201                 u32 reserved1:2; /* 13:14 Reserved */
 202                 u32 rpe:1;       /* 15 Read Protection Enable */
 203                 u32 limit:13;    /* 16:28 Protected Range Limit */
 204                 u32 reserved2:2; /* 29:30 Reserved */
 205                 u32 wpe:1;       /* 31 Write Protection Enable */
 206         } range;
 207         u32 regval;
 208 };
 209
 210 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 211 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 212 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 213 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 214 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 215                                                 u32 offset, u8 byte);
 216 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
 217                                          u8 *data);
 218 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 219                                          u16 *data);
 220 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 221                                          u8 size, u16 *data);
 222 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 223 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 224 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
 225 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
 226 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
 227 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
 228 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
 229 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
 230 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
 231 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
 232 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
 233 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
 234 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
 235 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
 236 static s32  e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
 237 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
 238 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
 239 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
 240
 241 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 242 {
 243         return readw(hw->flash_address + reg);
 244 }
 245
 246 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 247 {
 248         return readl(hw->flash_address + reg);
 249 }
 250
 251 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 252 {
 253         writew(val, hw->flash_address + reg);
 254 }
 255
 256 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 257 {
 258         writel(val, hw->flash_address + reg);
 259 }
 260
 261 #define er16flash(reg)          __er16flash(hw, (reg))
 262 #define er32flash(reg)          __er32flash(hw, (reg))
 263 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 264 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 265
 266 /**
 267  *  e1000_init_phy_params_pchlan - Initialize PHY function pointers
 268  *  @hw: pointer to the HW structure
 269  *
 270  *  Initialize family-specific PHY parameters and function pointers.
 271  **/
 272 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
 273 {
 274         struct e1000_phy_info *phy = &hw->phy;
 275         u32 ctrl;
 276         s32 ret_val = 0;
 277
 278         phy->addr                     = 1;
 279         phy->reset_delay_us           = 100;
 280
 281         phy->ops.read_reg             = e1000_read_phy_reg_hv;
 282         phy->ops.read_reg_locked      = e1000_read_phy_reg_hv_locked;
 283         phy->ops.set_d0_lplu_state    = e1000_set_lplu_state_pchlan;
 284         phy->ops.set_d3_lplu_state    = e1000_set_lplu_state_pchlan;
 285         phy->ops.write_reg            = e1000_write_phy_reg_hv;
 286         phy->ops.write_reg_locked     = e1000_write_phy_reg_hv_locked;
 287         phy->ops.power_up             = e1000_power_up_phy_copper;
 288         phy->ops.power_down           = e1000_power_down_phy_copper_ich8lan;
 289         phy->autoneg_mask             = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 290
 291         /*
 292          * The MAC-PHY interconnect may still be in SMBus mode
 293          * after Sx->S0.  If the manageability engine (ME) is
 294          * disabled, then toggle the LANPHYPC Value bit to force
 295          * the interconnect to PCIe mode.
 296          */
 297         if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
 298                 ctrl = er32(CTRL);
 299                 ctrl |=  E1000_CTRL_LANPHYPC_OVERRIDE;
 300                 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
 301                 ew32(CTRL, ctrl);
 302                 udelay(10);
 303                 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
 304                 ew32(CTRL, ctrl);
 305                 msleep(50);
 306         }
 307
 308         /*
 309          * Reset the PHY before any acccess to it.  Doing so, ensures that
 310          * the PHY is in a known good state before we read/write PHY registers.
 311          * The generic reset is sufficient here, because we haven't determined
 312          * the PHY type yet.
 313          */
 314         ret_val = e1000e_phy_hw_reset_generic(hw);
 315         if (ret_val)
 316                 goto out;
 317
 318         phy->id = e1000_phy_unknown;
 319         ret_val = e1000e_get_phy_id(hw);
 320         if (ret_val)
 321                 goto out;
 322         if ((phy->id == 0) || (phy->id == PHY_REVISION_MASK)) {
 323                 /*
 324                  * In case the PHY needs to be in mdio slow mode (eg. 82577),
 325                  * set slow mode and try to get the PHY id again.
 326                  */
 327                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
 328                 if (ret_val)
 329                         goto out;
 330                 ret_val = e1000e_get_phy_id(hw);
 331                 if (ret_val)
 332                         goto out;
 333         }
 334         phy->type = e1000e_get_phy_type_from_id(phy->id);
 335
 336         switch (phy->type) {
 337         case e1000_phy_82577:
 338         case e1000_phy_82579:
 339                 phy->ops.check_polarity = e1000_check_polarity_82577;
 340                 phy->ops.force_speed_duplex =
 341                         e1000_phy_force_speed_duplex_82577;
 342                 phy->ops.get_cable_length = e1000_get_cable_length_82577;
 343                 phy->ops.get_info = e1000_get_phy_info_82577;
 344                 phy->ops.commit = e1000e_phy_sw_reset;
 345                 break;
 346         case e1000_phy_82578:
 347                 phy->ops.check_polarity = e1000_check_polarity_m88;
 348                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 349                 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
 350                 phy->ops.get_info = e1000e_get_phy_info_m88;
 351                 break;
 352         default:
 353                 ret_val = -E1000_ERR_PHY;
 354                 break;
 355         }
 356
 357 out:
 358         return ret_val;
 359 }
 360
 361 /**
 362  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 363  *  @hw: pointer to the HW structure
 364  *
 365  *  Initialize family-specific PHY parameters and function pointers.
 366  **/
 367 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 368 {
 369         struct e1000_phy_info *phy = &hw->phy;
 370         s32 ret_val;
 371         u16 i = 0;
 372
 373         phy->addr                       = 1;
 374         phy->reset_delay_us             = 100;
 375
 376         phy->ops.power_up               = e1000_power_up_phy_copper;
 377         phy->ops.power_down             = e1000_power_down_phy_copper_ich8lan;
 378
 379         /*
 380          * We may need to do this twice - once for IGP and if that fails,
 381          * we'll set BM func pointers and try again
 382          */
 383         ret_val = e1000e_determine_phy_address(hw);
 384         if (ret_val) {
 385                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 386                 phy->ops.read_reg  = e1000e_read_phy_reg_bm;
 387                 ret_val = e1000e_determine_phy_address(hw);
 388                 if (ret_val) {
 389                         e_dbg("Cannot determine PHY addr. Erroring out\n");
 390                         return ret_val;
 391                 }
 392         }
 393
 394         phy->id = 0;
 395         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 396                (i++ < 100)) {
 397                 msleep(1);
 398                 ret_val = e1000e_get_phy_id(hw);
 399                 if (ret_val)
 400                         return ret_val;
 401         }
 402
 403         /* Verify phy id */
 404         switch (phy->id) {
 405         case IGP03E1000_E_PHY_ID:
 406                 phy->type = e1000_phy_igp_3;
 407                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 408                 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
 409                 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
 410                 phy->ops.get_info = e1000e_get_phy_info_igp;
 411                 phy->ops.check_polarity = e1000_check_polarity_igp;
 412                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
 413                 break;
 414         case IFE_E_PHY_ID:
 415         case IFE_PLUS_E_PHY_ID:
 416         case IFE_C_E_PHY_ID:
 417                 phy->type = e1000_phy_ife;
 418                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 419                 phy->ops.get_info = e1000_get_phy_info_ife;
 420                 phy->ops.check_polarity = e1000_check_polarity_ife;
 421                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
 422                 break;
 423         case BME1000_E_PHY_ID:
 424                 phy->type = e1000_phy_bm;
 425                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 426                 phy->ops.read_reg = e1000e_read_phy_reg_bm;
 427                 phy->ops.write_reg = e1000e_write_phy_reg_bm;
 428                 phy->ops.commit = e1000e_phy_sw_reset;
 429                 phy->ops.get_info = e1000e_get_phy_info_m88;
 430                 phy->ops.check_polarity = e1000_check_polarity_m88;
 431                 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
 432                 break;
 433         default:
 434                 return -E1000_ERR_PHY;
 435                 break;
 436         }
 437
 438         return 0;
 439 }
 440
 441 /**
 442  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 443  *  @hw: pointer to the HW structure
 444  *
 445  *  Initialize family-specific NVM parameters and function
 446  *  pointers.
 447  **/
 448 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 449 {
 450         struct e1000_nvm_info *nvm = &hw->nvm;
 451         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 452         u32 gfpreg, sector_base_addr, sector_end_addr;
 453         u16 i;
 454
 455         /* Can't read flash registers if the register set isn't mapped. */
 456         if (!hw->flash_address) {
 457                 e_dbg("ERROR: Flash registers not mapped\n");
 458                 return -E1000_ERR_CONFIG;
 459         }
 460
 461         nvm->type = e1000_nvm_flash_sw;
 462
 463         gfpreg = er32flash(ICH_FLASH_GFPREG);
 464
 465         /*
 466          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 467          * Add 1 to sector_end_addr since this sector is included in
 468          * the overall size.
 469          */
 470         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 471         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 472
 473         /* flash_base_addr is byte-aligned */
 474         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 475
 476         /*
 477          * find total size of the NVM, then cut in half since the total
 478          * size represents two separate NVM banks.
 479          */
 480         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 481                                 << FLASH_SECTOR_ADDR_SHIFT;
 482         nvm->flash_bank_size /= 2;
 483         /* Adjust to word count */
 484         nvm->flash_bank_size /= sizeof(u16);
 485
 486         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 487
 488         /* Clear shadow ram */
 489         for (i = 0; i < nvm->word_size; i++) {
 490                 dev_spec->shadow_ram[i].modified = false;
 491                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 492         }
 493
 494         return 0;
 495 }
 496
 497 /**
 498  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 499  *  @hw: pointer to the HW structure
 500  *
 501  *  Initialize family-specific MAC parameters and function
 502  *  pointers.
 503  **/
 504 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 505 {
 506         struct e1000_hw *hw = &adapter->hw;
 507         struct e1000_mac_info *mac = &hw->mac;
 508
 509         /* Set media type function pointer */
 510         hw->phy.media_type = e1000_media_type_copper;
 511
 512         /* Set mta register count */
 513         mac->mta_reg_count = 32;
 514         /* Set rar entry count */
 515         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 516         if (mac->type == e1000_ich8lan)
 517                 mac->rar_entry_count--;
 518         /* FWSM register */
 519         mac->has_fwsm = true;
 520         /* ARC subsystem not supported */
 521         mac->arc_subsystem_valid = false;
 522         /* Adaptive IFS supported */
 523         mac->adaptive_ifs = true;
 524
 525         /* LED operations */
 526         switch (mac->type) {
 527         case e1000_ich8lan:
 528         case e1000_ich9lan:
 529         case e1000_ich10lan:
 530                 /* check management mode */
 531                 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
 532                 /* ID LED init */
 533                 mac->ops.id_led_init = e1000e_id_led_init;
 534                 /* setup LED */
 535                 mac->ops.setup_led = e1000e_setup_led_generic;
 536                 /* cleanup LED */
 537                 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
 538                 /* turn on/off LED */
 539                 mac->ops.led_on = e1000_led_on_ich8lan;
 540                 mac->ops.led_off = e1000_led_off_ich8lan;
 541                 break;
 542         case e1000_pchlan:
 543         case e1000_pch2lan:
 544                 /* check management mode */
 545                 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
 546                 /* ID LED init */
 547                 mac->ops.id_led_init = e1000_id_led_init_pchlan;
 548                 /* setup LED */
 549                 mac->ops.setup_led = e1000_setup_led_pchlan;
 550                 /* cleanup LED */
 551                 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
 552                 /* turn on/off LED */
 553                 mac->ops.led_on = e1000_led_on_pchlan;
 554                 mac->ops.led_off = e1000_led_off_pchlan;
 555                 break;
 556         default:
 557                 break;
 558         }
 559
 560         /* Enable PCS Lock-loss workaround for ICH8 */
 561         if (mac->type == e1000_ich8lan)
 562                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
 563
 564         /* Disable PHY configuration by hardware, config by software */
 565         if (mac->type == e1000_pch2lan) {
 566                 u32 extcnf_ctrl = er32(EXTCNF_CTRL);
 567
 568                 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
 569                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 570         }
 571
 572         return 0;
 573 }
 574
 575 /**
 576  *  e1000_set_eee_pchlan - Enable/disable EEE support
 577  *  @hw: pointer to the HW structure
 578  *
 579  *  Enable/disable EEE based on setting in dev_spec structure.  The bits in
 580  *  the LPI Control register will remain set only if/when link is up.
 581  **/
 582 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
 583 {
 584         s32 ret_val = 0;
 585         u16 phy_reg;
 586
 587         if (hw->phy.type != e1000_phy_82579)
 588                 goto out;
 589
 590         ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
 591         if (ret_val)
 592                 goto out;
 593
 594         if (hw->dev_spec.ich8lan.eee_disable)
 595                 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
 596         else
 597                 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
 598
 599         ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
 600 out:
 601         return ret_val;
 602 }
 603
 604 /**
 605  *  e1000_check_for_copper_link_ich8lan - Check for link (Copper)
 606  *  @hw: pointer to the HW structure
 607  *
 608  *  Checks to see of the link status of the hardware has changed.  If a
 609  *  change in link status has been detected, then we read the PHY registers
 610  *  to get the current speed/duplex if link exists.
 611  **/
 612 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
 613 {
 614         struct e1000_mac_info *mac = &hw->mac;
 615         s32 ret_val;
 616         bool link;
 617
 618         /*
 619          * We only want to go out to the PHY registers to see if Auto-Neg
 620          * has completed and/or if our link status has changed.  The
 621          * get_link_status flag is set upon receiving a Link Status
 622          * Change or Rx Sequence Error interrupt.
 623          */
 624         if (!mac->get_link_status) {
 625                 ret_val = 0;
 626                 goto out;
 627         }
 628
 629         /*
 630          * First we want to see if the MII Status Register reports
 631          * link.  If so, then we want to get the current speed/duplex
 632          * of the PHY.
 633          */
 634         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 635         if (ret_val)
 636                 goto out;
 637
 638         if (hw->mac.type == e1000_pchlan) {
 639                 ret_val = e1000_k1_gig_workaround_hv(hw, link);
 640                 if (ret_val)
 641                         goto out;
 642         }
 643
 644         if (!link)
 645                 goto out; /* No link detected */
 646
 647         mac->get_link_status = false;
 648
 649         if (hw->phy.type == e1000_phy_82578) {
 650                 ret_val = e1000_link_stall_workaround_hv(hw);
 651                 if (ret_val)
 652                         goto out;
 653         }
 654
 655         /*
 656          * Check if there was DownShift, must be checked
 657          * immediately after link-up
 658          */
 659         e1000e_check_downshift(hw);
 660
 661         /* Enable/Disable EEE after link up */
 662         ret_val = e1000_set_eee_pchlan(hw);
 663         if (ret_val)
 664                 goto out;
 665
 666         /*
 667          * If we are forcing speed/duplex, then we simply return since
 668          * we have already determined whether we have link or not.
 669          */
 670         if (!mac->autoneg) {
 671                 ret_val = -E1000_ERR_CONFIG;
 672                 goto out;
 673         }
 674
 675         /*
 676          * Auto-Neg is enabled.  Auto Speed Detection takes care
 677          * of MAC speed/duplex configuration.  So we only need to
 678          * configure Collision Distance in the MAC.
 679          */
 680         e1000e_config_collision_dist(hw);
 681
 682         /*
 683          * Configure Flow Control now that Auto-Neg has completed.
 684          * First, we need to restore the desired flow control
 685          * settings because we may have had to re-autoneg with a
 686          * different link partner.
 687          */
 688         ret_val = e1000e_config_fc_after_link_up(hw);
 689         if (ret_val)
 690                 e_dbg("Error configuring flow control\n");
 691
 692 out:
 693         return ret_val;
 694 }
 695
 696 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 697 {
 698         struct e1000_hw *hw = &adapter->hw;
 699         s32 rc;
 700
 701         rc = e1000_init_mac_params_ich8lan(adapter);
 702         if (rc)
 703                 return rc;
 704
 705         rc = e1000_init_nvm_params_ich8lan(hw);
 706         if (rc)
 707                 return rc;
 708
 709         switch (hw->mac.type) {
 710         case e1000_ich8lan:
 711         case e1000_ich9lan:
 712         case e1000_ich10lan:
 713                 rc = e1000_init_phy_params_ich8lan(hw);
 714                 break;
 715         case e1000_pchlan:
 716         case e1000_pch2lan:
 717                 rc = e1000_init_phy_params_pchlan(hw);
 718                 break;
 719         default:
 720                 break;
 721         }
 722         if (rc)
 723                 return rc;
 724
 725         if (adapter->hw.phy.type == e1000_phy_ife) {
 726                 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
 727                 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
 728         }
 729
 730         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 731             (adapter->hw.phy.type == e1000_phy_igp_3))
 732                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 733
 734         /* Disable EEE by default until IEEE802.3az spec is finalized */
 735         if (adapter->flags2 & FLAG2_HAS_EEE)
 736                 adapter->hw.dev_spec.ich8lan.eee_disable = true;
 737
 738         return 0;
 739 }
 740
 741 static DEFINE_MUTEX(nvm_mutex);
 742
 743 /**
 744  *  e1000_acquire_nvm_ich8lan - Acquire NVM mutex
 745  *  @hw: pointer to the HW structure
 746  *
 747  *  Acquires the mutex for performing NVM operations.
 748  **/
 749 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
 750 {
 751         mutex_lock(&nvm_mutex);
 752
 753         return 0;
 754 }
 755
 756 /**
 757  *  e1000_release_nvm_ich8lan - Release NVM mutex
 758  *  @hw: pointer to the HW structure
 759  *
 760  *  Releases the mutex used while performing NVM operations.
 761  **/
 762 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
 763 {
 764         mutex_unlock(&nvm_mutex);
 765 }
 766
 767 static DEFINE_MUTEX(swflag_mutex);
 768
 769 /**
 770  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 771  *  @hw: pointer to the HW structure
 772  *
 773  *  Acquires the software control flag for performing PHY and select
 774  *  MAC CSR accesses.
 775  **/
 776 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 777 {
 778         u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
 779         s32 ret_val = 0;
 780
 781         mutex_lock(&swflag_mutex);
 782
 783         while (timeout) {
 784                 extcnf_ctrl = er32(EXTCNF_CTRL);
 785                 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
 786                         break;
 787
 788                 mdelay(1);
 789                 timeout--;
 790         }
 791
 792         if (!timeout) {
 793                 e_dbg("SW/FW/HW has locked the resource for too long.\n");
 794                 ret_val = -E1000_ERR_CONFIG;
 795                 goto out;
 796         }
 797
 798         timeout = SW_FLAG_TIMEOUT;
 799
 800         extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 801         ew32(EXTCNF_CTRL, extcnf_ctrl);
 802
 803         while (timeout) {
 804                 extcnf_ctrl = er32(EXTCNF_CTRL);
 805                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 806                         break;
 807
 808                 mdelay(1);
 809                 timeout--;
 810         }
 811
 812         if (!timeout) {
 813                 e_dbg("Failed to acquire the semaphore.\n");
 814                 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 815                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 816                 ret_val = -E1000_ERR_CONFIG;
 817                 goto out;
 818         }
 819
 820 out:
 821         if (ret_val)
 822                 mutex_unlock(&swflag_mutex);
 823
 824         return ret_val;
 825 }
 826
 827 /**
 828  *  e1000_release_swflag_ich8lan - Release software control flag
 829  *  @hw: pointer to the HW structure
 830  *
 831  *  Releases the software control flag for performing PHY and select
 832  *  MAC CSR accesses.
 833  **/
 834 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 835 {
 836         u32 extcnf_ctrl;
 837
 838         extcnf_ctrl = er32(EXTCNF_CTRL);
 839         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 840         ew32(EXTCNF_CTRL, extcnf_ctrl);
 841
 842         mutex_unlock(&swflag_mutex);
 843 }
 844
 845 /**
 846  *  e1000_check_mng_mode_ich8lan - Checks management mode
 847  *  @hw: pointer to the HW structure
 848  *
 849  *  This checks if the adapter has any manageability enabled.
 850  *  This is a function pointer entry point only called by read/write
 851  *  routines for the PHY and NVM parts.
 852  **/
 853 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
 854 {
 855         u32 fwsm;
 856
 857         fwsm = er32(FWSM);
 858         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 859                ((fwsm & E1000_FWSM_MODE_MASK) ==
 860                 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 861 }
 862
 863 /**
 864  *  e1000_check_mng_mode_pchlan - Checks management mode
 865  *  @hw: pointer to the HW structure
 866  *
 867  *  This checks if the adapter has iAMT enabled.
 868  *  This is a function pointer entry point only called by read/write
 869  *  routines for the PHY and NVM parts.
 870  **/
 871 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
 872 {
 873         u32 fwsm;
 874
 875         fwsm = er32(FWSM);
 876         return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
 877                (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
 878 }
 879
 880 /**
 881  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 882  *  @hw: pointer to the HW structure
 883  *
 884  *  Checks if firmware is blocking the reset of the PHY.
 885  *  This is a function pointer entry point only called by
 886  *  reset routines.
 887  **/
 888 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 889 {
 890         u32 fwsm;
 891
 892         fwsm = er32(FWSM);
 893
 894         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 895 }
 896
 897 /**
 898  *  e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
 899  *  @hw:   pointer to the HW structure
 900  *
 901  *  SW should configure the LCD from the NVM extended configuration region
 902  *  as a workaround for certain parts.
 903  **/
 904 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
 905 {
 906         struct e1000_adapter *adapter = hw->adapter;
 907         struct e1000_phy_info *phy = &hw->phy;
 908         u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
 909         s32 ret_val = 0;
 910         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 911
 912         /*
 913          * Initialize the PHY from the NVM on ICH platforms.  This
 914          * is needed due to an issue where the NVM configuration is
 915          * not properly autoloaded after power transitions.
 916          * Therefore, after each PHY reset, we will load the
 917          * configuration data out of the NVM manually.
 918          */
 919         switch (hw->mac.type) {
 920         case e1000_ich8lan:
 921                 if (phy->type != e1000_phy_igp_3)
 922                         return ret_val;
 923
 924                 if (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) {
 925                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 926                         break;
 927                 }
 928                 /* Fall-thru */
 929         case e1000_pchlan:
 930         case e1000_pch2lan:
 931                 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 932                 break;
 933         default:
 934                 return ret_val;
 935         }
 936
 937         ret_val = hw->phy.ops.acquire(hw);
 938         if (ret_val)
 939                 return ret_val;
 940
 941         data = er32(FEXTNVM);
 942         if (!(data & sw_cfg_mask))
 943                 goto out;
 944
 945         /*
 946          * Make sure HW does not configure LCD from PHY
 947          * extended configuration before SW configuration
 948          */
 949         data = er32(EXTCNF_CTRL);
 950         if (!(hw->mac.type == e1000_pch2lan)) {
 951                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 952                         goto out;
 953         }
 954
 955         cnf_size = er32(EXTCNF_SIZE);
 956         cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 957         cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 958         if (!cnf_size)
 959                 goto out;
 960
 961         cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 962         cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 963
 964         if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
 965             ((hw->mac.type == e1000_pchlan) ||
 966              (hw->mac.type == e1000_pch2lan))) {
 967                 /*
 968                  * HW configures the SMBus address and LEDs when the
 969                  * OEM and LCD Write Enable bits are set in the NVM.
 970                  * When both NVM bits are cleared, SW will configure
 971                  * them instead.
 972                  */
 973                 data = er32(STRAP);
 974                 data &= E1000_STRAP_SMBUS_ADDRESS_MASK;
 975                 reg_data = data >> E1000_STRAP_SMBUS_ADDRESS_SHIFT;
 976                 reg_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
 977                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR,
 978                                                         reg_data);
 979                 if (ret_val)
 980                         goto out;
 981
 982                 data = er32(LEDCTL);
 983                 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
 984                                                         (u16)data);
 985                 if (ret_val)
 986                         goto out;
 987         }
 988
 989         /* Configure LCD from extended configuration region. */
 990
 991         /* cnf_base_addr is in DWORD */
 992         word_addr = (u16)(cnf_base_addr << 1);
 993
 994         for (i = 0; i < cnf_size; i++) {
 995                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
 996                                          &reg_data);
 997                 if (ret_val)
 998                         goto out;
 999
1000                 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1001                                          1, &reg_addr);
1002                 if (ret_val)
1003                         goto out;
1004
1005                 /* Save off the PHY page for future writes. */
1006                 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1007                         phy_page = reg_data;
1008                         continue;
1009                 }
1010
1011                 reg_addr &= PHY_REG_MASK;
1012                 reg_addr |= phy_page;
1013
1014                 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1015                                                     reg_data);
1016                 if (ret_val)
1017                         goto out;
1018         }
1019
1020 out:
1021         hw->phy.ops.release(hw);
1022         return ret_val;
1023 }
1024
1025 /**
1026  *  e1000_k1_gig_workaround_hv - K1 Si workaround
1027  *  @hw:   pointer to the HW structure
1028  *  @link: link up bool flag
1029  *
1030  *  If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1031  *  from a lower speed.  This workaround disables K1 whenever link is at 1Gig
1032  *  If link is down, the function will restore the default K1 setting located
1033  *  in the NVM.
1034  **/
1035 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1036 {
1037         s32 ret_val = 0;
1038         u16 status_reg = 0;
1039         bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1040
1041         if (hw->mac.type != e1000_pchlan)
1042                 goto out;
1043
1044         /* Wrap the whole flow with the sw flag */
1045         ret_val = hw->phy.ops.acquire(hw);
1046         if (ret_val)
1047                 goto out;
1048
1049         /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1050         if (link) {
1051                 if (hw->phy.type == e1000_phy_82578) {
1052                         ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1053                                                                   &status_reg);
1054                         if (ret_val)
1055                                 goto release;
1056
1057                         status_reg &= BM_CS_STATUS_LINK_UP |
1058                                       BM_CS_STATUS_RESOLVED |
1059                                       BM_CS_STATUS_SPEED_MASK;
1060
1061                         if (status_reg == (BM_CS_STATUS_LINK_UP |
1062                                            BM_CS_STATUS_RESOLVED |
1063                                            BM_CS_STATUS_SPEED_1000))
1064                                 k1_enable = false;
1065                 }
1066
1067                 if (hw->phy.type == e1000_phy_82577) {
1068                         ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1069                                                                   &status_reg);
1070                         if (ret_val)
1071                                 goto release;
1072
1073                         status_reg &= HV_M_STATUS_LINK_UP |
1074                                       HV_M_STATUS_AUTONEG_COMPLETE |
1075                                       HV_M_STATUS_SPEED_MASK;
1076
1077                         if (status_reg == (HV_M_STATUS_LINK_UP |
1078                                            HV_M_STATUS_AUTONEG_COMPLETE |
1079                                            HV_M_STATUS_SPEED_1000))
1080                                 k1_enable = false;
1081                 }
1082
1083                 /* Link stall fix for link up */
1084                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1085                                                            0x0100);
1086                 if (ret_val)
1087                         goto release;
1088
1089         } else {
1090                 /* Link stall fix for link down */
1091                 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1092                                                            0x4100);
1093                 if (ret_val)
1094                         goto release;
1095         }
1096
1097         ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1098
1099 release:
1100         hw->phy.ops.release(hw);
1101 out:
1102         return ret_val;
1103 }
1104
1105 /**
1106  *  e1000_configure_k1_ich8lan - Configure K1 power state
1107  *  @hw: pointer to the HW structure
1108  *  @enable: K1 state to configure
1109  *
1110  *  Configure the K1 power state based on the provided parameter.
1111  *  Assumes semaphore already acquired.
1112  *
1113  *  Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1114  **/
1115 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1116 {
1117         s32 ret_val = 0;
1118         u32 ctrl_reg = 0;
1119         u32 ctrl_ext = 0;
1120         u32 reg = 0;
1121         u16 kmrn_reg = 0;
1122
1123         ret_val = e1000e_read_kmrn_reg_locked(hw,
1124                                              E1000_KMRNCTRLSTA_K1_CONFIG,
1125                                              &kmrn_reg);
1126         if (ret_val)
1127                 goto out;
1128
1129         if (k1_enable)
1130                 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1131         else
1132                 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1133
1134         ret_val = e1000e_write_kmrn_reg_locked(hw,
1135                                               E1000_KMRNCTRLSTA_K1_CONFIG,
1136                                               kmrn_reg);
1137         if (ret_val)
1138                 goto out;
1139
1140         udelay(20);
1141         ctrl_ext = er32(CTRL_EXT);
1142         ctrl_reg = er32(CTRL);
1143
1144         reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1145         reg |= E1000_CTRL_FRCSPD;
1146         ew32(CTRL, reg);
1147
1148         ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1149         udelay(20);
1150         ew32(CTRL, ctrl_reg);
1151         ew32(CTRL_EXT, ctrl_ext);
1152         udelay(20);
1153
1154 out:
1155         return ret_val;
1156 }
1157
1158 /**
1159  *  e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1160  *  @hw:       pointer to the HW structure
1161  *  @d0_state: boolean if entering d0 or d3 device state
1162  *
1163  *  SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1164  *  collectively called OEM bits.  The OEM Write Enable bit and SW Config bit
1165  *  in NVM determines whether HW should configure LPLU and Gbe Disable.
1166  **/
1167 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1168 {
1169         s32 ret_val = 0;
1170         u32 mac_reg;
1171         u16 oem_reg;
1172
1173         if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1174                 return ret_val;
1175
1176         ret_val = hw->phy.ops.acquire(hw);
1177         if (ret_val)
1178                 return ret_val;
1179
1180         if (!(hw->mac.type == e1000_pch2lan)) {
1181                 mac_reg = er32(EXTCNF_CTRL);
1182                 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1183                         goto out;
1184         }
1185
1186         mac_reg = er32(FEXTNVM);
1187         if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1188                 goto out;
1189
1190         mac_reg = er32(PHY_CTRL);
1191
1192         ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1193         if (ret_val)
1194                 goto out;
1195
1196         oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1197
1198         if (d0_state) {
1199                 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1200                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1201
1202                 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1203                         oem_reg |= HV_OEM_BITS_LPLU;
1204         } else {
1205                 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1206                         oem_reg |= HV_OEM_BITS_GBE_DIS;
1207
1208                 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1209                         oem_reg |= HV_OEM_BITS_LPLU;
1210         }
1211         /* Restart auto-neg to activate the bits */
1212         if (!e1000_check_reset_block(hw))
1213                 oem_reg |= HV_OEM_BITS_RESTART_AN;
1214         ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1215
1216 out:
1217         hw->phy.ops.release(hw);
1218
1219         return ret_val;
1220 }
1221
1222
1223 /**
1224  *  e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1225  *  @hw:   pointer to the HW structure
1226  **/
1227 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1228 {
1229         s32 ret_val;
1230         u16 data;
1231
1232         ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1233         if (ret_val)
1234                 return ret_val;
1235
1236         data |= HV_KMRN_MDIO_SLOW;
1237
1238         ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1239
1240         return ret_val;
1241 }
1242
1243 /**
1244  *  e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1245  *  done after every PHY reset.
1246  **/
1247 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1248 {
1249         s32 ret_val = 0;
1250         u16 phy_data;
1251
1252         if (hw->mac.type != e1000_pchlan)
1253                 return ret_val;
1254
1255         /* Set MDIO slow mode before any other MDIO access */
1256         if (hw->phy.type == e1000_phy_82577) {
1257                 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1258                 if (ret_val)
1259                         goto out;
1260         }
1261
1262         if (((hw->phy.type == e1000_phy_82577) &&
1263              ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1264             ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1265                 /* Disable generation of early preamble */
1266                 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1267                 if (ret_val)
1268                         return ret_val;
1269
1270                 /* Preamble tuning for SSC */
1271                 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1272                 if (ret_val)
1273                         return ret_val;
1274         }
1275
1276         if (hw->phy.type == e1000_phy_82578) {
1277                 /*
1278                  * Return registers to default by doing a soft reset then
1279                  * writing 0x3140 to the control register.
1280                  */
1281                 if (hw->phy.revision < 2) {
1282                         e1000e_phy_sw_reset(hw);
1283                         ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1284                 }
1285         }
1286
1287         /* Select page 0 */
1288         ret_val = hw->phy.ops.acquire(hw);
1289         if (ret_val)
1290                 return ret_val;
1291
1292         hw->phy.addr = 1;
1293         ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1294         hw->phy.ops.release(hw);
1295         if (ret_val)
1296                 goto out;
1297
1298         /*
1299          * Configure the K1 Si workaround during phy reset assuming there is
1300          * link so that it disables K1 if link is in 1Gbps.
1301          */
1302         ret_val = e1000_k1_gig_workaround_hv(hw, true);
1303         if (ret_val)
1304                 goto out;
1305
1306         /* Workaround for link disconnects on a busy hub in half duplex */
1307         ret_val = hw->phy.ops.acquire(hw);
1308         if (ret_val)
1309                 goto out;
1310         ret_val = hw->phy.ops.read_reg_locked(hw,
1311                                               PHY_REG(BM_PORT_CTRL_PAGE, 17),
1312                                               &phy_data);
1313         if (ret_val)
1314                 goto release;
1315         ret_val = hw->phy.ops.write_reg_locked(hw,
1316                                                PHY_REG(BM_PORT_CTRL_PAGE, 17),
1317                                                phy_data & 0x00FF);
1318 release:
1319         hw->phy.ops.release(hw);
1320 out:
1321         return ret_val;
1322 }
1323
1324 /**
1325  *  e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1326  *  @hw:   pointer to the HW structure
1327  **/
1328 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1329 {
1330         u32 mac_reg;
1331         u16 i;
1332
1333         /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1334         for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1335                 mac_reg = er32(RAL(i));
1336                 e1e_wphy(hw, BM_RAR_L(i), (u16)(mac_reg & 0xFFFF));
1337                 e1e_wphy(hw, BM_RAR_M(i), (u16)((mac_reg >> 16) & 0xFFFF));
1338                 mac_reg = er32(RAH(i));
1339                 e1e_wphy(hw, BM_RAR_H(i), (u16)(mac_reg & 0xFFFF));
1340                 e1e_wphy(hw, BM_RAR_CTRL(i), (u16)((mac_reg >> 16) & 0x8000));
1341         }
1342 }
1343
1344 static u32 e1000_calc_rx_da_crc(u8 mac[])
1345 {
1346         u32 poly = 0xEDB88320;  /* Polynomial for 802.3 CRC calculation */
1347         u32 i, j, mask, crc;
1348
1349         crc = 0xffffffff;
1350         for (i = 0; i < 6; i++) {
1351                 crc = crc ^ mac[i];
1352                 for (j = 8; j > 0; j--) {
1353                         mask = (crc & 1) * (-1);
1354                         crc = (crc >> 1) ^ (poly & mask);
1355                 }
1356         }
1357         return ~crc;
1358 }
1359
1360 /**
1361  *  e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1362  *  with 82579 PHY
1363  *  @hw: pointer to the HW structure
1364  *  @enable: flag to enable/disable workaround when enabling/disabling jumbos
1365  **/
1366 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1367 {
1368         s32 ret_val = 0;
1369         u16 phy_reg, data;
1370         u32 mac_reg;
1371         u16 i;
1372
1373         if (hw->mac.type != e1000_pch2lan)
1374                 goto out;
1375
1376         /* disable Rx path while enabling/disabling workaround */
1377         e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1378         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1379         if (ret_val)
1380                 goto out;
1381
1382         if (enable) {
1383                 /*
1384                  * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1385                  * SHRAL/H) and initial CRC values to the MAC
1386                  */
1387                 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1388                         u8 mac_addr[ETH_ALEN] = {0};
1389                         u32 addr_high, addr_low;
1390
1391                         addr_high = er32(RAH(i));
1392                         if (!(addr_high & E1000_RAH_AV))
1393                                 continue;
1394                         addr_low = er32(RAL(i));
1395                         mac_addr[0] = (addr_low & 0xFF);
1396                         mac_addr[1] = ((addr_low >> 8) & 0xFF);
1397                         mac_addr[2] = ((addr_low >> 16) & 0xFF);
1398                         mac_addr[3] = ((addr_low >> 24) & 0xFF);
1399                         mac_addr[4] = (addr_high & 0xFF);
1400                         mac_addr[5] = ((addr_high >> 8) & 0xFF);
1401
1402                         ew32(PCH_RAICC(i),
1403                                         e1000_calc_rx_da_crc(mac_addr));
1404                 }
1405
1406                 /* Write Rx addresses to the PHY */
1407                 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1408
1409                 /* Enable jumbo frame workaround in the MAC */
1410                 mac_reg = er32(FFLT_DBG);
1411                 mac_reg &= ~(1 << 14);
1412                 mac_reg |= (7 << 15);
1413                 ew32(FFLT_DBG, mac_reg);
1414
1415                 mac_reg = er32(RCTL);
1416                 mac_reg |= E1000_RCTL_SECRC;
1417                 ew32(RCTL, mac_reg);
1418
1419                 ret_val = e1000e_read_kmrn_reg(hw,
1420                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1421                                                 &data);
1422                 if (ret_val)
1423                         goto out;
1424                 ret_val = e1000e_write_kmrn_reg(hw,
1425                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1426                                                 data | (1 << 0));
1427                 if (ret_val)
1428                         goto out;
1429                 ret_val = e1000e_read_kmrn_reg(hw,
1430                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1431                                                 &data);
1432                 if (ret_val)
1433                         goto out;
1434                 data &= ~(0xF << 8);
1435                 data |= (0xB << 8);
1436                 ret_val = e1000e_write_kmrn_reg(hw,
1437                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1438                                                 data);
1439                 if (ret_val)
1440                         goto out;
1441
1442                 /* Enable jumbo frame workaround in the PHY */
1443                 e1e_rphy(hw, PHY_REG(769, 20), &data);
1444                 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1445                 if (ret_val)
1446                         goto out;
1447                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1448                 data &= ~(0x7F << 5);
1449                 data |= (0x37 << 5);
1450                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1451                 if (ret_val)
1452                         goto out;
1453                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1454                 data &= ~(1 << 13);
1455                 data |= (1 << 12);
1456                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1457                 if (ret_val)
1458                         goto out;
1459                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1460                 data &= ~(0x3FF << 2);
1461                 data |= (0x1A << 2);
1462                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1463                 if (ret_val)
1464                         goto out;
1465                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1466                 if (ret_val)
1467                         goto out;
1468                 e1e_rphy(hw, HV_PM_CTRL, &data);
1469                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1470                 if (ret_val)
1471                         goto out;
1472         } else {
1473                 /* Write MAC register values back to h/w defaults */
1474                 mac_reg = er32(FFLT_DBG);
1475                 mac_reg &= ~(0xF << 14);
1476                 ew32(FFLT_DBG, mac_reg);
1477
1478                 mac_reg = er32(RCTL);
1479                 mac_reg &= ~E1000_RCTL_SECRC;
1480                 ew32(FFLT_DBG, mac_reg);
1481
1482                 ret_val = e1000e_read_kmrn_reg(hw,
1483                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1484                                                 &data);
1485                 if (ret_val)
1486                         goto out;
1487                 ret_val = e1000e_write_kmrn_reg(hw,
1488                                                 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1489                                                 data & ~(1 << 0));
1490                 if (ret_val)
1491                         goto out;
1492                 ret_val = e1000e_read_kmrn_reg(hw,
1493                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1494                                                 &data);
1495                 if (ret_val)
1496                         goto out;
1497                 data &= ~(0xF << 8);
1498                 data |= (0xB << 8);
1499                 ret_val = e1000e_write_kmrn_reg(hw,
1500                                                 E1000_KMRNCTRLSTA_HD_CTRL,
1501                                                 data);
1502                 if (ret_val)
1503                         goto out;
1504
1505                 /* Write PHY register values back to h/w defaults */
1506                 e1e_rphy(hw, PHY_REG(769, 20), &data);
1507                 ret_val = e1e_wphy(hw, PHY_REG(769, 20), data & ~(1 << 14));
1508                 if (ret_val)
1509                         goto out;
1510                 e1e_rphy(hw, PHY_REG(769, 23), &data);
1511                 data &= ~(0x7F << 5);
1512                 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1513                 if (ret_val)
1514                         goto out;
1515                 e1e_rphy(hw, PHY_REG(769, 16), &data);
1516                 data &= ~(1 << 12);
1517                 data |= (1 << 13);
1518                 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1519                 if (ret_val)
1520                         goto out;
1521                 e1e_rphy(hw, PHY_REG(776, 20), &data);
1522                 data &= ~(0x3FF << 2);
1523                 data |= (0x8 << 2);
1524                 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1525                 if (ret_val)
1526                         goto out;
1527                 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1528                 if (ret_val)
1529                         goto out;
1530                 e1e_rphy(hw, HV_PM_CTRL, &data);
1531                 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1532                 if (ret_val)
1533                         goto out;
1534         }
1535
1536         /* re-enable Rx path after enabling/disabling workaround */
1537         ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1538
1539 out:
1540         return ret_val;
1541 }
1542
1543 /**
1544  *  e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1545  *  done after every PHY reset.
1546  **/
1547 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1548 {
1549         s32 ret_val = 0;
1550
1551         if (hw->mac.type != e1000_pch2lan)
1552                 goto out;
1553
1554         /* Set MDIO slow mode before any other MDIO access */
1555         ret_val = e1000_set_mdio_slow_mode_hv(hw);
1556
1557 out:
1558         return ret_val;
1559 }
1560
1561 /**
1562  *  e1000_lan_init_done_ich8lan - Check for PHY config completion
1563  *  @hw: pointer to the HW structure
1564  *
1565  *  Check the appropriate indication the MAC has finished configuring the
1566  *  PHY after a software reset.
1567  **/
1568 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1569 {
1570         u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1571
1572         /* Wait for basic configuration completes before proceeding */
1573         do {
1574                 data = er32(STATUS);
1575                 data &= E1000_STATUS_LAN_INIT_DONE;
1576                 udelay(100);
1577         } while ((!data) && --loop);
1578
1579         /*
1580          * If basic configuration is incomplete before the above loop
1581          * count reaches 0, loading the configuration from NVM will
1582          * leave the PHY in a bad state possibly resulting in no link.
1583          */
1584         if (loop == 0)
1585                 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1586
1587         /* Clear the Init Done bit for the next init event */
1588         data = er32(STATUS);
1589         data &= ~E1000_STATUS_LAN_INIT_DONE;
1590         ew32(STATUS, data);
1591 }
1592
1593 /**
1594  *  e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1595  *  @hw: pointer to the HW structure
1596  **/
1597 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1598 {
1599         s32 ret_val = 0;
1600         u16 reg;
1601
1602         if (e1000_check_reset_block(hw))
1603                 goto out;
1604
1605         /* Perform any necessary post-reset workarounds */
1606         switch (hw->mac.type) {
1607         case e1000_pchlan:
1608                 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1609                 if (ret_val)
1610                         goto out;
1611                 break;
1612         case e1000_pch2lan:
1613                 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1614                 if (ret_val)
1615                         goto out;
1616                 break;
1617         default:
1618                 break;
1619         }
1620
1621         /* Dummy read to clear the phy wakeup bit after lcd reset */
1622         if (hw->mac.type >= e1000_pchlan)
1623                 e1e_rphy(hw, BM_WUC, &reg);
1624
1625         /* Configure the LCD with the extended configuration region in NVM */
1626         ret_val = e1000_sw_lcd_config_ich8lan(hw);
1627         if (ret_val)
1628                 goto out;
1629
1630         /* Configure the LCD with the OEM bits in NVM */
1631         ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1632
1633 out:
1634         return ret_val;
1635 }
1636
1637 /**
1638  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1639  *  @hw: pointer to the HW structure
1640  *
1641  *  Resets the PHY
1642  *  This is a function pointer entry point called by drivers
1643  *  or other shared routines.
1644  **/
1645 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1646 {
1647         s32 ret_val = 0;
1648
1649         ret_val = e1000e_phy_hw_reset_generic(hw);
1650         if (ret_val)
1651                 goto out;
1652
1653         ret_val = e1000_post_phy_reset_ich8lan(hw);
1654
1655 out:
1656         return ret_val;
1657 }
1658
1659 /**
1660  *  e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1661  *  @hw: pointer to the HW structure
1662  *  @active: true to enable LPLU, false to disable
1663  *
1664  *  Sets the LPLU state according to the active flag.  For PCH, if OEM write
1665  *  bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1666  *  the phy speed. This function will manually set the LPLU bit and restart
1667  *  auto-neg as hw would do. D3 and D0 LPLU will call the same function
1668  *  since it configures the same bit.
1669  **/
1670 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1671 {
1672         s32 ret_val = 0;
1673         u16 oem_reg;
1674
1675         ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1676         if (ret_val)
1677                 goto out;
1678
1679         if (active)
1680                 oem_reg |= HV_OEM_BITS_LPLU;
1681         else
1682                 oem_reg &= ~HV_OEM_BITS_LPLU;
1683
1684         oem_reg |= HV_OEM_BITS_RESTART_AN;
1685         ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1686
1687 out:
1688         return ret_val;
1689 }
1690
1691 /**
1692  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1693  *  @hw: pointer to the HW structure
1694  *  @active: true to enable LPLU, false to disable
1695  *
1696  *  Sets the LPLU D0 state according to the active flag.  When
1697  *  activating LPLU this function also disables smart speed
1698  *  and vice versa.  LPLU will not be activated unless the
1699  *  device autonegotiation advertisement meets standards of
1700  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1701  *  This is a function pointer entry point only called by
1702  *  PHY setup routines.
1703  **/
1704 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1705 {
1706         struct e1000_phy_info *phy = &hw->phy;
1707         u32 phy_ctrl;
1708         s32 ret_val = 0;
1709         u16 data;
1710
1711         if (phy->type == e1000_phy_ife)
1712                 return ret_val;
1713
1714         phy_ctrl = er32(PHY_CTRL);
1715
1716         if (active) {
1717                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1718                 ew32(PHY_CTRL, phy_ctrl);
1719
1720                 if (phy->type != e1000_phy_igp_3)
1721                         return 0;
1722
1723                 /*
1724                  * Call gig speed drop workaround on LPLU before accessing
1725                  * any PHY registers
1726                  */
1727                 if (hw->mac.type == e1000_ich8lan)
1728                         e1000e_gig_downshift_workaround_ich8lan(hw);
1729
1730                 /* When LPLU is enabled, we should disable SmartSpeed */
1731                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1732                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1733                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1734                 if (ret_val)
1735                         return ret_val;
1736         } else {
1737                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1738                 ew32(PHY_CTRL, phy_ctrl);
1739
1740                 if (phy->type != e1000_phy_igp_3)
1741                         return 0;
1742
1743                 /*
1744                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1745                  * during Dx states where the power conservation is most
1746                  * important.  During driver activity we should enable
1747                  * SmartSpeed, so performance is maintained.
1748                  */
1749                 if (phy->smart_speed == e1000_smart_speed_on) {
1750                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1751                                            &data);
1752                         if (ret_val)
1753                                 return ret_val;
1754
1755                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1756                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1757                                            data);
1758                         if (ret_val)
1759                                 return ret_val;
1760                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1761                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1762                                            &data);
1763                         if (ret_val)
1764                                 return ret_val;
1765
1766                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1767                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1768                                            data);
1769                         if (ret_val)
1770                                 return ret_val;
1771                 }
1772         }
1773
1774         return 0;
1775 }
1776
1777 /**
1778  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1779  *  @hw: pointer to the HW structure
1780  *  @active: true to enable LPLU, false to disable
1781  *
1782  *  Sets the LPLU D3 state according to the active flag.  When
1783  *  activating LPLU this function also disables smart speed
1784  *  and vice versa.  LPLU will not be activated unless the
1785  *  device autonegotiation advertisement meets standards of
1786  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
1787  *  This is a function pointer entry point only called by
1788  *  PHY setup routines.
1789  **/
1790 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1791 {
1792         struct e1000_phy_info *phy = &hw->phy;
1793         u32 phy_ctrl;
1794         s32 ret_val;
1795         u16 data;
1796
1797         phy_ctrl = er32(PHY_CTRL);
1798
1799         if (!active) {
1800                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1801                 ew32(PHY_CTRL, phy_ctrl);
1802
1803                 if (phy->type != e1000_phy_igp_3)
1804                         return 0;
1805
1806                 /*
1807                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
1808                  * during Dx states where the power conservation is most
1809                  * important.  During driver activity we should enable
1810                  * SmartSpeed, so performance is maintained.
1811                  */
1812                 if (phy->smart_speed == e1000_smart_speed_on) {
1813                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1814                                            &data);
1815                         if (ret_val)
1816                                 return ret_val;
1817
1818                         data |= IGP01E1000_PSCFR_SMART_SPEED;
1819                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1820                                            data);
1821                         if (ret_val)
1822                                 return ret_val;
1823                 } else if (phy->smart_speed == e1000_smart_speed_off) {
1824                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1825                                            &data);
1826                         if (ret_val)
1827                                 return ret_val;
1828
1829                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1830                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1831                                            data);
1832                         if (ret_val)
1833                                 return ret_val;
1834                 }
1835         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1836                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1837                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1838                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
1839                 ew32(PHY_CTRL, phy_ctrl);
1840
1841                 if (phy->type != e1000_phy_igp_3)
1842                         return 0;
1843
1844                 /*
1845                  * Call gig speed drop workaround on LPLU before accessing
1846                  * any PHY registers
1847                  */
1848                 if (hw->mac.type == e1000_ich8lan)
1849                         e1000e_gig_downshift_workaround_ich8lan(hw);
1850
1851                 /* When LPLU is enabled, we should disable SmartSpeed */
1852                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1853                 if (ret_val)
1854                         return ret_val;
1855
1856                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1857                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1858         }
1859
1860         return 0;
1861 }
1862
1863 /**
1864  *  e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
1865  *  @hw: pointer to the HW structure
1866  *  @bank:  pointer to the variable that returns the active bank
1867  *
1868  *  Reads signature byte from the NVM using the flash access registers.
1869  *  Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
1870  **/
1871 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
1872 {
1873         u32 eecd;
1874         struct e1000_nvm_info *nvm = &hw->nvm;
1875         u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
1876         u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
1877         u8 sig_byte = 0;
1878         s32 ret_val = 0;
1879
1880         switch (hw->mac.type) {
1881         case e1000_ich8lan:
1882         case e1000_ich9lan:
1883                 eecd = er32(EECD);
1884                 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
1885                     E1000_EECD_SEC1VAL_VALID_MASK) {
1886                         if (eecd & E1000_EECD_SEC1VAL)
1887                                 *bank = 1;
1888                         else
1889                                 *bank = 0;
1890
1891                         return 0;
1892                 }
1893                 e_dbg("Unable to determine valid NVM bank via EEC - "
1894                        "reading flash signature\n");
1895                 /* fall-thru */
1896         default:
1897                 /* set bank to 0 in case flash read fails */
1898                 *bank = 0;
1899
1900                 /* Check bank 0 */
1901                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
1902                                                         &sig_byte);
1903                 if (ret_val)
1904                         return ret_val;
1905                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1906                     E1000_ICH_NVM_SIG_VALUE) {
1907                         *bank = 0;
1908                         return 0;
1909                 }
1910
1911                 /* Check bank 1 */
1912                 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
1913                                                         bank1_offset,
1914                                                         &sig_byte);
1915                 if (ret_val)
1916                         return ret_val;
1917                 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
1918                     E1000_ICH_NVM_SIG_VALUE) {
1919                         *bank = 1;
1920                         return 0;
1921                 }
1922
1923                 e_dbg("ERROR: No valid NVM bank present\n");
1924                 return -E1000_ERR_NVM;
1925         }
1926
1927         return 0;
1928 }
1929
1930 /**
1931  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
1932  *  @hw: pointer to the HW structure
1933  *  @offset: The offset (in bytes) of the word(s) to read.
1934  *  @words: Size of data to read in words
1935  *  @data: Pointer to the word(s) to read at offset.
1936  *
1937  *  Reads a word(s) from the NVM using the flash access registers.
1938  **/
1939 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1940                                   u16 *data)
1941 {
1942         struct e1000_nvm_info *nvm = &hw->nvm;
1943         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1944         u32 act_offset;
1945         s32 ret_val = 0;
1946         u32 bank = 0;
1947         u16 i, word;
1948
1949         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1950             (words == 0)) {
1951                 e_dbg("nvm parameter(s) out of bounds\n");
1952                 ret_val = -E1000_ERR_NVM;
1953                 goto out;
1954         }
1955
1956         nvm->ops.acquire(hw);
1957
1958         ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
1959         if (ret_val) {
1960                 e_dbg("Could not detect valid bank, assuming bank 0\n");
1961                 bank = 0;
1962         }
1963
1964         act_offset = (bank) ? nvm->flash_bank_size : 0;
1965         act_offset += offset;
1966
1967         ret_val = 0;
1968         for (i = 0; i < words; i++) {
1969                 if ((dev_spec->shadow_ram) &&
1970                     (dev_spec->shadow_ram[offset+i].modified)) {
1971                         data[i] = dev_spec->shadow_ram[offset+i].value;
1972                 } else {
1973                         ret_val = e1000_read_flash_word_ich8lan(hw,
1974                                                                 act_offset + i,
1975                                                                 &word);
1976                         if (ret_val)
1977                                 break;
1978                         data[i] = word;
1979                 }
1980         }
1981
1982         nvm->ops.release(hw);
1983
1984 out:
1985         if (ret_val)
1986                 e_dbg("NVM read error: %d\n", ret_val);
1987
1988         return ret_val;
1989 }
1990
1991 /**
1992  *  e1000_flash_cycle_init_ich8lan - Initialize flash
1993  *  @hw: pointer to the HW structure
1994  *
1995  *  This function does initial flash setup so that a new read/write/erase cycle
1996  *  can be started.
1997  **/
1998 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
1999 {
2000         union ich8_hws_flash_status hsfsts;
2001         s32 ret_val = -E1000_ERR_NVM;
2002         s32 i = 0;
2003
2004         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2005
2006         /* Check if the flash descriptor is valid */
2007         if (hsfsts.hsf_status.fldesvalid == 0) {
2008                 e_dbg("Flash descriptor invalid.  "
2009                          "SW Sequencing must be used.\n");
2010                 return -E1000_ERR_NVM;
2011         }
2012
2013         /* Clear FCERR and DAEL in hw status by writing 1 */
2014         hsfsts.hsf_status.flcerr = 1;
2015         hsfsts.hsf_status.dael = 1;
2016
2017         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2018
2019         /*
2020          * Either we should have a hardware SPI cycle in progress
2021          * bit to check against, in order to start a new cycle or
2022          * FDONE bit should be changed in the hardware so that it
2023          * is 1 after hardware reset, which can then be used as an
2024          * indication whether a cycle is in progress or has been
2025          * completed.
2026          */
2027
2028         if (hsfsts.hsf_status.flcinprog == 0) {
2029                 /*
2030                  * There is no cycle running at present,
2031                  * so we can start a cycle.
2032                  * Begin by setting Flash Cycle Done.
2033                  */
2034                 hsfsts.hsf_status.flcdone = 1;
2035                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2036                 ret_val = 0;
2037         } else {
2038                 /*
2039                  * Otherwise poll for sometime so the current
2040                  * cycle has a chance to end before giving up.
2041                  */
2042                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2043                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2044                         if (hsfsts.hsf_status.flcinprog == 0) {
2045                                 ret_val = 0;
2046                                 break;
2047                         }
2048                         udelay(1);
2049                 }
2050                 if (ret_val == 0) {
2051                         /*
2052                          * Successful in waiting for previous cycle to timeout,
2053                          * now set the Flash Cycle Done.
2054                          */
2055                         hsfsts.hsf_status.flcdone = 1;
2056                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2057                 } else {
2058                         e_dbg("Flash controller busy, cannot get access\n");
2059                 }
2060         }
2061
2062         return ret_val;
2063 }
2064
2065 /**
2066  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2067  *  @hw: pointer to the HW structure
2068  *  @timeout: maximum time to wait for completion
2069  *
2070  *  This function starts a flash cycle and waits for its completion.
2071  **/
2072 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2073 {
2074         union ich8_hws_flash_ctrl hsflctl;
2075         union ich8_hws_flash_status hsfsts;
2076         s32 ret_val = -E1000_ERR_NVM;
2077         u32 i = 0;
2078
2079         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2080         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2081         hsflctl.hsf_ctrl.flcgo = 1;
2082         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2083
2084         /* wait till FDONE bit is set to 1 */
2085         do {
2086                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2087                 if (hsfsts.hsf_status.flcdone == 1)
2088                         break;
2089                 udelay(1);
2090         } while (i++ < timeout);
2091
2092         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2093                 return 0;
2094
2095         return ret_val;
2096 }
2097
2098 /**
2099  *  e1000_read_flash_word_ich8lan - Read word from flash
2100  *  @hw: pointer to the HW structure
2101  *  @offset: offset to data location
2102  *  @data: pointer to the location for storing the data
2103  *
2104  *  Reads the flash word at offset into data.  Offset is converted
2105  *  to bytes before read.
2106  **/
2107 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2108                                          u16 *data)
2109 {
2110         /* Must convert offset into bytes. */
2111         offset <<= 1;
2112
2113         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2114 }
2115
2116 /**
2117  *  e1000_read_flash_byte_ich8lan - Read byte from flash
2118  *  @hw: pointer to the HW structure
2119  *  @offset: The offset of the byte to read.
2120  *  @data: Pointer to a byte to store the value read.
2121  *
2122  *  Reads a single byte from the NVM using the flash access registers.
2123  **/
2124 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2125                                          u8 *data)
2126 {
2127         s32 ret_val;
2128         u16 word = 0;
2129
2130         ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2131         if (ret_val)
2132                 return ret_val;
2133
2134         *data = (u8)word;
2135
2136         return 0;
2137 }
2138
2139 /**
2140  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
2141  *  @hw: pointer to the HW structure
2142  *  @offset: The offset (in bytes) of the byte or word to read.
2143  *  @size: Size of data to read, 1=byte 2=word
2144  *  @data: Pointer to the word to store the value read.
2145  *
2146  *  Reads a byte or word from the NVM using the flash access registers.
2147  **/
2148 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2149                                          u8 size, u16 *data)
2150 {
2151         union ich8_hws_flash_status hsfsts;
2152         union ich8_hws_flash_ctrl hsflctl;
2153         u32 flash_linear_addr;
2154         u32 flash_data = 0;
2155         s32 ret_val = -E1000_ERR_NVM;
2156         u8 count = 0;
2157
2158         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2159                 return -E1000_ERR_NVM;
2160
2161         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2162                             hw->nvm.flash_base_addr;
2163
2164         do {
2165                 udelay(1);
2166                 /* Steps */
2167                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2168                 if (ret_val != 0)
2169                         break;
2170
2171                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2172                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2173                 hsflctl.hsf_ctrl.fldbcount = size - 1;
2174                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2175                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2176
2177                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2178
2179                 ret_val = e1000_flash_cycle_ich8lan(hw,
2180                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
2181
2182                 /*
2183                  * Check if FCERR is set to 1, if set to 1, clear it
2184                  * and try the whole sequence a few more times, else
2185                  * read in (shift in) the Flash Data0, the order is
2186                  * least significant byte first msb to lsb
2187                  */
2188                 if (ret_val == 0) {
2189                         flash_data = er32flash(ICH_FLASH_FDATA0);
2190                         if (size == 1) {
2191                                 *data = (u8)(flash_data & 0x000000FF);
2192                         } else if (size == 2) {
2193                                 *data = (u16)(flash_data & 0x0000FFFF);
2194                         }
2195                         break;
2196                 } else {
2197                         /*
2198                          * If we've gotten here, then things are probably
2199                          * completely hosed, but if the error condition is
2200                          * detected, it won't hurt to give it another try...
2201                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2202                          */
2203                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2204                         if (hsfsts.hsf_status.flcerr == 1) {
2205                                 /* Repeat for some time before giving up. */
2206                                 continue;
2207                         } else if (hsfsts.hsf_status.flcdone == 0) {
2208                                 e_dbg("Timeout error - flash cycle "
2209                                          "did not complete.\n");
2210                                 break;
2211                         }
2212                 }
2213         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2214
2215         return ret_val;
2216 }
2217
2218 /**
2219  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
2220  *  @hw: pointer to the HW structure
2221  *  @offset: The offset (in bytes) of the word(s) to write.
2222  *  @words: Size of data to write in words
2223  *  @data: Pointer to the word(s) to write at offset.
2224  *
2225  *  Writes a byte or word to the NVM using the flash access registers.
2226  **/
2227 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2228                                    u16 *data)
2229 {
2230         struct e1000_nvm_info *nvm = &hw->nvm;
2231         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2232         u16 i;
2233
2234         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2235             (words == 0)) {
2236                 e_dbg("nvm parameter(s) out of bounds\n");
2237                 return -E1000_ERR_NVM;
2238         }
2239
2240         nvm->ops.acquire(hw);
2241
2242         for (i = 0; i < words; i++) {
2243                 dev_spec->shadow_ram[offset+i].modified = true;
2244                 dev_spec->shadow_ram[offset+i].value = data[i];
2245         }
2246
2247         nvm->ops.release(hw);
2248
2249         return 0;
2250 }
2251
2252 /**
2253  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2254  *  @hw: pointer to the HW structure
2255  *
2256  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
2257  *  which writes the checksum to the shadow ram.  The changes in the shadow
2258  *  ram are then committed to the EEPROM by processing each bank at a time
2259  *  checking for the modified bit and writing only the pending changes.
2260  *  After a successful commit, the shadow ram is cleared and is ready for
2261  *  future writes.
2262  **/
2263 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2264 {
2265         struct e1000_nvm_info *nvm = &hw->nvm;
2266         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2267         u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2268         s32 ret_val;
2269         u16 data;
2270
2271         ret_val = e1000e_update_nvm_checksum_generic(hw);
2272         if (ret_val)
2273                 goto out;
2274
2275         if (nvm->type != e1000_nvm_flash_sw)
2276                 goto out;
2277
2278         nvm->ops.acquire(hw);
2279
2280         /*
2281          * We're writing to the opposite bank so if we're on bank 1,
2282          * write to bank 0 etc.  We also need to erase the segment that
2283          * is going to be written
2284          */
2285         ret_val =  e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2286         if (ret_val) {
2287                 e_dbg("Could not detect valid bank, assuming bank 0\n");
2288                 bank = 0;
2289         }
2290
2291         if (bank == 0) {
2292                 new_bank_offset = nvm->flash_bank_size;
2293                 old_bank_offset = 0;
2294                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2295                 if (ret_val)
2296                         goto release;
2297         } else {
2298                 old_bank_offset = nvm->flash_bank_size;
2299                 new_bank_offset = 0;
2300                 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2301                 if (ret_val)
2302                         goto release;
2303         }
2304
2305         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2306                 /*
2307                  * Determine whether to write the value stored
2308                  * in the other NVM bank or a modified value stored
2309                  * in the shadow RAM
2310                  */
2311                 if (dev_spec->shadow_ram[i].modified) {
2312                         data = dev_spec->shadow_ram[i].value;
2313                 } else {
2314                         ret_val = e1000_read_flash_word_ich8lan(hw, i +
2315                                                                 old_bank_offset,
2316                                                                 &data);
2317                         if (ret_val)
2318                                 break;
2319                 }
2320
2321                 /*
2322                  * If the word is 0x13, then make sure the signature bits
2323                  * (15:14) are 11b until the commit has completed.
2324                  * This will allow us to write 10b which indicates the
2325                  * signature is valid.  We want to do this after the write
2326                  * has completed so that we don't mark the segment valid
2327                  * while the write is still in progress
2328                  */
2329                 if (i == E1000_ICH_NVM_SIG_WORD)
2330                         data |= E1000_ICH_NVM_SIG_MASK;
2331
2332                 /* Convert offset to bytes. */
2333                 act_offset = (i + new_bank_offset) << 1;
2334
2335                 udelay(100);
2336                 /* Write the bytes to the new bank. */
2337                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2338                                                                act_offset,
2339                                                                (u8)data);
2340                 if (ret_val)
2341                         break;
2342
2343                 udelay(100);
2344                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2345                                                           act_offset + 1,
2346                                                           (u8)(data >> 8));
2347                 if (ret_val)
2348                         break;
2349         }
2350
2351         /*
2352          * Don't bother writing the segment valid bits if sector
2353          * programming failed.
2354          */
2355         if (ret_val) {
2356                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2357                 e_dbg("Flash commit failed.\n");
2358                 goto release;
2359         }
2360
2361         /*
2362          * Finally validate the new segment by setting bit 15:14
2363          * to 10b in word 0x13 , this can be done without an
2364          * erase as well since these bits are 11 to start with
2365          * and we need to change bit 14 to 0b
2366          */
2367         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2368         ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2369         if (ret_val)
2370                 goto release;
2371
2372         data &= 0xBFFF;
2373         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2374                                                        act_offset * 2 + 1,
2375                                                        (u8)(data >> 8));
2376         if (ret_val)
2377                 goto release;
2378
2379         /*
2380          * And invalidate the previously valid segment by setting
2381          * its signature word (0x13) high_byte to 0b. This can be
2382          * done without an erase because flash erase sets all bits
2383          * to 1's. We can write 1's to 0's without an erase
2384          */
2385         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2386         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2387         if (ret_val)
2388                 goto release;
2389
2390         /* Great!  Everything worked, we can now clear the cached entries. */
2391         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2392                 dev_spec->shadow_ram[i].modified = false;
2393                 dev_spec->shadow_ram[i].value = 0xFFFF;
2394         }
2395
2396 release:
2397         nvm->ops.release(hw);
2398
2399         /*
2400          * Reload the EEPROM, or else modifications will not appear
2401          * until after the next adapter reset.
2402          */
2403         if (!ret_val) {
2404                 e1000e_reload_nvm(hw);
2405                 msleep(10);
2406         }
2407
2408 out:
2409         if (ret_val)
2410                 e_dbg("NVM update error: %d\n", ret_val);
2411
2412         return ret_val;
2413 }
2414
2415 /**
2416  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2417  *  @hw: pointer to the HW structure
2418  *
2419  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2420  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
2421  *  calculated, in which case we need to calculate the checksum and set bit 6.
2422  **/
2423 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2424 {
2425         s32 ret_val;
2426         u16 data;
2427
2428         /*
2429          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
2430          * needs to be fixed.  This bit is an indication that the NVM
2431          * was prepared by OEM software and did not calculate the
2432          * checksum...a likely scenario.
2433          */
2434         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2435         if (ret_val)
2436                 return ret_val;
2437
2438         if ((data & 0x40) == 0) {
2439                 data |= 0x40;
2440                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2441                 if (ret_val)
2442                         return ret_val;
2443                 ret_val = e1000e_update_nvm_checksum(hw);
2444                 if (ret_val)
2445                         return ret_val;
2446         }
2447
2448         return e1000e_validate_nvm_checksum_generic(hw);
2449 }
2450
2451 /**
2452  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2453  *  @hw: pointer to the HW structure
2454  *
2455  *  To prevent malicious write/erase of the NVM, set it to be read-only
2456  *  so that the hardware ignores all write/erase cycles of the NVM via
2457  *  the flash control registers.  The shadow-ram copy of the NVM will
2458  *  still be updated, however any updates to this copy will not stick
2459  *  across driver reloads.
2460  **/
2461 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2462 {
2463         struct e1000_nvm_info *nvm = &hw->nvm;
2464         union ich8_flash_protected_range pr0;
2465         union ich8_hws_flash_status hsfsts;
2466         u32 gfpreg;
2467
2468         nvm->ops.acquire(hw);
2469
2470         gfpreg = er32flash(ICH_FLASH_GFPREG);
2471
2472         /* Write-protect GbE Sector of NVM */
2473         pr0.regval = er32flash(ICH_FLASH_PR0);
2474         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2475         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2476         pr0.range.wpe = true;
2477         ew32flash(ICH_FLASH_PR0, pr0.regval);
2478
2479         /*
2480          * Lock down a subset of GbE Flash Control Registers, e.g.
2481          * PR0 to prevent the write-protection from being lifted.
2482          * Once FLOCKDN is set, the registers protected by it cannot
2483          * be written until FLOCKDN is cleared by a hardware reset.
2484          */
2485         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2486         hsfsts.hsf_status.flockdn = true;
2487         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2488
2489         nvm->ops.release(hw);
2490 }
2491
2492 /**
2493  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2494  *  @hw: pointer to the HW structure
2495  *  @offset: The offset (in bytes) of the byte/word to read.
2496  *  @size: Size of data to read, 1=byte 2=word
2497  *  @data: The byte(s) to write to the NVM.
2498  *
2499  *  Writes one/two bytes to the NVM using the flash access registers.
2500  **/
2501 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2502                                           u8 size, u16 data)
2503 {
2504         union ich8_hws_flash_status hsfsts;
2505         union ich8_hws_flash_ctrl hsflctl;
2506         u32 flash_linear_addr;
2507         u32 flash_data = 0;
2508         s32 ret_val;
2509         u8 count = 0;
2510
2511         if (size < 1 || size > 2 || data > size * 0xff ||
2512             offset > ICH_FLASH_LINEAR_ADDR_MASK)
2513                 return -E1000_ERR_NVM;
2514
2515         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2516                             hw->nvm.flash_base_addr;
2517
2518         do {
2519                 udelay(1);
2520                 /* Steps */
2521                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2522                 if (ret_val)
2523                         break;
2524
2525                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2526                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2527                 hsflctl.hsf_ctrl.fldbcount = size -1;
2528                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2529                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2530
2531                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2532
2533                 if (size == 1)
2534                         flash_data = (u32)data & 0x00FF;
2535                 else
2536                         flash_data = (u32)data;
2537
2538                 ew32flash(ICH_FLASH_FDATA0, flash_data);
2539
2540                 /*
2541                  * check if FCERR is set to 1 , if set to 1, clear it
2542                  * and try the whole sequence a few more times else done
2543                  */
2544                 ret_val = e1000_flash_cycle_ich8lan(hw,
2545                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2546                 if (!ret_val)
2547                         break;
2548
2549                 /*
2550                  * If we're here, then things are most likely
2551                  * completely hosed, but if the error condition
2552                  * is detected, it won't hurt to give it another
2553                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2554                  */
2555                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2556                 if (hsfsts.hsf_status.flcerr == 1)
2557                         /* Repeat for some time before giving up. */
2558                         continue;
2559                 if (hsfsts.hsf_status.flcdone == 0) {
2560                         e_dbg("Timeout error - flash cycle "
2561                                  "did not complete.");
2562                         break;
2563                 }
2564         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2565
2566         return ret_val;
2567 }
2568
2569 /**
2570  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2571  *  @hw: pointer to the HW structure
2572  *  @offset: The index of the byte to read.
2573  *  @data: The byte to write to the NVM.
2574  *
2575  *  Writes a single byte to the NVM using the flash access registers.
2576  **/
2577 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2578                                           u8 data)
2579 {
2580         u16 word = (u16)data;
2581
2582         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2583 }
2584
2585 /**
2586  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2587  *  @hw: pointer to the HW structure
2588  *  @offset: The offset of the byte to write.
2589  *  @byte: The byte to write to the NVM.
2590  *
2591  *  Writes a single byte to the NVM using the flash access registers.
2592  *  Goes through a retry algorithm before giving up.
2593  **/
2594 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2595                                                 u32 offset, u8 byte)
2596 {
2597         s32 ret_val;
2598         u16 program_retries;
2599
2600         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2601         if (!ret_val)
2602                 return ret_val;
2603
2604         for (program_retries = 0; program_retries < 100; program_retries++) {
2605                 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2606                 udelay(100);
2607                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2608                 if (!ret_val)
2609                         break;
2610         }
2611         if (program_retries == 100)
2612                 return -E1000_ERR_NVM;
2613
2614         return 0;
2615 }
2616
2617 /**
2618  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2619  *  @hw: pointer to the HW structure
2620  *  @bank: 0 for first bank, 1 for second bank, etc.
2621  *
2622  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2623  *  bank N is 4096 * N + flash_reg_addr.
2624  **/
2625 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2626 {
2627         struct e1000_nvm_info *nvm = &hw->nvm;
2628         union ich8_hws_flash_status hsfsts;
2629         union ich8_hws_flash_ctrl hsflctl;
2630         u32 flash_linear_addr;
2631         /* bank size is in 16bit words - adjust to bytes */
2632         u32 flash_bank_size = nvm->flash_bank_size * 2;
2633         s32 ret_val;
2634         s32 count = 0;
2635         s32 j, iteration, sector_size;
2636
2637         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2638
2639         /*
2640          * Determine HW Sector size: Read BERASE bits of hw flash status
2641          * register
2642          * 00: The Hw sector is 256 bytes, hence we need to erase 16
2643          *     consecutive sectors.  The start index for the nth Hw sector
2644          *     can be calculated as = bank * 4096 + n * 256
2645          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2646          *     The start index for the nth Hw sector can be calculated
2647          *     as = bank * 4096
2648          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2649          *     (ich9 only, otherwise error condition)
2650          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2651          */
2652         switch (hsfsts.hsf_status.berasesz) {
2653         case 0:
2654                 /* Hw sector size 256 */
2655                 sector_size = ICH_FLASH_SEG_SIZE_256;
2656                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2657                 break;
2658         case 1:
2659                 sector_size = ICH_FLASH_SEG_SIZE_4K;
2660                 iteration = 1;
2661                 break;
2662         case 2:
2663                 sector_size = ICH_FLASH_SEG_SIZE_8K;
2664                 iteration = 1;
2665                 break;
2666         case 3:
2667                 sector_size = ICH_FLASH_SEG_SIZE_64K;
2668                 iteration = 1;
2669                 break;
2670         default:
2671                 return -E1000_ERR_NVM;
2672         }
2673
2674         /* Start with the base address, then add the sector offset. */
2675         flash_linear_addr = hw->nvm.flash_base_addr;
2676         flash_linear_addr += (bank) ? flash_bank_size : 0;
2677
2678         for (j = 0; j < iteration ; j++) {
2679                 do {
2680                         /* Steps */
2681                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
2682                         if (ret_val)
2683                                 return ret_val;
2684
2685                         /*
2686                          * Write a value 11 (block Erase) in Flash
2687                          * Cycle field in hw flash control
2688                          */
2689                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2690                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2691                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2692
2693                         /*
2694                          * Write the last 24 bits of an index within the
2695                          * block into Flash Linear address field in Flash
2696                          * Address.
2697                          */
2698                         flash_linear_addr += (j * sector_size);
2699                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2700
2701                         ret_val = e1000_flash_cycle_ich8lan(hw,
2702                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2703                         if (ret_val == 0)
2704                                 break;
2705
2706                         /*
2707                          * Check if FCERR is set to 1.  If 1,
2708                          * clear it and try the whole sequence
2709                          * a few more times else Done
2710                          */
2711                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2712                         if (hsfsts.hsf_status.flcerr == 1)
2713                                 /* repeat for some time before giving up */
2714                                 continue;
2715                         else if (hsfsts.hsf_status.flcdone == 0)
2716                                 return ret_val;
2717                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2718         }
2719
2720         return 0;
2721 }
2722
2723 /**
2724  *  e1000_valid_led_default_ich8lan - Set the default LED settings
2725  *  @hw: pointer to the HW structure
2726  *  @data: Pointer to the LED settings
2727  *
2728  *  Reads the LED default settings from the NVM to data.  If the NVM LED
2729  *  settings is all 0's or F's, set the LED default to a valid LED default
2730  *  setting.
2731  **/
2732 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2733 {
2734         s32 ret_val;
2735
2736         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2737         if (ret_val) {
2738                 e_dbg("NVM Read Error\n");
2739                 return ret_val;
2740         }
2741
2742         if (*data == ID_LED_RESERVED_0000 ||
2743             *data == ID_LED_RESERVED_FFFF)
2744                 *data = ID_LED_DEFAULT_ICH8LAN;
2745
2746         return 0;
2747 }
2748
2749 /**
2750  *  e1000_id_led_init_pchlan - store LED configurations
2751  *  @hw: pointer to the HW structure
2752  *
2753  *  PCH does not control LEDs via the LEDCTL register, rather it uses
2754  *  the PHY LED configuration register.
2755  *
2756  *  PCH also does not have an "always on" or "always off" mode which
2757  *  complicates the ID feature.  Instead of using the "on" mode to indicate
2758  *  in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2759  *  use "link_up" mode.  The LEDs will still ID on request if there is no
2760  *  link based on logic in e1000_led_[on|off]_pchlan().
2761  **/
2762 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2763 {
2764         struct e1000_mac_info *mac = &hw->mac;
2765         s32 ret_val;
2766         const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2767         const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2768         u16 data, i, temp, shift;
2769
2770         /* Get default ID LED modes */
2771         ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2772         if (ret_val)
2773                 goto out;
2774
2775         mac->ledctl_default = er32(LEDCTL);
2776         mac->ledctl_mode1 = mac->ledctl_default;
2777         mac->ledctl_mode2 = mac->ledctl_default;
2778
2779         for (i = 0; i < 4; i++) {
2780                 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2781                 shift = (i * 5);
2782                 switch (temp) {
2783                 case ID_LED_ON1_DEF2:
2784                 case ID_LED_ON1_ON2:
2785                 case ID_LED_ON1_OFF2:
2786                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2787                         mac->ledctl_mode1 |= (ledctl_on << shift);
2788                         break;
2789                 case ID_LED_OFF1_DEF2:
2790                 case ID_LED_OFF1_ON2:
2791                 case ID_LED_OFF1_OFF2:
2792                         mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2793                         mac->ledctl_mode1 |= (ledctl_off << shift);
2794                         break;
2795                 default:
2796                         /* Do nothing */
2797                         break;
2798                 }
2799                 switch (temp) {
2800                 case ID_LED_DEF1_ON2:
2801                 case ID_LED_ON1_ON2:
2802                 case ID_LED_OFF1_ON2:
2803                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2804                         mac->ledctl_mode2 |= (ledctl_on << shift);
2805                         break;
2806                 case ID_LED_DEF1_OFF2:
2807                 case ID_LED_ON1_OFF2:
2808                 case ID_LED_OFF1_OFF2:
2809                         mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2810                         mac->ledctl_mode2 |= (ledctl_off << shift);
2811                         break;
2812                 default:
2813                         /* Do nothing */
2814                         break;
2815                 }
2816         }
2817
2818 out:
2819         return ret_val;
2820 }
2821
2822 /**
2823  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2824  *  @hw: pointer to the HW structure
2825  *
2826  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2827  *  register, so the the bus width is hard coded.
2828  **/
2829 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2830 {
2831         struct e1000_bus_info *bus = &hw->bus;
2832         s32 ret_val;
2833
2834         ret_val = e1000e_get_bus_info_pcie(hw);
2835
2836         /*
2837          * ICH devices are "PCI Express"-ish.  They have
2838          * a configuration space, but do not contain
2839          * PCI Express Capability registers, so bus width
2840          * must be hardcoded.
2841          */
2842         if (bus->width == e1000_bus_width_unknown)
2843                 bus->width = e1000_bus_width_pcie_x1;
2844
2845         return ret_val;
2846 }
2847
2848 /**
2849  *  e1000_reset_hw_ich8lan - Reset the hardware
2850  *  @hw: pointer to the HW structure
2851  *
2852  *  Does a full reset of the hardware which includes a reset of the PHY and
2853  *  MAC.
2854  **/
2855 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
2856 {
2857         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2858         u16 reg;
2859         u32 ctrl, icr, kab;
2860         s32 ret_val;
2861
2862         /*
2863          * Prevent the PCI-E bus from sticking if there is no TLP connection
2864          * on the last TLP read/write transaction when MAC is reset.
2865          */
2866         ret_val = e1000e_disable_pcie_master(hw);
2867         if (ret_val)
2868                 e_dbg("PCI-E Master disable polling has failed.\n");
2869
2870         e_dbg("Masking off all interrupts\n");
2871         ew32(IMC, 0xffffffff);
2872
2873         /*
2874          * Disable the Transmit and Receive units.  Then delay to allow
2875          * any pending transactions to complete before we hit the MAC
2876          * with the global reset.
2877          */
2878         ew32(RCTL, 0);
2879         ew32(TCTL, E1000_TCTL_PSP);
2880         e1e_flush();
2881
2882         msleep(10);
2883
2884         /* Workaround for ICH8 bit corruption issue in FIFO memory */
2885         if (hw->mac.type == e1000_ich8lan) {
2886                 /* Set Tx and Rx buffer allocation to 8k apiece. */
2887                 ew32(PBA, E1000_PBA_8K);
2888                 /* Set Packet Buffer Size to 16k. */
2889                 ew32(PBS, E1000_PBS_16K);
2890         }
2891
2892         if (hw->mac.type == e1000_pchlan) {
2893                 /* Save the NVM K1 bit setting*/
2894                 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &reg);
2895                 if (ret_val)
2896                         return ret_val;
2897
2898                 if (reg & E1000_NVM_K1_ENABLE)
2899                         dev_spec->nvm_k1_enabled = true;
2900                 else
2901                         dev_spec->nvm_k1_enabled = false;
2902         }
2903
2904         ctrl = er32(CTRL);
2905
2906         if (!e1000_check_reset_block(hw)) {
2907                 /*
2908                  * Full-chip reset requires MAC and PHY reset at the same
2909                  * time to make sure the interface between MAC and the
2910                  * external PHY is reset.
2911                  */
2912                 ctrl |= E1000_CTRL_PHY_RST;
2913         }
2914         ret_val = e1000_acquire_swflag_ich8lan(hw);
2915         e_dbg("Issuing a global reset to ich8lan\n");
2916         ew32(CTRL, (ctrl | E1000_CTRL_RST));
2917         msleep(20);
2918
2919         if (!ret_val)
2920                 e1000_release_swflag_ich8lan(hw);
2921
2922         if (ctrl & E1000_CTRL_PHY_RST) {
2923                 ret_val = hw->phy.ops.get_cfg_done(hw);
2924                 if (ret_val)
2925                         goto out;
2926
2927                 ret_val = e1000_post_phy_reset_ich8lan(hw);
2928                 if (ret_val)
2929                         goto out;
2930         }
2931
2932         /*
2933          * For PCH, this write will make sure that any noise
2934          * will be detected as a CRC error and be dropped rather than show up
2935          * as a bad packet to the DMA engine.
2936          */
2937         if (hw->mac.type == e1000_pchlan)
2938                 ew32(CRC_OFFSET, 0x65656565);
2939
2940         ew32(IMC, 0xffffffff);
2941         icr = er32(ICR);
2942
2943         kab = er32(KABGTXD);
2944         kab |= E1000_KABGTXD_BGSQLBIAS;
2945         ew32(KABGTXD, kab);
2946
2947 out:
2948         return ret_val;
2949 }
2950
2951 /**
2952  *  e1000_init_hw_ich8lan - Initialize the hardware
2953  *  @hw: pointer to the HW structure
2954  *
2955  *  Prepares the hardware for transmit and receive by doing the following:
2956  *   - initialize hardware bits
2957  *   - initialize LED identification
2958  *   - setup receive address registers
2959  *   - setup flow control
2960  *   - setup transmit descriptors
2961  *   - clear statistics
2962  **/
2963 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
2964 {
2965         struct e1000_mac_info *mac = &hw->mac;
2966         u32 ctrl_ext, txdctl, snoop;
2967         s32 ret_val;
2968         u16 i;
2969
2970         e1000_initialize_hw_bits_ich8lan(hw);
2971
2972         /* Initialize identification LED */
2973         ret_val = mac->ops.id_led_init(hw);
2974         if (ret_val)
2975                 e_dbg("Error initializing identification LED\n");
2976                 /* This is not fatal and we should not stop init due to this */
2977
2978         /* Setup the receive address. */
2979         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
2980
2981         /* Zero out the Multicast HASH table */
2982         e_dbg("Zeroing the MTA\n");
2983         for (i = 0; i < mac->mta_reg_count; i++)
2984                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
2985
2986         /*
2987          * The 82578 Rx buffer will stall if wakeup is enabled in host and
2988          * the ME.  Reading the BM_WUC register will clear the host wakeup bit.
2989          * Reset the phy after disabling host wakeup to reset the Rx buffer.
2990          */
2991         if (hw->phy.type == e1000_phy_82578) {
2992                 hw->phy.ops.read_reg(hw, BM_WUC, &i);
2993                 ret_val = e1000_phy_hw_reset_ich8lan(hw);
2994                 if (ret_val)
2995                         return ret_val;
2996         }
2997
2998         /* Setup link and flow control */
2999         ret_val = e1000_setup_link_ich8lan(hw);
3000
3001         /* Set the transmit descriptor write-back policy for both queues */
3002         txdctl = er32(TXDCTL(0));
3003         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3004                  E1000_TXDCTL_FULL_TX_DESC_WB;
3005         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3006                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3007         ew32(TXDCTL(0), txdctl);
3008         txdctl = er32(TXDCTL(1));
3009         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3010                  E1000_TXDCTL_FULL_TX_DESC_WB;
3011         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3012                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3013         ew32(TXDCTL(1), txdctl);
3014
3015         /*
3016          * ICH8 has opposite polarity of no_snoop bits.
3017          * By default, we should use snoop behavior.
3018          */
3019         if (mac->type == e1000_ich8lan)
3020                 snoop = PCIE_ICH8_SNOOP_ALL;
3021         else
3022                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3023         e1000e_set_pcie_no_snoop(hw, snoop);
3024
3025         ctrl_ext = er32(CTRL_EXT);
3026         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3027         ew32(CTRL_EXT, ctrl_ext);
3028
3029         /*
3030          * Clear all of the statistics registers (clear on read).  It is
3031          * important that we do this after we have tried to establish link
3032          * because the symbol error count will increment wildly if there
3033          * is no link.
3034          */
3035         e1000_clear_hw_cntrs_ich8lan(hw);
3036
3037         return 0;
3038 }
3039 /**
3040  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3041  *  @hw: pointer to the HW structure
3042  *
3043  *  Sets/Clears required hardware bits necessary for correctly setting up the
3044  *  hardware for transmit and receive.
3045  **/
3046 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3047 {
3048         u32 reg;
3049
3050         /* Extended Device Control */
3051         reg = er32(CTRL_EXT);
3052         reg |= (1 << 22);
3053         /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3054         if (hw->mac.type >= e1000_pchlan)
3055                 reg |= E1000_CTRL_EXT_PHYPDEN;
3056         ew32(CTRL_EXT, reg);
3057
3058         /* Transmit Descriptor Control 0 */
3059         reg = er32(TXDCTL(0));
3060         reg |= (1 << 22);
3061         ew32(TXDCTL(0), reg);
3062
3063         /* Transmit Descriptor Control 1 */
3064         reg = er32(TXDCTL(1));
3065         reg |= (1 << 22);
3066         ew32(TXDCTL(1), reg);
3067
3068         /* Transmit Arbitration Control 0 */
3069         reg = er32(TARC(0));
3070         if (hw->mac.type == e1000_ich8lan)
3071                 reg |= (1 << 28) | (1 << 29);
3072         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3073         ew32(TARC(0), reg);
3074
3075         /* Transmit Arbitration Control 1 */
3076         reg = er32(TARC(1));
3077         if (er32(TCTL) & E1000_TCTL_MULR)
3078                 reg &= ~(1 << 28);
3079         else
3080                 reg |= (1 << 28);
3081         reg |= (1 << 24) | (1 << 26) | (1 << 30);
3082         ew32(TARC(1), reg);
3083
3084         /* Device Status */
3085         if (hw->mac.type == e1000_ich8lan) {
3086                 reg = er32(STATUS);
3087                 reg &= ~(1 << 31);
3088                 ew32(STATUS, reg);
3089         }
3090
3091         /*
3092          * work-around descriptor data corruption issue during nfs v2 udp
3093          * traffic, just disable the nfs filtering capability
3094          */
3095         reg = er32(RFCTL);
3096         reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3097         ew32(RFCTL, reg);
3098 }
3099
3100 /**
3101  *  e1000_setup_link_ich8lan - Setup flow control and link settings
3102  *  @hw: pointer to the HW structure
3103  *
3104  *  Determines which flow control settings to use, then configures flow
3105  *  control.  Calls the appropriate media-specific link configuration
3106  *  function.  Assuming the adapter has a valid link partner, a valid link
3107  *  should be established.  Assumes the hardware has previously been reset
3108  *  and the transmitter and receiver are not enabled.
3109  **/
3110 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3111 {
3112         s32 ret_val;
3113
3114         if (e1000_check_reset_block(hw))
3115                 return 0;
3116
3117         /*
3118          * ICH parts do not have a word in the NVM to determine
3119          * the default flow control setting, so we explicitly
3120          * set it to full.
3121          */
3122         if (hw->fc.requested_mode == e1000_fc_default) {
3123                 /* Workaround h/w hang when Tx flow control enabled */
3124                 if (hw->mac.type == e1000_pchlan)
3125                         hw->fc.requested_mode = e1000_fc_rx_pause;
3126                 else
3127                         hw->fc.requested_mode = e1000_fc_full;
3128         }
3129
3130         /*
3131          * Save off the requested flow control mode for use later.  Depending
3132          * on the link partner's capabilities, we may or may not use this mode.
3133          */
3134         hw->fc.current_mode = hw->fc.requested_mode;
3135
3136         e_dbg("After fix-ups FlowControl is now = %x\n",
3137                 hw->fc.current_mode);
3138
3139         /* Continue to configure the copper link. */
3140         ret_val = e1000_setup_copper_link_ich8lan(hw);
3141         if (ret_val)
3142                 return ret_val;
3143
3144         ew32(FCTTV, hw->fc.pause_time);
3145         if ((hw->phy.type == e1000_phy_82578) ||
3146             (hw->phy.type == e1000_phy_82579) ||
3147             (hw->phy.type == e1000_phy_82577)) {
3148                 ew32(FCRTV_PCH, hw->fc.refresh_time);
3149
3150                 ret_val = hw->phy.ops.write_reg(hw,
3151                                              PHY_REG(BM_PORT_CTRL_PAGE, 27),
3152                                              hw->fc.pause_time);
3153                 if (ret_val)
3154                         return ret_val;
3155         }
3156
3157         return e1000e_set_fc_watermarks(hw);
3158 }
3159
3160 /**
3161  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3162  *  @hw: pointer to the HW structure
3163  *
3164  *  Configures the kumeran interface to the PHY to wait the appropriate time
3165  *  when polling the PHY, then call the generic setup_copper_link to finish
3166  *  configuring the copper link.
3167  **/
3168 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3169 {
3170         u32 ctrl;
3171         s32 ret_val;
3172         u16 reg_data;
3173
3174         ctrl = er32(CTRL);
3175         ctrl |= E1000_CTRL_SLU;
3176         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3177         ew32(CTRL, ctrl);
3178
3179         /*
3180          * Set the mac to wait the maximum time between each iteration
3181          * and increase the max iterations when polling the phy;
3182          * this fixes erroneous timeouts at 10Mbps.
3183          */
3184         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3185         if (ret_val)
3186                 return ret_val;
3187         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3188                                        &reg_data);
3189         if (ret_val)
3190                 return ret_val;
3191         reg_data |= 0x3F;
3192         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3193                                         reg_data);
3194         if (ret_val)
3195                 return ret_val;
3196
3197         switch (hw->phy.type) {
3198         case e1000_phy_igp_3:
3199                 ret_val = e1000e_copper_link_setup_igp(hw);
3200                 if (ret_val)
3201                         return ret_val;
3202                 break;
3203         case e1000_phy_bm:
3204         case e1000_phy_82578:
3205                 ret_val = e1000e_copper_link_setup_m88(hw);
3206                 if (ret_val)
3207                         return ret_val;
3208                 break;
3209         case e1000_phy_82577:
3210         case e1000_phy_82579:
3211                 ret_val = e1000_copper_link_setup_82577(hw);
3212                 if (ret_val)
3213                         return ret_val;
3214                 break;
3215         case e1000_phy_ife:
3216                 ret_val = hw->phy.ops.read_reg(hw, IFE_PHY_MDIX_CONTROL,
3217                                                &reg_data);
3218                 if (ret_val)
3219                         return ret_val;
3220
3221                 reg_data &= ~IFE_PMC_AUTO_MDIX;
3222
3223                 switch (hw->phy.mdix) {
3224                 case 1:
3225                         reg_data &= ~IFE_PMC_FORCE_MDIX;
3226                         break;
3227                 case 2:
3228                         reg_data |= IFE_PMC_FORCE_MDIX;
3229                         break;
3230                 case 0:
3231                 default:
3232                         reg_data |= IFE_PMC_AUTO_MDIX;
3233                         break;
3234                 }
3235                 ret_val = hw->phy.ops.write_reg(hw, IFE_PHY_MDIX_CONTROL,
3236                                                 reg_data);
3237                 if (ret_val)
3238                         return ret_val;
3239                 break;
3240         default:
3241                 break;
3242         }
3243         return e1000e_setup_copper_link(hw);
3244 }
3245
3246 /**
3247  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3248  *  @hw: pointer to the HW structure
3249  *  @speed: pointer to store current link speed
3250  *  @duplex: pointer to store the current link duplex
3251  *
3252  *  Calls the generic get_speed_and_duplex to retrieve the current link
3253  *  information and then calls the Kumeran lock loss workaround for links at
3254  *  gigabit speeds.
3255  **/
3256 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3257                                           u16 *duplex)
3258 {
3259         s32 ret_val;
3260
3261         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3262         if (ret_val)
3263                 return ret_val;
3264
3265         if ((hw->mac.type == e1000_ich8lan) &&
3266             (hw->phy.type == e1000_phy_igp_3) &&
3267             (*speed == SPEED_1000)) {
3268                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3269         }
3270
3271         return ret_val;
3272 }
3273
3274 /**
3275  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3276  *  @hw: pointer to the HW structure
3277  *
3278  *  Work-around for 82566 Kumeran PCS lock loss:
3279  *  On link status change (i.e. PCI reset, speed change) and link is up and
3280  *  speed is gigabit-
3281  *    0) if workaround is optionally disabled do nothing
3282  *    1) wait 1ms for Kumeran link to come up
3283  *    2) check Kumeran Diagnostic register PCS lock loss bit
3284  *    3) if not set the link is locked (all is good), otherwise...
3285  *    4) reset the PHY
3286  *    5) repeat up to 10 times
3287  *  Note: this is only called for IGP3 copper when speed is 1gb.
3288  **/
3289 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3290 {
3291         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3292         u32 phy_ctrl;
3293         s32 ret_val;
3294         u16 i, data;
3295         bool link;
3296
3297         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3298                 return 0;
3299
3300         /*
3301          * Make sure link is up before proceeding.  If not just return.
3302          * Attempting this while link is negotiating fouled up link
3303          * stability
3304          */
3305         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3306         if (!link)
3307                 return 0;
3308
3309         for (i = 0; i < 10; i++) {
3310                 /* read once to clear */
3311                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3312                 if (ret_val)
3313                         return ret_val;
3314                 /* and again to get new status */
3315                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3316                 if (ret_val)
3317                         return ret_val;
3318
3319                 /* check for PCS lock */
3320                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3321                         return 0;
3322
3323                 /* Issue PHY reset */
3324                 e1000_phy_hw_reset(hw);
3325                 mdelay(5);
3326         }
3327         /* Disable GigE link negotiation */
3328         phy_ctrl = er32(PHY_CTRL);
3329         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3330                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3331         ew32(PHY_CTRL, phy_ctrl);
3332
3333         /*
3334          * Call gig speed drop workaround on Gig disable before accessing
3335          * any PHY registers
3336          */
3337         e1000e_gig_downshift_workaround_ich8lan(hw);
3338
3339         /* unable to acquire PCS lock */
3340         return -E1000_ERR_PHY;
3341 }
3342
3343 /**
3344  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3345  *  @hw: pointer to the HW structure
3346  *  @state: boolean value used to set the current Kumeran workaround state
3347  *
3348  *  If ICH8, set the current Kumeran workaround state (enabled - true
3349  *  /disabled - false).
3350  **/
3351 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3352                                                  bool state)
3353 {
3354         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3355
3356         if (hw->mac.type != e1000_ich8lan) {
3357                 e_dbg("Workaround applies to ICH8 only.\n");
3358                 return;
3359         }
3360
3361         dev_spec->kmrn_lock_loss_workaround_enabled = state;
3362 }
3363
3364 /**
3365  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3366  *  @hw: pointer to the HW structure
3367  *
3368  *  Workaround for 82566 power-down on D3 entry:
3369  *    1) disable gigabit link
3370  *    2) write VR power-down enable
3371  *    3) read it back
3372  *  Continue if successful, else issue LCD reset and repeat
3373  **/
3374 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3375 {
3376         u32 reg;
3377         u16 data;
3378         u8  retry = 0;
3379
3380         if (hw->phy.type != e1000_phy_igp_3)
3381                 return;
3382
3383         /* Try the workaround twice (if needed) */
3384         do {
3385                 /* Disable link */
3386                 reg = er32(PHY_CTRL);
3387                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3388                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3389                 ew32(PHY_CTRL, reg);
3390
3391                 /*
3392                  * Call gig speed drop workaround on Gig disable before
3393                  * accessing any PHY registers
3394                  */
3395                 if (hw->mac.type == e1000_ich8lan)
3396                         e1000e_gig_downshift_workaround_ich8lan(hw);
3397
3398                 /* Write VR power-down enable */
3399                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3400                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3401                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3402
3403                 /* Read it back and test */
3404                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3405                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3406                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3407                         break;
3408
3409                 /* Issue PHY reset and repeat at most one more time */
3410                 reg = er32(CTRL);
3411                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3412                 retry++;
3413         } while (retry);
3414 }
3415
3416 /**
3417  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3418  *  @hw: pointer to the HW structure
3419  *
3420  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3421  *  LPLU, Gig disable, MDIC PHY reset):
3422  *    1) Set Kumeran Near-end loopback
3423  *    2) Clear Kumeran Near-end loopback
3424  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
3425  **/
3426 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3427 {
3428         s32 ret_val;
3429         u16 reg_data;
3430
3431         if ((hw->mac.type != e1000_ich8lan) ||
3432             (hw->phy.type != e1000_phy_igp_3))
3433                 return;
3434
3435         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3436                                       &reg_data);
3437         if (ret_val)
3438                 return;
3439         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3440         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3441                                        reg_data);
3442         if (ret_val)
3443                 return;
3444         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3445         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3446                                        reg_data);
3447 }
3448
3449 /**
3450  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
3451  *  @hw: pointer to the HW structure
3452  *
3453  *  During S0 to Sx transition, it is possible the link remains at gig
3454  *  instead of negotiating to a lower speed.  Before going to Sx, set
3455  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3456  *  to a lower speed.
3457  *
3458  *  Should only be called for applicable parts.
3459  **/
3460 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
3461 {
3462         u32 phy_ctrl;
3463
3464         phy_ctrl = er32(PHY_CTRL);
3465         phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3466         ew32(PHY_CTRL, phy_ctrl);
3467
3468         if (hw->mac.type >= e1000_pchlan)
3469                 e1000_phy_hw_reset_ich8lan(hw);
3470 }
3471
3472 /**
3473  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
3474  *  @hw: pointer to the HW structure
3475  *
3476  *  Return the LED back to the default configuration.
3477  **/
3478 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3479 {
3480         if (hw->phy.type == e1000_phy_ife)
3481                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3482
3483         ew32(LEDCTL, hw->mac.ledctl_default);
3484         return 0;
3485 }
3486
3487 /**
3488  *  e1000_led_on_ich8lan - Turn LEDs on
3489  *  @hw: pointer to the HW structure
3490  *
3491  *  Turn on the LEDs.
3492  **/
3493 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3494 {
3495         if (hw->phy.type == e1000_phy_ife)
3496                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3497                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3498
3499         ew32(LEDCTL, hw->mac.ledctl_mode2);
3500         return 0;
3501 }
3502
3503 /**
3504  *  e1000_led_off_ich8lan - Turn LEDs off
3505  *  @hw: pointer to the HW structure
3506  *
3507  *  Turn off the LEDs.
3508  **/
3509 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3510 {
3511         if (hw->phy.type == e1000_phy_ife)
3512                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3513                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
3514
3515         ew32(LEDCTL, hw->mac.ledctl_mode1);
3516         return 0;
3517 }
3518
3519 /**
3520  *  e1000_setup_led_pchlan - Configures SW controllable LED
3521  *  @hw: pointer to the HW structure
3522  *
3523  *  This prepares the SW controllable LED for use.
3524  **/
3525 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3526 {
3527         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3528                                         (u16)hw->mac.ledctl_mode1);
3529 }
3530
3531 /**
3532  *  e1000_cleanup_led_pchlan - Restore the default LED operation
3533  *  @hw: pointer to the HW structure
3534  *
3535  *  Return the LED back to the default configuration.
3536  **/
3537 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3538 {
3539         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG,
3540                                         (u16)hw->mac.ledctl_default);
3541 }
3542
3543 /**
3544  *  e1000_led_on_pchlan - Turn LEDs on
3545  *  @hw: pointer to the HW structure
3546  *
3547  *  Turn on the LEDs.
3548  **/
3549 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3550 {
3551         u16 data = (u16)hw->mac.ledctl_mode2;
3552         u32 i, led;
3553
3554         /*
3555          * If no link, then turn LED on by setting the invert bit
3556          * for each LED that's mode is "link_up" in ledctl_mode2.
3557          */
3558         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3559                 for (i = 0; i < 3; i++) {
3560                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3561                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3562                             E1000_LEDCTL_MODE_LINK_UP)
3563                                 continue;
3564                         if (led & E1000_PHY_LED0_IVRT)
3565                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3566                         else
3567                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3568                 }
3569         }
3570
3571         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3572 }
3573
3574 /**
3575  *  e1000_led_off_pchlan - Turn LEDs off
3576  *  @hw: pointer to the HW structure
3577  *
3578  *  Turn off the LEDs.
3579  **/
3580 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3581 {
3582         u16 data = (u16)hw->mac.ledctl_mode1;
3583         u32 i, led;
3584
3585         /*
3586          * If no link, then turn LED off by clearing the invert bit
3587          * for each LED that's mode is "link_up" in ledctl_mode1.
3588          */
3589         if (!(er32(STATUS) & E1000_STATUS_LU)) {
3590                 for (i = 0; i < 3; i++) {
3591                         led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3592                         if ((led & E1000_PHY_LED0_MODE_MASK) !=
3593                             E1000_LEDCTL_MODE_LINK_UP)
3594                                 continue;
3595                         if (led & E1000_PHY_LED0_IVRT)
3596                                 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3597                         else
3598                                 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3599                 }
3600         }
3601
3602         return hw->phy.ops.write_reg(hw, HV_LED_CONFIG, data);
3603 }
3604
3605 /**
3606  *  e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3607  *  @hw: pointer to the HW structure
3608  *
3609  *  Read appropriate register for the config done bit for completion status
3610  *  and configure the PHY through s/w for EEPROM-less parts.
3611  *
3612  *  NOTE: some silicon which is EEPROM-less will fail trying to read the
3613  *  config done bit, so only an error is logged and continues.  If we were
3614  *  to return with error, EEPROM-less silicon would not be able to be reset
3615  *  or change link.
3616  **/
3617 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3618 {
3619         s32 ret_val = 0;
3620         u32 bank = 0;
3621         u32 status;
3622
3623         e1000e_get_cfg_done(hw);
3624
3625         /* Wait for indication from h/w that it has completed basic config */
3626         if (hw->mac.type >= e1000_ich10lan) {
3627                 e1000_lan_init_done_ich8lan(hw);
3628         } else {
3629                 ret_val = e1000e_get_auto_rd_done(hw);
3630                 if (ret_val) {
3631                         /*
3632                          * When auto config read does not complete, do not
3633                          * return with an error. This can happen in situations
3634                          * where there is no eeprom and prevents getting link.
3635                          */
3636                         e_dbg("Auto Read Done did not complete\n");
3637                         ret_val = 0;
3638                 }
3639         }
3640
3641         /* Clear PHY Reset Asserted bit */
3642         status = er32(STATUS);
3643         if (status & E1000_STATUS_PHYRA)
3644                 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3645         else
3646                 e_dbg("PHY Reset Asserted not set - needs delay\n");
3647
3648         /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3649         if (hw->mac.type <= e1000_ich9lan) {
3650                 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3651                     (hw->phy.type == e1000_phy_igp_3)) {
3652                         e1000e_phy_init_script_igp3(hw);
3653                 }
3654         } else {
3655                 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3656                         /* Maybe we should do a basic PHY config */
3657                         e_dbg("EEPROM not present\n");
3658                         ret_val = -E1000_ERR_CONFIG;
3659                 }
3660         }
3661
3662         return ret_val;
3663 }
3664
3665 /**
3666  * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3667  * @hw: pointer to the HW structure
3668  *
3669  * In the case of a PHY power down to save power, or to turn off link during a
3670  * driver unload, or wake on lan is not enabled, remove the link.
3671  **/
3672 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3673 {
3674         /* If the management interface is not enabled, then power down */
3675         if (!(hw->mac.ops.check_mng_mode(hw) ||
3676               hw->phy.ops.check_reset_block(hw)))
3677                 e1000_power_down_phy_copper(hw);
3678 }
3679
3680 /**
3681  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3682  *  @hw: pointer to the HW structure
3683  *
3684  *  Clears hardware counters specific to the silicon family and calls
3685  *  clear_hw_cntrs_generic to clear all general purpose counters.
3686  **/
3687 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3688 {
3689         u16 phy_data;
3690
3691         e1000e_clear_hw_cntrs_base(hw);
3692
3693         er32(ALGNERRC);
3694         er32(RXERRC);
3695         er32(TNCRS);
3696         er32(CEXTERR);
3697         er32(TSCTC);
3698         er32(TSCTFC);
3699
3700         er32(MGTPRC);
3701         er32(MGTPDC);
3702         er32(MGTPTC);
3703
3704         er32(IAC);
3705         er32(ICRXOC);
3706
3707         /* Clear PHY statistics registers */
3708         if ((hw->phy.type == e1000_phy_82578) ||
3709             (hw->phy.type == e1000_phy_82579) ||
3710             (hw->phy.type == e1000_phy_82577)) {
3711                 hw->phy.ops.read_reg(hw, HV_SCC_UPPER, &phy_data);
3712                 hw->phy.ops.read_reg(hw, HV_SCC_LOWER, &phy_data);
3713                 hw->phy.ops.read_reg(hw, HV_ECOL_UPPER, &phy_data);
3714                 hw->phy.ops.read_reg(hw, HV_ECOL_LOWER, &phy_data);
3715                 hw->phy.ops.read_reg(hw, HV_MCC_UPPER, &phy_data);
3716                 hw->phy.ops.read_reg(hw, HV_MCC_LOWER, &phy_data);
3717                 hw->phy.ops.read_reg(hw, HV_LATECOL_UPPER, &phy_data);
3718                 hw->phy.ops.read_reg(hw, HV_LATECOL_LOWER, &phy_data);
3719                 hw->phy.ops.read_reg(hw, HV_COLC_UPPER, &phy_data);
3720                 hw->phy.ops.read_reg(hw, HV_COLC_LOWER, &phy_data);
3721                 hw->phy.ops.read_reg(hw, HV_DC_UPPER, &phy_data);
3722                 hw->phy.ops.read_reg(hw, HV_DC_LOWER, &phy_data);
3723                 hw->phy.ops.read_reg(hw, HV_TNCRS_UPPER, &phy_data);
3724                 hw->phy.ops.read_reg(hw, HV_TNCRS_LOWER, &phy_data);
3725         }
3726 }
3727
3728 static struct e1000_mac_operations ich8_mac_ops = {
3729         .id_led_init            = e1000e_id_led_init,
3730         /* check_mng_mode dependent on mac type */
3731         .check_for_link         = e1000_check_for_copper_link_ich8lan,
3732         /* cleanup_led dependent on mac type */
3733         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
3734         .get_bus_info           = e1000_get_bus_info_ich8lan,
3735         .set_lan_id             = e1000_set_lan_id_single_port,
3736         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
3737         /* led_on dependent on mac type */
3738         /* led_off dependent on mac type */
3739         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
3740         .reset_hw               = e1000_reset_hw_ich8lan,
3741         .init_hw                = e1000_init_hw_ich8lan,
3742         .setup_link             = e1000_setup_link_ich8lan,
3743         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3744         /* id_led_init dependent on mac type */
3745 };
3746
3747 static struct e1000_phy_operations ich8_phy_ops = {
3748         .acquire                = e1000_acquire_swflag_ich8lan,
3749         .check_reset_block      = e1000_check_reset_block_ich8lan,
3750         .commit                 = NULL,
3751         .get_cfg_done           = e1000_get_cfg_done_ich8lan,
3752         .get_cable_length       = e1000e_get_cable_length_igp_2,
3753         .read_reg               = e1000e_read_phy_reg_igp,
3754         .release                = e1000_release_swflag_ich8lan,
3755         .reset                  = e1000_phy_hw_reset_ich8lan,
3756         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
3757         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
3758         .write_reg              = e1000e_write_phy_reg_igp,
3759 };
3760
3761 static struct e1000_nvm_operations ich8_nvm_ops = {
3762         .acquire                = e1000_acquire_nvm_ich8lan,
3763         .read                   = e1000_read_nvm_ich8lan,
3764         .release                = e1000_release_nvm_ich8lan,
3765         .update                 = e1000_update_nvm_checksum_ich8lan,
3766         .valid_led_default      = e1000_valid_led_default_ich8lan,
3767         .validate               = e1000_validate_nvm_checksum_ich8lan,
3768         .write                  = e1000_write_nvm_ich8lan,
3769 };
3770
3771 struct e1000_info e1000_ich8_info = {
3772         .mac                    = e1000_ich8lan,
3773         .flags                  = FLAG_HAS_WOL
3774                                   | FLAG_IS_ICH
3775                                   | FLAG_RX_CSUM_ENABLED
3776                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3777                                   | FLAG_HAS_AMT
3778                                   | FLAG_HAS_FLASH
3779                                   | FLAG_APME_IN_WUC,
3780         .pba                    = 8,
3781         .max_hw_frame_size      = ETH_FRAME_LEN + ETH_FCS_LEN,
3782         .get_variants           = e1000_get_variants_ich8lan,
3783         .mac_ops                = &ich8_mac_ops,
3784         .phy_ops                = &ich8_phy_ops,
3785         .nvm_ops                = &ich8_nvm_ops,
3786 };
3787
3788 struct e1000_info e1000_ich9_info = {
3789         .mac                    = e1000_ich9lan,
3790         .flags                  = FLAG_HAS_JUMBO_FRAMES
3791                                   | FLAG_IS_ICH
3792                                   | FLAG_HAS_WOL
3793                                   | FLAG_RX_CSUM_ENABLED
3794                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3795                                   | FLAG_HAS_AMT
3796                                   | FLAG_HAS_ERT
3797                                   | FLAG_HAS_FLASH
3798                                   | FLAG_APME_IN_WUC,
3799         .pba                    = 10,
3800         .max_hw_frame_size      = DEFAULT_JUMBO,
3801         .get_variants           = e1000_get_variants_ich8lan,
3802         .mac_ops                = &ich8_mac_ops,
3803         .phy_ops                = &ich8_phy_ops,
3804         .nvm_ops                = &ich8_nvm_ops,
3805 };
3806
3807 struct e1000_info e1000_ich10_info = {
3808         .mac                    = e1000_ich10lan,
3809         .flags                  = FLAG_HAS_JUMBO_FRAMES
3810                                   | FLAG_IS_ICH
3811                                   | FLAG_HAS_WOL
3812                                   | FLAG_RX_CSUM_ENABLED
3813                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3814                                   | FLAG_HAS_AMT
3815                                   | FLAG_HAS_ERT
3816                                   | FLAG_HAS_FLASH
3817                                   | FLAG_APME_IN_WUC,
3818         .pba                    = 10,
3819         .max_hw_frame_size      = DEFAULT_JUMBO,
3820         .get_variants           = e1000_get_variants_ich8lan,
3821         .mac_ops                = &ich8_mac_ops,
3822         .phy_ops                = &ich8_phy_ops,
3823         .nvm_ops                = &ich8_nvm_ops,
3824 };
3825
3826 struct e1000_info e1000_pch_info = {
3827         .mac                    = e1000_pchlan,
3828         .flags                  = FLAG_IS_ICH
3829                                   | FLAG_HAS_WOL
3830                                   | FLAG_RX_CSUM_ENABLED
3831                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3832                                   | FLAG_HAS_AMT
3833                                   | FLAG_HAS_FLASH
3834                                   | FLAG_HAS_JUMBO_FRAMES
3835                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
3836                                   | FLAG_APME_IN_WUC,
3837         .flags2                 = FLAG2_HAS_PHY_STATS,
3838         .pba                    = 26,
3839         .max_hw_frame_size      = 4096,
3840         .get_variants           = e1000_get_variants_ich8lan,
3841         .mac_ops                = &ich8_mac_ops,
3842         .phy_ops                = &ich8_phy_ops,
3843         .nvm_ops                = &ich8_nvm_ops,
3844 };
3845
3846 struct e1000_info e1000_pch2_info = {
3847         .mac                    = e1000_pch2lan,
3848         .flags                  = FLAG_IS_ICH
3849                                   | FLAG_HAS_WOL
3850                                   | FLAG_RX_CSUM_ENABLED
3851                                   | FLAG_HAS_CTRLEXT_ON_LOAD
3852                                   | FLAG_HAS_AMT
3853                                   | FLAG_HAS_FLASH
3854                                   | FLAG_HAS_JUMBO_FRAMES
3855                                   | FLAG_APME_IN_WUC,
3856         .flags2                 = FLAG2_HAS_PHY_STATS
3857                                   | FLAG2_HAS_EEE,
3858         .pba                    = 18,
3859         .max_hw_frame_size      = DEFAULT_JUMBO,
3860         .get_variants           = e1000_get_variants_ich8lan,
3861         .mac_ops                = &ich8_mac_ops,
3862         .phy_ops                = &ich8_phy_ops,
3863         .nvm_ops                = &ich8_nvm_ops,
3864 };