2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
18 #include "mv88e6xxx.h"
20 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
21 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
22 * will be directly accessible on some {device address,register address}
23 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
24 * will only respond to SMI transactions to that specific address, and
25 * an indirect addressing mechanism needs to be used to access its
28 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
33 for (i = 0; i < 16; i++) {
34 ret = mdiobus_read(bus, sw_addr, 0);
38 if ((ret & 0x8000) == 0)
45 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
50 return mdiobus_read(bus, addr, reg);
52 /* Wait for the bus to become free. */
53 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
57 /* Transmit the read command. */
58 ret = mdiobus_write(bus, sw_addr, 0, 0x9800 | (addr << 5) | reg);
62 /* Wait for the read command to complete. */
63 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
68 ret = mdiobus_read(bus, sw_addr, 1);
75 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
77 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
78 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
84 mutex_lock(&ps->smi_mutex);
85 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
86 mutex_unlock(&ps->smi_mutex);
91 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
97 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
103 return mdiobus_write(bus, addr, reg, val);
105 /* Wait for the bus to become free. */
106 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
110 /* Transmit the data to write. */
111 ret = mdiobus_write(bus, sw_addr, 1, val);
115 /* Transmit the write command. */
116 ret = mdiobus_write(bus, sw_addr, 0, 0x9400 | (addr << 5) | reg);
120 /* Wait for the write command to complete. */
121 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
128 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
130 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
131 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
137 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
140 mutex_lock(&ps->smi_mutex);
141 ret = __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
142 mutex_unlock(&ps->smi_mutex);
147 int mv88e6xxx_config_prio(struct dsa_switch *ds)
149 /* Configure the IP ToS mapping registers. */
150 REG_WRITE(REG_GLOBAL, 0x10, 0x0000);
151 REG_WRITE(REG_GLOBAL, 0x11, 0x0000);
152 REG_WRITE(REG_GLOBAL, 0x12, 0x5555);
153 REG_WRITE(REG_GLOBAL, 0x13, 0x5555);
154 REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa);
155 REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa);
156 REG_WRITE(REG_GLOBAL, 0x16, 0xffff);
157 REG_WRITE(REG_GLOBAL, 0x17, 0xffff);
159 /* Configure the IEEE 802.1p priority mapping register. */
160 REG_WRITE(REG_GLOBAL, 0x18, 0xfa41);
165 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
167 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]);
168 REG_WRITE(REG_GLOBAL, 0x02, (addr[2] << 8) | addr[3]);
169 REG_WRITE(REG_GLOBAL, 0x03, (addr[4] << 8) | addr[5]);
174 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
179 for (i = 0; i < 6; i++) {
182 /* Write the MAC address byte. */
183 REG_WRITE(REG_GLOBAL2, 0x0d, 0x8000 | (i << 8) | addr[i]);
185 /* Wait for the write to complete. */
186 for (j = 0; j < 16; j++) {
187 ret = REG_READ(REG_GLOBAL2, 0x0d);
188 if ((ret & 0x8000) == 0)
198 int mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
201 return mv88e6xxx_reg_read(ds, addr, regnum);
205 int mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum, u16 val)
208 return mv88e6xxx_reg_write(ds, addr, regnum, val);
212 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
213 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
216 unsigned long timeout;
218 ret = REG_READ(REG_GLOBAL, 0x04);
219 REG_WRITE(REG_GLOBAL, 0x04, ret & ~0x4000);
221 timeout = jiffies + 1 * HZ;
222 while (time_before(jiffies, timeout)) {
223 ret = REG_READ(REG_GLOBAL, 0x00);
224 usleep_range(1000, 2000);
225 if ((ret & 0xc000) != 0xc000)
232 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
235 unsigned long timeout;
237 ret = REG_READ(REG_GLOBAL, 0x04);
238 REG_WRITE(REG_GLOBAL, 0x04, ret | 0x4000);
240 timeout = jiffies + 1 * HZ;
241 while (time_before(jiffies, timeout)) {
242 ret = REG_READ(REG_GLOBAL, 0x00);
243 usleep_range(1000, 2000);
244 if ((ret & 0xc000) == 0xc000)
251 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
253 struct mv88e6xxx_priv_state *ps;
255 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
256 if (mutex_trylock(&ps->ppu_mutex)) {
257 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
259 if (mv88e6xxx_ppu_enable(ds) == 0)
260 ps->ppu_disabled = 0;
261 mutex_unlock(&ps->ppu_mutex);
265 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
267 struct mv88e6xxx_priv_state *ps = (void *)_ps;
269 schedule_work(&ps->ppu_work);
272 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
274 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
277 mutex_lock(&ps->ppu_mutex);
279 /* If the PHY polling unit is enabled, disable it so that
280 * we can access the PHY registers. If it was already
281 * disabled, cancel the timer that is going to re-enable
284 if (!ps->ppu_disabled) {
285 ret = mv88e6xxx_ppu_disable(ds);
287 mutex_unlock(&ps->ppu_mutex);
290 ps->ppu_disabled = 1;
292 del_timer(&ps->ppu_timer);
299 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
303 /* Schedule a timer to re-enable the PHY polling unit. */
304 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
305 mutex_unlock(&ps->ppu_mutex);
308 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
310 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
312 mutex_init(&ps->ppu_mutex);
313 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
314 init_timer(&ps->ppu_timer);
315 ps->ppu_timer.data = (unsigned long)ps;
316 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
319 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
323 ret = mv88e6xxx_ppu_access_get(ds);
325 ret = mv88e6xxx_reg_read(ds, addr, regnum);
326 mv88e6xxx_ppu_access_put(ds);
332 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
337 ret = mv88e6xxx_ppu_access_get(ds);
339 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
340 mv88e6xxx_ppu_access_put(ds);
347 void mv88e6xxx_poll_link(struct dsa_switch *ds)
351 for (i = 0; i < DSA_MAX_PORTS; i++) {
352 struct net_device *dev;
353 int uninitialized_var(port_status);
364 if (dev->flags & IFF_UP) {
365 port_status = mv88e6xxx_reg_read(ds, REG_PORT(i), 0x00);
369 link = !!(port_status & 0x0800);
373 if (netif_carrier_ok(dev)) {
374 netdev_info(dev, "link down\n");
375 netif_carrier_off(dev);
380 switch (port_status & 0x0300) {
394 duplex = (port_status & 0x0400) ? 1 : 0;
395 fc = (port_status & 0x8000) ? 1 : 0;
397 if (!netif_carrier_ok(dev)) {
399 "link up, %d Mb/s, %s duplex, flow control %sabled\n",
401 duplex ? "full" : "half",
403 netif_carrier_on(dev);
408 static int mv88e6xxx_stats_wait(struct dsa_switch *ds)
413 for (i = 0; i < 10; i++) {
414 ret = REG_READ(REG_GLOBAL, 0x1d);
415 if ((ret & 0x8000) == 0)
422 static int mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
426 /* Snapshot the hardware statistics counters for this port. */
427 REG_WRITE(REG_GLOBAL, 0x1d, 0xdc00 | port);
429 /* Wait for the snapshotting to complete. */
430 ret = mv88e6xxx_stats_wait(ds);
437 static void mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
444 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x1d, 0xcc00 | stat);
448 ret = mv88e6xxx_stats_wait(ds);
452 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1e);
458 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x1f);
465 void mv88e6xxx_get_strings(struct dsa_switch *ds,
466 int nr_stats, struct mv88e6xxx_hw_stat *stats,
467 int port, uint8_t *data)
471 for (i = 0; i < nr_stats; i++) {
472 memcpy(data + i * ETH_GSTRING_LEN,
473 stats[i].string, ETH_GSTRING_LEN);
477 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
478 int nr_stats, struct mv88e6xxx_hw_stat *stats,
479 int port, uint64_t *data)
481 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
485 mutex_lock(&ps->stats_mutex);
487 ret = mv88e6xxx_stats_snapshot(ds, port);
489 mutex_unlock(&ps->stats_mutex);
493 /* Read each of the counters. */
494 for (i = 0; i < nr_stats; i++) {
495 struct mv88e6xxx_hw_stat *s = stats + i;
499 if (s->reg >= 0x100) {
502 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
507 if (s->sizeof_stat == 4) {
508 ret = mv88e6xxx_reg_read(ds, REG_PORT(port),
514 data[i] = (((u64)high) << 16) | low;
517 mv88e6xxx_stats_read(ds, s->reg, &low);
518 if (s->sizeof_stat == 8)
519 mv88e6xxx_stats_read(ds, s->reg + 1, &high);
521 data[i] = (((u64)high) << 32) | low;
524 mutex_unlock(&ps->stats_mutex);
527 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
529 return 32 * sizeof(u16);
532 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
533 struct ethtool_regs *regs, void *_p)
540 memset(p, 0xff, 32 * sizeof(u16));
542 for (i = 0; i < 32; i++) {
545 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
551 #ifdef CONFIG_NET_DSA_HWMON
553 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
555 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
561 mutex_lock(&ps->phy_mutex);
563 ret = mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
567 /* Enable temperature sensor */
568 ret = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
572 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
576 /* Wait for temperature to stabilize */
577 usleep_range(10000, 12000);
579 val = mv88e6xxx_phy_read(ds, 0x0, 0x1a);
585 /* Disable temperature sensor */
586 ret = mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
590 *temp = ((val & 0x1f) - 5) * 5;
593 mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
594 mutex_unlock(&ps->phy_mutex);
597 #endif /* CONFIG_NET_DSA_HWMON */
599 static int __init mv88e6xxx_init(void)
601 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
602 register_switch_driver(&mv88e6131_switch_driver);
604 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
605 register_switch_driver(&mv88e6123_61_65_switch_driver);
607 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
608 register_switch_driver(&mv88e6352_switch_driver);
610 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
611 register_switch_driver(&mv88e6171_switch_driver);
615 module_init(mv88e6xxx_init);
617 static void __exit mv88e6xxx_cleanup(void)
619 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
620 unregister_switch_driver(&mv88e6171_switch_driver);
622 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
623 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
625 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
626 unregister_switch_driver(&mv88e6131_switch_driver);
629 module_exit(mv88e6xxx_cleanup);
631 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
632 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
633 MODULE_LICENSE("GPL");