2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 static void be_mcc_notify(struct be_adapter *adapter)
23 struct be_queue_info *mccq = &adapter->mcc_obj.q;
26 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
27 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
28 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
31 /* To check if valid bit is set, check the entire word as we don't know
32 * the endianness of the data (old entry is host endian while a new entry is
34 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
36 if (compl->flags != 0) {
37 compl->flags = le32_to_cpu(compl->flags);
38 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
45 /* Need to reset the entire word that houses the valid bit */
46 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
51 static int be_mcc_compl_process(struct be_adapter *adapter,
52 struct be_mcc_compl *compl)
54 u16 compl_status, extd_status;
56 /* Just swap the status to host endian; mcc tag is opaquely copied
58 be_dws_le_to_cpu(compl, 4);
60 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
61 CQE_STATUS_COMPL_MASK;
62 if (compl_status == MCC_STATUS_SUCCESS) {
63 if (compl->tag0 == OPCODE_ETH_GET_STATISTICS) {
64 struct be_cmd_resp_get_stats *resp =
65 adapter->stats.cmd.va;
66 be_dws_le_to_cpu(&resp->hw_stats,
67 sizeof(resp->hw_stats));
68 netdev_stats_update(adapter);
70 } else if (compl_status != MCC_STATUS_NOT_SUPPORTED) {
71 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
73 dev_warn(&adapter->pdev->dev,
74 "Error in cmd completion - opcode %d, compl %d, extd %d\n",
75 compl->tag0, compl_status, extd_status);
80 /* Link state evt is a string of bytes; no need for endian swapping */
81 static void be_async_link_state_process(struct be_adapter *adapter,
82 struct be_async_event_link_state *evt)
84 be_link_status_update(adapter,
85 evt->port_link_status == ASYNC_EVENT_LINK_UP);
88 static inline bool is_link_state_evt(u32 trailer)
90 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
91 ASYNC_TRAILER_EVENT_CODE_MASK) ==
92 ASYNC_EVENT_CODE_LINK_STATE);
95 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
97 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
98 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
100 if (be_mcc_compl_is_new(compl)) {
101 queue_tail_inc(mcc_cq);
107 void be_async_mcc_enable(struct be_adapter *adapter)
109 spin_lock_bh(&adapter->mcc_cq_lock);
111 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
112 adapter->mcc_obj.rearm_cq = true;
114 spin_unlock_bh(&adapter->mcc_cq_lock);
117 void be_async_mcc_disable(struct be_adapter *adapter)
119 adapter->mcc_obj.rearm_cq = false;
122 int be_process_mcc(struct be_adapter *adapter, int *status)
124 struct be_mcc_compl *compl;
126 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
128 spin_lock_bh(&adapter->mcc_cq_lock);
129 while ((compl = be_mcc_compl_get(adapter))) {
130 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
131 /* Interpret flags as an async trailer */
132 BUG_ON(!is_link_state_evt(compl->flags));
134 /* Interpret compl as a async link evt */
135 be_async_link_state_process(adapter,
136 (struct be_async_event_link_state *) compl);
137 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
138 *status = be_mcc_compl_process(adapter, compl);
139 atomic_dec(&mcc_obj->q.used);
141 be_mcc_compl_use(compl);
145 spin_unlock_bh(&adapter->mcc_cq_lock);
149 /* Wait till no more pending mcc requests are present */
150 static int be_mcc_wait_compl(struct be_adapter *adapter)
152 #define mcc_timeout 120000 /* 12s timeout */
153 int i, num, status = 0;
154 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
156 for (i = 0; i < mcc_timeout; i++) {
157 num = be_process_mcc(adapter, &status);
159 be_cq_notify(adapter, mcc_obj->cq.id,
160 mcc_obj->rearm_cq, num);
162 if (atomic_read(&mcc_obj->q.used) == 0)
166 if (i == mcc_timeout) {
167 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
173 /* Notify MCC requests and wait for completion */
174 static int be_mcc_notify_wait(struct be_adapter *adapter)
176 be_mcc_notify(adapter);
177 return be_mcc_wait_compl(adapter);
180 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
182 int cnt = 0, wait = 5;
186 ready = ioread32(db);
187 if (ready == 0xffffffff) {
188 dev_err(&adapter->pdev->dev,
189 "pci slot disconnected\n");
193 ready &= MPU_MAILBOX_DB_RDY_MASK;
198 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
212 * Insert the mailbox address into the doorbell in two steps
213 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
215 static int be_mbox_notify_wait(struct be_adapter *adapter)
219 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
220 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
221 struct be_mcc_mailbox *mbox = mbox_mem->va;
222 struct be_mcc_compl *compl = &mbox->compl;
224 /* wait for ready to be set */
225 status = be_mbox_db_ready_wait(adapter, db);
229 val |= MPU_MAILBOX_DB_HI_MASK;
230 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
231 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
234 /* wait for ready to be set */
235 status = be_mbox_db_ready_wait(adapter, db);
240 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
241 val |= (u32)(mbox_mem->dma >> 4) << 2;
244 status = be_mbox_db_ready_wait(adapter, db);
248 /* A cq entry has been made now */
249 if (be_mcc_compl_is_new(compl)) {
250 status = be_mcc_compl_process(adapter, &mbox->compl);
251 be_mcc_compl_use(compl);
255 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
261 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
263 u32 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
265 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
266 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
272 int be_cmd_POST(struct be_adapter *adapter)
275 int status, timeout = 0;
278 status = be_POST_stage_get(adapter, &stage);
280 dev_err(&adapter->pdev->dev, "POST error; stage=0x%x\n",
283 } else if (stage != POST_STAGE_ARMFW_RDY) {
284 set_current_state(TASK_INTERRUPTIBLE);
285 schedule_timeout(2 * HZ);
290 } while (timeout < 20);
292 dev_err(&adapter->pdev->dev, "POST timeout; stage=0x%x\n", stage);
296 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
298 return wrb->payload.embedded_payload;
301 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
303 return &wrb->payload.sgl[0];
306 /* Don't touch the hdr after it's prepared */
307 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
308 bool embedded, u8 sge_cnt, u32 opcode)
311 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
313 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
314 MCC_WRB_SGE_CNT_SHIFT;
315 wrb->payload_length = payload_len;
317 be_dws_cpu_to_le(wrb, 8);
320 /* Don't touch the hdr after it's prepared */
321 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
322 u8 subsystem, u8 opcode, int cmd_len)
324 req_hdr->opcode = opcode;
325 req_hdr->subsystem = subsystem;
326 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
327 req_hdr->version = 0;
330 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
331 struct be_dma_mem *mem)
333 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
334 u64 dma = (u64)mem->dma;
336 for (i = 0; i < buf_pages; i++) {
337 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
338 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
343 /* Converts interrupt delay in microseconds to multiplier value */
344 static u32 eq_delay_to_mult(u32 usec_delay)
346 #define MAX_INTR_RATE 651042
347 const u32 round = 10;
353 u32 interrupt_rate = 1000000 / usec_delay;
354 /* Max delay, corresponding to the lowest interrupt rate */
355 if (interrupt_rate == 0)
358 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
359 multiplier /= interrupt_rate;
360 /* Round the multiplier to the closest value.*/
361 multiplier = (multiplier + round/2) / round;
362 multiplier = min(multiplier, (u32)1023);
368 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
370 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
371 struct be_mcc_wrb *wrb
372 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
373 memset(wrb, 0, sizeof(*wrb));
377 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
379 struct be_queue_info *mccq = &adapter->mcc_obj.q;
380 struct be_mcc_wrb *wrb;
382 if (atomic_read(&mccq->used) >= mccq->len) {
383 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
387 wrb = queue_head_node(mccq);
388 queue_head_inc(mccq);
389 atomic_inc(&mccq->used);
390 memset(wrb, 0, sizeof(*wrb));
394 /* Tell fw we're about to start firing cmds by writing a
395 * special pattern across the wrb hdr; uses mbox
397 int be_cmd_fw_init(struct be_adapter *adapter)
402 spin_lock(&adapter->mbox_lock);
404 wrb = (u8 *)wrb_from_mbox(adapter);
414 status = be_mbox_notify_wait(adapter);
416 spin_unlock(&adapter->mbox_lock);
420 /* Tell fw we're done with firing cmds by writing a
421 * special pattern across the wrb hdr; uses mbox
423 int be_cmd_fw_clean(struct be_adapter *adapter)
428 if (adapter->eeh_err)
431 spin_lock(&adapter->mbox_lock);
433 wrb = (u8 *)wrb_from_mbox(adapter);
443 status = be_mbox_notify_wait(adapter);
445 spin_unlock(&adapter->mbox_lock);
448 int be_cmd_eq_create(struct be_adapter *adapter,
449 struct be_queue_info *eq, int eq_delay)
451 struct be_mcc_wrb *wrb;
452 struct be_cmd_req_eq_create *req;
453 struct be_dma_mem *q_mem = &eq->dma_mem;
456 spin_lock(&adapter->mbox_lock);
458 wrb = wrb_from_mbox(adapter);
459 req = embedded_payload(wrb);
461 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
463 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
464 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
466 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
468 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
470 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
471 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
472 __ilog2_u32(eq->len/256));
473 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
474 eq_delay_to_mult(eq_delay));
475 be_dws_cpu_to_le(req->context, sizeof(req->context));
477 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
479 status = be_mbox_notify_wait(adapter);
481 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
482 eq->id = le16_to_cpu(resp->eq_id);
486 spin_unlock(&adapter->mbox_lock);
491 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
492 u8 type, bool permanent, u32 if_handle)
494 struct be_mcc_wrb *wrb;
495 struct be_cmd_req_mac_query *req;
498 spin_lock(&adapter->mbox_lock);
500 wrb = wrb_from_mbox(adapter);
501 req = embedded_payload(wrb);
503 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
504 OPCODE_COMMON_NTWK_MAC_QUERY);
506 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
507 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
513 req->if_id = cpu_to_le16((u16) if_handle);
517 status = be_mbox_notify_wait(adapter);
519 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
520 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
523 spin_unlock(&adapter->mbox_lock);
527 /* Uses synchronous MCCQ */
528 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
529 u32 if_id, u32 *pmac_id)
531 struct be_mcc_wrb *wrb;
532 struct be_cmd_req_pmac_add *req;
535 spin_lock_bh(&adapter->mcc_lock);
537 wrb = wrb_from_mccq(adapter);
542 req = embedded_payload(wrb);
544 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
545 OPCODE_COMMON_NTWK_PMAC_ADD);
547 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
548 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
550 req->if_id = cpu_to_le32(if_id);
551 memcpy(req->mac_address, mac_addr, ETH_ALEN);
553 status = be_mcc_notify_wait(adapter);
555 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
556 *pmac_id = le32_to_cpu(resp->pmac_id);
560 spin_unlock_bh(&adapter->mcc_lock);
564 /* Uses synchronous MCCQ */
565 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id)
567 struct be_mcc_wrb *wrb;
568 struct be_cmd_req_pmac_del *req;
571 spin_lock_bh(&adapter->mcc_lock);
573 wrb = wrb_from_mccq(adapter);
578 req = embedded_payload(wrb);
580 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
581 OPCODE_COMMON_NTWK_PMAC_DEL);
583 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
584 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
586 req->if_id = cpu_to_le32(if_id);
587 req->pmac_id = cpu_to_le32(pmac_id);
589 status = be_mcc_notify_wait(adapter);
592 spin_unlock_bh(&adapter->mcc_lock);
597 int be_cmd_cq_create(struct be_adapter *adapter,
598 struct be_queue_info *cq, struct be_queue_info *eq,
599 bool sol_evts, bool no_delay, int coalesce_wm)
601 struct be_mcc_wrb *wrb;
602 struct be_cmd_req_cq_create *req;
603 struct be_dma_mem *q_mem = &cq->dma_mem;
607 spin_lock(&adapter->mbox_lock);
609 wrb = wrb_from_mbox(adapter);
610 req = embedded_payload(wrb);
611 ctxt = &req->context;
613 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
614 OPCODE_COMMON_CQ_CREATE);
616 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
617 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
619 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
621 AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm);
622 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
623 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
624 __ilog2_u32(cq->len/256));
625 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
626 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
627 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
628 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
629 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
630 be_dws_cpu_to_le(ctxt, sizeof(req->context));
632 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
634 status = be_mbox_notify_wait(adapter);
636 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
637 cq->id = le16_to_cpu(resp->cq_id);
641 spin_unlock(&adapter->mbox_lock);
646 static u32 be_encoded_q_len(int q_len)
648 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
649 if (len_encoded == 16)
654 int be_cmd_mccq_create(struct be_adapter *adapter,
655 struct be_queue_info *mccq,
656 struct be_queue_info *cq)
658 struct be_mcc_wrb *wrb;
659 struct be_cmd_req_mcc_create *req;
660 struct be_dma_mem *q_mem = &mccq->dma_mem;
664 spin_lock(&adapter->mbox_lock);
666 wrb = wrb_from_mbox(adapter);
667 req = embedded_payload(wrb);
668 ctxt = &req->context;
670 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
671 OPCODE_COMMON_MCC_CREATE);
673 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
674 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
676 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
678 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
679 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
680 be_encoded_q_len(mccq->len));
681 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
683 be_dws_cpu_to_le(ctxt, sizeof(req->context));
685 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
687 status = be_mbox_notify_wait(adapter);
689 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
690 mccq->id = le16_to_cpu(resp->id);
691 mccq->created = true;
693 spin_unlock(&adapter->mbox_lock);
698 int be_cmd_txq_create(struct be_adapter *adapter,
699 struct be_queue_info *txq,
700 struct be_queue_info *cq)
702 struct be_mcc_wrb *wrb;
703 struct be_cmd_req_eth_tx_create *req;
704 struct be_dma_mem *q_mem = &txq->dma_mem;
708 spin_lock(&adapter->mbox_lock);
710 wrb = wrb_from_mbox(adapter);
711 req = embedded_payload(wrb);
712 ctxt = &req->context;
714 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
715 OPCODE_ETH_TX_CREATE);
717 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
720 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
721 req->ulp_num = BE_ULP1_NUM;
722 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
724 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
725 be_encoded_q_len(txq->len));
726 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
727 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
729 be_dws_cpu_to_le(ctxt, sizeof(req->context));
731 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
733 status = be_mbox_notify_wait(adapter);
735 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
736 txq->id = le16_to_cpu(resp->cid);
740 spin_unlock(&adapter->mbox_lock);
746 int be_cmd_rxq_create(struct be_adapter *adapter,
747 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
748 u16 max_frame_size, u32 if_id, u32 rss)
750 struct be_mcc_wrb *wrb;
751 struct be_cmd_req_eth_rx_create *req;
752 struct be_dma_mem *q_mem = &rxq->dma_mem;
755 spin_lock(&adapter->mbox_lock);
757 wrb = wrb_from_mbox(adapter);
758 req = embedded_payload(wrb);
760 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
761 OPCODE_ETH_RX_CREATE);
763 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
766 req->cq_id = cpu_to_le16(cq_id);
767 req->frag_size = fls(frag_size) - 1;
769 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
770 req->interface_id = cpu_to_le32(if_id);
771 req->max_frame_size = cpu_to_le16(max_frame_size);
772 req->rss_queue = cpu_to_le32(rss);
774 status = be_mbox_notify_wait(adapter);
776 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
777 rxq->id = le16_to_cpu(resp->id);
781 spin_unlock(&adapter->mbox_lock);
786 /* Generic destroyer function for all types of queues
789 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
792 struct be_mcc_wrb *wrb;
793 struct be_cmd_req_q_destroy *req;
794 u8 subsys = 0, opcode = 0;
797 if (adapter->eeh_err)
800 spin_lock(&adapter->mbox_lock);
802 wrb = wrb_from_mbox(adapter);
803 req = embedded_payload(wrb);
805 switch (queue_type) {
807 subsys = CMD_SUBSYSTEM_COMMON;
808 opcode = OPCODE_COMMON_EQ_DESTROY;
811 subsys = CMD_SUBSYSTEM_COMMON;
812 opcode = OPCODE_COMMON_CQ_DESTROY;
815 subsys = CMD_SUBSYSTEM_ETH;
816 opcode = OPCODE_ETH_TX_DESTROY;
819 subsys = CMD_SUBSYSTEM_ETH;
820 opcode = OPCODE_ETH_RX_DESTROY;
823 subsys = CMD_SUBSYSTEM_COMMON;
824 opcode = OPCODE_COMMON_MCC_DESTROY;
830 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
832 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
833 req->id = cpu_to_le16(q->id);
835 status = be_mbox_notify_wait(adapter);
837 spin_unlock(&adapter->mbox_lock);
842 /* Create an rx filtering policy configuration on an i/f
845 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
846 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
849 struct be_mcc_wrb *wrb;
850 struct be_cmd_req_if_create *req;
853 spin_lock(&adapter->mbox_lock);
855 wrb = wrb_from_mbox(adapter);
856 req = embedded_payload(wrb);
858 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
859 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
861 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
862 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
864 req->hdr.domain = domain;
865 req->capability_flags = cpu_to_le32(cap_flags);
866 req->enable_flags = cpu_to_le32(en_flags);
867 req->pmac_invalid = pmac_invalid;
869 memcpy(req->mac_addr, mac, ETH_ALEN);
871 status = be_mbox_notify_wait(adapter);
873 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
874 *if_handle = le32_to_cpu(resp->interface_id);
876 *pmac_id = le32_to_cpu(resp->pmac_id);
879 spin_unlock(&adapter->mbox_lock);
884 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id)
886 struct be_mcc_wrb *wrb;
887 struct be_cmd_req_if_destroy *req;
890 if (adapter->eeh_err)
893 spin_lock(&adapter->mbox_lock);
895 wrb = wrb_from_mbox(adapter);
896 req = embedded_payload(wrb);
898 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
899 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
901 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
902 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
904 req->interface_id = cpu_to_le32(interface_id);
906 status = be_mbox_notify_wait(adapter);
908 spin_unlock(&adapter->mbox_lock);
913 /* Get stats is a non embedded command: the request is not embedded inside
914 * WRB but is a separate dma memory block
915 * Uses asynchronous MCC
917 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
919 struct be_mcc_wrb *wrb;
920 struct be_cmd_req_get_stats *req;
924 spin_lock_bh(&adapter->mcc_lock);
926 wrb = wrb_from_mccq(adapter);
931 req = nonemb_cmd->va;
932 sge = nonembedded_sgl(wrb);
934 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
935 OPCODE_ETH_GET_STATISTICS);
937 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
938 OPCODE_ETH_GET_STATISTICS, sizeof(*req));
939 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
940 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
941 sge->len = cpu_to_le32(nonemb_cmd->size);
943 be_mcc_notify(adapter);
946 spin_unlock_bh(&adapter->mcc_lock);
950 /* Uses synchronous mcc */
951 int be_cmd_link_status_query(struct be_adapter *adapter,
952 bool *link_up, u8 *mac_speed, u16 *link_speed)
954 struct be_mcc_wrb *wrb;
955 struct be_cmd_req_link_status *req;
958 spin_lock_bh(&adapter->mcc_lock);
960 wrb = wrb_from_mccq(adapter);
965 req = embedded_payload(wrb);
969 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
970 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
972 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
973 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
975 status = be_mcc_notify_wait(adapter);
977 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
978 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
980 *link_speed = le16_to_cpu(resp->link_speed);
981 *mac_speed = resp->mac_speed;
986 spin_unlock_bh(&adapter->mcc_lock);
991 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver)
993 struct be_mcc_wrb *wrb;
994 struct be_cmd_req_get_fw_version *req;
997 spin_lock(&adapter->mbox_lock);
999 wrb = wrb_from_mbox(adapter);
1000 req = embedded_payload(wrb);
1002 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1003 OPCODE_COMMON_GET_FW_VERSION);
1005 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1006 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1008 status = be_mbox_notify_wait(adapter);
1010 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1011 strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN);
1014 spin_unlock(&adapter->mbox_lock);
1018 /* set the EQ delay interval of an EQ to specified value
1021 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1023 struct be_mcc_wrb *wrb;
1024 struct be_cmd_req_modify_eq_delay *req;
1027 spin_lock_bh(&adapter->mcc_lock);
1029 wrb = wrb_from_mccq(adapter);
1034 req = embedded_payload(wrb);
1036 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1037 OPCODE_COMMON_MODIFY_EQ_DELAY);
1039 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1040 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1042 req->num_eq = cpu_to_le32(1);
1043 req->delay[0].eq_id = cpu_to_le32(eq_id);
1044 req->delay[0].phase = 0;
1045 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1047 be_mcc_notify(adapter);
1050 spin_unlock_bh(&adapter->mcc_lock);
1054 /* Uses sycnhronous mcc */
1055 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1056 u32 num, bool untagged, bool promiscuous)
1058 struct be_mcc_wrb *wrb;
1059 struct be_cmd_req_vlan_config *req;
1062 spin_lock_bh(&adapter->mcc_lock);
1064 wrb = wrb_from_mccq(adapter);
1069 req = embedded_payload(wrb);
1071 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1072 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1074 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1075 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1077 req->interface_id = if_id;
1078 req->promiscuous = promiscuous;
1079 req->untagged = untagged;
1080 req->num_vlan = num;
1082 memcpy(req->normal_vlan, vtag_array,
1083 req->num_vlan * sizeof(vtag_array[0]));
1086 status = be_mcc_notify_wait(adapter);
1089 spin_unlock_bh(&adapter->mcc_lock);
1093 /* Uses MCC for this command as it may be called in BH context
1094 * Uses synchronous mcc
1096 int be_cmd_promiscuous_config(struct be_adapter *adapter, u8 port_num, bool en)
1098 struct be_mcc_wrb *wrb;
1099 struct be_cmd_req_promiscuous_config *req;
1102 spin_lock_bh(&adapter->mcc_lock);
1104 wrb = wrb_from_mccq(adapter);
1109 req = embedded_payload(wrb);
1111 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_PROMISCUOUS);
1113 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1114 OPCODE_ETH_PROMISCUOUS, sizeof(*req));
1117 req->port1_promiscuous = en;
1119 req->port0_promiscuous = en;
1121 status = be_mcc_notify_wait(adapter);
1124 spin_unlock_bh(&adapter->mcc_lock);
1129 * Uses MCC for this command as it may be called in BH context
1130 * (mc == NULL) => multicast promiscous
1132 int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
1133 struct net_device *netdev, struct be_dma_mem *mem)
1135 struct be_mcc_wrb *wrb;
1136 struct be_cmd_req_mcast_mac_config *req = mem->va;
1140 spin_lock_bh(&adapter->mcc_lock);
1142 wrb = wrb_from_mccq(adapter);
1147 sge = nonembedded_sgl(wrb);
1148 memset(req, 0, sizeof(*req));
1150 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1151 OPCODE_COMMON_NTWK_MULTICAST_SET);
1152 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1153 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1154 sge->len = cpu_to_le32(mem->size);
1156 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1157 OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req));
1159 req->interface_id = if_id;
1162 struct netdev_hw_addr *ha;
1164 req->num_mac = cpu_to_le16(netdev_mc_count(netdev));
1167 netdev_for_each_mc_addr(ha, netdev)
1168 memcpy(req->mac[i].byte, ha->addr, ETH_ALEN);
1170 req->promiscuous = 1;
1173 status = be_mcc_notify_wait(adapter);
1176 spin_unlock_bh(&adapter->mcc_lock);
1180 /* Uses synchrounous mcc */
1181 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1183 struct be_mcc_wrb *wrb;
1184 struct be_cmd_req_set_flow_control *req;
1187 spin_lock_bh(&adapter->mcc_lock);
1189 wrb = wrb_from_mccq(adapter);
1194 req = embedded_payload(wrb);
1196 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1197 OPCODE_COMMON_SET_FLOW_CONTROL);
1199 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1200 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1202 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1203 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1205 status = be_mcc_notify_wait(adapter);
1208 spin_unlock_bh(&adapter->mcc_lock);
1213 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1215 struct be_mcc_wrb *wrb;
1216 struct be_cmd_req_get_flow_control *req;
1219 spin_lock_bh(&adapter->mcc_lock);
1221 wrb = wrb_from_mccq(adapter);
1226 req = embedded_payload(wrb);
1228 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1229 OPCODE_COMMON_GET_FLOW_CONTROL);
1231 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1232 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1234 status = be_mcc_notify_wait(adapter);
1236 struct be_cmd_resp_get_flow_control *resp =
1237 embedded_payload(wrb);
1238 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1239 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1243 spin_unlock_bh(&adapter->mcc_lock);
1248 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num, u32 *cap)
1250 struct be_mcc_wrb *wrb;
1251 struct be_cmd_req_query_fw_cfg *req;
1254 spin_lock(&adapter->mbox_lock);
1256 wrb = wrb_from_mbox(adapter);
1257 req = embedded_payload(wrb);
1259 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1260 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1262 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1263 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1265 status = be_mbox_notify_wait(adapter);
1267 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1268 *port_num = le32_to_cpu(resp->phys_port);
1269 *cap = le32_to_cpu(resp->function_cap);
1272 spin_unlock(&adapter->mbox_lock);
1277 int be_cmd_reset_function(struct be_adapter *adapter)
1279 struct be_mcc_wrb *wrb;
1280 struct be_cmd_req_hdr *req;
1283 spin_lock(&adapter->mbox_lock);
1285 wrb = wrb_from_mbox(adapter);
1286 req = embedded_payload(wrb);
1288 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1289 OPCODE_COMMON_FUNCTION_RESET);
1291 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1292 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1294 status = be_mbox_notify_wait(adapter);
1296 spin_unlock(&adapter->mbox_lock);
1301 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1302 u8 bcn, u8 sts, u8 state)
1304 struct be_mcc_wrb *wrb;
1305 struct be_cmd_req_enable_disable_beacon *req;
1308 spin_lock_bh(&adapter->mcc_lock);
1310 wrb = wrb_from_mccq(adapter);
1315 req = embedded_payload(wrb);
1317 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1318 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1320 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1321 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1323 req->port_num = port_num;
1324 req->beacon_state = state;
1325 req->beacon_duration = bcn;
1326 req->status_duration = sts;
1328 status = be_mcc_notify_wait(adapter);
1331 spin_unlock_bh(&adapter->mcc_lock);
1336 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1338 struct be_mcc_wrb *wrb;
1339 struct be_cmd_req_get_beacon_state *req;
1342 spin_lock_bh(&adapter->mcc_lock);
1344 wrb = wrb_from_mccq(adapter);
1349 req = embedded_payload(wrb);
1351 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1352 OPCODE_COMMON_GET_BEACON_STATE);
1354 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1355 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1357 req->port_num = port_num;
1359 status = be_mcc_notify_wait(adapter);
1361 struct be_cmd_resp_get_beacon_state *resp =
1362 embedded_payload(wrb);
1363 *state = resp->beacon_state;
1367 spin_unlock_bh(&adapter->mcc_lock);
1372 int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
1375 struct be_mcc_wrb *wrb;
1376 struct be_cmd_req_port_type *req;
1379 spin_lock_bh(&adapter->mcc_lock);
1381 wrb = wrb_from_mccq(adapter);
1386 req = embedded_payload(wrb);
1388 be_wrb_hdr_prepare(wrb, sizeof(struct be_cmd_resp_port_type), true, 0,
1389 OPCODE_COMMON_READ_TRANSRECV_DATA);
1391 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1392 OPCODE_COMMON_READ_TRANSRECV_DATA, sizeof(*req));
1394 req->port = cpu_to_le32(port);
1395 req->page_num = cpu_to_le32(TR_PAGE_A0);
1396 status = be_mcc_notify_wait(adapter);
1398 struct be_cmd_resp_port_type *resp = embedded_payload(wrb);
1399 *connector = resp->data.connector;
1403 spin_unlock_bh(&adapter->mcc_lock);
1407 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1408 u32 flash_type, u32 flash_opcode, u32 buf_size)
1410 struct be_mcc_wrb *wrb;
1411 struct be_cmd_write_flashrom *req;
1415 spin_lock_bh(&adapter->mcc_lock);
1417 wrb = wrb_from_mccq(adapter);
1423 sge = nonembedded_sgl(wrb);
1425 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1426 OPCODE_COMMON_WRITE_FLASHROM);
1428 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1429 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1430 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1431 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1432 sge->len = cpu_to_le32(cmd->size);
1434 req->params.op_type = cpu_to_le32(flash_type);
1435 req->params.op_code = cpu_to_le32(flash_opcode);
1436 req->params.data_buf_size = cpu_to_le32(buf_size);
1438 status = be_mcc_notify_wait(adapter);
1441 spin_unlock_bh(&adapter->mcc_lock);
1445 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1448 struct be_mcc_wrb *wrb;
1449 struct be_cmd_write_flashrom *req;
1452 spin_lock_bh(&adapter->mcc_lock);
1454 wrb = wrb_from_mccq(adapter);
1459 req = embedded_payload(wrb);
1461 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1462 OPCODE_COMMON_READ_FLASHROM);
1464 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1465 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1467 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1468 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1469 req->params.offset = cpu_to_le32(offset);
1470 req->params.data_buf_size = cpu_to_le32(0x4);
1472 status = be_mcc_notify_wait(adapter);
1474 memcpy(flashed_crc, req->params.data_buf, 4);
1477 spin_unlock_bh(&adapter->mcc_lock);
1481 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
1482 struct be_dma_mem *nonemb_cmd)
1484 struct be_mcc_wrb *wrb;
1485 struct be_cmd_req_acpi_wol_magic_config *req;
1489 spin_lock_bh(&adapter->mcc_lock);
1491 wrb = wrb_from_mccq(adapter);
1496 req = nonemb_cmd->va;
1497 sge = nonembedded_sgl(wrb);
1499 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1500 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
1502 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1503 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
1504 memcpy(req->magic_mac, mac, ETH_ALEN);
1506 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1507 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1508 sge->len = cpu_to_le32(nonemb_cmd->size);
1510 status = be_mcc_notify_wait(adapter);
1513 spin_unlock_bh(&adapter->mcc_lock);
1517 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
1518 u8 loopback_type, u8 enable)
1520 struct be_mcc_wrb *wrb;
1521 struct be_cmd_req_set_lmode *req;
1524 spin_lock_bh(&adapter->mcc_lock);
1526 wrb = wrb_from_mccq(adapter);
1532 req = embedded_payload(wrb);
1534 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1535 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
1537 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1538 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
1541 req->src_port = port_num;
1542 req->dest_port = port_num;
1543 req->loopback_type = loopback_type;
1544 req->loopback_state = enable;
1546 status = be_mcc_notify_wait(adapter);
1548 spin_unlock_bh(&adapter->mcc_lock);
1552 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
1553 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
1555 struct be_mcc_wrb *wrb;
1556 struct be_cmd_req_loopback_test *req;
1559 spin_lock_bh(&adapter->mcc_lock);
1561 wrb = wrb_from_mccq(adapter);
1567 req = embedded_payload(wrb);
1569 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1570 OPCODE_LOWLEVEL_LOOPBACK_TEST);
1572 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1573 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
1574 req->hdr.timeout = 4;
1576 req->pattern = cpu_to_le64(pattern);
1577 req->src_port = cpu_to_le32(port_num);
1578 req->dest_port = cpu_to_le32(port_num);
1579 req->pkt_size = cpu_to_le32(pkt_size);
1580 req->num_pkts = cpu_to_le32(num_pkts);
1581 req->loopback_type = cpu_to_le32(loopback_type);
1583 status = be_mcc_notify_wait(adapter);
1585 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
1586 status = le32_to_cpu(resp->status);
1590 spin_unlock_bh(&adapter->mcc_lock);
1594 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
1595 u32 byte_cnt, struct be_dma_mem *cmd)
1597 struct be_mcc_wrb *wrb;
1598 struct be_cmd_req_ddrdma_test *req;
1603 spin_lock_bh(&adapter->mcc_lock);
1605 wrb = wrb_from_mccq(adapter);
1611 sge = nonembedded_sgl(wrb);
1612 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1613 OPCODE_LOWLEVEL_HOST_DDR_DMA);
1614 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
1615 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
1617 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1618 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1619 sge->len = cpu_to_le32(cmd->size);
1621 req->pattern = cpu_to_le64(pattern);
1622 req->byte_count = cpu_to_le32(byte_cnt);
1623 for (i = 0; i < byte_cnt; i++) {
1624 req->snd_buff[i] = (u8)(pattern >> (j*8));
1630 status = be_mcc_notify_wait(adapter);
1633 struct be_cmd_resp_ddrdma_test *resp;
1635 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
1642 spin_unlock_bh(&adapter->mcc_lock);
1646 extern int be_cmd_get_seeprom_data(struct be_adapter *adapter,
1647 struct be_dma_mem *nonemb_cmd)
1649 struct be_mcc_wrb *wrb;
1650 struct be_cmd_req_seeprom_read *req;
1654 spin_lock_bh(&adapter->mcc_lock);
1656 wrb = wrb_from_mccq(adapter);
1657 req = nonemb_cmd->va;
1658 sge = nonembedded_sgl(wrb);
1660 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1661 OPCODE_COMMON_SEEPROM_READ);
1663 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1664 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
1666 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1667 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1668 sge->len = cpu_to_le32(nonemb_cmd->size);
1670 status = be_mcc_notify_wait(adapter);
1672 spin_unlock_bh(&adapter->mcc_lock);