2 ** $Id: //Department/DaVinci/BRANCHES/MT6620_WIFI_DRIVER_V2_3/include/nic/mt6620_reg.h#1 $
5 /*! \file "mt6620_reg.h"
6 \brief The common register definition of mt6620
14 ** $Log: mt6620_reg.h $
17 * [WCXRP00000412] [MT6620 Wi-Fi][FW/Driver] Dump firmware assert info at android kernel log
18 * Print firmware ASSERT info at Android kernel log, driver side
22 * [WPD00003833] [MT6620 and MT5931] Driver migration - move to new repository.
24 * 06 06 2010 kevin.huang
25 * [WPD00003832][MT6620 5931] Create driver base
26 * [MT6620 5931] Create driver base
29 * [WPD00001943]Create WiFi test driver framework on WinXP
30 * 1) add ACPI D0/D3 state switching support
31 * * * * 2) use more formal way to handle interrupt when the status is retrieved from enhanced RX response
32 ** \main\maintrunk.MT6620WiFiDriver_Prj\15 2009-12-10 16:44:18 GMT mtk02752
33 ** remove 5921 definitions
34 ** \main\maintrunk.MT6620WiFiDriver_Prj\14 2009-11-09 22:56:32 GMT mtk01084
35 ** modify HW register definitions
36 ** \main\maintrunk.MT6620WiFiDriver_Prj\13 2009-11-04 14:11:04 GMT mtk01084
37 ** modify default IER bits
38 ** \main\maintrunk.MT6620WiFiDriver_Prj\12 2009-10-29 19:52:32 GMT mtk01084
39 ** modify data struture
40 ** \main\maintrunk.MT6620WiFiDriver_Prj\11 2009-10-23 16:08:20 GMT mtk01084
41 ** \main\maintrunk.MT6620WiFiDriver_Prj\10 2009-10-13 21:58:53 GMT mtk01084
42 ** update for new HW architecture design
43 ** \main\maintrunk.MT6620WiFiDriver_Prj\9 2009-09-09 17:26:11 GMT mtk01084
44 ** add CFG_TEST_WITH_MT5921
45 ** \main\maintrunk.MT6620WiFiDriver_Prj\8 2009-05-18 20:59:57 GMT mtk01426
46 ** Update WHIER_DEFAULT value
47 ** \main\maintrunk.MT6620WiFiDriver_Prj\7 2009-05-07 16:57:36 GMT mtk01426
48 ** Update CHIP ID to 0x6620, and WHLPCR bit definition
49 ** \main\maintrunk.MT6620WiFiDriver_Prj\6 2009-04-28 10:34:57 GMT mtk01461
50 ** Add read WTSR and fix RX STATUS is DW align for SDIO_STATUS_ENHANCE mode
51 ** \main\maintrunk.MT6620WiFiDriver_Prj\5 2009-03-24 09:46:52 GMT mtk01084
53 ** \main\maintrunk.MT6620WiFiDriver_Prj\4 2009-03-23 00:32:24 GMT mtk01461
54 ** Define constants for TX PATH
55 ** \main\maintrunk.MT6620WiFiDriver_Prj\3 2009-03-18 20:54:10 GMT mtk01426
56 ** Add WHCR_MAX_HIF_RX_AGG_LEN_OFFSET definition
57 ** \main\maintrunk.MT6620WiFiDriver_Prj\2 2009-03-10 20:16:29 GMT mtk01426
65 /*******************************************************************************
66 * C O M P I L E R F L A G S
67 ********************************************************************************
70 /*******************************************************************************
71 * E X T E R N A L R E F E R E N C E S
72 ********************************************************************************
75 /*******************************************************************************
77 ********************************************************************************
80 /*******************************************************************************
82 ********************************************************************************
86 /*******************************************************************************
88 ********************************************************************************
91 /*******************************************************************************
92 * P R I V A T E D A T A
93 ********************************************************************************
96 /*******************************************************************************
98 ********************************************************************************
101 /*******************************************************************************
102 * F U N C T I O N D E C L A R A T I O N S
103 ********************************************************************************
106 /*******************************************************************************
108 ********************************************************************************
111 //1 MT6620 MCR Definition
116 #define MCR_WCIR 0x0000
118 //4 HIF Low Power Control Register
119 #define MCR_WHLPCR 0x0004
120 //#define MCR_WHLPCR_BYTE1 0x0005
123 //4 Control Status Register
124 #define MCR_WSDIOCSR 0x0008
125 #define MCR_WSPICSR 0x0008
127 //4 HIF Control Register
128 #define MCR_WHCR 0x000C
130 //4 HIF Interrupt Status Register
131 #define MCR_WHISR 0x0010
133 //4 HIF Interrupt Enable Register
134 #define MCR_WHIER 0x0014
136 //4 Abnormal Status Register
137 #define MCR_WASR 0x0018
139 //4 WLAN Software Interrupt Control Register
140 #define MCR_WSICR 0x001C
142 //4 WLAN TX Status Register
143 #define MCR_WTSR0 0x0020
145 //4 WLAN TX Status Register
146 #define MCR_WTSR1 0x0024
148 //4 WLAN TX Data Register 0
149 #define MCR_WTDR0 0x0028
151 //4 WLAN TX Data Register 1
152 #define MCR_WTDR1 0x002C
154 //4 WLAN RX Data Register 0
155 #define MCR_WRDR0 0x0030
157 //4 WLAN RX Data Register 1
158 #define MCR_WRDR1 0x0034
160 //4 Host to Device Send Mailbox 0 Register
161 #define MCR_H2DSM0R 0x0038
163 //4 Host to Device Send Mailbox 1 Register
164 #define MCR_H2DSM1R 0x003c
166 //4 Device to Host Receive Mailbox 0 Register
167 #define MCR_D2HRM0R 0x0040
169 //4 Device to Host Receive Mailbox 1 Register
170 #define MCR_D2HRM1R 0x0044
172 //4 WLAN RX Packet Length Register
173 #define MCR_WRPLR 0x0048
178 //temp //#if CFG_SDIO_INTR_ENHANCE
179 typedef struct _ENHANCE_MODE_DATA_STRUCT_T {
195 UINT_16 u2NumValidRx0Len;
196 UINT_16 u2NumValidRx1Len;
197 UINT_16 au2Rx0Len[16];
198 UINT_16 au2Rx1Len[16];
200 UINT_32 au4RxStatusRaw[17];
202 UINT_32 u4RcvMailbox0;
203 UINT_32 u4RcvMailbox1;
204 } ENHANCE_MODE_DATA_STRUCT_T, *P_ENHANCE_MODE_DATA_STRUCT_T;
205 // #endif /* ENHANCE_MODE_DATA_STRUCT_T */
208 //2 Definition in each register
210 #define WCIR_WLAN_READY BIT(21)
211 #define WCIR_POR_INDICATOR BIT(20)
212 #define WCIR_REVISION_ID BITS(16,19)
213 #define WCIR_CHIP_ID BITS(0,15)
215 #define MTK_CHIP_REV 0x00006620
216 #define MTK_CHIP_MP_REVERSION_ID 0x0
219 #define WHLPCR_FW_OWN_REQ_CLR BIT(9)
220 #define WHLPCR_FW_OWN_REQ_SET BIT(8)
221 #define WHLPCR_IS_DRIVER_OWN BIT(8)
222 #define WHLPCR_INT_EN_CLR BIT(1)
223 #define WHLPCR_INT_EN_SET BIT(0)
226 #define WSDIOCSR_SDIO_RE_INIT_EN BIT(0)
229 #define WCSR_SPI_MODE_SEL BITS(3,4)
230 #define WCSR_SPI_ENDIAN_BIG BIT(2)
231 #define WCSR_SPI_INT_OUT_MODE BIT(1)
232 #define WCSR_SPI_DATA_OUT_MODE BIT(0)
235 #define WHCR_RX_ENHANCE_MODE_EN BIT(16)
236 #define WHCR_MAX_HIF_RX_LEN_NUM BITS(4,7)
237 #define WHCR_W_MAILBOX_RD_CLR_EN BIT(2)
238 #define WHCR_W_INT_CLR_CTRL BIT(1)
239 #define WHCR_MCU_DBG_EN BIT(0)
240 #define WHCR_OFFSET_MAX_HIF_RX_LEN_NUM 4
243 #define WHISR_D2H_SW_INT BITS(8,31)
244 #define WHISR_D2H_SW_ASSERT_INFO_INT BIT(31)
245 #define WHISR_FW_INT_INDICATOR BIT(7)
246 #define WHISR_FW_OWN_BACK_INT BIT(4)
247 #define WHISR_ABNORMAL_INT BIT(3)
248 #define WHISR_RX1_DONE_INT BIT(2)
249 #define WHISR_RX0_DONE_INT BIT(1)
250 #define WHISR_TX_DONE_INT BIT(0)
254 #define WHIER_D2H_SW_INT BITS(8,31)
255 #define WHIER_FW_INT_INDICATOR_EN BIT(7)
256 #define WHIER_FW_OWN_BACK_INT_EN BIT(4)
257 #define WHIER_ABNORMAL_INT_EN BIT(3)
258 #define WHIER_RX1_DONE_INT_EN BIT(2)
259 #define WHIER_RX0_DONE_INT_EN BIT(1)
260 #define WHIER_TX_DONE_INT_EN BIT(0)
261 #define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \
262 WHIER_RX1_DONE_INT_EN | \
263 WHIER_TX_DONE_INT_EN | \
264 WHIER_ABNORMAL_INT_EN | \
270 #define WASR_FW_OWN_INVALID_ACCESS BIT(4)
271 #define WASR_RX1_UNDER_FLOW BIT(3)
272 #define WASR_RX0_UNDER_FLOW BIT(2)
273 #define WASR_TX1_OVER_FLOW BIT(1)
274 #define WASR_TX0_OVER_FLOW BIT(0)
278 #define WSICR_H2D_SW_INT_SET BITS(16,31)
282 #define WRPLR_RX1_PACKET_LENGTH BITS(16,31)
283 #define WRPLR_RX0_PACKET_LENGTH BITS(0,15)
285 #endif /* _MT6620_REG_H */