1 /* Copyright Statement:
3 * This software/firmware and related documentation ("MediaTek Software") are
4 * protected under relevant copyright laws. The information contained herein
5 * is confidential and proprietary to MediaTek Inc. and/or its licensors.
6 * Without the prior written permission of MediaTek inc. and/or its licensors,
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13 * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
14 * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
15 * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
18 * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
19 * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
20 * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
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24 * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
25 * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
26 * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
27 * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
28 * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
29 * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
31 * The following software/firmware and/or related documentation ("MediaTek Software")
32 * have been modified by MediaTek Inc. All revisions are subject to any receiver's
33 * applicable license agreements with MediaTek Inc.
38 \brief Declaration of library functions
40 Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
43 /*******************************************************************************
44 * Copyright (c) 2009 MediaTek Inc.
46 * All rights reserved. Copying, compilation, modification, distribution
47 * or any other use whatsoever of this material is strictly prohibited
48 * except in accordance with a Software License Agreement with
50 ********************************************************************************
53 /*******************************************************************************
56 * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND
57 * AGREES THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK
58 * SOFTWARE") RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE
59 * PROVIDED TO BUYER ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY
60 * DISCLAIMS ANY AND ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT
61 * LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
62 * PARTICULAR PURPOSE OR NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE
63 * ANY WARRANTY WHATSOEVER WITH RESPECT TO THE SOFTWARE OF ANY THIRD PARTY
64 * WHICH MAY BE USED BY, INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK
65 * SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY
66 * WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE
67 * FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S SPECIFICATION OR TO
68 * CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
70 * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
71 * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL
72 * BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT
73 * ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY
74 * BUYER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
76 * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
77 * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT
78 * OF LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING
79 * THEREOF AND RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN
80 * FRANCISCO, CA, UNDER THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE
82 ********************************************************************************
86 /*******************************************************************************
87 * C O M P I L E R F L A G S
88 ********************************************************************************
91 /*******************************************************************************
93 ********************************************************************************
98 #define DFT_TAG "[WMT-CMB-HW]"
101 /*******************************************************************************
102 * E X T E R N A L R E F E R E N C E S
103 ********************************************************************************
106 #include "mtk_wcn_cmb_hw.h"
107 #include "wmt_plat.h"
110 /*******************************************************************************
112 ********************************************************************************
114 #define DFT_RTC_STABLE_TIME 100
115 #define DFT_LDO_STABLE_TIME 100
116 #define DFT_RST_STABLE_TIME 30
117 #define DFT_OFF_STABLE_TIME 10
118 #define DFT_ON_STABLE_TIME 30
120 /*******************************************************************************
122 ********************************************************************************
125 /*******************************************************************************
126 * P U B L I C D A T A
127 ********************************************************************************
132 /*******************************************************************************
133 * P R I V A T E D A T A
134 ********************************************************************************
137 PWR_SEQ_TIME gPwrSeqTime;
142 /*******************************************************************************
143 * F U N C T I O N D E C L A R A T I O N S
144 ********************************************************************************
149 /*******************************************************************************
151 ********************************************************************************
155 mtk_wcn_cmb_hw_pwr_off (VOID)
158 WMT_INFO_FUNC("CMB-HW, hw_pwr_off start\n");
160 /*1. disable irq --> should be done when do wmt-ic swDeinit period*/
161 // TODO:[FixMe][GeorgeKuo] clarify this
163 /*2. set bgf eint/all eint to deinit state, namely input low state*/
164 iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_DEINIT);
165 iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_DEINIT);
166 WMT_INFO_FUNC("CMB-HW, BGF_EINT IRQ unregistered and set BGF_EINT GPIO to correct state!\n");
167 /* 2.1 set ALL_EINT pin to correct state even it is not used currently */
168 iRet += wmt_plat_eirq_ctrl(PIN_ALL_EINT, PIN_STA_EINT_DIS);
169 WMT_INFO_FUNC("CMB-HW, ALL_EINT IRQ unregistered and disabled\n");
170 iRet += wmt_plat_gpio_ctrl(PIN_ALL_EINT, PIN_STA_DEINIT);
171 /* 2.2 deinit gps sync */
172 iRet += wmt_plat_gpio_ctrl(PIN_GPS_SYNC, PIN_STA_DEINIT);
174 /*3. set audio interface to CMB_STUB_AIF_0, BT PCM OFF, I2S OFF*/
175 iRet += wmt_plat_audio_ctrl(CMB_STUB_AIF_0, CMB_STUB_AIF_CTRL_DIS);
177 /*4. set control gpio into deinit state, namely input low state*/
178 iRet += wmt_plat_gpio_ctrl(PIN_SDIO_GRP, PIN_STA_DEINIT);
179 iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_L);
180 iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_L);
182 /*5. set uart tx/rx into deinit state, namely input low state*/
183 iRet += wmt_plat_gpio_ctrl(PIN_UART_GRP, PIN_STA_DEINIT);
185 /* 6. Last, LDO output low */
186 iRet += wmt_plat_gpio_ctrl(PIN_LDO, PIN_STA_OUT_L);
188 /*7. deinit gps_lna*/
189 iRet += wmt_plat_gpio_ctrl(PIN_GPS_LNA, PIN_STA_DEINIT);
191 WMT_INFO_FUNC("CMB-HW, hw_pwr_off finish\n");
196 mtk_wcn_cmb_hw_pwr_on (VOID)
198 static UINT32 _pwr_first_time = 1;
201 WMT_INFO_FUNC("CMB-HW, hw_pwr_on start\n");
202 #if 0 //IRQ should in inact state before power on, so this step is not needed
203 /* disable interrupt firstly */
204 iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
205 iRet += wmt_plat_eirq_ctrl(PIN_ALL_EINT, PIN_STA_EINT_DIS);
207 /*set all control and eint gpio to init state, namely input low mode*/
208 iRet += wmt_plat_gpio_ctrl(PIN_LDO, PIN_STA_INIT);
209 iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_INIT);
210 iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_INIT);
211 iRet += wmt_plat_gpio_ctrl(PIN_SDIO_GRP, PIN_STA_INIT);
212 iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_INIT);
213 iRet += wmt_plat_gpio_ctrl(PIN_ALL_EINT, PIN_STA_INIT);
214 iRet += wmt_plat_gpio_ctrl(PIN_GPS_SYNC, PIN_STA_INIT);
215 iRet += wmt_plat_gpio_ctrl(PIN_GPS_LNA, PIN_STA_INIT);
216 // wmt_plat_gpio_ctrl(PIN_WIFI_EINT, PIN_STA_INIT); /* WIFI_EINT is controlled by SDIO host driver */
217 // TODO: [FixMe][George]:WIFI_EINT is used in common SDIO
219 /*1. pull high LDO to supply power to chip*/
220 iRet += wmt_plat_gpio_ctrl(PIN_LDO, PIN_STA_OUT_H);
221 osal_msleep(gPwrSeqTime.ldoStableTime);
223 /* 2. export RTC clock to chip*/
224 if (_pwr_first_time) {
225 /* rtc clock should be output all the time, so no need to enable output again*/
226 iRet += wmt_plat_gpio_ctrl(PIN_RTC, PIN_STA_INIT);
227 osal_msleep(gPwrSeqTime.rtcStableTime);
228 WMT_INFO_FUNC("CMB-HW, rtc clock exported\n");
231 /*3. set UART Tx/Rx to UART mode*/
232 iRet += wmt_plat_gpio_ctrl(PIN_UART_GRP, PIN_STA_INIT);
234 /*4. PMU->output low, RST->output low, sleep off stable time*/
235 iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_L);
236 iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_L);
237 osal_msleep(gPwrSeqTime.offStableTime);
239 /*5. PMU->output high, sleep rst stable time*/
240 iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_H);
241 osal_msleep(gPwrSeqTime.rstStableTime);
243 /*6. RST->output high, sleep on stable time*/
244 iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_H);
245 osal_msleep(gPwrSeqTime.onStableTime);
247 /*7. set audio interface to CMB_STUB_AIF_1, BT PCM ON, I2S OFF*/
248 /* BT PCM bus default mode. Real control is done by audio */
249 iRet += wmt_plat_audio_ctrl(CMB_STUB_AIF_1, CMB_STUB_AIF_CTRL_DIS);
251 /*8. set EINT< -ommited-> move this to WMT-IC module, where common sdio interface will be identified and do proper operation*/
252 // TODO: [FixMe][GeorgeKuo] double check if BGF_INT is implemented ok
253 iRet += wmt_plat_gpio_ctrl(PIN_BGF_EINT, PIN_STA_MUX);
254 iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_INIT);
255 iRet += wmt_plat_eirq_ctrl(PIN_BGF_EINT, PIN_STA_EINT_DIS);
256 WMT_INFO_FUNC("CMB-HW, BGF_EINT IRQ registered and disabled \n");
258 /* 8.1 set ALL_EINT pin to correct state even it is not used currently */
259 iRet += wmt_plat_gpio_ctrl(PIN_ALL_EINT, PIN_STA_MUX);
260 iRet += wmt_plat_eirq_ctrl(PIN_ALL_EINT, PIN_STA_INIT);
261 iRet += wmt_plat_eirq_ctrl(PIN_ALL_EINT, PIN_STA_EINT_DIS);
262 WMT_INFO_FUNC("CMB-HW, hw_pwr_on finish (%d)\n", iRet);
270 mtk_wcn_cmb_hw_rst (VOID)
273 WMT_INFO_FUNC("CMB-HW, hw_rst start, eirq should be disabled before this step\n");
275 /*1. PMU->output low, RST->output low, sleep off stable time*/
276 iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_L);
277 iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_L);
278 osal_msleep(gPwrSeqTime.offStableTime);
280 /*2. PMU->output high, sleep rst stable time*/
281 iRet += wmt_plat_gpio_ctrl(PIN_PMU, PIN_STA_OUT_H);
282 osal_msleep(gPwrSeqTime.rstStableTime);
284 /*3. RST->output high, sleep on stable time*/
285 iRet += wmt_plat_gpio_ctrl(PIN_RST, PIN_STA_OUT_H);
286 osal_msleep(gPwrSeqTime.onStableTime);
287 WMT_INFO_FUNC("CMB-HW, hw_rst finish, eirq should be enabled after this step\n");
292 mtk_wcn_cmb_hw_dmp_seq (VOID)
294 PUINT32 pTimeSlot = (PUINT32)&gPwrSeqTime;
295 WMT_INFO_FUNC("combo chip power on sequence time, RTC (%d), LDO (%d), RST(%d), OFF(%d), ON(%d)\n",
296 pTimeSlot[0], /**pTimeSlot++,*/
306 mtk_wcn_cmb_hw_init (
307 P_PWR_SEQ_TIME pPwrSeqTime
310 if (NULL != pPwrSeqTime &&
311 pPwrSeqTime->ldoStableTime > 0 &&
312 pPwrSeqTime->rtcStableTime > 0 &&
313 pPwrSeqTime->offStableTime > DFT_OFF_STABLE_TIME &&
314 pPwrSeqTime->onStableTime > DFT_ON_STABLE_TIME &&
315 pPwrSeqTime->rstStableTime > DFT_RST_STABLE_TIME
317 /*memcpy may be more performance*/
318 WMT_DBG_FUNC("setting hw init sequence parameters\n");
319 osal_memcpy(&gPwrSeqTime, pPwrSeqTime, osal_sizeof(gPwrSeqTime));
322 WMT_WARN_FUNC("invalid pPwrSeqTime parameter, use default hw init sequence parameters\n");
323 gPwrSeqTime.ldoStableTime = DFT_LDO_STABLE_TIME;
324 gPwrSeqTime.offStableTime = DFT_OFF_STABLE_TIME;
325 gPwrSeqTime.onStableTime = DFT_ON_STABLE_TIME;
326 gPwrSeqTime.rstStableTime = DFT_RST_STABLE_TIME;
327 gPwrSeqTime.rtcStableTime = DFT_RTC_STABLE_TIME;
329 mtk_wcn_cmb_hw_dmp_seq();
334 mtk_wcn_cmb_hw_deinit (VOID)
337 WMT_WARN_FUNC("mtk_wcn_cmb_hw_deinit start, set to default hw init sequence parameters\n");
338 gPwrSeqTime.ldoStableTime = DFT_LDO_STABLE_TIME;
339 gPwrSeqTime.offStableTime = DFT_OFF_STABLE_TIME;
340 gPwrSeqTime.onStableTime = DFT_ON_STABLE_TIME;
341 gPwrSeqTime.rstStableTime = DFT_RST_STABLE_TIME;
342 gPwrSeqTime.rtcStableTime = DFT_RTC_STABLE_TIME;
343 WMT_WARN_FUNC("mtk_wcn_cmb_hw_deinit finish\n");