drivers/mtk_wcn_combo/common/core/wmt_ic_6620.c

   1 /*! \file
   2     \brief  Declaration of library functions
   3
   4     Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
   5 */
   6
   7
   8
   9
  10 /*******************************************************************************
  11 *                         C O M P I L E R   F L A G S
  12 ********************************************************************************
  13 */
  14
  15 /*******************************************************************************
  16 *                                 M A C R O S
  17 ********************************************************************************
  18 */
  19 #ifdef DFT_TAG
  20 #undef DFT_TAG
  21 #endif
  22 #define DFT_TAG         "[WMT-IC]"
  23
  24
  25 /*******************************************************************************
  26 *                    E X T E R N A L   R E F E R E N C E S
  27 ********************************************************************************
  28 */
  29 #include "osal_typedef.h"
  30 #include "wmt_ic.h"
  31 #include "wmt_core.h"
  32 #include "wmt_lib.h"
  33 #include "stp_core.h"
  34
  35 /*******************************************************************************
  36 *                              C O N S T A N T S
  37 ********************************************************************************
  38 */
  39
  40 #define DEFAULT_PATCH_FRAG_SIZE (1000)
  41 #define MT6620E2_PATCH_FRAG_SIZE (900)
  42 #define WMT_PATCH_FRAG_1ST (0x1)
  43 #define WMT_PATCH_FRAG_MID (0x2)
  44 #define WMT_PATCH_FRAG_LAST (0x3)
  45
  46 #define CFG_CHECK_WMT_RESULT (1)
  47 #define CFG_WMT_BT_PORT2 (0) /* BT Port 2 Feature. this command does not need after coex command is downconfirmed by LC,*/
  48
  49 #define CFG_SET_OPT_REG (0)
  50 #define CFG_WMT_I2S_DBGUART_SUPPORT (0)
  51 #define CFG_SET_OPT_REG_SWLA (0)
  52 #define CFG_SET_OPT_REG_MCUCLK (0)
  53 #define CFG_SET_OPT_REG_MCUIRQ (0)
  54
  55 #define CFG_WMT_COREDUMP_ENABLE 0
  56
  57 #define CFG_WMT_MULTI_PATCH (1)
  58 /*******************************************************************************
  59 *                             D A T A   T Y P E S
  60 ********************************************************************************
  61 */
  62
  63 /*******************************************************************************
  64 *                           P R I V A T E   D A T A
  65 ********************************************************************************
  66 */
  67 #if !(CFG_WMT_MULTI_PATCH)
  68 static UCHAR gDefPatchName[NAME_MAX + 1];
  69 #endif
  70 static UCHAR gFullPatchName[NAME_MAX + 1];
  71 static const WMT_IC_INFO_S *gp_mt6620_info = NULL;
  72
  73 static UCHAR WMT_WAKEUP_DIS_GATE_CMD[] = {0x1, 0x3, 0x01, 0x00, 0x04};
  74 static UCHAR WMT_WAKEUP_DIS_GATE_EVT[] = {0x2, 0x3, 0x02, 0x0, 0x0, 0x04};
  75 #if 0
  76 static UCHAR WMT_WAKEUP_EN_GATE_CMD[] = {0x1, 0x3, 0x01, 0x00, 0x05};
  77 static UCHAR WMT_WAKEUP_EN_GATE_EVT[] = {0x2, 0x3, 0x02, 0x0, 0x0, 0x05};
  78 #endif
  79 static UCHAR WMT_QUERY_BAUD_CMD[] = {0x01, 0x04, 0x01, 0x00, 0x02};
  80 static UCHAR WMT_QUERY_BAUD_EVT_115200[] = {0x02, 0x04, 0x06, 0x00, 0x00, 0x02, 0x00, 0xC2, 0x01, 0x00};
  81 static UCHAR WMT_QUERY_BAUD_EVT_X[] = {0x02, 0x04, 0x06, 0x00, 0x00, 0x02, 0xAA, 0xAA, 0xAA, 0xBB};
  82 static UCHAR WMT_QUERY_STP_CMD[] = {0x01, 0x04, 0x01, 0x00, 0x04};
  83 static UCHAR WMT_QUERY_STP_EVT_DEFAULT[] = {0x02, 0x04, 0x06, 0x00, 0x00, 0x04, 0x11, 0x00, 0x00, 0x00};
  84 static UCHAR WMT_QUERY_STP_EVT_UART[] = {0x02, 0x04, 0x06, 0x00, 0x00, 0x04, 0xDF, 0x0E, 0x68, 0x01};
  85 static UCHAR WMT_SET_BAUD_CMD_X[] = {0x01, 0x04, 0x05, 0x00, 0x01, 0xAA, 0xAA, 0xAA, 0xBB};
  86 static UCHAR WMT_SET_BAUD_EVT[] = {0x02, 0x04, 0x02, 0x00, 0x00, 0x01};
  87 static UCHAR WMT_SET_WAKEUP_WAKE_CMD_RAW[] = {0xFF};
  88 static UCHAR WMT_SET_WAKEUP_WAKE_EVT[] = {0x02, 0x03, 0x02, 0x00, 0x00, 0x03};
  89 #if CFG_WMT_MULTI_PATCH
  90 static UCHAR WMT_PATCH_ADDRESS_CMD[] = {0x01,0x08,0x10,0x00,0x01,0x01,0x00,0x01,0x64,0x0E,0x00,0x01,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff};
  91 static UCHAR WMT_PATCH_ADDRESS_EVT[] = {0x02,0x08,0x04,0x00,0x00,0x00,0x00,0x01};
  92 static UCHAR WMT_PATCH_P_ADDRESS_CMD[] = {0x01,0x08,0x10,0x00,0x01,0x01,0x00,0x01,0x38,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0xff,0xff,0xff,0xff};
  93 static UCHAR WMT_PATCH_P_ADDRESS_EVT[] = {0x02,0x08,0x04,0x00,0x00,0x00,0x00,0x01};
  94 #endif
  95
  96 static UCHAR WMT_PATCH_CMD[] = {0x01, 0x01, 0x00, 0x00, 0x00};
  97 static UCHAR WMT_PATCH_EVT[] = {0x02, 0x01, 0x01, 0x00, 0x00};
  98 static UCHAR WMT_RESET_CMD[] = {0x01, 0x07, 0x01, 0x00, 0x04};
  99 static UCHAR WMT_RESET_EVT[] = {0x02, 0x07, 0x01, 0x00, 0x00};
 100 #if CFG_WMT_BT_PORT2
 101 static UCHAR WMT_BTP2_CMD[] = {0x01, 0x10, 0x03, 0x00, 0x01, 0x03, 0x01};
 102 static UCHAR WMT_BTP2_EVT[] = {0x02, 0x10, 0x01, 0x00, 0x00};
 103 #endif
 104 /*coex cmd/evt++*/
 105 static UCHAR WMT_COEX_SETTING_CONFIG_CMD[] = {0x01, 0x10, 0x04, 0x00, 0x01, 0xAA, 0xBB, 0xCC};
 106 static UCHAR WMT_COEX_SETTING_CONFIG_EVT[] = {0x02, 0x10, 0x01, 0x00, 0x00};
 107 static UCHAR WMT_BT_COEX_SETTING_CONFIG_CMD[] = {0x01, 0x10, 0x0B,
 108                                                          0x00, 0x02,
 109                                                          0x00, 0x00, 0x00, 0x00,
 110                                                          0xBB,0xCC,0xDD,0xEE,0xFF,0xAA};
 111 static UCHAR WMT_BT_COEX_SETTING_CONFIG_EVT[] = {0x02, 0x10, 0x01, 0x00, 0x00};
 112 static UCHAR WMT_WIFI_COEX_SETTING_CONFIG_CMD[] = {0x01, 0x10, 0x0C,
 113                                                            0x00, 0x03,
 114                                                            0x00, 0x00,0x00,0x00,0x00,
 115                                                            0xBB, 0xCC, 0xDD, 0xEE, 0xFF, 0xAA};
 116 static UCHAR WMT_WIFI_COEX_SETTING_CONFIG_EVT[] = {0x02, 0x10, 0x01, 0x00, 0x00};
 117 static UCHAR WMT_PTA_COEX_SETTING_CONFIG_CMD[] = {0x01, 0x10, 0x0A,
 118                                                           0x00, 0x04,
 119                                                           0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xEE, 0xFF, 0xFF, 0xFE};
 120 static UCHAR WMT_PTA_COEX_SETTING_CONFIG_EVT[] = {0x02, 0x10, 0x01, 0x00, 0x00};
 121 static UCHAR WMT_MISC_COEX_SETTING_CONFIG_CMD[] = {0x01, 0x10, 0x09,
 122                                                            0x00, 0x05,
 123                                                            0xAA, 0xAA, 0xAA, 0xAA,
 124                                                            0xBB, 0xBB, 0xBB, 0xBB};
 125 static UCHAR WMT_MISC_COEX_SETTING_CONFIG_EVT[] = {0x02, 0x10, 0x01, 0x00, 0x00};
 126 /*coex cmd/evt--*/
 127 static UCHAR WMT_SET_STP_CMD[] = {0x01, 0x04, 0x05, 0x00, 0x03, 0xDF, 0x0E, 0x68, 0x01};
 128 static UCHAR WMT_SET_STP_EVT[] = {0x02, 0x04, 0x02, 0x00, 0x00, 0x03};
 129 static UCHAR WMT_STRAP_CONF_CMD_FM_COMM[] = {0x01, 0x05, 0x02, 0x00, 0x02, 0x02};
 130 static UCHAR WMT_STRAP_CONF_EVT[] = {0x02, 0x05, 0x02, 0x00, 0x00, 0x02};
 131 #if 0
 132 static UCHAR WMT_SET_OSC32K_BYPASS_CMD[]= {0x01, 0x0A, 0x01, 0x00, 0x05};
 133 static UCHAR WMT_SET_OSC32K_BYPASS_EVT[]= {0x02, 0x0A, 0x01, 0x00, 0x00};
 134 #endif
 135
 136 static UCHAR  WMT_CORE_DUMP_LEVEL_04_CMD[] = {0x1, 0x0F, 0x07, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
 137 static UCHAR  WMT_CORE_DUMP_LEVEL_04_EVT[] = {0x2, 0x0F, 0x01, 0x00, 0x00};
 138
 139 /* enable all interrupt */
 140 static UCHAR WMT_SET_ALLINT_REG_CMD[] = {0x01, 0x08, 0x10, 0x00/*length*/
 141     ,0x01 /* op: w */
 142     ,0x01 /*type: reg */
 143     ,0x00 /*rev*/
 144     ,0x01 /*1 registers*/
 145     ,0x00, 0x03, 0x05, 0x80/*addr:0x80050300*/
 146     ,0x00, 0xC4, 0x00, 0x00/*value:0x0000C400*/
 147     ,0x00, 0xC4, 0x00, 0x00/*mask:0x0000C400*/
 148 };
 149
 150 static UCHAR WMT_SET_ALLINT_REG_EVT[] = {0x02, 0x08, 0x04, 0x00/*length*/
 151     ,0x00 /*S: 0*/
 152     ,0x00 /*type: reg */
 153     ,0x00 /*rev*/
 154     ,0x01 /*1 registers*/
 155 };
 156
 157 #if CFG_SET_OPT_REG_SWLA /* enable swla: eesk(7) eecs(8) oscen(19) sck0(24) scs0(25)  */
 158 static UCHAR WMT_SET_SWLA_REG_CMD[] = {0x01, 0x08, 0x1C, 0x00/*length*/
 159     ,0x01 /* op: w */
 160     ,0x01 /*type: reg */
 161     ,0x00 /*rev*/
 162     ,0x02 /*2 registers*/
 163     ,0x10, 0x01, 0x05, 0x80/*addr:0x80050110*/
 164     ,0x10, 0x10, 0x01, 0x00/*value:0x00011010*/
 165     ,0xF0, 0xF0, 0x0F, 0x00/*mask:0x000FF0F0*/
 166     ,0x40, 0x01, 0x05, 0x80/*addr:0x80050140*/
 167     ,0x00, 0x10, 0x01, 0x00/*value:0x00011000*/
 168     ,0x00, 0xF0, 0x0F, 0x00/*mask:0x000FF000*/
 169 };
 170 static UCHAR WMT_SET_SWLA_REG_EVT[] = {0x02, 0x08, 0x04, 0x00/*length*/
 171     ,0x00 /*S: 0*/
 172     ,0x00 /*type: reg */
 173     ,0x00 /*rev*/
 174     ,0x02 /*2 registers*/
 175 };
 176 #endif
 177
 178 #if CFG_SET_OPT_REG_MCUCLK /* enable mcu clk: antsel_4, eedi */
 179 static UCHAR WMT_SET_MCUCLK_REG_CMD[] = {0x01, 0x08, (4 + 12*4), 0x00/*length*/
 180     ,0x01 /* op: w */
 181     ,0x01 /* type: reg */
 182     ,0x00 /* rev */
 183     ,0x04 /* 4 registers */
 184     ,0x00, 0x04, 0x00, 0x80 /* addr:0x8000 0400 */
 185     ,0x00, 0x14, 0x00, 0x00 /* value:0x0000 1400(osc, hclk), 0x0000 1501(PLL, en) */
 186     ,0xFF, 0xFF, 0x00, 0x00 /* mask:0x0000 FFFF */
 187     ,0x80, 0x01, 0x05, 0x80 /* addr:0x8005 0180 */
 188     ,0x12, 0x13, 0x00, 0x00 /* value:0x0000 1312(osc, hclk), 0x0000 1a19(PLL, en) */
 189     ,0xFF, 0xFF, 0x00, 0x00 /* mask:0x0000 FFFF */
 190     ,0x00, 0x01, 0x05, 0x80 /* addr:0x8005 0100 */
 191     ,0x00, 0x00, 0x02, 0x00 /* value:0x0002 0000 */
 192     ,0x00, 0x00, 0x0F, 0x00 /* mask:0x000F 0000 */
 193     ,0x10, 0x01, 0x05, 0x80 /* addr:0x8005 0110 */
 194     ,0x02, 0x00, 0x00, 0x00 /* value:0x0000 0002 */
 195     ,0x0F, 0x00, 0x00, 0x00 /* mask:0x0000 000F */
 196 };
 197
 198 static UCHAR WMT_SET_MCUCLK_REG_EVT[] = {0x02, 0x08, 0x04, 0x00/*length*/
 199     ,0x00 /* S: 0 */
 200     ,0x00 /* type: reg */
 201     ,0x00 /* rev */
 202     ,0x04 /* 4 registers */
 203 };
 204 #endif
 205
 206 #if CFG_WMT_I2S_DBGUART_SUPPORT /* register write for debug uart */
 207 static UCHAR WMT_SET_DBGUART_REG_CMD[] = {0x01, 0x08, 0x1C, 0x00/*length*/
 208     ,0x01 /* op: w */
 209     ,0x01 /*type: reg */
 210     ,0x00 /*rev*/
 211     ,0x02 /*2 registers*/
 212     ,0x30, 0x01, 0x05, 0x80/*addr:0x80050130*/
 213     ,0x00, 0x00, 0x00, 0x00/*value:0x00000000*/
 214     ,0xF0, 0x0F, 0x00, 0x00/*mask:0x00000FF0*/
 215     ,0x40, 0x01, 0x05, 0x80/*addr:0x80050140*/
 216     ,0x00, 0x01, 0x00, 0x00/*value:0x00000100*/
 217     ,0x00, 0x01, 0x00, 0x00/*mask:0x00000100*/
 218 };
 219 static UCHAR WMT_SET_DBGUART_REG_EVT[] = {0x02, 0x08, 0x04, 0x00/*length*/
 220     ,0x00 /*S: 0*/
 221     ,0x00 /*type: reg */
 222     ,0x00 /*rev*/
 223     ,0x02 /*2 registers*/
 224 };
 225 #endif
 226
 227 #if CFG_SET_OPT_REG_MCUIRQ /* enable mcu irq: antsel_4, wlan_act */
 228 #if 1 /* Ray */
 229 static UCHAR WMT_SET_MCUIRQ_REG_CMD[] = {0x01, 0x08, (4 + 12*4), 0x00/*length*/
 230     ,0x01 /* op: w */
 231     ,0x01 /* type: reg */
 232     ,0x00 /* rev */
 233     ,0x04 /* 4 registers */
 234     ,0x00, 0x04, 0x00, 0x80 /* addr:0x8000_0400 */
 235     ,0x03, 0x14, 0x00, 0x00 /* value:0x0000_1403 check confg debug flag 3 low word */
 236     ,0xFF, 0xFF, 0x00, 0x00 /* mask:0x0000_FFFF */
 237     /* cirq_int_n */
 238     ,0x10, 0x01, 0x05, 0x80 /* addr:0x8005_0110 */
 239     ,0x02, 0x00, 0x00, 0x00 /* value:0x0000_0002 set EEDI as cirq_int_n debug flag (monitor flag2) */
 240     ,0x07, 0x00, 0x00, 0x00 /* mask:0x0000_0007 */
 241     ,0x00, 0x01, 0x05, 0x80 /* addr:0x8005_0100 */
 242     ,0x00, 0x00, 0x02, 0x00 /* value:0x0002_0000 (ANTSEL4=>monitor flag 0, ahb_x2_gt_ck debug flag) */
 243     ,0x00, 0x00, 0x07, 0x00 /* mask:0x0007_0000 */
 244     /* 1.    ARM irq_b, monitor flag 0 */
 245     ,0x80, 0x01, 0x05, 0x80 /* addr:0x8005_0180 */
 246     ,0x1F, 0x1E, 0x00, 0x00 /* value:0x0000_1E1F check mcusys debug flag */
 247     ,0x7F, 0x7F, 0x00, 0x00 /* mask:0x0000_7F7F */
 248 };
 249
 250 static UCHAR WMT_SET_MCUIRQ_REG_EVT[] = {0x02, 0x08, 0x04, 0x00/*length*/
 251     ,0x00 /* S: 0 */
 252     ,0x00 /* type: reg */
 253     ,0x00 /* rev */
 254     ,0x04 /* 5 registers */
 255 };
 256 #elif 0 /* KC */
 257 static UCHAR WMT_SET_MCUIRQ_REG_CMD[] = {0x01, 0x08, (4 + 12*5), 0x00/*length*/
 258     ,0x01 /* op: w */
 259     ,0x01 /* type: reg */
 260     ,0x00 /* rev */
 261     ,0x05 /* 5 registers */
 262     ,0x00, 0x04, 0x00, 0x80 /* addr:0x8000_0400 */
 263     ,0x00, 0x02, 0x00, 0x00 /* value:0x0000_0200 [15:8]=0x2 arm irq_b, 0xA irq_bus[5] bt_timcon_irq_b */
 264     ,0x00, 0xFF, 0x00, 0x00 /* mask:0x0000_FF00 */
 265     /* 1.    ARM irq_b, monitor flag 0 */
 266     ,0x80, 0x01, 0x05, 0x80 /* addr:0x8005_0180 */
 267     ,0x18, 0x00, 0x00, 0x00 /* value:0x0000_0018 [6:0]=001_1000 (monitor flag 0 select, MCUSYS, SEL:8) */
 268     ,0x7F, 0x00, 0x00, 0x00 /* mask:0x0000_007F */
 269     ,0x00, 0x01, 0x05, 0x80 /* addr:0x8005_0100 */
 270     ,0x00, 0x00, 0x02, 0x00 /* value:0x0002_0000 (ANTSEL4=>monitor flag 0) */
 271     ,0x00, 0x00, 0x07, 0x00 /* mask:0x0007_0000 */
 272     /* 2.    irq_bus[5] bt_timcon_irq_b monitor flag 15 */
 273     ,0xB0, 0x01, 0x05, 0x80 /* addr:0x8005_01B0 */
 274     ,0x00, 0x00, 0x00, 0x16 /* value:0x1600_0000 [30:24]=001_0110 (monitor flag 15 select, MCUSYS, SEL:6) */
 275     ,0x00, 0x00, 0x00, 0x7F /* mask:0x7F00_0000 */
 276     ,0x30, 0x01, 0x05, 0x80 /* addr:0x8005_0130 */
 277     ,0x00, 0x20, 0x00, 0x00 /* value:0x0000_2000 (WLAN_ACT=>monitor flag 15) */
 278     ,0x00, 0x70, 0x00, 0x00 /* mask:0x0000_7000 */
 279 };
 280
 281 static UCHAR WMT_SET_MCUIRQ_REG_EVT[] = {0x02, 0x08, 0x04, 0x00/*length*/
 282     ,0x00 /* S: 0 */
 283     ,0x00 /* type: reg */
 284     ,0x00 /* rev */
 285     ,0x05 /* 5 registers */
 286 };
 287 #endif
 288 #endif
 289
 290 /* stp sdio init scripts */
 291 static struct init_script init_table_1_1[] =
 292 {
 293     /* table_1_1 is only applied to common SDIO interface */
 294     INIT_CMD(WMT_SET_ALLINT_REG_CMD, WMT_SET_ALLINT_REG_EVT, "enable all interrupt"),
 295     /* only applied to MT6620 E1/E2? */
 296     INIT_CMD(WMT_WAKEUP_DIS_GATE_CMD, WMT_WAKEUP_DIS_GATE_EVT, "disable gating"),
 297 };
 298
 299
 300 static struct init_script init_table_1_2[] =
 301 {
 302     INIT_CMD(WMT_QUERY_BAUD_CMD, WMT_QUERY_BAUD_EVT_115200, "query baud 115200"),
 303     INIT_CMD(WMT_QUERY_STP_CMD, WMT_QUERY_STP_EVT_DEFAULT, "query stp default"),
 304     INIT_CMD(WMT_SET_BAUD_CMD_X, WMT_SET_BAUD_EVT, "set baud rate"),
 305 };
 306
 307 static struct init_script init_table_2[] =
 308 {
 309     INIT_CMD(WMT_QUERY_BAUD_CMD, WMT_QUERY_BAUD_EVT_X, "query baud X"),
 310 };
 311
 312 static struct init_script init_table_3[] =
 313 {
 314     INIT_CMD(WMT_RESET_CMD, WMT_RESET_EVT, "wmt reset"),
 315 #if CFG_WMT_BT_PORT2
 316     INIT_CMD(WMT_BTP2_CMD, WMT_BTP2_EVT, "set bt port2"),
 317 #endif
 318 };
 319
 320 #if 0
 321 static struct init_script init_table_3_1[] =
 322 {
 323     INIT_CMD(WMT_WAKEUP_EN_GATE_CMD, WMT_WAKEUP_EN_GATE_EVT, "ensable gating"),
 324 };
 325 #endif
 326
 327 static struct init_script init_table_4[] =
 328 {
 329     INIT_CMD(WMT_SET_STP_CMD, WMT_SET_STP_EVT, "set stp"),
 330 };
 331
 332 static struct init_script init_table_5[] =
 333 {
 334     INIT_CMD(WMT_QUERY_STP_CMD, WMT_QUERY_STP_EVT_UART, "query stp uart"),
 335     INIT_CMD(WMT_QUERY_BAUD_CMD, WMT_QUERY_BAUD_EVT_X, "query baud X"),
 336 };
 337
 338 static struct init_script init_table_5_1[] = {
 339      INIT_CMD(WMT_STRAP_CONF_CMD_FM_COMM, WMT_STRAP_CONF_EVT, "configure FM comm"),
 340 };
 341
 342 static struct init_script init_table_6[] =
 343 {
 344 #if 0
 345     INIT_CMD(WMT_SET_OSC32K_BYPASS_CMD, WMT_SET_OSC32K_BYPASS_EVT, "set OSC32k by pass mode."),
 346 #endif
 347         INIT_CMD(WMT_CORE_DUMP_LEVEL_04_CMD,WMT_CORE_DUMP_LEVEL_04_EVT,"setup core dump level"),
 348 };
 349
 350 #if defined(CFG_SET_OPT_REG) && CFG_SET_OPT_REG
 351 static struct init_script set_registers[] =
 352 {
 353     //INIT_CMD(WMT_SET_GPS_REG_CMD, WMT_SET_GPS_REG_EVT, "set wmt registers"),
 354     //INIT_CMD(WMT_SET_SDIODRV_REG_CMD, WMT_SET_SDIODRV_REG_EVT, "set SDIO driving registers")
 355     #if CFG_WMT_I2S_DBGUART_SUPPORT
 356     INIT_CMD(WMT_SET_DBGUART_REG_CMD, WMT_SET_DBGUART_REG_EVT, "set debug uart registers"),
 357     #endif
 358     #if CFG_SET_OPT_REG_SWLA
 359     INIT_CMD(WMT_SET_SWLA_REG_CMD, WMT_SET_SWLA_REG_EVT, "set swla registers"),
 360     #endif
 361     #if CFG_SET_OPT_REG_MCUCLK
 362     INIT_CMD(WMT_SET_MCUCLK_REG_CMD, WMT_SET_MCUCLK_REG_EVT, "set mcuclk dbg registers"),
 363     #endif
 364     #if CFG_SET_OPT_REG_MCUIRQ
 365     INIT_CMD(WMT_SET_MCUIRQ_REG_CMD, WMT_SET_MCUIRQ_REG_EVT, "set mcu irq dbg registers"),
 366     #endif
 367 };
 368 #endif
 369
 370 static struct init_script coex_table[] = {
 371      INIT_CMD(WMT_COEX_SETTING_CONFIG_CMD, WMT_COEX_SETTING_CONFIG_EVT, "coex_wmt"),
 372      INIT_CMD(WMT_BT_COEX_SETTING_CONFIG_CMD, WMT_BT_COEX_SETTING_CONFIG_EVT, "coex_bt"),
 373      INIT_CMD(WMT_WIFI_COEX_SETTING_CONFIG_CMD, WMT_WIFI_COEX_SETTING_CONFIG_EVT, "coex_wifi"),
 374      INIT_CMD(WMT_PTA_COEX_SETTING_CONFIG_CMD, WMT_PTA_COEX_SETTING_CONFIG_EVT, "coex_ext_pta"),
 375      INIT_CMD(WMT_MISC_COEX_SETTING_CONFIG_CMD, WMT_MISC_COEX_SETTING_CONFIG_EVT, "coex_misc"),
 376 };
 377
 378 /* MT6620 Chip Version and Info Table */
 379 static const WMT_IC_INFO_S mt6620_info_table[] = {
 380     {
 381         .u4HwVer            = 0x8A00,
 382         .cChipName         = WMT_IC_NAME_MT6620,
 383         .cChipVersion      = WMT_IC_VER_E1,
 384         .cPatchNameExt     = WMT_IC_PATCH_NO_EXT,
 385         .eWmtHwVer        = WMTHWVER_MT6620_E1,
 386         .bWorkWithoutPatch = MTK_WCN_BOOL_FALSE,
 387         .bPsmSupport       = MTK_WCN_BOOL_FALSE,
 388     },
 389     {
 390         .u4HwVer            = 0x8A01,
 391         .cChipName         = WMT_IC_NAME_MT6620,
 392         .cChipVersion      = WMT_IC_VER_E2,
 393         .cPatchNameExt     = WMT_IC_PATCH_NO_EXT,
 394         .eWmtHwVer        = WMTHWVER_MT6620_E2,
 395         .bWorkWithoutPatch = MTK_WCN_BOOL_FALSE,
 396         .bPsmSupport       = MTK_WCN_BOOL_FALSE,
 397     },
 398     {
 399         .u4HwVer            = 0x8A10,
 400         .cChipName         = WMT_IC_NAME_MT6620,
 401         .cChipVersion      = WMT_IC_VER_E3,
 402         .cPatchNameExt     = WMT_IC_PATCH_E3_EXT,
 403         .eWmtHwVer        = WMTHWVER_MT6620_E3,
 404         .bWorkWithoutPatch = MTK_WCN_BOOL_FALSE,
 405         .bPsmSupport       = MTK_WCN_BOOL_TRUE,
 406     },
 407     {
 408         .u4HwVer            = 0x8A11,
 409         .cChipName         = WMT_IC_NAME_MT6620,
 410         .cChipVersion      = WMT_IC_VER_E4,
 411         .cPatchNameExt     = WMT_IC_PATCH_E3_EXT,
 412         .eWmtHwVer        = WMTHWVER_MT6620_E4,
 413         .bWorkWithoutPatch = MTK_WCN_BOOL_FALSE,
 414         .bPsmSupport       = MTK_WCN_BOOL_TRUE,
 415     },
 416     {
 417         .u4HwVer            = 0x8A30,
 418         .cChipName         = WMT_IC_NAME_MT6620,
 419         .cChipVersion      = WMT_IC_VER_E6,
 420         .cPatchNameExt     = WMT_IC_PATCH_E6_EXT,
 421         .eWmtHwVer        = WMTHWVER_MT6620_E6,
 422         .bWorkWithoutPatch = MTK_WCN_BOOL_TRUE /*MTK_WCN_BOOL_FALSE*/,
 423         .bPsmSupport       = MTK_WCN_BOOL_TRUE,
 424     },
 425     {
 426         .u4HwVer            = 0x8B30,
 427         .cChipName         = WMT_IC_NAME_MT6620,
 428         .cChipVersion      = WMT_IC_VER_E6,
 429         .cPatchNameExt     = WMT_IC_PATCH_E6_EXT,
 430         .eWmtHwVer        = WMTHWVER_MT6620_E6,
 431         .bWorkWithoutPatch = MTK_WCN_BOOL_TRUE /*MTK_WCN_BOOL_FALSE*/,
 432         .bPsmSupport       = MTK_WCN_BOOL_TRUE,
 433     },
 434     {
 435         .u4HwVer            = 0x8B31,
 436         .cChipName         = WMT_IC_NAME_MT6620,
 437         .cChipVersion      = WMT_IC_VER_E7,
 438         .cPatchNameExt     = WMT_IC_PATCH_E6_EXT,
 439         .eWmtHwVer        = WMTHWVER_MT6620_E7,
 440         .bWorkWithoutPatch = MTK_WCN_BOOL_TRUE /*MTK_WCN_BOOL_FALSE*/,
 441         .bPsmSupport       = MTK_WCN_BOOL_TRUE,
 442     },
 443 };
 444
 445 /*******************************************************************************
 446 *                  F U N C T I O N   D E C L A R A T I O N S
 447 ********************************************************************************
 448 */
 449
 450 static INT32
 451 mt6620_sw_init (
 452     P_WMT_HIF_CONF pWmtHifConf
 453     );
 454
 455 static INT32
 456 mt6620_sw_deinit (
 457     P_WMT_HIF_CONF pWmtHifConf
 458     );
 459
 460 static INT32
 461 mt6620_pin_ctrl (
 462     WMT_IC_PIN_ID id,
 463     WMT_IC_PIN_STATE state,
 464     UINT32 flag
 465     );
 466
 467 static INT32
 468 mt6620_aif_ctrl (
 469     WMT_IC_PIN_STATE state,
 470     UINT32 flag
 471     );
 472
 473 static INT32
 474 mt6620_ver_check (VOID);
 475
 476 static const WMT_IC_INFO_S*
 477 mt6620_find_wmt_ic_info (
 478     const UINT32 hw_ver
 479     );
 480
 481 static INT32
 482 wmt_stp_init_coex (VOID);
 483
 484 #if CFG_WMT_MULTI_PATCH
 485 static INT32
 486 mt6620_patch_dwn (UINT32 index);
 487 static INT32 mt6620_patch_info_prepare(VOID);
 488 #else
 489 static INT32
 490 mt6620_update_patch_name (VOID);
 491
 492 static INT32
 493 mt6620_patch_dwn (VOID);
 494 #endif
 495 static MTK_WCN_BOOL mt6620_quick_sleep_flag_get(VOID);
 496
 497 /*******************************************************************************
 498 *                            P U B L I C   D A T A
 499 ********************************************************************************
 500 */
 501
 502 /* MT6620 Operation Function Table */
 503 const WMT_IC_OPS wmt_ic_ops_mt6620 = {
 504     .icId = 0x6620,
 505     .sw_init = mt6620_sw_init,
 506     .sw_deinit = mt6620_sw_deinit,
 507     .ic_pin_ctrl = mt6620_pin_ctrl,
 508     .ic_ver_check = mt6620_ver_check,
 509     .co_clock_ctrl = NULL,
 510     .is_quick_sleep  = mt6620_quick_sleep_flag_get,
 511     .is_aee_dump_support = NULL,
 512 };
 513
 514 /*******************************************************************************
 515 *                              F U N C T I O N S
 516 ********************************************************************************
 517 */
 518 #if 0
 519 static INT32
 520 mt6620_sw_init (
 521     P_WMT_HIF_CONF pWmtHifConf
 522     )
 523 {
 524     INT32 iRet = -1;
 525     UINT32 u4Res = 0;
 526     UCHAR evtBuf[256];
 527     UINT32 ctrlPa1;
 528     UINT32 ctrlPa2;
 529     UINT32 hw_ver;
 530
 531     WMT_DBG_FUNC(" start\n");
 532
 533     osal_assert(NULL != gp_mt6620_info);
 534     if ( (NULL == gp_mt6620_info)
 535         || (NULL == pWmtHifConf)
 536         ) {
 537         WMT_ERR_FUNC("null pointers: gp_mt6620_info(0x%p), pWmtHifConf(0x%p)\n",
 538             gp_mt6620_info, pWmtHifConf);
 539         return -1;
 540     }
 541
 542     hw_ver = gp_mt6620_info->u4HwVer;
 543
 544     //4 <3.1> start init for sdio
 545     if (WMT_HIF_SDIO == pWmtHifConf->hifType) {
 546         /* 1. enable all INT32 */
 547         /* 2. disable mcu gate (only MT6620E1/E2) */
 548         iRet = wmt_core_init_script(init_table_1_1, osal_array_size(init_table_1_1));
 549         if (iRet) {
 550             WMT_ERR_FUNC("init_table_1_1 fail:%d\n", iRet);
 551             osal_assert(0);
 552             return -1;
 553         }
 554     }
 555
 556     //4 <3.2> start init for uart
 557     if (WMT_HIF_UART == pWmtHifConf->hifType) {
 558         /* init variable fields for script execution */
 559         osal_memcpy(&WMT_SET_BAUD_CMD_X[5], &pWmtHifConf->au4HifConf[0], osal_sizeof(UINT32));
 560         WMT_SET_BAUD_CMD_X[8] = (UCHAR)0x00;//0xC0 MTK Flow Control /* no flow control */
 561         osal_memcpy(&WMT_QUERY_BAUD_EVT_X[6], &pWmtHifConf->au4HifConf[0], osal_sizeof(UINT32));
 562         WMT_QUERY_BAUD_EVT_X[9] = (UCHAR)0x00; //0xC0 MTK Flow Control /* no flow control */
 563
 564         /* 3. Query chip baud rate (TEST-ONLY) */
 565         /* 4. Query chip STP options (TEST-ONLY) */
 566         /* 5. Change chip baud rate: t_baud */
 567         //WMT_DBG_FUNC("WMT-CORE: init_table_1_2 set chip baud:%d", pWmtHifConf->au4HifConf[0]);
 568         iRet = wmt_core_init_script(init_table_1_2, osal_array_size(init_table_1_2));
 569         if (iRet) {
 570             WMT_ERR_FUNC("init_table_1_2 fail(%d)\n", iRet);
 571             osal_assert(0);
 572             return -2;
 573         }
 574
 575         /* 6. Set host baudrate and flow control*/
 576         ctrlPa1 = pWmtHifConf->au4HifConf[0]; ctrlPa2 = 0;
 577         iRet = wmt_core_ctrl(WMT_CTRL_HOST_BAUDRATE_SET, &ctrlPa1, &ctrlPa2);
 578         if (iRet) {
 579             WMT_ERR_FUNC("change baudrate(%d) fail(%d)\n", pWmtHifConf->au4HifConf[0], iRet);
 580             return -3;
 581         }
 582         WMT_INFO_FUNC("WMT-CORE: change baudrate(%d) ok\n", pWmtHifConf->au4HifConf[0]);
 583
 584         /* 7. Wake up chip and check event */
 585 //          iRet = (*kal_stp_tx_raw)(&WMT_SET_WAKEUP_WAKE_CMD_RAW[0], 1, &u4Res);
 586         iRet = wmt_core_tx((PUINT8)&WMT_SET_WAKEUP_WAKE_CMD_RAW[0], 1, &u4Res, MTK_WCN_BOOL_TRUE);
 587         if (iRet || (u4Res != 1)) {
 588             WMT_ERR_FUNC("write raw iRet(%d) written(%d)\n", iRet, u4Res);
 589             return -4;
 590         }
 591
 592         osal_memset(evtBuf, 0, osal_sizeof(evtBuf));
 593         iRet = wmt_core_rx(evtBuf, osal_sizeof(WMT_SET_WAKEUP_WAKE_EVT), &u4Res);
 594 #ifdef CFG_DUMP_EVT
 595         WMT_DBG_FUNC("WAKEUP_WAKE_EVT read len %d [%02x,%02x,%02x,%02x,%02x,%02x]\n",
 596              (INT32)u4Res, evtBuf[0], evtBuf[1], evtBuf[2], evtBuf[3], evtBuf[4], evtBuf[5]);
 597 #endif
 598         if (iRet || (u4Res != osal_sizeof(WMT_SET_WAKEUP_WAKE_EVT))) {
 599             WMT_ERR_FUNC("read WAKEUP_WAKE_EVT fail(%d)\n", iRet);
 600             return -5;
 601         }
 602         //WMT_DBG_FUNC("WMT-CORE: read WMT_SET_WAKEUP_WAKE_EVT ok");
 603
 604 #if CFG_CHECK_WMT_RESULT
 605         if (osal_memcmp(evtBuf, WMT_SET_WAKEUP_WAKE_EVT, osal_sizeof(WMT_SET_WAKEUP_WAKE_EVT)) != 0) {
 606             WMT_ERR_FUNC("WMT-CORE: write WMT_SET_WAKEUP_WAKE_CMD_RAW status fail\n");
 607             return -6;
 608         }
 609 #endif
 610
 611         /* 8. Query baud rate (TEST-ONLY) */
 612         iRet = wmt_core_init_script(init_table_2, osal_array_size(init_table_2));
 613         if (iRet) {
 614             WMT_ERR_FUNC("init_table_2 fail(%d)\n", iRet);
 615             return -7;
 616         }
 617     }
 618
 619     /* 9. download patch */
 620     iRet = mt6620_patch_dwn();
 621
 622     WMT_INFO_FUNC("Not to check the patch validity\n");
 623 #if 0
 624     if (iRet) {
 625         WMT_ERR_FUNC("patch dwn fail (%d)\n", iRet);
 626         return -8;
 627     }
 628     else {
 629         WMT_INFO_FUNC("patch dwn ok\n");
 630     }
 631 #endif
 632     /* 10. WMT Reset command */
 633     iRet = wmt_core_init_script(init_table_3, osal_array_size(init_table_3));
 634     if (iRet) {
 635         WMT_ERR_FUNC("init_table_3 fail(%d)\n", iRet);
 636         return -9;
 637     }
 638     iRet = wmt_stp_init_coex();
 639     if (iRet) {
 640         WMT_ERR_FUNC("init_coex fail(%d)\n", iRet);
 641         return -10;
 642     }
 643     else {
 644         WMT_INFO_FUNC("init_coex ok\n");
 645     }
 646
 647 #if 0
 648     /*10-2 enable 32K By Pass Mode*/
 649     //if hwVer = E3/E4, please enable 32K by pass mode.
 650     //does not support mt6620E1/E2, always enable 32k bypass mode
 651     //if ((hwVer == 0x8a10 || hwVer == 0x8a11))
 652     {
 653         WMT_INFO_FUNC("WMT-CORE: init_table_6 OSC32K");
 654         iRet = wmt_core_init_script(init_table_6, osal_array_size(init_table_6));
 655         if (iRet == 0) {
 656             WMT_DBG_FUNC("WMT-CORE: init_table_6 OSC32K, successful\n");
 657         }
 658         else {
 659             WMT_WARN_FUNC("init table 6 OSC32K fail, continue init...\n");
 660             /*return -11;*/
 661         }
 662     }
 663 #endif
 664
 665     if (WMT_HIF_UART == pWmtHifConf->hifType) {
 666         /* 11. Set chip STP options */
 667         iRet = wmt_core_init_script(init_table_4, osal_array_size(init_table_4));
 668         if (iRet) {
 669             WMT_ERR_FUNC("init_table_4 fail(%d)\n", iRet);
 670             return -12;
 671         }
 672
 673         /* 12. Enable host STP-UART mode */
 674         ctrlPa1 = WMT_STP_CONF_MODE; ctrlPa2 = MTKSTP_UART_FULL_MODE;
 675         iRet = wmt_core_ctrl(WMT_CTRL_STP_CONF, &ctrlPa1, &ctrlPa2);
 676         ctrlPa1 = WMT_STP_CONF_EN; ctrlPa2 = 1;
 677         iRet += wmt_core_ctrl(WMT_CTRL_STP_CONF, &ctrlPa1, &ctrlPa2);
 678         if (iRet) {
 679             WMT_ERR_FUNC("enable host STP-UART-FULL mode fail(%d)\n", iRet);
 680             return -13;
 681         }
 682         WMT_INFO_FUNC("enable host STP-UART-FULL mode\n");
 683         /*13. wait for 10ms, enough for chip do mechanism switch.(at least 2ms is needed)*/
 684         osal_msleep(10);
 685         /* 14. Query chip STP options (TEST-ONLY) */
 686         /* 15. Query baud rate (stp, TEST-ONLY) */
 687         iRet = wmt_core_init_script(init_table_5, osal_array_size(init_table_5));
 688         if (iRet) {
 689             WMT_ERR_FUNC("init_table_5 fail(%d)\n", iRet);
 690             return -14;
 691         }
 692     }
 693
 694     /* 15. Set FM strap */
 695     WMT_STRAP_CONF_CMD_FM_COMM[5] = (UCHAR)pWmtHifConf->au4StrapConf[0];
 696     WMT_STRAP_CONF_EVT[5] = (UCHAR)pWmtHifConf->au4StrapConf[0];
 697     iRet = wmt_core_init_script(init_table_5_1, osal_array_size(init_table_5_1));
 698     if (iRet) {
 699         WMT_ERR_FUNC("init_table_5_1 fm mode(%d) fail(%d)\n",
 700             pWmtHifConf->au4StrapConf[0],
 701             iRet);
 702         return -15;
 703     }
 704     WMT_INFO_FUNC("set fm mode (%d) ok\n", pWmtHifConf->au4StrapConf[0]);
 705
 706 #if CFG_SET_OPT_REG /*set registers*/
 707         iRet = wmt_core_init_script(set_registers, osal_array_size(set_registers));
 708         if (iRet) {
 709             WMT_ERR_FUNC("set_registers fail(%d)", iRet);
 710             return -16;
 711         }
 712 #endif
 713
 714 #if 0
 715     /* 16. trace32 dump when fw assert*/
 716     {
 717         INT32 val = 0x00000001;
 718         WMT_INFO_FUNC("WMT-CORE: enable assert dump");
 719         wmt_reg_rw_raw(1, 0x0100092c, &val, 0xFFFFFFFF);
 720     }
 721 #endif
 722
 723 #if CFG_WMT_PS_SUPPORT
 724     osal_assert(NULL != gp_mt6620_info);
 725     if (NULL != gp_mt6620_info) {
 726        if (MTK_WCN_BOOL_FALSE != gp_mt6620_info->bPsmSupport) {
 727            wmt_lib_ps_enable();
 728        }
 729        else {
 730            wmt_lib_ps_disable();
 731        }
 732     }
 733 #endif
 734
 735     return 0;
 736 }
 737 #endif
 738
 739 static INT32
 740 mt6620_sw_init (
 741     P_WMT_HIF_CONF pWmtHifConf
 742     )
 743 {
 744     INT32 iRet = -1;
 745     UINT32 u4Res = 0;
 746     UCHAR evtBuf[256];
 747     UINT32 ctrlPa1;
 748     UINT32 ctrlPa2;
 749     UINT32 hw_ver;
 750         UINT32 patch_num = 0;
 751         UINT32 patch_index = 0;
 752     WMT_DBG_FUNC(" start\n");
 753
 754     osal_assert(NULL != gp_mt6620_info);
 755     if ( (NULL == gp_mt6620_info)
 756         || (NULL == pWmtHifConf)
 757         ) {
 758         WMT_ERR_FUNC("null pointers: gp_mt6620_info(0x%p), pWmtHifConf(0x%p)\n",
 759             gp_mt6620_info, pWmtHifConf);
 760         return -1;
 761     }
 762
 763     hw_ver = gp_mt6620_info->u4HwVer;
 764
 765     //4 <3.1> start init for sdio
 766     if (WMT_HIF_SDIO == pWmtHifConf->hifType) {
 767         /* 1. enable all INT32 */
 768         /* 2. disable mcu gate (only MT6620E1/E2) */
 769         iRet = wmt_core_init_script(init_table_1_1, osal_array_size(init_table_1_1));
 770         if (iRet) {
 771             WMT_ERR_FUNC("init_table_1_1 fail:%d\n", iRet);
 772             osal_assert(0);
 773             return -1;
 774         }
 775     }
 776
 777     //4 <3.2> start init for uart
 778     if (WMT_HIF_UART == pWmtHifConf->hifType) {
 779
 780                 /* init variable fields for script execution */
 781                  osal_memcpy(&WMT_SET_BAUD_CMD_X[5], &pWmtHifConf->au4HifConf[0], osal_sizeof(UINT32));
 782                  osal_memcpy(&WMT_QUERY_BAUD_EVT_X[6], &pWmtHifConf->au4HifConf[0], osal_sizeof(UINT32));
 783                  if (WMT_UART_MTK_SW_FC == pWmtHifConf->uartFcCtrl)
 784                  {
 785                          WMT_INFO_FUNC("enable MTK SW Flow Control\n");
 786                          WMT_SET_BAUD_CMD_X[8] = (UCHAR)0x80;//* MTK SW flow control */
 787                          WMT_QUERY_BAUD_EVT_X[9] = (UCHAR)0x80; //* MTK SW flow control */
 788                  }
 789                  else if (WMT_UART_LUX_SW_FC == pWmtHifConf->uartFcCtrl)
 790                  {
 791                          WMT_INFO_FUNC("enable Linux SW Flow Control\n");
 792                          WMT_SET_BAUD_CMD_X[8] = (UCHAR)0x80;//* Linux SW flow control */
 793                          WMT_QUERY_BAUD_EVT_X[9] = (UCHAR)0x80; //* Linux SW flow control */
 794                  }
 795                  else if (WMT_UART_HW_FC == pWmtHifConf->uartFcCtrl)
 796                  {
 797                          WMT_INFO_FUNC("enable HW Flow Control\n");
 798                          WMT_SET_BAUD_CMD_X[8] = (UCHAR)0xC0;//* HW flow control */
 799                          WMT_QUERY_BAUD_EVT_X[9] = (UCHAR)0xC0; //* HW flow control */
 800                  }
 801                  else {
 802                          /* WMT_UART_NO_FC and all other cases!!! */
 803                          WMT_INFO_FUNC("no Flow Control (uartFcCtrl:%d)\n", pWmtHifConf->uartFcCtrl);
 804                          WMT_SET_BAUD_CMD_X[8] = (UCHAR)0x00;//* no flow control */
 805                          WMT_QUERY_BAUD_EVT_X[9] = (UCHAR)0x00; //* no flow control */
 806                  }
 807
 808         /* 3. Query chip baud rate (TEST-ONLY) */
 809         /* 4. Query chip STP options (TEST-ONLY) */
 810         /* 5. Change chip baud rate: t_baud */
 811         //WMT_DBG_FUNC("WMT-CORE: init_table_1_2 set chip baud:%d", pWmtHifConf->au4HifConf[0]);
 812         iRet = wmt_core_init_script(init_table_1_2, osal_array_size(init_table_1_2));
 813         if (iRet) {
 814             WMT_ERR_FUNC("init_table_1_2 fail(%d)\n", iRet);
 815             osal_assert(0);
 816             return -2;
 817         }
 818
 819         /* 6. Set host baudrate and flow control*/
 820         ctrlPa1 = pWmtHifConf->au4HifConf[0]; ctrlPa2 = 0;
 821         iRet = wmt_core_ctrl(WMT_CTRL_HOST_BAUDRATE_SET, &ctrlPa1, &ctrlPa2);
 822         if (iRet) {
 823             WMT_ERR_FUNC("change baudrate(%d) fail(%d)\n", pWmtHifConf->au4HifConf[0], iRet);
 824             return -3;
 825         }
 826         WMT_INFO_FUNC("WMT-CORE: change baudrate(%d) ok\n", pWmtHifConf->au4HifConf[0]);
 827
 828         /* 7. Wake up chip and check event */
 829 //          iRet = (*kal_stp_tx_raw)(&WMT_SET_WAKEUP_WAKE_CMD_RAW[0], 1, &u4Res);
 830         iRet = wmt_core_tx((PUINT8)&WMT_SET_WAKEUP_WAKE_CMD_RAW[0], 1, &u4Res, MTK_WCN_BOOL_TRUE);
 831         if (iRet || (u4Res != 1)) {
 832             WMT_ERR_FUNC("write raw iRet(%d) written(%d)\n", iRet, u4Res);
 833             return -4;
 834         }
 835
 836         osal_memset(evtBuf, 0, osal_sizeof(evtBuf));
 837         iRet = wmt_core_rx(evtBuf, osal_sizeof(WMT_SET_WAKEUP_WAKE_EVT), &u4Res);
 838 #ifdef CFG_DUMP_EVT
 839         WMT_DBG_FUNC("WAKEUP_WAKE_EVT read len %d [%02x,%02x,%02x,%02x,%02x,%02x]\n",
 840              (INT32)u4Res, evtBuf[0], evtBuf[1], evtBuf[2], evtBuf[3], evtBuf[4], evtBuf[5]);
 841 #endif
 842         if (iRet || (u4Res != osal_sizeof(WMT_SET_WAKEUP_WAKE_EVT))) {
 843             WMT_ERR_FUNC("read WAKEUP_WAKE_EVT fail(%d)\n", iRet);
 844             return -5;
 845         }
 846         //WMT_DBG_FUNC("WMT-CORE: read WMT_SET_WAKEUP_WAKE_EVT ok");
 847
 848 #if CFG_CHECK_WMT_RESULT
 849         if (osal_memcmp(evtBuf, WMT_SET_WAKEUP_WAKE_EVT, osal_sizeof(WMT_SET_WAKEUP_WAKE_EVT)) != 0) {
 850             WMT_ERR_FUNC("WMT-CORE: write WMT_SET_WAKEUP_WAKE_CMD_RAW status fail\n");
 851             return -6;
 852         }
 853 #endif
 854
 855         /* 8. Query baud rate (TEST-ONLY) */
 856         iRet = wmt_core_init_script(init_table_2, osal_array_size(init_table_2));
 857         if (iRet) {
 858             WMT_ERR_FUNC("init_table_2 fail(%d)\n", iRet);
 859             return -7;
 860         }
 861     }
 862     if (WMT_HIF_UART == pWmtHifConf->hifType) {
 863         /* 9. Set chip STP options */
 864         iRet = wmt_core_init_script(init_table_4, osal_array_size(init_table_4));
 865         if (iRet) {
 866             WMT_ERR_FUNC("init_table_4 fail(%d)\n", iRet);
 867             return -8;
 868         }
 869
 870         /* 10. Enable host STP-UART mode */
 871         ctrlPa1 = WMT_STP_CONF_MODE; ctrlPa2 = MTKSTP_UART_FULL_MODE;
 872         iRet = wmt_core_ctrl(WMT_CTRL_STP_CONF, &ctrlPa1, &ctrlPa2);
 873         ctrlPa1 = WMT_STP_CONF_EN; ctrlPa2 = 1;
 874         iRet += wmt_core_ctrl(WMT_CTRL_STP_CONF, &ctrlPa1, &ctrlPa2);
 875         if (iRet) {
 876             WMT_ERR_FUNC("enable host STP-UART-FULL mode fail(%d)\n", iRet);
 877             return -9;
 878         }
 879         WMT_INFO_FUNC("enable host STP-UART-FULL mode\n");
 880         /*10. wait for 10ms, enough for chip do mechanism switch.(at least 2ms is needed)*/
 881         osal_msleep(10);
 882         /* 11. Query chip STP options (TEST-ONLY) */
 883         /* 12. Query baud rate (stp, TEST-ONLY) */
 884         iRet = wmt_core_init_script(init_table_5, osal_array_size(init_table_5));
 885         if (iRet) {
 886             WMT_ERR_FUNC("init_table_5 fail(%d)\n", iRet);
 887             return -10;
 888         }
 889     }
 890     /* 13. download patch */
 891 #if CFG_WMT_MULTI_PATCH
 892         iRet = mt6620_patch_info_prepare();
 893         if(iRet)
 894         {
 895                 WMT_ERR_FUNC("patch info perpare fail(%d)\n",iRet);
 896                 return -11;
 897         }
 898
 899         ctrlPa1 = 0;ctrlPa2 = 0;
 900         wmt_core_ctrl(WMT_CTRL_GET_PATCH_NUM,&ctrlPa1,&ctrlPa2);
 901         patch_num = ctrlPa1;
 902         WMT_INFO_FUNC("patch total num = [%d]\n",patch_num);
 903
 904         for(patch_index = 0;patch_index < patch_num;patch_index++)
 905         {
 906                 iRet = mt6620_patch_dwn(patch_index);
 907                 if(iRet){
 908                         WMT_ERR_FUNC("patch dwn fail (%d),patch_index(%d)\n", iRet,patch_index);
 909                 return -12;
 910                 }
 911                 iRet = wmt_core_init_script(init_table_3, osal_array_size(init_table_3));
 912             if (iRet) {
 913                 WMT_ERR_FUNC("init_table_3 fail(%d)\n", iRet);
 914                 return -13;
 915             }
 916         }
 917 #else
 918     iRet = mt6620_patch_dwn();
 919
 920     WMT_INFO_FUNC("Not to check the patch validity\n");
 921 #if 0
 922     if (iRet) {
 923         WMT_ERR_FUNC("patch dwn fail (%d)\n", iRet);
 924         return -11;
 925     }
 926     else {
 927         WMT_INFO_FUNC("patch dwn ok\n");
 928     }
 929 #endif
 930     /* 14. WMT Reset command */
 931     iRet = wmt_core_init_script(init_table_3, osal_array_size(init_table_3));
 932     if (iRet) {
 933         WMT_ERR_FUNC("init_table_3 fail(%d)\n", iRet);
 934         return -13;
 935     }
 936 #endif
 937     iRet = wmt_stp_init_coex();
 938     if (iRet) {
 939         WMT_ERR_FUNC("init_coex fail(%d)\n", iRet);
 940         return -14;
 941     }
 942     else {
 943         WMT_INFO_FUNC("init_coex ok\n");
 944     }
 945
 946 #if 0
 947     /*10-2 enable 32K By Pass Mode*/
 948     //if hwVer = E3/E4, please enable 32K by pass mode.
 949     //does not support mt6620E1/E2, always enable 32k bypass mode
 950     //if ((hwVer == 0x8a10 || hwVer == 0x8a11))
 951     {
 952         WMT_INFO_FUNC("WMT-CORE: init_table_6 OSC32K");
 953         iRet = wmt_core_init_script(init_table_6, osal_array_size(init_table_6));
 954         if (iRet == 0) {
 955             WMT_DBG_FUNC("WMT-CORE: init_table_6 OSC32K, successful\n");
 956         }
 957         else {
 958             WMT_WARN_FUNC("init table 6 OSC32K fail, continue init...\n");
 959             /*return -14;*/
 960         }
 961     }
 962 #endif
 963
 964
 965
 966     /* 15. Set FM strap */
 967     WMT_STRAP_CONF_CMD_FM_COMM[5] = (UCHAR)pWmtHifConf->au4StrapConf[0];
 968     WMT_STRAP_CONF_EVT[5] = (UCHAR)pWmtHifConf->au4StrapConf[0];
 969     iRet = wmt_core_init_script(init_table_5_1, osal_array_size(init_table_5_1));
 970     if (iRet) {
 971         WMT_ERR_FUNC("init_table_5_1 fm mode(%d) fail(%d)\n",
 972             pWmtHifConf->au4StrapConf[0],
 973             iRet);
 974         return -15;
 975     }
 976     WMT_INFO_FUNC("set fm mode (%d) ok\n", pWmtHifConf->au4StrapConf[0]);
 977
 978 #if CFG_SET_OPT_REG /*set registers*/
 979         iRet = wmt_core_init_script(set_registers, osal_array_size(set_registers));
 980         if (iRet) {
 981             WMT_ERR_FUNC("set_registers fail(%d)", iRet);
 982             return -16;
 983         }
 984 #endif
 985
 986 #if 0
 987     /* 16. trace32 dump when fw assert*/
 988     {
 989         INT32 val = 0x00000001;
 990         WMT_INFO_FUNC("WMT-CORE: enable assert dump");
 991         wmt_reg_rw_raw(1, 0x0100092c, &val, 0xFFFFFFFF);
 992     }
 993 #endif
 994
 995 #if CFG_WMT_COREDUMP_ENABLE
 996     /*Open Core Dump Function @QC begin*/
 997     mtk_wcn_stp_coredump_flag_ctrl(1);
 998 #endif
 999     if (0 != mtk_wcn_stp_coredump_flag_get())
1000     {
1001         iRet = wmt_core_init_script(init_table_6, osal_array_size(init_table_6));
1002         if (iRet) {
1003             WMT_ERR_FUNC("init_table_6 core dump setting fail(%d)\n",
1004                 iRet);
1005             return -17;
1006         } else {
1007             WMT_INFO_FUNC("enable mt662x firmware coredump\n");
1008         }
1009     }
1010     else
1011     {
1012         WMT_INFO_FUNC("disable mt662x firmware coredump\n");
1013     }
1014
1015 #if CFG_WMT_PS_SUPPORT
1016     osal_assert(NULL != gp_mt6620_info);
1017     if (NULL != gp_mt6620_info) {
1018        if (MTK_WCN_BOOL_FALSE != gp_mt6620_info->bPsmSupport) {
1019            wmt_lib_ps_enable();
1020        }
1021        else {
1022            wmt_lib_ps_disable();
1023        }
1024     }
1025 #endif
1026
1027     return 0;
1028 }
1029
1030
1031 static INT32
1032 mt6620_sw_deinit (
1033     P_WMT_HIF_CONF pWmtHifConf
1034     )
1035 {
1036     WMT_DBG_FUNC(" start\n");
1037
1038 #if CFG_WMT_PS_SUPPORT
1039     osal_assert(NULL != gp_mt6620_info);
1040     if ( (NULL != gp_mt6620_info)
1041         && (MTK_WCN_BOOL_FALSE != gp_mt6620_info->bPsmSupport) ) {
1042            wmt_lib_ps_disable();
1043        }
1044 #endif
1045
1046     gp_mt6620_info = NULL;
1047
1048     return 0;
1049 }
1050
1051 static INT32
1052 mt6620_aif_ctrl (
1053     WMT_IC_PIN_STATE state,
1054     UINT32 flag
1055     )
1056 {
1057     INT32   ret = -1;
1058     UINT32  val;
1059
1060     if ( (flag & WMT_LIB_AIF_FLAG_MASK) == WMT_LIB_AIF_FLAG_SHARE ) {
1061         WMT_INFO_FUNC("PCM & I2S PIN SHARE\n");
1062         switch (state) {
1063         case WMT_IC_AIF_0:
1064             /* BT_PCM_OFF & FM line in/out */
1065             val = 0x00000770;
1066             ret = wmt_core_reg_rw_raw(1, 0x80050140, &val, 0x00000FF0);
1067             val = 0x00000000;
1068             ret += wmt_core_reg_rw_raw(1, 0x80050150, &val, 0x00000800);
1069             break;
1070
1071         case WMT_IC_AIF_1:
1072             /* BT_PCM_ON & FM line in/out */
1073             val = 0x00000700;
1074             ret = wmt_core_reg_rw_raw(1, 0x80050140, &val, 0x00000FF0);
1075             val = 0x00000000;
1076             ret += wmt_core_reg_rw_raw(1, 0x80050150, &val, 0x00000800);
1077             break;
1078
1079         case WMT_IC_AIF_2:
1080             /* BT_PCM_OFF & FM I2S */
1081             val = 0x00000710;
1082             ret = wmt_core_reg_rw_raw(1, 0x80050140, &val, 0x00000FF0);
1083             val = 0x00000800; /* 800:3-wire, 000: 4-wire */
1084             ret += wmt_core_reg_rw_raw(1, 0x80050150, &val, 0x00000800);
1085             break;
1086         default:
1087             WMT_ERR_FUNC("unsupported state (%d) \n", state);
1088             ret = -1;
1089             break;
1090         }
1091     }
1092     else {
1093          /*PCM & I2S separate*/
1094         WMT_INFO_FUNC("PCM & I2S PIN SEPARATE\n");
1095         switch (state) {
1096         case WMT_IC_AIF_0:
1097             /* BT_PCM_OFF & FM line in/out */
1098             val = 0x00000770;
1099             ret = wmt_core_reg_rw_raw(1, 0x80050140, &val, 0x00000FF0);
1100             val = 0x00000000;
1101             ret += wmt_core_reg_rw_raw(1, 0x80050150, &val, 0x00000800);
1102             break;
1103
1104         case WMT_IC_AIF_1:
1105             /* BT_PCM_ON & FM line in/out */
1106             val = 0x00000700;
1107             ret = wmt_core_reg_rw_raw(1, 0x80050140, &val, 0x00000FF0);
1108             val = 0x00000000;
1109             ret += wmt_core_reg_rw_raw(1, 0x80050150, &val, 0x00000800);
1110             break;
1111
1112         case WMT_IC_AIF_2:
1113             /* BT_PCM_OFF & FM I2S */
1114             val = 0x00000070;
1115             ret = wmt_core_reg_rw_raw(1, 0x80050140, &val, 0x00000FF0);
1116             val = 0x00000800; /* 800:3-wire, 000: 4-wire */
1117             ret += wmt_core_reg_rw_raw(1, 0x80050150, &val, 0x00000800);
1118
1119             break;
1120         case WMT_IC_AIF_3:
1121             val = 0x00000000;
1122             ret = wmt_core_reg_rw_raw(1, 0x80050140, &val, 0x00000FF0);
1123             val = 0x00000800; /* 800:3-wire, 000: 4-wire */
1124             ret += wmt_core_reg_rw_raw(1, 0x80050150, &val, 0x00000800);
1125
1126         default:
1127             WMT_ERR_FUNC("unsupported state (%d) \n", state);
1128             ret = -1;
1129             break;
1130         }
1131     }
1132
1133     if (!ret) {
1134         WMT_INFO_FUNC("new state(%d) ok\n", state);
1135     }
1136     else {
1137         WMT_WARN_FUNC("new state(%d) fail(%d)\n", state, ret);
1138     }
1139
1140     return ret;
1141 }
1142
1143 static INT32
1144 mt6620_pin_ctrl (
1145     WMT_IC_PIN_ID id,
1146     WMT_IC_PIN_STATE state,
1147     UINT32 flag
1148     )
1149 {
1150     INT32 ret;
1151
1152     WMT_DBG_FUNC("ic pin id:%d, state:%d, flag:0x%x\n", id , state, flag);
1153
1154     ret = -1;
1155     switch (id) {
1156     case WMT_IC_PIN_AUDIO:
1157         ret = mt6620_aif_ctrl(state, flag);
1158         break;
1159
1160     case WMT_IC_PIN_EEDI:
1161         WMT_WARN_FUNC("TBD!!");
1162         ret = -1;
1163         break;
1164
1165     case WMT_IC_PIN_EEDO:
1166         WMT_WARN_FUNC("TBD!!");
1167         ret = -1;
1168         break;
1169     case WMT_IC_PIN_GSYNC:
1170         ret = -1;
1171         WMT_WARN_FUNC("TBD!!");
1172         break;
1173     default:
1174         break;
1175     }
1176     WMT_INFO_FUNC("ret = (%d)\n" , ret);
1177
1178     return ret;
1179 }
1180
1181
1182 static MTK_WCN_BOOL mt6620_quick_sleep_flag_get(VOID)
1183 {
1184     return MTK_WCN_BOOL_FALSE;
1185 }
1186
1187
1188
1189 static INT32
1190 mt6620_ver_check (VOID)
1191 {
1192     UINT32 hw_ver;
1193     UINT32 fw_ver;
1194     INT32 iret;
1195     const WMT_IC_INFO_S *p_info;
1196     UINT32 ctrlPa1;
1197     UINT32 ctrlPa2;
1198
1199     /* 1. identify chip versions: HVR(HW_VER) and FVR(FW_VER) */
1200     WMT_LOUD_FUNC("MT6620: before read hw_ver (hw version)\n");
1201     iret = wmt_core_reg_rw_raw(0, GEN_HVR, &hw_ver, GEN_VER_MASK);
1202     if (iret) {
1203         WMT_ERR_FUNC("MT6620: read hw_ver fail:%d\n", iret);
1204         return -2;
1205     }
1206     WMT_INFO_FUNC("MT6620: read hw_ver (hw version) (0x%x)\n", hw_ver);
1207
1208     WMT_LOUD_FUNC("MT6620: before fw_ver (rom version) \n");
1209     wmt_core_reg_rw_raw(0, GEN_FVR, &fw_ver, GEN_VER_MASK);
1210     if (iret) {
1211         WMT_ERR_FUNC("MT6620: read fw_ver fail:%d\n", iret);
1212         return -2;
1213     }
1214     WMT_INFO_FUNC("MT6620: read fw_ver (rom version) (0x%x)\n", fw_ver);
1215
1216     p_info = mt6620_find_wmt_ic_info(hw_ver);
1217     if (NULL == p_info) {
1218         WMT_ERR_FUNC("MT6620: hw_ver(0x%x) find wmt ic info fail\n");
1219         return -3;
1220     }
1221
1222     WMT_INFO_FUNC("MT6620: wmt ic info: %s.%s (0x%x, WMTHWVER:%d, patch_ext:%s)\n",
1223         p_info->cChipName, p_info->cChipVersion,
1224         p_info->u4HwVer, p_info->eWmtHwVer,
1225         p_info->cPatchNameExt);
1226
1227     /* hw id & version */
1228     ctrlPa1 = (0x00006620UL << 16) | (hw_ver & 0x0000FFFF);
1229     /* translated hw version & fw rom version */
1230     ctrlPa2 = ((UINT32)(p_info->eWmtHwVer) << 16) | (fw_ver & 0x0000FFFF);
1231
1232     iret = wmt_core_ctrl(WMT_CTRL_HWIDVER_SET, &ctrlPa1, &ctrlPa2);
1233     if (iret) {
1234         WMT_WARN_FUNC("MT6620: WMT_CTRL_HWIDVER_SET fail(%d)\n", iret);
1235     }
1236
1237     gp_mt6620_info = p_info;
1238     return 0;
1239 }
1240
1241 static const WMT_IC_INFO_S*
1242 mt6620_find_wmt_ic_info (
1243     const UINT32 hw_ver
1244     )
1245 {
1246     /* match chipversion with u4HwVer item in mt6620_info_table */
1247     const UINT32 size = osal_array_size(mt6620_info_table);
1248     INT32 index;
1249
1250     /* George: reverse the search order to favor newer version products */
1251     // TODO:[FixMe][GeorgeKuo] Remove full match once API wmt_lib_get_hwver() is changed correctly in the future!!
1252     // Leave full match here is a workaround for GPS to distinguish E3/E4 ICs.
1253     index = size - 1;
1254     /* full match */
1255     while ( (0 <= index)
1256         && (hw_ver != mt6620_info_table[index].u4HwVer) /* full match */
1257         ) {
1258         --index;
1259     }
1260     if (0 <= index) {
1261         WMT_INFO_FUNC("found ic info(0x%x) by full match! index:%d\n", hw_ver, index);
1262         return &mt6620_info_table[index];
1263     }
1264
1265     WMT_WARN_FUNC("find no ic info for (0x%x) by full match!try major num match!\n", hw_ver);
1266
1267     /* George: The ONLY CORRECT method to find supported hw table. Match MAJOR
1268      * NUM only can help us support future minor hw ECO, or fab switch, etc.
1269      * FULL matching eliminate such flexibility and software package have to be
1270      * updated EACH TIME even when minor hw ECO or fab switch!!!
1271      */
1272     /* George: reverse the search order to favor newer version products */
1273     index = size - 1;
1274     /* major num match */
1275     while ( (0 <= index)
1276         && (MAJORNUM(hw_ver) != MAJORNUM(mt6620_info_table[index].u4HwVer))
1277         ) {
1278         --index;
1279     }
1280     if (0 <= index) {
1281         WMT_INFO_FUNC("MT6620: found ic info for hw_ver(0x%x) by major num! index:%d\n", hw_ver, index);
1282         return &mt6620_info_table[index];
1283     }
1284
1285     WMT_ERR_FUNC("MT6620: find no ic info for hw_ver(0x%x) by full match nor major num match!\n", hw_ver);
1286     return NULL;
1287 }
1288
1289
1290 static INT32
1291 wmt_stp_init_coex (VOID)
1292 {
1293     INT32 iRet;
1294     UINT32 addr;
1295     WMT_GEN_CONF *pWmtGenConf;
1296
1297     #define COEX_WMT  0
1298     #define COEX_BT   1
1299     #define COEX_WIFI 2
1300     #define COEX_PTA  3
1301     #define COEX_MISC 4
1302
1303     /*Get wmt config*/
1304     iRet = wmt_core_ctrl(WMT_CTRL_GET_WMT_CONF, &addr, 0);
1305     if (iRet) {
1306         WMT_ERR_FUNC("ctrl GET_WMT_CONF fail(%d)\n", iRet);
1307         return -2;
1308     }
1309     WMT_INFO_FUNC("ctrl GET_WMT_CONF ok(0x%08lx)\n", addr);
1310
1311     pWmtGenConf = (P_WMT_GEN_CONF)addr;
1312
1313     /*Check if WMT.cfg exists*/
1314     if (pWmtGenConf->cfgExist == 0) {
1315         WMT_INFO_FUNC("cfgExist == 0, skip config chip\n");
1316         /*if WMT.cfg not existed, still return success and adopt the default value*/
1317         return 0;
1318     }
1319
1320     /*Dump the coex-related info*/
1321     WMT_DBG_FUNC("coex_wmt:0x%x 0x%x 0x%x\n",
1322         pWmtGenConf->coex_wmt_ant_mode,
1323         pWmtGenConf->coex_wmt_wifi_time_ctl,
1324         pWmtGenConf->coex_wmt_ext_pta_dev_on
1325         );
1326     WMT_DBG_FUNC("coex_bt:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1327         pWmtGenConf->coex_bt_rssi_upper_limit,
1328         pWmtGenConf->coex_bt_rssi_mid_limit,
1329         pWmtGenConf->coex_bt_rssi_lower_limit,
1330         pWmtGenConf->coex_bt_pwr_high,
1331         pWmtGenConf->coex_bt_pwr_mid,
1332         pWmtGenConf->coex_bt_pwr_low
1333         );
1334     WMT_DBG_FUNC("coex_wifi:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1335         pWmtGenConf->coex_wifi_rssi_upper_limit,
1336         pWmtGenConf->coex_wifi_rssi_mid_limit,
1337         pWmtGenConf->coex_wifi_rssi_lower_limit,
1338         pWmtGenConf->coex_wifi_pwr_high,
1339         pWmtGenConf->coex_wifi_pwr_mid,
1340         pWmtGenConf->coex_wifi_pwr_low
1341         );
1342     WMT_DBG_FUNC("coex_ext_pta:0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
1343         pWmtGenConf->coex_ext_pta_hi_tx_tag,
1344         pWmtGenConf->coex_ext_pta_hi_rx_tag,
1345         pWmtGenConf->coex_ext_pta_lo_tx_tag,
1346         pWmtGenConf->coex_ext_pta_lo_rx_tag,
1347         pWmtGenConf->coex_ext_pta_sample_t1,
1348         pWmtGenConf->coex_ext_pta_sample_t2,
1349         pWmtGenConf->coex_ext_pta_wifi_bt_con_trx
1350         );
1351     WMT_DBG_FUNC("coex_misc:0x%x 0x%x 0x%x\n",
1352         pWmtGenConf->coex_misc_ext_pta_on,
1353         pWmtGenConf->coex_misc_ext_feature_set
1354         );
1355
1356     /*command adjustion due to WMT.cfg*/
1357     coex_table[COEX_WMT].cmd[5]= pWmtGenConf->coex_wmt_ant_mode;
1358     coex_table[COEX_WMT].cmd[6]= pWmtGenConf->coex_wmt_wifi_time_ctl;
1359     coex_table[COEX_WMT].cmd[7]= pWmtGenConf->coex_wmt_ext_pta_dev_on;
1360     if (gWmtDbgLvl >= WMT_LOG_DBG) {
1361         wmt_core_dump_data(&coex_table[COEX_WMT].cmd[0],
1362             coex_table[COEX_WMT].str,
1363             coex_table[COEX_WMT].cmdSz);
1364     }
1365
1366     coex_table[COEX_BT].cmd[9]=   pWmtGenConf->coex_bt_rssi_upper_limit;
1367     coex_table[COEX_BT].cmd[10]=  pWmtGenConf->coex_bt_rssi_mid_limit;
1368     coex_table[COEX_BT].cmd[11]=  pWmtGenConf->coex_bt_rssi_lower_limit;
1369     coex_table[COEX_BT].cmd[12]=  pWmtGenConf->coex_bt_pwr_high;
1370     coex_table[COEX_BT].cmd[13]=  pWmtGenConf->coex_bt_pwr_mid;
1371     coex_table[COEX_BT].cmd[14]=  pWmtGenConf->coex_bt_pwr_low;
1372     if (gWmtDbgLvl >= WMT_LOG_DBG) {
1373         wmt_core_dump_data(&coex_table[COEX_BT].cmd[0],
1374             coex_table[COEX_BT].str,
1375             coex_table[COEX_BT].cmdSz);
1376     }
1377     coex_table[COEX_WIFI].cmd[10]=   pWmtGenConf->coex_wifi_rssi_upper_limit;
1378     coex_table[COEX_WIFI].cmd[11]=  pWmtGenConf->coex_wifi_rssi_mid_limit;
1379     coex_table[COEX_WIFI].cmd[12]=  pWmtGenConf->coex_wifi_rssi_lower_limit;
1380     coex_table[COEX_WIFI].cmd[13]=  pWmtGenConf->coex_wifi_pwr_high;
1381     coex_table[COEX_WIFI].cmd[14]=  pWmtGenConf->coex_wifi_pwr_mid;
1382     coex_table[COEX_WIFI].cmd[15]=  pWmtGenConf->coex_wifi_pwr_low;
1383     if (gWmtDbgLvl >= WMT_LOG_DBG) {
1384         wmt_core_dump_data(&coex_table[COEX_WIFI].cmd[0],
1385             coex_table[COEX_WIFI].str,
1386             coex_table[COEX_WIFI].cmdSz);
1387     }
1388     coex_table[COEX_PTA].cmd[5]=   pWmtGenConf->coex_ext_pta_hi_tx_tag;
1389     coex_table[COEX_PTA].cmd[6]=   pWmtGenConf->coex_ext_pta_hi_rx_tag;
1390     coex_table[COEX_PTA].cmd[7]=   pWmtGenConf->coex_ext_pta_lo_tx_tag;
1391     coex_table[COEX_PTA].cmd[8]=   pWmtGenConf->coex_ext_pta_lo_rx_tag;
1392     coex_table[COEX_PTA].cmd[9]=   ((pWmtGenConf->coex_ext_pta_sample_t1 & 0xff00) >> 8);
1393     coex_table[COEX_PTA].cmd[10]=  ((pWmtGenConf->coex_ext_pta_sample_t1 & 0x00ff) >> 0);
1394     coex_table[COEX_PTA].cmd[11]=  ((pWmtGenConf->coex_ext_pta_sample_t2 & 0xff00) >> 8);
1395     coex_table[COEX_PTA].cmd[12]=  ((pWmtGenConf->coex_ext_pta_sample_t2 & 0x00ff) >> 0);
1396     coex_table[COEX_PTA].cmd[13]=  pWmtGenConf->coex_ext_pta_wifi_bt_con_trx;
1397     if (gWmtDbgLvl >= WMT_LOG_DBG) {
1398         wmt_core_dump_data(&coex_table[COEX_PTA].cmd[0],
1399             coex_table[COEX_PTA].str,
1400             coex_table[COEX_PTA].cmdSz);
1401     }
1402
1403     osal_memcpy(&coex_table[COEX_MISC].cmd[5], &pWmtGenConf->coex_misc_ext_pta_on, sizeof(pWmtGenConf->coex_misc_ext_pta_on));
1404     osal_memcpy(&coex_table[COEX_MISC].cmd[9], &pWmtGenConf->coex_misc_ext_feature_set, sizeof(pWmtGenConf->coex_misc_ext_feature_set));
1405     if (gWmtDbgLvl >= WMT_LOG_DBG) {
1406         wmt_core_dump_data(& coex_table[COEX_MISC].cmd[0], coex_table[COEX_MISC].str, coex_table[COEX_MISC].cmdSz);
1407     }
1408     iRet = wmt_core_init_script(coex_table, sizeof(coex_table)/sizeof(coex_table[0]));
1409
1410     return iRet;
1411 }
1412
1413 #if CFG_WMT_MULTI_PATCH
1414
1415 static INT32 mt6620_patch_info_prepare(VOID)
1416 {
1417         INT32 iRet = -1;
1418         WMT_CTRL_DATA ctrlData;
1419
1420         ctrlData.ctrlId = WMT_CTRL_PATCH_SEARCH;
1421         iRet = wmt_ctrl(&ctrlData);
1422
1423         return iRet;
1424 }
1425 static INT32
1426 mt6620_patch_dwn (UINT32 index)
1427 {
1428     INT32 iRet = -1;
1429     P_WMT_PATCH patchHdr = NULL;
1430     PUINT8 pbuf = NULL;
1431     UINT32 patchSize = 0;
1432     UINT32 fragSeq = 0;
1433     UINT32 fragNum = 0;
1434     UINT16 fragSize = 0;
1435     UINT16 cmdLen;
1436     UINT32 offset;
1437     UINT32 u4Res;
1438     UINT8 patchevtBuf[8];
1439         UINT8 addressevtBuf[12];
1440         UCHAR addressByte[4];
1441     PCHAR cDataTime = NULL;
1442     /*PCHAR cPlat = NULL;*/
1443     UINT16 u2HwVer = 0;
1444     UINT16 u2SwVer = 0;
1445     UINT32 u4PatchVer = 0;
1446     UINT32 patchSizePerFrag = 0;
1447     WMT_CTRL_DATA ctrlData;
1448
1449     /*1.check hardware information */
1450     if (NULL == gp_mt6620_info) {
1451         WMT_ERR_FUNC("null gp_mt6620_info!\n");
1452         return -1;
1453     }
1454
1455         osal_memset(gFullPatchName,0,osal_sizeof(gFullPatchName));
1456
1457         ctrlData.ctrlId = WMT_CTRL_GET_PATCH_INFO;
1458         ctrlData.au4CtrlData[0] = index + 1;
1459         ctrlData.au4CtrlData[1] = (UINT32)&gFullPatchName;
1460         ctrlData.au4CtrlData[2] = (UINT32)&addressByte;
1461         iRet = wmt_ctrl(&ctrlData);
1462         WMT_INFO_FUNC("the %d time valid patch found: (%s)\n", index+1,gFullPatchName);
1463         //<2.2> read patch content
1464         ctrlData.ctrlId = WMT_CTRL_GET_PATCH;
1465         ctrlData.au4CtrlData[0] = (UINT32)NULL;
1466         ctrlData.au4CtrlData[1] = (UINT32)&gFullPatchName;
1467
1468         ctrlData.au4CtrlData[2] = (UINT32)&pbuf;
1469         ctrlData.au4CtrlData[3] = (UINT32)&patchSize;
1470         iRet = wmt_ctrl(&ctrlData);
1471         if (iRet) {
1472                 WMT_ERR_FUNC("wmt_core: WMT_CTRL_GET_PATCH fail:%d \n", iRet);
1473                 iRet -= 1;
1474                 goto done;
1475         }
1476
1477     /* |<-BCNT_PATCH_BUF_HEADROOM(8) bytes dummy allocated->|<-patch file->| */
1478     pbuf += BCNT_PATCH_BUF_HEADROOM;
1479     /* patch file with header:
1480      * |<-patch header: 28 Bytes->|<-patch body: X Bytes ----->|
1481      */
1482     patchHdr = (P_WMT_PATCH)pbuf;
1483     // check patch file information
1484
1485     cDataTime = patchHdr->ucDateTime;
1486     u2HwVer = patchHdr->u2HwVer;
1487     u2SwVer = patchHdr->u2SwVer;
1488     u4PatchVer = patchHdr->u4PatchVer;
1489     /*cPlat = &patchHdr->ucPLat[0];*/
1490     cDataTime[15] = '\0';
1491
1492     /* remove patch header:
1493     * |<-patch body: X Bytes (X=patchSize)--->|
1494     */
1495     patchSize -= sizeof(WMT_PATCH);
1496     pbuf += sizeof(WMT_PATCH);
1497
1498         if(index == 0)
1499         {
1500             WMT_INFO_FUNC("===========================================\n");
1501             WMT_INFO_FUNC("[Combo Patch] Built Time = %s\n", cDataTime);
1502             WMT_INFO_FUNC("[Combo Patch] Hw Ver = 0x%x\n", ((u2HwVer & 0x00ff) << 8) | ((u2HwVer & 0xff00) >> 8));
1503             WMT_INFO_FUNC("[Combo Patch] Sw Ver = 0x%x\n", ((u2SwVer & 0x00ff) << 8) | ((u2SwVer & 0xff00) >> 8));
1504             WMT_INFO_FUNC("[Combo Patch] Ph Ver = 0x%04x\n",  ((u4PatchVer & 0xff000000) >> 24) | ((u4PatchVer & 0x00ff0000) >> 16));
1505             WMT_INFO_FUNC("[Combo Patch] Platform = %c%c%c%c\n", patchHdr->ucPLat[0],
1506                 patchHdr->ucPLat[1], patchHdr->ucPLat[2], patchHdr->ucPLat[3]);
1507             WMT_INFO_FUNC("[Combo Patch] Content Size = 0x%x\n", patchSize);
1508             WMT_INFO_FUNC("[Combo Patch] Content CRC = 0x%04x\n", osal_crc16(pbuf, patchSize));
1509             WMT_INFO_FUNC("===========================================\n");
1510         }
1511
1512     patchSizePerFrag = (MAJORNUM(gp_mt6620_info->u4HwVer) != 0) ?
1513         DEFAULT_PATCH_FRAG_SIZE : MT6620E2_PATCH_FRAG_SIZE;
1514
1515   /* reserve 1st patch cmd space before patch body
1516      *        |<-WMT_CMD: 5Bytes->|<-patch body: X Bytes (X=patchSize)----->|
1517      */
1518     pbuf -= sizeof(WMT_PATCH_CMD);
1519
1520     fragNum = patchSize / patchSizePerFrag;
1521     fragNum += ((fragNum * patchSizePerFrag) == patchSize) ? 0 : 1;
1522
1523     WMT_DBG_FUNC("patch size(%d) fragNum(%d)\n", patchSize, fragNum);
1524
1525         /*send wmt part patch address command*/
1526         iRet = wmt_core_tx((PUINT8)&WMT_PATCH_ADDRESS_CMD[0],sizeof(WMT_PATCH_ADDRESS_CMD),&u4Res,MTK_WCN_BOOL_FALSE);
1527         if(iRet || (u4Res != sizeof(WMT_PATCH_ADDRESS_CMD)))
1528         {
1529                 WMT_ERR_FUNC("wmt_core:wmt patch address CMD fail(%d),size(%d)\n",iRet,u4Res);
1530                 iRet -= 1;
1531                 goto done;
1532         }
1533         osal_memset(addressevtBuf,0,sizeof(addressevtBuf));
1534         iRet = wmt_core_rx(addressevtBuf,sizeof(WMT_PATCH_ADDRESS_EVT),&u4Res);
1535         if(iRet || (u4Res != sizeof(WMT_PATCH_ADDRESS_EVT)))
1536         {
1537                 WMT_ERR_FUNC("wmt_core:wmt patch address EVT fail(%d),size(%d)\n",iRet,u4Res);
1538                 iRet -= 1;
1539                 goto done;
1540         }
1541 #if CFG_CHECK_WMT_RESULT
1542     if (osal_memcmp(addressevtBuf, WMT_PATCH_ADDRESS_EVT, osal_sizeof(WMT_PATCH_ADDRESS_EVT)) != 0) {
1543         WMT_ERR_FUNC("wmt_core: write WMT_PATCH_ADDRESS_CMD status fail\n");
1544         iRet -= 1;
1545                 goto done;
1546     }
1547 #endif
1548
1549         /*send part patch address command*/
1550         osal_memcpy(&WMT_PATCH_P_ADDRESS_CMD[12], addressByte,osal_sizeof(addressByte));
1551         WMT_INFO_FUNC("4 bytes address command:0x%02x,0x%02x,0x%02x,0x%02x",WMT_PATCH_P_ADDRESS_CMD[12],WMT_PATCH_P_ADDRESS_CMD[13],WMT_PATCH_P_ADDRESS_CMD[14],WMT_PATCH_P_ADDRESS_CMD[15]);
1552         iRet = wmt_core_tx((PUINT8)&WMT_PATCH_P_ADDRESS_CMD[0],sizeof(WMT_PATCH_P_ADDRESS_CMD),&u4Res,MTK_WCN_BOOL_FALSE);
1553         if(iRet || (u4Res != sizeof(WMT_PATCH_P_ADDRESS_CMD)))
1554         {
1555                 WMT_ERR_FUNC("wmt_core:wmt part patch address CMD fail(%d),size(%d),index(%d)\n",iRet,u4Res,index);
1556                 iRet -= 1;
1557                 goto done;
1558         }
1559         osal_memset(addressevtBuf,0,sizeof(addressevtBuf));
1560         iRet = wmt_core_rx(addressevtBuf,sizeof(WMT_PATCH_P_ADDRESS_EVT),&u4Res);
1561         if(iRet || (u4Res != sizeof(WMT_PATCH_P_ADDRESS_EVT)))
1562         {
1563                 WMT_ERR_FUNC("wmt_core:wmt patch address EVT fail(%d),size(%d),index(%d)\n",iRet,u4Res,index);
1564                 iRet -= 1;
1565                 goto done;
1566         }
1567 #if CFG_CHECK_WMT_RESULT
1568     if (osal_memcmp(addressevtBuf, WMT_PATCH_P_ADDRESS_EVT, osal_sizeof(WMT_PATCH_ADDRESS_EVT)) != 0) {
1569         WMT_ERR_FUNC("wmt_core: write WMT_PATCH_ADDRESS_CMD status fail,index(%d)\n",index);
1570         iRet -= 1;
1571                 goto done;
1572     }
1573 #endif
1574     /* send all fragments */
1575     offset = sizeof(WMT_PATCH_CMD);
1576     fragSeq = 0;
1577     while (fragSeq < fragNum) {
1578         WMT_DBG_FUNC("patch size(%d) fragNum(%d)\n", patchSize, fragNum);
1579         if (fragSeq == (fragNum-1)) {
1580             /* last fragment */
1581             fragSize = patchSize - fragSeq * patchSizePerFrag;
1582             WMT_PATCH_CMD[4] = WMT_PATCH_FRAG_LAST;
1583         }
1584         else {
1585             fragSize = patchSizePerFrag;
1586             WMT_PATCH_CMD[4] = (fragSeq == 0) ? WMT_PATCH_FRAG_1ST: WMT_PATCH_FRAG_MID;
1587         }
1588         /* update length field in CMD:flag+frag*/
1589         cmdLen = 1 + fragSize;
1590         osal_memcpy(&WMT_PATCH_CMD[2], &cmdLen, 2);
1591         /* copy patch CMD to buf (overwrite last 5-byte in prev frag) */
1592         osal_memcpy(pbuf + offset - sizeof(WMT_PATCH_CMD), WMT_PATCH_CMD, sizeof(WMT_PATCH_CMD));
1593
1594         //iRet = (*kal_stp_tx)(pbuf + offset - sizeof(WMT_PATCH_CMD), fragSize + sizeof(WMT_PATCH_CMD), &u4Res);
1595         iRet = wmt_core_tx(pbuf + offset - sizeof(WMT_PATCH_CMD), fragSize + sizeof(WMT_PATCH_CMD), &u4Res, MTK_WCN_BOOL_FALSE);
1596         if (iRet || (u4Res != fragSize + sizeof(WMT_PATCH_CMD))) {
1597             WMT_ERR_FUNC("wmt_core: write fragSeq(%d) size(%d, %d) fail(%d)\n", fragSeq, fragSize + sizeof(WMT_PATCH_CMD), u4Res, iRet );
1598             iRet = -4;
1599             break;
1600         }
1601         WMT_DBG_FUNC("wmt_core: write fragSeq(%d) size(%d, %d) ok\n",
1602             fragSeq, fragSize + sizeof(WMT_PATCH_CMD), u4Res);
1603
1604         osal_memset(patchevtBuf, 0, sizeof(patchevtBuf));
1605         //iRet = (*kal_stp_rx)(evtBuf, sizeof(WMT_PATCH_EVT), &u4Res);
1606         iRet = wmt_core_rx(patchevtBuf, sizeof(WMT_PATCH_EVT), &u4Res);
1607         if (iRet || (u4Res != sizeof(WMT_PATCH_EVT))) {
1608             WMT_ERR_FUNC("wmt_core: read WMT_PATCH_EVT length(%d, %d) fail(%d)\n", sizeof(WMT_PATCH_EVT), u4Res, iRet);
1609             iRet = -5;
1610             break;
1611         }
1612 #if CFG_CHECK_WMT_RESULT
1613         if (osal_memcmp(patchevtBuf, WMT_PATCH_EVT, sizeof(WMT_PATCH_EVT)) != 0) {
1614             WMT_ERR_FUNC("wmt_core: compare WMT_PATCH_EVT result error rx(%d):[%02X,%02X,%02X,%02X,%02X] exp(%d):[%02X,%02X,%02X,%02X,%02X]\n",
1615                 u4Res, patchevtBuf[0], patchevtBuf[1], patchevtBuf[2], patchevtBuf[3], patchevtBuf[4], sizeof(WMT_PATCH_EVT), WMT_PATCH_EVT[0], WMT_PATCH_EVT[1], WMT_PATCH_EVT[2], WMT_PATCH_EVT[3], WMT_PATCH_EVT[4]);
1616             iRet = -6;
1617             break;
1618         }
1619 #endif
1620         WMT_DBG_FUNC("wmt_core: read WMT_PATCH_EVT length(%d, %d) ok\n",
1621             sizeof(WMT_PATCH_EVT), u4Res);
1622
1623 #if 0
1624         WMT_DBG_FUNC("wmt_core: send patch frag(%d) [%02X,%02X,%02X,%02X,%02X] (%d) ok",
1625             fragSeq, WMT_PATCH_CMD[0], WMT_PATCH_CMD[1], WMT_PATCH_CMD[2],
1626             WMT_PATCH_CMD[3], WMT_PATCH_CMD[4], fragSize);
1627 #endif
1628
1629         offset += patchSizePerFrag;
1630         ++fragSeq;
1631     }
1632
1633     WMT_INFO_FUNC("wmt_core: patch dwn:%d frag(%d, %d) %s\n",
1634         iRet, fragSeq, fragSize, (!iRet && (fragSeq == fragNum)) ? "ok": "fail");
1635
1636     if (fragSeq != fragNum) {
1637         iRet = -7;
1638     }
1639 done:
1640     /* WMT_CTRL_FREE_PATCH always return 0 */
1641         ctrlData.ctrlId = WMT_CTRL_FREE_PATCH;
1642         ctrlData.au4CtrlData[0] = index + 1;
1643         wmt_ctrl(&ctrlData);
1644     //wmt_core_ctrl(WMT_CTRL_FREE_PATCH, NULL, NULL);
1645     if ( (iRet == -2) || (iRet == -3) ) {
1646         /*no patch found or patch version does not match with hw version, we check if patch is mandatory or not, if yes, return iRet, if not return 0*/
1647         if (MTK_WCN_BOOL_FALSE != gp_mt6620_info->bWorkWithoutPatch) {
1648             iRet = 0;
1649         }
1650     }
1651
1652     return iRet;
1653 }
1654
1655
1656 #else
1657 static INT32
1658 mt6620_patch_dwn (VOID)
1659 {
1660     INT32 iRet = -1;
1661     P_WMT_PATCH patchHdr;
1662     PUINT8 pbuf;
1663     UINT32 patchSize;
1664     UINT32 fragSeq;
1665     UINT32 fragNum;
1666     UINT16 fragSize = 0;
1667     UINT16 cmdLen;
1668     UINT32 offset;
1669     UINT32 u4Res;
1670     UINT8 evtBuf[8];
1671     PCHAR cDataTime = NULL;
1672     /*PCHAR cPlat = NULL;*/
1673     UINT16 u2HwVer = 0;
1674     UINT16 u2SwVer = 0;
1675     UINT32 u4PatchVer = 0;
1676     UINT32 patchSizePerFrag = 0;
1677     WMT_CTRL_DATA ctrlData;
1678
1679     /*1.check hardware information */
1680     if (NULL == gp_mt6620_info) {
1681         WMT_ERR_FUNC("null gp_mt6620_info!\n");
1682         return -1;
1683     }
1684 #if 0
1685                 ctrlData.ctrlId = WMT_CTRL_GET_PATCH_NAME;
1686                 ctrlData.au4CtrlData[0] = (UINT32)&gDefPatchName;
1687                 iRet = wmt_ctrl(&ctrlData);
1688
1689                 if (mt6620_update_patch_name()) {
1690                         WMT_ERR_FUNC("invalid patch name, ommit patch download process.\n");
1691                         return -1;
1692                 }
1693
1694                 ctrlData.ctrlId = WMT_CTRL_GET_PATCH;
1695                 ctrlData.au4CtrlData[0] = (UINT32)&gDefPatchName;
1696                 ctrlData.au4CtrlData[1] = (UINT32)&gFullPatchName;
1697                 ctrlData.au4CtrlData[2] = (UINT32)&pbuf;
1698                 ctrlData.au4CtrlData[3] = (UINT32)&patchSize;
1699                 iRet = wmt_ctrl(&ctrlData);
1700                 if (iRet) {
1701                         WMT_ERR_FUNC("wmt_core: WMT_CTRL_GET_PATCH fail:%d \n", iRet);
1702                         iRet = -2;
1703                         goto done;
1704                 }
1705 #else
1706                 //<2> search patch and read patch content
1707                 //<2.1> search patch
1708                 ctrlData.ctrlId = WMT_CTRL_PATCH_SEARCH;
1709                 iRet = wmt_ctrl(&ctrlData);
1710                 if (0 == iRet)
1711                 {
1712                         //patch with correct Hw Ver Major Num found
1713                         ctrlData.ctrlId = WMT_CTRL_GET_PATCH_NAME;
1714                         ctrlData.au4CtrlData[0] = (UINT32)&gFullPatchName;
1715                         iRet = wmt_ctrl(&ctrlData);
1716
1717                         WMT_INFO_FUNC("valid patch found: (%s)\n", gFullPatchName);
1718                         //<2.2> read patch content
1719                         ctrlData.ctrlId = WMT_CTRL_GET_PATCH;
1720                         ctrlData.au4CtrlData[0] = (UINT32)NULL;
1721                         ctrlData.au4CtrlData[1] = (UINT32)&gFullPatchName;
1722
1723                 }
1724                 else
1725                 {
1726                         iRet -= 1;
1727                         return iRet;
1728                 }
1729                 ctrlData.au4CtrlData[2] = (UINT32)&pbuf;
1730                 ctrlData.au4CtrlData[3] = (UINT32)&patchSize;
1731                 iRet = wmt_ctrl(&ctrlData);
1732                 if (iRet) {
1733                         WMT_ERR_FUNC("wmt_core: WMT_CTRL_GET_PATCH fail:%d \n", iRet);
1734                         iRet -= 1;
1735                         goto done;
1736                 }
1737
1738 #endif
1739
1740     /* |<-BCNT_PATCH_BUF_HEADROOM(8) bytes dummy allocated->|<-patch file->| */
1741     pbuf += BCNT_PATCH_BUF_HEADROOM;
1742     /* patch file with header:
1743      * |<-patch header: 28 Bytes->|<-patch body: X Bytes ----->|
1744      */
1745     patchHdr = (P_WMT_PATCH)pbuf;
1746     // check patch file information
1747
1748     cDataTime = patchHdr->ucDateTime;
1749     u2HwVer = patchHdr->u2HwVer;
1750     u2SwVer = patchHdr->u2SwVer;
1751     u4PatchVer = patchHdr->u4PatchVer;
1752     /*cPlat = &patchHdr->ucPLat[0];*/
1753
1754     cDataTime[15] = '\0';
1755
1756     /* remove patch header:
1757     * |<-patch body: X Bytes (X=patchSize)--->|
1758     */
1759     patchSize -= sizeof(WMT_PATCH);
1760     pbuf += sizeof(WMT_PATCH);
1761     WMT_INFO_FUNC("===========================================\n");
1762     WMT_INFO_FUNC("[Combo Patch] Built Time = %s\n", cDataTime);
1763     WMT_INFO_FUNC("[Combo Patch] Hw Ver = 0x%x\n", ((u2HwVer & 0x00ff) << 8) | ((u2HwVer & 0xff00) >> 8));
1764     WMT_INFO_FUNC("[Combo Patch] Sw Ver = 0x%x\n", ((u2SwVer & 0x00ff) << 8) | ((u2SwVer & 0xff00) >> 8));
1765     WMT_INFO_FUNC("[Combo Patch] Ph Ver = 0x%04x\n",  ((u4PatchVer & 0xff000000) >> 24) | ((u4PatchVer & 0x00ff0000) >> 16));
1766     WMT_INFO_FUNC("[Combo Patch] Platform = %c%c%c%c\n", patchHdr->ucPLat[0],
1767         patchHdr->ucPLat[1], patchHdr->ucPLat[2], patchHdr->ucPLat[3]);
1768     WMT_INFO_FUNC("[Combo Patch] Content Size = 0x%x\n", patchSize);
1769     WMT_INFO_FUNC("[Combo Patch] Content CRC = 0x%04x\n", osal_crc16(pbuf, patchSize));
1770     WMT_INFO_FUNC("===========================================\n");
1771
1772     patchSizePerFrag = (MAJORNUM(gp_mt6620_info->u4HwVer) != 0) ?
1773         DEFAULT_PATCH_FRAG_SIZE : MT6620E2_PATCH_FRAG_SIZE;
1774
1775   /* reserve 1st patch cmd space before patch body
1776      *        |<-WMT_CMD: 5Bytes->|<-patch body: X Bytes (X=patchSize)----->|
1777      */
1778     pbuf -= sizeof(WMT_PATCH_CMD);
1779
1780     fragNum = patchSize / patchSizePerFrag;
1781     fragNum += ((fragNum * patchSizePerFrag) == patchSize) ? 0 : 1;
1782
1783     WMT_DBG_FUNC("patch size(%d) fragNum(%d)\n", patchSize, fragNum);
1784
1785
1786     /* send all fragments */
1787     offset = sizeof(WMT_PATCH_CMD);
1788     fragSeq = 0;
1789     while (fragSeq < fragNum) {
1790         WMT_DBG_FUNC("patch size(%d) fragNum(%d)\n", patchSize, fragNum);
1791         if (fragSeq == (fragNum-1)) {
1792             /* last fragment */
1793             fragSize = patchSize - fragSeq * patchSizePerFrag;
1794             WMT_PATCH_CMD[4] = WMT_PATCH_FRAG_LAST;
1795         }
1796         else {
1797             fragSize = patchSizePerFrag;
1798             WMT_PATCH_CMD[4] = (fragSeq == 0) ? WMT_PATCH_FRAG_1ST: WMT_PATCH_FRAG_MID;
1799         }
1800         /* update length field in CMD:flag+frag*/
1801         cmdLen = 1 + fragSize;
1802         osal_memcpy(&WMT_PATCH_CMD[2], &cmdLen, 2);
1803         /* copy patch CMD to buf (overwrite last 5-byte in prev frag) */
1804         osal_memcpy(pbuf + offset - sizeof(WMT_PATCH_CMD), WMT_PATCH_CMD, sizeof(WMT_PATCH_CMD));
1805
1806         //iRet = (*kal_stp_tx)(pbuf + offset - sizeof(WMT_PATCH_CMD), fragSize + sizeof(WMT_PATCH_CMD), &u4Res);
1807         iRet = wmt_core_tx(pbuf + offset - sizeof(WMT_PATCH_CMD), fragSize + sizeof(WMT_PATCH_CMD), &u4Res, MTK_WCN_BOOL_FALSE);
1808         if (iRet || (u4Res != fragSize + sizeof(WMT_PATCH_CMD))) {
1809             WMT_ERR_FUNC("wmt_core: write fragSeq(%d) size(%d, %d) fail(%d)\n", fragSeq, fragSize + sizeof(WMT_PATCH_CMD), u4Res, iRet );
1810             iRet = -4;
1811             break;
1812         }
1813         WMT_DBG_FUNC("wmt_core: write fragSeq(%d) size(%d, %d) ok\n",
1814             fragSeq, fragSize + sizeof(WMT_PATCH_CMD), u4Res);
1815
1816         osal_memset(evtBuf, 0, sizeof(evtBuf));
1817         //iRet = (*kal_stp_rx)(evtBuf, sizeof(WMT_PATCH_EVT), &u4Res);
1818         iRet = wmt_core_rx(evtBuf, sizeof(WMT_PATCH_EVT), &u4Res);
1819         if (iRet || (u4Res != sizeof(WMT_PATCH_EVT))) {
1820             WMT_ERR_FUNC("wmt_core: read WMT_PATCH_EVT length(%d, %d) fail(%d)\n", sizeof(WMT_PATCH_EVT), u4Res, iRet);
1821             iRet = -5;
1822             break;
1823         }
1824 #if CFG_CHECK_WMT_RESULT
1825         if (osal_memcmp(evtBuf, WMT_PATCH_EVT, sizeof(WMT_PATCH_EVT)) != 0) {
1826             WMT_ERR_FUNC("wmt_core: compare WMT_PATCH_EVT result error rx(%d):[%02X,%02X,%02X,%02X,%02X] exp(%d):[%02X,%02X,%02X,%02X,%02X]\n",
1827                 u4Res, evtBuf[0], evtBuf[1], evtBuf[2], evtBuf[3], evtBuf[4], sizeof(WMT_PATCH_EVT), WMT_PATCH_EVT[0], WMT_PATCH_EVT[1], WMT_PATCH_EVT[2], WMT_PATCH_EVT[3], WMT_PATCH_EVT[4]);
1828             iRet = -6;
1829             break;
1830         }
1831 #endif
1832         WMT_DBG_FUNC("wmt_core: read WMT_PATCH_EVT length(%d, %d) ok\n",
1833             sizeof(WMT_PATCH_EVT), u4Res);
1834
1835 #if 0
1836         WMT_DBG_FUNC("wmt_core: send patch frag(%d) [%02X,%02X,%02X,%02X,%02X] (%d) ok",
1837             fragSeq, WMT_PATCH_CMD[0], WMT_PATCH_CMD[1], WMT_PATCH_CMD[2],
1838             WMT_PATCH_CMD[3], WMT_PATCH_CMD[4], fragSize);
1839 #endif
1840
1841         offset += patchSizePerFrag;
1842         ++fragSeq;
1843     }
1844
1845     WMT_INFO_FUNC("wmt_core: patch dwn:%d frag(%d, %d) %s\n",
1846         iRet, fragSeq, fragSize, (!iRet && (fragSeq == fragNum)) ? "ok": "fail");
1847
1848     if (fragSeq != fragNum) {
1849         iRet = -7;
1850     }
1851 done:
1852     /* WMT_CTRL_FREE_PATCH always return 0 */
1853     wmt_core_ctrl(WMT_CTRL_FREE_PATCH, NULL, NULL);
1854     if ( (iRet == -2) || (iRet == -3) ) {
1855         /*no patch found or patch version does not match with hw version, we check if patch is mandatory or not, if yes, return iRet, if not return 0*/
1856         if (MTK_WCN_BOOL_FALSE != gp_mt6620_info->bWorkWithoutPatch) {
1857             iRet = 0;
1858         }
1859     }
1860
1861     return iRet;
1862 }
1863
1864 static INT32
1865 mt6620_update_patch_name (VOID)
1866 {
1867     INT32 len;
1868     UCHAR cTmpPatchName[NAME_MAX + 1] = {0};
1869
1870     /*init.get hardware version */
1871     // TODO:[FixMe][GeorgeKuo]: check using memcpy or strncpy???
1872     /*osal_memcpy (gFullPatchName, gDefPatchName, osal_strlen(gDefPatchName));*/
1873     osal_strncpy(gFullPatchName, gDefPatchName, osal_sizeof(gFullPatchName));
1874
1875     /*1.check hardware information */
1876     if (NULL == gp_mt6620_info) {
1877         WMT_ERR_FUNC("null gp_mt6620_info!\n");
1878         osal_memset(gFullPatchName, 0, osal_sizeof(gFullPatchName));
1879         return -1;
1880     }
1881
1882     /*2.make possible firmware patch name with original name and hardware version*/
1883     if ( (osal_strlen(gDefPatchName) > osal_strlen(WMT_IC_PATCH_TAIL))
1884         && ((osal_strlen(gDefPatchName) + osal_strlen(WMT_IC_PATCH_DUMMY_EXT) <= NAME_MAX))
1885         ) {
1886         len = osal_strlen(gDefPatchName) - osal_strlen(WMT_IC_PATCH_TAIL);
1887         osal_memcpy (cTmpPatchName, gDefPatchName, len > NAME_MAX ? NAME_MAX : len);
1888         osal_memcpy (cTmpPatchName + osal_strlen(cTmpPatchName), gp_mt6620_info->cPatchNameExt, osal_strlen(gp_mt6620_info->cPatchNameExt));
1889         osal_memcpy (cTmpPatchName + osal_strlen(cTmpPatchName), WMT_IC_PATCH_TAIL, osal_strlen(WMT_IC_PATCH_TAIL));
1890         cTmpPatchName[osal_strlen(cTmpPatchName)] = '\0';
1891     }
1892     else {
1893         WMT_ERR_FUNC("invalid default firmware patch name (%s)\n", gDefPatchName);
1894         osal_memset(gFullPatchName, 0, osal_sizeof(gFullPatchName));
1895         return -2;
1896     }
1897
1898     /*patch with versioned name exist , update cFullPatchName with full named patch*/
1899     osal_memcpy (gFullPatchName, cTmpPatchName, osal_strlen(cTmpPatchName));
1900     *(gFullPatchName + osal_strlen(cTmpPatchName)) = '\0';
1901     WMT_INFO_FUNC("full firmware patch name: %s\n", cTmpPatchName);
1902
1903     return 0;
1904 }
1905 #endif
1906