2 \brief Declaration of library functions
4 Any definitions in this file will be shared among GLUE Layer and internal Driver Stack.
16 //TODO: [GeorgeKuo][FixMe] remove temporarily
17 //#include "mtk_wcn_cmb_stub.h" /* for AIF state definition */
19 /*******************************************************************************
20 * C O M P I L E R F L A G S
21 ********************************************************************************
23 #if defined(MT6620E3) || defined(MT6620E6) //need modify this part
24 #define CFG_CORE_MT6620_SUPPORT 1 /* whether MT6620 is supported or not */
26 #define CFG_CORE_MT6620_SUPPORT 1 /* whether MT6620 is supported or not */
30 #define CFG_CORE_MT6628_SUPPORT 1 /* whether MT6628 is supported or not */
32 #define CFG_CORE_MT6628_SUPPORT 1 /* whether MT6628 is supported or not */
35 // TODO:[ChangeFeature][George] move this definition outside so that wmt_dev can remove wmt_core.h inclusion.
36 #define defaultPatchName "mt66xx_patch_hdr.bin"
39 /*******************************************************************************
41 ********************************************************************************
44 #define BCNT_PATCH_BUF_HEADROOM (8)
46 #define DWCNT_HIF_CONF (4)
47 #define DWCNT_STRAP_CONF (4)
48 #define DWCNT_RESERVED (8)
49 #define DWCNT_CTRL_DATA (16)
52 #if 0 // TODO: [obsolete][GeorgeKuo]: remove ubsolete definitions
55 #define WMT_PKT_FMT_RAW (1)
56 #define WMT_PKT_FMT_STP (0)
59 #define WMT_FUNC_CTRL_ON (MTK_WCN_BOOL_TRUE)
60 #define WMT_FUNC_CTRL_OFF (MTK_WCN_BOOL_FALSE)
62 #define WMT_HDR_LEN (4) /* header length */
63 #define WMT_STS_LEN (1) /* status length */
64 #define WMT_FLAG_LEN (1)
65 #define WMT_HIF_UART_INFO_LEN (4)
66 #define WMT_FUNC_CTRL_PARAM_LEN (1)
67 #define WMT_LPBK_CMD_LEN (5)
68 #define WMT_LPBK_BUF_LEN (1024+WMT_LPBK_CMD_LEN)
69 #define WMT_DEFAULT_BAUD_RATE (115200)
71 #define INIT_CMD(c, e, s) {.cmd= c, .cmdSz=sizeof(c), .evt=e, .evtSz=sizeof(e), .str=s}
73 /*******************************************************************************
74 * E X T E R N A L R E F E R E N C E S
75 ********************************************************************************
78 /*******************************************************************************
80 ********************************************************************************
83 /*******************************************************************************
85 ********************************************************************************
88 typedef enum _ENUM_WMT_FM_T
94 } ENUM_WMT_FM_T, *P_ENUM_WMT_FM_T;
96 typedef enum _ENUM_WMT_HIF_T
101 } ENUM_WMT_HIF_T, *P_ENUM_WMT_HIF_T;
103 #if 0 /* [George] moved to wmt_exp.h for hif_sdio's use */
105 WMT_SDIO_SLOT_INVALID = 0,
106 WMT_SDIO_SLOT_SDIO1 = 1, /* Wi-Fi dedicated SDIO1*/
107 WMT_SDIO_SLOT_SDIO2 = 2,
112 WMT_SDIO_FUNC_STP = 0,
113 WMT_SDIO_FUNC_WIFI = 1,
115 } WMT_SDIO_FUNC_TYPE;
118 typedef enum _ENUM_WMT_OPID_T {
119 WMT_OPID_HIF_CONF = 0,
121 WMT_OPID_PWR_OFF = 2,
122 WMT_OPID_FUNC_ON = 3,
123 WMT_OPID_FUNC_OFF = 4,
124 WMT_OPID_REG_RW = 5, // TODO:[ChangeFeature][George] is this OP obsoleted?
129 WMT_OPID_CMD_TEST = 10,
130 WMT_OPID_HW_RST = 11,
131 WMT_OPID_SW_RST = 12,
132 WMT_OPID_BAUD_RST = 13,
133 WMT_OPID_STP_RST = 14,
134 WMT_OPID_THERM_CTRL = 15,
135 WMT_OPID_EFUSE_RW = 16,
136 WMT_OPID_GPIO_CTRL = 17,
137 WMT_OPID_SDIO_CTRL = 18,
138 WMT_OPID_FW_COREDMP = 19,
139 WMT_OPID_GPIO_STATE = 20,
141 } ENUM_WMT_OPID_T, *P_ENUM_WMT_OPID_T;
143 typedef OSAL_OP_DAT WMT_OP;
144 typedef P_OSAL_OP_DAT P_WMT_OP;
146 typedef enum _ENUM_WMT_UART_FC_T
149 WMT_UART_MTK_SW_FC = 1,
150 WMT_UART_LUX_SW_FC = 2,
153 } ENUM_WMT_UART_FC_T, *P_ENUM_UART_FC_T;
156 typedef struct _WMT_HIF_CONF {
157 UINT32 hifType; // HIF Type
158 UINT32 uartFcCtrl; // UART FC config
159 UINT32 au4HifConf[DWCNT_HIF_CONF]; // HIF Config
160 UINT32 au4StrapConf[DWCNT_STRAP_CONF]; // Strap Config
161 } WMT_HIF_CONF, *P_WMT_HIF_CONF;
163 typedef INT32 (*WMT_OPID_FUNC)(P_WMT_OP);
165 typedef struct _WMT_GEN_CONF {
168 UCHAR coex_wmt_ant_mode;
169 UCHAR coex_wmt_wifi_time_ctl;
170 UCHAR coex_wmt_ext_pta_dev_on;
172 UCHAR coex_bt_rssi_upper_limit;
173 UCHAR coex_bt_rssi_mid_limit;
174 UCHAR coex_bt_rssi_lower_limit;
175 UCHAR coex_bt_pwr_high;
176 UCHAR coex_bt_pwr_mid;
177 UCHAR coex_bt_pwr_low;
179 UCHAR coex_wifi_rssi_upper_limit;
180 UCHAR coex_wifi_rssi_mid_limit;
181 UCHAR coex_wifi_rssi_lower_limit;
182 UCHAR coex_wifi_pwr_high;
183 UCHAR coex_wifi_pwr_mid;
184 UCHAR coex_wifi_pwr_low;
186 UCHAR coex_ext_pta_hi_tx_tag;
187 UCHAR coex_ext_pta_hi_rx_tag;
188 UCHAR coex_ext_pta_lo_tx_tag;
189 UCHAR coex_ext_pta_lo_rx_tag;
190 UINT16 coex_ext_pta_sample_t1;
191 UINT16 coex_ext_pta_sample_t2;
192 UCHAR coex_ext_pta_wifi_bt_con_trx;
194 UINT32 coex_misc_ext_pta_on;
195 UINT32 coex_misc_ext_feature_set;
197 UCHAR wmt_gps_lna_pin;
198 UCHAR wmt_gps_lna_enable;
199 /*Power on sequence*/
200 UCHAR pwr_on_rtc_slot;
201 UCHAR pwr_on_ldo_slot;
202 UCHAR pwr_on_rst_slot;
203 UCHAR pwr_on_off_slot;
204 UCHAR pwr_on_on_slot;
207 /* Combo chip side SDIO driving setting */
208 UINT32 sdio_driving_cfg;
210 } WMT_GEN_CONF, *P_WMT_GEN_CONF;
212 typedef enum _ENUM_DRV_STS_ {
215 DRV_STS_UNREG = 1, /* Initial State */
217 DRV_STS_POWER_OFF = 0, /* initial state */
218 DRV_STS_POWER_ON = 1, /* powered on, only WMT */
219 DRV_STS_FUNC_ON = 2, /* FUNC ON */
221 } ENUM_DRV_STS, *P_ENUM_DRV_STS;
223 typedef enum _WMT_IC_PIN_ID_
225 WMT_IC_PIN_AUDIO = 0,
228 WMT_IC_PIN_GSYNC = 3,
230 }WMT_IC_PIN_ID, *P_WMT_IC_PIN_ID;
233 typedef enum _WMT_IC_PIN_STATE_
237 WMT_IC_AIF_0 = 2, // = CMB_STUB_AIF_0,
238 WMT_IC_AIF_1 = 3, // = CMB_STUB_AIF_1,
239 WMT_IC_AIF_2 = 4, // = CMB_STUB_AIF_2,
240 WMT_IC_AIF_3 = 5, // = CMB_STUB_AIF_3,
243 WMT_IC_PIN_GPIO_HIGH = 8,
244 WMT_IC_PIN_GPIO_LOW = 8,
246 } WMT_IC_PIN_STATE, *P_WMT_IC_PIN_STATE;
248 typedef enum _WMT_CO_CLOCK_
250 WMT_CO_CLOCK_DIS = 0,
253 } WMT_CO_CLOCK, *P_WMT_CO_CLOCK;
256 typedef INT32 (*SW_INIT)(P_WMT_HIF_CONF pWmtHifConf);
257 typedef INT32 (*SW_DEINIT)(P_WMT_HIF_CONF pWmtHifConf);
258 typedef INT32 (*IC_PIN_CTRL)(WMT_IC_PIN_ID id, WMT_IC_PIN_STATE state, UINT32 flag);
259 typedef INT32 (*IC_VER_CHECK)(VOID);
260 typedef INT32 (*CO_CLOCK_CTRL)(WMT_CO_CLOCK on);
261 typedef MTK_WCN_BOOL(*IS_QUICK_SLEEP_SUPPORT)(VOID);
262 typedef MTK_WCN_BOOL(*IS_AEE_DUMP_SUPPORT)(VOID);
265 typedef struct _WMT_IC_OPS_ {
269 IC_PIN_CTRL ic_pin_ctrl;
270 IC_VER_CHECK ic_ver_check;
271 CO_CLOCK_CTRL co_clock_ctrl;
272 IS_QUICK_SLEEP_SUPPORT is_quick_sleep;
273 IS_AEE_DUMP_SUPPORT is_aee_dump_support;
274 } WMT_IC_OPS, *P_WMT_IC_OPS;
276 typedef struct _WMT_CTX_
278 ENUM_DRV_STS eDrvStatus[WMTDRV_TYPE_MAX]; /* Controlled driver status */
279 UINT32 wmtInfoBit; /* valid info bit */
280 WMT_HIF_CONF wmtHifConf; /* HIF information */
282 /* Pointer to WMT_IC_OPS. Shall be assigned to a correct table in stp_init
283 * if and only if getting chip id successfully. hwver and fwver are kept in
284 * WMT-IC module only.
286 P_WMT_IC_OPS p_ic_ops;
287 } WMT_CTX, *P_WMT_CTX;
289 // TODO:[ChangeFeature][George] remove WMT_PKT. replace it with hardcoded arrays.
290 // Using this struct relies on compiler's implementation and pack() settings
291 typedef struct _WMT_PKT_ {
292 UINT8 eType; // PKT_TYPE_*
293 UINT8 eOpCode; // OPCODE_*
294 UINT16 u2SduLen; // 2 bytes length, little endian
296 } WMT_PKT, *P_WMT_PKT;
298 /* WMT Packet Format */
299 typedef enum _ENUM_PKT_TYPE {
300 PKT_TYPE_INVALID = 0,
304 } ENUM_PKT_TYPE, *P_ENUM_PKT_TYPE;
306 typedef enum _ENUM_OPCODE {
312 OPCODE_STRAP_CONF = 5,
313 OPCODE_FUNC_CTRL = 6,
317 } ENUM_OPCODE, *P_ENUM_OPCODE;
321 WMT_STP_CONF_RDY = 1,
322 WMT_STP_CONF_MODE = 2,
334 typedef struct _WMT_PATCH {
335 UINT8 ucDateTime[16];
340 } WMT_PATCH, *P_WMT_PATCH;
343 /*******************************************************************************
344 * P U B L I C D A T A
345 ********************************************************************************
348 /*******************************************************************************
349 * P R I V A T E D A T A
350 ********************************************************************************
353 /*******************************************************************************
354 * F U N C T I O N D E C L A R A T I O N S
355 ********************************************************************************
358 extern INT32 wmt_core_init(VOID);
359 extern INT32 wmt_core_deinit(VOID);
361 /*****************************************************************************
369 * INT32 0 = success, others = failure
370 *****************************************************************************/
378 ENUM_WMT_CTRL_T ctrId,
384 wmt_core_func_ctrl_cmd (
385 ENUM_WMTDRV_TYPE_T type,
390 wmt_core_reg_rw_raw (
405 wmt_core_patch_check (
411 wmt_core_init_script (
412 struct init_script *script,
428 MTK_WCN_BOOL bRawFlag
430 extern MTK_WCN_BOOL wmt_core_is_quick_ps_support (void);
432 extern MTK_WCN_BOOL wmt_core_get_aee_dump_flag(void);
435 /*******************************************************************************
437 ********************************************************************************
440 static _osal_inline_ MTK_WCN_BOOL
441 wmt_core_ic_ops_check (
446 return MTK_WCN_BOOL_FALSE;
448 if ( (NULL == p_ops->sw_init)
449 || (NULL == p_ops->sw_deinit)
450 || (NULL == p_ops->ic_ver_check)
451 || (NULL == p_ops->ic_pin_ctrl) ) {
452 return MTK_WCN_BOOL_FALSE;
455 return MTK_WCN_BOOL_TRUE;
459 #endif /* _WMT_CORE_H_ */