drivers/mtd/nand/sunxi_nand.c

   1 /*
   2  * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
   3  *
   4  * Derived from:
   5  *      https://github.com/yuq/sunxi-nfc-mtd
   6  *      Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
   7  *
   8  *      https://github.com/hno/Allwinner-Info
   9  *      Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
  10  *
  11  *      Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
  12  *      Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/of.h>
  31 #include <linux/of_device.h>
  32 #include <linux/of_gpio.h>
  33 #include <linux/of_mtd.h>
  34 #include <linux/mtd/mtd.h>
  35 #include <linux/mtd/nand.h>
  36 #include <linux/mtd/partitions.h>
  37 #include <linux/clk.h>
  38 #include <linux/delay.h>
  39 #include <linux/dmaengine.h>
  40 #include <linux/gpio.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/io.h>
  43
  44 #define NFC_REG_CTL             0x0000
  45 #define NFC_REG_ST              0x0004
  46 #define NFC_REG_INT             0x0008
  47 #define NFC_REG_TIMING_CTL      0x000C
  48 #define NFC_REG_TIMING_CFG      0x0010
  49 #define NFC_REG_ADDR_LOW        0x0014
  50 #define NFC_REG_ADDR_HIGH       0x0018
  51 #define NFC_REG_SECTOR_NUM      0x001C
  52 #define NFC_REG_CNT             0x0020
  53 #define NFC_REG_CMD             0x0024
  54 #define NFC_REG_RCMD_SET        0x0028
  55 #define NFC_REG_WCMD_SET        0x002C
  56 #define NFC_REG_IO_DATA         0x0030
  57 #define NFC_REG_ECC_CTL         0x0034
  58 #define NFC_REG_ECC_ST          0x0038
  59 #define NFC_REG_DEBUG           0x003C
  60 #define NFC_REG_ECC_ERR_CNT(x)  ((0x0040 + (x)) & ~0x3)
  61 #define NFC_REG_USER_DATA(x)    (0x0050 + ((x) * 4))
  62 #define NFC_REG_SPARE_AREA      0x00A0
  63 #define NFC_RAM0_BASE           0x0400
  64 #define NFC_RAM1_BASE           0x0800
  65
  66 /* define bit use in NFC_CTL */
  67 #define NFC_EN                  BIT(0)
  68 #define NFC_RESET               BIT(1)
  69 #define NFC_BUS_WIDTH_MSK       BIT(2)
  70 #define NFC_BUS_WIDTH_8         (0 << 2)
  71 #define NFC_BUS_WIDTH_16        (1 << 2)
  72 #define NFC_RB_SEL_MSK          BIT(3)
  73 #define NFC_RB_SEL(x)           ((x) << 3)
  74 #define NFC_CE_SEL_MSK          GENMASK(26, 24)
  75 #define NFC_CE_SEL(x)           ((x) << 24)
  76 #define NFC_CE_CTL              BIT(6)
  77 #define NFC_PAGE_SHIFT_MSK      GENMASK(11, 8)
  78 #define NFC_PAGE_SHIFT(x)       (((x) < 10 ? 0 : (x) - 10) << 8)
  79 #define NFC_SAM                 BIT(12)
  80 #define NFC_RAM_METHOD          BIT(14)
  81 #define NFC_DEBUG_CTL           BIT(31)
  82
  83 /* define bit use in NFC_ST */
  84 #define NFC_RB_B2R              BIT(0)
  85 #define NFC_CMD_INT_FLAG        BIT(1)
  86 #define NFC_DMA_INT_FLAG        BIT(2)
  87 #define NFC_CMD_FIFO_STATUS     BIT(3)
  88 #define NFC_STA                 BIT(4)
  89 #define NFC_NATCH_INT_FLAG      BIT(5)
  90 #define NFC_RB_STATE(x)         BIT(x + 8)
  91
  92 /* define bit use in NFC_INT */
  93 #define NFC_B2R_INT_ENABLE      BIT(0)
  94 #define NFC_CMD_INT_ENABLE      BIT(1)
  95 #define NFC_DMA_INT_ENABLE      BIT(2)
  96 #define NFC_INT_MASK            (NFC_B2R_INT_ENABLE | \
  97                                  NFC_CMD_INT_ENABLE | \
  98                                  NFC_DMA_INT_ENABLE)
  99
 100 /* define bit use in NFC_TIMING_CTL */
 101 #define NFC_TIMING_CTL_EDO      BIT(8)
 102
 103 /* define NFC_TIMING_CFG register layout */
 104 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD)             \
 105         (((tWB) & 0x3) | (((tADL) & 0x3) << 2) |                \
 106         (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) |         \
 107         (((tCAD) & 0x7) << 8))
 108
 109 /* define bit use in NFC_CMD */
 110 #define NFC_CMD_LOW_BYTE_MSK    GENMASK(7, 0)
 111 #define NFC_CMD_HIGH_BYTE_MSK   GENMASK(15, 8)
 112 #define NFC_CMD(x)              (x)
 113 #define NFC_ADR_NUM_MSK         GENMASK(18, 16)
 114 #define NFC_ADR_NUM(x)          (((x) - 1) << 16)
 115 #define NFC_SEND_ADR            BIT(19)
 116 #define NFC_ACCESS_DIR          BIT(20)
 117 #define NFC_DATA_TRANS          BIT(21)
 118 #define NFC_SEND_CMD1           BIT(22)
 119 #define NFC_WAIT_FLAG           BIT(23)
 120 #define NFC_SEND_CMD2           BIT(24)
 121 #define NFC_SEQ                 BIT(25)
 122 #define NFC_DATA_SWAP_METHOD    BIT(26)
 123 #define NFC_ROW_AUTO_INC        BIT(27)
 124 #define NFC_SEND_CMD3           BIT(28)
 125 #define NFC_SEND_CMD4           BIT(29)
 126 #define NFC_CMD_TYPE_MSK        GENMASK(31, 30)
 127 #define NFC_NORMAL_OP           (0 << 30)
 128 #define NFC_ECC_OP              (1 << 30)
 129 #define NFC_PAGE_OP             (2 << 30)
 130
 131 /* define bit use in NFC_RCMD_SET */
 132 #define NFC_READ_CMD_MSK        GENMASK(7, 0)
 133 #define NFC_RND_READ_CMD0_MSK   GENMASK(15, 8)
 134 #define NFC_RND_READ_CMD1_MSK   GENMASK(23, 16)
 135
 136 /* define bit use in NFC_WCMD_SET */
 137 #define NFC_PROGRAM_CMD_MSK     GENMASK(7, 0)
 138 #define NFC_RND_WRITE_CMD_MSK   GENMASK(15, 8)
 139 #define NFC_READ_CMD0_MSK       GENMASK(23, 16)
 140 #define NFC_READ_CMD1_MSK       GENMASK(31, 24)
 141
 142 /* define bit use in NFC_ECC_CTL */
 143 #define NFC_ECC_EN              BIT(0)
 144 #define NFC_ECC_PIPELINE        BIT(3)
 145 #define NFC_ECC_EXCEPTION       BIT(4)
 146 #define NFC_ECC_BLOCK_SIZE_MSK  BIT(5)
 147 #define NFC_RANDOM_EN           BIT(9)
 148 #define NFC_RANDOM_DIRECTION    BIT(10)
 149 #define NFC_ECC_MODE_MSK        GENMASK(15, 12)
 150 #define NFC_ECC_MODE(x)         ((x) << 12)
 151 #define NFC_RANDOM_SEED_MSK     GENMASK(30, 16)
 152 #define NFC_RANDOM_SEED(x)      ((x) << 16)
 153
 154 /* define bit use in NFC_ECC_ST */
 155 #define NFC_ECC_ERR(x)          BIT(x)
 156 #define NFC_ECC_PAT_FOUND(x)    BIT(x + 16)
 157 #define NFC_ECC_ERR_CNT(b, x)   (((x) >> ((b) * 8)) & 0xff)
 158
 159 /* NFC_USER_DATA helper macros */
 160 #define NFC_BUF_TO_USER_DATA(buf)       ((buf)[0] | ((buf)[1] << 8) | \
 161                                         ((buf)[2] << 16) | ((buf)[3] << 24))
 162
 163 #define NFC_DEFAULT_TIMEOUT_MS  1000
 164
 165 #define NFC_SRAM_SIZE           1024
 166
 167 #define NFC_MAX_CS              7
 168
 169 /*
 170  * Ready/Busy detection type: describes the Ready/Busy detection modes
 171  *
 172  * @RB_NONE:    no external detection available, rely on STATUS command
 173  *              and software timeouts
 174  * @RB_NATIVE:  use sunxi NAND controller Ready/Busy support. The Ready/Busy
 175  *              pin of the NAND flash chip must be connected to one of the
 176  *              native NAND R/B pins (those which can be muxed to the NAND
 177  *              Controller)
 178  * @RB_GPIO:    use a simple GPIO to handle Ready/Busy status. The Ready/Busy
 179  *              pin of the NAND flash chip must be connected to a GPIO capable
 180  *              pin.
 181  */
 182 enum sunxi_nand_rb_type {
 183         RB_NONE,
 184         RB_NATIVE,
 185         RB_GPIO,
 186 };
 187
 188 /*
 189  * Ready/Busy structure: stores information related to Ready/Busy detection
 190  *
 191  * @type:       the Ready/Busy detection mode
 192  * @info:       information related to the R/B detection mode. Either a gpio
 193  *              id or a native R/B id (those supported by the NAND controller).
 194  */
 195 struct sunxi_nand_rb {
 196         enum sunxi_nand_rb_type type;
 197         union {
 198                 int gpio;
 199                 int nativeid;
 200         } info;
 201 };
 202
 203 /*
 204  * Chip Select structure: stores information related to NAND Chip Select
 205  *
 206  * @cs:         the NAND CS id used to communicate with a NAND Chip
 207  * @rb:         the Ready/Busy description
 208  */
 209 struct sunxi_nand_chip_sel {
 210         u8 cs;
 211         struct sunxi_nand_rb rb;
 212 };
 213
 214 /*
 215  * sunxi HW ECC infos: stores information related to HW ECC support
 216  *
 217  * @mode:       the sunxi ECC mode field deduced from ECC requirements
 218  * @layout:     the OOB layout depending on the ECC requirements and the
 219  *              selected ECC mode
 220  */
 221 struct sunxi_nand_hw_ecc {
 222         int mode;
 223         struct nand_ecclayout layout;
 224 };
 225
 226 /*
 227  * NAND chip structure: stores NAND chip device related information
 228  *
 229  * @node:               used to store NAND chips into a list
 230  * @nand:               base NAND chip structure
 231  * @mtd:                base MTD structure
 232  * @clk_rate:           clk_rate required for this NAND chip
 233  * @timing_cfg          TIMING_CFG register value for this NAND chip
 234  * @selected:           current active CS
 235  * @nsels:              number of CS lines required by the NAND chip
 236  * @sels:               array of CS lines descriptions
 237  */
 238 struct sunxi_nand_chip {
 239         struct list_head node;
 240         struct nand_chip nand;
 241         struct mtd_info mtd;
 242         unsigned long clk_rate;
 243         u32 timing_cfg;
 244         u32 timing_ctl;
 245         int selected;
 246         int nsels;
 247         struct sunxi_nand_chip_sel sels[0];
 248 };
 249
 250 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
 251 {
 252         return container_of(nand, struct sunxi_nand_chip, nand);
 253 }
 254
 255 /*
 256  * NAND Controller structure: stores sunxi NAND controller information
 257  *
 258  * @controller:         base controller structure
 259  * @dev:                parent device (used to print error messages)
 260  * @regs:               NAND controller registers
 261  * @ahb_clk:            NAND Controller AHB clock
 262  * @mod_clk:            NAND Controller mod clock
 263  * @assigned_cs:        bitmask describing already assigned CS lines
 264  * @clk_rate:           NAND controller current clock rate
 265  * @chips:              a list containing all the NAND chips attached to
 266  *                      this NAND controller
 267  * @complete:           a completion object used to wait for NAND
 268  *                      controller events
 269  */
 270 struct sunxi_nfc {
 271         struct nand_hw_control controller;
 272         struct device *dev;
 273         void __iomem *regs;
 274         struct clk *ahb_clk;
 275         struct clk *mod_clk;
 276         unsigned long assigned_cs;
 277         unsigned long clk_rate;
 278         struct list_head chips;
 279         struct completion complete;
 280 };
 281
 282 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
 283 {
 284         return container_of(ctrl, struct sunxi_nfc, controller);
 285 }
 286
 287 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
 288 {
 289         struct sunxi_nfc *nfc = dev_id;
 290         u32 st = readl(nfc->regs + NFC_REG_ST);
 291         u32 ien = readl(nfc->regs + NFC_REG_INT);
 292
 293         if (!(ien & st))
 294                 return IRQ_NONE;
 295
 296         if ((ien & st) == ien)
 297                 complete(&nfc->complete);
 298
 299         writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
 300         writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
 301
 302         return IRQ_HANDLED;
 303 }
 304
 305 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
 306                               unsigned int timeout_ms)
 307 {
 308         init_completion(&nfc->complete);
 309
 310         writel(flags, nfc->regs + NFC_REG_INT);
 311
 312         if (!timeout_ms)
 313                 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
 314
 315         if (!wait_for_completion_timeout(&nfc->complete,
 316                                          msecs_to_jiffies(timeout_ms))) {
 317                 dev_err(nfc->dev, "wait interrupt timedout\n");
 318                 return -ETIMEDOUT;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
 325 {
 326         unsigned long timeout = jiffies +
 327                                 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
 328
 329         do {
 330                 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
 331                         return 0;
 332         } while (time_before(jiffies, timeout));
 333
 334         dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
 335         return -ETIMEDOUT;
 336 }
 337
 338 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
 339 {
 340         unsigned long timeout = jiffies +
 341                                 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
 342
 343         writel(0, nfc->regs + NFC_REG_ECC_CTL);
 344         writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
 345
 346         do {
 347                 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
 348                         return 0;
 349         } while (time_before(jiffies, timeout));
 350
 351         dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
 352         return -ETIMEDOUT;
 353 }
 354
 355 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
 356 {
 357         struct nand_chip *nand = mtd->priv;
 358         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 359         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 360         struct sunxi_nand_rb *rb;
 361         unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
 362         int ret;
 363
 364         if (sunxi_nand->selected < 0)
 365                 return 0;
 366
 367         rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
 368
 369         switch (rb->type) {
 370         case RB_NATIVE:
 371                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 372                          NFC_RB_STATE(rb->info.nativeid));
 373                 if (ret)
 374                         break;
 375
 376                 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
 377                 ret = !!(readl(nfc->regs + NFC_REG_ST) &
 378                          NFC_RB_STATE(rb->info.nativeid));
 379                 break;
 380         case RB_GPIO:
 381                 ret = gpio_get_value(rb->info.gpio);
 382                 break;
 383         case RB_NONE:
 384         default:
 385                 ret = 0;
 386                 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
 387                 break;
 388         }
 389
 390         return ret;
 391 }
 392
 393 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
 394 {
 395         struct nand_chip *nand = mtd->priv;
 396         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 397         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 398         struct sunxi_nand_chip_sel *sel;
 399         u32 ctl;
 400
 401         if (chip > 0 && chip >= sunxi_nand->nsels)
 402                 return;
 403
 404         if (chip == sunxi_nand->selected)
 405                 return;
 406
 407         ctl = readl(nfc->regs + NFC_REG_CTL) &
 408               ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN);
 409
 410         if (chip >= 0) {
 411                 sel = &sunxi_nand->sels[chip];
 412
 413                 ctl |= NFC_CE_SEL(sel->cs) | NFC_EN |
 414                        NFC_PAGE_SHIFT(nand->page_shift - 10);
 415                 if (sel->rb.type == RB_NONE) {
 416                         nand->dev_ready = NULL;
 417                 } else {
 418                         nand->dev_ready = sunxi_nfc_dev_ready;
 419                         if (sel->rb.type == RB_NATIVE)
 420                                 ctl |= NFC_RB_SEL(sel->rb.info.nativeid);
 421                 }
 422
 423                 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
 424
 425                 if (nfc->clk_rate != sunxi_nand->clk_rate) {
 426                         clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
 427                         nfc->clk_rate = sunxi_nand->clk_rate;
 428                 }
 429         }
 430
 431         writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
 432         writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
 433         writel(ctl, nfc->regs + NFC_REG_CTL);
 434
 435         sunxi_nand->selected = chip;
 436 }
 437
 438 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 439 {
 440         struct nand_chip *nand = mtd->priv;
 441         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 442         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 443         int ret;
 444         int cnt;
 445         int offs = 0;
 446         u32 tmp;
 447
 448         while (len > offs) {
 449                 cnt = min(len - offs, NFC_SRAM_SIZE);
 450
 451                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 452                 if (ret)
 453                         break;
 454
 455                 writel(cnt, nfc->regs + NFC_REG_CNT);
 456                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
 457                 writel(tmp, nfc->regs + NFC_REG_CMD);
 458
 459                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 460                 if (ret)
 461                         break;
 462
 463                 if (buf)
 464                         memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
 465                                       cnt);
 466                 offs += cnt;
 467         }
 468 }
 469
 470 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
 471                                 int len)
 472 {
 473         struct nand_chip *nand = mtd->priv;
 474         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 475         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 476         int ret;
 477         int cnt;
 478         int offs = 0;
 479         u32 tmp;
 480
 481         while (len > offs) {
 482                 cnt = min(len - offs, NFC_SRAM_SIZE);
 483
 484                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 485                 if (ret)
 486                         break;
 487
 488                 writel(cnt, nfc->regs + NFC_REG_CNT);
 489                 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
 490                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 491                       NFC_ACCESS_DIR;
 492                 writel(tmp, nfc->regs + NFC_REG_CMD);
 493
 494                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 495                 if (ret)
 496                         break;
 497
 498                 offs += cnt;
 499         }
 500 }
 501
 502 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
 503 {
 504         uint8_t ret;
 505
 506         sunxi_nfc_read_buf(mtd, &ret, 1);
 507
 508         return ret;
 509 }
 510
 511 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
 512                                unsigned int ctrl)
 513 {
 514         struct nand_chip *nand = mtd->priv;
 515         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
 516         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
 517         int ret;
 518         u32 tmp;
 519
 520         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 521         if (ret)
 522                 return;
 523
 524         if (ctrl & NAND_CTRL_CHANGE) {
 525                 tmp = readl(nfc->regs + NFC_REG_CTL);
 526                 if (ctrl & NAND_NCE)
 527                         tmp |= NFC_CE_CTL;
 528                 else
 529                         tmp &= ~NFC_CE_CTL;
 530                 writel(tmp, nfc->regs + NFC_REG_CTL);
 531         }
 532
 533         if (dat == NAND_CMD_NONE)
 534                 return;
 535
 536         if (ctrl & NAND_CLE) {
 537                 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
 538         } else {
 539                 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
 540                 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
 541         }
 542
 543         sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 544 }
 545
 546 static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd)
 547 {
 548         struct nand_chip *nand = mtd->priv;
 549         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 550         struct sunxi_nand_hw_ecc *data = nand->ecc.priv;
 551         u32 ecc_ctl;
 552
 553         ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL);
 554         ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE |
 555                      NFC_ECC_BLOCK_SIZE_MSK);
 556         ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION;
 557
 558         writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL);
 559 }
 560
 561 static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd)
 562 {
 563         struct nand_chip *nand = mtd->priv;
 564         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 565
 566         writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
 567                nfc->regs + NFC_REG_ECC_CTL);
 568 }
 569
 570 static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd,
 571                                        u8 *data, int data_off,
 572                                        u8 *oob, int oob_off,
 573                                        int *cur_off,
 574                                        unsigned int *max_bitflips)
 575 {
 576         struct nand_chip *nand = mtd->priv;
 577         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 578         struct nand_ecc_ctrl *ecc = &nand->ecc;
 579         u32 status;
 580         int ret;
 581
 582         if (*cur_off != data_off)
 583                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1);
 584
 585         sunxi_nfc_read_buf(mtd, data, ecc->size);
 586
 587         if (data_off + ecc->bytes != oob_off)
 588                 nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 589
 590         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 591         if (ret)
 592                 return ret;
 593
 594         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP,
 595                nfc->regs + NFC_REG_CMD);
 596
 597         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 598         if (ret)
 599                 return ret;
 600
 601         status = readl(nfc->regs + NFC_REG_ECC_ST);
 602         ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0)));
 603
 604         memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size);
 605
 606         nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1);
 607         sunxi_nfc_read_buf(mtd, oob, ecc->bytes + 4);
 608
 609         if (status & NFC_ECC_ERR(0))
 610                 ret = -EIO;
 611
 612         if (ret < 0) {
 613                 mtd->ecc_stats.failed++;
 614         } else {
 615                 mtd->ecc_stats.corrected += ret;
 616                 *max_bitflips = max_t(unsigned int, *max_bitflips, ret);
 617         }
 618
 619         *cur_off = oob_off + ecc->bytes + 4;
 620
 621         return 0;
 622 }
 623
 624 static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd,
 625                                         const u8 *data, int data_off,
 626                                         const u8 *oob, int oob_off,
 627                                         int *cur_off)
 628 {
 629         struct nand_chip *nand = mtd->priv;
 630         struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller);
 631         struct nand_ecc_ctrl *ecc = &nand->ecc;
 632         int ret;
 633
 634         if (data_off != *cur_off)
 635                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1);
 636
 637         sunxi_nfc_write_buf(mtd, data, ecc->size);
 638
 639         /* Fill OOB data in */
 640         writel(NFC_BUF_TO_USER_DATA(oob), nfc->regs + NFC_REG_USER_DATA(0));
 641
 642         if (data_off + ecc->bytes != oob_off)
 643                 nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1);
 644
 645         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 646         if (ret)
 647                 return ret;
 648
 649         writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
 650                NFC_ACCESS_DIR | NFC_ECC_OP,
 651                nfc->regs + NFC_REG_CMD);
 652
 653         ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 654         if (ret)
 655                 return ret;
 656
 657         *cur_off = oob_off + ecc->bytes + 4;
 658
 659         return 0;
 660 }
 661
 662 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
 663                                       struct nand_chip *chip, uint8_t *buf,
 664                                       int oob_required, int page)
 665 {
 666         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
 667         struct nand_ecc_ctrl *ecc = &chip->ecc;
 668         struct nand_ecclayout *layout = ecc->layout;
 669         unsigned int max_bitflips = 0;
 670         int offset;
 671         int ret;
 672         u32 tmp;
 673         int i;
 674         int cnt;
 675
 676         sunxi_nfc_hw_ecc_enable(mtd);
 677
 678         for (i = 0; i < ecc->steps; i++) {
 679                 if (i)
 680                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1);
 681
 682                 offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4;
 683
 684                 chip->read_buf(mtd, NULL, ecc->size);
 685
 686                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
 687
 688                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 689                 if (ret)
 690                         return ret;
 691
 692                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP;
 693                 writel(tmp, nfc->regs + NFC_REG_CMD);
 694
 695                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 696                 if (ret)
 697                         return ret;
 698
 699                 memcpy_fromio(buf + (i * ecc->size),
 700                               nfc->regs + NFC_RAM0_BASE, ecc->size);
 701
 702                 if (readl(nfc->regs + NFC_REG_ECC_ST) & NFC_ECC_ERR(0)) {
 703                         mtd->ecc_stats.failed++;
 704                 } else {
 705                         tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0));
 706                         mtd->ecc_stats.corrected += NFC_ECC_ERR_CNT(0, tmp);
 707                         max_bitflips = max_t(unsigned int, max_bitflips, tmp);
 708                 }
 709
 710                 if (oob_required) {
 711                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
 712
 713                         ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 714                         if (ret)
 715                                 return ret;
 716
 717                         offset -= mtd->writesize;
 718                         chip->read_buf(mtd, chip->oob_poi + offset,
 719                                       ecc->bytes + 4);
 720                 }
 721         }
 722
 723         if (oob_required) {
 724                 cnt = ecc->layout->oobfree[ecc->steps].length;
 725                 if (cnt > 0) {
 726                         offset = mtd->writesize +
 727                                  ecc->layout->oobfree[ecc->steps].offset;
 728                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
 729                         offset -= mtd->writesize;
 730                         chip->read_buf(mtd, chip->oob_poi + offset, cnt);
 731                 }
 732         }
 733
 734         sunxi_nfc_hw_ecc_disable(mtd);
 735
 736         return max_bitflips;
 737 }
 738
 739 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
 740                                        struct nand_chip *chip,
 741                                        const uint8_t *buf, int oob_required)
 742 {
 743         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
 744         struct nand_ecc_ctrl *ecc = &chip->ecc;
 745         struct nand_ecclayout *layout = ecc->layout;
 746         int offset;
 747         int ret;
 748         u32 tmp;
 749         int i;
 750         int cnt;
 751
 752         sunxi_nfc_hw_ecc_enable(mtd);
 753
 754         for (i = 0; i < ecc->steps; i++) {
 755                 if (i)
 756                         chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1);
 757
 758                 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
 759
 760                 offset = layout->eccpos[i * ecc->bytes] - 4 + mtd->writesize;
 761
 762                 /* Fill OOB data in */
 763                 writel(NFC_BUF_TO_USER_DATA(chip->oob_poi +
 764                                             layout->oobfree[i].offset),
 765                        nfc->regs + NFC_REG_USER_DATA(0));
 766
 767                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
 768
 769                 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
 770                 if (ret)
 771                         return ret;
 772
 773                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
 774                       NFC_ECC_OP;
 775                 writel(tmp, nfc->regs + NFC_REG_CMD);
 776                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 777                 if (ret)
 778                         return ret;
 779         }
 780
 781         if (oob_required) {
 782                 cnt = ecc->layout->oobfree[i].length;
 783                 if (cnt > 0) {
 784                         offset = mtd->writesize +
 785                                  ecc->layout->oobfree[i].offset;
 786                         chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
 787                         offset -= mtd->writesize;
 788                         chip->write_buf(mtd, chip->oob_poi + offset, cnt);
 789                 }
 790         }
 791
 792         sunxi_nfc_hw_ecc_disable(mtd);
 793
 794         return 0;
 795 }
 796
 797 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
 798                                                struct nand_chip *chip,
 799                                                uint8_t *buf, int oob_required,
 800                                                int page)
 801 {
 802         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
 803         struct nand_ecc_ctrl *ecc = &chip->ecc;
 804         unsigned int max_bitflips = 0;
 805         uint8_t *oob = chip->oob_poi;
 806         int offset = 0;
 807         int ret;
 808         int cnt;
 809         u32 tmp;
 810         int i;
 811
 812         sunxi_nfc_hw_ecc_enable(mtd);
 813
 814         for (i = 0; i < ecc->steps; i++) {
 815                 chip->read_buf(mtd, NULL, ecc->size);
 816
 817                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP;
 818                 writel(tmp, nfc->regs + NFC_REG_CMD);
 819
 820                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 821                 if (ret)
 822                         return ret;
 823
 824                 memcpy_fromio(buf, nfc->regs + NFC_RAM0_BASE, ecc->size);
 825                 buf += ecc->size;
 826                 offset += ecc->size;
 827
 828                 if (readl(nfc->regs + NFC_REG_ECC_ST) & NFC_ECC_ERR(0)) {
 829                         mtd->ecc_stats.failed++;
 830                 } else {
 831                         tmp = readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0));
 832                         mtd->ecc_stats.corrected += NFC_ECC_ERR_CNT(0, tmp);
 833                         max_bitflips = max_t(unsigned int, max_bitflips, tmp);
 834                 }
 835
 836                 if (oob_required) {
 837                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
 838                         chip->read_buf(mtd, oob, ecc->bytes + ecc->prepad);
 839                         oob += ecc->bytes + ecc->prepad;
 840                 }
 841
 842                 offset += ecc->bytes + ecc->prepad;
 843         }
 844
 845         if (oob_required) {
 846                 cnt = mtd->oobsize - (oob - chip->oob_poi);
 847                 if (cnt > 0) {
 848                         chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
 849                         chip->read_buf(mtd, oob, cnt);
 850                 }
 851         }
 852
 853         sunxi_nfc_hw_ecc_disable(mtd);
 854
 855         return max_bitflips;
 856 }
 857
 858 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
 859                                                 struct nand_chip *chip,
 860                                                 const uint8_t *buf,
 861                                                 int oob_required)
 862 {
 863         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
 864         struct nand_ecc_ctrl *ecc = &chip->ecc;
 865         uint8_t *oob = chip->oob_poi;
 866         int offset = 0;
 867         int ret;
 868         int cnt;
 869         u32 tmp;
 870         int i;
 871
 872         sunxi_nfc_hw_ecc_enable(mtd);
 873
 874         for (i = 0; i < ecc->steps; i++) {
 875                 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
 876                 offset += ecc->size;
 877
 878                 /* Fill OOB data in */
 879                 writel(NFC_BUF_TO_USER_DATA(oob),
 880                        nfc->regs + NFC_REG_USER_DATA(0));
 881
 882                 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
 883                       NFC_ECC_OP;
 884                 writel(tmp, nfc->regs + NFC_REG_CMD);
 885
 886                 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
 887                 if (ret)
 888                         return ret;
 889
 890                 offset += ecc->bytes + ecc->prepad;
 891                 oob += ecc->bytes + ecc->prepad;
 892         }
 893
 894         if (oob_required) {
 895                 cnt = mtd->oobsize - (oob - chip->oob_poi);
 896                 if (cnt > 0) {
 897                         chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
 898                         chip->write_buf(mtd, oob, cnt);
 899                 }
 900         }
 901
 902         sunxi_nfc_hw_ecc_disable(mtd);
 903
 904         return 0;
 905 }
 906
 907 static const s32 tWB_lut[] = {6, 12, 16, 20};
 908 static const s32 tRHW_lut[] = {4, 8, 12, 20};
 909
 910 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
 911                 u32 clk_period)
 912 {
 913         u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
 914         int i;
 915
 916         for (i = 0; i < lut_size; i++) {
 917                 if (clk_cycles <= lut[i])
 918                         return i;
 919         }
 920
 921         /* Doesn't fit */
 922         return -EINVAL;
 923 }
 924
 925 #define sunxi_nand_lookup_timing(l, p, c) \
 926                         _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
 927
 928 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
 929                                        const struct nand_sdr_timings *timings)
 930 {
 931         struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
 932         u32 min_clk_period = 0;
 933         s32 tWB, tADL, tWHR, tRHW, tCAD;
 934
 935         /* T1 <=> tCLS */
 936         if (timings->tCLS_min > min_clk_period)
 937                 min_clk_period = timings->tCLS_min;
 938
 939         /* T2 <=> tCLH */
 940         if (timings->tCLH_min > min_clk_period)
 941                 min_clk_period = timings->tCLH_min;
 942
 943         /* T3 <=> tCS */
 944         if (timings->tCS_min > min_clk_period)
 945                 min_clk_period = timings->tCS_min;
 946
 947         /* T4 <=> tCH */
 948         if (timings->tCH_min > min_clk_period)
 949                 min_clk_period = timings->tCH_min;
 950
 951         /* T5 <=> tWP */
 952         if (timings->tWP_min > min_clk_period)
 953                 min_clk_period = timings->tWP_min;
 954
 955         /* T6 <=> tWH */
 956         if (timings->tWH_min > min_clk_period)
 957                 min_clk_period = timings->tWH_min;
 958
 959         /* T7 <=> tALS */
 960         if (timings->tALS_min > min_clk_period)
 961                 min_clk_period = timings->tALS_min;
 962
 963         /* T8 <=> tDS */
 964         if (timings->tDS_min > min_clk_period)
 965                 min_clk_period = timings->tDS_min;
 966
 967         /* T9 <=> tDH */
 968         if (timings->tDH_min > min_clk_period)
 969                 min_clk_period = timings->tDH_min;
 970
 971         /* T10 <=> tRR */
 972         if (timings->tRR_min > (min_clk_period * 3))
 973                 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
 974
 975         /* T11 <=> tALH */
 976         if (timings->tALH_min > min_clk_period)
 977                 min_clk_period = timings->tALH_min;
 978
 979         /* T12 <=> tRP */
 980         if (timings->tRP_min > min_clk_period)
 981                 min_clk_period = timings->tRP_min;
 982
 983         /* T13 <=> tREH */
 984         if (timings->tREH_min > min_clk_period)
 985                 min_clk_period = timings->tREH_min;
 986
 987         /* T14 <=> tRC */
 988         if (timings->tRC_min > (min_clk_period * 2))
 989                 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
 990
 991         /* T15 <=> tWC */
 992         if (timings->tWC_min > (min_clk_period * 2))
 993                 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
 994
 995         /* T16 - T19 + tCAD */
 996         tWB  = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
 997                                         min_clk_period);
 998         if (tWB < 0) {
 999                 dev_err(nfc->dev, "unsupported tWB\n");
1000                 return tWB;
1001         }
1002
1003         tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
1004         if (tADL > 3) {
1005                 dev_err(nfc->dev, "unsupported tADL\n");
1006                 return -EINVAL;
1007         }
1008
1009         tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
1010         if (tWHR > 3) {
1011                 dev_err(nfc->dev, "unsupported tWHR\n");
1012                 return -EINVAL;
1013         }
1014
1015         tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
1016                                         min_clk_period);
1017         if (tRHW < 0) {
1018                 dev_err(nfc->dev, "unsupported tRHW\n");
1019                 return tRHW;
1020         }
1021
1022         /*
1023          * TODO: according to ONFI specs this value only applies for DDR NAND,
1024          * but Allwinner seems to set this to 0x7. Mimic them for now.
1025          */
1026         tCAD = 0x7;
1027
1028         /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
1029         chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
1030
1031         /*
1032          * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
1033          * output cycle timings shall be used if the host drives tRC less than
1034          * 30 ns.
1035          */
1036         chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
1037
1038         /* Convert min_clk_period from picoseconds to nanoseconds */
1039         min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
1040
1041         /*
1042          * Convert min_clk_period into a clk frequency, then get the
1043          * appropriate rate for the NAND controller IP given this formula
1044          * (specified in the datasheet):
1045          * nand clk_rate = 2 * min_clk_rate
1046          */
1047         chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
1048
1049         return 0;
1050 }
1051
1052 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
1053                                         struct device_node *np)
1054 {
1055         const struct nand_sdr_timings *timings;
1056         int ret;
1057         int mode;
1058
1059         mode = onfi_get_async_timing_mode(&chip->nand);
1060         if (mode == ONFI_TIMING_MODE_UNKNOWN) {
1061                 mode = chip->nand.onfi_timing_mode_default;
1062         } else {
1063                 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
1064                 int i;
1065
1066                 mode = fls(mode) - 1;
1067                 if (mode < 0)
1068                         mode = 0;
1069
1070                 feature[0] = mode;
1071                 for (i = 0; i < chip->nsels; i++) {
1072                         chip->nand.select_chip(&chip->mtd, i);
1073                         ret = chip->nand.onfi_set_features(&chip->mtd,
1074                                                 &chip->nand,
1075                                                 ONFI_FEATURE_ADDR_TIMING_MODE,
1076                                                 feature);
1077                         chip->nand.select_chip(&chip->mtd, -1);
1078                         if (ret)
1079                                 return ret;
1080                 }
1081         }
1082
1083         timings = onfi_async_timing_mode_to_sdr_timings(mode);
1084         if (IS_ERR(timings))
1085                 return PTR_ERR(timings);
1086
1087         return sunxi_nand_chip_set_timings(chip, timings);
1088 }
1089
1090 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1091                                               struct nand_ecc_ctrl *ecc,
1092                                               struct device_node *np)
1093 {
1094         static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1095         struct nand_chip *nand = mtd->priv;
1096         struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1097         struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1098         struct sunxi_nand_hw_ecc *data;
1099         struct nand_ecclayout *layout;
1100         int nsectors;
1101         int ret;
1102         int i;
1103
1104         data = kzalloc(sizeof(*data), GFP_KERNEL);
1105         if (!data)
1106                 return -ENOMEM;
1107
1108         /* Add ECC info retrieval from DT */
1109         for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1110                 if (ecc->strength <= strengths[i])
1111                         break;
1112         }
1113
1114         if (i >= ARRAY_SIZE(strengths)) {
1115                 dev_err(nfc->dev, "unsupported strength\n");
1116                 ret = -ENOTSUPP;
1117                 goto err;
1118         }
1119
1120         data->mode = i;
1121
1122         /* HW ECC always request ECC bytes for 1024 bytes blocks */
1123         ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1124
1125         /* HW ECC always work with even numbers of ECC bytes */
1126         ecc->bytes = ALIGN(ecc->bytes, 2);
1127
1128         layout = &data->layout;
1129         nsectors = mtd->writesize / ecc->size;
1130
1131         if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1132                 ret = -EINVAL;
1133                 goto err;
1134         }
1135
1136         layout->eccbytes = (ecc->bytes * nsectors);
1137
1138         ecc->layout = layout;
1139         ecc->priv = data;
1140
1141         return 0;
1142
1143 err:
1144         kfree(data);
1145
1146         return ret;
1147 }
1148
1149 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1150 {
1151         kfree(ecc->priv);
1152 }
1153
1154 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1155                                        struct nand_ecc_ctrl *ecc,
1156                                        struct device_node *np)
1157 {
1158         struct nand_ecclayout *layout;
1159         int nsectors;
1160         int i, j;
1161         int ret;
1162
1163         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1164         if (ret)
1165                 return ret;
1166
1167         ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1168         ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1169         layout = ecc->layout;
1170         nsectors = mtd->writesize / ecc->size;
1171
1172         for (i = 0; i < nsectors; i++) {
1173                 if (i) {
1174                         layout->oobfree[i].offset =
1175                                 layout->oobfree[i - 1].offset +
1176                                 layout->oobfree[i - 1].length +
1177                                 ecc->bytes;
1178                         layout->oobfree[i].length = 4;
1179                 } else {
1180                         /*
1181                          * The first 2 bytes are used for BB markers, hence we
1182                          * only have 2 bytes available in the first user data
1183                          * section.
1184                          */
1185                         layout->oobfree[i].length = 2;
1186                         layout->oobfree[i].offset = 2;
1187                 }
1188
1189                 for (j = 0; j < ecc->bytes; j++)
1190                         layout->eccpos[(ecc->bytes * i) + j] =
1191                                         layout->oobfree[i].offset +
1192                                         layout->oobfree[i].length + j;
1193         }
1194
1195         if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1196                 layout->oobfree[nsectors].offset =
1197                                 layout->oobfree[nsectors - 1].offset +
1198                                 layout->oobfree[nsectors - 1].length +
1199                                 ecc->bytes;
1200                 layout->oobfree[nsectors].length = mtd->oobsize -
1201                                 ((ecc->bytes + 4) * nsectors);
1202         }
1203
1204         return 0;
1205 }
1206
1207 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1208                                                 struct nand_ecc_ctrl *ecc,
1209                                                 struct device_node *np)
1210 {
1211         struct nand_ecclayout *layout;
1212         int nsectors;
1213         int i;
1214         int ret;
1215
1216         ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1217         if (ret)
1218                 return ret;
1219
1220         ecc->prepad = 4;
1221         ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1222         ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1223
1224         layout = ecc->layout;
1225         nsectors = mtd->writesize / ecc->size;
1226
1227         for (i = 0; i < (ecc->bytes * nsectors); i++)
1228                 layout->eccpos[i] = i;
1229
1230         layout->oobfree[0].length = mtd->oobsize - i;
1231         layout->oobfree[0].offset = i;
1232
1233         return 0;
1234 }
1235
1236 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1237 {
1238         switch (ecc->mode) {
1239         case NAND_ECC_HW:
1240         case NAND_ECC_HW_SYNDROME:
1241                 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1242                 break;
1243         case NAND_ECC_NONE:
1244                 kfree(ecc->layout);
1245         default:
1246                 break;
1247         }
1248 }
1249
1250 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1251                                struct device_node *np)
1252 {
1253         struct nand_chip *nand = mtd->priv;
1254         int ret;
1255
1256         if (!ecc->size) {
1257                 ecc->size = nand->ecc_step_ds;
1258                 ecc->strength = nand->ecc_strength_ds;
1259         }
1260
1261         if (!ecc->size || !ecc->strength)
1262                 return -EINVAL;
1263
1264         switch (ecc->mode) {
1265         case NAND_ECC_SOFT_BCH:
1266                 break;
1267         case NAND_ECC_HW:
1268                 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1269                 if (ret)
1270                         return ret;
1271                 break;
1272         case NAND_ECC_HW_SYNDROME:
1273                 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1274                 if (ret)
1275                         return ret;
1276                 break;
1277         case NAND_ECC_NONE:
1278                 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1279                 if (!ecc->layout)
1280                         return -ENOMEM;
1281                 ecc->layout->oobfree[0].length = mtd->oobsize;
1282         case NAND_ECC_SOFT:
1283                 break;
1284         default:
1285                 return -EINVAL;
1286         }
1287
1288         return 0;
1289 }
1290
1291 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1292                                 struct device_node *np)
1293 {
1294         const struct nand_sdr_timings *timings;
1295         struct sunxi_nand_chip *chip;
1296         struct mtd_part_parser_data ppdata;
1297         struct mtd_info *mtd;
1298         struct nand_chip *nand;
1299         int nsels;
1300         int ret;
1301         int i;
1302         u32 tmp;
1303
1304         if (!of_get_property(np, "reg", &nsels))
1305                 return -EINVAL;
1306
1307         nsels /= sizeof(u32);
1308         if (!nsels) {
1309                 dev_err(dev, "invalid reg property size\n");
1310                 return -EINVAL;
1311         }
1312
1313         chip = devm_kzalloc(dev,
1314                             sizeof(*chip) +
1315                             (nsels * sizeof(struct sunxi_nand_chip_sel)),
1316                             GFP_KERNEL);
1317         if (!chip) {
1318                 dev_err(dev, "could not allocate chip\n");
1319                 return -ENOMEM;
1320         }
1321
1322         chip->nsels = nsels;
1323         chip->selected = -1;
1324
1325         for (i = 0; i < nsels; i++) {
1326                 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1327                 if (ret) {
1328                         dev_err(dev, "could not retrieve reg property: %d\n",
1329                                 ret);
1330                         return ret;
1331                 }
1332
1333                 if (tmp > NFC_MAX_CS) {
1334                         dev_err(dev,
1335                                 "invalid reg value: %u (max CS = 7)\n",
1336                                 tmp);
1337                         return -EINVAL;
1338                 }
1339
1340                 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1341                         dev_err(dev, "CS %d already assigned\n", tmp);
1342                         return -EINVAL;
1343                 }
1344
1345                 chip->sels[i].cs = tmp;
1346
1347                 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1348                     tmp < 2) {
1349                         chip->sels[i].rb.type = RB_NATIVE;
1350                         chip->sels[i].rb.info.nativeid = tmp;
1351                 } else {
1352                         ret = of_get_named_gpio(np, "rb-gpios", i);
1353                         if (ret >= 0) {
1354                                 tmp = ret;
1355                                 chip->sels[i].rb.type = RB_GPIO;
1356                                 chip->sels[i].rb.info.gpio = tmp;
1357                                 ret = devm_gpio_request(dev, tmp, "nand-rb");
1358                                 if (ret)
1359                                         return ret;
1360
1361                                 ret = gpio_direction_input(tmp);
1362                                 if (ret)
1363                                         return ret;
1364                         } else {
1365                                 chip->sels[i].rb.type = RB_NONE;
1366                         }
1367                 }
1368         }
1369
1370         timings = onfi_async_timing_mode_to_sdr_timings(0);
1371         if (IS_ERR(timings)) {
1372                 ret = PTR_ERR(timings);
1373                 dev_err(dev,
1374                         "could not retrieve timings for ONFI mode 0: %d\n",
1375                         ret);
1376                 return ret;
1377         }
1378
1379         ret = sunxi_nand_chip_set_timings(chip, timings);
1380         if (ret) {
1381                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1382                 return ret;
1383         }
1384
1385         nand = &chip->nand;
1386         /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1387         nand->chip_delay = 200;
1388         nand->controller = &nfc->controller;
1389         /*
1390          * Set the ECC mode to the default value in case nothing is specified
1391          * in the DT.
1392          */
1393         nand->ecc.mode = NAND_ECC_HW;
1394         nand->flash_node = np;
1395         nand->select_chip = sunxi_nfc_select_chip;
1396         nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1397         nand->read_buf = sunxi_nfc_read_buf;
1398         nand->write_buf = sunxi_nfc_write_buf;
1399         nand->read_byte = sunxi_nfc_read_byte;
1400
1401         mtd = &chip->mtd;
1402         mtd->dev.parent = dev;
1403         mtd->priv = nand;
1404         mtd->owner = THIS_MODULE;
1405
1406         ret = nand_scan_ident(mtd, nsels, NULL);
1407         if (ret)
1408                 return ret;
1409
1410         if (nand->bbt_options & NAND_BBT_USE_FLASH)
1411                 nand->bbt_options |= NAND_BBT_NO_OOB;
1412
1413         ret = sunxi_nand_chip_init_timings(chip, np);
1414         if (ret) {
1415                 dev_err(dev, "could not configure chip timings: %d\n", ret);
1416                 return ret;
1417         }
1418
1419         ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1420         if (ret) {
1421                 dev_err(dev, "ECC init failed: %d\n", ret);
1422                 return ret;
1423         }
1424
1425         ret = nand_scan_tail(mtd);
1426         if (ret) {
1427                 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1428                 return ret;
1429         }
1430
1431         ppdata.of_node = np;
1432         ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1433         if (ret) {
1434                 dev_err(dev, "failed to register mtd device: %d\n", ret);
1435                 nand_release(mtd);
1436                 return ret;
1437         }
1438
1439         list_add_tail(&chip->node, &nfc->chips);
1440
1441         return 0;
1442 }
1443
1444 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1445 {
1446         struct device_node *np = dev->of_node;
1447         struct device_node *nand_np;
1448         int nchips = of_get_child_count(np);
1449         int ret;
1450
1451         if (nchips > 8) {
1452                 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1453                 return -EINVAL;
1454         }
1455
1456         for_each_child_of_node(np, nand_np) {
1457                 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1458                 if (ret)
1459                         return ret;
1460         }
1461
1462         return 0;
1463 }
1464
1465 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1466 {
1467         struct sunxi_nand_chip *chip;
1468
1469         while (!list_empty(&nfc->chips)) {
1470                 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1471                                         node);
1472                 nand_release(&chip->mtd);
1473                 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1474                 list_del(&chip->node);
1475         }
1476 }
1477
1478 static int sunxi_nfc_probe(struct platform_device *pdev)
1479 {
1480         struct device *dev = &pdev->dev;
1481         struct resource *r;
1482         struct sunxi_nfc *nfc;
1483         int irq;
1484         int ret;
1485
1486         nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1487         if (!nfc)
1488                 return -ENOMEM;
1489
1490         nfc->dev = dev;
1491         spin_lock_init(&nfc->controller.lock);
1492         init_waitqueue_head(&nfc->controller.wq);
1493         INIT_LIST_HEAD(&nfc->chips);
1494
1495         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1496         nfc->regs = devm_ioremap_resource(dev, r);
1497         if (IS_ERR(nfc->regs))
1498                 return PTR_ERR(nfc->regs);
1499
1500         irq = platform_get_irq(pdev, 0);
1501         if (irq < 0) {
1502                 dev_err(dev, "failed to retrieve irq\n");
1503                 return irq;
1504         }
1505
1506         nfc->ahb_clk = devm_clk_get(dev, "ahb");
1507         if (IS_ERR(nfc->ahb_clk)) {
1508                 dev_err(dev, "failed to retrieve ahb clk\n");
1509                 return PTR_ERR(nfc->ahb_clk);
1510         }
1511
1512         ret = clk_prepare_enable(nfc->ahb_clk);
1513         if (ret)
1514                 return ret;
1515
1516         nfc->mod_clk = devm_clk_get(dev, "mod");
1517         if (IS_ERR(nfc->mod_clk)) {
1518                 dev_err(dev, "failed to retrieve mod clk\n");
1519                 ret = PTR_ERR(nfc->mod_clk);
1520                 goto out_ahb_clk_unprepare;
1521         }
1522
1523         ret = clk_prepare_enable(nfc->mod_clk);
1524         if (ret)
1525                 goto out_ahb_clk_unprepare;
1526
1527         ret = sunxi_nfc_rst(nfc);
1528         if (ret)
1529                 goto out_mod_clk_unprepare;
1530
1531         writel(0, nfc->regs + NFC_REG_INT);
1532         ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1533                                0, "sunxi-nand", nfc);
1534         if (ret)
1535                 goto out_mod_clk_unprepare;
1536
1537         platform_set_drvdata(pdev, nfc);
1538
1539         ret = sunxi_nand_chips_init(dev, nfc);
1540         if (ret) {
1541                 dev_err(dev, "failed to init nand chips\n");
1542                 goto out_mod_clk_unprepare;
1543         }
1544
1545         return 0;
1546
1547 out_mod_clk_unprepare:
1548         clk_disable_unprepare(nfc->mod_clk);
1549 out_ahb_clk_unprepare:
1550         clk_disable_unprepare(nfc->ahb_clk);
1551
1552         return ret;
1553 }
1554
1555 static int sunxi_nfc_remove(struct platform_device *pdev)
1556 {
1557         struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1558
1559         sunxi_nand_chips_cleanup(nfc);
1560
1561         return 0;
1562 }
1563
1564 static const struct of_device_id sunxi_nfc_ids[] = {
1565         { .compatible = "allwinner,sun4i-a10-nand" },
1566         { /* sentinel */ }
1567 };
1568 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1569
1570 static struct platform_driver sunxi_nfc_driver = {
1571         .driver = {
1572                 .name = "sunxi_nand",
1573                 .of_match_table = sunxi_nfc_ids,
1574         },
1575         .probe = sunxi_nfc_probe,
1576         .remove = sunxi_nfc_remove,
1577 };
1578 module_platform_driver(sunxi_nfc_driver);
1579
1580 MODULE_LICENSE("GPL v2");
1581 MODULE_AUTHOR("Boris BREZILLON");
1582 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1583 MODULE_ALIAS("platform:sunxi_nand");