2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
5 * https://github.com/yuq/sunxi-nfc-mtd
6 * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
8 * https://github.com/hno/Allwinner-Info
9 * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
11 * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
12 * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/dma-mapping.h>
26 #include <linux/slab.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/platform_device.h>
31 #include <linux/of_device.h>
32 #include <linux/of_gpio.h>
33 #include <linux/of_mtd.h>
34 #include <linux/mtd/mtd.h>
35 #include <linux/mtd/nand.h>
36 #include <linux/mtd/partitions.h>
37 #include <linux/clk.h>
38 #include <linux/delay.h>
39 #include <linux/dmaengine.h>
40 #include <linux/gpio.h>
41 #include <linux/interrupt.h>
44 #define NFC_REG_CTL 0x0000
45 #define NFC_REG_ST 0x0004
46 #define NFC_REG_INT 0x0008
47 #define NFC_REG_TIMING_CTL 0x000C
48 #define NFC_REG_TIMING_CFG 0x0010
49 #define NFC_REG_ADDR_LOW 0x0014
50 #define NFC_REG_ADDR_HIGH 0x0018
51 #define NFC_REG_SECTOR_NUM 0x001C
52 #define NFC_REG_CNT 0x0020
53 #define NFC_REG_CMD 0x0024
54 #define NFC_REG_RCMD_SET 0x0028
55 #define NFC_REG_WCMD_SET 0x002C
56 #define NFC_REG_IO_DATA 0x0030
57 #define NFC_REG_ECC_CTL 0x0034
58 #define NFC_REG_ECC_ST 0x0038
59 #define NFC_REG_DEBUG 0x003C
60 #define NFC_REG_ECC_CNT0 0x0040
61 #define NFC_REG_ECC_CNT1 0x0044
62 #define NFC_REG_ECC_CNT2 0x0048
63 #define NFC_REG_ECC_CNT3 0x004c
64 #define NFC_REG_USER_DATA_BASE 0x0050
65 #define NFC_REG_SPARE_AREA 0x00A0
66 #define NFC_RAM0_BASE 0x0400
67 #define NFC_RAM1_BASE 0x0800
69 /* define bit use in NFC_CTL */
71 #define NFC_RESET BIT(1)
72 #define NFC_BUS_WIDYH BIT(2)
73 #define NFC_RB_SEL BIT(3)
74 #define NFC_CE_SEL GENMASK(26, 24)
75 #define NFC_CE_CTL BIT(6)
76 #define NFC_CE_CTL1 BIT(7)
77 #define NFC_PAGE_SIZE GENMASK(11, 8)
78 #define NFC_SAM BIT(12)
79 #define NFC_RAM_METHOD BIT(14)
80 #define NFC_DEBUG_CTL BIT(31)
82 /* define bit use in NFC_ST */
83 #define NFC_RB_B2R BIT(0)
84 #define NFC_CMD_INT_FLAG BIT(1)
85 #define NFC_DMA_INT_FLAG BIT(2)
86 #define NFC_CMD_FIFO_STATUS BIT(3)
87 #define NFC_STA BIT(4)
88 #define NFC_NATCH_INT_FLAG BIT(5)
89 #define NFC_RB_STATE0 BIT(8)
90 #define NFC_RB_STATE1 BIT(9)
91 #define NFC_RB_STATE2 BIT(10)
92 #define NFC_RB_STATE3 BIT(11)
94 /* define bit use in NFC_INT */
95 #define NFC_B2R_INT_ENABLE BIT(0)
96 #define NFC_CMD_INT_ENABLE BIT(1)
97 #define NFC_DMA_INT_ENABLE BIT(2)
98 #define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
99 NFC_CMD_INT_ENABLE | \
102 /* define bit use in NFC_TIMING_CTL */
103 #define NFC_TIMING_CTL_EDO BIT(8)
105 /* define NFC_TIMING_CFG register layout */
106 #define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \
107 (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \
108 (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \
109 (((tCAD) & 0x7) << 8))
111 /* define bit use in NFC_CMD */
112 #define NFC_CMD_LOW_BYTE GENMASK(7, 0)
113 #define NFC_CMD_HIGH_BYTE GENMASK(15, 8)
114 #define NFC_ADR_NUM GENMASK(18, 16)
115 #define NFC_SEND_ADR BIT(19)
116 #define NFC_ACCESS_DIR BIT(20)
117 #define NFC_DATA_TRANS BIT(21)
118 #define NFC_SEND_CMD1 BIT(22)
119 #define NFC_WAIT_FLAG BIT(23)
120 #define NFC_SEND_CMD2 BIT(24)
121 #define NFC_SEQ BIT(25)
122 #define NFC_DATA_SWAP_METHOD BIT(26)
123 #define NFC_ROW_AUTO_INC BIT(27)
124 #define NFC_SEND_CMD3 BIT(28)
125 #define NFC_SEND_CMD4 BIT(29)
126 #define NFC_CMD_TYPE GENMASK(31, 30)
128 /* define bit use in NFC_RCMD_SET */
129 #define NFC_READ_CMD GENMASK(7, 0)
130 #define NFC_RANDOM_READ_CMD0 GENMASK(15, 8)
131 #define NFC_RANDOM_READ_CMD1 GENMASK(23, 16)
133 /* define bit use in NFC_WCMD_SET */
134 #define NFC_PROGRAM_CMD GENMASK(7, 0)
135 #define NFC_RANDOM_WRITE_CMD GENMASK(15, 8)
136 #define NFC_READ_CMD0 GENMASK(23, 16)
137 #define NFC_READ_CMD1 GENMASK(31, 24)
139 /* define bit use in NFC_ECC_CTL */
140 #define NFC_ECC_EN BIT(0)
141 #define NFC_ECC_PIPELINE BIT(3)
142 #define NFC_ECC_EXCEPTION BIT(4)
143 #define NFC_ECC_BLOCK_SIZE BIT(5)
144 #define NFC_RANDOM_EN BIT(9)
145 #define NFC_RANDOM_DIRECTION BIT(10)
146 #define NFC_ECC_MODE_SHIFT 12
147 #define NFC_ECC_MODE GENMASK(15, 12)
148 #define NFC_RANDOM_SEED GENMASK(30, 16)
150 #define NFC_DEFAULT_TIMEOUT_MS 1000
152 #define NFC_SRAM_SIZE 1024
157 * Ready/Busy detection type: describes the Ready/Busy detection modes
159 * @RB_NONE: no external detection available, rely on STATUS command
160 * and software timeouts
161 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
162 * pin of the NAND flash chip must be connected to one of the
163 * native NAND R/B pins (those which can be muxed to the NAND
165 * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy
166 * pin of the NAND flash chip must be connected to a GPIO capable
169 enum sunxi_nand_rb_type {
176 * Ready/Busy structure: stores information related to Ready/Busy detection
178 * @type: the Ready/Busy detection mode
179 * @info: information related to the R/B detection mode. Either a gpio
180 * id or a native R/B id (those supported by the NAND controller).
182 struct sunxi_nand_rb {
183 enum sunxi_nand_rb_type type;
191 * Chip Select structure: stores information related to NAND Chip Select
193 * @cs: the NAND CS id used to communicate with a NAND Chip
194 * @rb: the Ready/Busy description
196 struct sunxi_nand_chip_sel {
198 struct sunxi_nand_rb rb;
202 * sunxi HW ECC infos: stores information related to HW ECC support
204 * @mode: the sunxi ECC mode field deduced from ECC requirements
205 * @layout: the OOB layout depending on the ECC requirements and the
208 struct sunxi_nand_hw_ecc {
210 struct nand_ecclayout layout;
214 * NAND chip structure: stores NAND chip device related information
216 * @node: used to store NAND chips into a list
217 * @nand: base NAND chip structure
218 * @mtd: base MTD structure
219 * @clk_rate: clk_rate required for this NAND chip
220 * @timing_cfg TIMING_CFG register value for this NAND chip
221 * @selected: current active CS
222 * @nsels: number of CS lines required by the NAND chip
223 * @sels: array of CS lines descriptions
225 struct sunxi_nand_chip {
226 struct list_head node;
227 struct nand_chip nand;
229 unsigned long clk_rate;
234 struct sunxi_nand_chip_sel sels[0];
237 static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
239 return container_of(nand, struct sunxi_nand_chip, nand);
243 * NAND Controller structure: stores sunxi NAND controller information
245 * @controller: base controller structure
246 * @dev: parent device (used to print error messages)
247 * @regs: NAND controller registers
248 * @ahb_clk: NAND Controller AHB clock
249 * @mod_clk: NAND Controller mod clock
250 * @assigned_cs: bitmask describing already assigned CS lines
251 * @clk_rate: NAND controller current clock rate
252 * @chips: a list containing all the NAND chips attached to
253 * this NAND controller
254 * @complete: a completion object used to wait for NAND
258 struct nand_hw_control controller;
263 unsigned long assigned_cs;
264 unsigned long clk_rate;
265 struct list_head chips;
266 struct completion complete;
269 static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
271 return container_of(ctrl, struct sunxi_nfc, controller);
274 static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
276 struct sunxi_nfc *nfc = dev_id;
277 u32 st = readl(nfc->regs + NFC_REG_ST);
278 u32 ien = readl(nfc->regs + NFC_REG_INT);
283 if ((ien & st) == ien)
284 complete(&nfc->complete);
286 writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
287 writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
292 static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
293 unsigned int timeout_ms)
295 init_completion(&nfc->complete);
297 writel(flags, nfc->regs + NFC_REG_INT);
300 timeout_ms = NFC_DEFAULT_TIMEOUT_MS;
302 if (!wait_for_completion_timeout(&nfc->complete,
303 msecs_to_jiffies(timeout_ms))) {
304 dev_err(nfc->dev, "wait interrupt timedout\n");
311 static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc)
313 unsigned long timeout = jiffies +
314 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
317 if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
319 } while (time_before(jiffies, timeout));
321 dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n");
325 static int sunxi_nfc_rst(struct sunxi_nfc *nfc)
327 unsigned long timeout = jiffies +
328 msecs_to_jiffies(NFC_DEFAULT_TIMEOUT_MS);
330 writel(0, nfc->regs + NFC_REG_ECC_CTL);
331 writel(NFC_RESET, nfc->regs + NFC_REG_CTL);
334 if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET))
336 } while (time_before(jiffies, timeout));
338 dev_err(nfc->dev, "wait for NAND controller reset timedout\n");
342 static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
344 struct nand_chip *nand = mtd->priv;
345 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
346 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
347 struct sunxi_nand_rb *rb;
348 unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
351 if (sunxi_nand->selected < 0)
354 rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
358 ret = !!(readl(nfc->regs + NFC_REG_ST) &
359 (NFC_RB_STATE0 << rb->info.nativeid));
363 sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
364 ret = !!(readl(nfc->regs + NFC_REG_ST) &
365 (NFC_RB_STATE0 << rb->info.nativeid));
368 ret = gpio_get_value(rb->info.gpio);
373 dev_err(nfc->dev, "cannot check R/B NAND status!\n");
380 static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
382 struct nand_chip *nand = mtd->priv;
383 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
384 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
385 struct sunxi_nand_chip_sel *sel;
388 if (chip > 0 && chip >= sunxi_nand->nsels)
391 if (chip == sunxi_nand->selected)
394 ctl = readl(nfc->regs + NFC_REG_CTL) &
395 ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
398 sel = &sunxi_nand->sels[chip];
400 ctl |= (sel->cs << 24) | NFC_EN |
401 (((nand->page_shift - 10) & 0xf) << 8);
402 if (sel->rb.type == RB_NONE) {
403 nand->dev_ready = NULL;
405 nand->dev_ready = sunxi_nfc_dev_ready;
406 if (sel->rb.type == RB_NATIVE)
407 ctl |= (sel->rb.info.nativeid << 3);
410 writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
412 if (nfc->clk_rate != sunxi_nand->clk_rate) {
413 clk_set_rate(nfc->mod_clk, sunxi_nand->clk_rate);
414 nfc->clk_rate = sunxi_nand->clk_rate;
418 writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL);
419 writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG);
420 writel(ctl, nfc->regs + NFC_REG_CTL);
422 sunxi_nand->selected = chip;
425 static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
427 struct nand_chip *nand = mtd->priv;
428 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
429 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
436 cnt = min(len - offs, NFC_SRAM_SIZE);
438 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
442 writel(cnt, nfc->regs + NFC_REG_CNT);
443 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
444 writel(tmp, nfc->regs + NFC_REG_CMD);
446 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
451 memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
457 static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
460 struct nand_chip *nand = mtd->priv;
461 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
462 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
469 cnt = min(len - offs, NFC_SRAM_SIZE);
471 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
475 writel(cnt, nfc->regs + NFC_REG_CNT);
476 memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
477 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
479 writel(tmp, nfc->regs + NFC_REG_CMD);
481 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
489 static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
493 sunxi_nfc_read_buf(mtd, &ret, 1);
498 static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
501 struct nand_chip *nand = mtd->priv;
502 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
503 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
507 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
511 if (ctrl & NAND_CTRL_CHANGE) {
512 tmp = readl(nfc->regs + NFC_REG_CTL);
517 writel(tmp, nfc->regs + NFC_REG_CTL);
520 if (dat == NAND_CMD_NONE)
523 if (ctrl & NAND_CLE) {
524 writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
526 writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
527 writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
530 sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
533 static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd,
534 struct nand_chip *chip, uint8_t *buf,
535 int oob_required, int page)
537 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
538 struct nand_ecc_ctrl *ecc = &chip->ecc;
539 struct nand_ecclayout *layout = ecc->layout;
540 struct sunxi_nand_hw_ecc *data = ecc->priv;
541 unsigned int max_bitflips = 0;
548 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
549 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
550 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
553 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
555 for (i = 0; i < ecc->steps; i++) {
557 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1);
559 offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4;
561 chip->read_buf(mtd, NULL, ecc->size);
563 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
565 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
569 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
570 writel(tmp, nfc->regs + NFC_REG_CMD);
572 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
576 memcpy_fromio(buf + (i * ecc->size),
577 nfc->regs + NFC_RAM0_BASE, ecc->size);
579 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
580 mtd->ecc_stats.failed++;
582 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
583 mtd->ecc_stats.corrected += tmp;
584 max_bitflips = max_t(unsigned int, max_bitflips, tmp);
588 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
590 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
594 offset -= mtd->writesize;
595 chip->read_buf(mtd, chip->oob_poi + offset,
601 cnt = ecc->layout->oobfree[ecc->steps].length;
603 offset = mtd->writesize +
604 ecc->layout->oobfree[ecc->steps].offset;
605 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
606 offset -= mtd->writesize;
607 chip->read_buf(mtd, chip->oob_poi + offset, cnt);
611 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
614 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
619 static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd,
620 struct nand_chip *chip,
621 const uint8_t *buf, int oob_required)
623 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
624 struct nand_ecc_ctrl *ecc = &chip->ecc;
625 struct nand_ecclayout *layout = ecc->layout;
626 struct sunxi_nand_hw_ecc *data = ecc->priv;
633 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
634 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
635 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
638 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
640 for (i = 0; i < ecc->steps; i++) {
642 chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1);
644 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
646 offset = layout->eccpos[i * ecc->bytes] - 4 + mtd->writesize;
648 /* Fill OOB data in */
651 memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, &tmp,
654 memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE,
655 chip->oob_poi + offset - mtd->writesize,
659 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
661 ret = sunxi_nfc_wait_cmd_fifo_empty(nfc);
665 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
667 writel(tmp, nfc->regs + NFC_REG_CMD);
668 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
674 cnt = ecc->layout->oobfree[i].length;
676 offset = mtd->writesize +
677 ecc->layout->oobfree[i].offset;
678 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
679 offset -= mtd->writesize;
680 chip->write_buf(mtd, chip->oob_poi + offset, cnt);
684 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
687 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
692 static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd,
693 struct nand_chip *chip,
694 uint8_t *buf, int oob_required,
697 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
698 struct nand_ecc_ctrl *ecc = &chip->ecc;
699 struct sunxi_nand_hw_ecc *data = ecc->priv;
700 unsigned int max_bitflips = 0;
701 uint8_t *oob = chip->oob_poi;
708 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
709 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
710 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
713 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
715 for (i = 0; i < ecc->steps; i++) {
716 chip->read_buf(mtd, NULL, ecc->size);
718 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
719 writel(tmp, nfc->regs + NFC_REG_CMD);
721 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
725 memcpy_fromio(buf, nfc->regs + NFC_RAM0_BASE, ecc->size);
729 if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
730 mtd->ecc_stats.failed++;
732 tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
733 mtd->ecc_stats.corrected += tmp;
734 max_bitflips = max_t(unsigned int, max_bitflips, tmp);
738 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
739 chip->read_buf(mtd, oob, ecc->bytes + ecc->prepad);
740 oob += ecc->bytes + ecc->prepad;
743 offset += ecc->bytes + ecc->prepad;
747 cnt = mtd->oobsize - (oob - chip->oob_poi);
749 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
750 chip->read_buf(mtd, oob, cnt);
754 writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN,
755 nfc->regs + NFC_REG_ECC_CTL);
760 static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd,
761 struct nand_chip *chip,
765 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->controller);
766 struct nand_ecc_ctrl *ecc = &chip->ecc;
767 struct sunxi_nand_hw_ecc *data = ecc->priv;
768 uint8_t *oob = chip->oob_poi;
775 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
776 tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE);
777 tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT) |
780 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
782 for (i = 0; i < ecc->steps; i++) {
783 chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
786 /* Fill OOB data in */
789 memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, &tmp,
792 memcpy_toio(nfc->regs + NFC_REG_USER_DATA_BASE, oob,
796 tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ACCESS_DIR |
798 writel(tmp, nfc->regs + NFC_REG_CMD);
800 ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
804 offset += ecc->bytes + ecc->prepad;
805 oob += ecc->bytes + ecc->prepad;
809 cnt = mtd->oobsize - (oob - chip->oob_poi);
811 chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
812 chip->write_buf(mtd, oob, cnt);
816 tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
819 writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
824 static const s32 tWB_lut[] = {6, 12, 16, 20};
825 static const s32 tRHW_lut[] = {4, 8, 12, 20};
827 static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration,
830 u32 clk_cycles = DIV_ROUND_UP(duration, clk_period);
833 for (i = 0; i < lut_size; i++) {
834 if (clk_cycles <= lut[i])
842 #define sunxi_nand_lookup_timing(l, p, c) \
843 _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c)
845 static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
846 const struct nand_sdr_timings *timings)
848 struct sunxi_nfc *nfc = to_sunxi_nfc(chip->nand.controller);
849 u32 min_clk_period = 0;
850 s32 tWB, tADL, tWHR, tRHW, tCAD;
853 if (timings->tCLS_min > min_clk_period)
854 min_clk_period = timings->tCLS_min;
857 if (timings->tCLH_min > min_clk_period)
858 min_clk_period = timings->tCLH_min;
861 if (timings->tCS_min > min_clk_period)
862 min_clk_period = timings->tCS_min;
865 if (timings->tCH_min > min_clk_period)
866 min_clk_period = timings->tCH_min;
869 if (timings->tWP_min > min_clk_period)
870 min_clk_period = timings->tWP_min;
873 if (timings->tWH_min > min_clk_period)
874 min_clk_period = timings->tWH_min;
877 if (timings->tALS_min > min_clk_period)
878 min_clk_period = timings->tALS_min;
881 if (timings->tDS_min > min_clk_period)
882 min_clk_period = timings->tDS_min;
885 if (timings->tDH_min > min_clk_period)
886 min_clk_period = timings->tDH_min;
889 if (timings->tRR_min > (min_clk_period * 3))
890 min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3);
893 if (timings->tALH_min > min_clk_period)
894 min_clk_period = timings->tALH_min;
897 if (timings->tRP_min > min_clk_period)
898 min_clk_period = timings->tRP_min;
901 if (timings->tREH_min > min_clk_period)
902 min_clk_period = timings->tREH_min;
905 if (timings->tRC_min > (min_clk_period * 2))
906 min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2);
909 if (timings->tWC_min > (min_clk_period * 2))
910 min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2);
912 /* T16 - T19 + tCAD */
913 tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max,
916 dev_err(nfc->dev, "unsupported tWB\n");
920 tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3;
922 dev_err(nfc->dev, "unsupported tADL\n");
926 tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3;
928 dev_err(nfc->dev, "unsupported tWHR\n");
932 tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min,
935 dev_err(nfc->dev, "unsupported tRHW\n");
940 * TODO: according to ONFI specs this value only applies for DDR NAND,
941 * but Allwinner seems to set this to 0x7. Mimic them for now.
945 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */
946 chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD);
949 * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data
950 * output cycle timings shall be used if the host drives tRC less than
953 chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0;
955 /* Convert min_clk_period from picoseconds to nanoseconds */
956 min_clk_period = DIV_ROUND_UP(min_clk_period, 1000);
959 * Convert min_clk_period into a clk frequency, then get the
960 * appropriate rate for the NAND controller IP given this formula
961 * (specified in the datasheet):
962 * nand clk_rate = 2 * min_clk_rate
964 chip->clk_rate = (2 * NSEC_PER_SEC) / min_clk_period;
969 static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
970 struct device_node *np)
972 const struct nand_sdr_timings *timings;
976 mode = onfi_get_async_timing_mode(&chip->nand);
977 if (mode == ONFI_TIMING_MODE_UNKNOWN) {
978 mode = chip->nand.onfi_timing_mode_default;
980 uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {};
983 mode = fls(mode) - 1;
988 for (i = 0; i < chip->nsels; i++) {
989 chip->nand.select_chip(&chip->mtd, i);
990 ret = chip->nand.onfi_set_features(&chip->mtd,
992 ONFI_FEATURE_ADDR_TIMING_MODE,
994 chip->nand.select_chip(&chip->mtd, -1);
1000 timings = onfi_async_timing_mode_to_sdr_timings(mode);
1001 if (IS_ERR(timings))
1002 return PTR_ERR(timings);
1004 return sunxi_nand_chip_set_timings(chip, timings);
1007 static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd,
1008 struct nand_ecc_ctrl *ecc,
1009 struct device_node *np)
1011 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 };
1012 struct nand_chip *nand = mtd->priv;
1013 struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand);
1014 struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
1015 struct sunxi_nand_hw_ecc *data;
1016 struct nand_ecclayout *layout;
1021 data = kzalloc(sizeof(*data), GFP_KERNEL);
1025 /* Add ECC info retrieval from DT */
1026 for (i = 0; i < ARRAY_SIZE(strengths); i++) {
1027 if (ecc->strength <= strengths[i])
1031 if (i >= ARRAY_SIZE(strengths)) {
1032 dev_err(nfc->dev, "unsupported strength\n");
1039 /* HW ECC always request ECC bytes for 1024 bytes blocks */
1040 ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8);
1042 /* HW ECC always work with even numbers of ECC bytes */
1043 ecc->bytes = ALIGN(ecc->bytes, 2);
1045 layout = &data->layout;
1046 nsectors = mtd->writesize / ecc->size;
1048 if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) {
1053 layout->eccbytes = (ecc->bytes * nsectors);
1055 ecc->layout = layout;
1066 static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc)
1071 static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
1072 struct nand_ecc_ctrl *ecc,
1073 struct device_node *np)
1075 struct nand_ecclayout *layout;
1080 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1084 ecc->read_page = sunxi_nfc_hw_ecc_read_page;
1085 ecc->write_page = sunxi_nfc_hw_ecc_write_page;
1086 layout = ecc->layout;
1087 nsectors = mtd->writesize / ecc->size;
1089 for (i = 0; i < nsectors; i++) {
1091 layout->oobfree[i].offset =
1092 layout->oobfree[i - 1].offset +
1093 layout->oobfree[i - 1].length +
1095 layout->oobfree[i].length = 4;
1098 * The first 2 bytes are used for BB markers, hence we
1099 * only have 2 bytes available in the first user data
1102 layout->oobfree[i].length = 2;
1103 layout->oobfree[i].offset = 2;
1106 for (j = 0; j < ecc->bytes; j++)
1107 layout->eccpos[(ecc->bytes * i) + j] =
1108 layout->oobfree[i].offset +
1109 layout->oobfree[i].length + j;
1112 if (mtd->oobsize > (ecc->bytes + 4) * nsectors) {
1113 layout->oobfree[nsectors].offset =
1114 layout->oobfree[nsectors - 1].offset +
1115 layout->oobfree[nsectors - 1].length +
1117 layout->oobfree[nsectors].length = mtd->oobsize -
1118 ((ecc->bytes + 4) * nsectors);
1124 static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd,
1125 struct nand_ecc_ctrl *ecc,
1126 struct device_node *np)
1128 struct nand_ecclayout *layout;
1133 ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc, np);
1138 ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page;
1139 ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page;
1141 layout = ecc->layout;
1142 nsectors = mtd->writesize / ecc->size;
1144 for (i = 0; i < (ecc->bytes * nsectors); i++)
1145 layout->eccpos[i] = i;
1147 layout->oobfree[0].length = mtd->oobsize - i;
1148 layout->oobfree[0].offset = i;
1153 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc)
1155 switch (ecc->mode) {
1157 case NAND_ECC_HW_SYNDROME:
1158 sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc);
1167 static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc,
1168 struct device_node *np)
1170 struct nand_chip *nand = mtd->priv;
1175 blk_size = of_get_nand_ecc_step_size(np);
1176 strength = of_get_nand_ecc_strength(np);
1177 if (blk_size > 0 && strength > 0) {
1178 ecc->size = blk_size;
1179 ecc->strength = strength;
1181 ecc->size = nand->ecc_step_ds;
1182 ecc->strength = nand->ecc_strength_ds;
1185 if (!ecc->size || !ecc->strength)
1188 ecc->mode = NAND_ECC_HW;
1190 ret = of_get_nand_ecc_mode(np);
1194 switch (ecc->mode) {
1195 case NAND_ECC_SOFT_BCH:
1198 ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc, np);
1202 case NAND_ECC_HW_SYNDROME:
1203 ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc, np);
1208 ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL);
1211 ecc->layout->oobfree[0].length = mtd->oobsize;
1221 static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
1222 struct device_node *np)
1224 const struct nand_sdr_timings *timings;
1225 struct sunxi_nand_chip *chip;
1226 struct mtd_part_parser_data ppdata;
1227 struct mtd_info *mtd;
1228 struct nand_chip *nand;
1234 if (!of_get_property(np, "reg", &nsels))
1237 nsels /= sizeof(u32);
1239 dev_err(dev, "invalid reg property size\n");
1243 chip = devm_kzalloc(dev,
1245 (nsels * sizeof(struct sunxi_nand_chip_sel)),
1248 dev_err(dev, "could not allocate chip\n");
1252 chip->nsels = nsels;
1253 chip->selected = -1;
1255 for (i = 0; i < nsels; i++) {
1256 ret = of_property_read_u32_index(np, "reg", i, &tmp);
1258 dev_err(dev, "could not retrieve reg property: %d\n",
1263 if (tmp > NFC_MAX_CS) {
1265 "invalid reg value: %u (max CS = 7)\n",
1270 if (test_and_set_bit(tmp, &nfc->assigned_cs)) {
1271 dev_err(dev, "CS %d already assigned\n", tmp);
1275 chip->sels[i].cs = tmp;
1277 if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
1279 chip->sels[i].rb.type = RB_NATIVE;
1280 chip->sels[i].rb.info.nativeid = tmp;
1282 ret = of_get_named_gpio(np, "rb-gpios", i);
1285 chip->sels[i].rb.type = RB_GPIO;
1286 chip->sels[i].rb.info.gpio = tmp;
1287 ret = devm_gpio_request(dev, tmp, "nand-rb");
1291 ret = gpio_direction_input(tmp);
1295 chip->sels[i].rb.type = RB_NONE;
1300 timings = onfi_async_timing_mode_to_sdr_timings(0);
1301 if (IS_ERR(timings)) {
1302 ret = PTR_ERR(timings);
1304 "could not retrieve timings for ONFI mode 0: %d\n",
1309 ret = sunxi_nand_chip_set_timings(chip, timings);
1311 dev_err(dev, "could not configure chip timings: %d\n", ret);
1316 /* Default tR value specified in the ONFI spec (chapter 4.15.1) */
1317 nand->chip_delay = 200;
1318 nand->controller = &nfc->controller;
1319 nand->select_chip = sunxi_nfc_select_chip;
1320 nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
1321 nand->read_buf = sunxi_nfc_read_buf;
1322 nand->write_buf = sunxi_nfc_write_buf;
1323 nand->read_byte = sunxi_nfc_read_byte;
1325 if (of_get_nand_on_flash_bbt(np))
1326 nand->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
1329 mtd->dev.parent = dev;
1331 mtd->owner = THIS_MODULE;
1333 ret = nand_scan_ident(mtd, nsels, NULL);
1337 ret = sunxi_nand_chip_init_timings(chip, np);
1339 dev_err(dev, "could not configure chip timings: %d\n", ret);
1343 ret = sunxi_nand_ecc_init(mtd, &nand->ecc, np);
1345 dev_err(dev, "ECC init failed: %d\n", ret);
1349 ret = nand_scan_tail(mtd);
1351 dev_err(dev, "nand_scan_tail failed: %d\n", ret);
1355 ppdata.of_node = np;
1356 ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
1358 dev_err(dev, "failed to register mtd device: %d\n", ret);
1363 list_add_tail(&chip->node, &nfc->chips);
1368 static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
1370 struct device_node *np = dev->of_node;
1371 struct device_node *nand_np;
1372 int nchips = of_get_child_count(np);
1376 dev_err(dev, "too many NAND chips: %d (max = 8)\n", nchips);
1380 for_each_child_of_node(np, nand_np) {
1381 ret = sunxi_nand_chip_init(dev, nfc, nand_np);
1389 static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc)
1391 struct sunxi_nand_chip *chip;
1393 while (!list_empty(&nfc->chips)) {
1394 chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip,
1396 nand_release(&chip->mtd);
1397 sunxi_nand_ecc_cleanup(&chip->nand.ecc);
1401 static int sunxi_nfc_probe(struct platform_device *pdev)
1403 struct device *dev = &pdev->dev;
1405 struct sunxi_nfc *nfc;
1409 nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
1414 spin_lock_init(&nfc->controller.lock);
1415 init_waitqueue_head(&nfc->controller.wq);
1416 INIT_LIST_HEAD(&nfc->chips);
1418 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1419 nfc->regs = devm_ioremap_resource(dev, r);
1420 if (IS_ERR(nfc->regs))
1421 return PTR_ERR(nfc->regs);
1423 irq = platform_get_irq(pdev, 0);
1425 dev_err(dev, "failed to retrieve irq\n");
1429 nfc->ahb_clk = devm_clk_get(dev, "ahb");
1430 if (IS_ERR(nfc->ahb_clk)) {
1431 dev_err(dev, "failed to retrieve ahb clk\n");
1432 return PTR_ERR(nfc->ahb_clk);
1435 ret = clk_prepare_enable(nfc->ahb_clk);
1439 nfc->mod_clk = devm_clk_get(dev, "mod");
1440 if (IS_ERR(nfc->mod_clk)) {
1441 dev_err(dev, "failed to retrieve mod clk\n");
1442 ret = PTR_ERR(nfc->mod_clk);
1443 goto out_ahb_clk_unprepare;
1446 ret = clk_prepare_enable(nfc->mod_clk);
1448 goto out_ahb_clk_unprepare;
1450 ret = sunxi_nfc_rst(nfc);
1452 goto out_mod_clk_unprepare;
1454 writel(0, nfc->regs + NFC_REG_INT);
1455 ret = devm_request_irq(dev, irq, sunxi_nfc_interrupt,
1456 0, "sunxi-nand", nfc);
1458 goto out_mod_clk_unprepare;
1460 platform_set_drvdata(pdev, nfc);
1462 ret = sunxi_nand_chips_init(dev, nfc);
1464 dev_err(dev, "failed to init nand chips\n");
1465 goto out_mod_clk_unprepare;
1470 out_mod_clk_unprepare:
1471 clk_disable_unprepare(nfc->mod_clk);
1472 out_ahb_clk_unprepare:
1473 clk_disable_unprepare(nfc->ahb_clk);
1478 static int sunxi_nfc_remove(struct platform_device *pdev)
1480 struct sunxi_nfc *nfc = platform_get_drvdata(pdev);
1482 sunxi_nand_chips_cleanup(nfc);
1487 static const struct of_device_id sunxi_nfc_ids[] = {
1488 { .compatible = "allwinner,sun4i-a10-nand" },
1491 MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
1493 static struct platform_driver sunxi_nfc_driver = {
1495 .name = "sunxi_nand",
1496 .of_match_table = sunxi_nfc_ids,
1498 .probe = sunxi_nfc_probe,
1499 .remove = sunxi_nfc_remove,
1501 module_platform_driver(sunxi_nfc_driver);
1503 MODULE_LICENSE("GPL v2");
1504 MODULE_AUTHOR("Boris BREZILLON");
1505 MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
1506 MODULE_ALIAS("platform:sunxi_nand");