5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * David Woodhouse for adding multichip support
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/interrupt.h>
46 #include <linux/bitops.h>
47 #include <linux/leds.h>
50 #ifdef CONFIG_MTD_PARTITIONS
51 #include <linux/mtd/partitions.h>
54 /* Define default oob placement schemes for large and small page devices */
55 static struct nand_ecclayout nand_oob_8 = {
65 static struct nand_ecclayout nand_oob_16 = {
67 .eccpos = {0, 1, 2, 3, 6, 7},
73 static struct nand_ecclayout nand_oob_64 = {
76 40, 41, 42, 43, 44, 45, 46, 47,
77 48, 49, 50, 51, 52, 53, 54, 55,
78 56, 57, 58, 59, 60, 61, 62, 63},
84 static struct nand_ecclayout nand_oob_128 = {
87 80, 81, 82, 83, 84, 85, 86, 87,
88 88, 89, 90, 91, 92, 93, 94, 95,
89 96, 97, 98, 99, 100, 101, 102, 103,
90 104, 105, 106, 107, 108, 109, 110, 111,
91 112, 113, 114, 115, 116, 117, 118, 119,
92 120, 121, 122, 123, 124, 125, 126, 127},
98 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
101 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
102 struct mtd_oob_ops *ops);
105 * For devices which display every fart in the system on a separate LED. Is
106 * compiled away when LED support is disabled.
108 DEFINE_LED_TRIGGER(nand_led_trigger);
110 static int check_offs_len(struct mtd_info *mtd,
111 loff_t ofs, uint64_t len)
113 struct nand_chip *chip = mtd->priv;
116 /* Start address must align on block boundary */
117 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
118 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
122 /* Length must align on block boundary */
123 if (len & ((1 << chip->phys_erase_shift) - 1)) {
124 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
129 /* Do not allow past end of device */
130 if (ofs + len > mtd->size) {
131 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
140 * nand_release_device - [GENERIC] release chip
141 * @mtd: MTD device structure
143 * Deselect, release chip lock and wake up anyone waiting on the device
145 static void nand_release_device(struct mtd_info *mtd)
147 struct nand_chip *chip = mtd->priv;
149 /* De-select the NAND device */
150 chip->select_chip(mtd, -1);
152 /* Release the controller and the chip */
153 spin_lock(&chip->controller->lock);
154 chip->controller->active = NULL;
155 chip->state = FL_READY;
156 wake_up(&chip->controller->wq);
157 spin_unlock(&chip->controller->lock);
161 * nand_read_byte - [DEFAULT] read one byte from the chip
162 * @mtd: MTD device structure
164 * Default read function for 8bit buswith
166 static uint8_t nand_read_byte(struct mtd_info *mtd)
168 struct nand_chip *chip = mtd->priv;
169 return readb(chip->IO_ADDR_R);
173 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
174 * @mtd: MTD device structure
176 * Default read function for 16bit buswith with
177 * endianess conversion
179 static uint8_t nand_read_byte16(struct mtd_info *mtd)
181 struct nand_chip *chip = mtd->priv;
182 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
186 * nand_read_word - [DEFAULT] read one word from the chip
187 * @mtd: MTD device structure
189 * Default read function for 16bit buswith without
190 * endianess conversion
192 static u16 nand_read_word(struct mtd_info *mtd)
194 struct nand_chip *chip = mtd->priv;
195 return readw(chip->IO_ADDR_R);
199 * nand_select_chip - [DEFAULT] control CE line
200 * @mtd: MTD device structure
201 * @chipnr: chipnumber to select, -1 for deselect
203 * Default select function for 1 chip devices.
205 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
207 struct nand_chip *chip = mtd->priv;
211 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
222 * nand_write_buf - [DEFAULT] write buffer to chip
223 * @mtd: MTD device structure
225 * @len: number of bytes to write
227 * Default write function for 8bit buswith
229 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
232 struct nand_chip *chip = mtd->priv;
234 for (i = 0; i < len; i++)
235 writeb(buf[i], chip->IO_ADDR_W);
239 * nand_read_buf - [DEFAULT] read chip data into buffer
240 * @mtd: MTD device structure
241 * @buf: buffer to store date
242 * @len: number of bytes to read
244 * Default read function for 8bit buswith
246 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
249 struct nand_chip *chip = mtd->priv;
251 for (i = 0; i < len; i++)
252 buf[i] = readb(chip->IO_ADDR_R);
256 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
257 * @mtd: MTD device structure
258 * @buf: buffer containing the data to compare
259 * @len: number of bytes to compare
261 * Default verify function for 8bit buswith
263 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
266 struct nand_chip *chip = mtd->priv;
268 for (i = 0; i < len; i++)
269 if (buf[i] != readb(chip->IO_ADDR_R))
275 * nand_write_buf16 - [DEFAULT] write buffer to chip
276 * @mtd: MTD device structure
278 * @len: number of bytes to write
280 * Default write function for 16bit buswith
282 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
285 struct nand_chip *chip = mtd->priv;
286 u16 *p = (u16 *) buf;
289 for (i = 0; i < len; i++)
290 writew(p[i], chip->IO_ADDR_W);
295 * nand_read_buf16 - [DEFAULT] read chip data into buffer
296 * @mtd: MTD device structure
297 * @buf: buffer to store date
298 * @len: number of bytes to read
300 * Default read function for 16bit buswith
302 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
305 struct nand_chip *chip = mtd->priv;
306 u16 *p = (u16 *) buf;
309 for (i = 0; i < len; i++)
310 p[i] = readw(chip->IO_ADDR_R);
314 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
315 * @mtd: MTD device structure
316 * @buf: buffer containing the data to compare
317 * @len: number of bytes to compare
319 * Default verify function for 16bit buswith
321 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
324 struct nand_chip *chip = mtd->priv;
325 u16 *p = (u16 *) buf;
328 for (i = 0; i < len; i++)
329 if (p[i] != readw(chip->IO_ADDR_R))
336 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
337 * @mtd: MTD device structure
338 * @ofs: offset from device start
339 * @getchip: 0, if the chip is already selected
341 * Check, if the block is bad.
343 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
345 int page, chipnr, res = 0;
346 struct nand_chip *chip = mtd->priv;
349 if (chip->options & NAND_BBT_SCANLASTPAGE)
350 ofs += mtd->erasesize - mtd->writesize;
352 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
355 chipnr = (int)(ofs >> chip->chip_shift);
357 nand_get_device(chip, mtd, FL_READING);
359 /* Select the NAND device */
360 chip->select_chip(mtd, chipnr);
363 if (chip->options & NAND_BUSWIDTH_16) {
364 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
366 bad = cpu_to_le16(chip->read_word(mtd));
367 if (chip->badblockpos & 0x1)
372 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
373 bad = chip->read_byte(mtd);
376 if (likely(chip->badblockbits == 8))
379 res = hweight8(bad) < chip->badblockbits;
382 nand_release_device(mtd);
388 * nand_default_block_markbad - [DEFAULT] mark a block bad
389 * @mtd: MTD device structure
390 * @ofs: offset from device start
392 * This is the default implementation, which can be overridden by
393 * a hardware specific driver.
395 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
397 struct nand_chip *chip = mtd->priv;
398 uint8_t buf[2] = { 0, 0 };
399 int block, ret, i = 0;
401 if (chip->options & NAND_BBT_SCANLASTPAGE)
402 ofs += mtd->erasesize - mtd->writesize;
404 /* Get block number */
405 block = (int)(ofs >> chip->bbt_erase_shift);
407 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
409 /* Do we have a flash based bad block table ? */
410 if (chip->options & NAND_USE_FLASH_BBT)
411 ret = nand_update_bbt(mtd, ofs);
413 nand_get_device(chip, mtd, FL_WRITING);
415 /* Write to first two pages and to byte 1 and 6 if necessary.
416 * If we write to more than one location, the first error
417 * encountered quits the procedure. We write two bytes per
418 * location, so we dont have to mess with 16 bit access.
421 chip->ops.len = chip->ops.ooblen = 2;
422 chip->ops.datbuf = NULL;
423 chip->ops.oobbuf = buf;
424 chip->ops.ooboffs = chip->badblockpos & ~0x01;
426 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
428 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
429 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
431 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
434 ofs += mtd->writesize;
435 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
438 nand_release_device(mtd);
441 mtd->ecc_stats.badblocks++;
447 * nand_check_wp - [GENERIC] check if the chip is write protected
448 * @mtd: MTD device structure
449 * Check, if the device is write protected
451 * The function expects, that the device is already selected
453 static int nand_check_wp(struct mtd_info *mtd)
455 struct nand_chip *chip = mtd->priv;
457 /* broken xD cards report WP despite being writable */
458 if (chip->options & NAND_BROKEN_XD)
461 /* Check the WP bit */
462 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
463 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
467 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
468 * @mtd: MTD device structure
469 * @ofs: offset from device start
470 * @getchip: 0, if the chip is already selected
471 * @allowbbt: 1, if its allowed to access the bbt area
473 * Check, if the block is bad. Either by reading the bad block table or
474 * calling of the scan function.
476 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
479 struct nand_chip *chip = mtd->priv;
482 return chip->block_bad(mtd, ofs, getchip);
484 /* Return info from the table */
485 return nand_isbad_bbt(mtd, ofs, allowbbt);
489 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
490 * @mtd: MTD device structure
493 * Helper function for nand_wait_ready used when needing to wait in interrupt
496 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
498 struct nand_chip *chip = mtd->priv;
501 /* Wait for the device to get ready */
502 for (i = 0; i < timeo; i++) {
503 if (chip->dev_ready(mtd))
505 touch_softlockup_watchdog();
511 * Wait for the ready pin, after a command
512 * The timeout is catched later.
514 void nand_wait_ready(struct mtd_info *mtd)
516 struct nand_chip *chip = mtd->priv;
517 unsigned long timeo = jiffies + 2;
520 if (in_interrupt() || oops_in_progress)
521 return panic_nand_wait_ready(mtd, 400);
523 led_trigger_event(nand_led_trigger, LED_FULL);
524 /* wait until command is processed or timeout occures */
526 if (chip->dev_ready(mtd))
528 touch_softlockup_watchdog();
529 } while (time_before(jiffies, timeo));
530 led_trigger_event(nand_led_trigger, LED_OFF);
532 EXPORT_SYMBOL_GPL(nand_wait_ready);
535 * nand_command - [DEFAULT] Send command to NAND device
536 * @mtd: MTD device structure
537 * @command: the command to be sent
538 * @column: the column address for this command, -1 if none
539 * @page_addr: the page address for this command, -1 if none
541 * Send command to NAND device. This function is used for small page
542 * devices (256/512 Bytes per page)
544 static void nand_command(struct mtd_info *mtd, unsigned int command,
545 int column, int page_addr)
547 register struct nand_chip *chip = mtd->priv;
548 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
551 * Write out the command to the device.
553 if (command == NAND_CMD_SEQIN) {
556 if (column >= mtd->writesize) {
558 column -= mtd->writesize;
559 readcmd = NAND_CMD_READOOB;
560 } else if (column < 256) {
561 /* First 256 bytes --> READ0 */
562 readcmd = NAND_CMD_READ0;
565 readcmd = NAND_CMD_READ1;
567 chip->cmd_ctrl(mtd, readcmd, ctrl);
568 ctrl &= ~NAND_CTRL_CHANGE;
570 chip->cmd_ctrl(mtd, command, ctrl);
573 * Address cycle, when necessary
575 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
576 /* Serially input address */
578 /* Adjust columns for 16 bit buswidth */
579 if (chip->options & NAND_BUSWIDTH_16)
581 chip->cmd_ctrl(mtd, column, ctrl);
582 ctrl &= ~NAND_CTRL_CHANGE;
584 if (page_addr != -1) {
585 chip->cmd_ctrl(mtd, page_addr, ctrl);
586 ctrl &= ~NAND_CTRL_CHANGE;
587 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
588 /* One more address cycle for devices > 32MiB */
589 if (chip->chipsize > (32 << 20))
590 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
592 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
595 * program and erase have their own busy handlers
596 * status and sequential in needs no delay
600 case NAND_CMD_PAGEPROG:
601 case NAND_CMD_ERASE1:
602 case NAND_CMD_ERASE2:
604 case NAND_CMD_STATUS:
610 udelay(chip->chip_delay);
611 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
612 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
614 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
615 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
618 /* This applies to read commands */
621 * If we don't have access to the busy pin, we apply the given
624 if (!chip->dev_ready) {
625 udelay(chip->chip_delay);
629 /* Apply this short delay always to ensure that we do wait tWB in
630 * any case on any machine. */
633 nand_wait_ready(mtd);
637 * nand_command_lp - [DEFAULT] Send command to NAND large page device
638 * @mtd: MTD device structure
639 * @command: the command to be sent
640 * @column: the column address for this command, -1 if none
641 * @page_addr: the page address for this command, -1 if none
643 * Send command to NAND device. This is the version for the new large page
644 * devices We dont have the separate regions as we have in the small page
645 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
647 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
648 int column, int page_addr)
650 register struct nand_chip *chip = mtd->priv;
652 /* Emulate NAND_CMD_READOOB */
653 if (command == NAND_CMD_READOOB) {
654 column += mtd->writesize;
655 command = NAND_CMD_READ0;
658 /* Command latch cycle */
659 chip->cmd_ctrl(mtd, command & 0xff,
660 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
662 if (column != -1 || page_addr != -1) {
663 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
665 /* Serially input address */
667 /* Adjust columns for 16 bit buswidth */
668 if (chip->options & NAND_BUSWIDTH_16)
670 chip->cmd_ctrl(mtd, column, ctrl);
671 ctrl &= ~NAND_CTRL_CHANGE;
672 chip->cmd_ctrl(mtd, column >> 8, ctrl);
674 if (page_addr != -1) {
675 chip->cmd_ctrl(mtd, page_addr, ctrl);
676 chip->cmd_ctrl(mtd, page_addr >> 8,
677 NAND_NCE | NAND_ALE);
678 /* One more address cycle for devices > 128MiB */
679 if (chip->chipsize > (128 << 20))
680 chip->cmd_ctrl(mtd, page_addr >> 16,
681 NAND_NCE | NAND_ALE);
684 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
687 * program and erase have their own busy handlers
688 * status, sequential in, and deplete1 need no delay
692 case NAND_CMD_CACHEDPROG:
693 case NAND_CMD_PAGEPROG:
694 case NAND_CMD_ERASE1:
695 case NAND_CMD_ERASE2:
698 case NAND_CMD_STATUS:
699 case NAND_CMD_DEPLETE1:
703 * read error status commands require only a short delay
705 case NAND_CMD_STATUS_ERROR:
706 case NAND_CMD_STATUS_ERROR0:
707 case NAND_CMD_STATUS_ERROR1:
708 case NAND_CMD_STATUS_ERROR2:
709 case NAND_CMD_STATUS_ERROR3:
710 udelay(chip->chip_delay);
716 udelay(chip->chip_delay);
717 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
718 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
719 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
720 NAND_NCE | NAND_CTRL_CHANGE);
721 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) ;
724 case NAND_CMD_RNDOUT:
725 /* No ready / busy check necessary */
726 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
727 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
728 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
729 NAND_NCE | NAND_CTRL_CHANGE);
733 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
738 /* This applies to read commands */
741 * If we don't have access to the busy pin, we apply the given
744 if (!chip->dev_ready) {
745 udelay(chip->chip_delay);
750 /* Apply this short delay always to ensure that we do wait tWB in
751 * any case on any machine. */
754 nand_wait_ready(mtd);
758 * panic_nand_get_device - [GENERIC] Get chip for selected access
759 * @chip: the nand chip descriptor
760 * @mtd: MTD device structure
761 * @new_state: the state which is requested
763 * Used when in panic, no locks are taken.
765 static void panic_nand_get_device(struct nand_chip *chip,
766 struct mtd_info *mtd, int new_state)
768 /* Hardware controller shared among independend devices */
769 chip->controller->active = chip;
770 chip->state = new_state;
774 * nand_get_device - [GENERIC] Get chip for selected access
775 * @chip: the nand chip descriptor
776 * @mtd: MTD device structure
777 * @new_state: the state which is requested
779 * Get the device and lock it for exclusive access
782 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
784 spinlock_t *lock = &chip->controller->lock;
785 wait_queue_head_t *wq = &chip->controller->wq;
786 DECLARE_WAITQUEUE(wait, current);
790 /* Hardware controller shared among independent devices */
791 if (!chip->controller->active)
792 chip->controller->active = chip;
794 if (chip->controller->active == chip && chip->state == FL_READY) {
795 chip->state = new_state;
799 if (new_state == FL_PM_SUSPENDED) {
800 if (chip->controller->active->state == FL_PM_SUSPENDED) {
801 chip->state = FL_PM_SUSPENDED;
806 set_current_state(TASK_UNINTERRUPTIBLE);
807 add_wait_queue(wq, &wait);
810 remove_wait_queue(wq, &wait);
815 * panic_nand_wait - [GENERIC] wait until the command is done
816 * @mtd: MTD device structure
817 * @chip: NAND chip structure
820 * Wait for command done. This is a helper function for nand_wait used when
821 * we are in interrupt context. May happen when in panic and trying to write
822 * an oops trough mtdoops.
824 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
828 for (i = 0; i < timeo; i++) {
829 if (chip->dev_ready) {
830 if (chip->dev_ready(mtd))
833 if (chip->read_byte(mtd) & NAND_STATUS_READY)
841 * nand_wait - [DEFAULT] wait until the command is done
842 * @mtd: MTD device structure
843 * @chip: NAND chip structure
845 * Wait for command done. This applies to erase and program only
846 * Erase can take up to 400ms and program up to 20ms according to
847 * general NAND and SmartMedia specs
849 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
852 unsigned long timeo = jiffies;
853 int status, state = chip->state;
855 if (state == FL_ERASING)
856 timeo += (HZ * 400) / 1000;
858 timeo += (HZ * 20) / 1000;
860 led_trigger_event(nand_led_trigger, LED_FULL);
862 /* Apply this short delay always to ensure that we do wait tWB in
863 * any case on any machine. */
866 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
867 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
869 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
871 if (in_interrupt() || oops_in_progress)
872 panic_nand_wait(mtd, chip, timeo);
874 while (time_before(jiffies, timeo)) {
875 if (chip->dev_ready) {
876 if (chip->dev_ready(mtd))
879 if (chip->read_byte(mtd) & NAND_STATUS_READY)
885 led_trigger_event(nand_led_trigger, LED_OFF);
887 status = (int)chip->read_byte(mtd);
892 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
895 * @ofs: offset to start unlock from
896 * @len: length to unlock
897 * @invert: when = 0, unlock the range of blocks within the lower and
898 * upper boundary address
899 * when = 1, unlock the range of blocks outside the boundaries
900 * of the lower and upper boundary address
902 * return - unlock status
904 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
905 uint64_t len, int invert)
909 struct nand_chip *chip = mtd->priv;
911 /* Submit address of first page to unlock */
912 page = ofs >> chip->page_shift;
913 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
915 /* Submit address of last page to unlock */
916 page = (ofs + len) >> chip->page_shift;
917 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
918 (page | invert) & chip->pagemask);
920 /* Call wait ready function */
921 status = chip->waitfunc(mtd, chip);
923 /* See if device thinks it succeeded */
925 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
934 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
937 * @ofs: offset to start unlock from
938 * @len: length to unlock
940 * return - unlock status
942 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
946 struct nand_chip *chip = mtd->priv;
948 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
949 __func__, (unsigned long long)ofs, len);
951 if (check_offs_len(mtd, ofs, len))
954 /* Align to last block address if size addresses end of the device */
955 if (ofs + len == mtd->size)
956 len -= mtd->erasesize;
958 nand_get_device(chip, mtd, FL_UNLOCKING);
960 /* Shift to get chip number */
961 chipnr = ofs >> chip->chip_shift;
963 chip->select_chip(mtd, chipnr);
965 /* Check, if it is write protected */
966 if (nand_check_wp(mtd)) {
967 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
973 ret = __nand_unlock(mtd, ofs, len, 0);
976 /* de-select the NAND device */
977 chip->select_chip(mtd, -1);
979 nand_release_device(mtd);
985 * nand_lock - [REPLACEABLE] locks all blocks present in the device
988 * @ofs: offset to start unlock from
989 * @len: length to unlock
991 * return - lock status
993 * This feature is not supported in many NAND parts. 'Micron' NAND parts
994 * do have this feature, but it allows only to lock all blocks, not for
995 * specified range for block.
997 * Implementing 'lock' feature by making use of 'unlock', for now.
999 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1002 int chipnr, status, page;
1003 struct nand_chip *chip = mtd->priv;
1005 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1006 __func__, (unsigned long long)ofs, len);
1008 if (check_offs_len(mtd, ofs, len))
1011 nand_get_device(chip, mtd, FL_LOCKING);
1013 /* Shift to get chip number */
1014 chipnr = ofs >> chip->chip_shift;
1016 chip->select_chip(mtd, chipnr);
1018 /* Check, if it is write protected */
1019 if (nand_check_wp(mtd)) {
1020 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1022 status = MTD_ERASE_FAILED;
1027 /* Submit address of first page to lock */
1028 page = ofs >> chip->page_shift;
1029 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1031 /* Call wait ready function */
1032 status = chip->waitfunc(mtd, chip);
1034 /* See if device thinks it succeeded */
1035 if (status & 0x01) {
1036 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1042 ret = __nand_unlock(mtd, ofs, len, 0x1);
1045 /* de-select the NAND device */
1046 chip->select_chip(mtd, -1);
1048 nand_release_device(mtd);
1054 * nand_read_page_raw - [Intern] read raw page data without ecc
1055 * @mtd: mtd info structure
1056 * @chip: nand chip info structure
1057 * @buf: buffer to store read data
1058 * @page: page number to read
1060 * Not for syndrome calculating ecc controllers, which use a special oob layout
1062 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1063 uint8_t *buf, int page)
1065 chip->read_buf(mtd, buf, mtd->writesize);
1066 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1071 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1072 * @mtd: mtd info structure
1073 * @chip: nand chip info structure
1074 * @buf: buffer to store read data
1075 * @page: page number to read
1077 * We need a special oob layout and handling even when OOB isn't used.
1079 static int nand_read_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1080 uint8_t *buf, int page)
1082 int eccsize = chip->ecc.size;
1083 int eccbytes = chip->ecc.bytes;
1084 uint8_t *oob = chip->oob_poi;
1087 for (steps = chip->ecc.steps; steps > 0; steps--) {
1088 chip->read_buf(mtd, buf, eccsize);
1091 if (chip->ecc.prepad) {
1092 chip->read_buf(mtd, oob, chip->ecc.prepad);
1093 oob += chip->ecc.prepad;
1096 chip->read_buf(mtd, oob, eccbytes);
1099 if (chip->ecc.postpad) {
1100 chip->read_buf(mtd, oob, chip->ecc.postpad);
1101 oob += chip->ecc.postpad;
1105 size = mtd->oobsize - (oob - chip->oob_poi);
1107 chip->read_buf(mtd, oob, size);
1113 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1114 * @mtd: mtd info structure
1115 * @chip: nand chip info structure
1116 * @buf: buffer to store read data
1117 * @page: page number to read
1119 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1120 uint8_t *buf, int page)
1122 int i, eccsize = chip->ecc.size;
1123 int eccbytes = chip->ecc.bytes;
1124 int eccsteps = chip->ecc.steps;
1126 uint8_t *ecc_calc = chip->buffers->ecccalc;
1127 uint8_t *ecc_code = chip->buffers->ecccode;
1128 uint32_t *eccpos = chip->ecc.layout->eccpos;
1130 chip->ecc.read_page_raw(mtd, chip, buf, page);
1132 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1133 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1135 for (i = 0; i < chip->ecc.total; i++)
1136 ecc_code[i] = chip->oob_poi[eccpos[i]];
1138 eccsteps = chip->ecc.steps;
1141 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1144 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1146 mtd->ecc_stats.failed++;
1148 mtd->ecc_stats.corrected += stat;
1154 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1155 * @mtd: mtd info structure
1156 * @chip: nand chip info structure
1157 * @data_offs: offset of requested data within the page
1158 * @readlen: data length
1159 * @bufpoi: buffer to store read data
1161 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip, uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1163 int start_step, end_step, num_steps;
1164 uint32_t *eccpos = chip->ecc.layout->eccpos;
1166 int data_col_addr, i, gaps = 0;
1167 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1168 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1170 /* Column address wihin the page aligned to ECC size (256bytes). */
1171 start_step = data_offs / chip->ecc.size;
1172 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1173 num_steps = end_step - start_step + 1;
1175 /* Data size aligned to ECC ecc.size*/
1176 datafrag_len = num_steps * chip->ecc.size;
1177 eccfrag_len = num_steps * chip->ecc.bytes;
1179 data_col_addr = start_step * chip->ecc.size;
1180 /* If we read not a page aligned data */
1181 if (data_col_addr != 0)
1182 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1184 p = bufpoi + data_col_addr;
1185 chip->read_buf(mtd, p, datafrag_len);
1188 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1189 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1191 /* The performance is faster if to position offsets
1192 according to ecc.pos. Let make sure here that
1193 there are no gaps in ecc positions */
1194 for (i = 0; i < eccfrag_len - 1; i++) {
1195 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1196 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1202 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1203 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1205 /* send the command to read the particular ecc bytes */
1206 /* take care about buswidth alignment in read_buf */
1207 aligned_pos = eccpos[start_step * chip->ecc.bytes] & ~(busw - 1);
1208 aligned_len = eccfrag_len;
1209 if (eccpos[start_step * chip->ecc.bytes] & (busw - 1))
1211 if (eccpos[(start_step + num_steps) * chip->ecc.bytes] & (busw - 1))
1214 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize + aligned_pos, -1);
1215 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1218 for (i = 0; i < eccfrag_len; i++)
1219 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + start_step * chip->ecc.bytes]];
1221 p = bufpoi + data_col_addr;
1222 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1225 stat = chip->ecc.correct(mtd, p, &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1227 mtd->ecc_stats.failed++;
1229 mtd->ecc_stats.corrected += stat;
1235 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1236 * @mtd: mtd info structure
1237 * @chip: nand chip info structure
1238 * @buf: buffer to store read data
1239 * @page: page number to read
1241 * Not for syndrome calculating ecc controllers which need a special oob layout
1243 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1244 uint8_t *buf, int page)
1246 int i, eccsize = chip->ecc.size;
1247 int eccbytes = chip->ecc.bytes;
1248 int eccsteps = chip->ecc.steps;
1250 uint8_t *ecc_calc = chip->buffers->ecccalc;
1251 uint8_t *ecc_code = chip->buffers->ecccode;
1252 uint32_t *eccpos = chip->ecc.layout->eccpos;
1254 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1255 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1256 chip->read_buf(mtd, p, eccsize);
1257 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1259 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1261 for (i = 0; i < chip->ecc.total; i++)
1262 ecc_code[i] = chip->oob_poi[eccpos[i]];
1264 eccsteps = chip->ecc.steps;
1267 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1270 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1272 mtd->ecc_stats.failed++;
1274 mtd->ecc_stats.corrected += stat;
1280 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1281 * @mtd: mtd info structure
1282 * @chip: nand chip info structure
1283 * @buf: buffer to store read data
1284 * @page: page number to read
1286 * Hardware ECC for large page chips, require OOB to be read first.
1287 * For this ECC mode, the write_page method is re-used from ECC_HW.
1288 * These methods read/write ECC from the OOB area, unlike the
1289 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1290 * "infix ECC" scheme and reads/writes ECC from the data area, by
1291 * overwriting the NAND manufacturer bad block markings.
1293 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1294 struct nand_chip *chip, uint8_t *buf, int page)
1296 int i, eccsize = chip->ecc.size;
1297 int eccbytes = chip->ecc.bytes;
1298 int eccsteps = chip->ecc.steps;
1300 uint8_t *ecc_code = chip->buffers->ecccode;
1301 uint32_t *eccpos = chip->ecc.layout->eccpos;
1302 uint8_t *ecc_calc = chip->buffers->ecccalc;
1304 /* Read the OOB area first */
1305 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1306 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1307 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1309 for (i = 0; i < chip->ecc.total; i++)
1310 ecc_code[i] = chip->oob_poi[eccpos[i]];
1312 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1315 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1316 chip->read_buf(mtd, p, eccsize);
1317 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1319 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1321 mtd->ecc_stats.failed++;
1323 mtd->ecc_stats.corrected += stat;
1329 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1330 * @mtd: mtd info structure
1331 * @chip: nand chip info structure
1332 * @buf: buffer to store read data
1333 * @page: page number to read
1335 * The hw generator calculates the error syndrome automatically. Therefor
1336 * we need a special oob layout and handling.
1338 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1339 uint8_t *buf, int page)
1341 int i, eccsize = chip->ecc.size;
1342 int eccbytes = chip->ecc.bytes;
1343 int eccsteps = chip->ecc.steps;
1345 uint8_t *oob = chip->oob_poi;
1347 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1350 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1351 chip->read_buf(mtd, p, eccsize);
1353 if (chip->ecc.prepad) {
1354 chip->read_buf(mtd, oob, chip->ecc.prepad);
1355 oob += chip->ecc.prepad;
1358 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1359 chip->read_buf(mtd, oob, eccbytes);
1360 stat = chip->ecc.correct(mtd, p, oob, NULL);
1363 mtd->ecc_stats.failed++;
1365 mtd->ecc_stats.corrected += stat;
1369 if (chip->ecc.postpad) {
1370 chip->read_buf(mtd, oob, chip->ecc.postpad);
1371 oob += chip->ecc.postpad;
1375 /* Calculate remaining oob bytes */
1376 i = mtd->oobsize - (oob - chip->oob_poi);
1378 chip->read_buf(mtd, oob, i);
1384 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1385 * @chip: nand chip structure
1386 * @oob: oob destination address
1387 * @ops: oob ops structure
1388 * @len: size of oob to transfer
1390 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1391 struct mtd_oob_ops *ops, size_t len)
1397 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1400 case MTD_OOB_AUTO: {
1401 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1402 uint32_t boffs = 0, roffs = ops->ooboffs;
1405 for(; free->length && len; free++, len -= bytes) {
1406 /* Read request not from offset 0 ? */
1407 if (unlikely(roffs)) {
1408 if (roffs >= free->length) {
1409 roffs -= free->length;
1412 boffs = free->offset + roffs;
1413 bytes = min_t(size_t, len,
1414 (free->length - roffs));
1417 bytes = min_t(size_t, len, free->length);
1418 boffs = free->offset;
1420 memcpy(oob, chip->oob_poi + boffs, bytes);
1432 * nand_do_read_ops - [Internal] Read data with ECC
1434 * @mtd: MTD device structure
1435 * @from: offset to read from
1436 * @ops: oob ops structure
1438 * Internal function. Called with chip held.
1440 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1441 struct mtd_oob_ops *ops)
1443 int chipnr, page, realpage, col, bytes, aligned;
1444 struct nand_chip *chip = mtd->priv;
1445 struct mtd_ecc_stats stats;
1446 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1449 uint32_t readlen = ops->len;
1450 uint32_t oobreadlen = ops->ooblen;
1451 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1452 mtd->oobavail : mtd->oobsize;
1454 uint8_t *bufpoi, *oob, *buf;
1456 stats = mtd->ecc_stats;
1458 chipnr = (int)(from >> chip->chip_shift);
1459 chip->select_chip(mtd, chipnr);
1461 realpage = (int)(from >> chip->page_shift);
1462 page = realpage & chip->pagemask;
1464 col = (int)(from & (mtd->writesize - 1));
1470 bytes = min(mtd->writesize - col, readlen);
1471 aligned = (bytes == mtd->writesize);
1473 /* Is the current page in the buffer ? */
1474 if (realpage != chip->pagebuf || oob) {
1475 bufpoi = aligned ? buf : chip->buffers->databuf;
1477 if (likely(sndcmd)) {
1478 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1482 /* Now read the page into the buffer */
1483 if (unlikely(ops->mode == MTD_OOB_RAW))
1484 ret = chip->ecc.read_page_raw(mtd, chip,
1486 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1487 ret = chip->ecc.read_subpage(mtd, chip, col, bytes, bufpoi);
1489 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1491 #ifdef CONFIG_MTD_NAND_RK29
1492 extern int rk29_nand_refresh(struct mtd_info *mtd, int srcAddr);
1494 ret=rk29_nand_refresh(mtd, page<<chip->page_shift);
1501 /* Transfer not aligned data */
1503 if (!NAND_SUBPAGE_READ(chip) && !oob)
1504 chip->pagebuf = realpage;
1505 memcpy(buf, chip->buffers->databuf + col, bytes);
1510 if (unlikely(oob)) {
1512 int toread = min(oobreadlen, max_oobsize);
1515 oob = nand_transfer_oob(chip,
1517 oobreadlen -= toread;
1521 if (!(chip->options & NAND_NO_READRDY)) {
1523 * Apply delay or wait for ready/busy pin. Do
1524 * this before the AUTOINCR check, so no
1525 * problems arise if a chip which does auto
1526 * increment is marked as NOAUTOINCR by the
1529 if (!chip->dev_ready)
1530 udelay(chip->chip_delay);
1532 nand_wait_ready(mtd);
1535 memcpy(buf, chip->buffers->databuf + col, bytes);
1544 /* For subsequent reads align to page boundary. */
1546 /* Increment page address */
1549 page = realpage & chip->pagemask;
1550 /* Check, if we cross a chip boundary */
1553 chip->select_chip(mtd, -1);
1554 chip->select_chip(mtd, chipnr);
1557 /* Check, if the chip supports auto page increment
1558 * or if we have hit a block boundary.
1560 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1564 ops->retlen = ops->len - (size_t) readlen;
1566 ops->oobretlen = ops->ooblen - oobreadlen;
1571 if (mtd->ecc_stats.failed - stats.failed)
1574 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1578 * nand_read - [MTD Interface] MTD compability function for nand_do_read_ecc
1579 * @mtd: MTD device structure
1580 * @from: offset to read from
1581 * @len: number of bytes to read
1582 * @retlen: pointer to variable to store the number of read bytes
1583 * @buf: the databuffer to put data
1585 * Get hold of the chip and call nand_do_read
1587 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1588 size_t *retlen, uint8_t *buf)
1590 struct nand_chip *chip = mtd->priv;
1593 /* Do not allow reads past end of device */
1594 if ((from + len) > mtd->size)
1599 nand_get_device(chip, mtd, FL_READING);
1601 chip->ops.len = len;
1602 chip->ops.datbuf = buf;
1603 chip->ops.oobbuf = NULL;
1605 ret = nand_do_read_ops(mtd, from, &chip->ops);
1607 *retlen = chip->ops.retlen;
1609 nand_release_device(mtd);
1615 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1616 * @mtd: mtd info structure
1617 * @chip: nand chip info structure
1618 * @page: page number to read
1619 * @sndcmd: flag whether to issue read command or not
1621 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1622 int page, int sndcmd)
1625 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1628 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1633 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1635 * @mtd: mtd info structure
1636 * @chip: nand chip info structure
1637 * @page: page number to read
1638 * @sndcmd: flag whether to issue read command or not
1640 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1641 int page, int sndcmd)
1643 uint8_t *buf = chip->oob_poi;
1644 int length = mtd->oobsize;
1645 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1646 int eccsize = chip->ecc.size;
1647 uint8_t *bufpoi = buf;
1648 int i, toread, sndrnd = 0, pos;
1650 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1651 for (i = 0; i < chip->ecc.steps; i++) {
1653 pos = eccsize + i * (eccsize + chunk);
1654 if (mtd->writesize > 512)
1655 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1657 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1660 toread = min_t(int, length, chunk);
1661 chip->read_buf(mtd, bufpoi, toread);
1666 chip->read_buf(mtd, bufpoi, length);
1672 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1673 * @mtd: mtd info structure
1674 * @chip: nand chip info structure
1675 * @page: page number to write
1677 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1681 const uint8_t *buf = chip->oob_poi;
1682 int length = mtd->oobsize;
1684 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1685 chip->write_buf(mtd, buf, length);
1686 /* Send command to program the OOB data */
1687 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1689 status = chip->waitfunc(mtd, chip);
1691 return status & NAND_STATUS_FAIL ? -EIO : 0;
1695 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1696 * with syndrome - only for large page flash !
1697 * @mtd: mtd info structure
1698 * @chip: nand chip info structure
1699 * @page: page number to write
1701 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1702 struct nand_chip *chip, int page)
1704 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1705 int eccsize = chip->ecc.size, length = mtd->oobsize;
1706 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1707 const uint8_t *bufpoi = chip->oob_poi;
1710 * data-ecc-data-ecc ... ecc-oob
1712 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1714 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1715 pos = steps * (eccsize + chunk);
1720 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1721 for (i = 0; i < steps; i++) {
1723 if (mtd->writesize <= 512) {
1724 uint32_t fill = 0xFFFFFFFF;
1728 int num = min_t(int, len, 4);
1729 chip->write_buf(mtd, (uint8_t *)&fill,
1734 pos = eccsize + i * (eccsize + chunk);
1735 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1739 len = min_t(int, length, chunk);
1740 chip->write_buf(mtd, bufpoi, len);
1745 chip->write_buf(mtd, bufpoi, length);
1747 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1748 status = chip->waitfunc(mtd, chip);
1750 return status & NAND_STATUS_FAIL ? -EIO : 0;
1754 * nand_do_read_oob - [Intern] NAND read out-of-band
1755 * @mtd: MTD device structure
1756 * @from: offset to read from
1757 * @ops: oob operations description structure
1759 * NAND read out-of-band data from the spare area
1761 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1762 struct mtd_oob_ops *ops)
1764 int page, realpage, chipnr, sndcmd = 1;
1765 struct nand_chip *chip = mtd->priv;
1766 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1767 int readlen = ops->ooblen;
1769 uint8_t *buf = ops->oobbuf;
1771 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1772 __func__, (unsigned long long)from, readlen);
1774 if (ops->mode == MTD_OOB_AUTO)
1775 len = chip->ecc.layout->oobavail;
1779 if (unlikely(ops->ooboffs >= len)) {
1780 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1781 "outside oob\n", __func__);
1785 /* Do not allow reads past end of device */
1786 if (unlikely(from >= mtd->size ||
1787 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1788 (from >> chip->page_shift)) * len)) {
1789 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1790 "of device\n", __func__);
1794 chipnr = (int)(from >> chip->chip_shift);
1795 chip->select_chip(mtd, chipnr);
1797 /* Shift to get page */
1798 realpage = (int)(from >> chip->page_shift);
1799 page = realpage & chip->pagemask;
1802 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1804 len = min(len, readlen);
1805 buf = nand_transfer_oob(chip, buf, ops, len);
1807 if (!(chip->options & NAND_NO_READRDY)) {
1809 * Apply delay or wait for ready/busy pin. Do this
1810 * before the AUTOINCR check, so no problems arise if a
1811 * chip which does auto increment is marked as
1812 * NOAUTOINCR by the board driver.
1814 if (!chip->dev_ready)
1815 udelay(chip->chip_delay);
1817 nand_wait_ready(mtd);
1824 /* Increment page address */
1827 page = realpage & chip->pagemask;
1828 /* Check, if we cross a chip boundary */
1831 chip->select_chip(mtd, -1);
1832 chip->select_chip(mtd, chipnr);
1835 /* Check, if the chip supports auto page increment
1836 * or if we have hit a block boundary.
1838 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1842 ops->oobretlen = ops->ooblen;
1847 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1848 * @mtd: MTD device structure
1849 * @from: offset to read from
1850 * @ops: oob operation description structure
1852 * NAND read data and/or out-of-band data
1854 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1855 struct mtd_oob_ops *ops)
1857 struct nand_chip *chip = mtd->priv;
1858 int ret = -ENOTSUPP;
1862 /* Do not allow reads past end of device */
1863 if (ops->datbuf && (from + ops->len) > mtd->size) {
1864 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1865 "beyond end of device\n", __func__);
1869 nand_get_device(chip, mtd, FL_READING);
1882 ret = nand_do_read_oob(mtd, from, ops);
1884 ret = nand_do_read_ops(mtd, from, ops);
1887 nand_release_device(mtd);
1893 * nand_write_page_raw - [Intern] raw page write function
1894 * @mtd: mtd info structure
1895 * @chip: nand chip info structure
1898 * Not for syndrome calculating ecc controllers, which use a special oob layout
1900 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1903 chip->write_buf(mtd, buf, mtd->writesize);
1904 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1908 * nand_write_page_raw_syndrome - [Intern] raw page write function
1909 * @mtd: mtd info structure
1910 * @chip: nand chip info structure
1913 * We need a special oob layout and handling even when ECC isn't checked.
1915 static void nand_write_page_raw_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1918 int eccsize = chip->ecc.size;
1919 int eccbytes = chip->ecc.bytes;
1920 uint8_t *oob = chip->oob_poi;
1923 for (steps = chip->ecc.steps; steps > 0; steps--) {
1924 chip->write_buf(mtd, buf, eccsize);
1927 if (chip->ecc.prepad) {
1928 chip->write_buf(mtd, oob, chip->ecc.prepad);
1929 oob += chip->ecc.prepad;
1932 chip->read_buf(mtd, oob, eccbytes);
1935 if (chip->ecc.postpad) {
1936 chip->write_buf(mtd, oob, chip->ecc.postpad);
1937 oob += chip->ecc.postpad;
1941 size = mtd->oobsize - (oob - chip->oob_poi);
1943 chip->write_buf(mtd, oob, size);
1946 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1947 * @mtd: mtd info structure
1948 * @chip: nand chip info structure
1951 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1954 int i, eccsize = chip->ecc.size;
1955 int eccbytes = chip->ecc.bytes;
1956 int eccsteps = chip->ecc.steps;
1957 uint8_t *ecc_calc = chip->buffers->ecccalc;
1958 const uint8_t *p = buf;
1959 uint32_t *eccpos = chip->ecc.layout->eccpos;
1961 /* Software ecc calculation */
1962 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1963 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1965 for (i = 0; i < chip->ecc.total; i++)
1966 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1968 chip->ecc.write_page_raw(mtd, chip, buf);
1972 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1973 * @mtd: mtd info structure
1974 * @chip: nand chip info structure
1977 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1980 int i, eccsize = chip->ecc.size;
1981 int eccbytes = chip->ecc.bytes;
1982 int eccsteps = chip->ecc.steps;
1983 uint8_t *ecc_calc = chip->buffers->ecccalc;
1984 const uint8_t *p = buf;
1985 uint32_t *eccpos = chip->ecc.layout->eccpos;
1987 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1988 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1989 chip->write_buf(mtd, p, eccsize);
1990 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1993 for (i = 0; i < chip->ecc.total; i++)
1994 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1996 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
2000 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
2001 * @mtd: mtd info structure
2002 * @chip: nand chip info structure
2005 * The hw generator calculates the error syndrome automatically. Therefor
2006 * we need a special oob layout and handling.
2008 static void nand_write_page_syndrome(struct mtd_info *mtd,
2009 struct nand_chip *chip, const uint8_t *buf)
2011 int i, eccsize = chip->ecc.size;
2012 int eccbytes = chip->ecc.bytes;
2013 int eccsteps = chip->ecc.steps;
2014 const uint8_t *p = buf;
2015 uint8_t *oob = chip->oob_poi;
2017 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2019 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2020 chip->write_buf(mtd, p, eccsize);
2022 if (chip->ecc.prepad) {
2023 chip->write_buf(mtd, oob, chip->ecc.prepad);
2024 oob += chip->ecc.prepad;
2027 chip->ecc.calculate(mtd, p, oob);
2028 chip->write_buf(mtd, oob, eccbytes);
2031 if (chip->ecc.postpad) {
2032 chip->write_buf(mtd, oob, chip->ecc.postpad);
2033 oob += chip->ecc.postpad;
2037 /* Calculate remaining oob bytes */
2038 i = mtd->oobsize - (oob - chip->oob_poi);
2040 chip->write_buf(mtd, oob, i);
2044 * nand_write_page - [REPLACEABLE] write one page
2045 * @mtd: MTD device structure
2046 * @chip: NAND chip descriptor
2047 * @buf: the data to write
2048 * @page: page number to write
2049 * @cached: cached programming
2050 * @raw: use _raw version of write_page
2052 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2053 const uint8_t *buf, int page, int cached, int raw)
2057 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2060 chip->ecc.write_page_raw(mtd, chip, buf);
2062 chip->ecc.write_page(mtd, chip, buf);
2065 * Cached progamming disabled for now, Not sure if its worth the
2066 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2070 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2072 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2073 status = chip->waitfunc(mtd, chip);
2075 * See if operation failed and additional status checks are
2078 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2079 status = chip->errstat(mtd, chip, FL_WRITING, status,
2082 if (status & NAND_STATUS_FAIL)
2085 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2086 status = chip->waitfunc(mtd, chip);
2089 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2090 /* Send command to read back the data */
2091 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2093 if (chip->verify_buf(mtd, buf, mtd->writesize))
2100 * nand_fill_oob - [Internal] Transfer client buffer to oob
2101 * @chip: nand chip structure
2102 * @oob: oob data buffer
2103 * @len: oob data write length
2104 * @ops: oob ops structure
2106 static uint8_t *nand_fill_oob(struct nand_chip *chip, uint8_t *oob, size_t len,
2107 struct mtd_oob_ops *ops)
2113 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2116 case MTD_OOB_AUTO: {
2117 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2118 uint32_t boffs = 0, woffs = ops->ooboffs;
2121 for(; free->length && len; free++, len -= bytes) {
2122 /* Write request not from offset 0 ? */
2123 if (unlikely(woffs)) {
2124 if (woffs >= free->length) {
2125 woffs -= free->length;
2128 boffs = free->offset + woffs;
2129 bytes = min_t(size_t, len,
2130 (free->length - woffs));
2133 bytes = min_t(size_t, len, free->length);
2134 boffs = free->offset;
2136 memcpy(chip->oob_poi + boffs, oob, bytes);
2147 #define NOTALIGNED(x) (x & (chip->subpagesize - 1)) != 0
2150 * nand_do_write_ops - [Internal] NAND write with ECC
2151 * @mtd: MTD device structure
2152 * @to: offset to write to
2153 * @ops: oob operations description structure
2155 * NAND write with ECC
2157 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2158 struct mtd_oob_ops *ops)
2160 int chipnr, realpage, page, blockmask, column;
2161 struct nand_chip *chip = mtd->priv;
2162 uint32_t writelen = ops->len;
2164 uint32_t oobwritelen = ops->ooblen;
2165 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2166 mtd->oobavail : mtd->oobsize;
2168 uint8_t *oob = ops->oobbuf;
2169 uint8_t *buf = ops->datbuf;
2176 /* reject writes, which are not page aligned */
2177 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2178 printk(KERN_NOTICE "%s: Attempt to write not "
2179 "page aligned data\n", __func__);
2183 column = to & (mtd->writesize - 1);
2184 subpage = column || (writelen & (mtd->writesize - 1));
2189 chipnr = (int)(to >> chip->chip_shift);
2190 chip->select_chip(mtd, chipnr);
2192 /* Check, if it is write protected */
2193 if (nand_check_wp(mtd))
2196 realpage = (int)(to >> chip->page_shift);
2197 page = realpage & chip->pagemask;
2198 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2200 /* Invalidate the page cache, when we write to the cached page */
2201 if (to <= (chip->pagebuf << chip->page_shift) &&
2202 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2205 /* If we're not given explicit OOB data, let it be 0xFF */
2207 memset(chip->oob_poi, 0xff, mtd->oobsize);
2209 /* Don't allow multipage oob writes with offset */
2210 if (ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2214 int bytes = mtd->writesize;
2215 int cached = writelen > bytes && page != blockmask;
2216 uint8_t *wbuf = buf;
2218 /* Partial page write ? */
2219 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2221 bytes = min_t(int, bytes - column, (int) writelen);
2223 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2224 memcpy(&chip->buffers->databuf[column], buf, bytes);
2225 wbuf = chip->buffers->databuf;
2228 if (unlikely(oob)) {
2229 size_t len = min(oobwritelen, oobmaxlen);
2230 oob = nand_fill_oob(chip, oob, len, ops);
2234 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2235 (ops->mode == MTD_OOB_RAW));
2247 page = realpage & chip->pagemask;
2248 /* Check, if we cross a chip boundary */
2251 chip->select_chip(mtd, -1);
2252 chip->select_chip(mtd, chipnr);
2256 ops->retlen = ops->len - writelen;
2258 ops->oobretlen = ops->ooblen;
2263 * panic_nand_write - [MTD Interface] NAND write with ECC
2264 * @mtd: MTD device structure
2265 * @to: offset to write to
2266 * @len: number of bytes to write
2267 * @retlen: pointer to variable to store the number of written bytes
2268 * @buf: the data to write
2270 * NAND write with ECC. Used when performing writes in interrupt context, this
2271 * may for example be called by mtdoops when writing an oops while in panic.
2273 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2274 size_t *retlen, const uint8_t *buf)
2276 struct nand_chip *chip = mtd->priv;
2279 /* Do not allow reads past end of device */
2280 if ((to + len) > mtd->size)
2285 /* Wait for the device to get ready. */
2286 panic_nand_wait(mtd, chip, 400);
2288 /* Grab the device. */
2289 panic_nand_get_device(chip, mtd, FL_WRITING);
2291 chip->ops.len = len;
2292 chip->ops.datbuf = (uint8_t *)buf;
2293 chip->ops.oobbuf = NULL;
2295 ret = nand_do_write_ops(mtd, to, &chip->ops);
2297 *retlen = chip->ops.retlen;
2302 * nand_write - [MTD Interface] NAND write with ECC
2303 * @mtd: MTD device structure
2304 * @to: offset to write to
2305 * @len: number of bytes to write
2306 * @retlen: pointer to variable to store the number of written bytes
2307 * @buf: the data to write
2309 * NAND write with ECC
2311 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2312 size_t *retlen, const uint8_t *buf)
2314 struct nand_chip *chip = mtd->priv;
2317 /* Do not allow reads past end of device */
2318 if ((to + len) > mtd->size)
2323 nand_get_device(chip, mtd, FL_WRITING);
2325 chip->ops.len = len;
2326 chip->ops.datbuf = (uint8_t *)buf;
2327 chip->ops.oobbuf = NULL;
2329 ret = nand_do_write_ops(mtd, to, &chip->ops);
2331 *retlen = chip->ops.retlen;
2333 nand_release_device(mtd);
2339 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2340 * @mtd: MTD device structure
2341 * @to: offset to write to
2342 * @ops: oob operation description structure
2344 * NAND write out-of-band
2346 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2347 struct mtd_oob_ops *ops)
2349 int chipnr, page, status, len;
2350 struct nand_chip *chip = mtd->priv;
2352 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2353 __func__, (unsigned int)to, (int)ops->ooblen);
2355 if (ops->mode == MTD_OOB_AUTO)
2356 len = chip->ecc.layout->oobavail;
2360 /* Do not allow write past end of page */
2361 if ((ops->ooboffs + ops->ooblen) > len) {
2362 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2363 "past end of page\n", __func__);
2367 if (unlikely(ops->ooboffs >= len)) {
2368 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2369 "write outside oob\n", __func__);
2373 /* Do not allow reads past end of device */
2374 if (unlikely(to >= mtd->size ||
2375 ops->ooboffs + ops->ooblen >
2376 ((mtd->size >> chip->page_shift) -
2377 (to >> chip->page_shift)) * len)) {
2378 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2379 "end of device\n", __func__);
2383 chipnr = (int)(to >> chip->chip_shift);
2384 chip->select_chip(mtd, chipnr);
2386 /* Shift to get page */
2387 page = (int)(to >> chip->page_shift);
2390 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2391 * of my DiskOnChip 2000 test units) will clear the whole data page too
2392 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2393 * it in the doc2000 driver in August 1999. dwmw2.
2395 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2397 /* Check, if it is write protected */
2398 if (nand_check_wp(mtd))
2401 /* Invalidate the page cache, if we write to the cached page */
2402 if (page == chip->pagebuf)
2405 memset(chip->oob_poi, 0xff, mtd->oobsize);
2406 nand_fill_oob(chip, ops->oobbuf, ops->ooblen, ops);
2407 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2408 memset(chip->oob_poi, 0xff, mtd->oobsize);
2413 ops->oobretlen = ops->ooblen;
2419 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2420 * @mtd: MTD device structure
2421 * @to: offset to write to
2422 * @ops: oob operation description structure
2424 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2425 struct mtd_oob_ops *ops)
2427 struct nand_chip *chip = mtd->priv;
2428 int ret = -ENOTSUPP;
2432 /* Do not allow writes past end of device */
2433 if (ops->datbuf && (to + ops->len) > mtd->size) {
2434 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2435 "end of device\n", __func__);
2439 nand_get_device(chip, mtd, FL_WRITING);
2452 ret = nand_do_write_oob(mtd, to, ops);
2454 ret = nand_do_write_ops(mtd, to, ops);
2457 nand_release_device(mtd);
2462 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2463 * @mtd: MTD device structure
2464 * @page: the page address of the block which will be erased
2466 * Standard erase command for NAND chips
2468 static void single_erase_cmd(struct mtd_info *mtd, int page)
2470 struct nand_chip *chip = mtd->priv;
2471 /* Send commands to erase a block */
2472 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2473 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2477 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2478 * @mtd: MTD device structure
2479 * @page: the page address of the block which will be erased
2481 * AND multi block erase command function
2482 * Erase 4 consecutive blocks
2484 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2486 struct nand_chip *chip = mtd->priv;
2487 /* Send commands to erase a block */
2488 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2489 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2490 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2491 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2492 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2496 * nand_erase - [MTD Interface] erase block(s)
2497 * @mtd: MTD device structure
2498 * @instr: erase instruction
2500 * Erase one ore more blocks
2502 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2504 return nand_erase_nand(mtd, instr, 0);
2507 #define BBT_PAGE_MASK 0xffffff3f
2509 * nand_erase_nand - [Internal] erase block(s)
2510 * @mtd: MTD device structure
2511 * @instr: erase instruction
2512 * @allowbbt: allow erasing the bbt area
2514 * Erase one ore more blocks
2516 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2519 int page, status, pages_per_block, ret, chipnr;
2520 struct nand_chip *chip = mtd->priv;
2521 loff_t rewrite_bbt[NAND_MAX_CHIPS]={0};
2522 unsigned int bbt_masked_page = 0xffffffff;
2525 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2526 __func__, (unsigned long long)instr->addr,
2527 (unsigned long long)instr->len);
2529 if (check_offs_len(mtd, instr->addr, instr->len))
2532 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2534 /* Grab the lock and see if the device is available */
2535 nand_get_device(chip, mtd, FL_ERASING);
2537 /* Shift to get first page */
2538 page = (int)(instr->addr >> chip->page_shift);
2539 chipnr = (int)(instr->addr >> chip->chip_shift);
2541 /* Calculate pages in each block */
2542 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2544 /* Select the NAND device */
2545 chip->select_chip(mtd, chipnr);
2547 /* Check, if it is write protected */
2548 if (nand_check_wp(mtd)) {
2549 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2551 instr->state = MTD_ERASE_FAILED;
2556 * If BBT requires refresh, set the BBT page mask to see if the BBT
2557 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2558 * can not be matched. This is also done when the bbt is actually
2559 * erased to avoid recusrsive updates
2561 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2562 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2564 /* Loop through the pages */
2567 instr->state = MTD_ERASING;
2571 * heck if we have a bad block, we do not erase bad blocks !
2573 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2574 chip->page_shift, 0, allowbbt)) {
2575 printk(KERN_WARNING "%s: attempt to erase a bad block "
2576 "at page 0x%08x\n", __func__, page);
2577 instr->state = MTD_ERASE_FAILED;
2582 * Invalidate the page cache, if we erase the block which
2583 * contains the current cached page
2585 if (page <= chip->pagebuf && chip->pagebuf <
2586 (page + pages_per_block))
2589 chip->erase_cmd(mtd, page & chip->pagemask);
2591 status = chip->waitfunc(mtd, chip);
2594 * See if operation failed and additional status checks are
2597 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2598 status = chip->errstat(mtd, chip, FL_ERASING,
2601 /* See if block erase succeeded */
2602 if (status & NAND_STATUS_FAIL) {
2603 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2604 "page 0x%08x\n", __func__, page);
2605 instr->state = MTD_ERASE_FAILED;
2607 ((loff_t)page << chip->page_shift);
2612 * If BBT requires refresh, set the BBT rewrite flag to the
2615 if (bbt_masked_page != 0xffffffff &&
2616 (page & BBT_PAGE_MASK) == bbt_masked_page)
2617 rewrite_bbt[chipnr] =
2618 ((loff_t)page << chip->page_shift);
2620 /* Increment page address and decrement length */
2621 len -= (1 << chip->phys_erase_shift);
2622 page += pages_per_block;
2624 /* Check, if we cross a chip boundary */
2625 if (len && !(page & chip->pagemask)) {
2627 chip->select_chip(mtd, -1);
2628 chip->select_chip(mtd, chipnr);
2631 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2632 * page mask to see if this BBT should be rewritten
2634 if (bbt_masked_page != 0xffffffff &&
2635 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2636 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2640 instr->state = MTD_ERASE_DONE;
2644 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2646 /* Deselect and wake up anyone waiting on the device */
2647 nand_release_device(mtd);
2649 /* Do call back function */
2651 mtd_erase_callback(instr);
2654 * If BBT requires refresh and erase was successful, rewrite any
2655 * selected bad block tables
2657 if (bbt_masked_page == 0xffffffff || ret)
2660 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2661 if (!rewrite_bbt[chipnr])
2663 /* update the BBT for chip */
2664 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2665 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2666 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2667 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2670 /* Return more or less happy */
2675 * nand_sync - [MTD Interface] sync
2676 * @mtd: MTD device structure
2678 * Sync is actually a wait for chip ready function
2680 static void nand_sync(struct mtd_info *mtd)
2682 struct nand_chip *chip = mtd->priv;
2684 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2686 /* Grab the lock and see if the device is available */
2687 nand_get_device(chip, mtd, FL_SYNCING);
2688 /* Release it and go back */
2689 nand_release_device(mtd);
2693 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2694 * @mtd: MTD device structure
2695 * @offs: offset relative to mtd start
2697 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2699 /* Check for invalid offset */
2700 if (offs > mtd->size)
2703 return nand_block_checkbad(mtd, offs, 1, 0);
2707 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2708 * @mtd: MTD device structure
2709 * @ofs: offset relative to mtd start
2711 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2713 struct nand_chip *chip = mtd->priv;
2716 if ((ret = nand_block_isbad(mtd, ofs))) {
2717 /* If it was bad already, return success and do nothing. */
2723 return chip->block_markbad(mtd, ofs);
2727 * nand_suspend - [MTD Interface] Suspend the NAND flash
2728 * @mtd: MTD device structure
2730 static int nand_suspend(struct mtd_info *mtd)
2732 struct nand_chip *chip = mtd->priv;
2734 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2738 * nand_resume - [MTD Interface] Resume the NAND flash
2739 * @mtd: MTD device structure
2741 static void nand_resume(struct mtd_info *mtd)
2743 struct nand_chip *chip = mtd->priv;
2745 if (chip->state == FL_PM_SUSPENDED)
2746 nand_release_device(mtd);
2748 printk(KERN_ERR "%s called for a chip which is not "
2749 "in suspended state\n", __func__);
2753 * Set default functions
2755 static void nand_set_defaults(struct nand_chip *chip, int busw)
2757 /* check for proper chip_delay setup, set 20us if not */
2758 if (!chip->chip_delay)
2759 chip->chip_delay = 20;
2761 /* check, if a user supplied command function given */
2762 if (chip->cmdfunc == NULL)
2763 chip->cmdfunc = nand_command;
2765 /* check, if a user supplied wait function given */
2766 if (chip->waitfunc == NULL)
2767 chip->waitfunc = nand_wait;
2769 if (!chip->select_chip)
2770 chip->select_chip = nand_select_chip;
2771 if (!chip->read_byte)
2772 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2773 if (!chip->read_word)
2774 chip->read_word = nand_read_word;
2775 if (!chip->block_bad)
2776 chip->block_bad = nand_block_bad;
2777 if (!chip->block_markbad)
2778 chip->block_markbad = nand_default_block_markbad;
2779 if (!chip->write_buf)
2780 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2781 if (!chip->read_buf)
2782 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2783 if (!chip->verify_buf)
2784 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2785 if (!chip->scan_bbt)
2786 chip->scan_bbt = nand_default_bbt;
2788 if (!chip->controller) {
2789 chip->controller = &chip->hwcontrol;
2790 spin_lock_init(&chip->controller->lock);
2791 init_waitqueue_head(&chip->controller->wq);
2797 * Get the flash and manufacturer id and lookup if the type is supported
2799 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2800 struct nand_chip *chip,
2801 int busw, int *maf_id,
2802 struct nand_flash_dev *type)
2804 int i, dev_id, maf_idx;
2807 /* Select the device */
2808 chip->select_chip(mtd, 0);
2811 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2814 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2816 /* Send the command for reading device ID */
2817 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2819 /* Read manufacturer and device IDs */
2820 *maf_id = chip->read_byte(mtd);
2821 dev_id = chip->read_byte(mtd);
2823 /* Try again to make sure, as some systems the bus-hold or other
2824 * interface concerns can cause random data which looks like a
2825 * possibly credible NAND flash to appear. If the two results do
2826 * not match, ignore the device completely.
2829 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2831 /* Read entire ID string */
2833 for (i = 0; i < 8; i++)
2834 id_data[i] = chip->read_byte(mtd);
2836 if (id_data[0] != *maf_id || id_data[1] != dev_id) {
2837 printk(KERN_INFO "%s: second ID read did not match "
2838 "%02x,%02x against %02x,%02x\n", __func__,
2839 *maf_id, dev_id, id_data[0], id_data[1]);
2840 return ERR_PTR(-ENODEV);
2844 type = nand_flash_ids;
2846 for (; type->name != NULL; type++)
2847 if (dev_id == type->id)
2851 return ERR_PTR(-ENODEV);
2854 mtd->name = type->name;
2856 chip->chipsize = (uint64_t)type->chipsize << 20;
2858 /* Newer devices have all the information in additional id bytes */
2859 if (!type->pagesize) {
2861 /* The 3rd id byte holds MLC / multichip data */
2862 chip->cellinfo = id_data[2];
2863 /* The 4th id byte is the important one */
2867 * Field definitions are in the following datasheets:
2868 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2869 * New style (6 byte ID): Samsung K9GAG08U0D (p.40)
2871 * Check for wraparound + Samsung ID + nonzero 6th byte
2872 * to decide what to do.
2874 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2875 id_data[0] == NAND_MFR_SAMSUNG &&
2876 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2877 id_data[5] != 0x00) {
2879 mtd->writesize = 2048 << (extid & 0x03);
2882 mtd->oobsize = (extid & 0x03) == 0x01 ? 128 : 218;
2884 /* Calc blocksize */
2885 mtd->erasesize = (128 * 1024) <<
2886 (((extid >> 1) & 0x04) | (extid & 0x03));
2890 mtd->writesize = 1024 << (extid & 0x03);
2893 mtd->oobsize = (8 << (extid & 0x01)) *
2894 (mtd->writesize >> 9);
2896 /* Calc blocksize. Blocksize is multiples of 64KiB */
2897 mtd->erasesize = (64 * 1024) << (extid & 0x03);
2899 /* Get buswidth information */
2900 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
2904 * Old devices have chip data hardcoded in the device id table
2906 mtd->erasesize = type->erasesize;
2907 mtd->writesize = type->pagesize;
2908 mtd->oobsize = mtd->writesize / 32;
2909 busw = type->options & NAND_BUSWIDTH_16;
2912 /* Try to identify manufacturer */
2913 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
2914 if (nand_manuf_ids[maf_idx].id == *maf_id)
2918 chip->options |= busw;
2921 * Check, if buswidth is correct. Hardware drivers should set
2924 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
2925 printk(KERN_INFO "NAND device: Manufacturer ID:"
2926 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
2927 dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
2928 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
2929 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
2931 return ERR_PTR(-EINVAL);
2934 /* Calculate the address shift from the page size */
2935 chip->page_shift = ffs(mtd->writesize) - 1;
2936 /* Convert chipsize to number of pages per chip -1. */
2937 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
2939 chip->bbt_erase_shift = chip->phys_erase_shift =
2940 ffs(mtd->erasesize) - 1;
2941 if (chip->chipsize & 0xffffffff)
2942 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
2944 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32)) + 32 - 1;
2946 /* Set the bad block position */
2947 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
2948 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
2950 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
2952 /* Get chip options, preserve non chip based options */
2953 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2954 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
2957 * Set chip as a default. Board drivers can override it, if necessary
2959 chip->options |= NAND_NO_AUTOINCR;
2961 /* Check if chip is a not a samsung device. Do not clear the
2962 * options for chips which are not having an extended id.
2964 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
2965 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
2968 * Bad block marker is stored in the last page of each block
2969 * on Samsung and Hynix MLC devices; stored in first two pages
2970 * of each block on Micron devices with 2KiB pages and on
2971 * SLC Samsung, Hynix, and AMD/Spansion. All others scan only
2974 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2975 (*maf_id == NAND_MFR_SAMSUNG ||
2976 *maf_id == NAND_MFR_HYNIX))
2977 chip->options |= NAND_BBT_SCANLASTPAGE;
2978 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2979 (*maf_id == NAND_MFR_SAMSUNG ||
2980 *maf_id == NAND_MFR_HYNIX ||
2981 *maf_id == NAND_MFR_AMD)) ||
2982 (mtd->writesize == 2048 &&
2983 *maf_id == NAND_MFR_MICRON))
2984 chip->options |= NAND_BBT_SCAN2NDPAGE;
2987 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
2989 if (!(busw & NAND_BUSWIDTH_16) &&
2990 *maf_id == NAND_MFR_STMICRO &&
2991 mtd->writesize == 2048) {
2992 chip->options |= NAND_BBT_SCANBYTE1AND6;
2993 chip->badblockpos = 0;
2996 /* Check for AND chips with 4 page planes */
2997 if (chip->options & NAND_4PAGE_ARRAY)
2998 chip->erase_cmd = multi_erase_cmd;
3000 chip->erase_cmd = single_erase_cmd;
3002 /* Do not replace user supplied command function ! */
3003 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3004 chip->cmdfunc = nand_command_lp;
3006 printk(KERN_INFO "NAND device: Manufacturer ID:"
3007 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id,
3008 nand_manuf_ids[maf_idx].name, type->name);
3014 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3015 * @mtd: MTD device structure
3016 * @maxchips: Number of chips to scan for
3017 * @table: Alternative NAND ID table
3019 * This is the first phase of the normal nand_scan() function. It
3020 * reads the flash ID and sets up MTD fields accordingly.
3022 * The mtd->owner field must be set to the module of the caller.
3024 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3025 struct nand_flash_dev *table)
3027 int i, busw, nand_maf_id;
3028 struct nand_chip *chip = mtd->priv;
3029 struct nand_flash_dev *type;
3031 /* Get buswidth to select the correct functions */
3032 busw = chip->options & NAND_BUSWIDTH_16;
3033 /* Set the default functions */
3034 nand_set_defaults(chip, busw);
3036 /* Read the flash type */
3037 type = nand_get_flash_type(mtd, chip, busw, &nand_maf_id, table);
3040 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3041 printk(KERN_WARNING "No NAND device found.\n");
3042 chip->select_chip(mtd, -1);
3043 return PTR_ERR(type);
3046 /* Check for a chip array */
3047 for (i = 1; i < maxchips; i++) {
3048 chip->select_chip(mtd, i);
3049 /* See comment in nand_get_flash_type for reset */
3050 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3051 /* Send the command for reading device ID */
3052 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3053 /* Read manufacturer and device IDs */
3054 if (nand_maf_id != chip->read_byte(mtd) ||
3055 type->id != chip->read_byte(mtd))
3059 printk(KERN_INFO "%d NAND chips detected\n", i);
3061 /* Store the number of chips and calc total size for mtd */
3063 mtd->size = i * chip->chipsize;
3070 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3071 * @mtd: MTD device structure
3073 * This is the second phase of the normal nand_scan() function. It
3074 * fills out all the uninitialized function pointers with the defaults
3075 * and scans for a bad block table if appropriate.
3077 int nand_scan_tail(struct mtd_info *mtd)
3080 struct nand_chip *chip = mtd->priv;
3082 if (!(chip->options & NAND_OWN_BUFFERS))
3083 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3087 /* Set the internal oob buffer location, just after the page data */
3088 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3091 * If no default placement scheme is given, select an appropriate one
3093 if (!chip->ecc.layout) {
3094 switch (mtd->oobsize) {
3096 chip->ecc.layout = &nand_oob_8;
3099 chip->ecc.layout = &nand_oob_16;
3102 chip->ecc.layout = &nand_oob_64;
3105 chip->ecc.layout = &nand_oob_128;
3108 printk(KERN_WARNING "No oob scheme defined for "
3109 "oobsize %d\n", mtd->oobsize);
3114 if (!chip->write_page)
3115 chip->write_page = nand_write_page;
3118 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3119 * selected and we have 256 byte pagesize fallback to software ECC
3122 switch (chip->ecc.mode) {
3123 case NAND_ECC_HW_OOB_FIRST:
3124 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3125 if (!chip->ecc.calculate || !chip->ecc.correct ||
3127 printk(KERN_WARNING "No ECC functions supplied; "
3128 "Hardware ECC not possible\n");
3131 if (!chip->ecc.read_page)
3132 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3135 /* Use standard hwecc read page function ? */
3136 if (!chip->ecc.read_page)
3137 chip->ecc.read_page = nand_read_page_hwecc;
3138 if (!chip->ecc.write_page)
3139 chip->ecc.write_page = nand_write_page_hwecc;
3140 if (!chip->ecc.read_page_raw)
3141 chip->ecc.read_page_raw = nand_read_page_raw;
3142 if (!chip->ecc.write_page_raw)
3143 chip->ecc.write_page_raw = nand_write_page_raw;
3144 if (!chip->ecc.read_oob)
3145 chip->ecc.read_oob = nand_read_oob_std;
3146 if (!chip->ecc.write_oob)
3147 chip->ecc.write_oob = nand_write_oob_std;
3149 case NAND_ECC_HW_SYNDROME:
3150 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3151 !chip->ecc.hwctl) &&
3152 (!chip->ecc.read_page ||
3153 chip->ecc.read_page == nand_read_page_hwecc ||
3154 !chip->ecc.write_page ||
3155 chip->ecc.write_page == nand_write_page_hwecc)) {
3156 printk(KERN_WARNING "No ECC functions supplied; "
3157 "Hardware ECC not possible\n");
3160 /* Use standard syndrome read/write page function ? */
3161 if (!chip->ecc.read_page)
3162 chip->ecc.read_page = nand_read_page_syndrome;
3163 if (!chip->ecc.write_page)
3164 chip->ecc.write_page = nand_write_page_syndrome;
3165 if (!chip->ecc.read_page_raw)
3166 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3167 if (!chip->ecc.write_page_raw)
3168 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3169 if (!chip->ecc.read_oob)
3170 chip->ecc.read_oob = nand_read_oob_syndrome;
3171 if (!chip->ecc.write_oob)
3172 chip->ecc.write_oob = nand_write_oob_syndrome;
3174 if (mtd->writesize >= chip->ecc.size)
3176 printk(KERN_WARNING "%d byte HW ECC not possible on "
3177 "%d byte page size, fallback to SW ECC\n",
3178 chip->ecc.size, mtd->writesize);
3179 chip->ecc.mode = NAND_ECC_SOFT;
3182 chip->ecc.calculate = nand_calculate_ecc;
3183 chip->ecc.correct = nand_correct_data;
3184 chip->ecc.read_page = nand_read_page_swecc;
3185 chip->ecc.read_subpage = nand_read_subpage;
3186 chip->ecc.write_page = nand_write_page_swecc;
3187 chip->ecc.read_page_raw = nand_read_page_raw;
3188 chip->ecc.write_page_raw = nand_write_page_raw;
3189 chip->ecc.read_oob = nand_read_oob_std;
3190 chip->ecc.write_oob = nand_write_oob_std;
3191 if (!chip->ecc.size)
3192 chip->ecc.size = 256;
3193 chip->ecc.bytes = 3;
3197 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3198 "This is not recommended !!\n");
3199 chip->ecc.read_page = nand_read_page_raw;
3200 chip->ecc.write_page = nand_write_page_raw;
3201 chip->ecc.read_oob = nand_read_oob_std;
3202 chip->ecc.read_page_raw = nand_read_page_raw;
3203 chip->ecc.write_page_raw = nand_write_page_raw;
3204 chip->ecc.write_oob = nand_write_oob_std;
3205 chip->ecc.size = mtd->writesize;
3206 chip->ecc.bytes = 0;
3210 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3216 * The number of bytes available for a client to place data into
3217 * the out of band area
3219 chip->ecc.layout->oobavail = 0;
3220 for (i = 0; chip->ecc.layout->oobfree[i].length
3221 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3222 chip->ecc.layout->oobavail +=
3223 chip->ecc.layout->oobfree[i].length;
3224 mtd->oobavail = chip->ecc.layout->oobavail;
3227 * Set the number of read / write steps for one page depending on ECC
3230 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3231 if(chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3232 printk(KERN_WARNING "Invalid ecc parameters\n");
3235 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3238 * Allow subpage writes up to ecc.steps. Not possible for MLC
3241 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3242 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3243 switch(chip->ecc.steps) {
3245 mtd->subpage_sft = 1;
3250 mtd->subpage_sft = 2;
3254 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3256 /* Initialize state */
3257 chip->state = FL_READY;
3259 /* De-select the device */
3260 chip->select_chip(mtd, -1);
3262 /* Invalidate the pagebuffer reference */
3265 /* Fill in remaining MTD driver data */
3266 mtd->type = MTD_NANDFLASH;
3267 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3269 mtd->erase = nand_erase;
3271 mtd->unpoint = NULL;
3272 mtd->read = nand_read;
3273 mtd->write = nand_write;
3274 mtd->panic_write = panic_nand_write;
3275 mtd->read_oob = nand_read_oob;
3276 mtd->write_oob = nand_write_oob;
3277 mtd->sync = nand_sync;
3280 mtd->suspend = nand_suspend;
3281 mtd->resume = nand_resume;
3282 mtd->block_isbad = nand_block_isbad;
3283 mtd->block_markbad = nand_block_markbad;
3285 /* propagate ecc.layout to mtd_info */
3286 mtd->ecclayout = chip->ecc.layout;
3288 /* Check, if we should skip the bad block table scan */
3289 if (chip->options & NAND_SKIP_BBTSCAN)
3292 /* Build bad block table */
3293 return chip->scan_bbt(mtd);
3296 /* is_module_text_address() isn't exported, and it's mostly a pointless
3297 test if this is a module _anyway_ -- they'd have to try _really_ hard
3298 to call us from in-kernel code if the core NAND support is modular. */
3300 #define caller_is_module() (1)
3302 #define caller_is_module() \
3303 is_module_text_address((unsigned long)__builtin_return_address(0))
3307 * nand_scan - [NAND Interface] Scan for the NAND device
3308 * @mtd: MTD device structure
3309 * @maxchips: Number of chips to scan for
3311 * This fills out all the uninitialized function pointers
3312 * with the defaults.
3313 * The flash ID is read and the mtd/chip structures are
3314 * filled with the appropriate values.
3315 * The mtd->owner field must be set to the module of the caller
3318 int nand_scan(struct mtd_info *mtd, int maxchips)
3322 /* Many callers got this wrong, so check for it for a while... */
3323 if (!mtd->owner && caller_is_module()) {
3324 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3329 ret = nand_scan_ident(mtd, maxchips, NULL);
3331 ret = nand_scan_tail(mtd);
3336 * nand_release - [NAND Interface] Free resources held by the NAND device
3337 * @mtd: MTD device structure
3339 void nand_release(struct mtd_info *mtd)
3341 struct nand_chip *chip = mtd->priv;
3343 #ifdef CONFIG_MTD_PARTITIONS
3344 /* Deregister partitions */
3345 del_mtd_partitions(mtd);
3347 /* Deregister the device */
3348 del_mtd_device(mtd);
3350 /* Free bad block table memory */
3352 if (!(chip->options & NAND_OWN_BUFFERS))
3353 kfree(chip->buffers);
3355 /* Free bad block descriptor memory */
3356 if (chip->badblock_pattern && chip->badblock_pattern->options
3357 & NAND_BBT_DYNAMICSTRUCT)
3358 kfree(chip->badblock_pattern);
3361 EXPORT_SYMBOL_GPL(nand_lock);
3362 EXPORT_SYMBOL_GPL(nand_unlock);
3363 EXPORT_SYMBOL_GPL(nand_scan);
3364 EXPORT_SYMBOL_GPL(nand_scan_ident);
3365 EXPORT_SYMBOL_GPL(nand_scan_tail);
3366 EXPORT_SYMBOL_GPL(nand_release);
3368 static int __init nand_base_init(void)
3370 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3374 static void __exit nand_base_exit(void)
3376 led_trigger_unregister_simple(nand_led_trigger);
3379 module_init(nand_base_init);
3380 module_exit(nand_base_exit);
3382 MODULE_LICENSE("GPL");
3383 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>, Thomas Gleixner <tglx@linutronix.de>");
3384 MODULE_DESCRIPTION("Generic NAND flash driver code");