drivers/mtd/nand/nand_base.c

   1 /*
   2  *  drivers/mtd/nand.c
   3  *
   4  *  Overview:
   5  *   This is the generic MTD driver for NAND flash devices. It should be
   6  *   capable of working with almost all NAND chips currently available.
   7  *   Basic support for AG-AND chips is provided.
   8  *
   9  *      Additional technical information is available on
  10  *      http://www.linux-mtd.infradead.org/doc/nand.html
  11  *
  12  *  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  13  *                2002-2006 Thomas Gleixner (tglx@linutronix.de)
  14  *
  15  *  Credits:
  16  *      David Woodhouse for adding multichip support
  17  *
  18  *      Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  19  *      rework for 2K page size chips
  20  *
  21  *  TODO:
  22  *      Enable cached programming for 2k page size chips
  23  *      Check, if mtd->ecctype should be set to MTD_ECC_HW
  24  *      if we have HW ECC support.
  25  *      The AG-AND chips have nice features for speed improvement,
  26  *      which are not supported yet. Read / program 4 pages in one go.
  27  *      BBT table is not serialized, has to be fixed
  28  *
  29  * This program is free software; you can redistribute it and/or modify
  30  * it under the terms of the GNU General Public License version 2 as
  31  * published by the Free Software Foundation.
  32  *
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/delay.h>
  37 #include <linux/errno.h>
  38 #include <linux/err.h>
  39 #include <linux/sched.h>
  40 #include <linux/slab.h>
  41 #include <linux/types.h>
  42 #include <linux/mtd/mtd.h>
  43 #include <linux/mtd/nand.h>
  44 #include <linux/mtd/nand_ecc.h>
  45 #include <linux/mtd/nand_bch.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/bitops.h>
  48 #include <linux/leds.h>
  49 #include <linux/io.h>
  50 #include <linux/mtd/partitions.h>
  51
  52 /* Define default oob placement schemes for large and small page devices */
  53 static struct nand_ecclayout nand_oob_8 = {
  54         .eccbytes = 3,
  55         .eccpos = {0, 1, 2},
  56         .oobfree = {
  57                 {.offset = 3,
  58                  .length = 2},
  59                 {.offset = 6,
  60                  .length = 2} }
  61 };
  62
  63 static struct nand_ecclayout nand_oob_16 = {
  64         .eccbytes = 6,
  65         .eccpos = {0, 1, 2, 3, 6, 7},
  66         .oobfree = {
  67                 {.offset = 8,
  68                  . length = 8} }
  69 };
  70
  71 static struct nand_ecclayout nand_oob_64 = {
  72         .eccbytes = 24,
  73         .eccpos = {
  74                    40, 41, 42, 43, 44, 45, 46, 47,
  75                    48, 49, 50, 51, 52, 53, 54, 55,
  76                    56, 57, 58, 59, 60, 61, 62, 63},
  77         .oobfree = {
  78                 {.offset = 2,
  79                  .length = 38} }
  80 };
  81
  82 static struct nand_ecclayout nand_oob_128 = {
  83         .eccbytes = 48,
  84         .eccpos = {
  85                    80, 81, 82, 83, 84, 85, 86, 87,
  86                    88, 89, 90, 91, 92, 93, 94, 95,
  87                    96, 97, 98, 99, 100, 101, 102, 103,
  88                    104, 105, 106, 107, 108, 109, 110, 111,
  89                    112, 113, 114, 115, 116, 117, 118, 119,
  90                    120, 121, 122, 123, 124, 125, 126, 127},
  91         .oobfree = {
  92                 {.offset = 2,
  93                  .length = 78} }
  94 };
  95
  96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
  97                            int new_state);
  98
  99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
 100                              struct mtd_oob_ops *ops);
 101
 102 /*
 103  * For devices which display every fart in the system on a separate LED. Is
 104  * compiled away when LED support is disabled.
 105  */
 106 DEFINE_LED_TRIGGER(nand_led_trigger);
 107
 108 static int check_offs_len(struct mtd_info *mtd,
 109                                         loff_t ofs, uint64_t len)
 110 {
 111         struct nand_chip *chip = mtd->priv;
 112         int ret = 0;
 113
 114         /* Start address must align on block boundary */
 115         if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
 116                 pr_debug("%s: unaligned address\n", __func__);
 117                 ret = -EINVAL;
 118         }
 119
 120         /* Length must align on block boundary */
 121         if (len & ((1 << chip->phys_erase_shift) - 1)) {
 122                 pr_debug("%s: length not block aligned\n", __func__);
 123                 ret = -EINVAL;
 124         }
 125
 126         return ret;
 127 }
 128
 129 /**
 130  * nand_release_device - [GENERIC] release chip
 131  * @mtd: MTD device structure
 132  *
 133  * Deselect, release chip lock and wake up anyone waiting on the device.
 134  */
 135 static void nand_release_device(struct mtd_info *mtd)
 136 {
 137         struct nand_chip *chip = mtd->priv;
 138
 139         /* De-select the NAND device */
 140         chip->select_chip(mtd, -1);
 141
 142         /* Release the controller and the chip */
 143         spin_lock(&chip->controller->lock);
 144         chip->controller->active = NULL;
 145         chip->state = FL_READY;
 146         wake_up(&chip->controller->wq);
 147         spin_unlock(&chip->controller->lock);
 148 }
 149
 150 /**
 151  * nand_read_byte - [DEFAULT] read one byte from the chip
 152  * @mtd: MTD device structure
 153  *
 154  * Default read function for 8bit buswidth
 155  */
 156 static uint8_t nand_read_byte(struct mtd_info *mtd)
 157 {
 158         struct nand_chip *chip = mtd->priv;
 159         return readb(chip->IO_ADDR_R);
 160 }
 161
 162 /**
 163  * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
 164  * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
 165  * @mtd: MTD device structure
 166  *
 167  * Default read function for 16bit buswidth with endianness conversion.
 168  *
 169  */
 170 static uint8_t nand_read_byte16(struct mtd_info *mtd)
 171 {
 172         struct nand_chip *chip = mtd->priv;
 173         return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
 174 }
 175
 176 /**
 177  * nand_read_word - [DEFAULT] read one word from the chip
 178  * @mtd: MTD device structure
 179  *
 180  * Default read function for 16bit buswidth without endianness conversion.
 181  */
 182 static u16 nand_read_word(struct mtd_info *mtd)
 183 {
 184         struct nand_chip *chip = mtd->priv;
 185         return readw(chip->IO_ADDR_R);
 186 }
 187
 188 /**
 189  * nand_select_chip - [DEFAULT] control CE line
 190  * @mtd: MTD device structure
 191  * @chipnr: chipnumber to select, -1 for deselect
 192  *
 193  * Default select function for 1 chip devices.
 194  */
 195 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
 196 {
 197         struct nand_chip *chip = mtd->priv;
 198
 199         switch (chipnr) {
 200         case -1:
 201                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 202                 break;
 203         case 0:
 204                 break;
 205
 206         default:
 207                 BUG();
 208         }
 209 }
 210
 211 /**
 212  * nand_write_buf - [DEFAULT] write buffer to chip
 213  * @mtd: MTD device structure
 214  * @buf: data buffer
 215  * @len: number of bytes to write
 216  *
 217  * Default write function for 8bit buswidth.
 218  */
 219 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 220 {
 221         int i;
 222         struct nand_chip *chip = mtd->priv;
 223
 224         for (i = 0; i < len; i++)
 225                 writeb(buf[i], chip->IO_ADDR_W);
 226 }
 227
 228 /**
 229  * nand_read_buf - [DEFAULT] read chip data into buffer
 230  * @mtd: MTD device structure
 231  * @buf: buffer to store date
 232  * @len: number of bytes to read
 233  *
 234  * Default read function for 8bit buswidth.
 235  */
 236 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 237 {
 238         int i;
 239         struct nand_chip *chip = mtd->priv;
 240
 241         for (i = 0; i < len; i++)
 242                 buf[i] = readb(chip->IO_ADDR_R);
 243 }
 244
 245 /**
 246  * nand_write_buf16 - [DEFAULT] write buffer to chip
 247  * @mtd: MTD device structure
 248  * @buf: data buffer
 249  * @len: number of bytes to write
 250  *
 251  * Default write function for 16bit buswidth.
 252  */
 253 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
 254 {
 255         int i;
 256         struct nand_chip *chip = mtd->priv;
 257         u16 *p = (u16 *) buf;
 258         len >>= 1;
 259
 260         for (i = 0; i < len; i++)
 261                 writew(p[i], chip->IO_ADDR_W);
 262
 263 }
 264
 265 /**
 266  * nand_read_buf16 - [DEFAULT] read chip data into buffer
 267  * @mtd: MTD device structure
 268  * @buf: buffer to store date
 269  * @len: number of bytes to read
 270  *
 271  * Default read function for 16bit buswidth.
 272  */
 273 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 274 {
 275         int i;
 276         struct nand_chip *chip = mtd->priv;
 277         u16 *p = (u16 *) buf;
 278         len >>= 1;
 279
 280         for (i = 0; i < len; i++)
 281                 p[i] = readw(chip->IO_ADDR_R);
 282 }
 283
 284 /**
 285  * nand_block_bad - [DEFAULT] Read bad block marker from the chip
 286  * @mtd: MTD device structure
 287  * @ofs: offset from device start
 288  * @getchip: 0, if the chip is already selected
 289  *
 290  * Check, if the block is bad.
 291  */
 292 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
 293 {
 294         int page, chipnr, res = 0, i = 0;
 295         struct nand_chip *chip = mtd->priv;
 296         u16 bad;
 297
 298         if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 299                 ofs += mtd->erasesize - mtd->writesize;
 300
 301         page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 302
 303         if (getchip) {
 304                 chipnr = (int)(ofs >> chip->chip_shift);
 305
 306                 nand_get_device(chip, mtd, FL_READING);
 307
 308                 /* Select the NAND device */
 309                 chip->select_chip(mtd, chipnr);
 310         }
 311
 312         do {
 313                 if (chip->options & NAND_BUSWIDTH_16) {
 314                         chip->cmdfunc(mtd, NAND_CMD_READOOB,
 315                                         chip->badblockpos & 0xFE, page);
 316                         bad = cpu_to_le16(chip->read_word(mtd));
 317                         if (chip->badblockpos & 0x1)
 318                                 bad >>= 8;
 319                         else
 320                                 bad &= 0xFF;
 321                 } else {
 322                         chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
 323                                         page);
 324                         bad = chip->read_byte(mtd);
 325                 }
 326
 327                 if (likely(chip->badblockbits == 8))
 328                         res = bad != 0xFF;
 329                 else
 330                         res = hweight8(bad) < chip->badblockbits;
 331                 ofs += mtd->writesize;
 332                 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
 333                 i++;
 334         } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
 335
 336         if (getchip)
 337                 nand_release_device(mtd);
 338
 339         return res;
 340 }
 341
 342 /**
 343  * nand_default_block_markbad - [DEFAULT] mark a block bad
 344  * @mtd: MTD device structure
 345  * @ofs: offset from device start
 346  *
 347  * This is the default implementation, which can be overridden by a hardware
 348  * specific driver. We try operations in the following order, according to our
 349  * bbt_options (NAND_BBT_NO_OOB_BBM and NAND_BBT_USE_FLASH):
 350  *  (1) erase the affected block, to allow OOB marker to be written cleanly
 351  *  (2) update in-memory BBT
 352  *  (3) write bad block marker to OOB area of affected block
 353  *  (4) update flash-based BBT
 354  * Note that we retain the first error encountered in (3) or (4), finish the
 355  * procedures, and dump the error in the end.
 356 */
 357 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
 358 {
 359         struct nand_chip *chip = mtd->priv;
 360         uint8_t buf[2] = { 0, 0 };
 361         int block, res, ret = 0, i = 0;
 362         int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
 363
 364         if (write_oob) {
 365                 struct erase_info einfo;
 366
 367                 /* Attempt erase before marking OOB */
 368                 memset(&einfo, 0, sizeof(einfo));
 369                 einfo.mtd = mtd;
 370                 einfo.addr = ofs;
 371                 einfo.len = 1 << chip->phys_erase_shift;
 372                 nand_erase_nand(mtd, &einfo, 0);
 373         }
 374
 375         /* Get block number */
 376         block = (int)(ofs >> chip->bbt_erase_shift);
 377         /* Mark block bad in memory-based BBT */
 378         if (chip->bbt)
 379                 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
 380
 381         /* Write bad block marker to OOB */
 382         if (write_oob) {
 383                 struct mtd_oob_ops ops;
 384                 loff_t wr_ofs = ofs;
 385
 386                 nand_get_device(chip, mtd, FL_WRITING);
 387
 388                 ops.datbuf = NULL;
 389                 ops.oobbuf = buf;
 390                 ops.ooboffs = chip->badblockpos;
 391                 if (chip->options & NAND_BUSWIDTH_16) {
 392                         ops.ooboffs &= ~0x01;
 393                         ops.len = ops.ooblen = 2;
 394                 } else {
 395                         ops.len = ops.ooblen = 1;
 396                 }
 397                 ops.mode = MTD_OPS_PLACE_OOB;
 398
 399                 /* Write to first/last page(s) if necessary */
 400                 if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
 401                         wr_ofs += mtd->erasesize - mtd->writesize;
 402                 do {
 403                         res = nand_do_write_oob(mtd, wr_ofs, &ops);
 404                         if (!ret)
 405                                 ret = res;
 406
 407                         i++;
 408                         wr_ofs += mtd->writesize;
 409                 } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
 410
 411                 nand_release_device(mtd);
 412         }
 413
 414         /* Update flash-based bad block table */
 415         if (chip->bbt_options & NAND_BBT_USE_FLASH) {
 416                 res = nand_update_bbt(mtd, ofs);
 417                 if (!ret)
 418                         ret = res;
 419         }
 420
 421         if (!ret)
 422                 mtd->ecc_stats.badblocks++;
 423
 424         return ret;
 425 }
 426
 427 /**
 428  * nand_check_wp - [GENERIC] check if the chip is write protected
 429  * @mtd: MTD device structure
 430  *
 431  * Check, if the device is write protected. The function expects, that the
 432  * device is already selected.
 433  */
 434 static int nand_check_wp(struct mtd_info *mtd)
 435 {
 436         struct nand_chip *chip = mtd->priv;
 437
 438         /* Broken xD cards report WP despite being writable */
 439         if (chip->options & NAND_BROKEN_XD)
 440                 return 0;
 441
 442         /* Check the WP bit */
 443         chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 444         return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
 445 }
 446
 447 /**
 448  * nand_block_checkbad - [GENERIC] Check if a block is marked bad
 449  * @mtd: MTD device structure
 450  * @ofs: offset from device start
 451  * @getchip: 0, if the chip is already selected
 452  * @allowbbt: 1, if its allowed to access the bbt area
 453  *
 454  * Check, if the block is bad. Either by reading the bad block table or
 455  * calling of the scan function.
 456  */
 457 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
 458                                int allowbbt)
 459 {
 460         struct nand_chip *chip = mtd->priv;
 461
 462         if (!chip->bbt)
 463                 return chip->block_bad(mtd, ofs, getchip);
 464
 465         /* Return info from the table */
 466         return nand_isbad_bbt(mtd, ofs, allowbbt);
 467 }
 468
 469 /**
 470  * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
 471  * @mtd: MTD device structure
 472  * @timeo: Timeout
 473  *
 474  * Helper function for nand_wait_ready used when needing to wait in interrupt
 475  * context.
 476  */
 477 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
 478 {
 479         struct nand_chip *chip = mtd->priv;
 480         int i;
 481
 482         /* Wait for the device to get ready */
 483         for (i = 0; i < timeo; i++) {
 484                 if (chip->dev_ready(mtd))
 485                         break;
 486                 touch_softlockup_watchdog();
 487                 mdelay(1);
 488         }
 489 }
 490
 491 /* Wait for the ready pin, after a command. The timeout is caught later. */
 492 void nand_wait_ready(struct mtd_info *mtd)
 493 {
 494         struct nand_chip *chip = mtd->priv;
 495         unsigned long timeo = jiffies + 2;
 496
 497         /* 400ms timeout */
 498         if (in_interrupt() || oops_in_progress)
 499                 return panic_nand_wait_ready(mtd, 400);
 500
 501         led_trigger_event(nand_led_trigger, LED_FULL);
 502         /* Wait until command is processed or timeout occurs */
 503         do {
 504                 if (chip->dev_ready(mtd))
 505                         break;
 506                 touch_softlockup_watchdog();
 507         } while (time_before(jiffies, timeo));
 508         led_trigger_event(nand_led_trigger, LED_OFF);
 509 }
 510 EXPORT_SYMBOL_GPL(nand_wait_ready);
 511
 512 /**
 513  * nand_command - [DEFAULT] Send command to NAND device
 514  * @mtd: MTD device structure
 515  * @command: the command to be sent
 516  * @column: the column address for this command, -1 if none
 517  * @page_addr: the page address for this command, -1 if none
 518  *
 519  * Send command to NAND device. This function is used for small page devices
 520  * (256/512 Bytes per page).
 521  */
 522 static void nand_command(struct mtd_info *mtd, unsigned int command,
 523                          int column, int page_addr)
 524 {
 525         register struct nand_chip *chip = mtd->priv;
 526         int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
 527
 528         /* Write out the command to the device */
 529         if (command == NAND_CMD_SEQIN) {
 530                 int readcmd;
 531
 532                 if (column >= mtd->writesize) {
 533                         /* OOB area */
 534                         column -= mtd->writesize;
 535                         readcmd = NAND_CMD_READOOB;
 536                 } else if (column < 256) {
 537                         /* First 256 bytes --> READ0 */
 538                         readcmd = NAND_CMD_READ0;
 539                 } else {
 540                         column -= 256;
 541                         readcmd = NAND_CMD_READ1;
 542                 }
 543                 chip->cmd_ctrl(mtd, readcmd, ctrl);
 544                 ctrl &= ~NAND_CTRL_CHANGE;
 545         }
 546         chip->cmd_ctrl(mtd, command, ctrl);
 547
 548         /* Address cycle, when necessary */
 549         ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
 550         /* Serially input address */
 551         if (column != -1) {
 552                 /* Adjust columns for 16 bit buswidth */
 553                 if (chip->options & NAND_BUSWIDTH_16)
 554                         column >>= 1;
 555                 chip->cmd_ctrl(mtd, column, ctrl);
 556                 ctrl &= ~NAND_CTRL_CHANGE;
 557         }
 558         if (page_addr != -1) {
 559                 chip->cmd_ctrl(mtd, page_addr, ctrl);
 560                 ctrl &= ~NAND_CTRL_CHANGE;
 561                 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
 562                 /* One more address cycle for devices > 32MiB */
 563                 if (chip->chipsize > (32 << 20))
 564                         chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
 565         }
 566         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 567
 568         /*
 569          * Program and erase have their own busy handlers status and sequential
 570          * in needs no delay
 571          */
 572         switch (command) {
 573
 574         case NAND_CMD_PAGEPROG:
 575         case NAND_CMD_ERASE1:
 576         case NAND_CMD_ERASE2:
 577         case NAND_CMD_SEQIN:
 578         case NAND_CMD_STATUS:
 579                 return;
 580
 581         case NAND_CMD_RESET:
 582                 if (chip->dev_ready)
 583                         break;
 584                 udelay(chip->chip_delay);
 585                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 586                                NAND_CTRL_CLE | NAND_CTRL_CHANGE);
 587                 chip->cmd_ctrl(mtd,
 588                                NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 589                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 590                                 ;
 591                 return;
 592
 593                 /* This applies to read commands */
 594         default:
 595                 /*
 596                  * If we don't have access to the busy pin, we apply the given
 597                  * command delay
 598                  */
 599                 if (!chip->dev_ready) {
 600                         udelay(chip->chip_delay);
 601                         return;
 602                 }
 603         }
 604         /*
 605          * Apply this short delay always to ensure that we do wait tWB in
 606          * any case on any machine.
 607          */
 608         ndelay(100);
 609
 610         nand_wait_ready(mtd);
 611 }
 612
 613 /**
 614  * nand_command_lp - [DEFAULT] Send command to NAND large page device
 615  * @mtd: MTD device structure
 616  * @command: the command to be sent
 617  * @column: the column address for this command, -1 if none
 618  * @page_addr: the page address for this command, -1 if none
 619  *
 620  * Send command to NAND device. This is the version for the new large page
 621  * devices. We don't have the separate regions as we have in the small page
 622  * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
 623  */
 624 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
 625                             int column, int page_addr)
 626 {
 627         register struct nand_chip *chip = mtd->priv;
 628
 629         /* Emulate NAND_CMD_READOOB */
 630         if (command == NAND_CMD_READOOB) {
 631                 column += mtd->writesize;
 632                 command = NAND_CMD_READ0;
 633         }
 634
 635         /* Command latch cycle */
 636         chip->cmd_ctrl(mtd, command & 0xff,
 637                        NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 638
 639         if (column != -1 || page_addr != -1) {
 640                 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
 641
 642                 /* Serially input address */
 643                 if (column != -1) {
 644                         /* Adjust columns for 16 bit buswidth */
 645                         if (chip->options & NAND_BUSWIDTH_16)
 646                                 column >>= 1;
 647                         chip->cmd_ctrl(mtd, column, ctrl);
 648                         ctrl &= ~NAND_CTRL_CHANGE;
 649                         chip->cmd_ctrl(mtd, column >> 8, ctrl);
 650                 }
 651                 if (page_addr != -1) {
 652                         chip->cmd_ctrl(mtd, page_addr, ctrl);
 653                         chip->cmd_ctrl(mtd, page_addr >> 8,
 654                                        NAND_NCE | NAND_ALE);
 655                         /* One more address cycle for devices > 128MiB */
 656                         if (chip->chipsize > (128 << 20))
 657                                 chip->cmd_ctrl(mtd, page_addr >> 16,
 658                                                NAND_NCE | NAND_ALE);
 659                 }
 660         }
 661         chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
 662
 663         /*
 664          * Program and erase have their own busy handlers status, sequential
 665          * in, and deplete1 need no delay.
 666          */
 667         switch (command) {
 668
 669         case NAND_CMD_CACHEDPROG:
 670         case NAND_CMD_PAGEPROG:
 671         case NAND_CMD_ERASE1:
 672         case NAND_CMD_ERASE2:
 673         case NAND_CMD_SEQIN:
 674         case NAND_CMD_RNDIN:
 675         case NAND_CMD_STATUS:
 676         case NAND_CMD_DEPLETE1:
 677                 return;
 678
 679         case NAND_CMD_STATUS_ERROR:
 680         case NAND_CMD_STATUS_ERROR0:
 681         case NAND_CMD_STATUS_ERROR1:
 682         case NAND_CMD_STATUS_ERROR2:
 683         case NAND_CMD_STATUS_ERROR3:
 684                 /* Read error status commands require only a short delay */
 685                 udelay(chip->chip_delay);
 686                 return;
 687
 688         case NAND_CMD_RESET:
 689                 if (chip->dev_ready)
 690                         break;
 691                 udelay(chip->chip_delay);
 692                 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
 693                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 694                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 695                                NAND_NCE | NAND_CTRL_CHANGE);
 696                 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
 697                                 ;
 698                 return;
 699
 700         case NAND_CMD_RNDOUT:
 701                 /* No ready / busy check necessary */
 702                 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
 703                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 704                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 705                                NAND_NCE | NAND_CTRL_CHANGE);
 706                 return;
 707
 708         case NAND_CMD_READ0:
 709                 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
 710                                NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
 711                 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
 712                                NAND_NCE | NAND_CTRL_CHANGE);
 713
 714                 /* This applies to read commands */
 715         default:
 716                 /*
 717                  * If we don't have access to the busy pin, we apply the given
 718                  * command delay.
 719                  */
 720                 if (!chip->dev_ready) {
 721                         udelay(chip->chip_delay);
 722                         return;
 723                 }
 724         }
 725
 726         /*
 727          * Apply this short delay always to ensure that we do wait tWB in
 728          * any case on any machine.
 729          */
 730         ndelay(100);
 731
 732         nand_wait_ready(mtd);
 733 }
 734
 735 /**
 736  * panic_nand_get_device - [GENERIC] Get chip for selected access
 737  * @chip: the nand chip descriptor
 738  * @mtd: MTD device structure
 739  * @new_state: the state which is requested
 740  *
 741  * Used when in panic, no locks are taken.
 742  */
 743 static void panic_nand_get_device(struct nand_chip *chip,
 744                       struct mtd_info *mtd, int new_state)
 745 {
 746         /* Hardware controller shared among independent devices */
 747         chip->controller->active = chip;
 748         chip->state = new_state;
 749 }
 750
 751 /**
 752  * nand_get_device - [GENERIC] Get chip for selected access
 753  * @chip: the nand chip descriptor
 754  * @mtd: MTD device structure
 755  * @new_state: the state which is requested
 756  *
 757  * Get the device and lock it for exclusive access
 758  */
 759 static int
 760 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
 761 {
 762         spinlock_t *lock = &chip->controller->lock;
 763         wait_queue_head_t *wq = &chip->controller->wq;
 764         DECLARE_WAITQUEUE(wait, current);
 765 retry:
 766         spin_lock(lock);
 767
 768         /* Hardware controller shared among independent devices */
 769         if (!chip->controller->active)
 770                 chip->controller->active = chip;
 771
 772         if (chip->controller->active == chip && chip->state == FL_READY) {
 773                 chip->state = new_state;
 774                 spin_unlock(lock);
 775                 return 0;
 776         }
 777         if (new_state == FL_PM_SUSPENDED) {
 778                 if (chip->controller->active->state == FL_PM_SUSPENDED) {
 779                         chip->state = FL_PM_SUSPENDED;
 780                         spin_unlock(lock);
 781                         return 0;
 782                 }
 783         }
 784         set_current_state(TASK_UNINTERRUPTIBLE);
 785         add_wait_queue(wq, &wait);
 786         spin_unlock(lock);
 787         schedule();
 788         remove_wait_queue(wq, &wait);
 789         goto retry;
 790 }
 791
 792 /**
 793  * panic_nand_wait - [GENERIC] wait until the command is done
 794  * @mtd: MTD device structure
 795  * @chip: NAND chip structure
 796  * @timeo: timeout
 797  *
 798  * Wait for command done. This is a helper function for nand_wait used when
 799  * we are in interrupt context. May happen when in panic and trying to write
 800  * an oops through mtdoops.
 801  */
 802 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
 803                             unsigned long timeo)
 804 {
 805         int i;
 806         for (i = 0; i < timeo; i++) {
 807                 if (chip->dev_ready) {
 808                         if (chip->dev_ready(mtd))
 809                                 break;
 810                 } else {
 811                         if (chip->read_byte(mtd) & NAND_STATUS_READY)
 812                                 break;
 813                 }
 814                 mdelay(1);
 815         }
 816 }
 817
 818 /**
 819  * nand_wait - [DEFAULT] wait until the command is done
 820  * @mtd: MTD device structure
 821  * @chip: NAND chip structure
 822  *
 823  * Wait for command done. This applies to erase and program only. Erase can
 824  * take up to 400ms and program up to 20ms according to general NAND and
 825  * SmartMedia specs.
 826  */
 827 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
 828 {
 829
 830         unsigned long timeo = jiffies;
 831         int status, state = chip->state;
 832
 833         if (state == FL_ERASING)
 834                 timeo += (HZ * 400) / 1000;
 835         else
 836                 timeo += (HZ * 20) / 1000;
 837
 838         led_trigger_event(nand_led_trigger, LED_FULL);
 839
 840         /*
 841          * Apply this short delay always to ensure that we do wait tWB in any
 842          * case on any machine.
 843          */
 844         ndelay(100);
 845
 846         if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
 847                 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
 848         else
 849                 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
 850
 851         if (in_interrupt() || oops_in_progress)
 852                 panic_nand_wait(mtd, chip, timeo);
 853         else {
 854                 while (time_before(jiffies, timeo)) {
 855                         if (chip->dev_ready) {
 856                                 if (chip->dev_ready(mtd))
 857                                         break;
 858                         } else {
 859                                 if (chip->read_byte(mtd) & NAND_STATUS_READY)
 860                                         break;
 861                         }
 862                         cond_resched();
 863                 }
 864         }
 865         led_trigger_event(nand_led_trigger, LED_OFF);
 866
 867         status = (int)chip->read_byte(mtd);
 868         return status;
 869 }
 870
 871 /**
 872  * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 873  * @mtd: mtd info
 874  * @ofs: offset to start unlock from
 875  * @len: length to unlock
 876  * @invert: when = 0, unlock the range of blocks within the lower and
 877  *                    upper boundary address
 878  *          when = 1, unlock the range of blocks outside the boundaries
 879  *                    of the lower and upper boundary address
 880  *
 881  * Returs unlock status.
 882  */
 883 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
 884                                         uint64_t len, int invert)
 885 {
 886         int ret = 0;
 887         int status, page;
 888         struct nand_chip *chip = mtd->priv;
 889
 890         /* Submit address of first page to unlock */
 891         page = ofs >> chip->page_shift;
 892         chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
 893
 894         /* Submit address of last page to unlock */
 895         page = (ofs + len) >> chip->page_shift;
 896         chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
 897                                 (page | invert) & chip->pagemask);
 898
 899         /* Call wait ready function */
 900         status = chip->waitfunc(mtd, chip);
 901         /* See if device thinks it succeeded */
 902         if (status & 0x01) {
 903                 pr_debug("%s: error status = 0x%08x\n",
 904                                         __func__, status);
 905                 ret = -EIO;
 906         }
 907
 908         return ret;
 909 }
 910
 911 /**
 912  * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
 913  * @mtd: mtd info
 914  * @ofs: offset to start unlock from
 915  * @len: length to unlock
 916  *
 917  * Returns unlock status.
 918  */
 919 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 920 {
 921         int ret = 0;
 922         int chipnr;
 923         struct nand_chip *chip = mtd->priv;
 924
 925         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 926                         __func__, (unsigned long long)ofs, len);
 927
 928         if (check_offs_len(mtd, ofs, len))
 929                 ret = -EINVAL;
 930
 931         /* Align to last block address if size addresses end of the device */
 932         if (ofs + len == mtd->size)
 933                 len -= mtd->erasesize;
 934
 935         nand_get_device(chip, mtd, FL_UNLOCKING);
 936
 937         /* Shift to get chip number */
 938         chipnr = ofs >> chip->chip_shift;
 939
 940         chip->select_chip(mtd, chipnr);
 941
 942         /* Check, if it is write protected */
 943         if (nand_check_wp(mtd)) {
 944                 pr_debug("%s: device is write protected!\n",
 945                                         __func__);
 946                 ret = -EIO;
 947                 goto out;
 948         }
 949
 950         ret = __nand_unlock(mtd, ofs, len, 0);
 951
 952 out:
 953         nand_release_device(mtd);
 954
 955         return ret;
 956 }
 957 EXPORT_SYMBOL(nand_unlock);
 958
 959 /**
 960  * nand_lock - [REPLACEABLE] locks all blocks present in the device
 961  * @mtd: mtd info
 962  * @ofs: offset to start unlock from
 963  * @len: length to unlock
 964  *
 965  * This feature is not supported in many NAND parts. 'Micron' NAND parts do
 966  * have this feature, but it allows only to lock all blocks, not for specified
 967  * range for block. Implementing 'lock' feature by making use of 'unlock', for
 968  * now.
 969  *
 970  * Returns lock status.
 971  */
 972 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 973 {
 974         int ret = 0;
 975         int chipnr, status, page;
 976         struct nand_chip *chip = mtd->priv;
 977
 978         pr_debug("%s: start = 0x%012llx, len = %llu\n",
 979                         __func__, (unsigned long long)ofs, len);
 980
 981         if (check_offs_len(mtd, ofs, len))
 982                 ret = -EINVAL;
 983
 984         nand_get_device(chip, mtd, FL_LOCKING);
 985
 986         /* Shift to get chip number */
 987         chipnr = ofs >> chip->chip_shift;
 988
 989         chip->select_chip(mtd, chipnr);
 990
 991         /* Check, if it is write protected */
 992         if (nand_check_wp(mtd)) {
 993                 pr_debug("%s: device is write protected!\n",
 994                                         __func__);
 995                 status = MTD_ERASE_FAILED;
 996                 ret = -EIO;
 997                 goto out;
 998         }
 999
1000         /* Submit address of first page to lock */
1001         page = ofs >> chip->page_shift;
1002         chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1003
1004         /* Call wait ready function */
1005         status = chip->waitfunc(mtd, chip);
1006         /* See if device thinks it succeeded */
1007         if (status & 0x01) {
1008                 pr_debug("%s: error status = 0x%08x\n",
1009                                         __func__, status);
1010                 ret = -EIO;
1011                 goto out;
1012         }
1013
1014         ret = __nand_unlock(mtd, ofs, len, 0x1);
1015
1016 out:
1017         nand_release_device(mtd);
1018
1019         return ret;
1020 }
1021 EXPORT_SYMBOL(nand_lock);
1022
1023 /**
1024  * nand_read_page_raw - [INTERN] read raw page data without ecc
1025  * @mtd: mtd info structure
1026  * @chip: nand chip info structure
1027  * @buf: buffer to store read data
1028  * @oob_required: caller requires OOB data read to chip->oob_poi
1029  * @page: page number to read
1030  *
1031  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1032  */
1033 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1034                               uint8_t *buf, int oob_required, int page)
1035 {
1036         chip->read_buf(mtd, buf, mtd->writesize);
1037         if (oob_required)
1038                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1039         return 0;
1040 }
1041
1042 /**
1043  * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
1044  * @mtd: mtd info structure
1045  * @chip: nand chip info structure
1046  * @buf: buffer to store read data
1047  * @oob_required: caller requires OOB data read to chip->oob_poi
1048  * @page: page number to read
1049  *
1050  * We need a special oob layout and handling even when OOB isn't used.
1051  */
1052 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1053                                        struct nand_chip *chip, uint8_t *buf,
1054                                        int oob_required, int page)
1055 {
1056         int eccsize = chip->ecc.size;
1057         int eccbytes = chip->ecc.bytes;
1058         uint8_t *oob = chip->oob_poi;
1059         int steps, size;
1060
1061         for (steps = chip->ecc.steps; steps > 0; steps--) {
1062                 chip->read_buf(mtd, buf, eccsize);
1063                 buf += eccsize;
1064
1065                 if (chip->ecc.prepad) {
1066                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1067                         oob += chip->ecc.prepad;
1068                 }
1069
1070                 chip->read_buf(mtd, oob, eccbytes);
1071                 oob += eccbytes;
1072
1073                 if (chip->ecc.postpad) {
1074                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1075                         oob += chip->ecc.postpad;
1076                 }
1077         }
1078
1079         size = mtd->oobsize - (oob - chip->oob_poi);
1080         if (size)
1081                 chip->read_buf(mtd, oob, size);
1082
1083         return 0;
1084 }
1085
1086 /**
1087  * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
1088  * @mtd: mtd info structure
1089  * @chip: nand chip info structure
1090  * @buf: buffer to store read data
1091  * @oob_required: caller requires OOB data read to chip->oob_poi
1092  * @page: page number to read
1093  */
1094 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1095                                 uint8_t *buf, int oob_required, int page)
1096 {
1097         int i, eccsize = chip->ecc.size;
1098         int eccbytes = chip->ecc.bytes;
1099         int eccsteps = chip->ecc.steps;
1100         uint8_t *p = buf;
1101         uint8_t *ecc_calc = chip->buffers->ecccalc;
1102         uint8_t *ecc_code = chip->buffers->ecccode;
1103         uint32_t *eccpos = chip->ecc.layout->eccpos;
1104         unsigned int max_bitflips = 0;
1105
1106         chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
1107
1108         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1109                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1110
1111         for (i = 0; i < chip->ecc.total; i++)
1112                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1113
1114         eccsteps = chip->ecc.steps;
1115         p = buf;
1116
1117         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1118                 int stat;
1119
1120                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1121                 if (stat < 0) {
1122                         mtd->ecc_stats.failed++;
1123                 } else {
1124                         mtd->ecc_stats.corrected += stat;
1125                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1126                 }
1127         }
1128         return max_bitflips;
1129 }
1130
1131 /**
1132  * nand_read_subpage - [REPLACEABLE] software ECC based sub-page read function
1133  * @mtd: mtd info structure
1134  * @chip: nand chip info structure
1135  * @data_offs: offset of requested data within the page
1136  * @readlen: data length
1137  * @bufpoi: buffer to store read data
1138  */
1139 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1140                         uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1141 {
1142         int start_step, end_step, num_steps;
1143         uint32_t *eccpos = chip->ecc.layout->eccpos;
1144         uint8_t *p;
1145         int data_col_addr, i, gaps = 0;
1146         int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1147         int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1148         int index = 0;
1149         unsigned int max_bitflips = 0;
1150
1151         /* Column address within the page aligned to ECC size (256bytes) */
1152         start_step = data_offs / chip->ecc.size;
1153         end_step = (data_offs + readlen - 1) / chip->ecc.size;
1154         num_steps = end_step - start_step + 1;
1155
1156         /* Data size aligned to ECC ecc.size */
1157         datafrag_len = num_steps * chip->ecc.size;
1158         eccfrag_len = num_steps * chip->ecc.bytes;
1159
1160         data_col_addr = start_step * chip->ecc.size;
1161         /* If we read not a page aligned data */
1162         if (data_col_addr != 0)
1163                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1164
1165         p = bufpoi + data_col_addr;
1166         chip->read_buf(mtd, p, datafrag_len);
1167
1168         /* Calculate ECC */
1169         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1170                 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1171
1172         /*
1173          * The performance is faster if we position offsets according to
1174          * ecc.pos. Let's make sure that there are no gaps in ECC positions.
1175          */
1176         for (i = 0; i < eccfrag_len - 1; i++) {
1177                 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1178                         eccpos[i + start_step * chip->ecc.bytes + 1]) {
1179                         gaps = 1;
1180                         break;
1181                 }
1182         }
1183         if (gaps) {
1184                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1185                 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1186         } else {
1187                 /*
1188                  * Send the command to read the particular ECC bytes take care
1189                  * about buswidth alignment in read_buf.
1190                  */
1191                 index = start_step * chip->ecc.bytes;
1192
1193                 aligned_pos = eccpos[index] & ~(busw - 1);
1194                 aligned_len = eccfrag_len;
1195                 if (eccpos[index] & (busw - 1))
1196                         aligned_len++;
1197                 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1198                         aligned_len++;
1199
1200                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1201                                         mtd->writesize + aligned_pos, -1);
1202                 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1203         }
1204
1205         for (i = 0; i < eccfrag_len; i++)
1206                 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1207
1208         p = bufpoi + data_col_addr;
1209         for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1210                 int stat;
1211
1212                 stat = chip->ecc.correct(mtd, p,
1213                         &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1214                 if (stat < 0) {
1215                         mtd->ecc_stats.failed++;
1216                 } else {
1217                         mtd->ecc_stats.corrected += stat;
1218                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1219                 }
1220         }
1221         return max_bitflips;
1222 }
1223
1224 /**
1225  * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
1226  * @mtd: mtd info structure
1227  * @chip: nand chip info structure
1228  * @buf: buffer to store read data
1229  * @oob_required: caller requires OOB data read to chip->oob_poi
1230  * @page: page number to read
1231  *
1232  * Not for syndrome calculating ECC controllers which need a special oob layout.
1233  */
1234 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1235                                 uint8_t *buf, int oob_required, int page)
1236 {
1237         int i, eccsize = chip->ecc.size;
1238         int eccbytes = chip->ecc.bytes;
1239         int eccsteps = chip->ecc.steps;
1240         uint8_t *p = buf;
1241         uint8_t *ecc_calc = chip->buffers->ecccalc;
1242         uint8_t *ecc_code = chip->buffers->ecccode;
1243         uint32_t *eccpos = chip->ecc.layout->eccpos;
1244         unsigned int max_bitflips = 0;
1245
1246         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1247                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1248                 chip->read_buf(mtd, p, eccsize);
1249                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1250         }
1251         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1252
1253         for (i = 0; i < chip->ecc.total; i++)
1254                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1255
1256         eccsteps = chip->ecc.steps;
1257         p = buf;
1258
1259         for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1260                 int stat;
1261
1262                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1263                 if (stat < 0) {
1264                         mtd->ecc_stats.failed++;
1265                 } else {
1266                         mtd->ecc_stats.corrected += stat;
1267                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1268                 }
1269         }
1270         return max_bitflips;
1271 }
1272
1273 /**
1274  * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
1275  * @mtd: mtd info structure
1276  * @chip: nand chip info structure
1277  * @buf: buffer to store read data
1278  * @oob_required: caller requires OOB data read to chip->oob_poi
1279  * @page: page number to read
1280  *
1281  * Hardware ECC for large page chips, require OOB to be read first. For this
1282  * ECC mode, the write_page method is re-used from ECC_HW. These methods
1283  * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
1284  * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
1285  * the data area, by overwriting the NAND manufacturer bad block markings.
1286  */
1287 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1288         struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
1289 {
1290         int i, eccsize = chip->ecc.size;
1291         int eccbytes = chip->ecc.bytes;
1292         int eccsteps = chip->ecc.steps;
1293         uint8_t *p = buf;
1294         uint8_t *ecc_code = chip->buffers->ecccode;
1295         uint32_t *eccpos = chip->ecc.layout->eccpos;
1296         uint8_t *ecc_calc = chip->buffers->ecccalc;
1297         unsigned int max_bitflips = 0;
1298
1299         /* Read the OOB area first */
1300         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1301         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1302         chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1303
1304         for (i = 0; i < chip->ecc.total; i++)
1305                 ecc_code[i] = chip->oob_poi[eccpos[i]];
1306
1307         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1308                 int stat;
1309
1310                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1311                 chip->read_buf(mtd, p, eccsize);
1312                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1313
1314                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1315                 if (stat < 0) {
1316                         mtd->ecc_stats.failed++;
1317                 } else {
1318                         mtd->ecc_stats.corrected += stat;
1319                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1320                 }
1321         }
1322         return max_bitflips;
1323 }
1324
1325 /**
1326  * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
1327  * @mtd: mtd info structure
1328  * @chip: nand chip info structure
1329  * @buf: buffer to store read data
1330  * @oob_required: caller requires OOB data read to chip->oob_poi
1331  * @page: page number to read
1332  *
1333  * The hw generator calculates the error syndrome automatically. Therefore we
1334  * need a special oob layout and handling.
1335  */
1336 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1337                                    uint8_t *buf, int oob_required, int page)
1338 {
1339         int i, eccsize = chip->ecc.size;
1340         int eccbytes = chip->ecc.bytes;
1341         int eccsteps = chip->ecc.steps;
1342         uint8_t *p = buf;
1343         uint8_t *oob = chip->oob_poi;
1344         unsigned int max_bitflips = 0;
1345
1346         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1347                 int stat;
1348
1349                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1350                 chip->read_buf(mtd, p, eccsize);
1351
1352                 if (chip->ecc.prepad) {
1353                         chip->read_buf(mtd, oob, chip->ecc.prepad);
1354                         oob += chip->ecc.prepad;
1355                 }
1356
1357                 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1358                 chip->read_buf(mtd, oob, eccbytes);
1359                 stat = chip->ecc.correct(mtd, p, oob, NULL);
1360
1361                 if (stat < 0) {
1362                         mtd->ecc_stats.failed++;
1363                 } else {
1364                         mtd->ecc_stats.corrected += stat;
1365                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
1366                 }
1367
1368                 oob += eccbytes;
1369
1370                 if (chip->ecc.postpad) {
1371                         chip->read_buf(mtd, oob, chip->ecc.postpad);
1372                         oob += chip->ecc.postpad;
1373                 }
1374         }
1375
1376         /* Calculate remaining oob bytes */
1377         i = mtd->oobsize - (oob - chip->oob_poi);
1378         if (i)
1379                 chip->read_buf(mtd, oob, i);
1380
1381         return max_bitflips;
1382 }
1383
1384 /**
1385  * nand_transfer_oob - [INTERN] Transfer oob to client buffer
1386  * @chip: nand chip structure
1387  * @oob: oob destination address
1388  * @ops: oob ops structure
1389  * @len: size of oob to transfer
1390  */
1391 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1392                                   struct mtd_oob_ops *ops, size_t len)
1393 {
1394         switch (ops->mode) {
1395
1396         case MTD_OPS_PLACE_OOB:
1397         case MTD_OPS_RAW:
1398                 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1399                 return oob + len;
1400
1401         case MTD_OPS_AUTO_OOB: {
1402                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1403                 uint32_t boffs = 0, roffs = ops->ooboffs;
1404                 size_t bytes = 0;
1405
1406                 for (; free->length && len; free++, len -= bytes) {
1407                         /* Read request not from offset 0? */
1408                         if (unlikely(roffs)) {
1409                                 if (roffs >= free->length) {
1410                                         roffs -= free->length;
1411                                         continue;
1412                                 }
1413                                 boffs = free->offset + roffs;
1414                                 bytes = min_t(size_t, len,
1415                                               (free->length - roffs));
1416                                 roffs = 0;
1417                         } else {
1418                                 bytes = min_t(size_t, len, free->length);
1419                                 boffs = free->offset;
1420                         }
1421                         memcpy(oob, chip->oob_poi + boffs, bytes);
1422                         oob += bytes;
1423                 }
1424                 return oob;
1425         }
1426         default:
1427                 BUG();
1428         }
1429         return NULL;
1430 }
1431
1432 /**
1433  * nand_do_read_ops - [INTERN] Read data with ECC
1434  * @mtd: MTD device structure
1435  * @from: offset to read from
1436  * @ops: oob ops structure
1437  *
1438  * Internal function. Called with chip held.
1439  */
1440 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1441                             struct mtd_oob_ops *ops)
1442 {
1443         int chipnr, page, realpage, col, bytes, aligned, oob_required;
1444         struct nand_chip *chip = mtd->priv;
1445         struct mtd_ecc_stats stats;
1446         int ret = 0;
1447         uint32_t readlen = ops->len;
1448         uint32_t oobreadlen = ops->ooblen;
1449         uint32_t max_oobsize = ops->mode == MTD_OPS_AUTO_OOB ?
1450                 mtd->oobavail : mtd->oobsize;
1451
1452         uint8_t *bufpoi, *oob, *buf;
1453         unsigned int max_bitflips = 0;
1454
1455         stats = mtd->ecc_stats;
1456
1457         chipnr = (int)(from >> chip->chip_shift);
1458         chip->select_chip(mtd, chipnr);
1459
1460         realpage = (int)(from >> chip->page_shift);
1461         page = realpage & chip->pagemask;
1462
1463         col = (int)(from & (mtd->writesize - 1));
1464
1465         buf = ops->datbuf;
1466         oob = ops->oobbuf;
1467         oob_required = oob ? 1 : 0;
1468
1469         while (1) {
1470                 bytes = min(mtd->writesize - col, readlen);
1471                 aligned = (bytes == mtd->writesize);
1472
1473                 /* Is the current page in the buffer? */
1474                 if (realpage != chip->pagebuf || oob) {
1475                         bufpoi = aligned ? buf : chip->buffers->databuf;
1476
1477                         chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1478
1479                         /*
1480                          * Now read the page into the buffer.  Absent an error,
1481                          * the read methods return max bitflips per ecc step.
1482                          */
1483                         if (unlikely(ops->mode == MTD_OPS_RAW))
1484                                 ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
1485                                                               oob_required,
1486                                                               page);
1487                         else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
1488                                  !oob)
1489                                 ret = chip->ecc.read_subpage(mtd, chip,
1490                                                         col, bytes, bufpoi);
1491                         else
1492                                 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1493                                                           oob_required, page);
1494                         if (ret < 0) {
1495                                 if (!aligned)
1496                                         /* Invalidate page cache */
1497                                         chip->pagebuf = -1;
1498                                 break;
1499                         }
1500
1501                         max_bitflips = max_t(unsigned int, max_bitflips, ret);
1502
1503                         /* Transfer not aligned data */
1504                         if (!aligned) {
1505                                 if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
1506                                     !(mtd->ecc_stats.failed - stats.failed) &&
1507                                     (ops->mode != MTD_OPS_RAW)) {
1508                                         chip->pagebuf = realpage;
1509                                         chip->pagebuf_bitflips = ret;
1510                                 } else {
1511                                         /* Invalidate page cache */
1512                                         chip->pagebuf = -1;
1513                                 }
1514                                 memcpy(buf, chip->buffers->databuf + col, bytes);
1515                         }
1516
1517                         buf += bytes;
1518
1519                         if (unlikely(oob)) {
1520                                 int toread = min(oobreadlen, max_oobsize);
1521
1522                                 if (toread) {
1523                                         oob = nand_transfer_oob(chip,
1524                                                 oob, ops, toread);
1525                                         oobreadlen -= toread;
1526                                 }
1527                         }
1528                 } else {
1529                         memcpy(buf, chip->buffers->databuf + col, bytes);
1530                         buf += bytes;
1531                         max_bitflips = max_t(unsigned int, max_bitflips,
1532                                              chip->pagebuf_bitflips);
1533                 }
1534
1535                 readlen -= bytes;
1536
1537                 if (!readlen)
1538                         break;
1539
1540                 /* For subsequent reads align to page boundary */
1541                 col = 0;
1542                 /* Increment page address */
1543                 realpage++;
1544
1545                 page = realpage & chip->pagemask;
1546                 /* Check, if we cross a chip boundary */
1547                 if (!page) {
1548                         chipnr++;
1549                         chip->select_chip(mtd, -1);
1550                         chip->select_chip(mtd, chipnr);
1551                 }
1552         }
1553
1554         ops->retlen = ops->len - (size_t) readlen;
1555         if (oob)
1556                 ops->oobretlen = ops->ooblen - oobreadlen;
1557
1558         if (ret < 0)
1559                 return ret;
1560
1561         if (mtd->ecc_stats.failed - stats.failed)
1562                 return -EBADMSG;
1563
1564         return max_bitflips;
1565 }
1566
1567 /**
1568  * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1569  * @mtd: MTD device structure
1570  * @from: offset to read from
1571  * @len: number of bytes to read
1572  * @retlen: pointer to variable to store the number of read bytes
1573  * @buf: the databuffer to put data
1574  *
1575  * Get hold of the chip and call nand_do_read.
1576  */
1577 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1578                      size_t *retlen, uint8_t *buf)
1579 {
1580         struct nand_chip *chip = mtd->priv;
1581         struct mtd_oob_ops ops;
1582         int ret;
1583
1584         nand_get_device(chip, mtd, FL_READING);
1585         ops.len = len;
1586         ops.datbuf = buf;
1587         ops.oobbuf = NULL;
1588         ops.mode = MTD_OPS_PLACE_OOB;
1589         ret = nand_do_read_ops(mtd, from, &ops);
1590         *retlen = ops.retlen;
1591         nand_release_device(mtd);
1592         return ret;
1593 }
1594
1595 /**
1596  * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
1597  * @mtd: mtd info structure
1598  * @chip: nand chip info structure
1599  * @page: page number to read
1600  */
1601 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1602                              int page)
1603 {
1604         chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1605         chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1606         return 0;
1607 }
1608
1609 /**
1610  * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
1611  *                          with syndromes
1612  * @mtd: mtd info structure
1613  * @chip: nand chip info structure
1614  * @page: page number to read
1615  */
1616 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1617                                   int page)
1618 {
1619         uint8_t *buf = chip->oob_poi;
1620         int length = mtd->oobsize;
1621         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1622         int eccsize = chip->ecc.size;
1623         uint8_t *bufpoi = buf;
1624         int i, toread, sndrnd = 0, pos;
1625
1626         chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1627         for (i = 0; i < chip->ecc.steps; i++) {
1628                 if (sndrnd) {
1629                         pos = eccsize + i * (eccsize + chunk);
1630                         if (mtd->writesize > 512)
1631                                 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1632                         else
1633                                 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1634                 } else
1635                         sndrnd = 1;
1636                 toread = min_t(int, length, chunk);
1637                 chip->read_buf(mtd, bufpoi, toread);
1638                 bufpoi += toread;
1639                 length -= toread;
1640         }
1641         if (length > 0)
1642                 chip->read_buf(mtd, bufpoi, length);
1643
1644         return 0;
1645 }
1646
1647 /**
1648  * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
1649  * @mtd: mtd info structure
1650  * @chip: nand chip info structure
1651  * @page: page number to write
1652  */
1653 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1654                               int page)
1655 {
1656         int status = 0;
1657         const uint8_t *buf = chip->oob_poi;
1658         int length = mtd->oobsize;
1659
1660         chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1661         chip->write_buf(mtd, buf, length);
1662         /* Send command to program the OOB data */
1663         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1664
1665         status = chip->waitfunc(mtd, chip);
1666
1667         return status & NAND_STATUS_FAIL ? -EIO : 0;
1668 }
1669
1670 /**
1671  * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
1672  *                           with syndrome - only for large page flash
1673  * @mtd: mtd info structure
1674  * @chip: nand chip info structure
1675  * @page: page number to write
1676  */
1677 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1678                                    struct nand_chip *chip, int page)
1679 {
1680         int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1681         int eccsize = chip->ecc.size, length = mtd->oobsize;
1682         int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1683         const uint8_t *bufpoi = chip->oob_poi;
1684
1685         /*
1686          * data-ecc-data-ecc ... ecc-oob
1687          * or
1688          * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1689          */
1690         if (!chip->ecc.prepad && !chip->ecc.postpad) {
1691                 pos = steps * (eccsize + chunk);
1692                 steps = 0;
1693         } else
1694                 pos = eccsize;
1695
1696         chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1697         for (i = 0; i < steps; i++) {
1698                 if (sndcmd) {
1699                         if (mtd->writesize <= 512) {
1700                                 uint32_t fill = 0xFFFFFFFF;
1701
1702                                 len = eccsize;
1703                                 while (len > 0) {
1704                                         int num = min_t(int, len, 4);
1705                                         chip->write_buf(mtd, (uint8_t *)&fill,
1706                                                         num);
1707                                         len -= num;
1708                                 }
1709                         } else {
1710                                 pos = eccsize + i * (eccsize + chunk);
1711                                 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1712                         }
1713                 } else
1714                         sndcmd = 1;
1715                 len = min_t(int, length, chunk);
1716                 chip->write_buf(mtd, bufpoi, len);
1717                 bufpoi += len;
1718                 length -= len;
1719         }
1720         if (length > 0)
1721                 chip->write_buf(mtd, bufpoi, length);
1722
1723         chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1724         status = chip->waitfunc(mtd, chip);
1725
1726         return status & NAND_STATUS_FAIL ? -EIO : 0;
1727 }
1728
1729 /**
1730  * nand_do_read_oob - [INTERN] NAND read out-of-band
1731  * @mtd: MTD device structure
1732  * @from: offset to read from
1733  * @ops: oob operations description structure
1734  *
1735  * NAND read out-of-band data from the spare area.
1736  */
1737 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1738                             struct mtd_oob_ops *ops)
1739 {
1740         int page, realpage, chipnr;
1741         struct nand_chip *chip = mtd->priv;
1742         struct mtd_ecc_stats stats;
1743         int readlen = ops->ooblen;
1744         int len;
1745         uint8_t *buf = ops->oobbuf;
1746         int ret = 0;
1747
1748         pr_debug("%s: from = 0x%08Lx, len = %i\n",
1749                         __func__, (unsigned long long)from, readlen);
1750
1751         stats = mtd->ecc_stats;
1752
1753         if (ops->mode == MTD_OPS_AUTO_OOB)
1754                 len = chip->ecc.layout->oobavail;
1755         else
1756                 len = mtd->oobsize;
1757
1758         if (unlikely(ops->ooboffs >= len)) {
1759                 pr_debug("%s: attempt to start read outside oob\n",
1760                                 __func__);
1761                 return -EINVAL;
1762         }
1763
1764         /* Do not allow reads past end of device */
1765         if (unlikely(from >= mtd->size ||
1766                      ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1767                                         (from >> chip->page_shift)) * len)) {
1768                 pr_debug("%s: attempt to read beyond end of device\n",
1769                                 __func__);
1770                 return -EINVAL;
1771         }
1772
1773         chipnr = (int)(from >> chip->chip_shift);
1774         chip->select_chip(mtd, chipnr);
1775
1776         /* Shift to get page */
1777         realpage = (int)(from >> chip->page_shift);
1778         page = realpage & chip->pagemask;
1779
1780         while (1) {
1781                 if (ops->mode == MTD_OPS_RAW)
1782                         ret = chip->ecc.read_oob_raw(mtd, chip, page);
1783                 else
1784                         ret = chip->ecc.read_oob(mtd, chip, page);
1785
1786                 if (ret < 0)
1787                         break;
1788
1789                 len = min(len, readlen);
1790                 buf = nand_transfer_oob(chip, buf, ops, len);
1791
1792                 readlen -= len;
1793                 if (!readlen)
1794                         break;
1795
1796                 /* Increment page address */
1797                 realpage++;
1798
1799                 page = realpage & chip->pagemask;
1800                 /* Check, if we cross a chip boundary */
1801                 if (!page) {
1802                         chipnr++;
1803                         chip->select_chip(mtd, -1);
1804                         chip->select_chip(mtd, chipnr);
1805                 }
1806         }
1807
1808         ops->oobretlen = ops->ooblen - readlen;
1809
1810         if (ret < 0)
1811                 return ret;
1812
1813         if (mtd->ecc_stats.failed - stats.failed)
1814                 return -EBADMSG;
1815
1816         return  mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1817 }
1818
1819 /**
1820  * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1821  * @mtd: MTD device structure
1822  * @from: offset to read from
1823  * @ops: oob operation description structure
1824  *
1825  * NAND read data and/or out-of-band data.
1826  */
1827 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1828                          struct mtd_oob_ops *ops)
1829 {
1830         struct nand_chip *chip = mtd->priv;
1831         int ret = -ENOTSUPP;
1832
1833         ops->retlen = 0;
1834
1835         /* Do not allow reads past end of device */
1836         if (ops->datbuf && (from + ops->len) > mtd->size) {
1837                 pr_debug("%s: attempt to read beyond end of device\n",
1838                                 __func__);
1839                 return -EINVAL;
1840         }
1841
1842         nand_get_device(chip, mtd, FL_READING);
1843
1844         switch (ops->mode) {
1845         case MTD_OPS_PLACE_OOB:
1846         case MTD_OPS_AUTO_OOB:
1847         case MTD_OPS_RAW:
1848                 break;
1849
1850         default:
1851                 goto out;
1852         }
1853
1854         if (!ops->datbuf)
1855                 ret = nand_do_read_oob(mtd, from, ops);
1856         else
1857                 ret = nand_do_read_ops(mtd, from, ops);
1858
1859 out:
1860         nand_release_device(mtd);
1861         return ret;
1862 }
1863
1864
1865 /**
1866  * nand_write_page_raw - [INTERN] raw page write function
1867  * @mtd: mtd info structure
1868  * @chip: nand chip info structure
1869  * @buf: data buffer
1870  * @oob_required: must write chip->oob_poi to OOB
1871  *
1872  * Not for syndrome calculating ECC controllers, which use a special oob layout.
1873  */
1874 static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1875                                 const uint8_t *buf, int oob_required)
1876 {
1877         chip->write_buf(mtd, buf, mtd->writesize);
1878         if (oob_required)
1879                 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1880
1881         return 0;
1882 }
1883
1884 /**
1885  * nand_write_page_raw_syndrome - [INTERN] raw page write function
1886  * @mtd: mtd info structure
1887  * @chip: nand chip info structure
1888  * @buf: data buffer
1889  * @oob_required: must write chip->oob_poi to OOB
1890  *
1891  * We need a special oob layout and handling even when ECC isn't checked.
1892  */
1893 static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
1894                                         struct nand_chip *chip,
1895                                         const uint8_t *buf, int oob_required)
1896 {
1897         int eccsize = chip->ecc.size;
1898         int eccbytes = chip->ecc.bytes;
1899         uint8_t *oob = chip->oob_poi;
1900         int steps, size;
1901
1902         for (steps = chip->ecc.steps; steps > 0; steps--) {
1903                 chip->write_buf(mtd, buf, eccsize);
1904                 buf += eccsize;
1905
1906                 if (chip->ecc.prepad) {
1907                         chip->write_buf(mtd, oob, chip->ecc.prepad);
1908                         oob += chip->ecc.prepad;
1909                 }
1910
1911                 chip->read_buf(mtd, oob, eccbytes);
1912                 oob += eccbytes;
1913
1914                 if (chip->ecc.postpad) {
1915                         chip->write_buf(mtd, oob, chip->ecc.postpad);
1916                         oob += chip->ecc.postpad;
1917                 }
1918         }
1919
1920         size = mtd->oobsize - (oob - chip->oob_poi);
1921         if (size)
1922                 chip->write_buf(mtd, oob, size);
1923
1924         return 0;
1925 }
1926 /**
1927  * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
1928  * @mtd: mtd info structure
1929  * @chip: nand chip info structure
1930  * @buf: data buffer
1931  * @oob_required: must write chip->oob_poi to OOB
1932  */
1933 static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1934                                   const uint8_t *buf, int oob_required)
1935 {
1936         int i, eccsize = chip->ecc.size;
1937         int eccbytes = chip->ecc.bytes;
1938         int eccsteps = chip->ecc.steps;
1939         uint8_t *ecc_calc = chip->buffers->ecccalc;
1940         const uint8_t *p = buf;
1941         uint32_t *eccpos = chip->ecc.layout->eccpos;
1942
1943         /* Software ECC calculation */
1944         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1945                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1946
1947         for (i = 0; i < chip->ecc.total; i++)
1948                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1949
1950         return chip->ecc.write_page_raw(mtd, chip, buf, 1);
1951 }
1952
1953 /**
1954  * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
1955  * @mtd: mtd info structure
1956  * @chip: nand chip info structure
1957  * @buf: data buffer
1958  * @oob_required: must write chip->oob_poi to OOB
1959  */
1960 static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1961                                   const uint8_t *buf, int oob_required)
1962 {
1963         int i, eccsize = chip->ecc.size;
1964         int eccbytes = chip->ecc.bytes;
1965         int eccsteps = chip->ecc.steps;
1966         uint8_t *ecc_calc = chip->buffers->ecccalc;
1967         const uint8_t *p = buf;
1968         uint32_t *eccpos = chip->ecc.layout->eccpos;
1969
1970         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1971                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1972                 chip->write_buf(mtd, p, eccsize);
1973                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1974         }
1975
1976         for (i = 0; i < chip->ecc.total; i++)
1977                 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1978
1979         chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1980
1981         return 0;
1982 }
1983
1984 /**
1985  * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
1986  * @mtd: mtd info structure
1987  * @chip: nand chip info structure
1988  * @buf: data buffer
1989  * @oob_required: must write chip->oob_poi to OOB
1990  *
1991  * The hw generator calculates the error syndrome automatically. Therefore we
1992  * need a special oob layout and handling.
1993  */
1994 static int nand_write_page_syndrome(struct mtd_info *mtd,
1995                                     struct nand_chip *chip,
1996                                     const uint8_t *buf, int oob_required)
1997 {
1998         int i, eccsize = chip->ecc.size;
1999         int eccbytes = chip->ecc.bytes;
2000         int eccsteps = chip->ecc.steps;
2001         const uint8_t *p = buf;
2002         uint8_t *oob = chip->oob_poi;
2003
2004         for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2005
2006                 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2007                 chip->write_buf(mtd, p, eccsize);
2008
2009                 if (chip->ecc.prepad) {
2010                         chip->write_buf(mtd, oob, chip->ecc.prepad);
2011                         oob += chip->ecc.prepad;
2012                 }
2013
2014                 chip->ecc.calculate(mtd, p, oob);
2015                 chip->write_buf(mtd, oob, eccbytes);
2016                 oob += eccbytes;
2017
2018                 if (chip->ecc.postpad) {
2019                         chip->write_buf(mtd, oob, chip->ecc.postpad);
2020                         oob += chip->ecc.postpad;
2021                 }
2022         }
2023
2024         /* Calculate remaining oob bytes */
2025         i = mtd->oobsize - (oob - chip->oob_poi);
2026         if (i)
2027                 chip->write_buf(mtd, oob, i);
2028
2029         return 0;
2030 }
2031
2032 /**
2033  * nand_write_page - [REPLACEABLE] write one page
2034  * @mtd: MTD device structure
2035  * @chip: NAND chip descriptor
2036  * @buf: the data to write
2037  * @oob_required: must write chip->oob_poi to OOB
2038  * @page: page number to write
2039  * @cached: cached programming
2040  * @raw: use _raw version of write_page
2041  */
2042 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2043                            const uint8_t *buf, int oob_required, int page,
2044                            int cached, int raw)
2045 {
2046         int status;
2047
2048         chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2049
2050         if (unlikely(raw))
2051                 status = chip->ecc.write_page_raw(mtd, chip, buf, oob_required);
2052         else
2053                 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2054
2055         if (status < 0)
2056                 return status;
2057
2058         /*
2059          * Cached progamming disabled for now. Not sure if it's worth the
2060          * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s).
2061          */
2062         cached = 0;
2063
2064         if (!cached || !(chip->options & NAND_CACHEPRG)) {
2065
2066                 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2067                 status = chip->waitfunc(mtd, chip);
2068                 /*
2069                  * See if operation failed and additional status checks are
2070                  * available.
2071                  */
2072                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2073                         status = chip->errstat(mtd, chip, FL_WRITING, status,
2074                                                page);
2075
2076                 if (status & NAND_STATUS_FAIL)
2077                         return -EIO;
2078         } else {
2079                 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2080                 status = chip->waitfunc(mtd, chip);
2081         }
2082
2083         return 0;
2084 }
2085
2086 /**
2087  * nand_fill_oob - [INTERN] Transfer client buffer to oob
2088  * @mtd: MTD device structure
2089  * @oob: oob data buffer
2090  * @len: oob data write length
2091  * @ops: oob ops structure
2092  */
2093 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2094                               struct mtd_oob_ops *ops)
2095 {
2096         struct nand_chip *chip = mtd->priv;
2097
2098         /*
2099          * Initialise to all 0xFF, to avoid the possibility of left over OOB
2100          * data from a previous OOB read.
2101          */
2102         memset(chip->oob_poi, 0xff, mtd->oobsize);
2103
2104         switch (ops->mode) {
2105
2106         case MTD_OPS_PLACE_OOB:
2107         case MTD_OPS_RAW:
2108                 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2109                 return oob + len;
2110
2111         case MTD_OPS_AUTO_OOB: {
2112                 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2113                 uint32_t boffs = 0, woffs = ops->ooboffs;
2114                 size_t bytes = 0;
2115
2116                 for (; free->length && len; free++, len -= bytes) {
2117                         /* Write request not from offset 0? */
2118                         if (unlikely(woffs)) {
2119                                 if (woffs >= free->length) {
2120                                         woffs -= free->length;
2121                                         continue;
2122                                 }
2123                                 boffs = free->offset + woffs;
2124                                 bytes = min_t(size_t, len,
2125                                               (free->length - woffs));
2126                                 woffs = 0;
2127                         } else {
2128                                 bytes = min_t(size_t, len, free->length);
2129                                 boffs = free->offset;
2130                         }
2131                         memcpy(chip->oob_poi + boffs, oob, bytes);
2132                         oob += bytes;
2133                 }
2134                 return oob;
2135         }
2136         default:
2137                 BUG();
2138         }
2139         return NULL;
2140 }
2141
2142 #define NOTALIGNED(x)   ((x & (chip->subpagesize - 1)) != 0)
2143
2144 /**
2145  * nand_do_write_ops - [INTERN] NAND write with ECC
2146  * @mtd: MTD device structure
2147  * @to: offset to write to
2148  * @ops: oob operations description structure
2149  *
2150  * NAND write with ECC.
2151  */
2152 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2153                              struct mtd_oob_ops *ops)
2154 {
2155         int chipnr, realpage, page, blockmask, column;
2156         struct nand_chip *chip = mtd->priv;
2157         uint32_t writelen = ops->len;
2158
2159         uint32_t oobwritelen = ops->ooblen;
2160         uint32_t oobmaxlen = ops->mode == MTD_OPS_AUTO_OOB ?
2161                                 mtd->oobavail : mtd->oobsize;
2162
2163         uint8_t *oob = ops->oobbuf;
2164         uint8_t *buf = ops->datbuf;
2165         int ret, subpage;
2166         int oob_required = oob ? 1 : 0;
2167
2168         ops->retlen = 0;
2169         if (!writelen)
2170                 return 0;
2171
2172         /* Reject writes, which are not page aligned */
2173         if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2174                 pr_notice("%s: attempt to write non page aligned data\n",
2175                            __func__);
2176                 return -EINVAL;
2177         }
2178
2179         column = to & (mtd->writesize - 1);
2180         subpage = column || (writelen & (mtd->writesize - 1));
2181
2182         if (subpage && oob)
2183                 return -EINVAL;
2184
2185         chipnr = (int)(to >> chip->chip_shift);
2186         chip->select_chip(mtd, chipnr);
2187
2188         /* Check, if it is write protected */
2189         if (nand_check_wp(mtd))
2190                 return -EIO;
2191
2192         realpage = (int)(to >> chip->page_shift);
2193         page = realpage & chip->pagemask;
2194         blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2195
2196         /* Invalidate the page cache, when we write to the cached page */
2197         if (to <= (chip->pagebuf << chip->page_shift) &&
2198             (chip->pagebuf << chip->page_shift) < (to + ops->len))
2199                 chip->pagebuf = -1;
2200
2201         /* Don't allow multipage oob writes with offset */
2202         if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2203                 return -EINVAL;
2204
2205         while (1) {
2206                 int bytes = mtd->writesize;
2207                 int cached = writelen > bytes && page != blockmask;
2208                 uint8_t *wbuf = buf;
2209
2210                 /* Partial page write? */
2211                 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2212                         cached = 0;
2213                         bytes = min_t(int, bytes - column, (int) writelen);
2214                         chip->pagebuf = -1;
2215                         memset(chip->buffers->databuf, 0xff, mtd->writesize);
2216                         memcpy(&chip->buffers->databuf[column], buf, bytes);
2217                         wbuf = chip->buffers->databuf;
2218                 }
2219
2220                 if (unlikely(oob)) {
2221                         size_t len = min(oobwritelen, oobmaxlen);
2222                         oob = nand_fill_oob(mtd, oob, len, ops);
2223                         oobwritelen -= len;
2224                 } else {
2225                         /* We still need to erase leftover OOB data */
2226                         memset(chip->oob_poi, 0xff, mtd->oobsize);
2227                 }
2228
2229                 ret = chip->write_page(mtd, chip, wbuf, oob_required, page,
2230                                        cached, (ops->mode == MTD_OPS_RAW));
2231                 if (ret)
2232                         break;
2233
2234                 writelen -= bytes;
2235                 if (!writelen)
2236                         break;
2237
2238                 column = 0;
2239                 buf += bytes;
2240                 realpage++;
2241
2242                 page = realpage & chip->pagemask;
2243                 /* Check, if we cross a chip boundary */
2244                 if (!page) {
2245                         chipnr++;
2246                         chip->select_chip(mtd, -1);
2247                         chip->select_chip(mtd, chipnr);
2248                 }
2249         }
2250
2251         ops->retlen = ops->len - writelen;
2252         if (unlikely(oob))
2253                 ops->oobretlen = ops->ooblen;
2254         return ret;
2255 }
2256
2257 /**
2258  * panic_nand_write - [MTD Interface] NAND write with ECC
2259  * @mtd: MTD device structure
2260  * @to: offset to write to
2261  * @len: number of bytes to write
2262  * @retlen: pointer to variable to store the number of written bytes
2263  * @buf: the data to write
2264  *
2265  * NAND write with ECC. Used when performing writes in interrupt context, this
2266  * may for example be called by mtdoops when writing an oops while in panic.
2267  */
2268 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2269                             size_t *retlen, const uint8_t *buf)
2270 {
2271         struct nand_chip *chip = mtd->priv;
2272         struct mtd_oob_ops ops;
2273         int ret;
2274
2275         /* Wait for the device to get ready */
2276         panic_nand_wait(mtd, chip, 400);
2277
2278         /* Grab the device */
2279         panic_nand_get_device(chip, mtd, FL_WRITING);
2280
2281         ops.len = len;
2282         ops.datbuf = (uint8_t *)buf;
2283         ops.oobbuf = NULL;
2284         ops.mode = MTD_OPS_PLACE_OOB;
2285
2286         ret = nand_do_write_ops(mtd, to, &ops);
2287
2288         *retlen = ops.retlen;
2289         return ret;
2290 }
2291
2292 /**
2293  * nand_write - [MTD Interface] NAND write with ECC
2294  * @mtd: MTD device structure
2295  * @to: offset to write to
2296  * @len: number of bytes to write
2297  * @retlen: pointer to variable to store the number of written bytes
2298  * @buf: the data to write
2299  *
2300  * NAND write with ECC.
2301  */
2302 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2303                           size_t *retlen, const uint8_t *buf)
2304 {
2305         struct nand_chip *chip = mtd->priv;
2306         struct mtd_oob_ops ops;
2307         int ret;
2308
2309         nand_get_device(chip, mtd, FL_WRITING);
2310         ops.len = len;
2311         ops.datbuf = (uint8_t *)buf;
2312         ops.oobbuf = NULL;
2313         ops.mode = MTD_OPS_PLACE_OOB;
2314         ret = nand_do_write_ops(mtd, to, &ops);
2315         *retlen = ops.retlen;
2316         nand_release_device(mtd);
2317         return ret;
2318 }
2319
2320 /**
2321  * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2322  * @mtd: MTD device structure
2323  * @to: offset to write to
2324  * @ops: oob operation description structure
2325  *
2326  * NAND write out-of-band.
2327  */
2328 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2329                              struct mtd_oob_ops *ops)
2330 {
2331         int chipnr, page, status, len;
2332         struct nand_chip *chip = mtd->priv;
2333
2334         pr_debug("%s: to = 0x%08x, len = %i\n",
2335                          __func__, (unsigned int)to, (int)ops->ooblen);
2336
2337         if (ops->mode == MTD_OPS_AUTO_OOB)
2338                 len = chip->ecc.layout->oobavail;
2339         else
2340                 len = mtd->oobsize;
2341
2342         /* Do not allow write past end of page */
2343         if ((ops->ooboffs + ops->ooblen) > len) {
2344                 pr_debug("%s: attempt to write past end of page\n",
2345                                 __func__);
2346                 return -EINVAL;
2347         }
2348
2349         if (unlikely(ops->ooboffs >= len)) {
2350                 pr_debug("%s: attempt to start write outside oob\n",
2351                                 __func__);
2352                 return -EINVAL;
2353         }
2354
2355         /* Do not allow write past end of device */
2356         if (unlikely(to >= mtd->size ||
2357                      ops->ooboffs + ops->ooblen >
2358                         ((mtd->size >> chip->page_shift) -
2359                          (to >> chip->page_shift)) * len)) {
2360                 pr_debug("%s: attempt to write beyond end of device\n",
2361                                 __func__);
2362                 return -EINVAL;
2363         }
2364
2365         chipnr = (int)(to >> chip->chip_shift);
2366         chip->select_chip(mtd, chipnr);
2367
2368         /* Shift to get page */
2369         page = (int)(to >> chip->page_shift);
2370
2371         /*
2372          * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2373          * of my DiskOnChip 2000 test units) will clear the whole data page too
2374          * if we don't do this. I have no clue why, but I seem to have 'fixed'
2375          * it in the doc2000 driver in August 1999.  dwmw2.
2376          */
2377         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2378
2379         /* Check, if it is write protected */
2380         if (nand_check_wp(mtd))
2381                 return -EROFS;
2382
2383         /* Invalidate the page cache, if we write to the cached page */
2384         if (page == chip->pagebuf)
2385                 chip->pagebuf = -1;
2386
2387         nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2388
2389         if (ops->mode == MTD_OPS_RAW)
2390                 status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
2391         else
2392                 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2393
2394         if (status)
2395                 return status;
2396
2397         ops->oobretlen = ops->ooblen;
2398
2399         return 0;
2400 }
2401
2402 /**
2403  * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2404  * @mtd: MTD device structure
2405  * @to: offset to write to
2406  * @ops: oob operation description structure
2407  */
2408 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2409                           struct mtd_oob_ops *ops)
2410 {
2411         struct nand_chip *chip = mtd->priv;
2412         int ret = -ENOTSUPP;
2413
2414         ops->retlen = 0;
2415
2416         /* Do not allow writes past end of device */
2417         if (ops->datbuf && (to + ops->len) > mtd->size) {
2418                 pr_debug("%s: attempt to write beyond end of device\n",
2419                                 __func__);
2420                 return -EINVAL;
2421         }
2422
2423         nand_get_device(chip, mtd, FL_WRITING);
2424
2425         switch (ops->mode) {
2426         case MTD_OPS_PLACE_OOB:
2427         case MTD_OPS_AUTO_OOB:
2428         case MTD_OPS_RAW:
2429                 break;
2430
2431         default:
2432                 goto out;
2433         }
2434
2435         if (!ops->datbuf)
2436                 ret = nand_do_write_oob(mtd, to, ops);
2437         else
2438                 ret = nand_do_write_ops(mtd, to, ops);
2439
2440 out:
2441         nand_release_device(mtd);
2442         return ret;
2443 }
2444
2445 /**
2446  * single_erase_cmd - [GENERIC] NAND standard block erase command function
2447  * @mtd: MTD device structure
2448  * @page: the page address of the block which will be erased
2449  *
2450  * Standard erase command for NAND chips.
2451  */
2452 static void single_erase_cmd(struct mtd_info *mtd, int page)
2453 {
2454         struct nand_chip *chip = mtd->priv;
2455         /* Send commands to erase a block */
2456         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2457         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2458 }
2459
2460 /**
2461  * multi_erase_cmd - [GENERIC] AND specific block erase command function
2462  * @mtd: MTD device structure
2463  * @page: the page address of the block which will be erased
2464  *
2465  * AND multi block erase command function. Erase 4 consecutive blocks.
2466  */
2467 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2468 {
2469         struct nand_chip *chip = mtd->priv;
2470         /* Send commands to erase a block */
2471         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2472         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2473         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2474         chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2475         chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2476 }
2477
2478 /**
2479  * nand_erase - [MTD Interface] erase block(s)
2480  * @mtd: MTD device structure
2481  * @instr: erase instruction
2482  *
2483  * Erase one ore more blocks.
2484  */
2485 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2486 {
2487         return nand_erase_nand(mtd, instr, 0);
2488 }
2489
2490 #define BBT_PAGE_MASK   0xffffff3f
2491 /**
2492  * nand_erase_nand - [INTERN] erase block(s)
2493  * @mtd: MTD device structure
2494  * @instr: erase instruction
2495  * @allowbbt: allow erasing the bbt area
2496  *
2497  * Erase one ore more blocks.
2498  */
2499 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2500                     int allowbbt)
2501 {
2502         int page, status, pages_per_block, ret, chipnr;
2503         struct nand_chip *chip = mtd->priv;
2504         loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2505         unsigned int bbt_masked_page = 0xffffffff;
2506         loff_t len;
2507
2508         pr_debug("%s: start = 0x%012llx, len = %llu\n",
2509                         __func__, (unsigned long long)instr->addr,
2510                         (unsigned long long)instr->len);
2511
2512         if (check_offs_len(mtd, instr->addr, instr->len))
2513                 return -EINVAL;
2514
2515         /* Grab the lock and see if the device is available */
2516         nand_get_device(chip, mtd, FL_ERASING);
2517
2518         /* Shift to get first page */
2519         page = (int)(instr->addr >> chip->page_shift);
2520         chipnr = (int)(instr->addr >> chip->chip_shift);
2521
2522         /* Calculate pages in each block */
2523         pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2524
2525         /* Select the NAND device */
2526         chip->select_chip(mtd, chipnr);
2527
2528         /* Check, if it is write protected */
2529         if (nand_check_wp(mtd)) {
2530                 pr_debug("%s: device is write protected!\n",
2531                                 __func__);
2532                 instr->state = MTD_ERASE_FAILED;
2533                 goto erase_exit;
2534         }
2535
2536         /*
2537          * If BBT requires refresh, set the BBT page mask to see if the BBT
2538          * should be rewritten. Otherwise the mask is set to 0xffffffff which
2539          * can not be matched. This is also done when the bbt is actually
2540          * erased to avoid recursive updates.
2541          */
2542         if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2543                 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2544
2545         /* Loop through the pages */
2546         len = instr->len;
2547
2548         instr->state = MTD_ERASING;
2549
2550         while (len) {
2551                 /* Check if we have a bad block, we do not erase bad blocks! */
2552                 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2553                                         chip->page_shift, 0, allowbbt)) {
2554                         pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
2555                                     __func__, page);
2556                         instr->state = MTD_ERASE_FAILED;
2557                         goto erase_exit;
2558                 }
2559
2560                 /*
2561                  * Invalidate the page cache, if we erase the block which
2562                  * contains the current cached page.
2563                  */
2564                 if (page <= chip->pagebuf && chip->pagebuf <
2565                     (page + pages_per_block))
2566                         chip->pagebuf = -1;
2567
2568                 chip->erase_cmd(mtd, page & chip->pagemask);
2569
2570                 status = chip->waitfunc(mtd, chip);
2571
2572                 /*
2573                  * See if operation failed and additional status checks are
2574                  * available
2575                  */
2576                 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2577                         status = chip->errstat(mtd, chip, FL_ERASING,
2578                                                status, page);
2579
2580                 /* See if block erase succeeded */
2581                 if (status & NAND_STATUS_FAIL) {
2582                         pr_debug("%s: failed erase, page 0x%08x\n",
2583                                         __func__, page);
2584                         instr->state = MTD_ERASE_FAILED;
2585                         instr->fail_addr =
2586                                 ((loff_t)page << chip->page_shift);
2587                         goto erase_exit;
2588                 }
2589
2590                 /*
2591                  * If BBT requires refresh, set the BBT rewrite flag to the
2592                  * page being erased.
2593                  */
2594                 if (bbt_masked_page != 0xffffffff &&
2595                     (page & BBT_PAGE_MASK) == bbt_masked_page)
2596                             rewrite_bbt[chipnr] =
2597                                         ((loff_t)page << chip->page_shift);
2598
2599                 /* Increment page address and decrement length */
2600                 len -= (1 << chip->phys_erase_shift);
2601                 page += pages_per_block;
2602
2603                 /* Check, if we cross a chip boundary */
2604                 if (len && !(page & chip->pagemask)) {
2605                         chipnr++;
2606                         chip->select_chip(mtd, -1);
2607                         chip->select_chip(mtd, chipnr);
2608
2609                         /*
2610                          * If BBT requires refresh and BBT-PERCHIP, set the BBT
2611                          * page mask to see if this BBT should be rewritten.
2612                          */
2613                         if (bbt_masked_page != 0xffffffff &&
2614                             (chip->bbt_td->options & NAND_BBT_PERCHIP))
2615                                 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2616                                         BBT_PAGE_MASK;
2617                 }
2618         }
2619         instr->state = MTD_ERASE_DONE;
2620
2621 erase_exit:
2622
2623         ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2624
2625         /* Deselect and wake up anyone waiting on the device */
2626         nand_release_device(mtd);
2627
2628         /* Do call back function */
2629         if (!ret)
2630                 mtd_erase_callback(instr);
2631
2632         /*
2633          * If BBT requires refresh and erase was successful, rewrite any
2634          * selected bad block tables.
2635          */
2636         if (bbt_masked_page == 0xffffffff || ret)
2637                 return ret;
2638
2639         for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2640                 if (!rewrite_bbt[chipnr])
2641                         continue;
2642                 /* Update the BBT for chip */
2643                 pr_debug("%s: nand_update_bbt (%d:0x%0llx 0x%0x)\n",
2644                                 __func__, chipnr, rewrite_bbt[chipnr],
2645                                 chip->bbt_td->pages[chipnr]);
2646                 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2647         }
2648
2649         /* Return more or less happy */
2650         return ret;
2651 }
2652
2653 /**
2654  * nand_sync - [MTD Interface] sync
2655  * @mtd: MTD device structure
2656  *
2657  * Sync is actually a wait for chip ready function.
2658  */
2659 static void nand_sync(struct mtd_info *mtd)
2660 {
2661         struct nand_chip *chip = mtd->priv;
2662
2663         pr_debug("%s: called\n", __func__);
2664
2665         /* Grab the lock and see if the device is available */
2666         nand_get_device(chip, mtd, FL_SYNCING);
2667         /* Release it and go back */
2668         nand_release_device(mtd);
2669 }
2670
2671 /**
2672  * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2673  * @mtd: MTD device structure
2674  * @offs: offset relative to mtd start
2675  */
2676 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2677 {
2678         return nand_block_checkbad(mtd, offs, 1, 0);
2679 }
2680
2681 /**
2682  * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2683  * @mtd: MTD device structure
2684  * @ofs: offset relative to mtd start
2685  */
2686 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2687 {
2688         struct nand_chip *chip = mtd->priv;
2689         int ret;
2690
2691         ret = nand_block_isbad(mtd, ofs);
2692         if (ret) {
2693                 /* If it was bad already, return success and do nothing */
2694                 if (ret > 0)
2695                         return 0;
2696                 return ret;
2697         }
2698
2699         return chip->block_markbad(mtd, ofs);
2700 }
2701
2702 /**
2703  * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
2704  * @mtd: MTD device structure
2705  * @chip: nand chip info structure
2706  * @addr: feature address.
2707  * @subfeature_param: the subfeature parameters, a four bytes array.
2708  */
2709 static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
2710                         int addr, uint8_t *subfeature_param)
2711 {
2712         int status;
2713
2714         if (!chip->onfi_version)
2715                 return -EINVAL;
2716
2717         chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
2718         chip->write_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2719         status = chip->waitfunc(mtd, chip);
2720         if (status & NAND_STATUS_FAIL)
2721                 return -EIO;
2722         return 0;
2723 }
2724
2725 /**
2726  * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
2727  * @mtd: MTD device structure
2728  * @chip: nand chip info structure
2729  * @addr: feature address.
2730  * @subfeature_param: the subfeature parameters, a four bytes array.
2731  */
2732 static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
2733                         int addr, uint8_t *subfeature_param)
2734 {
2735         if (!chip->onfi_version)
2736                 return -EINVAL;
2737
2738         /* clear the sub feature parameters */
2739         memset(subfeature_param, 0, ONFI_SUBFEATURE_PARAM_LEN);
2740
2741         chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
2742         chip->read_buf(mtd, subfeature_param, ONFI_SUBFEATURE_PARAM_LEN);
2743         return 0;
2744 }
2745
2746 /**
2747  * nand_suspend - [MTD Interface] Suspend the NAND flash
2748  * @mtd: MTD device structure
2749  */
2750 static int nand_suspend(struct mtd_info *mtd)
2751 {
2752         struct nand_chip *chip = mtd->priv;
2753
2754         return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2755 }
2756
2757 /**
2758  * nand_resume - [MTD Interface] Resume the NAND flash
2759  * @mtd: MTD device structure
2760  */
2761 static void nand_resume(struct mtd_info *mtd)
2762 {
2763         struct nand_chip *chip = mtd->priv;
2764
2765         if (chip->state == FL_PM_SUSPENDED)
2766                 nand_release_device(mtd);
2767         else
2768                 pr_err("%s called for a chip which is not in suspended state\n",
2769                         __func__);
2770 }
2771
2772 /* Set default functions */
2773 static void nand_set_defaults(struct nand_chip *chip, int busw)
2774 {
2775         /* check for proper chip_delay setup, set 20us if not */
2776         if (!chip->chip_delay)
2777                 chip->chip_delay = 20;
2778
2779         /* check, if a user supplied command function given */
2780         if (chip->cmdfunc == NULL)
2781                 chip->cmdfunc = nand_command;
2782
2783         /* check, if a user supplied wait function given */
2784         if (chip->waitfunc == NULL)
2785                 chip->waitfunc = nand_wait;
2786
2787         if (!chip->select_chip)
2788                 chip->select_chip = nand_select_chip;
2789         if (!chip->read_byte)
2790                 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2791         if (!chip->read_word)
2792                 chip->read_word = nand_read_word;
2793         if (!chip->block_bad)
2794                 chip->block_bad = nand_block_bad;
2795         if (!chip->block_markbad)
2796                 chip->block_markbad = nand_default_block_markbad;
2797         if (!chip->write_buf)
2798                 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2799         if (!chip->read_buf)
2800                 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2801         if (!chip->scan_bbt)
2802                 chip->scan_bbt = nand_default_bbt;
2803
2804         if (!chip->controller) {
2805                 chip->controller = &chip->hwcontrol;
2806                 spin_lock_init(&chip->controller->lock);
2807                 init_waitqueue_head(&chip->controller->wq);
2808         }
2809
2810 }
2811
2812 /* Sanitize ONFI strings so we can safely print them */
2813 static void sanitize_string(uint8_t *s, size_t len)
2814 {
2815         ssize_t i;
2816
2817         /* Null terminate */
2818         s[len - 1] = 0;
2819
2820         /* Remove non printable chars */
2821         for (i = 0; i < len - 1; i++) {
2822                 if (s[i] < ' ' || s[i] > 127)
2823                         s[i] = '?';
2824         }
2825
2826         /* Remove trailing spaces */
2827         strim(s);
2828 }
2829
2830 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2831 {
2832         int i;
2833         while (len--) {
2834                 crc ^= *p++ << 8;
2835                 for (i = 0; i < 8; i++)
2836                         crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2837         }
2838
2839         return crc;
2840 }
2841
2842 /*
2843  * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
2844  */
2845 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2846                                         int *busw)
2847 {
2848         struct nand_onfi_params *p = &chip->onfi_params;
2849         int i;
2850         int val;
2851
2852         /* Try ONFI for unknown chip or LP */
2853         chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2854         if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2855                 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2856                 return 0;
2857
2858         chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2859         for (i = 0; i < 3; i++) {
2860                 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2861                 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2862                                 le16_to_cpu(p->crc)) {
2863                         pr_info("ONFI param page %d valid\n", i);
2864                         break;
2865                 }
2866         }
2867
2868         if (i == 3)
2869                 return 0;
2870
2871         /* Check version */
2872         val = le16_to_cpu(p->revision);
2873         if (val & (1 << 5))
2874                 chip->onfi_version = 23;
2875         else if (val & (1 << 4))
2876                 chip->onfi_version = 22;
2877         else if (val & (1 << 3))
2878                 chip->onfi_version = 21;
2879         else if (val & (1 << 2))
2880                 chip->onfi_version = 20;
2881         else if (val & (1 << 1))
2882                 chip->onfi_version = 10;
2883         else
2884                 chip->onfi_version = 0;
2885
2886         if (!chip->onfi_version) {
2887                 pr_info("%s: unsupported ONFI version: %d\n", __func__, val);
2888                 return 0;
2889         }
2890
2891         sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2892         sanitize_string(p->model, sizeof(p->model));
2893         if (!mtd->name)
2894                 mtd->name = p->model;
2895         mtd->writesize = le32_to_cpu(p->byte_per_page);
2896         mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2897         mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2898         chip->chipsize = le32_to_cpu(p->blocks_per_lun);
2899         chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
2900         *busw = 0;
2901         if (le16_to_cpu(p->features) & 1)
2902                 *busw = NAND_BUSWIDTH_16;
2903
2904         pr_info("ONFI flash detected\n");
2905         return 1;
2906 }
2907
2908 /*
2909  * nand_id_has_period - Check if an ID string has a given wraparound period
2910  * @id_data: the ID string
2911  * @arrlen: the length of the @id_data array
2912  * @period: the period of repitition
2913  *
2914  * Check if an ID string is repeated within a given sequence of bytes at
2915  * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
2916  * period of 2). This is a helper function for nand_id_len(). Returns non-zero
2917  * if the repetition has a period of @period; otherwise, returns zero.
2918  */
2919 static int nand_id_has_period(u8 *id_data, int arrlen, int period)
2920 {
2921         int i, j;
2922         for (i = 0; i < period; i++)
2923                 for (j = i + period; j < arrlen; j += period)
2924                         if (id_data[i] != id_data[j])
2925                                 return 0;
2926         return 1;
2927 }
2928
2929 /*
2930  * nand_id_len - Get the length of an ID string returned by CMD_READID
2931  * @id_data: the ID string
2932  * @arrlen: the length of the @id_data array
2933
2934  * Returns the length of the ID string, according to known wraparound/trailing
2935  * zero patterns. If no pattern exists, returns the length of the array.
2936  */
2937 static int nand_id_len(u8 *id_data, int arrlen)
2938 {
2939         int last_nonzero, period;
2940
2941         /* Find last non-zero byte */
2942         for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
2943                 if (id_data[last_nonzero])
2944                         break;
2945
2946         /* All zeros */
2947         if (last_nonzero < 0)
2948                 return 0;
2949
2950         /* Calculate wraparound period */
2951         for (period = 1; period < arrlen; period++)
2952                 if (nand_id_has_period(id_data, arrlen, period))
2953                         break;
2954
2955         /* There's a repeated pattern */
2956         if (period < arrlen)
2957                 return period;
2958
2959         /* There are trailing zeros */
2960         if (last_nonzero < arrlen - 1)
2961                 return last_nonzero + 1;
2962
2963         /* No pattern detected */
2964         return arrlen;
2965 }
2966
2967 /*
2968  * Many new NAND share similar device ID codes, which represent the size of the
2969  * chip. The rest of the parameters must be decoded according to generic or
2970  * manufacturer-specific "extended ID" decoding patterns.
2971  */
2972 static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
2973                                 u8 id_data[8], int *busw)
2974 {
2975         int extid, id_len;
2976         /* The 3rd id byte holds MLC / multichip data */
2977         chip->cellinfo = id_data[2];
2978         /* The 4th id byte is the important one */
2979         extid = id_data[3];
2980
2981         id_len = nand_id_len(id_data, 8);
2982
2983         /*
2984          * Field definitions are in the following datasheets:
2985          * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2986          * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
2987          * Hynix MLC   (6 byte ID): Hynix H27UBG8T2B (p.22)
2988          *
2989          * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
2990          * ID to decide what to do.
2991          */
2992         if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
2993                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
2994                         id_data[5] != 0x00) {
2995                 /* Calc pagesize */
2996                 mtd->writesize = 2048 << (extid & 0x03);
2997                 extid >>= 2;
2998                 /* Calc oobsize */
2999                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3000                 case 1:
3001                         mtd->oobsize = 128;
3002                         break;
3003                 case 2:
3004                         mtd->oobsize = 218;
3005                         break;
3006                 case 3:
3007                         mtd->oobsize = 400;
3008                         break;
3009                 case 4:
3010                         mtd->oobsize = 436;
3011                         break;
3012                 case 5:
3013                         mtd->oobsize = 512;
3014                         break;
3015                 case 6:
3016                 default: /* Other cases are "reserved" (unknown) */
3017                         mtd->oobsize = 640;
3018                         break;
3019                 }
3020                 extid >>= 2;
3021                 /* Calc blocksize */
3022                 mtd->erasesize = (128 * 1024) <<
3023                         (((extid >> 1) & 0x04) | (extid & 0x03));
3024                 *busw = 0;
3025         } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
3026                         (chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3027                 unsigned int tmp;
3028
3029                 /* Calc pagesize */
3030                 mtd->writesize = 2048 << (extid & 0x03);
3031                 extid >>= 2;
3032                 /* Calc oobsize */
3033                 switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
3034                 case 0:
3035                         mtd->oobsize = 128;
3036                         break;
3037                 case 1:
3038                         mtd->oobsize = 224;
3039                         break;
3040                 case 2:
3041                         mtd->oobsize = 448;
3042                         break;
3043                 case 3:
3044                         mtd->oobsize = 64;
3045                         break;
3046                 case 4:
3047                         mtd->oobsize = 32;
3048                         break;
3049                 case 5:
3050                         mtd->oobsize = 16;
3051                         break;
3052                 default:
3053                         mtd->oobsize = 640;
3054                         break;
3055                 }
3056                 extid >>= 2;
3057                 /* Calc blocksize */
3058                 tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
3059                 if (tmp < 0x03)
3060                         mtd->erasesize = (128 * 1024) << tmp;
3061                 else if (tmp == 0x03)
3062                         mtd->erasesize = 768 * 1024;
3063                 else
3064                         mtd->erasesize = (64 * 1024) << tmp;
3065                 *busw = 0;
3066         } else {
3067                 /* Calc pagesize */
3068                 mtd->writesize = 1024 << (extid & 0x03);
3069                 extid >>= 2;
3070                 /* Calc oobsize */
3071                 mtd->oobsize = (8 << (extid & 0x01)) *
3072                         (mtd->writesize >> 9);
3073                 extid >>= 2;
3074                 /* Calc blocksize. Blocksize is multiples of 64KiB */
3075                 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3076                 extid >>= 2;
3077                 /* Get buswidth information */
3078                 *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3079         }
3080 }
3081
3082 /*
3083  * Old devices have chip data hardcoded in the device ID table. nand_decode_id
3084  * decodes a matching ID table entry and assigns the MTD size parameters for
3085  * the chip.
3086  */
3087 static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
3088                                 struct nand_flash_dev *type, u8 id_data[8],
3089                                 int *busw)
3090 {
3091         int maf_id = id_data[0];
3092
3093         mtd->erasesize = type->erasesize;
3094         mtd->writesize = type->pagesize;
3095         mtd->oobsize = mtd->writesize / 32;
3096         *busw = type->options & NAND_BUSWIDTH_16;
3097
3098         /*
3099          * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3100          * some Spansion chips have erasesize that conflicts with size
3101          * listed in nand_ids table.
3102          * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3103          */
3104         if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
3105                         && id_data[6] == 0x00 && id_data[7] == 0x00
3106                         && mtd->writesize == 512) {
3107                 mtd->erasesize = 128 * 1024;
3108                 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3109         }
3110 }
3111
3112 /*
3113  * Set the bad block marker/indicator (BBM/BBI) patterns according to some
3114  * heuristic patterns using various detected parameters (e.g., manufacturer,
3115  * page size, cell-type information).
3116  */
3117 static void nand_decode_bbm_options(struct mtd_info *mtd,
3118                                     struct nand_chip *chip, u8 id_data[8])
3119 {
3120         int maf_id = id_data[0];
3121
3122         /* Set the bad block position */
3123         if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
3124                 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3125         else
3126                 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3127
3128         /*
3129          * Bad block marker is stored in the last page of each block on Samsung
3130          * and Hynix MLC devices; stored in first two pages of each block on
3131          * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
3132          * AMD/Spansion, and Macronix.  All others scan only the first page.
3133          */
3134         if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3135                         (maf_id == NAND_MFR_SAMSUNG ||
3136                          maf_id == NAND_MFR_HYNIX))
3137                 chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
3138         else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3139                                 (maf_id == NAND_MFR_SAMSUNG ||
3140                                  maf_id == NAND_MFR_HYNIX ||
3141                                  maf_id == NAND_MFR_TOSHIBA ||
3142                                  maf_id == NAND_MFR_AMD ||
3143                                  maf_id == NAND_MFR_MACRONIX)) ||
3144                         (mtd->writesize == 2048 &&
3145                          maf_id == NAND_MFR_MICRON))
3146                 chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
3147 }
3148
3149 /*
3150  * Get the flash and manufacturer id and lookup if the type is supported.
3151  */
3152 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
3153                                                   struct nand_chip *chip,
3154                                                   int busw,
3155                                                   int *maf_id, int *dev_id,
3156                                                   struct nand_flash_dev *type)
3157 {
3158         int i, maf_idx;
3159         u8 id_data[8];
3160
3161         /* Select the device */
3162         chip->select_chip(mtd, 0);
3163
3164         /*
3165          * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3166          * after power-up.
3167          */
3168         chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3169
3170         /* Send the command for reading device ID */
3171         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3172
3173         /* Read manufacturer and device IDs */
3174         *maf_id = chip->read_byte(mtd);
3175         *dev_id = chip->read_byte(mtd);
3176
3177         /*
3178          * Try again to make sure, as some systems the bus-hold or other
3179          * interface concerns can cause random data which looks like a
3180          * possibly credible NAND flash to appear. If the two results do
3181          * not match, ignore the device completely.
3182          */
3183
3184         chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3185
3186         /* Read entire ID string */
3187         for (i = 0; i < 8; i++)
3188                 id_data[i] = chip->read_byte(mtd);
3189
3190         if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
3191                 pr_info("%s: second ID read did not match "
3192                         "%02x,%02x against %02x,%02x\n", __func__,
3193                         *maf_id, *dev_id, id_data[0], id_data[1]);
3194                 return ERR_PTR(-ENODEV);
3195         }
3196
3197         if (!type)
3198                 type = nand_flash_ids;
3199
3200         for (; type->name != NULL; type++)
3201                 if (*dev_id == type->id)
3202                         break;
3203
3204         chip->onfi_version = 0;
3205         if (!type->name || !type->pagesize) {
3206                 /* Check is chip is ONFI compliant */
3207                 if (nand_flash_detect_onfi(mtd, chip, &busw))
3208                         goto ident_done;
3209         }
3210
3211         if (!type->name)
3212                 return ERR_PTR(-ENODEV);
3213
3214         if (!mtd->name)
3215                 mtd->name = type->name;
3216
3217         chip->chipsize = (uint64_t)type->chipsize << 20;
3218
3219         if (!type->pagesize && chip->init_size) {
3220                 /* Set the pagesize, oobsize, erasesize by the driver */
3221                 busw = chip->init_size(mtd, chip, id_data);
3222         } else if (!type->pagesize) {
3223                 /* Decode parameters from extended ID */
3224                 nand_decode_ext_id(mtd, chip, id_data, &busw);
3225         } else {
3226                 nand_decode_id(mtd, chip, type, id_data, &busw);
3227         }
3228         /* Get chip options */
3229         chip->options |= type->options;
3230
3231         /*
3232          * Check if chip is not a Samsung device. Do not clear the
3233          * options for chips which do not have an extended id.
3234          */
3235         if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3236                 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3237 ident_done:
3238
3239         /* Try to identify manufacturer */
3240         for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3241                 if (nand_manuf_ids[maf_idx].id == *maf_id)
3242                         break;
3243         }
3244
3245         /*
3246          * Check, if buswidth is correct. Hardware drivers should set
3247          * chip correct!
3248          */
3249         if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3250                 pr_info("NAND device: Manufacturer ID:"
3251                         " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3252                         *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3253                 pr_warn("NAND bus width %d instead %d bit\n",
3254                            (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3255                            busw ? 16 : 8);
3256                 return ERR_PTR(-EINVAL);
3257         }
3258
3259         nand_decode_bbm_options(mtd, chip, id_data);
3260
3261         /* Calculate the address shift from the page size */
3262         chip->page_shift = ffs(mtd->writesize) - 1;
3263         /* Convert chipsize to number of pages per chip -1 */
3264         chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3265
3266         chip->bbt_erase_shift = chip->phys_erase_shift =
3267                 ffs(mtd->erasesize) - 1;
3268         if (chip->chipsize & 0xffffffff)
3269                 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3270         else {
3271                 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3272                 chip->chip_shift += 32 - 1;
3273         }
3274
3275         chip->badblockbits = 8;
3276
3277         /* Check for AND chips with 4 page planes */
3278         if (chip->options & NAND_4PAGE_ARRAY)
3279                 chip->erase_cmd = multi_erase_cmd;
3280         else
3281                 chip->erase_cmd = single_erase_cmd;
3282
3283         /* Do not replace user supplied command function! */
3284         if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3285                 chip->cmdfunc = nand_command_lp;
3286
3287         pr_info("NAND device: Manufacturer ID: 0x%02x, Chip ID: 0x%02x (%s %s),"
3288                 " page size: %d, OOB size: %d\n",
3289                 *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
3290                 chip->onfi_version ? chip->onfi_params.model : type->name,
3291                 mtd->writesize, mtd->oobsize);
3292
3293         return type;
3294 }
3295
3296 /**
3297  * nand_scan_ident - [NAND Interface] Scan for the NAND device
3298  * @mtd: MTD device structure
3299  * @maxchips: number of chips to scan for
3300  * @table: alternative NAND ID table
3301  *
3302  * This is the first phase of the normal nand_scan() function. It reads the
3303  * flash ID and sets up MTD fields accordingly.
3304  *
3305  * The mtd->owner field must be set to the module of the caller.
3306  */
3307 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3308                     struct nand_flash_dev *table)
3309 {
3310         int i, busw, nand_maf_id, nand_dev_id;
3311         struct nand_chip *chip = mtd->priv;
3312         struct nand_flash_dev *type;
3313
3314         /* Get buswidth to select the correct functions */
3315         busw = chip->options & NAND_BUSWIDTH_16;
3316         /* Set the default functions */
3317         nand_set_defaults(chip, busw);
3318
3319         /* Read the flash type */
3320         type = nand_get_flash_type(mtd, chip, busw,
3321                                 &nand_maf_id, &nand_dev_id, table);
3322
3323         if (IS_ERR(type)) {
3324                 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3325                         pr_warn("No NAND device found\n");
3326                 chip->select_chip(mtd, -1);
3327                 return PTR_ERR(type);
3328         }
3329
3330         /* Check for a chip array */
3331         for (i = 1; i < maxchips; i++) {
3332                 chip->select_chip(mtd, i);
3333                 /* See comment in nand_get_flash_type for reset */
3334                 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3335                 /* Send the command for reading device ID */
3336                 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3337                 /* Read manufacturer and device IDs */
3338                 if (nand_maf_id != chip->read_byte(mtd) ||
3339                     nand_dev_id != chip->read_byte(mtd))
3340                         break;
3341         }
3342         if (i > 1)
3343                 pr_info("%d NAND chips detected\n", i);
3344
3345         /* Store the number of chips and calc total size for mtd */
3346         chip->numchips = i;
3347         mtd->size = i * chip->chipsize;
3348
3349         return 0;
3350 }
3351 EXPORT_SYMBOL(nand_scan_ident);
3352
3353
3354 /**
3355  * nand_scan_tail - [NAND Interface] Scan for the NAND device
3356  * @mtd: MTD device structure
3357  *
3358  * This is the second phase of the normal nand_scan() function. It fills out
3359  * all the uninitialized function pointers with the defaults and scans for a
3360  * bad block table if appropriate.
3361  */
3362 int nand_scan_tail(struct mtd_info *mtd)
3363 {
3364         int i;
3365         struct nand_chip *chip = mtd->priv;
3366
3367         /* New bad blocks should be marked in OOB, flash-based BBT, or both */
3368         BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
3369                         !(chip->bbt_options & NAND_BBT_USE_FLASH));
3370
3371         if (!(chip->options & NAND_OWN_BUFFERS))
3372                 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3373         if (!chip->buffers)
3374                 return -ENOMEM;
3375
3376         /* Set the internal oob buffer location, just after the page data */
3377         chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3378
3379         /*
3380          * If no default placement scheme is given, select an appropriate one.
3381          */
3382         if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3383                 switch (mtd->oobsize) {
3384                 case 8:
3385                         chip->ecc.layout = &nand_oob_8;
3386                         break;
3387                 case 16:
3388                         chip->ecc.layout = &nand_oob_16;
3389                         break;
3390                 case 64:
3391                         chip->ecc.layout = &nand_oob_64;
3392                         break;
3393                 case 128:
3394                         chip->ecc.layout = &nand_oob_128;
3395                         break;
3396                 default:
3397                         pr_warn("No oob scheme defined for oobsize %d\n",
3398                                    mtd->oobsize);
3399                         BUG();
3400                 }
3401         }
3402
3403         if (!chip->write_page)
3404                 chip->write_page = nand_write_page;
3405
3406         /* set for ONFI nand */
3407         if (!chip->onfi_set_features)
3408                 chip->onfi_set_features = nand_onfi_set_features;
3409         if (!chip->onfi_get_features)
3410                 chip->onfi_get_features = nand_onfi_get_features;
3411
3412         /*
3413          * Check ECC mode, default to software if 3byte/512byte hardware ECC is
3414          * selected and we have 256 byte pagesize fallback to software ECC
3415          */
3416
3417         switch (chip->ecc.mode) {
3418         case NAND_ECC_HW_OOB_FIRST:
3419                 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3420                 if (!chip->ecc.calculate || !chip->ecc.correct ||
3421                      !chip->ecc.hwctl) {
3422                         pr_warn("No ECC functions supplied; "
3423                                    "hardware ECC not possible\n");
3424                         BUG();
3425                 }
3426                 if (!chip->ecc.read_page)
3427                         chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3428
3429         case NAND_ECC_HW:
3430                 /* Use standard hwecc read page function? */
3431                 if (!chip->ecc.read_page)
3432                         chip->ecc.read_page = nand_read_page_hwecc;
3433                 if (!chip->ecc.write_page)
3434                         chip->ecc.write_page = nand_write_page_hwecc;
3435                 if (!chip->ecc.read_page_raw)
3436                         chip->ecc.read_page_raw = nand_read_page_raw;
3437                 if (!chip->ecc.write_page_raw)
3438                         chip->ecc.write_page_raw = nand_write_page_raw;
3439                 if (!chip->ecc.read_oob)
3440                         chip->ecc.read_oob = nand_read_oob_std;
3441                 if (!chip->ecc.write_oob)
3442                         chip->ecc.write_oob = nand_write_oob_std;
3443
3444         case NAND_ECC_HW_SYNDROME:
3445                 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3446                      !chip->ecc.hwctl) &&
3447                     (!chip->ecc.read_page ||
3448                      chip->ecc.read_page == nand_read_page_hwecc ||
3449                      !chip->ecc.write_page ||
3450                      chip->ecc.write_page == nand_write_page_hwecc)) {
3451                         pr_warn("No ECC functions supplied; "
3452                                    "hardware ECC not possible\n");
3453                         BUG();
3454                 }
3455                 /* Use standard syndrome read/write page function? */
3456                 if (!chip->ecc.read_page)
3457                         chip->ecc.read_page = nand_read_page_syndrome;
3458                 if (!chip->ecc.write_page)
3459                         chip->ecc.write_page = nand_write_page_syndrome;
3460                 if (!chip->ecc.read_page_raw)
3461                         chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3462                 if (!chip->ecc.write_page_raw)
3463                         chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3464                 if (!chip->ecc.read_oob)
3465                         chip->ecc.read_oob = nand_read_oob_syndrome;
3466                 if (!chip->ecc.write_oob)
3467                         chip->ecc.write_oob = nand_write_oob_syndrome;
3468
3469                 if (mtd->writesize >= chip->ecc.size) {
3470                         if (!chip->ecc.strength) {
3471                                 pr_warn("Driver must set ecc.strength when using hardware ECC\n");
3472                                 BUG();
3473                         }
3474                         break;
3475                 }
3476                 pr_warn("%d byte HW ECC not possible on "
3477                            "%d byte page size, fallback to SW ECC\n",
3478                            chip->ecc.size, mtd->writesize);
3479                 chip->ecc.mode = NAND_ECC_SOFT;
3480
3481         case NAND_ECC_SOFT:
3482                 chip->ecc.calculate = nand_calculate_ecc;
3483                 chip->ecc.correct = nand_correct_data;
3484                 chip->ecc.read_page = nand_read_page_swecc;
3485                 chip->ecc.read_subpage = nand_read_subpage;
3486                 chip->ecc.write_page = nand_write_page_swecc;
3487                 chip->ecc.read_page_raw = nand_read_page_raw;
3488                 chip->ecc.write_page_raw = nand_write_page_raw;
3489                 chip->ecc.read_oob = nand_read_oob_std;
3490                 chip->ecc.write_oob = nand_write_oob_std;
3491                 if (!chip->ecc.size)
3492                         chip->ecc.size = 256;
3493                 chip->ecc.bytes = 3;
3494                 chip->ecc.strength = 1;
3495                 break;
3496
3497         case NAND_ECC_SOFT_BCH:
3498                 if (!mtd_nand_has_bch()) {
3499                         pr_warn("CONFIG_MTD_ECC_BCH not enabled\n");
3500                         BUG();
3501                 }
3502                 chip->ecc.calculate = nand_bch_calculate_ecc;
3503                 chip->ecc.correct = nand_bch_correct_data;
3504                 chip->ecc.read_page = nand_read_page_swecc;
3505                 chip->ecc.read_subpage = nand_read_subpage;
3506                 chip->ecc.write_page = nand_write_page_swecc;
3507                 chip->ecc.read_page_raw = nand_read_page_raw;
3508                 chip->ecc.write_page_raw = nand_write_page_raw;
3509                 chip->ecc.read_oob = nand_read_oob_std;
3510                 chip->ecc.write_oob = nand_write_oob_std;
3511                 /*
3512                  * Board driver should supply ecc.size and ecc.bytes values to
3513                  * select how many bits are correctable; see nand_bch_init()
3514                  * for details. Otherwise, default to 4 bits for large page
3515                  * devices.
3516                  */
3517                 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3518                         chip->ecc.size = 512;
3519                         chip->ecc.bytes = 7;
3520                 }
3521                 chip->ecc.priv = nand_bch_init(mtd,
3522                                                chip->ecc.size,
3523                                                chip->ecc.bytes,
3524                                                &chip->ecc.layout);
3525                 if (!chip->ecc.priv) {
3526                         pr_warn("BCH ECC initialization failed!\n");
3527                         BUG();
3528                 }
3529                 chip->ecc.strength =
3530                         chip->ecc.bytes * 8 / fls(8 * chip->ecc.size);
3531                 break;
3532
3533         case NAND_ECC_NONE:
3534                 pr_warn("NAND_ECC_NONE selected by board driver. "
3535                            "This is not recommended!\n");
3536                 chip->ecc.read_page = nand_read_page_raw;
3537                 chip->ecc.write_page = nand_write_page_raw;
3538                 chip->ecc.read_oob = nand_read_oob_std;
3539                 chip->ecc.read_page_raw = nand_read_page_raw;
3540                 chip->ecc.write_page_raw = nand_write_page_raw;
3541                 chip->ecc.write_oob = nand_write_oob_std;
3542                 chip->ecc.size = mtd->writesize;
3543                 chip->ecc.bytes = 0;
3544                 chip->ecc.strength = 0;
3545                 break;
3546
3547         default:
3548                 pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
3549                 BUG();
3550         }
3551
3552         /* For many systems, the standard OOB write also works for raw */
3553         if (!chip->ecc.read_oob_raw)
3554                 chip->ecc.read_oob_raw = chip->ecc.read_oob;
3555         if (!chip->ecc.write_oob_raw)
3556                 chip->ecc.write_oob_raw = chip->ecc.write_oob;
3557
3558         /*
3559          * The number of bytes available for a client to place data into
3560          * the out of band area.
3561          */
3562         chip->ecc.layout->oobavail = 0;
3563         for (i = 0; chip->ecc.layout->oobfree[i].length
3564                         && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3565                 chip->ecc.layout->oobavail +=
3566                         chip->ecc.layout->oobfree[i].length;
3567         mtd->oobavail = chip->ecc.layout->oobavail;
3568
3569         /*
3570          * Set the number of read / write steps for one page depending on ECC
3571          * mode.
3572          */
3573         chip->ecc.steps = mtd->writesize / chip->ecc.size;
3574         if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3575                 pr_warn("Invalid ECC parameters\n");
3576                 BUG();
3577         }
3578         chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3579
3580         /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
3581         if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3582             !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3583                 switch (chip->ecc.steps) {
3584                 case 2:
3585                         mtd->subpage_sft = 1;
3586                         break;
3587                 case 4:
3588                 case 8:
3589                 case 16:
3590                         mtd->subpage_sft = 2;
3591                         break;
3592                 }
3593         }
3594         chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3595
3596         /* Initialize state */
3597         chip->state = FL_READY;
3598
3599         /* De-select the device */
3600         chip->select_chip(mtd, -1);
3601
3602         /* Invalidate the pagebuffer reference */
3603         chip->pagebuf = -1;
3604
3605         /* Large page NAND with SOFT_ECC should support subpage reads */
3606         if ((chip->ecc.mode == NAND_ECC_SOFT) && (chip->page_shift > 9))
3607                 chip->options |= NAND_SUBPAGE_READ;
3608
3609         /* Fill in remaining MTD driver data */
3610         mtd->type = MTD_NANDFLASH;
3611         mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3612                                                 MTD_CAP_NANDFLASH;
3613         mtd->_erase = nand_erase;
3614         mtd->_point = NULL;
3615         mtd->_unpoint = NULL;
3616         mtd->_read = nand_read;
3617         mtd->_write = nand_write;
3618         mtd->_panic_write = panic_nand_write;
3619         mtd->_read_oob = nand_read_oob;
3620         mtd->_write_oob = nand_write_oob;
3621         mtd->_sync = nand_sync;
3622         mtd->_lock = NULL;
3623         mtd->_unlock = NULL;
3624         mtd->_suspend = nand_suspend;
3625         mtd->_resume = nand_resume;
3626         mtd->_block_isbad = nand_block_isbad;
3627         mtd->_block_markbad = nand_block_markbad;
3628         mtd->writebufsize = mtd->writesize;
3629
3630         /* propagate ecc info to mtd_info */
3631         mtd->ecclayout = chip->ecc.layout;
3632         mtd->ecc_strength = chip->ecc.strength;
3633         /*
3634          * Initialize bitflip_threshold to its default prior scan_bbt() call.
3635          * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
3636          * properly set.
3637          */
3638         if (!mtd->bitflip_threshold)
3639                 mtd->bitflip_threshold = mtd->ecc_strength;
3640
3641         /* Check, if we should skip the bad block table scan */
3642         if (chip->options & NAND_SKIP_BBTSCAN)
3643                 return 0;
3644
3645         /* Build bad block table */
3646         return chip->scan_bbt(mtd);
3647 }
3648 EXPORT_SYMBOL(nand_scan_tail);
3649
3650 /*
3651  * is_module_text_address() isn't exported, and it's mostly a pointless
3652  * test if this is a module _anyway_ -- they'd have to try _really_ hard
3653  * to call us from in-kernel code if the core NAND support is modular.
3654  */
3655 #ifdef MODULE
3656 #define caller_is_module() (1)
3657 #else
3658 #define caller_is_module() \
3659         is_module_text_address((unsigned long)__builtin_return_address(0))
3660 #endif
3661
3662 /**
3663  * nand_scan - [NAND Interface] Scan for the NAND device
3664  * @mtd: MTD device structure
3665  * @maxchips: number of chips to scan for
3666  *
3667  * This fills out all the uninitialized function pointers with the defaults.
3668  * The flash ID is read and the mtd/chip structures are filled with the
3669  * appropriate values. The mtd->owner field must be set to the module of the
3670  * caller.
3671  */
3672 int nand_scan(struct mtd_info *mtd, int maxchips)
3673 {
3674         int ret;
3675
3676         /* Many callers got this wrong, so check for it for a while... */
3677         if (!mtd->owner && caller_is_module()) {
3678                 pr_crit("%s called with NULL mtd->owner!\n", __func__);
3679                 BUG();
3680         }
3681
3682         ret = nand_scan_ident(mtd, maxchips, NULL);
3683         if (!ret)
3684                 ret = nand_scan_tail(mtd);
3685         return ret;
3686 }
3687 EXPORT_SYMBOL(nand_scan);
3688
3689 /**
3690  * nand_release - [NAND Interface] Free resources held by the NAND device
3691  * @mtd: MTD device structure
3692  */
3693 void nand_release(struct mtd_info *mtd)
3694 {
3695         struct nand_chip *chip = mtd->priv;
3696
3697         if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3698                 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3699
3700         mtd_device_unregister(mtd);
3701
3702         /* Free bad block table memory */
3703         kfree(chip->bbt);
3704         if (!(chip->options & NAND_OWN_BUFFERS))
3705                 kfree(chip->buffers);
3706
3707         /* Free bad block descriptor memory */
3708         if (chip->badblock_pattern && chip->badblock_pattern->options
3709                         & NAND_BBT_DYNAMICSTRUCT)
3710                 kfree(chip->badblock_pattern);
3711 }
3712 EXPORT_SYMBOL_GPL(nand_release);
3713
3714 static int __init nand_base_init(void)
3715 {
3716         led_trigger_register_simple("nand-disk", &nand_led_trigger);
3717         return 0;
3718 }
3719
3720 static void __exit nand_base_exit(void)
3721 {
3722         led_trigger_unregister_simple(nand_led_trigger);
3723 }
3724
3725 module_init(nand_base_init);
3726 module_exit(nand_base_exit);
3727
3728 MODULE_LICENSE("GPL");
3729 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3730 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3731 MODULE_DESCRIPTION("Generic NAND flash driver code");