2 * drivers/mtd/nand/fsmc_nand.c
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
12 * Based on drivers/mtd/nand/nomadik_nand.c
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
35 #include <linux/mtd/partitions.h>
37 #include <linux/slab.h>
38 #include <linux/mtd/fsmc.h>
39 #include <linux/amba/bus.h>
40 #include <mtd/mtd-abi.h>
42 static struct nand_ecclayout fsmc_ecc1_128_layout = {
44 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
45 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
47 {.offset = 8, .length = 8},
48 {.offset = 24, .length = 8},
49 {.offset = 40, .length = 8},
50 {.offset = 56, .length = 8},
51 {.offset = 72, .length = 8},
52 {.offset = 88, .length = 8},
53 {.offset = 104, .length = 8},
54 {.offset = 120, .length = 8}
58 static struct nand_ecclayout fsmc_ecc1_64_layout = {
60 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
62 {.offset = 8, .length = 8},
63 {.offset = 24, .length = 8},
64 {.offset = 40, .length = 8},
65 {.offset = 56, .length = 8},
69 static struct nand_ecclayout fsmc_ecc1_16_layout = {
73 {.offset = 8, .length = 8},
78 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80 * bytes are free for use.
82 static struct nand_ecclayout fsmc_ecc4_256_layout = {
84 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85 9, 10, 11, 12, 13, 14,
86 18, 19, 20, 21, 22, 23, 24,
87 25, 26, 27, 28, 29, 30,
88 34, 35, 36, 37, 38, 39, 40,
89 41, 42, 43, 44, 45, 46,
90 50, 51, 52, 53, 54, 55, 56,
91 57, 58, 59, 60, 61, 62,
92 66, 67, 68, 69, 70, 71, 72,
93 73, 74, 75, 76, 77, 78,
94 82, 83, 84, 85, 86, 87, 88,
95 89, 90, 91, 92, 93, 94,
96 98, 99, 100, 101, 102, 103, 104,
97 105, 106, 107, 108, 109, 110,
98 114, 115, 116, 117, 118, 119, 120,
99 121, 122, 123, 124, 125, 126,
100 130, 131, 132, 133, 134, 135, 136,
101 137, 138, 139, 140, 141, 142,
102 146, 147, 148, 149, 150, 151, 152,
103 153, 154, 155, 156, 157, 158,
104 162, 163, 164, 165, 166, 167, 168,
105 169, 170, 171, 172, 173, 174,
106 178, 179, 180, 181, 182, 183, 184,
107 185, 186, 187, 188, 189, 190,
108 194, 195, 196, 197, 198, 199, 200,
109 201, 202, 203, 204, 205, 206,
110 210, 211, 212, 213, 214, 215, 216,
111 217, 218, 219, 220, 221, 222,
112 226, 227, 228, 229, 230, 231, 232,
113 233, 234, 235, 236, 237, 238,
114 242, 243, 244, 245, 246, 247, 248,
115 249, 250, 251, 252, 253, 254
118 {.offset = 15, .length = 3},
119 {.offset = 31, .length = 3},
120 {.offset = 47, .length = 3},
121 {.offset = 63, .length = 3},
122 {.offset = 79, .length = 3},
123 {.offset = 95, .length = 3},
124 {.offset = 111, .length = 3},
125 {.offset = 127, .length = 3},
126 {.offset = 143, .length = 3},
127 {.offset = 159, .length = 3},
128 {.offset = 175, .length = 3},
129 {.offset = 191, .length = 3},
130 {.offset = 207, .length = 3},
131 {.offset = 223, .length = 3},
132 {.offset = 239, .length = 3},
133 {.offset = 255, .length = 1}
138 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140 * bytes are free for use.
142 static struct nand_ecclayout fsmc_ecc4_224_layout = {
144 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145 9, 10, 11, 12, 13, 14,
146 18, 19, 20, 21, 22, 23, 24,
147 25, 26, 27, 28, 29, 30,
148 34, 35, 36, 37, 38, 39, 40,
149 41, 42, 43, 44, 45, 46,
150 50, 51, 52, 53, 54, 55, 56,
151 57, 58, 59, 60, 61, 62,
152 66, 67, 68, 69, 70, 71, 72,
153 73, 74, 75, 76, 77, 78,
154 82, 83, 84, 85, 86, 87, 88,
155 89, 90, 91, 92, 93, 94,
156 98, 99, 100, 101, 102, 103, 104,
157 105, 106, 107, 108, 109, 110,
158 114, 115, 116, 117, 118, 119, 120,
159 121, 122, 123, 124, 125, 126
162 {.offset = 15, .length = 3},
163 {.offset = 31, .length = 3},
164 {.offset = 47, .length = 3},
165 {.offset = 63, .length = 3},
166 {.offset = 79, .length = 3},
167 {.offset = 95, .length = 3},
168 {.offset = 111, .length = 3},
169 {.offset = 127, .length = 97}
174 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176 * bytes are free for use.
178 static struct nand_ecclayout fsmc_ecc4_128_layout = {
180 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
181 9, 10, 11, 12, 13, 14,
182 18, 19, 20, 21, 22, 23, 24,
183 25, 26, 27, 28, 29, 30,
184 34, 35, 36, 37, 38, 39, 40,
185 41, 42, 43, 44, 45, 46,
186 50, 51, 52, 53, 54, 55, 56,
187 57, 58, 59, 60, 61, 62,
188 66, 67, 68, 69, 70, 71, 72,
189 73, 74, 75, 76, 77, 78,
190 82, 83, 84, 85, 86, 87, 88,
191 89, 90, 91, 92, 93, 94,
192 98, 99, 100, 101, 102, 103, 104,
193 105, 106, 107, 108, 109, 110,
194 114, 115, 116, 117, 118, 119, 120,
195 121, 122, 123, 124, 125, 126
198 {.offset = 15, .length = 3},
199 {.offset = 31, .length = 3},
200 {.offset = 47, .length = 3},
201 {.offset = 63, .length = 3},
202 {.offset = 79, .length = 3},
203 {.offset = 95, .length = 3},
204 {.offset = 111, .length = 3},
205 {.offset = 127, .length = 1}
210 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212 * bytes are free for use.
214 static struct nand_ecclayout fsmc_ecc4_64_layout = {
216 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217 9, 10, 11, 12, 13, 14,
218 18, 19, 20, 21, 22, 23, 24,
219 25, 26, 27, 28, 29, 30,
220 34, 35, 36, 37, 38, 39, 40,
221 41, 42, 43, 44, 45, 46,
222 50, 51, 52, 53, 54, 55, 56,
223 57, 58, 59, 60, 61, 62,
226 {.offset = 15, .length = 3},
227 {.offset = 31, .length = 3},
228 {.offset = 47, .length = 3},
229 {.offset = 63, .length = 1},
234 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236 * byte is free for use.
238 static struct nand_ecclayout fsmc_ecc4_16_layout = {
240 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241 9, 10, 11, 12, 13, 14
244 {.offset = 15, .length = 1},
249 * ECC placement definitions in oobfree type format.
250 * There are 13 bytes of ecc for every 512 byte block and it has to be read
251 * consecutively and immediately after the 512 byte data block for hardware to
252 * generate the error bit offsets in 512 byte data.
253 * Managing the ecc bytes in the following way makes it easier for software to
254 * read ecc bytes consecutive to data bytes. This way is similar to
255 * oobfree structure maintained already in generic nand driver
257 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
259 {.offset = 2, .length = 13},
260 {.offset = 18, .length = 13},
261 {.offset = 34, .length = 13},
262 {.offset = 50, .length = 13},
263 {.offset = 66, .length = 13},
264 {.offset = 82, .length = 13},
265 {.offset = 98, .length = 13},
266 {.offset = 114, .length = 13}
270 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
272 {.offset = 0, .length = 4},
273 {.offset = 6, .length = 9}
278 * struct fsmc_nand_data - structure for FSMC NAND device state
280 * @pid: Part ID on the AMBA PrimeCell format
281 * @mtd: MTD info for a NAND flash.
282 * @nand: Chip related info for a NAND flash.
283 * @partitions: Partition info for a NAND Flash.
284 * @nr_partitions: Total number of partition of a NAND flash.
286 * @ecc_place: ECC placing locations in oobfree type format.
287 * @bank: Bank number for probed device.
288 * @clk: Clock structure for FSMC.
290 * @read_dma_chan: DMA channel for read access
291 * @write_dma_chan: DMA channel for write access to NAND
292 * @dma_access_complete: Completion structure
294 * @data_pa: NAND Physical port for Data.
295 * @data_va: NAND port for Data.
296 * @cmd_va: NAND port for Command.
297 * @addr_va: NAND port for Address.
298 * @regs_va: FSMC regs base address.
300 struct fsmc_nand_data {
303 struct nand_chip nand;
304 struct mtd_partition *partitions;
305 unsigned int nr_partitions;
307 struct fsmc_eccplace *ecc_place;
310 enum access_mode mode;
313 /* DMA related objects */
314 struct dma_chan *read_dma_chan;
315 struct dma_chan *write_dma_chan;
316 struct completion dma_access_complete;
318 struct fsmc_nand_timings *dev_timings;
321 void __iomem *data_va;
322 void __iomem *cmd_va;
323 void __iomem *addr_va;
324 void __iomem *regs_va;
326 void (*select_chip)(uint32_t bank, uint32_t busw);
329 /* Assert CS signal based on chipnr */
330 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
332 struct nand_chip *chip = mtd->priv;
333 struct fsmc_nand_data *host;
335 host = container_of(mtd, struct fsmc_nand_data, mtd);
339 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
345 if (host->select_chip)
346 host->select_chip(chipnr,
347 chip->options & NAND_BUSWIDTH_16);
356 * fsmc_cmd_ctrl - For facilitaing Hardware access
357 * This routine allows hardware specific access to control-lines(ALE,CLE)
359 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
361 struct nand_chip *this = mtd->priv;
362 struct fsmc_nand_data *host = container_of(mtd,
363 struct fsmc_nand_data, mtd);
364 void __iomem *regs = host->regs_va;
365 unsigned int bank = host->bank;
367 if (ctrl & NAND_CTRL_CHANGE) {
370 if (ctrl & NAND_CLE) {
371 this->IO_ADDR_R = host->cmd_va;
372 this->IO_ADDR_W = host->cmd_va;
373 } else if (ctrl & NAND_ALE) {
374 this->IO_ADDR_R = host->addr_va;
375 this->IO_ADDR_W = host->addr_va;
377 this->IO_ADDR_R = host->data_va;
378 this->IO_ADDR_W = host->data_va;
381 pc = readl(FSMC_NAND_REG(regs, bank, PC));
386 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
391 if (cmd != NAND_CMD_NONE)
392 writeb_relaxed(cmd, this->IO_ADDR_W);
396 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
398 * This routine initializes timing parameters related to NAND memory access in
401 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
402 uint32_t busw, struct fsmc_nand_timings *timings)
404 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
405 uint32_t tclr, tar, thiz, thold, twait, tset;
406 struct fsmc_nand_timings *tims;
407 struct fsmc_nand_timings default_timings = {
411 .thold = FSMC_THOLD_4,
412 .twait = FSMC_TWAIT_6,
419 tims = &default_timings;
421 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
429 writel_relaxed(value | FSMC_DEVWID_16,
430 FSMC_NAND_REG(regs, bank, PC));
432 writel_relaxed(value | FSMC_DEVWID_8,
433 FSMC_NAND_REG(regs, bank, PC));
435 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
436 FSMC_NAND_REG(regs, bank, PC));
437 writel_relaxed(thiz | thold | twait | tset,
438 FSMC_NAND_REG(regs, bank, COMM));
439 writel_relaxed(thiz | thold | twait | tset,
440 FSMC_NAND_REG(regs, bank, ATTRIB));
444 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
446 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
448 struct fsmc_nand_data *host = container_of(mtd,
449 struct fsmc_nand_data, mtd);
450 void __iomem *regs = host->regs_va;
451 uint32_t bank = host->bank;
453 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
454 FSMC_NAND_REG(regs, bank, PC));
455 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
456 FSMC_NAND_REG(regs, bank, PC));
457 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
458 FSMC_NAND_REG(regs, bank, PC));
462 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
463 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
466 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
469 struct fsmc_nand_data *host = container_of(mtd,
470 struct fsmc_nand_data, mtd);
471 void __iomem *regs = host->regs_va;
472 uint32_t bank = host->bank;
474 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
477 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
481 } while (!time_after_eq(jiffies, deadline));
483 if (time_after_eq(jiffies, deadline)) {
484 dev_err(host->dev, "calculate ecc timed out\n");
488 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
489 ecc[0] = (uint8_t) (ecc_tmp >> 0);
490 ecc[1] = (uint8_t) (ecc_tmp >> 8);
491 ecc[2] = (uint8_t) (ecc_tmp >> 16);
492 ecc[3] = (uint8_t) (ecc_tmp >> 24);
494 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
495 ecc[4] = (uint8_t) (ecc_tmp >> 0);
496 ecc[5] = (uint8_t) (ecc_tmp >> 8);
497 ecc[6] = (uint8_t) (ecc_tmp >> 16);
498 ecc[7] = (uint8_t) (ecc_tmp >> 24);
500 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
501 ecc[8] = (uint8_t) (ecc_tmp >> 0);
502 ecc[9] = (uint8_t) (ecc_tmp >> 8);
503 ecc[10] = (uint8_t) (ecc_tmp >> 16);
504 ecc[11] = (uint8_t) (ecc_tmp >> 24);
506 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
507 ecc[12] = (uint8_t) (ecc_tmp >> 16);
513 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
514 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
517 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
520 struct fsmc_nand_data *host = container_of(mtd,
521 struct fsmc_nand_data, mtd);
522 void __iomem *regs = host->regs_va;
523 uint32_t bank = host->bank;
526 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
527 ecc[0] = (uint8_t) (ecc_tmp >> 0);
528 ecc[1] = (uint8_t) (ecc_tmp >> 8);
529 ecc[2] = (uint8_t) (ecc_tmp >> 16);
534 /* Count the number of 0's in buff upto a max of max_bits */
535 static int count_written_bits(uint8_t *buff, int size, int max_bits)
537 int k, written_bits = 0;
539 for (k = 0; k < size; k++) {
540 written_bits += hweight8(~buff[k]);
541 if (written_bits > max_bits)
548 static void dma_complete(void *param)
550 struct fsmc_nand_data *host = param;
552 complete(&host->dma_access_complete);
555 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
556 enum dma_data_direction direction)
558 struct dma_chan *chan;
559 struct dma_device *dma_dev;
560 struct dma_async_tx_descriptor *tx;
561 dma_addr_t dma_dst, dma_src, dma_addr;
563 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
566 if (direction == DMA_TO_DEVICE)
567 chan = host->write_dma_chan;
568 else if (direction == DMA_FROM_DEVICE)
569 chan = host->read_dma_chan;
573 dma_dev = chan->device;
574 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
576 if (direction == DMA_TO_DEVICE) {
578 dma_dst = host->data_pa;
580 dma_src = host->data_pa;
584 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
587 dev_err(host->dev, "device_prep_dma_memcpy error\n");
592 tx->callback = dma_complete;
593 tx->callback_param = host;
594 cookie = tx->tx_submit(tx);
596 ret = dma_submit_error(cookie);
598 dev_err(host->dev, "dma_submit_error %d\n", cookie);
602 dma_async_issue_pending(chan);
605 wait_for_completion_timeout(&host->dma_access_complete,
606 msecs_to_jiffies(3000));
608 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
609 dev_err(host->dev, "wait_for_completion_timeout\n");
618 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
624 * fsmc_write_buf - write buffer to chip
625 * @mtd: MTD device structure
627 * @len: number of bytes to write
629 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
632 struct nand_chip *chip = mtd->priv;
634 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
635 IS_ALIGNED(len, sizeof(uint32_t))) {
636 uint32_t *p = (uint32_t *)buf;
638 for (i = 0; i < len; i++)
639 writel_relaxed(p[i], chip->IO_ADDR_W);
641 for (i = 0; i < len; i++)
642 writeb_relaxed(buf[i], chip->IO_ADDR_W);
647 * fsmc_read_buf - read chip data into buffer
648 * @mtd: MTD device structure
649 * @buf: buffer to store date
650 * @len: number of bytes to read
652 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
655 struct nand_chip *chip = mtd->priv;
657 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
658 IS_ALIGNED(len, sizeof(uint32_t))) {
659 uint32_t *p = (uint32_t *)buf;
661 for (i = 0; i < len; i++)
662 p[i] = readl_relaxed(chip->IO_ADDR_R);
664 for (i = 0; i < len; i++)
665 buf[i] = readb_relaxed(chip->IO_ADDR_R);
670 * fsmc_read_buf_dma - read chip data into buffer
671 * @mtd: MTD device structure
672 * @buf: buffer to store date
673 * @len: number of bytes to read
675 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
677 struct fsmc_nand_data *host;
679 host = container_of(mtd, struct fsmc_nand_data, mtd);
680 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
684 * fsmc_write_buf_dma - write buffer to chip
685 * @mtd: MTD device structure
687 * @len: number of bytes to write
689 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
692 struct fsmc_nand_data *host;
694 host = container_of(mtd, struct fsmc_nand_data, mtd);
695 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
699 * fsmc_read_page_hwecc
700 * @mtd: mtd info structure
701 * @chip: nand chip info structure
702 * @buf: buffer to store read data
703 * @oob_required: caller expects OOB data read to chip->oob_poi
704 * @page: page number to read
706 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
707 * performed in a strict sequence as follows:
708 * data(512 byte) -> ecc(13 byte)
709 * After this read, fsmc hardware generates and reports error data bits(up to a
712 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
713 uint8_t *buf, int oob_required, int page)
715 struct fsmc_nand_data *host = container_of(mtd,
716 struct fsmc_nand_data, mtd);
717 struct fsmc_eccplace *ecc_place = host->ecc_place;
718 int i, j, s, stat, eccsize = chip->ecc.size;
719 int eccbytes = chip->ecc.bytes;
720 int eccsteps = chip->ecc.steps;
722 uint8_t *ecc_calc = chip->buffers->ecccalc;
723 uint8_t *ecc_code = chip->buffers->ecccode;
724 int off, len, group = 0;
726 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
727 * end up reading 14 bytes (7 words) from oob. The local array is
728 * to maintain word alignment
731 uint8_t *oob = (uint8_t *)&ecc_oob[0];
732 unsigned int max_bitflips = 0;
734 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
735 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
736 chip->ecc.hwctl(mtd, NAND_ECC_READ);
737 chip->read_buf(mtd, p, eccsize);
739 for (j = 0; j < eccbytes;) {
740 off = ecc_place->eccplace[group].offset;
741 len = ecc_place->eccplace[group].length;
745 * length is intentionally kept a higher multiple of 2
746 * to read at least 13 bytes even in case of 16 bit NAND
749 if (chip->options & NAND_BUSWIDTH_16)
750 len = roundup(len, 2);
752 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
753 chip->read_buf(mtd, oob + j, len);
757 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
758 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
760 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
762 mtd->ecc_stats.failed++;
764 mtd->ecc_stats.corrected += stat;
765 max_bitflips = max_t(unsigned int, max_bitflips, stat);
773 * fsmc_bch8_correct_data
774 * @mtd: mtd info structure
775 * @dat: buffer of read data
776 * @read_ecc: ecc read from device spare area
777 * @calc_ecc: ecc calculated from read data
779 * calc_ecc is a 104 bit information containing maximum of 8 error
780 * offset informations of 13 bits each in 512 bytes of read data.
782 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
783 uint8_t *read_ecc, uint8_t *calc_ecc)
785 struct fsmc_nand_data *host = container_of(mtd,
786 struct fsmc_nand_data, mtd);
787 struct nand_chip *chip = mtd->priv;
788 void __iomem *regs = host->regs_va;
789 unsigned int bank = host->bank;
792 uint32_t ecc1, ecc2, ecc3, ecc4;
794 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
796 /* no bit flipping */
797 if (likely(num_err == 0))
800 /* too many errors */
801 if (unlikely(num_err > 8)) {
803 * This is a temporary erase check. A newly erased page read
804 * would result in an ecc error because the oob data is also
805 * erased to FF and the calculated ecc for an FF data is not
807 * This is a workaround to skip performing correction in case
811 * For every page, each bit written as 0 is counted until these
812 * number of bits are greater than 8 (the maximum correction
813 * capability of FSMC for each 512 + 13 bytes)
816 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
817 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
819 if ((bits_ecc + bits_data) <= 8) {
821 memset(dat, 0xff, chip->ecc.size);
829 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
830 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
832 * calc_ecc is a 104 bit information containing maximum of 8 error
833 * offset informations of 13 bits each. calc_ecc is copied into a
834 * uint64_t array and error offset indexes are populated in err_idx
837 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
838 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
839 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
840 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
842 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
843 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
844 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
845 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
846 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
847 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
848 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
849 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
853 change_bit(0, (unsigned long *)&err_idx[i]);
854 change_bit(1, (unsigned long *)&err_idx[i]);
856 if (err_idx[i] < chip->ecc.size * 8) {
857 change_bit(err_idx[i], (unsigned long *)dat);
864 static bool filter(struct dma_chan *chan, void *slave)
866 chan->private = slave;
871 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
872 struct device_node *np)
874 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
877 /* Set default NAND width to 8 bits */
879 if (!of_property_read_u32(np, "bank-width", &val)) {
882 } else if (val != 1) {
883 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
887 if (of_get_property(np, "nand-skip-bbtscan", NULL))
888 pdata->options = NAND_SKIP_BBTSCAN;
890 pdata->nand_timings = devm_kzalloc(&pdev->dev,
891 sizeof(*pdata->nand_timings), GFP_KERNEL);
892 if (!pdata->nand_timings) {
893 dev_err(&pdev->dev, "no memory for nand_timing\n");
896 of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
897 sizeof(*pdata->nand_timings));
899 /* Set default NAND bank to 0 */
901 if (!of_property_read_u32(np, "bank", &val)) {
903 dev_err(&pdev->dev, "invalid bank %u\n", val);
911 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
912 struct device_node *np)
919 * fsmc_nand_probe - Probe function
920 * @pdev: platform device structure
922 static int __init fsmc_nand_probe(struct platform_device *pdev)
924 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
925 struct device_node __maybe_unused *np = pdev->dev.of_node;
926 struct mtd_part_parser_data ppdata = {};
927 struct fsmc_nand_data *host;
928 struct mtd_info *mtd;
929 struct nand_chip *nand;
930 struct resource *res;
937 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
938 pdev->dev.platform_data = pdata;
939 ret = fsmc_nand_probe_config_dt(pdev, np);
941 dev_err(&pdev->dev, "no platform data\n");
947 dev_err(&pdev->dev, "platform data is NULL\n");
951 /* Allocate memory for the device structure (and zero it) */
952 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
954 dev_err(&pdev->dev, "failed to allocate device structure\n");
958 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
959 host->data_va = devm_ioremap_resource(&pdev->dev, res);
960 if (IS_ERR(host->data_va))
961 return PTR_ERR(host->data_va);
963 host->data_pa = (dma_addr_t)res->start;
965 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
966 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
967 if (IS_ERR(host->addr_va))
968 return PTR_ERR(host->addr_va);
970 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
971 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
972 if (IS_ERR(host->cmd_va))
973 return PTR_ERR(host->cmd_va);
975 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
976 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
977 if (IS_ERR(host->regs_va))
978 return PTR_ERR(host->regs_va);
980 host->clk = clk_get(&pdev->dev, NULL);
981 if (IS_ERR(host->clk)) {
982 dev_err(&pdev->dev, "failed to fetch block clock\n");
983 return PTR_ERR(host->clk);
986 ret = clk_prepare_enable(host->clk);
988 goto err_clk_prepare_enable;
991 * This device ID is actually a common AMBA ID as used on the
992 * AMBA PrimeCell bus. However it is not a PrimeCell.
994 for (pid = 0, i = 0; i < 4; i++)
995 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
997 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
998 "revision %02x, config %02x\n",
999 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
1000 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
1002 host->bank = pdata->bank;
1003 host->select_chip = pdata->select_bank;
1004 host->partitions = pdata->partitions;
1005 host->nr_partitions = pdata->nr_partitions;
1006 host->dev = &pdev->dev;
1007 host->dev_timings = pdata->nand_timings;
1008 host->mode = pdata->mode;
1010 if (host->mode == USE_DMA_ACCESS)
1011 init_completion(&host->dma_access_complete);
1013 /* Link all private pointers */
1019 host->mtd.owner = THIS_MODULE;
1020 nand->IO_ADDR_R = host->data_va;
1021 nand->IO_ADDR_W = host->data_va;
1022 nand->cmd_ctrl = fsmc_cmd_ctrl;
1023 nand->chip_delay = 30;
1025 nand->ecc.mode = NAND_ECC_HW;
1026 nand->ecc.hwctl = fsmc_enable_hwecc;
1027 nand->ecc.size = 512;
1028 nand->options = pdata->options;
1029 nand->select_chip = fsmc_select_chip;
1030 nand->badblockbits = 7;
1032 if (pdata->width == FSMC_NAND_BW16)
1033 nand->options |= NAND_BUSWIDTH_16;
1035 switch (host->mode) {
1036 case USE_DMA_ACCESS:
1038 dma_cap_set(DMA_MEMCPY, mask);
1039 host->read_dma_chan = dma_request_channel(mask, filter,
1040 pdata->read_dma_priv);
1041 if (!host->read_dma_chan) {
1042 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1043 goto err_req_read_chnl;
1045 host->write_dma_chan = dma_request_channel(mask, filter,
1046 pdata->write_dma_priv);
1047 if (!host->write_dma_chan) {
1048 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1049 goto err_req_write_chnl;
1051 nand->read_buf = fsmc_read_buf_dma;
1052 nand->write_buf = fsmc_write_buf_dma;
1056 case USE_WORD_ACCESS:
1057 nand->read_buf = fsmc_read_buf;
1058 nand->write_buf = fsmc_write_buf;
1062 fsmc_nand_setup(host->regs_va, host->bank,
1063 nand->options & NAND_BUSWIDTH_16,
1066 if (AMBA_REV_BITS(host->pid) >= 8) {
1067 nand->ecc.read_page = fsmc_read_page_hwecc;
1068 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1069 nand->ecc.correct = fsmc_bch8_correct_data;
1070 nand->ecc.bytes = 13;
1071 nand->ecc.strength = 8;
1073 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1074 nand->ecc.correct = nand_correct_data;
1075 nand->ecc.bytes = 3;
1076 nand->ecc.strength = 1;
1080 * Scan to find existence of the device
1082 if (nand_scan_ident(&host->mtd, 1, NULL)) {
1084 dev_err(&pdev->dev, "No NAND Device found!\n");
1085 goto err_scan_ident;
1088 if (AMBA_REV_BITS(host->pid) >= 8) {
1089 switch (host->mtd.oobsize) {
1091 nand->ecc.layout = &fsmc_ecc4_16_layout;
1092 host->ecc_place = &fsmc_ecc4_sp_place;
1095 nand->ecc.layout = &fsmc_ecc4_64_layout;
1096 host->ecc_place = &fsmc_ecc4_lp_place;
1099 nand->ecc.layout = &fsmc_ecc4_128_layout;
1100 host->ecc_place = &fsmc_ecc4_lp_place;
1103 nand->ecc.layout = &fsmc_ecc4_224_layout;
1104 host->ecc_place = &fsmc_ecc4_lp_place;
1107 nand->ecc.layout = &fsmc_ecc4_256_layout;
1108 host->ecc_place = &fsmc_ecc4_lp_place;
1111 printk(KERN_WARNING "No oob scheme defined for "
1112 "oobsize %d\n", mtd->oobsize);
1116 switch (host->mtd.oobsize) {
1118 nand->ecc.layout = &fsmc_ecc1_16_layout;
1121 nand->ecc.layout = &fsmc_ecc1_64_layout;
1124 nand->ecc.layout = &fsmc_ecc1_128_layout;
1127 printk(KERN_WARNING "No oob scheme defined for "
1128 "oobsize %d\n", mtd->oobsize);
1133 /* Second stage of scan to fill MTD data-structures */
1134 if (nand_scan_tail(&host->mtd)) {
1140 * The partition information can is accessed by (in the same precedence)
1142 * command line through Bootloader,
1144 * default partition information present in driver.
1147 * Check for partition info passed
1149 host->mtd.name = "nand";
1150 ppdata.of_node = np;
1151 ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
1152 host->partitions, host->nr_partitions);
1156 platform_set_drvdata(pdev, host);
1157 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1162 if (host->mode == USE_DMA_ACCESS)
1163 dma_release_channel(host->write_dma_chan);
1165 if (host->mode == USE_DMA_ACCESS)
1166 dma_release_channel(host->read_dma_chan);
1168 clk_disable_unprepare(host->clk);
1169 err_clk_prepare_enable:
1177 static int fsmc_nand_remove(struct platform_device *pdev)
1179 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1182 nand_release(&host->mtd);
1184 if (host->mode == USE_DMA_ACCESS) {
1185 dma_release_channel(host->write_dma_chan);
1186 dma_release_channel(host->read_dma_chan);
1188 clk_disable_unprepare(host->clk);
1195 #ifdef CONFIG_PM_SLEEP
1196 static int fsmc_nand_suspend(struct device *dev)
1198 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1200 clk_disable_unprepare(host->clk);
1204 static int fsmc_nand_resume(struct device *dev)
1206 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1208 clk_prepare_enable(host->clk);
1209 fsmc_nand_setup(host->regs_va, host->bank,
1210 host->nand.options & NAND_BUSWIDTH_16,
1217 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1220 static const struct of_device_id fsmc_nand_id_table[] = {
1221 { .compatible = "st,spear600-fsmc-nand" },
1222 { .compatible = "stericsson,fsmc-nand" },
1225 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1228 static struct platform_driver fsmc_nand_driver = {
1229 .remove = fsmc_nand_remove,
1231 .owner = THIS_MODULE,
1232 .name = "fsmc-nand",
1233 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1234 .pm = &fsmc_nand_pm_ops,
1238 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1240 MODULE_LICENSE("GPL");
1241 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1242 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");