2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
4 * Copyright © 2006 Texas Instruments.
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/err.h>
31 #include <linux/clk.h>
33 #include <linux/mtd/nand.h>
34 #include <linux/mtd/partitions.h>
36 #include <mach/nand.h>
38 #include <asm/mach-types.h>
42 * This is a device driver for the NAND flash controller found on the
43 * various DaVinci family chips. It handles up to four SoC chipselects,
44 * and some flavors of secondary chipselect (e.g. based on A12) as used
45 * with multichip packages.
47 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
48 * available on chips like the DM355 and OMAP-L137 and needed with the
49 * more error-prone MLC NAND chips.
51 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
52 * outputs in a "wire-AND" configuration, with no per-chip signals.
54 struct davinci_nand_info {
56 struct nand_chip chip;
57 struct nand_ecclayout ecclayout;
71 uint32_t mask_chipsel;
75 uint32_t core_chipsel;
78 static DEFINE_SPINLOCK(davinci_nand_lock);
79 static bool ecc4_busy;
81 #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
84 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
87 return __raw_readl(info->base + offset);
90 static inline void davinci_nand_writel(struct davinci_nand_info *info,
91 int offset, unsigned long value)
93 __raw_writel(value, info->base + offset);
96 /*----------------------------------------------------------------------*/
99 * Access to hardware control lines: ALE, CLE, secondary chipselect.
102 static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
105 struct davinci_nand_info *info = to_davinci_nand(mtd);
106 uint32_t addr = info->current_cs;
107 struct nand_chip *nand = mtd->priv;
109 /* Did the control lines change? */
110 if (ctrl & NAND_CTRL_CHANGE) {
111 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
112 addr |= info->mask_cle;
113 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
114 addr |= info->mask_ale;
116 nand->IO_ADDR_W = (void __iomem __force *)addr;
119 if (cmd != NAND_CMD_NONE)
120 iowrite8(cmd, nand->IO_ADDR_W);
123 static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
125 struct davinci_nand_info *info = to_davinci_nand(mtd);
126 uint32_t addr = info->ioaddr;
128 /* maybe kick in a second chipselect */
130 addr |= info->mask_chipsel;
131 info->current_cs = addr;
133 info->chip.IO_ADDR_W = (void __iomem __force *)addr;
134 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
137 /*----------------------------------------------------------------------*/
140 * 1-bit hardware ECC ... context maintained for each core chipselect
143 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
145 struct davinci_nand_info *info = to_davinci_nand(mtd);
147 return davinci_nand_readl(info, NANDF1ECC_OFFSET
148 + 4 * info->core_chipsel);
151 static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
153 struct davinci_nand_info *info;
157 info = to_davinci_nand(mtd);
159 /* Reset ECC hardware */
160 nand_davinci_readecc_1bit(mtd);
162 spin_lock_irqsave(&davinci_nand_lock, flags);
164 /* Restart ECC hardware */
165 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
166 nandcfr |= BIT(8 + info->core_chipsel);
167 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
169 spin_unlock_irqrestore(&davinci_nand_lock, flags);
173 * Read hardware ECC value and pack into three bytes
175 static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
176 const u_char *dat, u_char *ecc_code)
178 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
179 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
181 /* invert so that erased block ecc is correct */
183 ecc_code[0] = (u_char)(ecc24);
184 ecc_code[1] = (u_char)(ecc24 >> 8);
185 ecc_code[2] = (u_char)(ecc24 >> 16);
190 static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
191 u_char *read_ecc, u_char *calc_ecc)
193 struct nand_chip *chip = mtd->priv;
194 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
196 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
198 uint32_t diff = eccCalc ^ eccNand;
201 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
202 /* Correctable error */
203 if ((diff >> (12 + 3)) < chip->ecc.size) {
204 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
209 } else if (!(diff & (diff - 1))) {
210 /* Single bit ECC error in the ECC itself,
214 /* Uncorrectable error */
222 /*----------------------------------------------------------------------*/
225 * 4-bit hardware ECC ... context maintained over entire AEMIF
227 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
228 * since that forces use of a problematic "infix OOB" layout.
229 * Among other things, it trashes manufacturer bad block markers.
230 * Also, and specific to this hardware, it ECC-protects the "prepad"
231 * in the OOB ... while having ECC protection for parts of OOB would
232 * seem useful, the current MTD stack sometimes wants to update the
233 * OOB without recomputing ECC.
236 static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
238 struct davinci_nand_info *info = to_davinci_nand(mtd);
242 spin_lock_irqsave(&davinci_nand_lock, flags);
244 /* Start 4-bit ECC calculation for read/write */
245 val = davinci_nand_readl(info, NANDFCR_OFFSET);
247 val |= (info->core_chipsel << 4) | BIT(12);
248 davinci_nand_writel(info, NANDFCR_OFFSET, val);
250 info->is_readmode = (mode == NAND_ECC_READ);
252 spin_unlock_irqrestore(&davinci_nand_lock, flags);
255 /* Read raw ECC code after writing to NAND. */
257 nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
259 const u32 mask = 0x03ff03ff;
261 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
262 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
263 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
264 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
267 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
268 static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
269 const u_char *dat, u_char *ecc_code)
271 struct davinci_nand_info *info = to_davinci_nand(mtd);
275 /* After a read, terminate ECC calculation by a dummy read
276 * of some 4-bit ECC register. ECC covers everything that
277 * was read; correct() just uses the hardware state, so
278 * ecc_code is not needed.
280 if (info->is_readmode) {
281 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
285 /* Pack eight raw 10-bit ecc values into ten bytes, making
286 * two passes which each convert four values (in upper and
287 * lower halves of two 32-bit words) into five bytes. The
288 * ROM boot loader uses this same packing scheme.
290 nand_davinci_readecc_4bit(info, raw_ecc);
291 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
292 *ecc_code++ = p[0] & 0xff;
293 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
294 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
295 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
296 *ecc_code++ = (p[1] >> 18) & 0xff;
302 /* Correct up to 4 bits in data we just read, using state left in the
303 * hardware plus the ecc_code computed when it was first written.
305 static int nand_davinci_correct_4bit(struct mtd_info *mtd,
306 u_char *data, u_char *ecc_code, u_char *null)
309 struct davinci_nand_info *info = to_davinci_nand(mtd);
310 unsigned short ecc10[8];
311 unsigned short *ecc16;
313 unsigned num_errors, corrected;
315 /* All bytes 0xff? It's an erased page; ignore its ECC. */
316 for (i = 0; i < 10; i++) {
317 if (ecc_code[i] != 0xff)
323 /* Unpack ten bytes into eight 10 bit values. We know we're
324 * little-endian, and use type punning for less shifting/masking.
326 if (WARN_ON(0x01 & (unsigned) ecc_code))
328 ecc16 = (unsigned short *)ecc_code;
330 ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
331 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
332 ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
333 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
334 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
335 ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
336 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
337 ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
339 /* Tell ECC controller about the expected ECC codes. */
340 for (i = 7; i >= 0; i--)
341 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
343 /* Allow time for syndrome calculation ... then read it.
344 * A syndrome of all zeroes 0 means no detected errors.
346 davinci_nand_readl(info, NANDFSR_OFFSET);
347 nand_davinci_readecc_4bit(info, syndrome);
348 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
351 /* Start address calculation, and wait for it to complete.
352 * We _could_ start reading more data while this is working,
353 * to speed up the overall page read.
355 davinci_nand_writel(info, NANDFCR_OFFSET,
356 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
358 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
360 switch ((fsr >> 8) & 0x0f) {
361 case 0: /* no error, should not happen */
363 case 1: /* five or more errors detected */
365 case 2: /* error addresses computed */
367 num_errors = 1 + ((fsr >> 16) & 0x03);
369 default: /* still working on it */
376 /* correct each error */
377 for (i = 0, corrected = 0; i < num_errors; i++) {
378 int error_address, error_value;
381 error_address = davinci_nand_readl(info,
382 NAND_ERR_ADD2_OFFSET);
383 error_value = davinci_nand_readl(info,
384 NAND_ERR_ERRVAL2_OFFSET);
386 error_address = davinci_nand_readl(info,
387 NAND_ERR_ADD1_OFFSET);
388 error_value = davinci_nand_readl(info,
389 NAND_ERR_ERRVAL1_OFFSET);
393 error_address >>= 16;
396 error_address &= 0x3ff;
397 error_address = (512 + 7) - error_address;
399 if (error_address < 512) {
400 data[error_address] ^= error_value;
408 /*----------------------------------------------------------------------*/
411 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
412 * how these chips are normally wired. This translates to both 8 and 16
413 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
415 * For now we assume that configuration, or any other one which ignores
416 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
417 * and have that transparently morphed into multiple NAND operations.
419 static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
421 struct nand_chip *chip = mtd->priv;
423 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
424 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
425 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
426 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
428 ioread8_rep(chip->IO_ADDR_R, buf, len);
431 static void nand_davinci_write_buf(struct mtd_info *mtd,
432 const uint8_t *buf, int len)
434 struct nand_chip *chip = mtd->priv;
436 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
437 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
438 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
439 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
441 iowrite8_rep(chip->IO_ADDR_R, buf, len);
445 * Check hardware register for wait status. Returns 1 if device is ready,
446 * 0 if it is still busy.
448 static int nand_davinci_dev_ready(struct mtd_info *mtd)
450 struct davinci_nand_info *info = to_davinci_nand(mtd);
452 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
455 static void __init nand_dm6446evm_flash_init(struct davinci_nand_info *info)
457 uint32_t regval, a1cr;
460 * NAND FLASH timings @ PLL1 == 459 MHz
461 * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz
462 * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
465 | (0 << 31) /* selectStrobe */
466 | (0 << 30) /* extWait (never with NAND) */
467 | (1 << 26) /* writeSetup 10 ns */
468 | (3 << 20) /* writeStrobe 40 ns */
469 | (1 << 17) /* writeHold 10 ns */
470 | (0 << 13) /* readSetup 10 ns */
471 | (3 << 7) /* readStrobe 60 ns */
472 | (0 << 4) /* readHold 10 ns */
473 | (3 << 2) /* turnAround ?? ns */
474 | (0 << 0) /* asyncSize 8-bit bus */
476 a1cr = davinci_nand_readl(info, A1CR_OFFSET);
477 if (a1cr != regval) {
478 dev_dbg(info->dev, "Warning: NAND config: Set A1CR " \
479 "reg to 0x%08x, was 0x%08x, should be done by " \
480 "bootloader.\n", regval, a1cr);
481 davinci_nand_writel(info, A1CR_OFFSET, regval);
485 /*----------------------------------------------------------------------*/
487 /* An ECC layout for using 4-bit ECC with small-page flash, storing
488 * ten ECC bytes plus the manufacturer's bad block marker byte, and
489 * and not overlapping the default BBT markers.
491 static struct nand_ecclayout hwecc4_small __initconst = {
493 .eccpos = { 0, 1, 2, 3, 4,
494 /* offset 5 holds the badblock marker */
498 {.offset = 8, .length = 5, },
504 static int __init nand_davinci_probe(struct platform_device *pdev)
506 struct davinci_nand_pdata *pdata = pdev->dev.platform_data;
507 struct davinci_nand_info *info;
508 struct resource *res1;
509 struct resource *res2;
514 nand_ecc_modes_t ecc_mode;
516 /* insist on board-specific configuration */
520 /* which external chipselect will we be managing? */
521 if (pdev->id < 0 || pdev->id > 3)
524 info = kzalloc(sizeof(*info), GFP_KERNEL);
526 dev_err(&pdev->dev, "unable to allocate memory\n");
531 platform_set_drvdata(pdev, info);
533 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
534 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
535 if (!res1 || !res2) {
536 dev_err(&pdev->dev, "resource missing\n");
541 vaddr = ioremap(res1->start, res1->end - res1->start);
542 base = ioremap(res2->start, res2->end - res2->start);
543 if (!vaddr || !base) {
544 dev_err(&pdev->dev, "ioremap failed\n");
549 info->dev = &pdev->dev;
553 info->mtd.priv = &info->chip;
554 info->mtd.name = dev_name(&pdev->dev);
555 info->mtd.owner = THIS_MODULE;
557 info->mtd.dev.parent = &pdev->dev;
559 info->chip.IO_ADDR_R = vaddr;
560 info->chip.IO_ADDR_W = vaddr;
561 info->chip.chip_delay = 0;
562 info->chip.select_chip = nand_davinci_select_chip;
564 /* options such as NAND_USE_FLASH_BBT or 16-bit widths */
565 info->chip.options = pdata->options;
567 info->ioaddr = (uint32_t __force) vaddr;
569 info->current_cs = info->ioaddr;
570 info->core_chipsel = pdev->id;
571 info->mask_chipsel = pdata->mask_chipsel;
573 /* use nandboot-capable ALE/CLE masks by default */
574 info->mask_ale = pdata->mask_cle ? : MASK_ALE;
575 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
577 /* Set address of hardware control function */
578 info->chip.cmd_ctrl = nand_davinci_hwcontrol;
579 info->chip.dev_ready = nand_davinci_dev_ready;
581 /* Speed up buffer I/O */
582 info->chip.read_buf = nand_davinci_read_buf;
583 info->chip.write_buf = nand_davinci_write_buf;
585 /* Use board-specific ECC config */
586 ecc_mode = pdata->ecc_mode;
595 if (pdata->ecc_bits == 4) {
596 /* No sanity checks: CPUs must support this,
597 * and the chips may not use NAND_BUSWIDTH_16.
600 /* No sharing 4-bit hardware between chipselects yet */
601 spin_lock_irq(&davinci_nand_lock);
606 spin_unlock_irq(&davinci_nand_lock);
611 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
612 info->chip.ecc.correct = nand_davinci_correct_4bit;
613 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
614 info->chip.ecc.bytes = 10;
616 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
617 info->chip.ecc.correct = nand_davinci_correct_1bit;
618 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
619 info->chip.ecc.bytes = 3;
621 info->chip.ecc.size = 512;
627 info->chip.ecc.mode = ecc_mode;
629 info->clk = clk_get(&pdev->dev, "AEMIFCLK");
630 if (IS_ERR(info->clk)) {
631 ret = PTR_ERR(info->clk);
632 dev_dbg(&pdev->dev, "unable to get AEMIFCLK, err %d\n", ret);
636 ret = clk_enable(info->clk);
638 dev_dbg(&pdev->dev, "unable to enable AEMIFCLK, err %d\n", ret);
642 /* EMIF timings should normally be set by the boot loader,
643 * especially after boot-from-NAND. The *only* reason to
644 * have this special casing for the DM6446 EVM is to work
645 * with boot-from-NOR ... with CS0 manually re-jumpered
646 * (after startup) so it addresses the NAND flash, not NOR.
647 * Even for dev boards, that's unusually rude...
649 if (machine_is_davinci_evm())
650 nand_dm6446evm_flash_init(info);
652 spin_lock_irq(&davinci_nand_lock);
654 /* put CSxNAND into NAND mode */
655 val = davinci_nand_readl(info, NANDFCR_OFFSET);
656 val |= BIT(info->core_chipsel);
657 davinci_nand_writel(info, NANDFCR_OFFSET, val);
659 spin_unlock_irq(&davinci_nand_lock);
661 /* Scan to find existence of the device(s) */
662 ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1);
664 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
668 /* Update ECC layout if needed ... for 1-bit HW ECC, the default
669 * is OK, but it allocates 6 bytes when only 3 are needed (for
670 * each 512 bytes). For the 4-bit HW ECC, that default is not
671 * usable: 10 bytes are needed, not 6.
673 if (pdata->ecc_bits == 4) {
674 int chunks = info->mtd.writesize / 512;
676 if (!chunks || info->mtd.oobsize < 16) {
677 dev_dbg(&pdev->dev, "too small\n");
682 /* For small page chips, preserve the manufacturer's
683 * badblock marking data ... and make sure a flash BBT
684 * table marker fits in the free bytes.
687 info->ecclayout = hwecc4_small;
688 info->ecclayout.oobfree[1].length =
689 info->mtd.oobsize - 16;
693 /* For large page chips we'll be wanting to use a
694 * not-yet-implemented mode that reads OOB data
695 * before reading the body of the page, to avoid
696 * the "infix OOB" model of NAND_ECC_HW_SYNDROME
697 * (and preserve manufacturer badblock markings).
699 dev_warn(&pdev->dev, "no 4-bit ECC support yet "
700 "for large page NAND\n");
705 info->chip.ecc.layout = &info->ecclayout;
708 ret = nand_scan_tail(&info->mtd);
712 if (mtd_has_partitions()) {
713 struct mtd_partition *mtd_parts = NULL;
714 int mtd_parts_nb = 0;
716 if (mtd_has_cmdlinepart()) {
717 static const char *probes[] __initconst =
718 { "cmdlinepart", NULL };
720 const char *master_name;
722 /* Set info->mtd.name = 0 temporarily */
723 master_name = info->mtd.name;
724 info->mtd.name = (char *)0;
726 /* info->mtd.name == 0, means: don't bother checking
728 mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
731 /* Restore info->mtd.name */
732 info->mtd.name = master_name;
735 if (mtd_parts_nb <= 0) {
736 mtd_parts = pdata->parts;
737 mtd_parts_nb = pdata->nr_parts;
740 /* Register any partitions */
741 if (mtd_parts_nb > 0) {
742 ret = add_mtd_partitions(&info->mtd,
743 mtd_parts, mtd_parts_nb);
745 info->partitioned = true;
748 } else if (pdata->nr_parts) {
749 dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
750 pdata->nr_parts, info->mtd.name);
753 /* If there's no partition info, just package the whole chip
754 * as a single MTD device.
756 if (!info->partitioned)
757 ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;
762 val = davinci_nand_readl(info, NRCSR_OFFSET);
763 dev_info(&pdev->dev, "controller rev. %d.%d\n",
764 (val >> 8) & 0xff, val & 0xff);
769 clk_disable(info->clk);
774 spin_lock_irq(&davinci_nand_lock);
775 if (ecc_mode == NAND_ECC_HW_SYNDROME)
777 spin_unlock_irq(&davinci_nand_lock);
792 static int __exit nand_davinci_remove(struct platform_device *pdev)
794 struct davinci_nand_info *info = platform_get_drvdata(pdev);
797 if (mtd_has_partitions() && info->partitioned)
798 status = del_mtd_partitions(&info->mtd);
800 status = del_mtd_device(&info->mtd);
802 spin_lock_irq(&davinci_nand_lock);
803 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
805 spin_unlock_irq(&davinci_nand_lock);
808 iounmap(info->vaddr);
810 nand_release(&info->mtd);
812 clk_disable(info->clk);
820 static struct platform_driver nand_davinci_driver = {
821 .remove = __exit_p(nand_davinci_remove),
823 .name = "davinci_nand",
826 MODULE_ALIAS("platform:davinci_nand");
828 static int __init nand_davinci_init(void)
830 return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
832 module_init(nand_davinci_init);
834 static void __exit nand_davinci_exit(void)
836 platform_driver_unregister(&nand_davinci_driver);
838 module_exit(nand_davinci_exit);
840 MODULE_LICENSE("GPL");
841 MODULE_AUTHOR("Texas Instruments");
842 MODULE_DESCRIPTION("Davinci NAND flash driver");